1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>
5 * Driver for Alcor Micro AU6601 and AU6621 controllers
8 /* Note: this driver was created without any documentation. Based
9 * on sniffing, testing and in some cases mimic of original driver.
10 * As soon as some one with documentation or more experience in SD/MMC, or
11 * reverse engineering then me, please review this driver and question every
12 * thing what I did. 2018 Oleksij Rempel <linux@rempel-privat.de>
15 #include <linux/delay.h>
16 #include <linux/pci.h>
17 #include <linux/module.h>
20 #include <linux/irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/mmc.h>
27 #include <linux/alcor_pci.h>
35 struct alcor_pll_conf {
36 unsigned int clk_src_freq;
37 unsigned int clk_src_reg;
42 struct alcor_sdmmc_host {
44 struct alcor_pci_priv *alcor_pci;
47 struct mmc_request *mrq;
48 struct mmc_command *cmd;
49 struct mmc_data *data;
50 unsigned int dma_on:1;
51 unsigned int early_data:1;
53 struct mutex cmd_mutex;
55 struct delayed_work timeout_work;
57 struct sg_mapping_iter sg_miter; /* SG state for PIO */
58 struct scatterlist *sg;
59 unsigned int blocks; /* remaining PIO blocks */
63 unsigned char cur_power_mode;
66 static const struct alcor_pll_conf alcor_pll_cfg[] = {
67 /* MHZ, CLK src, max div, min div */
68 { 31250000, AU6601_CLK_31_25_MHZ, 1, 511},
69 { 48000000, AU6601_CLK_48_MHZ, 1, 511},
70 {125000000, AU6601_CLK_125_MHZ, 1, 511},
71 {384000000, AU6601_CLK_384_MHZ, 1, 511},
74 static inline void alcor_rmw8(struct alcor_sdmmc_host *host, unsigned int addr,
77 struct alcor_pci_priv *priv = host->alcor_pci;
80 var = alcor_read8(priv, addr);
83 alcor_write8(priv, var, addr);
86 /* As soon as irqs are masked, some status updates may be missed.
89 static inline void alcor_mask_sd_irqs(struct alcor_sdmmc_host *host)
91 struct alcor_pci_priv *priv = host->alcor_pci;
93 alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
96 static inline void alcor_unmask_sd_irqs(struct alcor_sdmmc_host *host)
98 struct alcor_pci_priv *priv = host->alcor_pci;
100 alcor_write32(priv, AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK |
101 AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE |
102 AU6601_INT_OVER_CURRENT_ERR,
103 AU6601_REG_INT_ENABLE);
106 static void alcor_reset(struct alcor_sdmmc_host *host, u8 val)
108 struct alcor_pci_priv *priv = host->alcor_pci;
111 alcor_write8(priv, val | AU6601_BUF_CTRL_RESET,
112 AU6601_REG_SW_RESET);
113 for (i = 0; i < 100; i++) {
114 if (!(alcor_read8(priv, AU6601_REG_SW_RESET) & val))
118 dev_err(host->dev, "%s: timeout\n", __func__);
121 static void alcor_data_set_dma(struct alcor_sdmmc_host *host)
123 struct alcor_pci_priv *priv = host->alcor_pci;
130 dev_err(host->dev, "have blocks, but no SG\n");
134 if (!sg_dma_len(host->sg)) {
135 dev_err(host->dev, "DMA SG len == 0\n");
140 addr = (u32)sg_dma_address(host->sg);
142 alcor_write32(priv, addr, AU6601_REG_SDMA_ADDR);
143 host->sg = sg_next(host->sg);
147 static void alcor_trigger_data_transfer(struct alcor_sdmmc_host *host,
150 struct alcor_pci_priv *priv = host->alcor_pci;
151 struct mmc_data *data = host->data;
154 if (data->flags & MMC_DATA_WRITE)
155 ctrl |= AU6601_DATA_WRITE;
157 if (data->host_cookie == COOKIE_MAPPED) {
158 if (host->early_data) {
159 host->early_data = false;
163 host->early_data = early;
165 alcor_data_set_dma(host);
166 ctrl |= AU6601_DATA_DMA_MODE;
168 alcor_write32(priv, data->sg_count * 0x1000,
169 AU6601_REG_BLOCK_SIZE);
171 alcor_write32(priv, data->blksz, AU6601_REG_BLOCK_SIZE);
174 alcor_write8(priv, ctrl | AU6601_DATA_START_XFER,
175 AU6601_DATA_XFER_CTRL);
178 static void alcor_trf_block_pio(struct alcor_sdmmc_host *host, bool read)
180 struct alcor_pci_priv *priv = host->alcor_pci;
188 dev_err(host->dev, "configured DMA but got PIO request.\n");
192 if (!!(host->data->flags & MMC_DATA_READ) != read) {
193 dev_err(host->dev, "got unexpected direction %i != %i\n",
194 !!(host->data->flags & MMC_DATA_READ), read);
197 if (!sg_miter_next(&host->sg_miter))
200 blksize = host->data->blksz;
201 len = min(host->sg_miter.length, blksize);
203 dev_dbg(host->dev, "PIO, %s block size: 0x%zx\n",
204 read ? "read" : "write", blksize);
206 host->sg_miter.consumed = len;
209 buf = host->sg_miter.addr;
212 ioread32_rep(priv->iobase + AU6601_REG_BUFFER, buf, len >> 2);
214 iowrite32_rep(priv->iobase + AU6601_REG_BUFFER, buf, len >> 2);
216 sg_miter_stop(&host->sg_miter);
219 static void alcor_prepare_sg_miter(struct alcor_sdmmc_host *host)
221 unsigned int flags = SG_MITER_ATOMIC;
222 struct mmc_data *data = host->data;
224 if (data->flags & MMC_DATA_READ)
225 flags |= SG_MITER_TO_SG;
227 flags |= SG_MITER_FROM_SG;
228 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
231 static void alcor_prepare_data(struct alcor_sdmmc_host *host,
232 struct mmc_command *cmd)
234 struct mmc_data *data = cmd->data;
241 host->data->bytes_xfered = 0;
242 host->blocks = data->blocks;
244 host->sg_count = data->sg_count;
245 dev_dbg(host->dev, "prepare DATA: sg %i, blocks: %i\n",
246 host->sg_count, host->blocks);
248 if (data->host_cookie != COOKIE_MAPPED)
249 alcor_prepare_sg_miter(host);
251 alcor_trigger_data_transfer(host, true);
254 static void alcor_send_cmd(struct alcor_sdmmc_host *host,
255 struct mmc_command *cmd, bool set_timeout)
257 struct alcor_pci_priv *priv = host->alcor_pci;
258 unsigned long timeout = 0;
262 alcor_prepare_data(host, cmd);
264 dev_dbg(host->dev, "send CMD. opcode: 0x%02x, arg; 0x%08x\n",
265 cmd->opcode, cmd->arg);
266 alcor_write8(priv, cmd->opcode | 0x40, AU6601_REG_CMD_OPCODE);
267 alcor_write32be(priv, cmd->arg, AU6601_REG_CMD_ARG);
269 switch (mmc_resp_type(cmd)) {
271 ctrl = AU6601_CMD_NO_RESP;
274 ctrl = AU6601_CMD_6_BYTE_CRC;
277 ctrl = AU6601_CMD_6_BYTE_CRC | AU6601_CMD_STOP_WAIT_RDY;
280 ctrl = AU6601_CMD_17_BYTE_CRC;
283 ctrl = AU6601_CMD_6_BYTE_WO_CRC;
286 dev_err(host->dev, "%s: cmd->flag (0x%02x) is not valid\n",
287 mmc_hostname(host->mmc), mmc_resp_type(cmd));
292 if (!cmd->data && cmd->busy_timeout)
293 timeout = cmd->busy_timeout;
297 schedule_delayed_work(&host->timeout_work,
298 msecs_to_jiffies(timeout));
301 dev_dbg(host->dev, "xfer ctrl: 0x%02x; timeout: %lu\n", ctrl, timeout);
302 alcor_write8(priv, ctrl | AU6601_CMD_START_XFER,
303 AU6601_CMD_XFER_CTRL);
306 static void alcor_request_complete(struct alcor_sdmmc_host *host,
309 struct mmc_request *mrq;
312 * If this work gets rescheduled while running, it will
313 * be run again afterwards but without any active request.
319 cancel_delayed_work(&host->timeout_work);
328 mmc_request_done(host->mmc, mrq);
331 static void alcor_finish_data(struct alcor_sdmmc_host *host)
333 struct mmc_data *data;
340 * The specification states that the block count register must
341 * be updated, but it does not specify at what point in the
342 * data flow. That makes the register entirely useless to read
343 * back so we have to assume that nothing made it to the card
344 * in the event of an error.
347 data->bytes_xfered = 0;
349 data->bytes_xfered = data->blksz * data->blocks;
352 * Need to send CMD12 if -
353 * a) open-ended multiblock transfer (no CMD23)
354 * b) error in multiblock transfer
361 * The controller needs a reset of internal state machines
362 * upon error conditions.
365 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
367 alcor_unmask_sd_irqs(host);
368 alcor_send_cmd(host, data->stop, false);
372 alcor_request_complete(host, 1);
375 static void alcor_err_irq(struct alcor_sdmmc_host *host, u32 intmask)
377 dev_dbg(host->dev, "ERR IRQ %x\n", intmask);
380 if (intmask & AU6601_INT_CMD_TIMEOUT_ERR)
381 host->cmd->error = -ETIMEDOUT;
383 host->cmd->error = -EILSEQ;
387 if (intmask & AU6601_INT_DATA_TIMEOUT_ERR)
388 host->data->error = -ETIMEDOUT;
390 host->data->error = -EILSEQ;
392 host->data->bytes_xfered = 0;
395 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
396 alcor_request_complete(host, 1);
399 static int alcor_cmd_irq_done(struct alcor_sdmmc_host *host, u32 intmask)
401 struct alcor_pci_priv *priv = host->alcor_pci;
403 intmask &= AU6601_INT_CMD_END;
408 /* got CMD_END but no CMD is in progress, wake thread an process the
414 if (host->cmd->flags & MMC_RSP_PRESENT) {
415 struct mmc_command *cmd = host->cmd;
417 cmd->resp[0] = alcor_read32be(priv, AU6601_REG_CMD_RSP0);
418 dev_dbg(host->dev, "RSP0: 0x%04x\n", cmd->resp[0]);
419 if (host->cmd->flags & MMC_RSP_136) {
421 alcor_read32be(priv, AU6601_REG_CMD_RSP1);
423 alcor_read32be(priv, AU6601_REG_CMD_RSP2);
425 alcor_read32be(priv, AU6601_REG_CMD_RSP3);
426 dev_dbg(host->dev, "RSP1,2,3: 0x%04x 0x%04x 0x%04x\n",
427 cmd->resp[1], cmd->resp[2], cmd->resp[3]);
432 host->cmd->error = 0;
434 /* Processed actual command. */
438 alcor_trigger_data_transfer(host, false);
443 static void alcor_cmd_irq_thread(struct alcor_sdmmc_host *host, u32 intmask)
445 intmask &= AU6601_INT_CMD_END;
450 if (!host->cmd && intmask & AU6601_INT_CMD_END) {
451 dev_dbg(host->dev, "Got command interrupt 0x%08x even though no command operation was in progress.\n",
455 /* Processed actual command. */
457 alcor_request_complete(host, 1);
459 alcor_trigger_data_transfer(host, false);
463 static int alcor_data_irq_done(struct alcor_sdmmc_host *host, u32 intmask)
467 intmask &= AU6601_INT_DATA_MASK;
469 /* nothing here to do */
473 /* we was too fast and got DATA_END after it was processed?
474 * lets ignore it for now.
476 if (!host->data && intmask == AU6601_INT_DATA_END)
479 /* looks like an error, so lets handle it. */
483 tmp = intmask & (AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY
484 | AU6601_INT_DMA_END);
488 case AU6601_INT_READ_BUF_RDY:
489 alcor_trf_block_pio(host, true);
492 alcor_trigger_data_transfer(host, false);
494 case AU6601_INT_WRITE_BUF_RDY:
495 alcor_trf_block_pio(host, false);
498 alcor_trigger_data_transfer(host, false);
500 case AU6601_INT_DMA_END:
504 alcor_data_set_dma(host);
507 dev_err(host->dev, "Got READ_BUF_RDY and WRITE_BUF_RDY at same time\n");
511 if (intmask & AU6601_INT_DATA_END)
517 static void alcor_data_irq_thread(struct alcor_sdmmc_host *host, u32 intmask)
519 intmask &= AU6601_INT_DATA_MASK;
525 dev_dbg(host->dev, "Got data interrupt 0x%08x even though no data operation was in progress.\n",
527 alcor_reset(host, AU6601_RESET_DATA);
531 if (alcor_data_irq_done(host, intmask))
534 if ((intmask & AU6601_INT_DATA_END) || !host->blocks ||
535 (host->dma_on && !host->sg_count))
536 alcor_finish_data(host);
539 static void alcor_cd_irq(struct alcor_sdmmc_host *host, u32 intmask)
541 dev_dbg(host->dev, "card %s\n",
542 intmask & AU6601_INT_CARD_REMOVE ? "removed" : "inserted");
545 dev_dbg(host->dev, "cancel all pending tasks.\n");
548 host->data->error = -ENOMEDIUM;
551 host->cmd->error = -ENOMEDIUM;
553 host->mrq->cmd->error = -ENOMEDIUM;
555 alcor_request_complete(host, 1);
558 mmc_detect_change(host->mmc, msecs_to_jiffies(1));
561 static irqreturn_t alcor_irq_thread(int irq, void *d)
563 struct alcor_sdmmc_host *host = d;
564 irqreturn_t ret = IRQ_HANDLED;
567 mutex_lock(&host->cmd_mutex);
569 intmask = host->irq_status_sd;
572 if (unlikely(!intmask || AU6601_INT_ALL_MASK == intmask)) {
573 dev_dbg(host->dev, "unexpected IRQ: 0x%04x\n", intmask);
578 tmp = intmask & (AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK);
580 if (tmp & AU6601_INT_ERROR_MASK)
581 alcor_err_irq(host, tmp);
583 alcor_cmd_irq_thread(host, tmp);
584 alcor_data_irq_thread(host, tmp);
586 intmask &= ~(AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK);
589 if (intmask & (AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE)) {
590 alcor_cd_irq(host, intmask);
591 intmask &= ~(AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE);
594 if (intmask & AU6601_INT_OVER_CURRENT_ERR) {
596 "warning: over current detected!\n");
597 intmask &= ~AU6601_INT_OVER_CURRENT_ERR;
601 dev_dbg(host->dev, "got not handled IRQ: 0x%04x\n", intmask);
604 mutex_unlock(&host->cmd_mutex);
605 alcor_unmask_sd_irqs(host);
610 static irqreturn_t alcor_irq(int irq, void *d)
612 struct alcor_sdmmc_host *host = d;
613 struct alcor_pci_priv *priv = host->alcor_pci;
616 int cmd_done, data_done;
618 status = alcor_read32(priv, AU6601_REG_INT_STATUS);
622 alcor_write32(priv, status, AU6601_REG_INT_STATUS);
624 tmp = status & (AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY
625 | AU6601_INT_DATA_END | AU6601_INT_DMA_END
626 | AU6601_INT_CMD_END);
628 cmd_done = alcor_cmd_irq_done(host, tmp);
629 data_done = alcor_data_irq_done(host, tmp);
630 /* use fast path for simple tasks */
631 if (cmd_done && data_done) {
637 host->irq_status_sd = status;
638 ret = IRQ_WAKE_THREAD;
639 alcor_mask_sd_irqs(host);
644 static void alcor_set_clock(struct alcor_sdmmc_host *host, unsigned int clock)
646 struct alcor_pci_priv *priv = host->alcor_pci;
647 int i, diff = 0x7fffffff, tmp_clock = 0;
652 alcor_write16(priv, 0, AU6601_CLK_SELECT);
656 for (i = 0; i < ARRAY_SIZE(alcor_pll_cfg); i++) {
657 unsigned int tmp_div, tmp_diff;
658 const struct alcor_pll_conf *cfg = &alcor_pll_cfg[i];
660 tmp_div = DIV_ROUND_UP(cfg->clk_src_freq, clock);
661 if (cfg->min_div > tmp_div || tmp_div > cfg->max_div)
664 tmp_clock = DIV_ROUND_UP(cfg->clk_src_freq, tmp_div);
665 tmp_diff = abs(clock - tmp_clock);
667 if (tmp_diff >= 0 && tmp_diff < diff) {
669 clk_src = cfg->clk_src_reg;
674 clk_src |= ((clk_div - 1) << 8);
675 clk_src |= AU6601_CLK_ENABLE;
677 dev_dbg(host->dev, "set freq %d cal freq %d, use div %d, mod %x\n",
678 clock, tmp_clock, clk_div, clk_src);
680 alcor_write16(priv, clk_src, AU6601_CLK_SELECT);
684 static void alcor_set_timing(struct mmc_host *mmc, struct mmc_ios *ios)
686 struct alcor_sdmmc_host *host = mmc_priv(mmc);
688 if (ios->timing == MMC_TIMING_LEGACY) {
689 alcor_rmw8(host, AU6601_CLK_DELAY,
690 AU6601_CLK_POSITIVE_EDGE_ALL, 0);
692 alcor_rmw8(host, AU6601_CLK_DELAY,
693 0, AU6601_CLK_POSITIVE_EDGE_ALL);
697 static void alcor_set_bus_width(struct mmc_host *mmc, struct mmc_ios *ios)
699 struct alcor_sdmmc_host *host = mmc_priv(mmc);
700 struct alcor_pci_priv *priv = host->alcor_pci;
702 if (ios->bus_width == MMC_BUS_WIDTH_1) {
703 alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
704 } else if (ios->bus_width == MMC_BUS_WIDTH_4) {
705 alcor_write8(priv, AU6601_BUS_WIDTH_4BIT,
706 AU6601_REG_BUS_CTRL);
708 dev_err(host->dev, "Unknown BUS mode\n");
712 static int alcor_card_busy(struct mmc_host *mmc)
714 struct alcor_sdmmc_host *host = mmc_priv(mmc);
715 struct alcor_pci_priv *priv = host->alcor_pci;
718 /* Check whether dat[0:3] low */
719 status = alcor_read8(priv, AU6601_DATA_PIN_STATE);
721 return !(status & AU6601_BUS_STAT_DAT_MASK);
724 static int alcor_get_cd(struct mmc_host *mmc)
726 struct alcor_sdmmc_host *host = mmc_priv(mmc);
727 struct alcor_pci_priv *priv = host->alcor_pci;
730 detect = alcor_read8(priv, AU6601_DETECT_STATUS)
731 & AU6601_DETECT_STATUS_M;
732 /* check if card is present then send command and data */
733 return (detect == AU6601_SD_DETECTED);
736 static int alcor_get_ro(struct mmc_host *mmc)
738 struct alcor_sdmmc_host *host = mmc_priv(mmc);
739 struct alcor_pci_priv *priv = host->alcor_pci;
742 /* get write protect pin status */
743 status = alcor_read8(priv, AU6601_INTERFACE_MODE_CTRL);
745 return !!(status & AU6601_SD_CARD_WP);
748 static void alcor_request(struct mmc_host *mmc, struct mmc_request *mrq)
750 struct alcor_sdmmc_host *host = mmc_priv(mmc);
752 mutex_lock(&host->cmd_mutex);
756 /* check if card is present then send command and data */
757 if (alcor_get_cd(mmc))
758 alcor_send_cmd(host, mrq->cmd, true);
760 mrq->cmd->error = -ENOMEDIUM;
761 alcor_request_complete(host, 1);
764 mutex_unlock(&host->cmd_mutex);
767 static void alcor_pre_req(struct mmc_host *mmc,
768 struct mmc_request *mrq)
770 struct alcor_sdmmc_host *host = mmc_priv(mmc);
771 struct mmc_data *data = mrq->data;
772 struct mmc_command *cmd = mrq->cmd;
773 struct scatterlist *sg;
774 unsigned int i, sg_len;
779 data->host_cookie = COOKIE_UNMAPPED;
781 /* FIXME: looks like the DMA engine works only with CMD18 */
782 if (cmd->opcode != 18)
785 * We don't do DMA on "complex" transfers, i.e. with
786 * non-word-aligned buffers or lengths. Also, we don't bother
787 * with all the DMA setup overhead for short transfers.
789 if (data->blocks * data->blksz < AU6601_MAX_DMA_BLOCK_SIZE)
795 for_each_sg(data->sg, sg, data->sg_len, i) {
796 if (sg->length != AU6601_MAX_DMA_BLOCK_SIZE)
800 /* This data might be unmapped at this time */
802 sg_len = dma_map_sg(host->dev, data->sg, data->sg_len,
803 mmc_get_dma_dir(data));
805 data->host_cookie = COOKIE_MAPPED;
807 data->sg_count = sg_len;
810 static void alcor_post_req(struct mmc_host *mmc,
811 struct mmc_request *mrq,
814 struct alcor_sdmmc_host *host = mmc_priv(mmc);
815 struct mmc_data *data = mrq->data;
820 if (data->host_cookie == COOKIE_MAPPED) {
821 dma_unmap_sg(host->dev,
824 mmc_get_dma_dir(data));
827 data->host_cookie = COOKIE_UNMAPPED;
830 static void alcor_set_power_mode(struct mmc_host *mmc, struct mmc_ios *ios)
832 struct alcor_sdmmc_host *host = mmc_priv(mmc);
833 struct alcor_pci_priv *priv = host->alcor_pci;
835 switch (ios->power_mode) {
837 alcor_set_clock(host, ios->clock);
838 /* set all pins to input */
839 alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
841 alcor_write8(priv, 0, AU6601_POWER_CONTROL);
846 /* This is most trickiest part. The order and timings of
847 * instructions seems to play important role. Any changes may
848 * confuse internal state engine if this HW.
849 * FIXME: If we will ever get access to documentation, then this
850 * part should be reviewed again.
853 /* enable SD card mode */
854 alcor_write8(priv, AU6601_SD_CARD,
856 /* set signal voltage to 3.3V */
857 alcor_write8(priv, 0, AU6601_OPT);
858 /* no documentation about clk delay, for now just try to mimic
861 alcor_write8(priv, 0x20, AU6601_CLK_DELAY);
862 /* set BUS width to 1 bit */
863 alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
864 /* set CLK first time */
865 alcor_set_clock(host, ios->clock);
867 alcor_write8(priv, AU6601_SD_CARD,
868 AU6601_POWER_CONTROL);
869 /* wait until the CLK will get stable */
871 /* set CLK again, mimic original driver. */
872 alcor_set_clock(host, ios->clock);
875 alcor_write8(priv, AU6601_SD_CARD,
876 AU6601_OUTPUT_ENABLE);
877 /* The clk will not work on au6621. We need to trigger data
880 alcor_write8(priv, AU6601_DATA_WRITE,
881 AU6601_DATA_XFER_CTRL);
882 /* configure timeout. Not clear what exactly it means. */
883 alcor_write8(priv, 0x7d, AU6601_TIME_OUT_CTRL);
887 dev_err(host->dev, "Unknown power parameter\n");
891 static void alcor_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
893 struct alcor_sdmmc_host *host = mmc_priv(mmc);
895 mutex_lock(&host->cmd_mutex);
897 dev_dbg(host->dev, "set ios. bus width: %x, power mode: %x\n",
898 ios->bus_width, ios->power_mode);
900 if (ios->power_mode != host->cur_power_mode) {
901 alcor_set_power_mode(mmc, ios);
902 host->cur_power_mode = ios->power_mode;
904 alcor_set_timing(mmc, ios);
905 alcor_set_bus_width(mmc, ios);
906 alcor_set_clock(host, ios->clock);
909 mutex_unlock(&host->cmd_mutex);
912 static int alcor_signal_voltage_switch(struct mmc_host *mmc,
915 struct alcor_sdmmc_host *host = mmc_priv(mmc);
917 mutex_lock(&host->cmd_mutex);
919 switch (ios->signal_voltage) {
920 case MMC_SIGNAL_VOLTAGE_330:
921 alcor_rmw8(host, AU6601_OPT, AU6601_OPT_SD_18V, 0);
923 case MMC_SIGNAL_VOLTAGE_180:
924 alcor_rmw8(host, AU6601_OPT, 0, AU6601_OPT_SD_18V);
927 /* No signal voltage switch required */
931 mutex_unlock(&host->cmd_mutex);
935 static const struct mmc_host_ops alcor_sdc_ops = {
936 .card_busy = alcor_card_busy,
937 .get_cd = alcor_get_cd,
938 .get_ro = alcor_get_ro,
939 .post_req = alcor_post_req,
940 .pre_req = alcor_pre_req,
941 .request = alcor_request,
942 .set_ios = alcor_set_ios,
943 .start_signal_voltage_switch = alcor_signal_voltage_switch,
946 static void alcor_timeout_timer(struct work_struct *work)
948 struct delayed_work *d = to_delayed_work(work);
949 struct alcor_sdmmc_host *host = container_of(d, struct alcor_sdmmc_host,
951 mutex_lock(&host->cmd_mutex);
953 dev_dbg(host->dev, "triggered timeout\n");
955 dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
958 host->data->error = -ETIMEDOUT;
961 host->cmd->error = -ETIMEDOUT;
963 host->mrq->cmd->error = -ETIMEDOUT;
966 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
967 alcor_request_complete(host, 0);
971 mutex_unlock(&host->cmd_mutex);
974 static void alcor_hw_init(struct alcor_sdmmc_host *host)
976 struct alcor_pci_priv *priv = host->alcor_pci;
977 struct alcor_dev_cfg *cfg = priv->cfg;
979 /* FIXME: This part is a mimics HW init of original driver.
980 * If we will ever get access to documentation, then this part
981 * should be reviewed again.
984 /* reset command state engine */
985 alcor_reset(host, AU6601_RESET_CMD);
987 alcor_write8(priv, 0, AU6601_DMA_BOUNDARY);
988 /* enable sd card mode */
989 alcor_write8(priv, AU6601_SD_CARD, AU6601_ACTIVE_CTRL);
991 /* set BUS width to 1 bit */
992 alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
994 /* reset data state engine */
995 alcor_reset(host, AU6601_RESET_DATA);
996 /* Not sure if a voodoo with AU6601_DMA_BOUNDARY is really needed */
997 alcor_write8(priv, 0, AU6601_DMA_BOUNDARY);
999 alcor_write8(priv, 0, AU6601_INTERFACE_MODE_CTRL);
1000 /* not clear what we are doing here. */
1001 alcor_write8(priv, 0x44, AU6601_PAD_DRIVE0);
1002 alcor_write8(priv, 0x44, AU6601_PAD_DRIVE1);
1003 alcor_write8(priv, 0x00, AU6601_PAD_DRIVE2);
1005 /* for 6601 - dma_boundary; for 6621 - dma_page_cnt
1006 * exact meaning of this register is not clear.
1008 alcor_write8(priv, cfg->dma, AU6601_DMA_BOUNDARY);
1010 /* make sure all pins are set to input and VDD is off */
1011 alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
1012 alcor_write8(priv, 0, AU6601_POWER_CONTROL);
1014 alcor_write8(priv, AU6601_DETECT_EN, AU6601_DETECT_STATUS);
1015 /* now we should be safe to enable IRQs */
1016 alcor_unmask_sd_irqs(host);
1019 static void alcor_hw_uninit(struct alcor_sdmmc_host *host)
1021 struct alcor_pci_priv *priv = host->alcor_pci;
1023 alcor_mask_sd_irqs(host);
1024 alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
1026 alcor_write8(priv, 0, AU6601_DETECT_STATUS);
1028 alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
1029 alcor_write8(priv, 0, AU6601_POWER_CONTROL);
1031 alcor_write8(priv, 0, AU6601_OPT);
1034 static void alcor_init_mmc(struct alcor_sdmmc_host *host)
1036 struct mmc_host *mmc = host->mmc;
1038 mmc->f_min = AU6601_MIN_CLOCK;
1039 mmc->f_max = AU6601_MAX_CLOCK;
1040 mmc->ocr_avail = MMC_VDD_33_34;
1041 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED
1042 | MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
1043 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50;
1044 mmc->caps2 = MMC_CAP2_NO_SDIO;
1045 mmc->ops = &alcor_sdc_ops;
1047 /* The hardware does DMA data transfer of 4096 bytes to/from a single
1048 * buffer address. Scatterlists are not supported, but upon DMA
1049 * completion (signalled via IRQ), the original vendor driver does
1050 * then immediately set up another DMA transfer of the next 4096
1053 * This means that we need to handle the I/O in 4096 byte chunks.
1054 * Lacking a way to limit the sglist entries to 4096 bytes, we instead
1055 * impose that only one segment is provided, with maximum size 4096,
1056 * which also happens to be the minimum size. This means that the
1057 * single-entry sglist handled by this driver can be handed directly
1058 * to the hardware, nice and simple.
1060 * Unfortunately though, that means we only do 4096 bytes I/O per
1061 * MMC command. A future improvement would be to make the driver
1062 * accept sg lists and entries of any size, and simply iterate
1063 * through them 4096 bytes at a time.
1065 mmc->max_segs = AU6601_MAX_DMA_SEGMENTS;
1066 mmc->max_seg_size = AU6601_MAX_DMA_BLOCK_SIZE;
1067 mmc->max_req_size = mmc->max_seg_size;
1070 static int alcor_pci_sdmmc_drv_probe(struct platform_device *pdev)
1072 struct alcor_pci_priv *priv = pdev->dev.platform_data;
1073 struct mmc_host *mmc;
1074 struct alcor_sdmmc_host *host;
1077 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1079 dev_err(&pdev->dev, "Can't allocate MMC\n");
1083 host = mmc_priv(mmc);
1085 host->dev = &pdev->dev;
1086 host->cur_power_mode = MMC_POWER_UNDEFINED;
1087 host->alcor_pci = priv;
1089 /* make sure irqs are disabled */
1090 alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
1091 alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
1093 ret = devm_request_threaded_irq(&pdev->dev, priv->irq,
1094 alcor_irq, alcor_irq_thread, IRQF_SHARED,
1095 DRV_NAME_ALCOR_PCI_SDMMC, host);
1098 dev_err(&pdev->dev, "Failed to get irq for data line\n");
1102 mutex_init(&host->cmd_mutex);
1103 INIT_DELAYED_WORK(&host->timeout_work, alcor_timeout_timer);
1105 alcor_init_mmc(host);
1106 alcor_hw_init(host);
1108 dev_set_drvdata(&pdev->dev, host);
1113 static int alcor_pci_sdmmc_drv_remove(struct platform_device *pdev)
1115 struct alcor_sdmmc_host *host = dev_get_drvdata(&pdev->dev);
1117 if (cancel_delayed_work_sync(&host->timeout_work))
1118 alcor_request_complete(host, 0);
1120 alcor_hw_uninit(host);
1121 mmc_remove_host(host->mmc);
1122 mmc_free_host(host->mmc);
1127 #ifdef CONFIG_PM_SLEEP
1128 static int alcor_pci_sdmmc_suspend(struct device *dev)
1130 struct alcor_sdmmc_host *host = dev_get_drvdata(dev);
1132 if (cancel_delayed_work_sync(&host->timeout_work))
1133 alcor_request_complete(host, 0);
1135 alcor_hw_uninit(host);
1140 static int alcor_pci_sdmmc_resume(struct device *dev)
1142 struct alcor_sdmmc_host *host = dev_get_drvdata(dev);
1144 alcor_hw_init(host);
1148 #endif /* CONFIG_PM_SLEEP */
1150 static SIMPLE_DEV_PM_OPS(alcor_mmc_pm_ops, alcor_pci_sdmmc_suspend,
1151 alcor_pci_sdmmc_resume);
1153 static const struct platform_device_id alcor_pci_sdmmc_ids[] = {
1155 .name = DRV_NAME_ALCOR_PCI_SDMMC,
1160 MODULE_DEVICE_TABLE(platform, alcor_pci_sdmmc_ids);
1162 static struct platform_driver alcor_pci_sdmmc_driver = {
1163 .probe = alcor_pci_sdmmc_drv_probe,
1164 .remove = alcor_pci_sdmmc_drv_remove,
1165 .id_table = alcor_pci_sdmmc_ids,
1167 .name = DRV_NAME_ALCOR_PCI_SDMMC,
1168 .pm = &alcor_mmc_pm_ops
1171 module_platform_driver(alcor_pci_sdmmc_driver);
1173 MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>");
1174 MODULE_DESCRIPTION("PCI driver for Alcor Micro AU6601 Secure Digital Host Controller Interface");
1175 MODULE_LICENSE("GPL");