drivers/mmc/host/atmel-mci.c

   1 /*
   2  * Atmel MultiMedia Card Interface driver
   3  *
   4  * Copyright (C) 2004-2008 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/blkdev.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/device.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/ioport.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <linux/stat.h>
  31 #include <linux/types.h>
  32
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/sdio.h>
  35
  36 #include <linux/atmel-mci.h>
  37 #include <linux/atmel_pdc.h>
  38 #include <linux/pm.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/pinctrl/consumer.h>
  41
  42 #include <asm/cacheflush.h>
  43 #include <asm/io.h>
  44 #include <asm/unaligned.h>
  45
  46 /*
  47  * Superset of MCI IP registers integrated in Atmel AT91 Processor
  48  * Registers and bitfields marked with [2] are only available in MCI2
  49  */
  50
  51 /* MCI Register Definitions */
  52 #define ATMCI_CR                        0x0000  /* Control */
  53 #define         ATMCI_CR_MCIEN                  BIT(0)          /* MCI Enable */
  54 #define         ATMCI_CR_MCIDIS                 BIT(1)          /* MCI Disable */
  55 #define         ATMCI_CR_PWSEN                  BIT(2)          /* Power Save Enable */
  56 #define         ATMCI_CR_PWSDIS                 BIT(3)          /* Power Save Disable */
  57 #define         ATMCI_CR_SWRST                  BIT(7)          /* Software Reset */
  58 #define ATMCI_MR                        0x0004  /* Mode */
  59 #define         ATMCI_MR_CLKDIV(x)              ((x) <<  0)     /* Clock Divider */
  60 #define         ATMCI_MR_PWSDIV(x)              ((x) <<  8)     /* Power Saving Divider */
  61 #define         ATMCI_MR_RDPROOF                BIT(11)         /* Read Proof */
  62 #define         ATMCI_MR_WRPROOF                BIT(12)         /* Write Proof */
  63 #define         ATMCI_MR_PDCFBYTE               BIT(13)         /* Force Byte Transfer */
  64 #define         ATMCI_MR_PDCPADV                BIT(14)         /* Padding Value */
  65 #define         ATMCI_MR_PDCMODE                BIT(15)         /* PDC-oriented Mode */
  66 #define         ATMCI_MR_CLKODD(x)              ((x) << 16)     /* LSB of Clock Divider */
  67 #define ATMCI_DTOR                      0x0008  /* Data Timeout */
  68 #define         ATMCI_DTOCYC(x)                 ((x) <<  0)     /* Data Timeout Cycles */
  69 #define         ATMCI_DTOMUL(x)                 ((x) <<  4)     /* Data Timeout Multiplier */
  70 #define ATMCI_SDCR                      0x000c  /* SD Card / SDIO */
  71 #define         ATMCI_SDCSEL_SLOT_A             (0 <<  0)       /* Select SD slot A */
  72 #define         ATMCI_SDCSEL_SLOT_B             (1 <<  0)       /* Select SD slot A */
  73 #define         ATMCI_SDCSEL_MASK               (3 <<  0)
  74 #define         ATMCI_SDCBUS_1BIT               (0 <<  6)       /* 1-bit data bus */
  75 #define         ATMCI_SDCBUS_4BIT               (2 <<  6)       /* 4-bit data bus */
  76 #define         ATMCI_SDCBUS_8BIT               (3 <<  6)       /* 8-bit data bus[2] */
  77 #define         ATMCI_SDCBUS_MASK               (3 <<  6)
  78 #define ATMCI_ARGR                      0x0010  /* Command Argument */
  79 #define ATMCI_CMDR                      0x0014  /* Command */
  80 #define         ATMCI_CMDR_CMDNB(x)             ((x) <<  0)     /* Command Opcode */
  81 #define         ATMCI_CMDR_RSPTYP_NONE          (0 <<  6)       /* No response */
  82 #define         ATMCI_CMDR_RSPTYP_48BIT         (1 <<  6)       /* 48-bit response */
  83 #define         ATMCI_CMDR_RSPTYP_136BIT        (2 <<  6)       /* 136-bit response */
  84 #define         ATMCI_CMDR_SPCMD_INIT           (1 <<  8)       /* Initialization command */
  85 #define         ATMCI_CMDR_SPCMD_SYNC           (2 <<  8)       /* Synchronized command */
  86 #define         ATMCI_CMDR_SPCMD_INT            (4 <<  8)       /* Interrupt command */
  87 #define         ATMCI_CMDR_SPCMD_INTRESP        (5 <<  8)       /* Interrupt response */
  88 #define         ATMCI_CMDR_OPDCMD               (1 << 11)       /* Open Drain */
  89 #define         ATMCI_CMDR_MAXLAT_5CYC          (0 << 12)       /* Max latency 5 cycles */
  90 #define         ATMCI_CMDR_MAXLAT_64CYC         (1 << 12)       /* Max latency 64 cycles */
  91 #define         ATMCI_CMDR_START_XFER           (1 << 16)       /* Start data transfer */
  92 #define         ATMCI_CMDR_STOP_XFER            (2 << 16)       /* Stop data transfer */
  93 #define         ATMCI_CMDR_TRDIR_WRITE          (0 << 18)       /* Write data */
  94 #define         ATMCI_CMDR_TRDIR_READ           (1 << 18)       /* Read data */
  95 #define         ATMCI_CMDR_BLOCK                (0 << 19)       /* Single-block transfer */
  96 #define         ATMCI_CMDR_MULTI_BLOCK          (1 << 19)       /* Multi-block transfer */
  97 #define         ATMCI_CMDR_STREAM               (2 << 19)       /* MMC Stream transfer */
  98 #define         ATMCI_CMDR_SDIO_BYTE            (4 << 19)       /* SDIO Byte transfer */
  99 #define         ATMCI_CMDR_SDIO_BLOCK           (5 << 19)       /* SDIO Block transfer */
 100 #define         ATMCI_CMDR_SDIO_SUSPEND         (1 << 24)       /* SDIO Suspend Command */
 101 #define         ATMCI_CMDR_SDIO_RESUME          (2 << 24)       /* SDIO Resume Command */
 102 #define ATMCI_BLKR                      0x0018  /* Block */
 103 #define         ATMCI_BCNT(x)                   ((x) <<  0)     /* Data Block Count */
 104 #define         ATMCI_BLKLEN(x)                 ((x) << 16)     /* Data Block Length */
 105 #define ATMCI_CSTOR                     0x001c  /* Completion Signal Timeout[2] */
 106 #define         ATMCI_CSTOCYC(x)                ((x) <<  0)     /* CST cycles */
 107 #define         ATMCI_CSTOMUL(x)                ((x) <<  4)     /* CST multiplier */
 108 #define ATMCI_RSPR                      0x0020  /* Response 0 */
 109 #define ATMCI_RSPR1                     0x0024  /* Response 1 */
 110 #define ATMCI_RSPR2                     0x0028  /* Response 2 */
 111 #define ATMCI_RSPR3                     0x002c  /* Response 3 */
 112 #define ATMCI_RDR                       0x0030  /* Receive Data */
 113 #define ATMCI_TDR                       0x0034  /* Transmit Data */
 114 #define ATMCI_SR                        0x0040  /* Status */
 115 #define ATMCI_IER                       0x0044  /* Interrupt Enable */
 116 #define ATMCI_IDR                       0x0048  /* Interrupt Disable */
 117 #define ATMCI_IMR                       0x004c  /* Interrupt Mask */
 118 #define         ATMCI_CMDRDY                    BIT(0)          /* Command Ready */
 119 #define         ATMCI_RXRDY                     BIT(1)          /* Receiver Ready */
 120 #define         ATMCI_TXRDY                     BIT(2)          /* Transmitter Ready */
 121 #define         ATMCI_BLKE                      BIT(3)          /* Data Block Ended */
 122 #define         ATMCI_DTIP                      BIT(4)          /* Data Transfer In Progress */
 123 #define         ATMCI_NOTBUSY                   BIT(5)          /* Data Not Busy */
 124 #define         ATMCI_ENDRX                     BIT(6)          /* End of RX Buffer */
 125 #define         ATMCI_ENDTX                     BIT(7)          /* End of TX Buffer */
 126 #define         ATMCI_SDIOIRQA                  BIT(8)          /* SDIO IRQ in slot A */
 127 #define         ATMCI_SDIOIRQB                  BIT(9)          /* SDIO IRQ in slot B */
 128 #define         ATMCI_SDIOWAIT                  BIT(12)         /* SDIO Read Wait Operation Status */
 129 #define         ATMCI_CSRCV                     BIT(13)         /* CE-ATA Completion Signal Received */
 130 #define         ATMCI_RXBUFF                    BIT(14)         /* RX Buffer Full */
 131 #define         ATMCI_TXBUFE                    BIT(15)         /* TX Buffer Empty */
 132 #define         ATMCI_RINDE                     BIT(16)         /* Response Index Error */
 133 #define         ATMCI_RDIRE                     BIT(17)         /* Response Direction Error */
 134 #define         ATMCI_RCRCE                     BIT(18)         /* Response CRC Error */
 135 #define         ATMCI_RENDE                     BIT(19)         /* Response End Bit Error */
 136 #define         ATMCI_RTOE                      BIT(20)         /* Response Time-Out Error */
 137 #define         ATMCI_DCRCE                     BIT(21)         /* Data CRC Error */
 138 #define         ATMCI_DTOE                      BIT(22)         /* Data Time-Out Error */
 139 #define         ATMCI_CSTOE                     BIT(23)         /* Completion Signal Time-out Error */
 140 #define         ATMCI_BLKOVRE                   BIT(24)         /* DMA Block Overrun Error */
 141 #define         ATMCI_DMADONE                   BIT(25)         /* DMA Transfer Done */
 142 #define         ATMCI_FIFOEMPTY                 BIT(26)         /* FIFO Empty Flag */
 143 #define         ATMCI_XFRDONE                   BIT(27)         /* Transfer Done Flag */
 144 #define         ATMCI_ACKRCV                    BIT(28)         /* Boot Operation Acknowledge Received */
 145 #define         ATMCI_ACKRCVE                   BIT(29)         /* Boot Operation Acknowledge Error */
 146 #define         ATMCI_OVRE                      BIT(30)         /* RX Overrun Error */
 147 #define         ATMCI_UNRE                      BIT(31)         /* TX Underrun Error */
 148 #define ATMCI_DMA                       0x0050  /* DMA Configuration[2] */
 149 #define         ATMCI_DMA_OFFSET(x)             ((x) <<  0)     /* DMA Write Buffer Offset */
 150 #define         ATMCI_DMA_CHKSIZE(x)            ((x) <<  4)     /* DMA Channel Read and Write Chunk Size */
 151 #define         ATMCI_DMAEN                     BIT(8)  /* DMA Hardware Handshaking Enable */
 152 #define ATMCI_CFG                       0x0054  /* Configuration[2] */
 153 #define         ATMCI_CFG_FIFOMODE_1DATA        BIT(0)          /* MCI Internal FIFO control mode */
 154 #define         ATMCI_CFG_FERRCTRL_COR          BIT(4)          /* Flow Error flag reset control mode */
 155 #define         ATMCI_CFG_HSMODE                BIT(8)          /* High Speed Mode */
 156 #define         ATMCI_CFG_LSYNC                 BIT(12)         /* Synchronize on the last block */
 157 #define ATMCI_WPMR                      0x00e4  /* Write Protection Mode[2] */
 158 #define         ATMCI_WP_EN                     BIT(0)          /* WP Enable */
 159 #define         ATMCI_WP_KEY                    (0x4d4349 << 8) /* WP Key */
 160 #define ATMCI_WPSR                      0x00e8  /* Write Protection Status[2] */
 161 #define         ATMCI_GET_WP_VS(x)              ((x) & 0x0f)
 162 #define         ATMCI_GET_WP_VSRC(x)            (((x) >> 8) & 0xffff)
 163 #define ATMCI_VERSION                   0x00FC  /* Version */
 164 #define ATMCI_FIFO_APERTURE             0x0200  /* FIFO Aperture[2] */
 165
 166 /* This is not including the FIFO Aperture on MCI2 */
 167 #define ATMCI_REGS_SIZE         0x100
 168
 169 /* Register access macros */
 170 #define atmci_readl(port, reg)                          \
 171         __raw_readl((port)->regs + reg)
 172 #define atmci_writel(port, reg, value)                  \
 173         __raw_writel((value), (port)->regs + reg)
 174
 175 #define AUTOSUSPEND_DELAY       50
 176
 177 #define ATMCI_DATA_ERROR_FLAGS  (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
 178 #define ATMCI_DMA_THRESHOLD     16
 179
 180 enum {
 181         EVENT_CMD_RDY = 0,
 182         EVENT_XFER_COMPLETE,
 183         EVENT_NOTBUSY,
 184         EVENT_DATA_ERROR,
 185 };
 186
 187 enum atmel_mci_state {
 188         STATE_IDLE = 0,
 189         STATE_SENDING_CMD,
 190         STATE_DATA_XFER,
 191         STATE_WAITING_NOTBUSY,
 192         STATE_SENDING_STOP,
 193         STATE_END_REQUEST,
 194 };
 195
 196 enum atmci_xfer_dir {
 197         XFER_RECEIVE = 0,
 198         XFER_TRANSMIT,
 199 };
 200
 201 enum atmci_pdc_buf {
 202         PDC_FIRST_BUF = 0,
 203         PDC_SECOND_BUF,
 204 };
 205
 206 struct atmel_mci_caps {
 207         bool    has_dma_conf_reg;
 208         bool    has_pdc;
 209         bool    has_cfg_reg;
 210         bool    has_cstor_reg;
 211         bool    has_highspeed;
 212         bool    has_rwproof;
 213         bool    has_odd_clk_div;
 214         bool    has_bad_data_ordering;
 215         bool    need_reset_after_xfer;
 216         bool    need_blksz_mul_4;
 217         bool    need_notbusy_for_read_ops;
 218 };
 219
 220 struct atmel_mci_dma {
 221         struct dma_chan                 *chan;
 222         struct dma_async_tx_descriptor  *data_desc;
 223 };
 224
 225 /**
 226  * struct atmel_mci - MMC controller state shared between all slots
 227  * @lock: Spinlock protecting the queue and associated data.
 228  * @regs: Pointer to MMIO registers.
 229  * @sg: Scatterlist entry currently being processed by PIO or PDC code.
 230  * @pio_offset: Offset into the current scatterlist entry.
 231  * @buffer: Buffer used if we don't have the r/w proof capability. We
 232  *      don't have the time to switch pdc buffers so we have to use only
 233  *      one buffer for the full transaction.
 234  * @buf_size: size of the buffer.
 235  * @phys_buf_addr: buffer address needed for pdc.
 236  * @cur_slot: The slot which is currently using the controller.
 237  * @mrq: The request currently being processed on @cur_slot,
 238  *      or NULL if the controller is idle.
 239  * @cmd: The command currently being sent to the card, or NULL.
 240  * @data: The data currently being transferred, or NULL if no data
 241  *      transfer is in progress.
 242  * @data_size: just data->blocks * data->blksz.
 243  * @dma: DMA client state.
 244  * @data_chan: DMA channel being used for the current data transfer.
 245  * @cmd_status: Snapshot of SR taken upon completion of the current
 246  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
 247  * @data_status: Snapshot of SR taken upon completion of the current
 248  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
 249  *      EVENT_DATA_ERROR is pending.
 250  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
 251  *      to be sent.
 252  * @tasklet: Tasklet running the request state machine.
 253  * @pending_events: Bitmask of events flagged by the interrupt handler
 254  *      to be processed by the tasklet.
 255  * @completed_events: Bitmask of events which the state machine has
 256  *      processed.
 257  * @state: Tasklet state.
 258  * @queue: List of slots waiting for access to the controller.
 259  * @need_clock_update: Update the clock rate before the next request.
 260  * @need_reset: Reset controller before next request.
 261  * @timer: Timer to balance the data timeout error flag which cannot rise.
 262  * @mode_reg: Value of the MR register.
 263  * @cfg_reg: Value of the CFG register.
 264  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
 265  *      rate and timeout calculations.
 266  * @mapbase: Physical address of the MMIO registers.
 267  * @mck: The peripheral bus clock hooked up to the MMC controller.
 268  * @pdev: Platform device associated with the MMC controller.
 269  * @slot: Slots sharing this MMC controller.
 270  * @caps: MCI capabilities depending on MCI version.
 271  * @prepare_data: function to setup MCI before data transfer which
 272  * depends on MCI capabilities.
 273  * @submit_data: function to start data transfer which depends on MCI
 274  * capabilities.
 275  * @stop_transfer: function to stop data transfer which depends on MCI
 276  * capabilities.
 277  *
 278  * Locking
 279  * =======
 280  *
 281  * @lock is a softirq-safe spinlock protecting @queue as well as
 282  * @cur_slot, @mrq and @state. These must always be updated
 283  * at the same time while holding @lock.
 284  *
 285  * @lock also protects mode_reg and need_clock_update since these are
 286  * used to synchronize mode register updates with the queue
 287  * processing.
 288  *
 289  * The @mrq field of struct atmel_mci_slot is also protected by @lock,
 290  * and must always be written at the same time as the slot is added to
 291  * @queue.
 292  *
 293  * @pending_events and @completed_events are accessed using atomic bit
 294  * operations, so they don't need any locking.
 295  *
 296  * None of the fields touched by the interrupt handler need any
 297  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 298  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 299  * interrupts must be disabled and @data_status updated with a
 300  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 301  * CMDRDY interrupt must be disabled and @cmd_status updated with a
 302  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 303  * bytes_xfered field of @data must be written. This is ensured by
 304  * using barriers.
 305  */
 306 struct atmel_mci {
 307         spinlock_t              lock;
 308         void __iomem            *regs;
 309
 310         struct scatterlist      *sg;
 311         unsigned int            sg_len;
 312         unsigned int            pio_offset;
 313         unsigned int            *buffer;
 314         unsigned int            buf_size;
 315         dma_addr_t              buf_phys_addr;
 316
 317         struct atmel_mci_slot   *cur_slot;
 318         struct mmc_request      *mrq;
 319         struct mmc_command      *cmd;
 320         struct mmc_data         *data;
 321         unsigned int            data_size;
 322
 323         struct atmel_mci_dma    dma;
 324         struct dma_chan         *data_chan;
 325         struct dma_slave_config dma_conf;
 326
 327         u32                     cmd_status;
 328         u32                     data_status;
 329         u32                     stop_cmdr;
 330
 331         struct tasklet_struct   tasklet;
 332         unsigned long           pending_events;
 333         unsigned long           completed_events;
 334         enum atmel_mci_state    state;
 335         struct list_head        queue;
 336
 337         bool                    need_clock_update;
 338         bool                    need_reset;
 339         struct timer_list       timer;
 340         u32                     mode_reg;
 341         u32                     cfg_reg;
 342         unsigned long           bus_hz;
 343         unsigned long           mapbase;
 344         struct clk              *mck;
 345         struct platform_device  *pdev;
 346
 347         struct atmel_mci_slot   *slot[ATMCI_MAX_NR_SLOTS];
 348
 349         struct atmel_mci_caps   caps;
 350
 351         u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
 352         void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
 353         void (*stop_transfer)(struct atmel_mci *host);
 354 };
 355
 356 /**
 357  * struct atmel_mci_slot - MMC slot state
 358  * @mmc: The mmc_host representing this slot.
 359  * @host: The MMC controller this slot is using.
 360  * @sdc_reg: Value of SDCR to be written before using this slot.
 361  * @sdio_irq: SDIO irq mask for this slot.
 362  * @mrq: mmc_request currently being processed or waiting to be
 363  *      processed, or NULL when the slot is idle.
 364  * @queue_node: List node for placing this node in the @queue list of
 365  *      &struct atmel_mci.
 366  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
 367  * @flags: Random state bits associated with the slot.
 368  * @detect_pin: GPIO pin used for card detection, or negative if not
 369  *      available.
 370  * @wp_pin: GPIO pin used for card write protect sending, or negative
 371  *      if not available.
 372  * @detect_is_active_high: The state of the detect pin when it is active.
 373  * @detect_timer: Timer used for debouncing @detect_pin interrupts.
 374  */
 375 struct atmel_mci_slot {
 376         struct mmc_host         *mmc;
 377         struct atmel_mci        *host;
 378
 379         u32                     sdc_reg;
 380         u32                     sdio_irq;
 381
 382         struct mmc_request      *mrq;
 383         struct list_head        queue_node;
 384
 385         unsigned int            clock;
 386         unsigned long           flags;
 387 #define ATMCI_CARD_PRESENT      0
 388 #define ATMCI_CARD_NEED_INIT    1
 389 #define ATMCI_SHUTDOWN          2
 390
 391         int                     detect_pin;
 392         int                     wp_pin;
 393         bool                    detect_is_active_high;
 394
 395         struct timer_list       detect_timer;
 396 };
 397
 398 #define atmci_test_and_clear_pending(host, event)               \
 399         test_and_clear_bit(event, &host->pending_events)
 400 #define atmci_set_completed(host, event)                        \
 401         set_bit(event, &host->completed_events)
 402 #define atmci_set_pending(host, event)                          \
 403         set_bit(event, &host->pending_events)
 404
 405 /*
 406  * The debugfs stuff below is mostly optimized away when
 407  * CONFIG_DEBUG_FS is not set.
 408  */
 409 static int atmci_req_show(struct seq_file *s, void *v)
 410 {
 411         struct atmel_mci_slot   *slot = s->private;
 412         struct mmc_request      *mrq;
 413         struct mmc_command      *cmd;
 414         struct mmc_command      *stop;
 415         struct mmc_data         *data;
 416
 417         /* Make sure we get a consistent snapshot */
 418         spin_lock_bh(&slot->host->lock);
 419         mrq = slot->mrq;
 420
 421         if (mrq) {
 422                 cmd = mrq->cmd;
 423                 data = mrq->data;
 424                 stop = mrq->stop;
 425
 426                 if (cmd)
 427                         seq_printf(s,
 428                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 429                                 cmd->opcode, cmd->arg, cmd->flags,
 430                                 cmd->resp[0], cmd->resp[1], cmd->resp[2],
 431                                 cmd->resp[3], cmd->error);
 432                 if (data)
 433                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 434                                 data->bytes_xfered, data->blocks,
 435                                 data->blksz, data->flags, data->error);
 436                 if (stop)
 437                         seq_printf(s,
 438                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 439                                 stop->opcode, stop->arg, stop->flags,
 440                                 stop->resp[0], stop->resp[1], stop->resp[2],
 441                                 stop->resp[3], stop->error);
 442         }
 443
 444         spin_unlock_bh(&slot->host->lock);
 445
 446         return 0;
 447 }
 448
 449 DEFINE_SHOW_ATTRIBUTE(atmci_req);
 450
 451 static void atmci_show_status_reg(struct seq_file *s,
 452                 const char *regname, u32 value)
 453 {
 454         static const char       *sr_bit[] = {
 455                 [0]     = "CMDRDY",
 456                 [1]     = "RXRDY",
 457                 [2]     = "TXRDY",
 458                 [3]     = "BLKE",
 459                 [4]     = "DTIP",
 460                 [5]     = "NOTBUSY",
 461                 [6]     = "ENDRX",
 462                 [7]     = "ENDTX",
 463                 [8]     = "SDIOIRQA",
 464                 [9]     = "SDIOIRQB",
 465                 [12]    = "SDIOWAIT",
 466                 [14]    = "RXBUFF",
 467                 [15]    = "TXBUFE",
 468                 [16]    = "RINDE",
 469                 [17]    = "RDIRE",
 470                 [18]    = "RCRCE",
 471                 [19]    = "RENDE",
 472                 [20]    = "RTOE",
 473                 [21]    = "DCRCE",
 474                 [22]    = "DTOE",
 475                 [23]    = "CSTOE",
 476                 [24]    = "BLKOVRE",
 477                 [25]    = "DMADONE",
 478                 [26]    = "FIFOEMPTY",
 479                 [27]    = "XFRDONE",
 480                 [30]    = "OVRE",
 481                 [31]    = "UNRE",
 482         };
 483         unsigned int            i;
 484
 485         seq_printf(s, "%s:\t0x%08x", regname, value);
 486         for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
 487                 if (value & (1 << i)) {
 488                         if (sr_bit[i])
 489                                 seq_printf(s, " %s", sr_bit[i]);
 490                         else
 491                                 seq_puts(s, " UNKNOWN");
 492                 }
 493         }
 494         seq_putc(s, '\n');
 495 }
 496
 497 static int atmci_regs_show(struct seq_file *s, void *v)
 498 {
 499         struct atmel_mci        *host = s->private;
 500         u32                     *buf;
 501         int                     ret = 0;
 502
 503
 504         buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
 505         if (!buf)
 506                 return -ENOMEM;
 507
 508         pm_runtime_get_sync(&host->pdev->dev);
 509
 510         /*
 511          * Grab a more or less consistent snapshot. Note that we're
 512          * not disabling interrupts, so IMR and SR may not be
 513          * consistent.
 514          */
 515         spin_lock_bh(&host->lock);
 516         memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
 517         spin_unlock_bh(&host->lock);
 518
 519         pm_runtime_mark_last_busy(&host->pdev->dev);
 520         pm_runtime_put_autosuspend(&host->pdev->dev);
 521
 522         seq_printf(s, "MR:\t0x%08x%s%s ",
 523                         buf[ATMCI_MR / 4],
 524                         buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
 525                         buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
 526         if (host->caps.has_odd_clk_div)
 527                 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
 528                                 ((buf[ATMCI_MR / 4] & 0xff) << 1)
 529                                 | ((buf[ATMCI_MR / 4] >> 16) & 1));
 530         else
 531                 seq_printf(s, "CLKDIV=%u\n",
 532                                 (buf[ATMCI_MR / 4] & 0xff));
 533         seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
 534         seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
 535         seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
 536         seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
 537                         buf[ATMCI_BLKR / 4],
 538                         buf[ATMCI_BLKR / 4] & 0xffff,
 539                         (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
 540         if (host->caps.has_cstor_reg)
 541                 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
 542
 543         /* Don't read RSPR and RDR; it will consume the data there */
 544
 545         atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
 546         atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
 547
 548         if (host->caps.has_dma_conf_reg) {
 549                 u32 val;
 550
 551                 val = buf[ATMCI_DMA / 4];
 552                 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
 553                                 val, val & 3,
 554                                 ((val >> 4) & 3) ?
 555                                         1 << (((val >> 4) & 3) + 1) : 1,
 556                                 val & ATMCI_DMAEN ? " DMAEN" : "");
 557         }
 558         if (host->caps.has_cfg_reg) {
 559                 u32 val;
 560
 561                 val = buf[ATMCI_CFG / 4];
 562                 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
 563                                 val,
 564                                 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
 565                                 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
 566                                 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
 567                                 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
 568         }
 569
 570         kfree(buf);
 571
 572         return ret;
 573 }
 574
 575 DEFINE_SHOW_ATTRIBUTE(atmci_regs);
 576
 577 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
 578 {
 579         struct mmc_host         *mmc = slot->mmc;
 580         struct atmel_mci        *host = slot->host;
 581         struct dentry           *root;
 582         struct dentry           *node;
 583
 584         root = mmc->debugfs_root;
 585         if (!root)
 586                 return;
 587
 588         node = debugfs_create_file("regs", S_IRUSR, root, host,
 589                                    &atmci_regs_fops);
 590         if (IS_ERR(node))
 591                 return;
 592         if (!node)
 593                 goto err;
 594
 595         node = debugfs_create_file("req", S_IRUSR, root, slot,
 596                                    &atmci_req_fops);
 597         if (!node)
 598                 goto err;
 599
 600         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 601         if (!node)
 602                 goto err;
 603
 604         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 605                                      (u32 *)&host->pending_events);
 606         if (!node)
 607                 goto err;
 608
 609         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 610                                      (u32 *)&host->completed_events);
 611         if (!node)
 612                 goto err;
 613
 614         return;
 615
 616 err:
 617         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 618 }
 619
 620 #if defined(CONFIG_OF)
 621 static const struct of_device_id atmci_dt_ids[] = {
 622         { .compatible = "atmel,hsmci" },
 623         { /* sentinel */ }
 624 };
 625
 626 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
 627
 628 static struct mci_platform_data*
 629 atmci_of_init(struct platform_device *pdev)
 630 {
 631         struct device_node *np = pdev->dev.of_node;
 632         struct device_node *cnp;
 633         struct mci_platform_data *pdata;
 634         u32 slot_id;
 635
 636         if (!np) {
 637                 dev_err(&pdev->dev, "device node not found\n");
 638                 return ERR_PTR(-EINVAL);
 639         }
 640
 641         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 642         if (!pdata)
 643                 return ERR_PTR(-ENOMEM);
 644
 645         for_each_child_of_node(np, cnp) {
 646                 if (of_property_read_u32(cnp, "reg", &slot_id)) {
 647                         dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
 648                                  cnp);
 649                         continue;
 650                 }
 651
 652                 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
 653                         dev_warn(&pdev->dev, "can't have more than %d slots\n",
 654                                  ATMCI_MAX_NR_SLOTS);
 655                         of_node_put(cnp);
 656                         break;
 657                 }
 658
 659                 if (of_property_read_u32(cnp, "bus-width",
 660                                          &pdata->slot[slot_id].bus_width))
 661                         pdata->slot[slot_id].bus_width = 1;
 662
 663                 pdata->slot[slot_id].detect_pin =
 664                         of_get_named_gpio(cnp, "cd-gpios", 0);
 665
 666                 pdata->slot[slot_id].detect_is_active_high =
 667                         of_property_read_bool(cnp, "cd-inverted");
 668
 669                 pdata->slot[slot_id].non_removable =
 670                         of_property_read_bool(cnp, "non-removable");
 671
 672                 pdata->slot[slot_id].wp_pin =
 673                         of_get_named_gpio(cnp, "wp-gpios", 0);
 674         }
 675
 676         return pdata;
 677 }
 678 #else /* CONFIG_OF */
 679 static inline struct mci_platform_data*
 680 atmci_of_init(struct platform_device *dev)
 681 {
 682         return ERR_PTR(-EINVAL);
 683 }
 684 #endif
 685
 686 static inline unsigned int atmci_get_version(struct atmel_mci *host)
 687 {
 688         return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
 689 }
 690
 691 /*
 692  * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
 693  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 694  * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
 695  * 8 -> 3, 16 -> 4.
 696  *
 697  * This can be done by finding most significant bit set.
 698  */
 699 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
 700                                                  unsigned int maxburst)
 701 {
 702         unsigned int version = atmci_get_version(host);
 703         unsigned int offset = 2;
 704
 705         if (version >= 0x600)
 706                 offset = 1;
 707
 708         if (maxburst > 1)
 709                 return fls(maxburst) - offset;
 710         else
 711                 return 0;
 712 }
 713
 714 static void atmci_timeout_timer(struct timer_list *t)
 715 {
 716         struct atmel_mci *host;
 717
 718         host = from_timer(host, t, timer);
 719
 720         dev_dbg(&host->pdev->dev, "software timeout\n");
 721
 722         if (host->mrq->cmd->data) {
 723                 host->mrq->cmd->data->error = -ETIMEDOUT;
 724                 host->data = NULL;
 725                 /*
 726                  * With some SDIO modules, sometimes DMA transfer hangs. If
 727                  * stop_transfer() is not called then the DMA request is not
 728                  * removed, following ones are queued and never computed.
 729                  */
 730                 if (host->state == STATE_DATA_XFER)
 731                         host->stop_transfer(host);
 732         } else {
 733                 host->mrq->cmd->error = -ETIMEDOUT;
 734                 host->cmd = NULL;
 735         }
 736         host->need_reset = 1;
 737         host->state = STATE_END_REQUEST;
 738         smp_wmb();
 739         tasklet_schedule(&host->tasklet);
 740 }
 741
 742 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 743                                         unsigned int ns)
 744 {
 745         /*
 746          * It is easier here to use us instead of ns for the timeout,
 747          * it prevents from overflows during calculation.
 748          */
 749         unsigned int us = DIV_ROUND_UP(ns, 1000);
 750
 751         /* Maximum clock frequency is host->bus_hz/2 */
 752         return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
 753 }
 754
 755 static void atmci_set_timeout(struct atmel_mci *host,
 756                 struct atmel_mci_slot *slot, struct mmc_data *data)
 757 {
 758         static unsigned dtomul_to_shift[] = {
 759                 0, 4, 7, 8, 10, 12, 16, 20
 760         };
 761         unsigned        timeout;
 762         unsigned        dtocyc;
 763         unsigned        dtomul;
 764
 765         timeout = atmci_ns_to_clocks(host, data->timeout_ns)
 766                 + data->timeout_clks;
 767
 768         for (dtomul = 0; dtomul < 8; dtomul++) {
 769                 unsigned shift = dtomul_to_shift[dtomul];
 770                 dtocyc = (timeout + (1 << shift) - 1) >> shift;
 771                 if (dtocyc < 15)
 772                         break;
 773         }
 774
 775         if (dtomul >= 8) {
 776                 dtomul = 7;
 777                 dtocyc = 15;
 778         }
 779
 780         dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
 781                         dtocyc << dtomul_to_shift[dtomul]);
 782         atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
 783 }
 784
 785 /*
 786  * Return mask with command flags to be enabled for this command.
 787  */
 788 static u32 atmci_prepare_command(struct mmc_host *mmc,
 789                                  struct mmc_command *cmd)
 790 {
 791         struct mmc_data *data;
 792         u32             cmdr;
 793
 794         cmd->error = -EINPROGRESS;
 795
 796         cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
 797
 798         if (cmd->flags & MMC_RSP_PRESENT) {
 799                 if (cmd->flags & MMC_RSP_136)
 800                         cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
 801                 else
 802                         cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
 803         }
 804
 805         /*
 806          * This should really be MAXLAT_5 for CMD2 and ACMD41, but
 807          * it's too difficult to determine whether this is an ACMD or
 808          * not. Better make it 64.
 809          */
 810         cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
 811
 812         if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
 813                 cmdr |= ATMCI_CMDR_OPDCMD;
 814
 815         data = cmd->data;
 816         if (data) {
 817                 cmdr |= ATMCI_CMDR_START_XFER;
 818
 819                 if (cmd->opcode == SD_IO_RW_EXTENDED) {
 820                         cmdr |= ATMCI_CMDR_SDIO_BLOCK;
 821                 } else {
 822                         if (data->blocks > 1)
 823                                 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
 824                         else
 825                                 cmdr |= ATMCI_CMDR_BLOCK;
 826                 }
 827
 828                 if (data->flags & MMC_DATA_READ)
 829                         cmdr |= ATMCI_CMDR_TRDIR_READ;
 830         }
 831
 832         return cmdr;
 833 }
 834
 835 static void atmci_send_command(struct atmel_mci *host,
 836                 struct mmc_command *cmd, u32 cmd_flags)
 837 {
 838         WARN_ON(host->cmd);
 839         host->cmd = cmd;
 840
 841         dev_vdbg(&host->pdev->dev,
 842                         "start command: ARGR=0x%08x CMDR=0x%08x\n",
 843                         cmd->arg, cmd_flags);
 844
 845         atmci_writel(host, ATMCI_ARGR, cmd->arg);
 846         atmci_writel(host, ATMCI_CMDR, cmd_flags);
 847 }
 848
 849 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
 850 {
 851         dev_dbg(&host->pdev->dev, "send stop command\n");
 852         atmci_send_command(host, data->stop, host->stop_cmdr);
 853         atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
 854 }
 855
 856 /*
 857  * Configure given PDC buffer taking care of alignement issues.
 858  * Update host->data_size and host->sg.
 859  */
 860 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
 861         enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
 862 {
 863         u32 pointer_reg, counter_reg;
 864         unsigned int buf_size;
 865
 866         if (dir == XFER_RECEIVE) {
 867                 pointer_reg = ATMEL_PDC_RPR;
 868                 counter_reg = ATMEL_PDC_RCR;
 869         } else {
 870                 pointer_reg = ATMEL_PDC_TPR;
 871                 counter_reg = ATMEL_PDC_TCR;
 872         }
 873
 874         if (buf_nb == PDC_SECOND_BUF) {
 875                 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
 876                 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
 877         }
 878
 879         if (!host->caps.has_rwproof) {
 880                 buf_size = host->buf_size;
 881                 atmci_writel(host, pointer_reg, host->buf_phys_addr);
 882         } else {
 883                 buf_size = sg_dma_len(host->sg);
 884                 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
 885         }
 886
 887         if (host->data_size <= buf_size) {
 888                 if (host->data_size & 0x3) {
 889                         /* If size is different from modulo 4, transfer bytes */
 890                         atmci_writel(host, counter_reg, host->data_size);
 891                         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
 892                 } else {
 893                         /* Else transfer 32-bits words */
 894                         atmci_writel(host, counter_reg, host->data_size / 4);
 895                 }
 896                 host->data_size = 0;
 897         } else {
 898                 /* We assume the size of a page is 32-bits aligned */
 899                 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
 900                 host->data_size -= sg_dma_len(host->sg);
 901                 if (host->data_size)
 902                         host->sg = sg_next(host->sg);
 903         }
 904 }
 905
 906 /*
 907  * Configure PDC buffer according to the data size ie configuring one or two
 908  * buffers. Don't use this function if you want to configure only the second
 909  * buffer. In this case, use atmci_pdc_set_single_buf.
 910  */
 911 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
 912 {
 913         atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
 914         if (host->data_size)
 915                 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
 916 }
 917
 918 /*
 919  * Unmap sg lists, called when transfer is finished.
 920  */
 921 static void atmci_pdc_cleanup(struct atmel_mci *host)
 922 {
 923         struct mmc_data         *data = host->data;
 924
 925         if (data)
 926                 dma_unmap_sg(&host->pdev->dev,
 927                                 data->sg, data->sg_len,
 928                                 mmc_get_dma_dir(data));
 929 }
 930
 931 /*
 932  * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
 933  * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
 934  * interrupt needed for both transfer directions.
 935  */
 936 static void atmci_pdc_complete(struct atmel_mci *host)
 937 {
 938         int transfer_size = host->data->blocks * host->data->blksz;
 939         int i;
 940
 941         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
 942
 943         if ((!host->caps.has_rwproof)
 944             && (host->data->flags & MMC_DATA_READ)) {
 945                 if (host->caps.has_bad_data_ordering)
 946                         for (i = 0; i < transfer_size; i++)
 947                                 host->buffer[i] = swab32(host->buffer[i]);
 948                 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
 949                                     host->buffer, transfer_size);
 950         }
 951
 952         atmci_pdc_cleanup(host);
 953
 954         dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
 955         atmci_set_pending(host, EVENT_XFER_COMPLETE);
 956         tasklet_schedule(&host->tasklet);
 957 }
 958
 959 static void atmci_dma_cleanup(struct atmel_mci *host)
 960 {
 961         struct mmc_data                 *data = host->data;
 962
 963         if (data)
 964                 dma_unmap_sg(host->dma.chan->device->dev,
 965                                 data->sg, data->sg_len,
 966                                 mmc_get_dma_dir(data));
 967 }
 968
 969 /*
 970  * This function is called by the DMA driver from tasklet context.
 971  */
 972 static void atmci_dma_complete(void *arg)
 973 {
 974         struct atmel_mci        *host = arg;
 975         struct mmc_data         *data = host->data;
 976
 977         dev_vdbg(&host->pdev->dev, "DMA complete\n");
 978
 979         if (host->caps.has_dma_conf_reg)
 980                 /* Disable DMA hardware handshaking on MCI */
 981                 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
 982
 983         atmci_dma_cleanup(host);
 984
 985         /*
 986          * If the card was removed, data will be NULL. No point trying
 987          * to send the stop command or waiting for NBUSY in this case.
 988          */
 989         if (data) {
 990                 dev_dbg(&host->pdev->dev,
 991                         "(%s) set pending xfer complete\n", __func__);
 992                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
 993                 tasklet_schedule(&host->tasklet);
 994
 995                 /*
 996                  * Regardless of what the documentation says, we have
 997                  * to wait for NOTBUSY even after block read
 998                  * operations.
 999                  *
1000                  * When the DMA transfer is complete, the controller
1001                  * may still be reading the CRC from the card, i.e.
1002                  * the data transfer is still in progress and we
1003                  * haven't seen all the potential error bits yet.
1004                  *
1005                  * The interrupt handler will schedule a different
1006                  * tasklet to finish things up when the data transfer
1007                  * is completely done.
1008                  *
1009                  * We may not complete the mmc request here anyway
1010                  * because the mmc layer may call back and cause us to
1011                  * violate the "don't submit new operations from the
1012                  * completion callback" rule of the dma engine
1013                  * framework.
1014                  */
1015                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1016         }
1017 }
1018
1019 /*
1020  * Returns a mask of interrupt flags to be enabled after the whole
1021  * request has been prepared.
1022  */
1023 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1024 {
1025         u32 iflags;
1026
1027         data->error = -EINPROGRESS;
1028
1029         host->sg = data->sg;
1030         host->sg_len = data->sg_len;
1031         host->data = data;
1032         host->data_chan = NULL;
1033
1034         iflags = ATMCI_DATA_ERROR_FLAGS;
1035
1036         /*
1037          * Errata: MMC data write operation with less than 12
1038          * bytes is impossible.
1039          *
1040          * Errata: MCI Transmit Data Register (TDR) FIFO
1041          * corruption when length is not multiple of 4.
1042          */
1043         if (data->blocks * data->blksz < 12
1044                         || (data->blocks * data->blksz) & 3)
1045                 host->need_reset = true;
1046
1047         host->pio_offset = 0;
1048         if (data->flags & MMC_DATA_READ)
1049                 iflags |= ATMCI_RXRDY;
1050         else
1051                 iflags |= ATMCI_TXRDY;
1052
1053         return iflags;
1054 }
1055
1056 /*
1057  * Set interrupt flags and set block length into the MCI mode register even
1058  * if this value is also accessible in the MCI block register. It seems to be
1059  * necessary before the High Speed MCI version. It also map sg and configure
1060  * PDC registers.
1061  */
1062 static u32
1063 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1064 {
1065         u32 iflags, tmp;
1066         int i;
1067
1068         data->error = -EINPROGRESS;
1069
1070         host->data = data;
1071         host->sg = data->sg;
1072         iflags = ATMCI_DATA_ERROR_FLAGS;
1073
1074         /* Enable pdc mode */
1075         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1076
1077         if (data->flags & MMC_DATA_READ)
1078                 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1079         else
1080                 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1081
1082         /* Set BLKLEN */
1083         tmp = atmci_readl(host, ATMCI_MR);
1084         tmp &= 0x0000ffff;
1085         tmp |= ATMCI_BLKLEN(data->blksz);
1086         atmci_writel(host, ATMCI_MR, tmp);
1087
1088         /* Configure PDC */
1089         host->data_size = data->blocks * data->blksz;
1090         dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1091                    mmc_get_dma_dir(data));
1092
1093         if ((!host->caps.has_rwproof)
1094             && (host->data->flags & MMC_DATA_WRITE)) {
1095                 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1096                                   host->buffer, host->data_size);
1097                 if (host->caps.has_bad_data_ordering)
1098                         for (i = 0; i < host->data_size; i++)
1099                                 host->buffer[i] = swab32(host->buffer[i]);
1100         }
1101
1102         if (host->data_size)
1103                 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1104                                        XFER_RECEIVE : XFER_TRANSMIT);
1105         return iflags;
1106 }
1107
1108 static u32
1109 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1110 {
1111         struct dma_chan                 *chan;
1112         struct dma_async_tx_descriptor  *desc;
1113         struct scatterlist              *sg;
1114         unsigned int                    i;
1115         enum dma_transfer_direction     slave_dirn;
1116         unsigned int                    sglen;
1117         u32                             maxburst;
1118         u32 iflags;
1119
1120         data->error = -EINPROGRESS;
1121
1122         WARN_ON(host->data);
1123         host->sg = NULL;
1124         host->data = data;
1125
1126         iflags = ATMCI_DATA_ERROR_FLAGS;
1127
1128         /*
1129          * We don't do DMA on "complex" transfers, i.e. with
1130          * non-word-aligned buffers or lengths. Also, we don't bother
1131          * with all the DMA setup overhead for short transfers.
1132          */
1133         if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1134                 return atmci_prepare_data(host, data);
1135         if (data->blksz & 3)
1136                 return atmci_prepare_data(host, data);
1137
1138         for_each_sg(data->sg, sg, data->sg_len, i) {
1139                 if (sg->offset & 3 || sg->length & 3)
1140                         return atmci_prepare_data(host, data);
1141         }
1142
1143         /* If we don't have a channel, we can't do DMA */
1144         chan = host->dma.chan;
1145         if (chan)
1146                 host->data_chan = chan;
1147
1148         if (!chan)
1149                 return -ENODEV;
1150
1151         if (data->flags & MMC_DATA_READ) {
1152                 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1153                 maxburst = atmci_convert_chksize(host,
1154                                                  host->dma_conf.src_maxburst);
1155         } else {
1156                 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1157                 maxburst = atmci_convert_chksize(host,
1158                                                  host->dma_conf.dst_maxburst);
1159         }
1160
1161         if (host->caps.has_dma_conf_reg)
1162                 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1163                         ATMCI_DMAEN);
1164
1165         sglen = dma_map_sg(chan->device->dev, data->sg,
1166                         data->sg_len, mmc_get_dma_dir(data));
1167
1168         dmaengine_slave_config(chan, &host->dma_conf);
1169         desc = dmaengine_prep_slave_sg(chan,
1170                         data->sg, sglen, slave_dirn,
1171                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1172         if (!desc)
1173                 goto unmap_exit;
1174
1175         host->dma.data_desc = desc;
1176         desc->callback = atmci_dma_complete;
1177         desc->callback_param = host;
1178
1179         return iflags;
1180 unmap_exit:
1181         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1182                      mmc_get_dma_dir(data));
1183         return -ENOMEM;
1184 }
1185
1186 static void
1187 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1188 {
1189         return;
1190 }
1191
1192 /*
1193  * Start PDC according to transfer direction.
1194  */
1195 static void
1196 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1197 {
1198         if (data->flags & MMC_DATA_READ)
1199                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1200         else
1201                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1202 }
1203
1204 static void
1205 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1206 {
1207         struct dma_chan                 *chan = host->data_chan;
1208         struct dma_async_tx_descriptor  *desc = host->dma.data_desc;
1209
1210         if (chan) {
1211                 dmaengine_submit(desc);
1212                 dma_async_issue_pending(chan);
1213         }
1214 }
1215
1216 static void atmci_stop_transfer(struct atmel_mci *host)
1217 {
1218         dev_dbg(&host->pdev->dev,
1219                 "(%s) set pending xfer complete\n", __func__);
1220         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1221         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1222 }
1223
1224 /*
1225  * Stop data transfer because error(s) occurred.
1226  */
1227 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1228 {
1229         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1230 }
1231
1232 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1233 {
1234         struct dma_chan *chan = host->data_chan;
1235
1236         if (chan) {
1237                 dmaengine_terminate_all(chan);
1238                 atmci_dma_cleanup(host);
1239         } else {
1240                 /* Data transfer was stopped by the interrupt handler */
1241                 dev_dbg(&host->pdev->dev,
1242                         "(%s) set pending xfer complete\n", __func__);
1243                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1244                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1245         }
1246 }
1247
1248 /*
1249  * Start a request: prepare data if needed, prepare the command and activate
1250  * interrupts.
1251  */
1252 static void atmci_start_request(struct atmel_mci *host,
1253                 struct atmel_mci_slot *slot)
1254 {
1255         struct mmc_request      *mrq;
1256         struct mmc_command      *cmd;
1257         struct mmc_data         *data;
1258         u32                     iflags;
1259         u32                     cmdflags;
1260
1261         mrq = slot->mrq;
1262         host->cur_slot = slot;
1263         host->mrq = mrq;
1264
1265         host->pending_events = 0;
1266         host->completed_events = 0;
1267         host->cmd_status = 0;
1268         host->data_status = 0;
1269
1270         dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1271
1272         if (host->need_reset || host->caps.need_reset_after_xfer) {
1273                 iflags = atmci_readl(host, ATMCI_IMR);
1274                 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1275                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1276                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1277                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1278                 if (host->caps.has_cfg_reg)
1279                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1280                 atmci_writel(host, ATMCI_IER, iflags);
1281                 host->need_reset = false;
1282         }
1283         atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1284
1285         iflags = atmci_readl(host, ATMCI_IMR);
1286         if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1287                 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1288                                 iflags);
1289
1290         if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1291                 /* Send init sequence (74 clock cycles) */
1292                 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1293                 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1294                         cpu_relax();
1295         }
1296         iflags = 0;
1297         data = mrq->data;
1298         if (data) {
1299                 atmci_set_timeout(host, slot, data);
1300
1301                 /* Must set block count/size before sending command */
1302                 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1303                                 | ATMCI_BLKLEN(data->blksz));
1304                 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1305                         ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1306
1307                 iflags |= host->prepare_data(host, data);
1308         }
1309
1310         iflags |= ATMCI_CMDRDY;
1311         cmd = mrq->cmd;
1312         cmdflags = atmci_prepare_command(slot->mmc, cmd);
1313
1314         /*
1315          * DMA transfer should be started before sending the command to avoid
1316          * unexpected errors especially for read operations in SDIO mode.
1317          * Unfortunately, in PDC mode, command has to be sent before starting
1318          * the transfer.
1319          */
1320         if (host->submit_data != &atmci_submit_data_dma)
1321                 atmci_send_command(host, cmd, cmdflags);
1322
1323         if (data)
1324                 host->submit_data(host, data);
1325
1326         if (host->submit_data == &atmci_submit_data_dma)
1327                 atmci_send_command(host, cmd, cmdflags);
1328
1329         if (mrq->stop) {
1330                 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1331                 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1332                 if (!(data->flags & MMC_DATA_WRITE))
1333                         host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1334                 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1335         }
1336
1337         /*
1338          * We could have enabled interrupts earlier, but I suspect
1339          * that would open up a nice can of interesting race
1340          * conditions (e.g. command and data complete, but stop not
1341          * prepared yet.)
1342          */
1343         atmci_writel(host, ATMCI_IER, iflags);
1344
1345         mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
1346 }
1347
1348 static void atmci_queue_request(struct atmel_mci *host,
1349                 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1350 {
1351         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1352                         host->state);
1353
1354         spin_lock_bh(&host->lock);
1355         slot->mrq = mrq;
1356         if (host->state == STATE_IDLE) {
1357                 host->state = STATE_SENDING_CMD;
1358                 atmci_start_request(host, slot);
1359         } else {
1360                 dev_dbg(&host->pdev->dev, "queue request\n");
1361                 list_add_tail(&slot->queue_node, &host->queue);
1362         }
1363         spin_unlock_bh(&host->lock);
1364 }
1365
1366 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1367 {
1368         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1369         struct atmel_mci        *host = slot->host;
1370         struct mmc_data         *data;
1371
1372         WARN_ON(slot->mrq);
1373         dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1374
1375         /*
1376          * We may "know" the card is gone even though there's still an
1377          * electrical connection. If so, we really need to communicate
1378          * this to the MMC core since there won't be any more
1379          * interrupts as the card is completely removed. Otherwise,
1380          * the MMC core might believe the card is still there even
1381          * though the card was just removed very slowly.
1382          */
1383         if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1384                 mrq->cmd->error = -ENOMEDIUM;
1385                 mmc_request_done(mmc, mrq);
1386                 return;
1387         }
1388
1389         /* We don't support multiple blocks of weird lengths. */
1390         data = mrq->data;
1391         if (data && data->blocks > 1 && data->blksz & 3) {
1392                 mrq->cmd->error = -EINVAL;
1393                 mmc_request_done(mmc, mrq);
1394         }
1395
1396         atmci_queue_request(host, slot, mrq);
1397 }
1398
1399 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1400 {
1401         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1402         struct atmel_mci        *host = slot->host;
1403         unsigned int            i;
1404
1405         slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1406         switch (ios->bus_width) {
1407         case MMC_BUS_WIDTH_1:
1408                 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1409                 break;
1410         case MMC_BUS_WIDTH_4:
1411                 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1412                 break;
1413         }
1414
1415         if (ios->clock) {
1416                 unsigned int clock_min = ~0U;
1417                 int clkdiv;
1418
1419                 spin_lock_bh(&host->lock);
1420                 if (!host->mode_reg) {
1421                         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1422                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1423                         if (host->caps.has_cfg_reg)
1424                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1425                 }
1426
1427                 /*
1428                  * Use mirror of ios->clock to prevent race with mmc
1429                  * core ios update when finding the minimum.
1430                  */
1431                 slot->clock = ios->clock;
1432                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1433                         if (host->slot[i] && host->slot[i]->clock
1434                                         && host->slot[i]->clock < clock_min)
1435                                 clock_min = host->slot[i]->clock;
1436                 }
1437
1438                 /* Calculate clock divider */
1439                 if (host->caps.has_odd_clk_div) {
1440                         clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1441                         if (clkdiv < 0) {
1442                                 dev_warn(&mmc->class_dev,
1443                                          "clock %u too fast; using %lu\n",
1444                                          clock_min, host->bus_hz / 2);
1445                                 clkdiv = 0;
1446                         } else if (clkdiv > 511) {
1447                                 dev_warn(&mmc->class_dev,
1448                                          "clock %u too slow; using %lu\n",
1449                                          clock_min, host->bus_hz / (511 + 2));
1450                                 clkdiv = 511;
1451                         }
1452                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1453                                          | ATMCI_MR_CLKODD(clkdiv & 1);
1454                 } else {
1455                         clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1456                         if (clkdiv > 255) {
1457                                 dev_warn(&mmc->class_dev,
1458                                          "clock %u too slow; using %lu\n",
1459                                          clock_min, host->bus_hz / (2 * 256));
1460                                 clkdiv = 255;
1461                         }
1462                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1463                 }
1464
1465                 /*
1466                  * WRPROOF and RDPROOF prevent overruns/underruns by
1467                  * stopping the clock when the FIFO is full/empty.
1468                  * This state is not expected to last for long.
1469                  */
1470                 if (host->caps.has_rwproof)
1471                         host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1472
1473                 if (host->caps.has_cfg_reg) {
1474                         /* setup High Speed mode in relation with card capacity */
1475                         if (ios->timing == MMC_TIMING_SD_HS)
1476                                 host->cfg_reg |= ATMCI_CFG_HSMODE;
1477                         else
1478                                 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1479                 }
1480
1481                 if (list_empty(&host->queue)) {
1482                         atmci_writel(host, ATMCI_MR, host->mode_reg);
1483                         if (host->caps.has_cfg_reg)
1484                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1485                 } else {
1486                         host->need_clock_update = true;
1487                 }
1488
1489                 spin_unlock_bh(&host->lock);
1490         } else {
1491                 bool any_slot_active = false;
1492
1493                 spin_lock_bh(&host->lock);
1494                 slot->clock = 0;
1495                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1496                         if (host->slot[i] && host->slot[i]->clock) {
1497                                 any_slot_active = true;
1498                                 break;
1499                         }
1500                 }
1501                 if (!any_slot_active) {
1502                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1503                         if (host->mode_reg) {
1504                                 atmci_readl(host, ATMCI_MR);
1505                         }
1506                         host->mode_reg = 0;
1507                 }
1508                 spin_unlock_bh(&host->lock);
1509         }
1510
1511         switch (ios->power_mode) {
1512         case MMC_POWER_OFF:
1513                 if (!IS_ERR(mmc->supply.vmmc))
1514                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1515                 break;
1516         case MMC_POWER_UP:
1517                 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1518                 if (!IS_ERR(mmc->supply.vmmc))
1519                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1520                 break;
1521         default:
1522                 break;
1523         }
1524 }
1525
1526 static int atmci_get_ro(struct mmc_host *mmc)
1527 {
1528         int                     read_only = -ENOSYS;
1529         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1530
1531         if (gpio_is_valid(slot->wp_pin)) {
1532                 read_only = gpio_get_value(slot->wp_pin);
1533                 dev_dbg(&mmc->class_dev, "card is %s\n",
1534                                 read_only ? "read-only" : "read-write");
1535         }
1536
1537         return read_only;
1538 }
1539
1540 static int atmci_get_cd(struct mmc_host *mmc)
1541 {
1542         int                     present = -ENOSYS;
1543         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1544
1545         if (gpio_is_valid(slot->detect_pin)) {
1546                 present = !(gpio_get_value(slot->detect_pin) ^
1547                             slot->detect_is_active_high);
1548                 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1549                                 present ? "" : "not ");
1550         }
1551
1552         return present;
1553 }
1554
1555 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1556 {
1557         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1558         struct atmel_mci        *host = slot->host;
1559
1560         if (enable)
1561                 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1562         else
1563                 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1564 }
1565
1566 static const struct mmc_host_ops atmci_ops = {
1567         .request        = atmci_request,
1568         .set_ios        = atmci_set_ios,
1569         .get_ro         = atmci_get_ro,
1570         .get_cd         = atmci_get_cd,
1571         .enable_sdio_irq = atmci_enable_sdio_irq,
1572 };
1573
1574 /* Called with host->lock held */
1575 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1576         __releases(&host->lock)
1577         __acquires(&host->lock)
1578 {
1579         struct atmel_mci_slot   *slot = NULL;
1580         struct mmc_host         *prev_mmc = host->cur_slot->mmc;
1581
1582         WARN_ON(host->cmd || host->data);
1583
1584         /*
1585          * Update the MMC clock rate if necessary. This may be
1586          * necessary if set_ios() is called when a different slot is
1587          * busy transferring data.
1588          */
1589         if (host->need_clock_update) {
1590                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1591                 if (host->caps.has_cfg_reg)
1592                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1593         }
1594
1595         host->cur_slot->mrq = NULL;
1596         host->mrq = NULL;
1597         if (!list_empty(&host->queue)) {
1598                 slot = list_entry(host->queue.next,
1599                                 struct atmel_mci_slot, queue_node);
1600                 list_del(&slot->queue_node);
1601                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1602                                 mmc_hostname(slot->mmc));
1603                 host->state = STATE_SENDING_CMD;
1604                 atmci_start_request(host, slot);
1605         } else {
1606                 dev_vdbg(&host->pdev->dev, "list empty\n");
1607                 host->state = STATE_IDLE;
1608         }
1609
1610         del_timer(&host->timer);
1611
1612         spin_unlock(&host->lock);
1613         mmc_request_done(prev_mmc, mrq);
1614         spin_lock(&host->lock);
1615 }
1616
1617 static void atmci_command_complete(struct atmel_mci *host,
1618                         struct mmc_command *cmd)
1619 {
1620         u32             status = host->cmd_status;
1621
1622         /* Read the response from the card (up to 16 bytes) */
1623         cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1624         cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1625         cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1626         cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1627
1628         if (status & ATMCI_RTOE)
1629                 cmd->error = -ETIMEDOUT;
1630         else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1631                 cmd->error = -EILSEQ;
1632         else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1633                 cmd->error = -EIO;
1634         else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1635                 if (host->caps.need_blksz_mul_4) {
1636                         cmd->error = -EINVAL;
1637                         host->need_reset = 1;
1638                 }
1639         } else
1640                 cmd->error = 0;
1641 }
1642
1643 static void atmci_detect_change(struct timer_list *t)
1644 {
1645         struct atmel_mci_slot   *slot = from_timer(slot, t, detect_timer);
1646         bool                    present;
1647         bool                    present_old;
1648
1649         /*
1650          * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1651          * freeing the interrupt. We must not re-enable the interrupt
1652          * if it has been freed, and if we're shutting down, it
1653          * doesn't really matter whether the card is present or not.
1654          */
1655         smp_rmb();
1656         if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1657                 return;
1658
1659         enable_irq(gpio_to_irq(slot->detect_pin));
1660         present = !(gpio_get_value(slot->detect_pin) ^
1661                     slot->detect_is_active_high);
1662         present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1663
1664         dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1665                         present, present_old);
1666
1667         if (present != present_old) {
1668                 struct atmel_mci        *host = slot->host;
1669                 struct mmc_request      *mrq;
1670
1671                 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1672                         present ? "inserted" : "removed");
1673
1674                 spin_lock(&host->lock);
1675
1676                 if (!present)
1677                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1678                 else
1679                         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1680
1681                 /* Clean up queue if present */
1682                 mrq = slot->mrq;
1683                 if (mrq) {
1684                         if (mrq == host->mrq) {
1685                                 /*
1686                                  * Reset controller to terminate any ongoing
1687                                  * commands or data transfers.
1688                                  */
1689                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1690                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1691                                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1692                                 if (host->caps.has_cfg_reg)
1693                                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1694
1695                                 host->data = NULL;
1696                                 host->cmd = NULL;
1697
1698                                 switch (host->state) {
1699                                 case STATE_IDLE:
1700                                         break;
1701                                 case STATE_SENDING_CMD:
1702                                         mrq->cmd->error = -ENOMEDIUM;
1703                                         if (mrq->data)
1704                                                 host->stop_transfer(host);
1705                                         break;
1706                                 case STATE_DATA_XFER:
1707                                         mrq->data->error = -ENOMEDIUM;
1708                                         host->stop_transfer(host);
1709                                         break;
1710                                 case STATE_WAITING_NOTBUSY:
1711                                         mrq->data->error = -ENOMEDIUM;
1712                                         break;
1713                                 case STATE_SENDING_STOP:
1714                                         mrq->stop->error = -ENOMEDIUM;
1715                                         break;
1716                                 case STATE_END_REQUEST:
1717                                         break;
1718                                 }
1719
1720                                 atmci_request_end(host, mrq);
1721                         } else {
1722                                 list_del(&slot->queue_node);
1723                                 mrq->cmd->error = -ENOMEDIUM;
1724                                 if (mrq->data)
1725                                         mrq->data->error = -ENOMEDIUM;
1726                                 if (mrq->stop)
1727                                         mrq->stop->error = -ENOMEDIUM;
1728
1729                                 spin_unlock(&host->lock);
1730                                 mmc_request_done(slot->mmc, mrq);
1731                                 spin_lock(&host->lock);
1732                         }
1733                 }
1734                 spin_unlock(&host->lock);
1735
1736                 mmc_detect_change(slot->mmc, 0);
1737         }
1738 }
1739
1740 static void atmci_tasklet_func(unsigned long priv)
1741 {
1742         struct atmel_mci        *host = (struct atmel_mci *)priv;
1743         struct mmc_request      *mrq = host->mrq;
1744         struct mmc_data         *data = host->data;
1745         enum atmel_mci_state    state = host->state;
1746         enum atmel_mci_state    prev_state;
1747         u32                     status;
1748
1749         spin_lock(&host->lock);
1750
1751         state = host->state;
1752
1753         dev_vdbg(&host->pdev->dev,
1754                 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1755                 state, host->pending_events, host->completed_events,
1756                 atmci_readl(host, ATMCI_IMR));
1757
1758         do {
1759                 prev_state = state;
1760                 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1761
1762                 switch (state) {
1763                 case STATE_IDLE:
1764                         break;
1765
1766                 case STATE_SENDING_CMD:
1767                         /*
1768                          * Command has been sent, we are waiting for command
1769                          * ready. Then we have three next states possible:
1770                          * END_REQUEST by default, WAITING_NOTBUSY if it's a
1771                          * command needing it or DATA_XFER if there is data.
1772                          */
1773                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1774                         if (!atmci_test_and_clear_pending(host,
1775                                                 EVENT_CMD_RDY))
1776                                 break;
1777
1778                         dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1779                         host->cmd = NULL;
1780                         atmci_set_completed(host, EVENT_CMD_RDY);
1781                         atmci_command_complete(host, mrq->cmd);
1782                         if (mrq->data) {
1783                                 dev_dbg(&host->pdev->dev,
1784                                         "command with data transfer");
1785                                 /*
1786                                  * If there is a command error don't start
1787                                  * data transfer.
1788                                  */
1789                                 if (mrq->cmd->error) {
1790                                         host->stop_transfer(host);
1791                                         host->data = NULL;
1792                                         atmci_writel(host, ATMCI_IDR,
1793                                                      ATMCI_TXRDY | ATMCI_RXRDY
1794                                                      | ATMCI_DATA_ERROR_FLAGS);
1795                                         state = STATE_END_REQUEST;
1796                                 } else
1797                                         state = STATE_DATA_XFER;
1798                         } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1799                                 dev_dbg(&host->pdev->dev,
1800                                         "command response need waiting notbusy");
1801                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1802                                 state = STATE_WAITING_NOTBUSY;
1803                         } else
1804                                 state = STATE_END_REQUEST;
1805
1806                         break;
1807
1808                 case STATE_DATA_XFER:
1809                         if (atmci_test_and_clear_pending(host,
1810                                                 EVENT_DATA_ERROR)) {
1811                                 dev_dbg(&host->pdev->dev, "set completed data error\n");
1812                                 atmci_set_completed(host, EVENT_DATA_ERROR);
1813                                 state = STATE_END_REQUEST;
1814                                 break;
1815                         }
1816
1817                         /*
1818                          * A data transfer is in progress. The event expected
1819                          * to move to the next state depends of data transfer
1820                          * type (PDC or DMA). Once transfer done we can move
1821                          * to the next step which is WAITING_NOTBUSY in write
1822                          * case and directly SENDING_STOP in read case.
1823                          */
1824                         dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1825                         if (!atmci_test_and_clear_pending(host,
1826                                                 EVENT_XFER_COMPLETE))
1827                                 break;
1828
1829                         dev_dbg(&host->pdev->dev,
1830                                 "(%s) set completed xfer complete\n",
1831                                 __func__);
1832                         atmci_set_completed(host, EVENT_XFER_COMPLETE);
1833
1834                         if (host->caps.need_notbusy_for_read_ops ||
1835                            (host->data->flags & MMC_DATA_WRITE)) {
1836                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1837                                 state = STATE_WAITING_NOTBUSY;
1838                         } else if (host->mrq->stop) {
1839                                 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1840                                 atmci_send_stop_cmd(host, data);
1841                                 state = STATE_SENDING_STOP;
1842                         } else {
1843                                 host->data = NULL;
1844                                 data->bytes_xfered = data->blocks * data->blksz;
1845                                 data->error = 0;
1846                                 state = STATE_END_REQUEST;
1847                         }
1848                         break;
1849
1850                 case STATE_WAITING_NOTBUSY:
1851                         /*
1852                          * We can be in the state for two reasons: a command
1853                          * requiring waiting not busy signal (stop command
1854                          * included) or a write operation. In the latest case,
1855                          * we need to send a stop command.
1856                          */
1857                         dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1858                         if (!atmci_test_and_clear_pending(host,
1859                                                 EVENT_NOTBUSY))
1860                                 break;
1861
1862                         dev_dbg(&host->pdev->dev, "set completed not busy\n");
1863                         atmci_set_completed(host, EVENT_NOTBUSY);
1864
1865                         if (host->data) {
1866                                 /*
1867                                  * For some commands such as CMD53, even if
1868                                  * there is data transfer, there is no stop
1869                                  * command to send.
1870                                  */
1871                                 if (host->mrq->stop) {
1872                                         atmci_writel(host, ATMCI_IER,
1873                                                      ATMCI_CMDRDY);
1874                                         atmci_send_stop_cmd(host, data);
1875                                         state = STATE_SENDING_STOP;
1876                                 } else {
1877                                         host->data = NULL;
1878                                         data->bytes_xfered = data->blocks
1879                                                              * data->blksz;
1880                                         data->error = 0;
1881                                         state = STATE_END_REQUEST;
1882                                 }
1883                         } else
1884                                 state = STATE_END_REQUEST;
1885                         break;
1886
1887                 case STATE_SENDING_STOP:
1888                         /*
1889                          * In this state, it is important to set host->data to
1890                          * NULL (which is tested in the waiting notbusy state)
1891                          * in order to go to the end request state instead of
1892                          * sending stop again.
1893                          */
1894                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1895                         if (!atmci_test_and_clear_pending(host,
1896                                                 EVENT_CMD_RDY))
1897                                 break;
1898
1899                         dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1900                         host->cmd = NULL;
1901                         data->bytes_xfered = data->blocks * data->blksz;
1902                         data->error = 0;
1903                         atmci_command_complete(host, mrq->stop);
1904                         if (mrq->stop->error) {
1905                                 host->stop_transfer(host);
1906                                 atmci_writel(host, ATMCI_IDR,
1907                                              ATMCI_TXRDY | ATMCI_RXRDY
1908                                              | ATMCI_DATA_ERROR_FLAGS);
1909                                 state = STATE_END_REQUEST;
1910                         } else {
1911                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1912                                 state = STATE_WAITING_NOTBUSY;
1913                         }
1914                         host->data = NULL;
1915                         break;
1916
1917                 case STATE_END_REQUEST:
1918                         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1919                                            | ATMCI_DATA_ERROR_FLAGS);
1920                         status = host->data_status;
1921                         if (unlikely(status)) {
1922                                 host->stop_transfer(host);
1923                                 host->data = NULL;
1924                                 if (data) {
1925                                         if (status & ATMCI_DTOE) {
1926                                                 data->error = -ETIMEDOUT;
1927                                         } else if (status & ATMCI_DCRCE) {
1928                                                 data->error = -EILSEQ;
1929                                         } else {
1930                                                 data->error = -EIO;
1931                                         }
1932                                 }
1933                         }
1934
1935                         atmci_request_end(host, host->mrq);
1936                         goto unlock; /* atmci_request_end() sets host->state */
1937                         break;
1938                 }
1939         } while (state != prev_state);
1940
1941         host->state = state;
1942
1943 unlock:
1944         spin_unlock(&host->lock);
1945 }
1946
1947 static void atmci_read_data_pio(struct atmel_mci *host)
1948 {
1949         struct scatterlist      *sg = host->sg;
1950         unsigned int            offset = host->pio_offset;
1951         struct mmc_data         *data = host->data;
1952         u32                     value;
1953         u32                     status;
1954         unsigned int            nbytes = 0;
1955
1956         do {
1957                 value = atmci_readl(host, ATMCI_RDR);
1958                 if (likely(offset + 4 <= sg->length)) {
1959                         sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
1960
1961                         offset += 4;
1962                         nbytes += 4;
1963
1964                         if (offset == sg->length) {
1965                                 flush_dcache_page(sg_page(sg));
1966                                 host->sg = sg = sg_next(sg);
1967                                 host->sg_len--;
1968                                 if (!sg || !host->sg_len)
1969                                         goto done;
1970
1971                                 offset = 0;
1972                         }
1973                 } else {
1974                         unsigned int remaining = sg->length - offset;
1975
1976                         sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
1977                         nbytes += remaining;
1978
1979                         flush_dcache_page(sg_page(sg));
1980                         host->sg = sg = sg_next(sg);
1981                         host->sg_len--;
1982                         if (!sg || !host->sg_len)
1983                                 goto done;
1984
1985                         offset = 4 - remaining;
1986                         sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
1987                                         offset, 0);
1988                         nbytes += offset;
1989                 }
1990
1991                 status = atmci_readl(host, ATMCI_SR);
1992                 if (status & ATMCI_DATA_ERROR_FLAGS) {
1993                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1994                                                 | ATMCI_DATA_ERROR_FLAGS));
1995                         host->data_status = status;
1996                         data->bytes_xfered += nbytes;
1997                         return;
1998                 }
1999         } while (status & ATMCI_RXRDY);
2000
2001         host->pio_offset = offset;
2002         data->bytes_xfered += nbytes;
2003
2004         return;
2005
2006 done:
2007         atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
2008         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2009         data->bytes_xfered += nbytes;
2010         smp_wmb();
2011         atmci_set_pending(host, EVENT_XFER_COMPLETE);
2012 }
2013
2014 static void atmci_write_data_pio(struct atmel_mci *host)
2015 {
2016         struct scatterlist      *sg = host->sg;
2017         unsigned int            offset = host->pio_offset;
2018         struct mmc_data         *data = host->data;
2019         u32                     value;
2020         u32                     status;
2021         unsigned int            nbytes = 0;
2022
2023         do {
2024                 if (likely(offset + 4 <= sg->length)) {
2025                         sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
2026                         atmci_writel(host, ATMCI_TDR, value);
2027
2028                         offset += 4;
2029                         nbytes += 4;
2030                         if (offset == sg->length) {
2031                                 host->sg = sg = sg_next(sg);
2032                                 host->sg_len--;
2033                                 if (!sg || !host->sg_len)
2034                                         goto done;
2035
2036                                 offset = 0;
2037                         }
2038                 } else {
2039                         unsigned int remaining = sg->length - offset;
2040
2041                         value = 0;
2042                         sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
2043                         nbytes += remaining;
2044
2045                         host->sg = sg = sg_next(sg);
2046                         host->sg_len--;
2047                         if (!sg || !host->sg_len) {
2048                                 atmci_writel(host, ATMCI_TDR, value);
2049                                 goto done;
2050                         }
2051
2052                         offset = 4 - remaining;
2053                         sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
2054                                         offset, 0);
2055                         atmci_writel(host, ATMCI_TDR, value);
2056                         nbytes += offset;
2057                 }
2058
2059                 status = atmci_readl(host, ATMCI_SR);
2060                 if (status & ATMCI_DATA_ERROR_FLAGS) {
2061                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2062                                                 | ATMCI_DATA_ERROR_FLAGS));
2063                         host->data_status = status;
2064                         data->bytes_xfered += nbytes;
2065                         return;
2066                 }
2067         } while (status & ATMCI_TXRDY);
2068
2069         host->pio_offset = offset;
2070         data->bytes_xfered += nbytes;
2071
2072         return;
2073
2074 done:
2075         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2076         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2077         data->bytes_xfered += nbytes;
2078         smp_wmb();
2079         atmci_set_pending(host, EVENT_XFER_COMPLETE);
2080 }
2081
2082 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2083 {
2084         int     i;
2085
2086         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2087                 struct atmel_mci_slot *slot = host->slot[i];
2088                 if (slot && (status & slot->sdio_irq)) {
2089                         mmc_signal_sdio_irq(slot->mmc);
2090                 }
2091         }
2092 }
2093
2094
2095 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2096 {
2097         struct atmel_mci        *host = dev_id;
2098         u32                     status, mask, pending;
2099         unsigned int            pass_count = 0;
2100
2101         do {
2102                 status = atmci_readl(host, ATMCI_SR);
2103                 mask = atmci_readl(host, ATMCI_IMR);
2104                 pending = status & mask;
2105                 if (!pending)
2106                         break;
2107
2108                 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2109                         dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2110                         atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2111                                         | ATMCI_RXRDY | ATMCI_TXRDY
2112                                         | ATMCI_ENDRX | ATMCI_ENDTX
2113                                         | ATMCI_RXBUFF | ATMCI_TXBUFE);
2114
2115                         host->data_status = status;
2116                         dev_dbg(&host->pdev->dev, "set pending data error\n");
2117                         smp_wmb();
2118                         atmci_set_pending(host, EVENT_DATA_ERROR);
2119                         tasklet_schedule(&host->tasklet);
2120                 }
2121
2122                 if (pending & ATMCI_TXBUFE) {
2123                         dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2124                         atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2125                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2126                         /*
2127                          * We can receive this interruption before having configured
2128                          * the second pdc buffer, so we need to reconfigure first and
2129                          * second buffers again
2130                          */
2131                         if (host->data_size) {
2132                                 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2133                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2134                                 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2135                         } else {
2136                                 atmci_pdc_complete(host);
2137                         }
2138                 } else if (pending & ATMCI_ENDTX) {
2139                         dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2140                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2141
2142                         if (host->data_size) {
2143                                 atmci_pdc_set_single_buf(host,
2144                                                 XFER_TRANSMIT, PDC_SECOND_BUF);
2145                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2146                         }
2147                 }
2148
2149                 if (pending & ATMCI_RXBUFF) {
2150                         dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2151                         atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2152                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2153                         /*
2154                          * We can receive this interruption before having configured
2155                          * the second pdc buffer, so we need to reconfigure first and
2156                          * second buffers again
2157                          */
2158                         if (host->data_size) {
2159                                 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2160                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2161                                 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2162                         } else {
2163                                 atmci_pdc_complete(host);
2164                         }
2165                 } else if (pending & ATMCI_ENDRX) {
2166                         dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2167                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2168
2169                         if (host->data_size) {
2170                                 atmci_pdc_set_single_buf(host,
2171                                                 XFER_RECEIVE, PDC_SECOND_BUF);
2172                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2173                         }
2174                 }
2175
2176                 /*
2177                  * First mci IPs, so mainly the ones having pdc, have some
2178                  * issues with the notbusy signal. You can't get it after
2179                  * data transmission if you have not sent a stop command.
2180                  * The appropriate workaround is to use the BLKE signal.
2181                  */
2182                 if (pending & ATMCI_BLKE) {
2183                         dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2184                         atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2185                         smp_wmb();
2186                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2187                         atmci_set_pending(host, EVENT_NOTBUSY);
2188                         tasklet_schedule(&host->tasklet);
2189                 }
2190
2191                 if (pending & ATMCI_NOTBUSY) {
2192                         dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2193                         atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2194                         smp_wmb();
2195                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2196                         atmci_set_pending(host, EVENT_NOTBUSY);
2197                         tasklet_schedule(&host->tasklet);
2198                 }
2199
2200                 if (pending & ATMCI_RXRDY)
2201                         atmci_read_data_pio(host);
2202                 if (pending & ATMCI_TXRDY)
2203                         atmci_write_data_pio(host);
2204
2205                 if (pending & ATMCI_CMDRDY) {
2206                         dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2207                         atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2208                         host->cmd_status = status;
2209                         smp_wmb();
2210                         dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2211                         atmci_set_pending(host, EVENT_CMD_RDY);
2212                         tasklet_schedule(&host->tasklet);
2213                 }
2214
2215                 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2216                         atmci_sdio_interrupt(host, status);
2217
2218         } while (pass_count++ < 5);
2219
2220         return pass_count ? IRQ_HANDLED : IRQ_NONE;
2221 }
2222
2223 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2224 {
2225         struct atmel_mci_slot   *slot = dev_id;
2226
2227         /*
2228          * Disable interrupts until the pin has stabilized and check
2229          * the state then. Use mod_timer() since we may be in the
2230          * middle of the timer routine when this interrupt triggers.
2231          */
2232         disable_irq_nosync(irq);
2233         mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2234
2235         return IRQ_HANDLED;
2236 }
2237
2238 static int atmci_init_slot(struct atmel_mci *host,
2239                 struct mci_slot_pdata *slot_data, unsigned int id,
2240                 u32 sdc_reg, u32 sdio_irq)
2241 {
2242         struct mmc_host                 *mmc;
2243         struct atmel_mci_slot           *slot;
2244
2245         mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2246         if (!mmc)
2247                 return -ENOMEM;
2248
2249         slot = mmc_priv(mmc);
2250         slot->mmc = mmc;
2251         slot->host = host;
2252         slot->detect_pin = slot_data->detect_pin;
2253         slot->wp_pin = slot_data->wp_pin;
2254         slot->detect_is_active_high = slot_data->detect_is_active_high;
2255         slot->sdc_reg = sdc_reg;
2256         slot->sdio_irq = sdio_irq;
2257
2258         dev_dbg(&mmc->class_dev,
2259                 "slot[%u]: bus_width=%u, detect_pin=%d, "
2260                 "detect_is_active_high=%s, wp_pin=%d\n",
2261                 id, slot_data->bus_width, slot_data->detect_pin,
2262                 slot_data->detect_is_active_high ? "true" : "false",
2263                 slot_data->wp_pin);
2264
2265         mmc->ops = &atmci_ops;
2266         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2267         mmc->f_max = host->bus_hz / 2;
2268         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
2269         if (sdio_irq)
2270                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2271         if (host->caps.has_highspeed)
2272                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2273         /*
2274          * Without the read/write proof capability, it is strongly suggested to
2275          * use only one bit for data to prevent fifo underruns and overruns
2276          * which will corrupt data.
2277          */
2278         if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2279                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2280
2281         if (atmci_get_version(host) < 0x200) {
2282                 mmc->max_segs = 256;
2283                 mmc->max_blk_size = 4095;
2284                 mmc->max_blk_count = 256;
2285                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2286                 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2287         } else {
2288                 mmc->max_segs = 64;
2289                 mmc->max_req_size = 32768 * 512;
2290                 mmc->max_blk_size = 32768;
2291                 mmc->max_blk_count = 512;
2292         }
2293
2294         /* Assume card is present initially */
2295         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2296         if (gpio_is_valid(slot->detect_pin)) {
2297                 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2298                                       "mmc_detect")) {
2299                         dev_dbg(&mmc->class_dev, "no detect pin available\n");
2300                         slot->detect_pin = -EBUSY;
2301                 } else if (gpio_get_value(slot->detect_pin) ^
2302                                 slot->detect_is_active_high) {
2303                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2304                 }
2305         }
2306
2307         if (!gpio_is_valid(slot->detect_pin)) {
2308                 if (slot_data->non_removable)
2309                         mmc->caps |= MMC_CAP_NONREMOVABLE;
2310                 else
2311                         mmc->caps |= MMC_CAP_NEEDS_POLL;
2312         }
2313
2314         if (gpio_is_valid(slot->wp_pin)) {
2315                 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2316                                       "mmc_wp")) {
2317                         dev_dbg(&mmc->class_dev, "no WP pin available\n");
2318                         slot->wp_pin = -EBUSY;
2319                 }
2320         }
2321
2322         host->slot[id] = slot;
2323         mmc_regulator_get_supply(mmc);
2324         mmc_add_host(mmc);
2325
2326         if (gpio_is_valid(slot->detect_pin)) {
2327                 int ret;
2328
2329                 timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2330
2331                 ret = request_irq(gpio_to_irq(slot->detect_pin),
2332                                 atmci_detect_interrupt,
2333                                 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2334                                 "mmc-detect", slot);
2335                 if (ret) {
2336                         dev_dbg(&mmc->class_dev,
2337                                 "could not request IRQ %d for detect pin\n",
2338                                 gpio_to_irq(slot->detect_pin));
2339                         slot->detect_pin = -EBUSY;
2340                 }
2341         }
2342
2343         atmci_init_debugfs(slot);
2344
2345         return 0;
2346 }
2347
2348 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2349                 unsigned int id)
2350 {
2351         /* Debugfs stuff is cleaned up by mmc core */
2352
2353         set_bit(ATMCI_SHUTDOWN, &slot->flags);
2354         smp_wmb();
2355
2356         mmc_remove_host(slot->mmc);
2357
2358         if (gpio_is_valid(slot->detect_pin)) {
2359                 int pin = slot->detect_pin;
2360
2361                 free_irq(gpio_to_irq(pin), slot);
2362                 del_timer_sync(&slot->detect_timer);
2363         }
2364
2365         slot->host->slot[id] = NULL;
2366         mmc_free_host(slot->mmc);
2367 }
2368
2369 static int atmci_configure_dma(struct atmel_mci *host)
2370 {
2371         host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
2372                                                         "rxtx");
2373
2374         if (PTR_ERR(host->dma.chan) == -ENODEV) {
2375                 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2376                 dma_cap_mask_t mask;
2377
2378                 if (!pdata || !pdata->dma_filter)
2379                         return -ENODEV;
2380
2381                 dma_cap_zero(mask);
2382                 dma_cap_set(DMA_SLAVE, mask);
2383
2384                 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2385                                                      pdata->dma_slave);
2386                 if (!host->dma.chan)
2387                         host->dma.chan = ERR_PTR(-ENODEV);
2388         }
2389
2390         if (IS_ERR(host->dma.chan))
2391                 return PTR_ERR(host->dma.chan);
2392
2393         dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2394                  dma_chan_name(host->dma.chan));
2395
2396         host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2397         host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2398         host->dma_conf.src_maxburst = 1;
2399         host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2400         host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2401         host->dma_conf.dst_maxburst = 1;
2402         host->dma_conf.device_fc = false;
2403
2404         return 0;
2405 }
2406
2407 /*
2408  * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2409  * HSMCI provides DMA support and a new config register but no more supports
2410  * PDC.
2411  */
2412 static void atmci_get_cap(struct atmel_mci *host)
2413 {
2414         unsigned int version;
2415
2416         version = atmci_get_version(host);
2417         dev_info(&host->pdev->dev,
2418                         "version: 0x%x\n", version);
2419
2420         host->caps.has_dma_conf_reg = 0;
2421         host->caps.has_pdc = 1;
2422         host->caps.has_cfg_reg = 0;
2423         host->caps.has_cstor_reg = 0;
2424         host->caps.has_highspeed = 0;
2425         host->caps.has_rwproof = 0;
2426         host->caps.has_odd_clk_div = 0;
2427         host->caps.has_bad_data_ordering = 1;
2428         host->caps.need_reset_after_xfer = 1;
2429         host->caps.need_blksz_mul_4 = 1;
2430         host->caps.need_notbusy_for_read_ops = 0;
2431
2432         /* keep only major version number */
2433         switch (version & 0xf00) {
2434         case 0x600:
2435         case 0x500:
2436                 host->caps.has_odd_clk_div = 1;
2437         case 0x400:
2438         case 0x300:
2439                 host->caps.has_dma_conf_reg = 1;
2440                 host->caps.has_pdc = 0;
2441                 host->caps.has_cfg_reg = 1;
2442                 host->caps.has_cstor_reg = 1;
2443                 host->caps.has_highspeed = 1;
2444         case 0x200:
2445                 host->caps.has_rwproof = 1;
2446                 host->caps.need_blksz_mul_4 = 0;
2447                 host->caps.need_notbusy_for_read_ops = 1;
2448         case 0x100:
2449                 host->caps.has_bad_data_ordering = 0;
2450                 host->caps.need_reset_after_xfer = 0;
2451         case 0x0:
2452                 break;
2453         default:
2454                 host->caps.has_pdc = 0;
2455                 dev_warn(&host->pdev->dev,
2456                                 "Unmanaged mci version, set minimum capabilities\n");
2457                 break;
2458         }
2459 }
2460
2461 static int atmci_probe(struct platform_device *pdev)
2462 {
2463         struct mci_platform_data        *pdata;
2464         struct atmel_mci                *host;
2465         struct resource                 *regs;
2466         unsigned int                    nr_slots;
2467         int                             irq;
2468         int                             ret, i;
2469
2470         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2471         if (!regs)
2472                 return -ENXIO;
2473         pdata = pdev->dev.platform_data;
2474         if (!pdata) {
2475                 pdata = atmci_of_init(pdev);
2476                 if (IS_ERR(pdata)) {
2477                         dev_err(&pdev->dev, "platform data not available\n");
2478                         return PTR_ERR(pdata);
2479                 }
2480         }
2481
2482         irq = platform_get_irq(pdev, 0);
2483         if (irq < 0)
2484                 return irq;
2485
2486         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2487         if (!host)
2488                 return -ENOMEM;
2489
2490         host->pdev = pdev;
2491         spin_lock_init(&host->lock);
2492         INIT_LIST_HEAD(&host->queue);
2493
2494         host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2495         if (IS_ERR(host->mck))
2496                 return PTR_ERR(host->mck);
2497
2498         host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2499         if (!host->regs)
2500                 return -ENOMEM;
2501
2502         ret = clk_prepare_enable(host->mck);
2503         if (ret)
2504                 return ret;
2505
2506         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2507         host->bus_hz = clk_get_rate(host->mck);
2508
2509         host->mapbase = regs->start;
2510
2511         tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2512
2513         ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2514         if (ret) {
2515                 clk_disable_unprepare(host->mck);
2516                 return ret;
2517         }
2518
2519         /* Get MCI capabilities and set operations according to it */
2520         atmci_get_cap(host);
2521         ret = atmci_configure_dma(host);
2522         if (ret == -EPROBE_DEFER)
2523                 goto err_dma_probe_defer;
2524         if (ret == 0) {
2525                 host->prepare_data = &atmci_prepare_data_dma;
2526                 host->submit_data = &atmci_submit_data_dma;
2527                 host->stop_transfer = &atmci_stop_transfer_dma;
2528         } else if (host->caps.has_pdc) {
2529                 dev_info(&pdev->dev, "using PDC\n");
2530                 host->prepare_data = &atmci_prepare_data_pdc;
2531                 host->submit_data = &atmci_submit_data_pdc;
2532                 host->stop_transfer = &atmci_stop_transfer_pdc;
2533         } else {
2534                 dev_info(&pdev->dev, "using PIO\n");
2535                 host->prepare_data = &atmci_prepare_data;
2536                 host->submit_data = &atmci_submit_data;
2537                 host->stop_transfer = &atmci_stop_transfer;
2538         }
2539
2540         platform_set_drvdata(pdev, host);
2541
2542         timer_setup(&host->timer, atmci_timeout_timer, 0);
2543
2544         pm_runtime_get_noresume(&pdev->dev);
2545         pm_runtime_set_active(&pdev->dev);
2546         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2547         pm_runtime_use_autosuspend(&pdev->dev);
2548         pm_runtime_enable(&pdev->dev);
2549
2550         /* We need at least one slot to succeed */
2551         nr_slots = 0;
2552         ret = -ENODEV;
2553         if (pdata->slot[0].bus_width) {
2554                 ret = atmci_init_slot(host, &pdata->slot[0],
2555                                 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2556                 if (!ret) {
2557                         nr_slots++;
2558                         host->buf_size = host->slot[0]->mmc->max_req_size;
2559                 }
2560         }
2561         if (pdata->slot[1].bus_width) {
2562                 ret = atmci_init_slot(host, &pdata->slot[1],
2563                                 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2564                 if (!ret) {
2565                         nr_slots++;
2566                         if (host->slot[1]->mmc->max_req_size > host->buf_size)
2567                                 host->buf_size =
2568                                         host->slot[1]->mmc->max_req_size;
2569                 }
2570         }
2571
2572         if (!nr_slots) {
2573                 dev_err(&pdev->dev, "init failed: no slot defined\n");
2574                 goto err_init_slot;
2575         }
2576
2577         if (!host->caps.has_rwproof) {
2578                 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2579                                                   &host->buf_phys_addr,
2580                                                   GFP_KERNEL);
2581                 if (!host->buffer) {
2582                         ret = -ENOMEM;
2583                         dev_err(&pdev->dev, "buffer allocation failed\n");
2584                         goto err_dma_alloc;
2585                 }
2586         }
2587
2588         dev_info(&pdev->dev,
2589                         "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2590                         host->mapbase, irq, nr_slots);
2591
2592         pm_runtime_mark_last_busy(&host->pdev->dev);
2593         pm_runtime_put_autosuspend(&pdev->dev);
2594
2595         return 0;
2596
2597 err_dma_alloc:
2598         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2599                 if (host->slot[i])
2600                         atmci_cleanup_slot(host->slot[i], i);
2601         }
2602 err_init_slot:
2603         clk_disable_unprepare(host->mck);
2604
2605         pm_runtime_disable(&pdev->dev);
2606         pm_runtime_put_noidle(&pdev->dev);
2607
2608         del_timer_sync(&host->timer);
2609         if (!IS_ERR(host->dma.chan))
2610                 dma_release_channel(host->dma.chan);
2611 err_dma_probe_defer:
2612         free_irq(irq, host);
2613         return ret;
2614 }
2615
2616 static int atmci_remove(struct platform_device *pdev)
2617 {
2618         struct atmel_mci        *host = platform_get_drvdata(pdev);
2619         unsigned int            i;
2620
2621         pm_runtime_get_sync(&pdev->dev);
2622
2623         if (host->buffer)
2624                 dma_free_coherent(&pdev->dev, host->buf_size,
2625                                   host->buffer, host->buf_phys_addr);
2626
2627         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2628                 if (host->slot[i])
2629                         atmci_cleanup_slot(host->slot[i], i);
2630         }
2631
2632         atmci_writel(host, ATMCI_IDR, ~0UL);
2633         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2634         atmci_readl(host, ATMCI_SR);
2635
2636         del_timer_sync(&host->timer);
2637         if (!IS_ERR(host->dma.chan))
2638                 dma_release_channel(host->dma.chan);
2639
2640         free_irq(platform_get_irq(pdev, 0), host);
2641
2642         clk_disable_unprepare(host->mck);
2643
2644         pm_runtime_disable(&pdev->dev);
2645         pm_runtime_put_noidle(&pdev->dev);
2646
2647         return 0;
2648 }
2649
2650 #ifdef CONFIG_PM
2651 static int atmci_runtime_suspend(struct device *dev)
2652 {
2653         struct atmel_mci *host = dev_get_drvdata(dev);
2654
2655         clk_disable_unprepare(host->mck);
2656
2657         pinctrl_pm_select_sleep_state(dev);
2658
2659         return 0;
2660 }
2661
2662 static int atmci_runtime_resume(struct device *dev)
2663 {
2664         struct atmel_mci *host = dev_get_drvdata(dev);
2665
2666         pinctrl_pm_select_default_state(dev);
2667
2668         return clk_prepare_enable(host->mck);
2669 }
2670 #endif
2671
2672 static const struct dev_pm_ops atmci_dev_pm_ops = {
2673         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2674                                 pm_runtime_force_resume)
2675         SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2676 };
2677
2678 static struct platform_driver atmci_driver = {
2679         .probe          = atmci_probe,
2680         .remove         = atmci_remove,
2681         .driver         = {
2682                 .name           = "atmel_mci",
2683                 .of_match_table = of_match_ptr(atmci_dt_ids),
2684                 .pm             = &atmci_dev_pm_ops,
2685         },
2686 };
2687 module_platform_driver(atmci_driver);
2688
2689 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2690 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2691 MODULE_LICENSE("GPL v2");