2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE | SDMMC_INT_HLE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
59 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
64 #define DESC_RING_BUF_SZ PAGE_SIZE
66 struct idmac_desc_64addr {
67 u32 des0; /* Control Descriptor */
69 u32 des1; /* Reserved */
71 u32 des2; /*Buffer sizes */
72 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
73 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
74 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
76 u32 des3; /* Reserved */
78 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
79 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
81 u32 des6; /* Lower 32-bits of Next Descriptor Address */
82 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86 __le32 des0; /* Control Descriptor */
87 #define IDMAC_DES0_DIC BIT(1)
88 #define IDMAC_DES0_LD BIT(2)
89 #define IDMAC_DES0_FD BIT(3)
90 #define IDMAC_DES0_CH BIT(4)
91 #define IDMAC_DES0_ER BIT(5)
92 #define IDMAC_DES0_CES BIT(30)
93 #define IDMAC_DES0_OWN BIT(31)
95 __le32 des1; /* Buffer sizes */
96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
97 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
99 __le32 des2; /* buffer 1 physical address */
101 __le32 des3; /* buffer 2 physical address */
104 /* Each descriptor can transfer up to 4KB of data in chained mode */
105 #define DW_MCI_DESC_DATA_LENGTH 0x1000
107 static bool dw_mci_reset(struct dw_mci *host);
108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
109 static int dw_mci_card_busy(struct mmc_host *mmc);
110 static int dw_mci_get_cd(struct mmc_host *mmc);
112 #if defined(CONFIG_DEBUG_FS)
113 static int dw_mci_req_show(struct seq_file *s, void *v)
115 struct dw_mci_slot *slot = s->private;
116 struct mmc_request *mrq;
117 struct mmc_command *cmd;
118 struct mmc_command *stop;
119 struct mmc_data *data;
121 /* Make sure we get a consistent snapshot */
122 spin_lock_bh(&slot->host->lock);
132 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
133 cmd->opcode, cmd->arg, cmd->flags,
134 cmd->resp[0], cmd->resp[1], cmd->resp[2],
135 cmd->resp[2], cmd->error);
137 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
138 data->bytes_xfered, data->blocks,
139 data->blksz, data->flags, data->error);
142 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
143 stop->opcode, stop->arg, stop->flags,
144 stop->resp[0], stop->resp[1], stop->resp[2],
145 stop->resp[2], stop->error);
148 spin_unlock_bh(&slot->host->lock);
153 static int dw_mci_req_open(struct inode *inode, struct file *file)
155 return single_open(file, dw_mci_req_show, inode->i_private);
158 static const struct file_operations dw_mci_req_fops = {
159 .owner = THIS_MODULE,
160 .open = dw_mci_req_open,
163 .release = single_release,
166 static int dw_mci_regs_show(struct seq_file *s, void *v)
168 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
169 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
170 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
171 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
172 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
173 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
180 return single_open(file, dw_mci_regs_show, inode->i_private);
183 static const struct file_operations dw_mci_regs_fops = {
184 .owner = THIS_MODULE,
185 .open = dw_mci_regs_open,
188 .release = single_release,
191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
193 struct mmc_host *mmc = slot->mmc;
194 struct dw_mci *host = slot->host;
198 root = mmc->debugfs_root;
202 node = debugfs_create_file("regs", S_IRUSR, root, host,
207 node = debugfs_create_file("req", S_IRUSR, root, slot,
212 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
216 node = debugfs_create_x32("pending_events", S_IRUSR, root,
217 (u32 *)&host->pending_events);
221 node = debugfs_create_x32("completed_events", S_IRUSR, root,
222 (u32 *)&host->completed_events);
229 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
231 #endif /* defined(CONFIG_DEBUG_FS) */
233 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
235 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
237 struct mmc_data *data;
238 struct dw_mci_slot *slot = mmc_priv(mmc);
239 struct dw_mci *host = slot->host;
242 cmd->error = -EINPROGRESS;
245 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
246 cmd->opcode == MMC_GO_IDLE_STATE ||
247 cmd->opcode == MMC_GO_INACTIVE_STATE ||
248 (cmd->opcode == SD_IO_RW_DIRECT &&
249 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
250 cmdr |= SDMMC_CMD_STOP;
251 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
252 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
254 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
257 /* Special bit makes CMD11 not die */
258 cmdr |= SDMMC_CMD_VOLT_SWITCH;
260 /* Change state to continue to handle CMD11 weirdness */
261 WARN_ON(slot->host->state != STATE_SENDING_CMD);
262 slot->host->state = STATE_SENDING_CMD11;
265 * We need to disable low power mode (automatic clock stop)
266 * while doing voltage switch so we don't confuse the card,
267 * since stopping the clock is a specific part of the UHS
268 * voltage change dance.
270 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
271 * unconditionally turned back on in dw_mci_setup_bus() if it's
272 * ever called with a non-zero clock. That shouldn't happen
273 * until the voltage change is all done.
275 clk_en_a = mci_readl(host, CLKENA);
276 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
277 mci_writel(host, CLKENA, clk_en_a);
278 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
279 SDMMC_CMD_PRV_DAT_WAIT, 0);
282 if (cmd->flags & MMC_RSP_PRESENT) {
283 /* We expect a response, so set this bit */
284 cmdr |= SDMMC_CMD_RESP_EXP;
285 if (cmd->flags & MMC_RSP_136)
286 cmdr |= SDMMC_CMD_RESP_LONG;
289 if (cmd->flags & MMC_RSP_CRC)
290 cmdr |= SDMMC_CMD_RESP_CRC;
294 cmdr |= SDMMC_CMD_DAT_EXP;
295 if (data->flags & MMC_DATA_WRITE)
296 cmdr |= SDMMC_CMD_DAT_WR;
299 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
300 cmdr |= SDMMC_CMD_USE_HOLD_REG;
305 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
307 struct mmc_command *stop;
313 stop = &host->stop_abort;
315 memset(stop, 0, sizeof(struct mmc_command));
317 if (cmdr == MMC_READ_SINGLE_BLOCK ||
318 cmdr == MMC_READ_MULTIPLE_BLOCK ||
319 cmdr == MMC_WRITE_BLOCK ||
320 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
321 cmdr == MMC_SEND_TUNING_BLOCK ||
322 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
323 stop->opcode = MMC_STOP_TRANSMISSION;
325 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
326 } else if (cmdr == SD_IO_RW_EXTENDED) {
327 stop->opcode = SD_IO_RW_DIRECT;
328 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
329 ((cmd->arg >> 28) & 0x7);
330 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
335 cmdr = stop->opcode | SDMMC_CMD_STOP |
336 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
341 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
343 unsigned long timeout = jiffies + msecs_to_jiffies(500);
346 * Databook says that before issuing a new data transfer command
347 * we need to check to see if the card is busy. Data transfer commands
348 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
350 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
353 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
354 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
355 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
356 if (time_after(jiffies, timeout)) {
357 /* Command will fail; we'll pass error then */
358 dev_err(host->dev, "Busy; trying anyway\n");
366 static void dw_mci_start_command(struct dw_mci *host,
367 struct mmc_command *cmd, u32 cmd_flags)
371 "start command: ARGR=0x%08x CMDR=0x%08x\n",
372 cmd->arg, cmd_flags);
374 mci_writel(host, CMDARG, cmd->arg);
375 wmb(); /* drain writebuffer */
376 dw_mci_wait_while_busy(host, cmd_flags);
378 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
381 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
383 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
385 dw_mci_start_command(host, stop, host->stop_cmdr);
388 /* DMA interface functions */
389 static void dw_mci_stop_dma(struct dw_mci *host)
391 if (host->using_dma) {
392 host->dma_ops->stop(host);
393 host->dma_ops->cleanup(host);
396 /* Data transfer was stopped by the interrupt handler */
397 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
400 static int dw_mci_get_dma_dir(struct mmc_data *data)
402 if (data->flags & MMC_DATA_WRITE)
403 return DMA_TO_DEVICE;
405 return DMA_FROM_DEVICE;
408 static void dw_mci_dma_cleanup(struct dw_mci *host)
410 struct mmc_data *data = host->data;
413 if (!data->host_cookie)
414 dma_unmap_sg(host->dev,
417 dw_mci_get_dma_dir(data));
420 static void dw_mci_idmac_reset(struct dw_mci *host)
422 u32 bmod = mci_readl(host, BMOD);
423 /* Software reset of DMA */
424 bmod |= SDMMC_IDMAC_SWRESET;
425 mci_writel(host, BMOD, bmod);
428 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
432 /* Disable and reset the IDMAC interface */
433 temp = mci_readl(host, CTRL);
434 temp &= ~SDMMC_CTRL_USE_IDMAC;
435 temp |= SDMMC_CTRL_DMA_RESET;
436 mci_writel(host, CTRL, temp);
438 /* Stop the IDMAC running */
439 temp = mci_readl(host, BMOD);
440 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
441 temp |= SDMMC_IDMAC_SWRESET;
442 mci_writel(host, BMOD, temp);
445 static void dw_mci_dmac_complete_dma(void *arg)
447 struct dw_mci *host = arg;
448 struct mmc_data *data = host->data;
450 dev_vdbg(host->dev, "DMA complete\n");
452 if ((host->use_dma == TRANS_MODE_EDMAC) &&
453 data && (data->flags & MMC_DATA_READ))
454 /* Invalidate cache after read */
455 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
460 host->dma_ops->cleanup(host);
463 * If the card was removed, data will be NULL. No point in trying to
464 * send the stop command or waiting for NBUSY in this case.
467 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
468 tasklet_schedule(&host->tasklet);
472 static int dw_mci_idmac_init(struct dw_mci *host)
476 if (host->dma_64bit_address == 1) {
477 struct idmac_desc_64addr *p;
478 /* Number of descriptors in the ring buffer */
480 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
482 /* Forward link the descriptor list */
483 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
485 p->des6 = (host->sg_dma +
486 (sizeof(struct idmac_desc_64addr) *
487 (i + 1))) & 0xffffffff;
489 p->des7 = (u64)(host->sg_dma +
490 (sizeof(struct idmac_desc_64addr) *
492 /* Initialize reserved and buffer size fields to "0" */
498 /* Set the last descriptor as the end-of-ring descriptor */
499 p->des6 = host->sg_dma & 0xffffffff;
500 p->des7 = (u64)host->sg_dma >> 32;
501 p->des0 = IDMAC_DES0_ER;
504 struct idmac_desc *p;
505 /* Number of descriptors in the ring buffer */
507 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
509 /* Forward link the descriptor list */
510 for (i = 0, p = host->sg_cpu;
511 i < host->ring_size - 1;
513 p->des3 = cpu_to_le32(host->sg_dma +
514 (sizeof(struct idmac_desc) * (i + 1)));
518 /* Set the last descriptor as the end-of-ring descriptor */
519 p->des3 = cpu_to_le32(host->sg_dma);
520 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
523 dw_mci_idmac_reset(host);
525 if (host->dma_64bit_address == 1) {
526 /* Mask out interrupts - get Tx & Rx complete only */
527 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
528 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
529 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
531 /* Set the descriptor base address */
532 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
533 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
536 /* Mask out interrupts - get Tx & Rx complete only */
537 mci_writel(host, IDSTS, IDMAC_INT_CLR);
538 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
539 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
541 /* Set the descriptor base address */
542 mci_writel(host, DBADDR, host->sg_dma);
548 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
549 struct mmc_data *data,
552 unsigned int desc_len;
553 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
554 unsigned long timeout;
557 desc_first = desc_last = desc = host->sg_cpu;
559 for (i = 0; i < sg_len; i++) {
560 unsigned int length = sg_dma_len(&data->sg[i]);
562 u64 mem_addr = sg_dma_address(&data->sg[i]);
564 for ( ; length ; desc++) {
565 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
566 length : DW_MCI_DESC_DATA_LENGTH;
571 * Wait for the former clear OWN bit operation
572 * of IDMAC to make sure that this descriptor
573 * isn't still owned by IDMAC as IDMAC's write
574 * ops and CPU's read ops are asynchronous.
576 timeout = jiffies + msecs_to_jiffies(100);
577 while (readl(&desc->des0) & IDMAC_DES0_OWN) {
578 if (time_after(jiffies, timeout))
584 * Set the OWN bit and disable interrupts
585 * for this descriptor
587 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
591 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
593 /* Physical address to DMA to/from */
594 desc->des4 = mem_addr & 0xffffffff;
595 desc->des5 = mem_addr >> 32;
597 /* Update physical address for the next desc */
598 mem_addr += desc_len;
600 /* Save pointer to the last descriptor */
605 /* Set first descriptor */
606 desc_first->des0 |= IDMAC_DES0_FD;
608 /* Set last descriptor */
609 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
610 desc_last->des0 |= IDMAC_DES0_LD;
614 /* restore the descriptor chain as it's polluted */
615 dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
616 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
617 dw_mci_idmac_init(host);
622 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
623 struct mmc_data *data,
626 unsigned int desc_len;
627 struct idmac_desc *desc_first, *desc_last, *desc;
628 unsigned long timeout;
631 desc_first = desc_last = desc = host->sg_cpu;
633 for (i = 0; i < sg_len; i++) {
634 unsigned int length = sg_dma_len(&data->sg[i]);
636 u32 mem_addr = sg_dma_address(&data->sg[i]);
638 for ( ; length ; desc++) {
639 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
640 length : DW_MCI_DESC_DATA_LENGTH;
645 * Wait for the former clear OWN bit operation
646 * of IDMAC to make sure that this descriptor
647 * isn't still owned by IDMAC as IDMAC's write
648 * ops and CPU's read ops are asynchronous.
650 timeout = jiffies + msecs_to_jiffies(100);
651 while (readl(&desc->des0) &
652 cpu_to_le32(IDMAC_DES0_OWN)) {
653 if (time_after(jiffies, timeout))
659 * Set the OWN bit and disable interrupts
660 * for this descriptor
662 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
667 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
669 /* Physical address to DMA to/from */
670 desc->des2 = cpu_to_le32(mem_addr);
672 /* Update physical address for the next desc */
673 mem_addr += desc_len;
675 /* Save pointer to the last descriptor */
680 /* Set first descriptor */
681 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
683 /* Set last descriptor */
684 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
686 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
690 /* restore the descriptor chain as it's polluted */
691 dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
692 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
693 dw_mci_idmac_init(host);
697 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
702 if (host->dma_64bit_address == 1)
703 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
705 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
710 /* drain writebuffer */
713 /* Make sure to reset DMA in case we did PIO before this */
714 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
715 dw_mci_idmac_reset(host);
717 /* Select IDMAC interface */
718 temp = mci_readl(host, CTRL);
719 temp |= SDMMC_CTRL_USE_IDMAC;
720 mci_writel(host, CTRL, temp);
722 /* drain writebuffer */
725 /* Enable the IDMAC */
726 temp = mci_readl(host, BMOD);
727 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
728 mci_writel(host, BMOD, temp);
730 /* Start it running */
731 mci_writel(host, PLDMND, 1);
737 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
738 .init = dw_mci_idmac_init,
739 .start = dw_mci_idmac_start_dma,
740 .stop = dw_mci_idmac_stop_dma,
741 .complete = dw_mci_dmac_complete_dma,
742 .cleanup = dw_mci_dma_cleanup,
745 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
747 dmaengine_terminate_async(host->dms->ch);
750 static int dw_mci_edmac_start_dma(struct dw_mci *host,
753 struct dma_slave_config cfg;
754 struct dma_async_tx_descriptor *desc = NULL;
755 struct scatterlist *sgl = host->data->sg;
756 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
757 u32 sg_elems = host->data->sg_len;
759 u32 fifo_offset = host->fifo_reg - host->regs;
762 /* Set external dma config: burst size, burst width */
763 cfg.dst_addr = host->phy_regs + fifo_offset;
764 cfg.src_addr = cfg.dst_addr;
765 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
766 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
768 /* Match burst msize with external dma config */
769 fifoth_val = mci_readl(host, FIFOTH);
770 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
771 cfg.src_maxburst = cfg.dst_maxburst;
773 if (host->data->flags & MMC_DATA_WRITE)
774 cfg.direction = DMA_MEM_TO_DEV;
776 cfg.direction = DMA_DEV_TO_MEM;
778 ret = dmaengine_slave_config(host->dms->ch, &cfg);
780 dev_err(host->dev, "Failed to config edmac.\n");
784 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
785 sg_len, cfg.direction,
786 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
788 dev_err(host->dev, "Can't prepare slave sg.\n");
792 /* Set dw_mci_dmac_complete_dma as callback */
793 desc->callback = dw_mci_dmac_complete_dma;
794 desc->callback_param = (void *)host;
795 dmaengine_submit(desc);
797 /* Flush cache before write */
798 if (host->data->flags & MMC_DATA_WRITE)
799 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
800 sg_elems, DMA_TO_DEVICE);
802 dma_async_issue_pending(host->dms->ch);
807 static int dw_mci_edmac_init(struct dw_mci *host)
809 /* Request external dma channel */
810 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
814 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
815 if (!host->dms->ch) {
816 dev_err(host->dev, "Failed to get external DMA channel.\n");
825 static void dw_mci_edmac_exit(struct dw_mci *host)
829 dma_release_channel(host->dms->ch);
830 host->dms->ch = NULL;
837 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
838 .init = dw_mci_edmac_init,
839 .exit = dw_mci_edmac_exit,
840 .start = dw_mci_edmac_start_dma,
841 .stop = dw_mci_edmac_stop_dma,
842 .complete = dw_mci_dmac_complete_dma,
843 .cleanup = dw_mci_dma_cleanup,
846 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
847 struct mmc_data *data,
850 struct scatterlist *sg;
851 unsigned int i, sg_len;
853 if (!next && data->host_cookie)
854 return data->host_cookie;
857 * We don't do DMA on "complex" transfers, i.e. with
858 * non-word-aligned buffers or lengths. Also, we don't bother
859 * with all the DMA setup overhead for short transfers.
861 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
867 for_each_sg(data->sg, sg, data->sg_len, i) {
868 if (sg->offset & 3 || sg->length & 3)
872 sg_len = dma_map_sg(host->dev,
875 dw_mci_get_dma_dir(data));
880 data->host_cookie = sg_len;
885 static void dw_mci_pre_req(struct mmc_host *mmc,
886 struct mmc_request *mrq,
889 struct dw_mci_slot *slot = mmc_priv(mmc);
890 struct mmc_data *data = mrq->data;
892 if (!slot->host->use_dma || !data)
895 if (data->host_cookie) {
896 data->host_cookie = 0;
900 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
901 data->host_cookie = 0;
904 static void dw_mci_post_req(struct mmc_host *mmc,
905 struct mmc_request *mrq,
908 struct dw_mci_slot *slot = mmc_priv(mmc);
909 struct mmc_data *data = mrq->data;
911 if (!slot->host->use_dma || !data)
914 if (data->host_cookie)
915 dma_unmap_sg(slot->host->dev,
918 dw_mci_get_dma_dir(data));
919 data->host_cookie = 0;
922 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
924 unsigned int blksz = data->blksz;
925 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
926 u32 fifo_width = 1 << host->data_shift;
927 u32 blksz_depth = blksz / fifo_width, fifoth_val;
928 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
929 int idx = ARRAY_SIZE(mszs) - 1;
931 /* pio should ship this scenario */
935 tx_wmark = (host->fifo_depth) / 2;
936 tx_wmark_invers = host->fifo_depth - tx_wmark;
940 * if blksz is not a multiple of the FIFO width
942 if (blksz % fifo_width)
946 if (!((blksz_depth % mszs[idx]) ||
947 (tx_wmark_invers % mszs[idx]))) {
949 rx_wmark = mszs[idx] - 1;
954 * If idx is '0', it won't be tried
955 * Thus, initial values are uesed
958 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
959 mci_writel(host, FIFOTH, fifoth_val);
962 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
964 unsigned int blksz = data->blksz;
965 u32 blksz_depth, fifo_depth;
970 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
971 * in the FIFO region, so we really shouldn't access it).
973 if (host->verid < DW_MMC_240A ||
974 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
978 * Card write Threshold is introduced since 2.80a
979 * It's used when HS400 mode is enabled.
981 if (data->flags & MMC_DATA_WRITE &&
982 !(host->timing != MMC_TIMING_MMC_HS400))
985 if (data->flags & MMC_DATA_WRITE)
986 enable = SDMMC_CARD_WR_THR_EN;
988 enable = SDMMC_CARD_RD_THR_EN;
990 if (host->timing != MMC_TIMING_MMC_HS200 &&
991 host->timing != MMC_TIMING_UHS_SDR104)
994 blksz_depth = blksz / (1 << host->data_shift);
995 fifo_depth = host->fifo_depth;
997 if (blksz_depth > fifo_depth)
1001 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1002 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1003 * Currently just choose blksz.
1006 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1010 mci_writel(host, CDTHRCTL, 0);
1013 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1015 unsigned long irqflags;
1019 host->using_dma = 0;
1021 /* If we don't have a channel, we can't do DMA */
1025 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
1027 host->dma_ops->stop(host);
1031 host->using_dma = 1;
1033 if (host->use_dma == TRANS_MODE_IDMAC)
1035 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1036 (unsigned long)host->sg_cpu,
1037 (unsigned long)host->sg_dma,
1041 * Decide the MSIZE and RX/TX Watermark.
1042 * If current block size is same with previous size,
1043 * no need to update fifoth.
1045 if (host->prev_blksz != data->blksz)
1046 dw_mci_adjust_fifoth(host, data);
1048 /* Enable the DMA interface */
1049 temp = mci_readl(host, CTRL);
1050 temp |= SDMMC_CTRL_DMA_ENABLE;
1051 mci_writel(host, CTRL, temp);
1053 /* Disable RX/TX IRQs, let DMA handle it */
1054 spin_lock_irqsave(&host->irq_lock, irqflags);
1055 temp = mci_readl(host, INTMASK);
1056 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1057 mci_writel(host, INTMASK, temp);
1058 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1060 if (host->dma_ops->start(host, sg_len)) {
1061 host->dma_ops->stop(host);
1062 /* We can't do DMA, try PIO for this one */
1064 "%s: fall back to PIO mode for current transfer\n",
1072 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1074 unsigned long irqflags;
1075 int flags = SG_MITER_ATOMIC;
1078 data->error = -EINPROGRESS;
1080 WARN_ON(host->data);
1084 if (data->flags & MMC_DATA_READ)
1085 host->dir_status = DW_MCI_RECV_STATUS;
1087 host->dir_status = DW_MCI_SEND_STATUS;
1089 dw_mci_ctrl_thld(host, data);
1091 if (dw_mci_submit_data_dma(host, data)) {
1092 if (host->data->flags & MMC_DATA_READ)
1093 flags |= SG_MITER_TO_SG;
1095 flags |= SG_MITER_FROM_SG;
1097 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1098 host->sg = data->sg;
1099 host->part_buf_start = 0;
1100 host->part_buf_count = 0;
1102 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1104 spin_lock_irqsave(&host->irq_lock, irqflags);
1105 temp = mci_readl(host, INTMASK);
1106 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1107 mci_writel(host, INTMASK, temp);
1108 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1110 temp = mci_readl(host, CTRL);
1111 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1112 mci_writel(host, CTRL, temp);
1115 * Use the initial fifoth_val for PIO mode.
1116 * If next issued data may be transfered by DMA mode,
1117 * prev_blksz should be invalidated.
1119 mci_writel(host, FIFOTH, host->fifoth_val);
1120 host->prev_blksz = 0;
1123 * Keep the current block size.
1124 * It will be used to decide whether to update
1125 * fifoth register next time.
1127 host->prev_blksz = data->blksz;
1131 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1133 struct dw_mci *host = slot->host;
1134 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1135 unsigned int cmd_status = 0;
1137 mci_writel(host, CMDARG, arg);
1138 wmb(); /* drain writebuffer */
1139 dw_mci_wait_while_busy(host, cmd);
1140 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1142 while (time_before(jiffies, timeout)) {
1143 cmd_status = mci_readl(host, CMD);
1144 if (!(cmd_status & SDMMC_CMD_START))
1147 dev_err(&slot->mmc->class_dev,
1148 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1149 cmd, arg, cmd_status);
1152 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1154 struct dw_mci *host = slot->host;
1155 unsigned int clock = slot->clock;
1158 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1160 /* We must continue to set bit 28 in CMD until the change is complete */
1161 if (host->state == STATE_WAITING_CMD11_DONE)
1162 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1165 mci_writel(host, CLKENA, 0);
1166 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1167 } else if (clock != host->current_speed || force_clkinit) {
1168 div = host->bus_hz / clock;
1169 if (host->bus_hz % clock && host->bus_hz > clock)
1171 * move the + 1 after the divide to prevent
1172 * over-clocking the card.
1176 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1178 if (clock != slot->__clk_old || force_clkinit)
1179 dev_info(&slot->mmc->class_dev,
1180 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1181 slot->id, host->bus_hz, clock,
1182 div ? ((host->bus_hz / div) >> 1) :
1186 mci_writel(host, CLKENA, 0);
1187 mci_writel(host, CLKSRC, 0);
1190 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1192 /* set clock to desired speed */
1193 mci_writel(host, CLKDIV, div);
1196 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1198 /* enable clock; only low power if no SDIO */
1199 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1200 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1201 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1202 mci_writel(host, CLKENA, clk_en_a);
1205 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1207 /* keep the last clock value that was requested from core */
1208 slot->__clk_old = clock;
1211 host->current_speed = clock;
1213 /* Set the current slot bus width */
1214 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1217 static void __dw_mci_start_request(struct dw_mci *host,
1218 struct dw_mci_slot *slot,
1219 struct mmc_command *cmd)
1221 struct mmc_request *mrq;
1222 struct mmc_data *data;
1227 host->cur_slot = slot;
1230 host->pending_events = 0;
1231 host->completed_events = 0;
1232 host->cmd_status = 0;
1233 host->data_status = 0;
1234 host->dir_status = 0;
1238 mci_writel(host, TMOUT, 0xFFFFFFFF);
1239 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1240 mci_writel(host, BLKSIZ, data->blksz);
1243 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1245 /* this is the first command, send the initialization clock */
1246 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1247 cmdflags |= SDMMC_CMD_INIT;
1250 dw_mci_submit_data(host, data);
1251 wmb(); /* drain writebuffer */
1254 dw_mci_start_command(host, cmd, cmdflags);
1256 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1257 unsigned long irqflags;
1260 * Databook says to fail after 2ms w/ no response, but evidence
1261 * shows that sometimes the cmd11 interrupt takes over 130ms.
1262 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1263 * is just about to roll over.
1265 * We do this whole thing under spinlock and only if the
1266 * command hasn't already completed (indicating the the irq
1267 * already ran so we don't want the timeout).
1269 spin_lock_irqsave(&host->irq_lock, irqflags);
1270 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1271 mod_timer(&host->cmd11_timer,
1272 jiffies + msecs_to_jiffies(500) + 1);
1273 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1277 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1279 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1282 static void dw_mci_start_request(struct dw_mci *host,
1283 struct dw_mci_slot *slot)
1285 struct mmc_request *mrq = slot->mrq;
1286 struct mmc_command *cmd;
1288 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1289 __dw_mci_start_request(host, slot, cmd);
1292 /* must be called with host->lock held */
1293 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1294 struct mmc_request *mrq)
1296 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1301 if (host->state == STATE_WAITING_CMD11_DONE) {
1302 dev_warn(&slot->mmc->class_dev,
1303 "Voltage change didn't complete\n");
1305 * this case isn't expected to happen, so we can
1306 * either crash here or just try to continue on
1307 * in the closest possible state
1309 host->state = STATE_IDLE;
1312 if (host->state == STATE_IDLE) {
1313 host->state = STATE_SENDING_CMD;
1314 dw_mci_start_request(host, slot);
1316 list_add_tail(&slot->queue_node, &host->queue);
1320 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1322 struct dw_mci_slot *slot = mmc_priv(mmc);
1323 struct dw_mci *host = slot->host;
1328 * The check for card presence and queueing of the request must be
1329 * atomic, otherwise the card could be removed in between and the
1330 * request wouldn't fail until another card was inserted.
1333 if (!dw_mci_get_cd(mmc)) {
1334 mrq->cmd->error = -ENOMEDIUM;
1335 mmc_request_done(mmc, mrq);
1339 spin_lock_bh(&host->lock);
1341 dw_mci_queue_request(host, slot, mrq);
1343 spin_unlock_bh(&host->lock);
1346 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1348 struct dw_mci_slot *slot = mmc_priv(mmc);
1349 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1353 switch (ios->bus_width) {
1354 case MMC_BUS_WIDTH_4:
1355 slot->ctype = SDMMC_CTYPE_4BIT;
1357 case MMC_BUS_WIDTH_8:
1358 slot->ctype = SDMMC_CTYPE_8BIT;
1361 /* set default 1 bit mode */
1362 slot->ctype = SDMMC_CTYPE_1BIT;
1365 regs = mci_readl(slot->host, UHS_REG);
1368 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1369 ios->timing == MMC_TIMING_UHS_DDR50 ||
1370 ios->timing == MMC_TIMING_MMC_HS400)
1371 regs |= ((0x1 << slot->id) << 16);
1373 regs &= ~((0x1 << slot->id) << 16);
1375 mci_writel(slot->host, UHS_REG, regs);
1376 slot->host->timing = ios->timing;
1379 * Use mirror of ios->clock to prevent race with mmc
1380 * core ios update when finding the minimum.
1382 slot->clock = ios->clock;
1384 if (drv_data && drv_data->set_ios)
1385 drv_data->set_ios(slot->host, ios);
1387 switch (ios->power_mode) {
1389 if (!IS_ERR(mmc->supply.vmmc)) {
1390 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1393 dev_err(slot->host->dev,
1394 "failed to enable vmmc regulator\n");
1395 /*return, if failed turn on vmmc*/
1399 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1400 regs = mci_readl(slot->host, PWREN);
1401 regs |= (1 << slot->id);
1402 mci_writel(slot->host, PWREN, regs);
1405 if (!slot->host->vqmmc_enabled) {
1406 if (!IS_ERR(mmc->supply.vqmmc)) {
1407 ret = regulator_enable(mmc->supply.vqmmc);
1409 dev_err(slot->host->dev,
1410 "failed to enable vqmmc\n");
1412 slot->host->vqmmc_enabled = true;
1415 /* Keep track so we don't reset again */
1416 slot->host->vqmmc_enabled = true;
1419 /* Reset our state machine after powering on */
1420 dw_mci_ctrl_reset(slot->host,
1421 SDMMC_CTRL_ALL_RESET_FLAGS);
1424 /* Adjust clock / bus width after power is up */
1425 dw_mci_setup_bus(slot, false);
1429 /* Turn clock off before power goes down */
1430 dw_mci_setup_bus(slot, false);
1432 if (!IS_ERR(mmc->supply.vmmc))
1433 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1435 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1436 regulator_disable(mmc->supply.vqmmc);
1437 slot->host->vqmmc_enabled = false;
1439 regs = mci_readl(slot->host, PWREN);
1440 regs &= ~(1 << slot->id);
1441 mci_writel(slot->host, PWREN, regs);
1447 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1448 slot->host->state = STATE_IDLE;
1451 static int dw_mci_card_busy(struct mmc_host *mmc)
1453 struct dw_mci_slot *slot = mmc_priv(mmc);
1457 * Check the busy bit which is low when DAT[3:0]
1458 * (the data lines) are 0000
1460 status = mci_readl(slot->host, STATUS);
1462 return !!(status & SDMMC_STATUS_BUSY);
1465 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1467 struct dw_mci_slot *slot = mmc_priv(mmc);
1468 struct dw_mci *host = slot->host;
1469 const struct dw_mci_drv_data *drv_data = host->drv_data;
1471 u32 v18 = SDMMC_UHS_18V << slot->id;
1474 if (drv_data && drv_data->switch_voltage)
1475 return drv_data->switch_voltage(mmc, ios);
1478 * Program the voltage. Note that some instances of dw_mmc may use
1479 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1480 * does no harm but you need to set the regulator directly. Try both.
1482 uhs = mci_readl(host, UHS_REG);
1483 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1488 if (!IS_ERR(mmc->supply.vqmmc)) {
1489 ret = mmc_regulator_set_vqmmc(mmc, ios);
1492 dev_dbg(&mmc->class_dev,
1493 "Regulator set error %d - %s V\n",
1494 ret, uhs & v18 ? "1.8" : "3.3");
1498 mci_writel(host, UHS_REG, uhs);
1503 static int dw_mci_get_ro(struct mmc_host *mmc)
1506 struct dw_mci_slot *slot = mmc_priv(mmc);
1507 int gpio_ro = mmc_gpio_get_ro(mmc);
1509 /* Use platform get_ro function, else try on board write protect */
1511 read_only = gpio_ro;
1514 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1516 dev_dbg(&mmc->class_dev, "card is %s\n",
1517 read_only ? "read-only" : "read-write");
1522 static int dw_mci_get_cd(struct mmc_host *mmc)
1525 struct dw_mci_slot *slot = mmc_priv(mmc);
1526 struct dw_mci *host = slot->host;
1527 int gpio_cd = mmc_gpio_get_cd(mmc);
1529 /* Use platform get_cd function, else try onboard card detect */
1530 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1532 else if (gpio_cd >= 0)
1535 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1538 spin_lock_bh(&host->lock);
1540 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1541 dev_dbg(&mmc->class_dev, "card is present\n");
1543 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1544 dev_dbg(&mmc->class_dev, "card is not present\n");
1546 spin_unlock_bh(&host->lock);
1551 static void dw_mci_hw_reset(struct mmc_host *mmc)
1553 struct dw_mci_slot *slot = mmc_priv(mmc);
1554 struct dw_mci *host = slot->host;
1557 if (host->use_dma == TRANS_MODE_IDMAC)
1558 dw_mci_idmac_reset(host);
1560 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1561 SDMMC_CTRL_FIFO_RESET))
1565 * According to eMMC spec, card reset procedure:
1566 * tRstW >= 1us: RST_n pulse width
1567 * tRSCA >= 200us: RST_n to Command time
1568 * tRSTH >= 1us: RST_n high period
1570 reset = mci_readl(host, RST_N);
1571 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1572 mci_writel(host, RST_N, reset);
1574 reset |= SDMMC_RST_HWACTIVE << slot->id;
1575 mci_writel(host, RST_N, reset);
1576 usleep_range(200, 300);
1579 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1581 struct dw_mci_slot *slot = mmc_priv(mmc);
1582 struct dw_mci *host = slot->host;
1585 * Low power mode will stop the card clock when idle. According to the
1586 * description of the CLKENA register we should disable low power mode
1587 * for SDIO cards if we need SDIO interrupts to work.
1589 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1590 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1594 clk_en_a_old = mci_readl(host, CLKENA);
1596 if (card->type == MMC_TYPE_SDIO ||
1597 card->type == MMC_TYPE_SD_COMBO) {
1598 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1599 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1601 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1602 clk_en_a = clk_en_a_old | clken_low_pwr;
1605 if (clk_en_a != clk_en_a_old) {
1606 mci_writel(host, CLKENA, clk_en_a);
1607 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1608 SDMMC_CMD_PRV_DAT_WAIT, 0);
1613 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1615 struct dw_mci_slot *slot = mmc_priv(mmc);
1616 struct dw_mci *host = slot->host;
1617 unsigned long irqflags;
1620 spin_lock_irqsave(&host->irq_lock, irqflags);
1622 /* Enable/disable Slot Specific SDIO interrupt */
1623 int_mask = mci_readl(host, INTMASK);
1625 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1627 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1628 mci_writel(host, INTMASK, int_mask);
1630 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1633 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1635 struct dw_mci_slot *slot = mmc_priv(mmc);
1636 struct dw_mci *host = slot->host;
1637 const struct dw_mci_drv_data *drv_data = host->drv_data;
1640 if (drv_data && drv_data->execute_tuning)
1641 err = drv_data->execute_tuning(slot, opcode);
1645 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1646 struct mmc_ios *ios)
1648 struct dw_mci_slot *slot = mmc_priv(mmc);
1649 struct dw_mci *host = slot->host;
1650 const struct dw_mci_drv_data *drv_data = host->drv_data;
1652 if (drv_data && drv_data->prepare_hs400_tuning)
1653 return drv_data->prepare_hs400_tuning(host, ios);
1658 static const struct mmc_host_ops dw_mci_ops = {
1659 .request = dw_mci_request,
1660 .pre_req = dw_mci_pre_req,
1661 .post_req = dw_mci_post_req,
1662 .set_ios = dw_mci_set_ios,
1663 .get_ro = dw_mci_get_ro,
1664 .get_cd = dw_mci_get_cd,
1665 .hw_reset = dw_mci_hw_reset,
1666 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1667 .execute_tuning = dw_mci_execute_tuning,
1668 .card_busy = dw_mci_card_busy,
1669 .start_signal_voltage_switch = dw_mci_switch_voltage,
1670 .init_card = dw_mci_init_card,
1671 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1674 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1675 __releases(&host->lock)
1676 __acquires(&host->lock)
1678 struct dw_mci_slot *slot;
1679 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1681 WARN_ON(host->cmd || host->data);
1683 host->cur_slot->mrq = NULL;
1685 if (!list_empty(&host->queue)) {
1686 slot = list_entry(host->queue.next,
1687 struct dw_mci_slot, queue_node);
1688 list_del(&slot->queue_node);
1689 dev_vdbg(host->dev, "list not empty: %s is next\n",
1690 mmc_hostname(slot->mmc));
1691 host->state = STATE_SENDING_CMD;
1692 dw_mci_start_request(host, slot);
1694 dev_vdbg(host->dev, "list empty\n");
1696 if (host->state == STATE_SENDING_CMD11)
1697 host->state = STATE_WAITING_CMD11_DONE;
1699 host->state = STATE_IDLE;
1702 spin_unlock(&host->lock);
1703 mmc_request_done(prev_mmc, mrq);
1704 spin_lock(&host->lock);
1707 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1709 u32 status = host->cmd_status;
1711 host->cmd_status = 0;
1713 /* Read the response from the card (up to 16 bytes) */
1714 if (cmd->flags & MMC_RSP_PRESENT) {
1715 if (cmd->flags & MMC_RSP_136) {
1716 cmd->resp[3] = mci_readl(host, RESP0);
1717 cmd->resp[2] = mci_readl(host, RESP1);
1718 cmd->resp[1] = mci_readl(host, RESP2);
1719 cmd->resp[0] = mci_readl(host, RESP3);
1721 cmd->resp[0] = mci_readl(host, RESP0);
1728 if (status & SDMMC_INT_RTO)
1729 cmd->error = -ETIMEDOUT;
1730 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1731 cmd->error = -EILSEQ;
1732 else if (status & SDMMC_INT_RESP_ERR)
1740 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1742 u32 status = host->data_status;
1744 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1745 if (status & SDMMC_INT_DRTO) {
1746 data->error = -ETIMEDOUT;
1747 } else if (status & SDMMC_INT_DCRC) {
1748 data->error = -EILSEQ;
1749 } else if (status & SDMMC_INT_EBE) {
1750 if (host->dir_status ==
1751 DW_MCI_SEND_STATUS) {
1753 * No data CRC status was returned.
1754 * The number of bytes transferred
1755 * will be exaggerated in PIO mode.
1757 data->bytes_xfered = 0;
1758 data->error = -ETIMEDOUT;
1759 } else if (host->dir_status ==
1760 DW_MCI_RECV_STATUS) {
1761 data->error = -EILSEQ;
1764 /* SDMMC_INT_SBE is included */
1765 data->error = -EILSEQ;
1768 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1771 * After an error, there may be data lingering
1776 data->bytes_xfered = data->blocks * data->blksz;
1783 static void dw_mci_set_drto(struct dw_mci *host)
1785 unsigned int drto_clks;
1786 unsigned int drto_ms;
1788 drto_clks = mci_readl(host, TMOUT) >> 8;
1789 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1791 /* add a bit spare time */
1794 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1797 static void dw_mci_tasklet_func(unsigned long priv)
1799 struct dw_mci *host = (struct dw_mci *)priv;
1800 struct mmc_data *data;
1801 struct mmc_command *cmd;
1802 struct mmc_request *mrq;
1803 enum dw_mci_state state;
1804 enum dw_mci_state prev_state;
1807 spin_lock(&host->lock);
1809 state = host->state;
1818 case STATE_WAITING_CMD11_DONE:
1821 case STATE_SENDING_CMD11:
1822 case STATE_SENDING_CMD:
1823 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1824 &host->pending_events))
1829 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1830 err = dw_mci_command_complete(host, cmd);
1831 if (cmd == mrq->sbc && !err) {
1832 prev_state = state = STATE_SENDING_CMD;
1833 __dw_mci_start_request(host, host->cur_slot,
1838 if (cmd->data && err) {
1840 * During UHS tuning sequence, sending the stop
1841 * command after the response CRC error would
1842 * throw the system into a confused state
1843 * causing all future tuning phases to report
1846 * In such case controller will move into a data
1847 * transfer state after a response error or
1848 * response CRC error. Let's let that finish
1849 * before trying to send a stop, so we'll go to
1850 * STATE_SENDING_DATA.
1852 * Although letting the data transfer take place
1853 * will waste a bit of time (we already know
1854 * the command was bad), it can't cause any
1855 * errors since it's possible it would have
1856 * taken place anyway if this tasklet got
1857 * delayed. Allowing the transfer to take place
1858 * avoids races and keeps things simple.
1860 if ((err != -ETIMEDOUT) &&
1861 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1862 state = STATE_SENDING_DATA;
1866 dw_mci_stop_dma(host);
1867 send_stop_abort(host, data);
1868 state = STATE_SENDING_STOP;
1872 if (!cmd->data || err) {
1873 dw_mci_request_end(host, mrq);
1877 prev_state = state = STATE_SENDING_DATA;
1880 case STATE_SENDING_DATA:
1882 * We could get a data error and never a transfer
1883 * complete so we'd better check for it here.
1885 * Note that we don't really care if we also got a
1886 * transfer complete; stopping the DMA and sending an
1889 if (test_and_clear_bit(EVENT_DATA_ERROR,
1890 &host->pending_events)) {
1891 dw_mci_stop_dma(host);
1893 !(host->data_status & (SDMMC_INT_DRTO |
1895 send_stop_abort(host, data);
1896 state = STATE_DATA_ERROR;
1900 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1901 &host->pending_events)) {
1903 * If all data-related interrupts don't come
1904 * within the given time in reading data state.
1906 if (host->dir_status == DW_MCI_RECV_STATUS)
1907 dw_mci_set_drto(host);
1911 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1914 * Handle an EVENT_DATA_ERROR that might have shown up
1915 * before the transfer completed. This might not have
1916 * been caught by the check above because the interrupt
1917 * could have gone off between the previous check and
1918 * the check for transfer complete.
1920 * Technically this ought not be needed assuming we
1921 * get a DATA_COMPLETE eventually (we'll notice the
1922 * error and end the request), but it shouldn't hurt.
1924 * This has the advantage of sending the stop command.
1926 if (test_and_clear_bit(EVENT_DATA_ERROR,
1927 &host->pending_events)) {
1928 dw_mci_stop_dma(host);
1930 !(host->data_status & (SDMMC_INT_DRTO |
1932 send_stop_abort(host, data);
1933 state = STATE_DATA_ERROR;
1936 prev_state = state = STATE_DATA_BUSY;
1940 case STATE_DATA_BUSY:
1941 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1942 &host->pending_events)) {
1944 * If data error interrupt comes but data over
1945 * interrupt doesn't come within the given time.
1946 * in reading data state.
1948 if (host->dir_status == DW_MCI_RECV_STATUS)
1949 dw_mci_set_drto(host);
1954 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1955 err = dw_mci_data_complete(host, data);
1958 if (!data->stop || mrq->sbc) {
1959 if (mrq->sbc && data->stop)
1960 data->stop->error = 0;
1961 dw_mci_request_end(host, mrq);
1965 /* stop command for open-ended transfer*/
1967 send_stop_abort(host, data);
1970 * If we don't have a command complete now we'll
1971 * never get one since we just reset everything;
1972 * better end the request.
1974 * If we do have a command complete we'll fall
1975 * through to the SENDING_STOP command and
1976 * everything will be peachy keen.
1978 if (!test_bit(EVENT_CMD_COMPLETE,
1979 &host->pending_events)) {
1981 dw_mci_request_end(host, mrq);
1987 * If err has non-zero,
1988 * stop-abort command has been already issued.
1990 prev_state = state = STATE_SENDING_STOP;
1994 case STATE_SENDING_STOP:
1995 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1996 &host->pending_events))
1999 /* CMD error in data command */
2000 if (mrq->cmd->error && mrq->data)
2007 dw_mci_command_complete(host, mrq->stop);
2009 host->cmd_status = 0;
2011 dw_mci_request_end(host, mrq);
2014 case STATE_DATA_ERROR:
2015 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2016 &host->pending_events))
2019 state = STATE_DATA_BUSY;
2022 } while (state != prev_state);
2024 host->state = state;
2026 spin_unlock(&host->lock);
2030 /* push final bytes to part_buf, only use during push */
2031 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2033 memcpy((void *)&host->part_buf, buf, cnt);
2034 host->part_buf_count = cnt;
2037 /* append bytes to part_buf, only use during push */
2038 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2040 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2041 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2042 host->part_buf_count += cnt;
2046 /* pull first bytes from part_buf, only use during pull */
2047 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2049 cnt = min_t(int, cnt, host->part_buf_count);
2051 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2053 host->part_buf_count -= cnt;
2054 host->part_buf_start += cnt;
2059 /* pull final bytes from the part_buf, assuming it's just been filled */
2060 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2062 memcpy(buf, &host->part_buf, cnt);
2063 host->part_buf_start = cnt;
2064 host->part_buf_count = (1 << host->data_shift) - cnt;
2067 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2069 struct mmc_data *data = host->data;
2072 /* try and push anything in the part_buf */
2073 if (unlikely(host->part_buf_count)) {
2074 int len = dw_mci_push_part_bytes(host, buf, cnt);
2078 if (host->part_buf_count == 2) {
2079 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2080 host->part_buf_count = 0;
2083 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2084 if (unlikely((unsigned long)buf & 0x1)) {
2086 u16 aligned_buf[64];
2087 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2088 int items = len >> 1;
2090 /* memcpy from input buffer into aligned buffer */
2091 memcpy(aligned_buf, buf, len);
2094 /* push data from aligned buffer into fifo */
2095 for (i = 0; i < items; ++i)
2096 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2103 for (; cnt >= 2; cnt -= 2)
2104 mci_fifo_writew(host->fifo_reg, *pdata++);
2107 /* put anything remaining in the part_buf */
2109 dw_mci_set_part_bytes(host, buf, cnt);
2110 /* Push data if we have reached the expected data length */
2111 if ((data->bytes_xfered + init_cnt) ==
2112 (data->blksz * data->blocks))
2113 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2117 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2119 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2120 if (unlikely((unsigned long)buf & 0x1)) {
2122 /* pull data from fifo into aligned buffer */
2123 u16 aligned_buf[64];
2124 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2125 int items = len >> 1;
2128 for (i = 0; i < items; ++i)
2129 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2130 /* memcpy from aligned buffer into output buffer */
2131 memcpy(buf, aligned_buf, len);
2140 for (; cnt >= 2; cnt -= 2)
2141 *pdata++ = mci_fifo_readw(host->fifo_reg);
2145 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2146 dw_mci_pull_final_bytes(host, buf, cnt);
2150 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2152 struct mmc_data *data = host->data;
2155 /* try and push anything in the part_buf */
2156 if (unlikely(host->part_buf_count)) {
2157 int len = dw_mci_push_part_bytes(host, buf, cnt);
2161 if (host->part_buf_count == 4) {
2162 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2163 host->part_buf_count = 0;
2166 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2167 if (unlikely((unsigned long)buf & 0x3)) {
2169 u32 aligned_buf[32];
2170 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2171 int items = len >> 2;
2173 /* memcpy from input buffer into aligned buffer */
2174 memcpy(aligned_buf, buf, len);
2177 /* push data from aligned buffer into fifo */
2178 for (i = 0; i < items; ++i)
2179 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2186 for (; cnt >= 4; cnt -= 4)
2187 mci_fifo_writel(host->fifo_reg, *pdata++);
2190 /* put anything remaining in the part_buf */
2192 dw_mci_set_part_bytes(host, buf, cnt);
2193 /* Push data if we have reached the expected data length */
2194 if ((data->bytes_xfered + init_cnt) ==
2195 (data->blksz * data->blocks))
2196 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2200 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2202 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2203 if (unlikely((unsigned long)buf & 0x3)) {
2205 /* pull data from fifo into aligned buffer */
2206 u32 aligned_buf[32];
2207 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2208 int items = len >> 2;
2211 for (i = 0; i < items; ++i)
2212 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2213 /* memcpy from aligned buffer into output buffer */
2214 memcpy(buf, aligned_buf, len);
2223 for (; cnt >= 4; cnt -= 4)
2224 *pdata++ = mci_fifo_readl(host->fifo_reg);
2228 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2229 dw_mci_pull_final_bytes(host, buf, cnt);
2233 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2235 struct mmc_data *data = host->data;
2238 /* try and push anything in the part_buf */
2239 if (unlikely(host->part_buf_count)) {
2240 int len = dw_mci_push_part_bytes(host, buf, cnt);
2245 if (host->part_buf_count == 8) {
2246 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2247 host->part_buf_count = 0;
2250 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2251 if (unlikely((unsigned long)buf & 0x7)) {
2253 u64 aligned_buf[16];
2254 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2255 int items = len >> 3;
2257 /* memcpy from input buffer into aligned buffer */
2258 memcpy(aligned_buf, buf, len);
2261 /* push data from aligned buffer into fifo */
2262 for (i = 0; i < items; ++i)
2263 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2270 for (; cnt >= 8; cnt -= 8)
2271 mci_fifo_writeq(host->fifo_reg, *pdata++);
2274 /* put anything remaining in the part_buf */
2276 dw_mci_set_part_bytes(host, buf, cnt);
2277 /* Push data if we have reached the expected data length */
2278 if ((data->bytes_xfered + init_cnt) ==
2279 (data->blksz * data->blocks))
2280 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2284 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2286 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2287 if (unlikely((unsigned long)buf & 0x7)) {
2289 /* pull data from fifo into aligned buffer */
2290 u64 aligned_buf[16];
2291 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2292 int items = len >> 3;
2295 for (i = 0; i < items; ++i)
2296 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2298 /* memcpy from aligned buffer into output buffer */
2299 memcpy(buf, aligned_buf, len);
2308 for (; cnt >= 8; cnt -= 8)
2309 *pdata++ = mci_fifo_readq(host->fifo_reg);
2313 host->part_buf = mci_fifo_readq(host->fifo_reg);
2314 dw_mci_pull_final_bytes(host, buf, cnt);
2318 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2322 /* get remaining partial bytes */
2323 len = dw_mci_pull_part_bytes(host, buf, cnt);
2324 if (unlikely(len == cnt))
2329 /* get the rest of the data */
2330 host->pull_data(host, buf, cnt);
2333 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2335 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2337 unsigned int offset;
2338 struct mmc_data *data = host->data;
2339 int shift = host->data_shift;
2342 unsigned int remain, fcnt;
2345 if (!sg_miter_next(sg_miter))
2348 host->sg = sg_miter->piter.sg;
2349 buf = sg_miter->addr;
2350 remain = sg_miter->length;
2354 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2355 << shift) + host->part_buf_count;
2356 len = min(remain, fcnt);
2359 dw_mci_pull_data(host, (void *)(buf + offset), len);
2360 data->bytes_xfered += len;
2365 sg_miter->consumed = offset;
2366 status = mci_readl(host, MINTSTS);
2367 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2368 /* if the RXDR is ready read again */
2369 } while ((status & SDMMC_INT_RXDR) ||
2370 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2373 if (!sg_miter_next(sg_miter))
2375 sg_miter->consumed = 0;
2377 sg_miter_stop(sg_miter);
2381 sg_miter_stop(sg_miter);
2383 smp_wmb(); /* drain writebuffer */
2384 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2387 static void dw_mci_write_data_pio(struct dw_mci *host)
2389 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2391 unsigned int offset;
2392 struct mmc_data *data = host->data;
2393 int shift = host->data_shift;
2396 unsigned int fifo_depth = host->fifo_depth;
2397 unsigned int remain, fcnt;
2400 if (!sg_miter_next(sg_miter))
2403 host->sg = sg_miter->piter.sg;
2404 buf = sg_miter->addr;
2405 remain = sg_miter->length;
2409 fcnt = ((fifo_depth -
2410 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2411 << shift) - host->part_buf_count;
2412 len = min(remain, fcnt);
2415 host->push_data(host, (void *)(buf + offset), len);
2416 data->bytes_xfered += len;
2421 sg_miter->consumed = offset;
2422 status = mci_readl(host, MINTSTS);
2423 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2424 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2427 if (!sg_miter_next(sg_miter))
2429 sg_miter->consumed = 0;
2431 sg_miter_stop(sg_miter);
2435 sg_miter_stop(sg_miter);
2437 smp_wmb(); /* drain writebuffer */
2438 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2441 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2443 if (!host->cmd_status)
2444 host->cmd_status = status;
2446 smp_wmb(); /* drain writebuffer */
2448 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2449 tasklet_schedule(&host->tasklet);
2452 static void dw_mci_handle_cd(struct dw_mci *host)
2456 for (i = 0; i < host->num_slots; i++) {
2457 struct dw_mci_slot *slot = host->slot[i];
2462 if (slot->mmc->ops->card_event)
2463 slot->mmc->ops->card_event(slot->mmc);
2464 mmc_detect_change(slot->mmc,
2465 msecs_to_jiffies(host->pdata->detect_delay_ms));
2469 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2471 struct dw_mci *host = dev_id;
2475 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2478 /* Check volt switch first, since it can look like an error */
2479 if ((host->state == STATE_SENDING_CMD11) &&
2480 (pending & SDMMC_INT_VOLT_SWITCH)) {
2481 unsigned long irqflags;
2483 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2484 pending &= ~SDMMC_INT_VOLT_SWITCH;
2487 * Hold the lock; we know cmd11_timer can't be kicked
2488 * off after the lock is released, so safe to delete.
2490 spin_lock_irqsave(&host->irq_lock, irqflags);
2491 dw_mci_cmd_interrupt(host, pending);
2492 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2494 del_timer(&host->cmd11_timer);
2497 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2498 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2499 host->cmd_status = pending;
2500 smp_wmb(); /* drain writebuffer */
2501 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2504 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2505 /* if there is an error report DATA_ERROR */
2506 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2507 host->data_status = pending;
2508 smp_wmb(); /* drain writebuffer */
2509 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2510 tasklet_schedule(&host->tasklet);
2513 if (pending & SDMMC_INT_DATA_OVER) {
2514 del_timer(&host->dto_timer);
2516 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2517 if (!host->data_status)
2518 host->data_status = pending;
2519 smp_wmb(); /* drain writebuffer */
2520 if (host->dir_status == DW_MCI_RECV_STATUS) {
2521 if (host->sg != NULL)
2522 dw_mci_read_data_pio(host, true);
2524 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2525 tasklet_schedule(&host->tasklet);
2528 if (pending & SDMMC_INT_RXDR) {
2529 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2530 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2531 dw_mci_read_data_pio(host, false);
2534 if (pending & SDMMC_INT_TXDR) {
2535 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2536 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2537 dw_mci_write_data_pio(host);
2540 if (pending & SDMMC_INT_CMD_DONE) {
2541 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2542 dw_mci_cmd_interrupt(host, pending);
2545 if (pending & SDMMC_INT_CD) {
2546 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2547 dw_mci_handle_cd(host);
2550 /* Handle SDIO Interrupts */
2551 for (i = 0; i < host->num_slots; i++) {
2552 struct dw_mci_slot *slot = host->slot[i];
2557 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2558 mci_writel(host, RINTSTS,
2559 SDMMC_INT_SDIO(slot->sdio_id));
2560 mmc_signal_sdio_irq(slot->mmc);
2566 if (host->use_dma != TRANS_MODE_IDMAC)
2569 /* Handle IDMA interrupts */
2570 if (host->dma_64bit_address == 1) {
2571 pending = mci_readl(host, IDSTS64);
2572 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2573 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2574 SDMMC_IDMAC_INT_RI);
2575 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2576 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2577 host->dma_ops->complete((void *)host);
2580 pending = mci_readl(host, IDSTS);
2581 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2582 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2583 SDMMC_IDMAC_INT_RI);
2584 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2585 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2586 host->dma_ops->complete((void *)host);
2593 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2595 struct mmc_host *mmc;
2596 struct dw_mci_slot *slot;
2597 const struct dw_mci_drv_data *drv_data = host->drv_data;
2601 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2605 slot = mmc_priv(mmc);
2607 slot->sdio_id = host->sdio_id0 + id;
2610 host->slot[id] = slot;
2612 mmc->ops = &dw_mci_ops;
2613 if (of_property_read_u32_array(host->dev->of_node,
2614 "clock-freq-min-max", freq, 2)) {
2615 mmc->f_min = DW_MCI_FREQ_MIN;
2616 mmc->f_max = DW_MCI_FREQ_MAX;
2618 mmc->f_min = freq[0];
2619 mmc->f_max = freq[1];
2622 /*if there are external regulators, get them*/
2623 ret = mmc_regulator_get_supply(mmc);
2624 if (ret == -EPROBE_DEFER)
2625 goto err_host_allocated;
2627 if (!mmc->ocr_avail)
2628 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2630 if (host->pdata->caps)
2631 mmc->caps = host->pdata->caps;
2634 * Support MMC_CAP_ERASE by default.
2635 * It needs to use trim/discard/erase commands.
2637 mmc->caps |= MMC_CAP_ERASE;
2639 if (host->pdata->pm_caps)
2640 mmc->pm_caps = host->pdata->pm_caps;
2642 if (host->dev->of_node) {
2643 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2647 ctrl_id = to_platform_device(host->dev)->id;
2649 if (drv_data && drv_data->caps)
2650 mmc->caps |= drv_data->caps[ctrl_id];
2652 if (host->pdata->caps2)
2653 mmc->caps2 = host->pdata->caps2;
2655 ret = mmc_of_parse(mmc);
2657 goto err_host_allocated;
2659 /* Useful defaults if platform data is unset. */
2660 if (host->use_dma == TRANS_MODE_IDMAC) {
2661 mmc->max_segs = host->ring_size;
2662 mmc->max_blk_size = 65535;
2663 mmc->max_seg_size = 0x1000;
2664 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2665 mmc->max_blk_count = mmc->max_req_size / 512;
2666 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2668 mmc->max_blk_size = 65535;
2669 mmc->max_blk_count = 65535;
2671 mmc->max_blk_size * mmc->max_blk_count;
2672 mmc->max_seg_size = mmc->max_req_size;
2674 /* TRANS_MODE_PIO */
2676 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2677 mmc->max_blk_count = 512;
2678 mmc->max_req_size = mmc->max_blk_size *
2680 mmc->max_seg_size = mmc->max_req_size;
2685 ret = mmc_add_host(mmc);
2687 goto err_host_allocated;
2689 #if defined(CONFIG_DEBUG_FS)
2690 dw_mci_init_debugfs(slot);
2700 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2702 /* Debugfs stuff is cleaned up by mmc core */
2703 mmc_remove_host(slot->mmc);
2704 slot->host->slot[id] = NULL;
2705 mmc_free_host(slot->mmc);
2708 static void dw_mci_init_dma(struct dw_mci *host)
2711 struct device *dev = host->dev;
2712 struct device_node *np = dev->of_node;
2715 * Check tansfer mode from HCON[17:16]
2716 * Clear the ambiguous description of dw_mmc databook:
2717 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2718 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2719 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2720 * 2b'11: Non DW DMA Interface -> pio only
2721 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2722 * simpler request/acknowledge handshake mechanism and both of them
2723 * are regarded as external dma master for dw_mmc.
2725 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2726 if (host->use_dma == DMA_INTERFACE_IDMA) {
2727 host->use_dma = TRANS_MODE_IDMAC;
2728 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2729 host->use_dma == DMA_INTERFACE_GDMA) {
2730 host->use_dma = TRANS_MODE_EDMAC;
2735 /* Determine which DMA interface to use */
2736 if (host->use_dma == TRANS_MODE_IDMAC) {
2738 * Check ADDR_CONFIG bit in HCON to find
2739 * IDMAC address bus width
2741 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2743 if (addr_config == 1) {
2744 /* host supports IDMAC in 64-bit address mode */
2745 host->dma_64bit_address = 1;
2747 "IDMAC supports 64-bit address mode.\n");
2748 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2749 dma_set_coherent_mask(host->dev,
2752 /* host supports IDMAC in 32-bit address mode */
2753 host->dma_64bit_address = 0;
2755 "IDMAC supports 32-bit address mode.\n");
2758 /* Alloc memory for sg translation */
2759 host->sg_cpu = dmam_alloc_coherent(host->dev,
2761 &host->sg_dma, GFP_KERNEL);
2762 if (!host->sg_cpu) {
2764 "%s: could not alloc DMA memory\n",
2769 host->dma_ops = &dw_mci_idmac_ops;
2770 dev_info(host->dev, "Using internal DMA controller.\n");
2772 /* TRANS_MODE_EDMAC: check dma bindings again */
2773 if ((of_property_count_strings(np, "dma-names") < 0) ||
2774 (!of_find_property(np, "dmas", NULL))) {
2777 host->dma_ops = &dw_mci_edmac_ops;
2778 dev_info(host->dev, "Using external DMA controller.\n");
2781 if (host->dma_ops->init && host->dma_ops->start &&
2782 host->dma_ops->stop && host->dma_ops->cleanup) {
2783 if (host->dma_ops->init(host)) {
2784 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2789 dev_err(host->dev, "DMA initialization not found.\n");
2796 dev_info(host->dev, "Using PIO mode.\n");
2797 host->use_dma = TRANS_MODE_PIO;
2800 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2802 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2805 ctrl = mci_readl(host, CTRL);
2807 mci_writel(host, CTRL, ctrl);
2809 /* wait till resets clear */
2811 ctrl = mci_readl(host, CTRL);
2812 if (!(ctrl & reset))
2814 } while (time_before(jiffies, timeout));
2817 "Timeout resetting block (ctrl reset %#x)\n",
2823 static bool dw_mci_reset(struct dw_mci *host)
2825 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2829 * Reseting generates a block interrupt, hence setting
2830 * the scatter-gather pointer to NULL.
2833 sg_miter_stop(&host->sg_miter);
2838 flags |= SDMMC_CTRL_DMA_RESET;
2840 if (dw_mci_ctrl_reset(host, flags)) {
2842 * In all cases we clear the RAWINTS register to clear any
2845 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2847 /* if using dma we wait for dma_req to clear */
2848 if (host->use_dma) {
2849 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2853 status = mci_readl(host, STATUS);
2854 if (!(status & SDMMC_STATUS_DMA_REQ))
2857 } while (time_before(jiffies, timeout));
2859 if (status & SDMMC_STATUS_DMA_REQ) {
2861 "%s: Timeout waiting for dma_req to clear during reset\n",
2866 /* when using DMA next we reset the fifo again */
2867 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2871 /* if the controller reset bit did clear, then set clock regs */
2872 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2874 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2880 if (host->use_dma == TRANS_MODE_IDMAC)
2881 /* It is also recommended that we reset and reprogram idmac */
2882 dw_mci_idmac_reset(host);
2887 /* After a CTRL reset we need to have CIU set clock registers */
2888 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2893 static void dw_mci_cmd11_timer(unsigned long arg)
2895 struct dw_mci *host = (struct dw_mci *)arg;
2897 if (host->state != STATE_SENDING_CMD11) {
2898 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2902 host->cmd_status = SDMMC_INT_RTO;
2903 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2904 tasklet_schedule(&host->tasklet);
2907 static void dw_mci_dto_timer(unsigned long arg)
2909 struct dw_mci *host = (struct dw_mci *)arg;
2911 switch (host->state) {
2912 case STATE_SENDING_DATA:
2913 case STATE_DATA_BUSY:
2915 * If DTO interrupt does NOT come in sending data state,
2916 * we should notify the driver to terminate current transfer
2917 * and report a data timeout to the core.
2919 host->data_status = SDMMC_INT_DRTO;
2920 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2921 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2922 tasklet_schedule(&host->tasklet);
2930 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2932 struct dw_mci_board *pdata;
2933 struct device *dev = host->dev;
2934 struct device_node *np = dev->of_node;
2935 const struct dw_mci_drv_data *drv_data = host->drv_data;
2937 u32 clock_frequency;
2939 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2941 return ERR_PTR(-ENOMEM);
2943 /* find reset controller when exist */
2944 pdata->rstc = devm_reset_control_get_optional(dev, "reset");
2945 if (IS_ERR(pdata->rstc)) {
2946 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2947 return ERR_PTR(-EPROBE_DEFER);
2950 /* find out number of slots supported */
2951 of_property_read_u32(np, "num-slots", &pdata->num_slots);
2953 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2955 "fifo-depth property not found, using value of FIFOTH register as default\n");
2957 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2959 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2960 pdata->bus_hz = clock_frequency;
2962 if (drv_data && drv_data->parse_dt) {
2963 ret = drv_data->parse_dt(host);
2965 return ERR_PTR(ret);
2971 #else /* CONFIG_OF */
2972 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2974 return ERR_PTR(-EINVAL);
2976 #endif /* CONFIG_OF */
2978 static void dw_mci_enable_cd(struct dw_mci *host)
2980 unsigned long irqflags;
2983 struct dw_mci_slot *slot;
2986 * No need for CD if all slots have a non-error GPIO
2987 * as well as broken card detection is found.
2989 for (i = 0; i < host->num_slots; i++) {
2990 slot = host->slot[i];
2991 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2994 if (mmc_gpio_get_cd(slot->mmc) < 0)
2997 if (i == host->num_slots)
3000 spin_lock_irqsave(&host->irq_lock, irqflags);
3001 temp = mci_readl(host, INTMASK);
3002 temp |= SDMMC_INT_CD;
3003 mci_writel(host, INTMASK, temp);
3004 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3007 int dw_mci_probe(struct dw_mci *host)
3009 const struct dw_mci_drv_data *drv_data = host->drv_data;
3010 int width, i, ret = 0;
3015 host->pdata = dw_mci_parse_dt(host);
3016 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3017 return -EPROBE_DEFER;
3018 } else if (IS_ERR(host->pdata)) {
3019 dev_err(host->dev, "platform data not available\n");
3024 host->biu_clk = devm_clk_get(host->dev, "biu");
3025 if (IS_ERR(host->biu_clk)) {
3026 dev_dbg(host->dev, "biu clock not available\n");
3028 ret = clk_prepare_enable(host->biu_clk);
3030 dev_err(host->dev, "failed to enable biu clock\n");
3035 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3036 if (IS_ERR(host->ciu_clk)) {
3037 dev_dbg(host->dev, "ciu clock not available\n");
3038 host->bus_hz = host->pdata->bus_hz;
3040 ret = clk_prepare_enable(host->ciu_clk);
3042 dev_err(host->dev, "failed to enable ciu clock\n");
3046 if (host->pdata->bus_hz) {
3047 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3050 "Unable to set bus rate to %uHz\n",
3051 host->pdata->bus_hz);
3053 host->bus_hz = clk_get_rate(host->ciu_clk);
3056 if (!host->bus_hz) {
3058 "Platform data must supply bus speed\n");
3063 if (drv_data && drv_data->init) {
3064 ret = drv_data->init(host);
3067 "implementation specific init failed\n");
3072 if (!IS_ERR(host->pdata->rstc)) {
3073 reset_control_assert(host->pdata->rstc);
3074 usleep_range(10, 50);
3075 reset_control_deassert(host->pdata->rstc);
3078 setup_timer(&host->cmd11_timer,
3079 dw_mci_cmd11_timer, (unsigned long)host);
3081 setup_timer(&host->dto_timer,
3082 dw_mci_dto_timer, (unsigned long)host);
3084 spin_lock_init(&host->lock);
3085 spin_lock_init(&host->irq_lock);
3086 INIT_LIST_HEAD(&host->queue);
3089 * Get the host data width - this assumes that HCON has been set with
3090 * the correct values.
3092 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3094 host->push_data = dw_mci_push_data16;
3095 host->pull_data = dw_mci_pull_data16;
3097 host->data_shift = 1;
3098 } else if (i == 2) {
3099 host->push_data = dw_mci_push_data64;
3100 host->pull_data = dw_mci_pull_data64;
3102 host->data_shift = 3;
3104 /* Check for a reserved value, and warn if it is */
3106 "HCON reports a reserved host data width!\n"
3107 "Defaulting to 32-bit access.\n");
3108 host->push_data = dw_mci_push_data32;
3109 host->pull_data = dw_mci_pull_data32;
3111 host->data_shift = 2;
3114 /* Reset all blocks */
3115 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3120 host->dma_ops = host->pdata->dma_ops;
3121 dw_mci_init_dma(host);
3123 /* Clear the interrupts for the host controller */
3124 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3125 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3127 /* Put in max timeout */
3128 mci_writel(host, TMOUT, 0xFFFFFFFF);
3131 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3132 * Tx Mark = fifo_size / 2 DMA Size = 8
3134 if (!host->pdata->fifo_depth) {
3136 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3137 * have been overwritten by the bootloader, just like we're
3138 * about to do, so if you know the value for your hardware, you
3139 * should put it in the platform data.
3141 fifo_size = mci_readl(host, FIFOTH);
3142 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3144 fifo_size = host->pdata->fifo_depth;
3146 host->fifo_depth = fifo_size;
3148 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3149 mci_writel(host, FIFOTH, host->fifoth_val);
3151 /* disable clock to CIU */
3152 mci_writel(host, CLKENA, 0);
3153 mci_writel(host, CLKSRC, 0);
3156 * In 2.40a spec, Data offset is changed.
3157 * Need to check the version-id and set data-offset for DATA register.
3159 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3160 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3162 if (host->verid < DW_MMC_240A)
3163 host->fifo_reg = host->regs + DATA_OFFSET;
3165 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3167 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3168 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3169 host->irq_flags, "dw-mci", host);
3173 if (host->pdata->num_slots)
3174 host->num_slots = host->pdata->num_slots;
3176 host->num_slots = 1;
3178 if (host->num_slots < 1 ||
3179 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3181 "Platform data must supply correct num_slots.\n");
3187 * Enable interrupts for command done, data over, data empty,
3188 * receive ready and error such as transmit, receive timeout, crc error
3190 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3191 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3192 DW_MCI_ERROR_FLAGS);
3193 /* Enable mci interrupt */
3194 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3197 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3198 host->irq, width, fifo_size);
3200 /* We need at least one slot to succeed */
3201 for (i = 0; i < host->num_slots; i++) {
3202 ret = dw_mci_init_slot(host, i);
3204 dev_dbg(host->dev, "slot %d init failed\n", i);
3210 dev_info(host->dev, "%d slots initialized\n", init_slots);
3213 "attempted to initialize %d slots, but failed on all\n",
3218 /* Now that slots are all setup, we can enable card detect */
3219 dw_mci_enable_cd(host);
3224 if (host->use_dma && host->dma_ops->exit)
3225 host->dma_ops->exit(host);
3227 if (!IS_ERR(host->pdata->rstc))
3228 reset_control_assert(host->pdata->rstc);
3231 clk_disable_unprepare(host->ciu_clk);
3234 clk_disable_unprepare(host->biu_clk);
3238 EXPORT_SYMBOL(dw_mci_probe);
3240 void dw_mci_remove(struct dw_mci *host)
3244 for (i = 0; i < host->num_slots; i++) {
3245 dev_dbg(host->dev, "remove slot %d\n", i);
3247 dw_mci_cleanup_slot(host->slot[i], i);
3250 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3251 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3253 /* disable clock to CIU */
3254 mci_writel(host, CLKENA, 0);
3255 mci_writel(host, CLKSRC, 0);
3257 if (host->use_dma && host->dma_ops->exit)
3258 host->dma_ops->exit(host);
3260 if (!IS_ERR(host->pdata->rstc))
3261 reset_control_assert(host->pdata->rstc);
3263 clk_disable_unprepare(host->ciu_clk);
3264 clk_disable_unprepare(host->biu_clk);
3266 EXPORT_SYMBOL(dw_mci_remove);
3270 #ifdef CONFIG_PM_SLEEP
3272 * TODO: we should probably disable the clock to the card in the suspend path.
3274 int dw_mci_suspend(struct dw_mci *host)
3276 if (host->use_dma && host->dma_ops->exit)
3277 host->dma_ops->exit(host);
3281 EXPORT_SYMBOL(dw_mci_suspend);
3283 int dw_mci_resume(struct dw_mci *host)
3287 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3292 if (host->use_dma && host->dma_ops->init)
3293 host->dma_ops->init(host);
3296 * Restore the initial value at FIFOTH register
3297 * And Invalidate the prev_blksz with zero
3299 mci_writel(host, FIFOTH, host->fifoth_val);
3300 host->prev_blksz = 0;
3302 /* Put in max timeout */
3303 mci_writel(host, TMOUT, 0xFFFFFFFF);
3305 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3306 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3307 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3308 DW_MCI_ERROR_FLAGS);
3309 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3311 for (i = 0; i < host->num_slots; i++) {
3312 struct dw_mci_slot *slot = host->slot[i];
3316 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3317 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3318 dw_mci_setup_bus(slot, true);
3322 /* Now that slots are all setup, we can enable card detect */
3323 dw_mci_enable_cd(host);
3327 EXPORT_SYMBOL(dw_mci_resume);
3328 #endif /* CONFIG_PM_SLEEP */
3330 static int __init dw_mci_init(void)
3332 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3336 static void __exit dw_mci_exit(void)
3340 module_init(dw_mci_init);
3341 module_exit(dw_mci_exit);
3343 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3344 MODULE_AUTHOR("NXP Semiconductor VietNam");
3345 MODULE_AUTHOR("Imagination Technologies Ltd");
3346 MODULE_LICENSE("GPL v2");