drivers/mmc/host/rtsx_pci_sdmmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Realtek PCI-Express SD/MMC Card Interface driver
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Wei WANG <wei_wang@realsil.com.cn>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/slab.h>
  12 #include <linux/highmem.h>
  13 #include <linux/delay.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/mmc/host.h>
  17 #include <linux/mmc/mmc.h>
  18 #include <linux/mmc/sd.h>
  19 #include <linux/mmc/sdio.h>
  20 #include <linux/mmc/card.h>
  21 #include <linux/rtsx_pci.h>
  22 #include <asm/unaligned.h>
  23
  24 struct realtek_pci_sdmmc {
  25         struct platform_device  *pdev;
  26         struct rtsx_pcr         *pcr;
  27         struct mmc_host         *mmc;
  28         struct mmc_request      *mrq;
  29 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  30
  31         struct work_struct      work;
  32         struct mutex            host_mutex;
  33
  34         u8                      ssc_depth;
  35         unsigned int            clock;
  36         bool                    vpclk;
  37         bool                    double_clk;
  38         bool                    eject;
  39         bool                    initial_mode;
  40         int                     power_state;
  41 #define SDMMC_POWER_ON          1
  42 #define SDMMC_POWER_OFF         0
  43
  44         int                     sg_count;
  45         s32                     cookie;
  46         int                     cookie_sg_count;
  47         bool                    using_cookie;
  48 };
  49
  50 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  51 {
  52         return &(host->pdev->dev);
  53 }
  54
  55 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  56 {
  57         rtsx_pci_write_register(host->pcr, CARD_STOP,
  58                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  59 }
  60
  61 #ifdef DEBUG
  62 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
  63 {
  64         u16 len = end - start + 1;
  65         int i;
  66         u8 data[8];
  67
  68         for (i = 0; i < len; i += 8) {
  69                 int j;
  70                 int n = min(8, len - i);
  71
  72                 memset(&data, 0, sizeof(data));
  73                 for (j = 0; j < n; j++)
  74                         rtsx_pci_read_register(host->pcr, start + i + j,
  75                                 data + j);
  76                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
  77                         start + i, n, data);
  78         }
  79 }
  80
  81 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  82 {
  83         dump_reg_range(host, 0xFDA0, 0xFDB3);
  84         dump_reg_range(host, 0xFD52, 0xFD69);
  85 }
  86 #else
  87 #define sd_print_debug_regs(host)
  88 #endif /* DEBUG */
  89
  90 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
  91 {
  92         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
  93 }
  94
  95 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
  96 {
  97         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
  98                 SD_CMD_START | cmd->opcode);
  99         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
 100 }
 101
 102 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
 103 {
 104         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
 105         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
 106         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
 107         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
 108 }
 109
 110 static int sd_response_type(struct mmc_command *cmd)
 111 {
 112         switch (mmc_resp_type(cmd)) {
 113         case MMC_RSP_NONE:
 114                 return SD_RSP_TYPE_R0;
 115         case MMC_RSP_R1:
 116                 return SD_RSP_TYPE_R1;
 117         case MMC_RSP_R1_NO_CRC:
 118                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 119         case MMC_RSP_R1B:
 120                 return SD_RSP_TYPE_R1b;
 121         case MMC_RSP_R2:
 122                 return SD_RSP_TYPE_R2;
 123         case MMC_RSP_R3:
 124                 return SD_RSP_TYPE_R3;
 125         default:
 126                 return -EINVAL;
 127         }
 128 }
 129
 130 static int sd_status_index(int resp_type)
 131 {
 132         if (resp_type == SD_RSP_TYPE_R0)
 133                 return 0;
 134         else if (resp_type == SD_RSP_TYPE_R2)
 135                 return 16;
 136
 137         return 5;
 138 }
 139 /*
 140  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 141  *
 142  * @pre: if called in pre_req()
 143  * return:
 144  *      0 - do dma_map_sg()
 145  *      1 - using cookie
 146  */
 147 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 148                 struct mmc_data *data, bool pre)
 149 {
 150         struct rtsx_pcr *pcr = host->pcr;
 151         int read = data->flags & MMC_DATA_READ;
 152         int count = 0;
 153         int using_cookie = 0;
 154
 155         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 156                 dev_err(sdmmc_dev(host),
 157                         "error: data->host_cookie = %d, host->cookie = %d\n",
 158                         data->host_cookie, host->cookie);
 159                 data->host_cookie = 0;
 160         }
 161
 162         if (pre || data->host_cookie != host->cookie) {
 163                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 164         } else {
 165                 count = host->cookie_sg_count;
 166                 using_cookie = 1;
 167         }
 168
 169         if (pre) {
 170                 host->cookie_sg_count = count;
 171                 if (++host->cookie < 0)
 172                         host->cookie = 1;
 173                 data->host_cookie = host->cookie;
 174         } else {
 175                 host->sg_count = count;
 176         }
 177
 178         return using_cookie;
 179 }
 180
 181 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
 182 {
 183         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 184         struct mmc_data *data = mrq->data;
 185
 186         if (data->host_cookie) {
 187                 dev_err(sdmmc_dev(host),
 188                         "error: reset data->host_cookie = %d\n",
 189                         data->host_cookie);
 190                 data->host_cookie = 0;
 191         }
 192
 193         sd_pre_dma_transfer(host, data, true);
 194         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 195 }
 196
 197 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 198                 int err)
 199 {
 200         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 201         struct rtsx_pcr *pcr = host->pcr;
 202         struct mmc_data *data = mrq->data;
 203         int read = data->flags & MMC_DATA_READ;
 204
 205         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 206         data->host_cookie = 0;
 207 }
 208
 209 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 210                 struct mmc_command *cmd)
 211 {
 212         struct rtsx_pcr *pcr = host->pcr;
 213         u8 cmd_idx = (u8)cmd->opcode;
 214         u32 arg = cmd->arg;
 215         int err = 0;
 216         int timeout = 100;
 217         int i;
 218         u8 *ptr;
 219         int rsp_type;
 220         int stat_idx;
 221         bool clock_toggled = false;
 222
 223         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 224                         __func__, cmd_idx, arg);
 225
 226         rsp_type = sd_response_type(cmd);
 227         if (rsp_type < 0)
 228                 goto out;
 229
 230         stat_idx = sd_status_index(rsp_type);
 231
 232         if (rsp_type == SD_RSP_TYPE_R1b)
 233                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
 234
 235         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 236                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 237                                 0xFF, SD_CLK_TOGGLE_EN);
 238                 if (err < 0)
 239                         goto out;
 240
 241                 clock_toggled = true;
 242         }
 243
 244         rtsx_pci_init_cmd(pcr);
 245         sd_cmd_set_sd_cmd(pcr, cmd);
 246         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 247         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 248                         0x01, PINGPONG_BUFFER);
 249         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 250                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 251         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 252                      SD_TRANSFER_END | SD_STAT_IDLE,
 253                      SD_TRANSFER_END | SD_STAT_IDLE);
 254
 255         if (rsp_type == SD_RSP_TYPE_R2) {
 256                 /* Read data from ping-pong buffer */
 257                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 258                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 259         } else if (rsp_type != SD_RSP_TYPE_R0) {
 260                 /* Read data from SD_CMDx registers */
 261                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 262                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 263         }
 264
 265         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 266
 267         err = rtsx_pci_send_cmd(pcr, timeout);
 268         if (err < 0) {
 269                 sd_print_debug_regs(host);
 270                 sd_clear_error(host);
 271                 dev_dbg(sdmmc_dev(host),
 272                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 273                 goto out;
 274         }
 275
 276         if (rsp_type == SD_RSP_TYPE_R0) {
 277                 err = 0;
 278                 goto out;
 279         }
 280
 281         /* Eliminate returned value of CHECK_REG_CMD */
 282         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 283
 284         /* Check (Start,Transmission) bit of Response */
 285         if ((ptr[0] & 0xC0) != 0) {
 286                 err = -EILSEQ;
 287                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 288                 goto out;
 289         }
 290
 291         /* Check CRC7 */
 292         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 293                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 294                         err = -EILSEQ;
 295                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 296                         goto out;
 297                 }
 298         }
 299
 300         if (rsp_type == SD_RSP_TYPE_R2) {
 301                 /*
 302                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
 303                  * of response type R2. Assign dummy CRC, 0, and end bit to the
 304                  * byte(ptr[16], goes into the LSB of resp[3] later).
 305                  */
 306                 ptr[16] = 1;
 307
 308                 for (i = 0; i < 4; i++) {
 309                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 310                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 311                                         i, cmd->resp[i]);
 312                 }
 313         } else {
 314                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 315                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 316                                 cmd->resp[0]);
 317         }
 318
 319 out:
 320         cmd->error = err;
 321
 322         if (err && clock_toggled)
 323                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 324                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 325 }
 326
 327 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
 328         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
 329 {
 330         struct rtsx_pcr *pcr = host->pcr;
 331         int err;
 332         u8 trans_mode;
 333
 334         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 335                 __func__, cmd->opcode, cmd->arg);
 336
 337         if (!buf)
 338                 buf_len = 0;
 339
 340         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
 341                 trans_mode = SD_TM_AUTO_TUNING;
 342         else
 343                 trans_mode = SD_TM_NORMAL_READ;
 344
 345         rtsx_pci_init_cmd(pcr);
 346         sd_cmd_set_sd_cmd(pcr, cmd);
 347         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 348         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 349                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 350                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 351         if (trans_mode != SD_TM_AUTO_TUNING)
 352                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 353                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 354
 355         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 356                         0xFF, trans_mode | SD_TRANSFER_START);
 357         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 358                         SD_TRANSFER_END, SD_TRANSFER_END);
 359
 360         err = rtsx_pci_send_cmd(pcr, timeout);
 361         if (err < 0) {
 362                 sd_print_debug_regs(host);
 363                 dev_dbg(sdmmc_dev(host),
 364                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 365                 return err;
 366         }
 367
 368         if (buf && buf_len) {
 369                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 370                 if (err < 0) {
 371                         dev_dbg(sdmmc_dev(host),
 372                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 373                         return err;
 374                 }
 375         }
 376
 377         return 0;
 378 }
 379
 380 static int sd_write_data(struct realtek_pci_sdmmc *host,
 381         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
 382         int timeout)
 383 {
 384         struct rtsx_pcr *pcr = host->pcr;
 385         int err;
 386
 387         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 388                 __func__, cmd->opcode, cmd->arg);
 389
 390         if (!buf)
 391                 buf_len = 0;
 392
 393         sd_send_cmd_get_rsp(host, cmd);
 394         if (cmd->error)
 395                 return cmd->error;
 396
 397         if (buf && buf_len) {
 398                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 399                 if (err < 0) {
 400                         dev_dbg(sdmmc_dev(host),
 401                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 402                         return err;
 403                 }
 404         }
 405
 406         rtsx_pci_init_cmd(pcr);
 407         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 408         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 409                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 410                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
 411         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 412                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 413         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 414                         SD_TRANSFER_END, SD_TRANSFER_END);
 415
 416         err = rtsx_pci_send_cmd(pcr, timeout);
 417         if (err < 0) {
 418                 sd_print_debug_regs(host);
 419                 dev_dbg(sdmmc_dev(host),
 420                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 421                 return err;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
 428         struct mmc_request *mrq)
 429 {
 430         struct rtsx_pcr *pcr = host->pcr;
 431         struct mmc_host *mmc = host->mmc;
 432         struct mmc_card *card = mmc->card;
 433         struct mmc_command *cmd = mrq->cmd;
 434         struct mmc_data *data = mrq->data;
 435         int uhs = mmc_card_uhs(card);
 436         u8 cfg2 = 0;
 437         int err;
 438         int resp_type;
 439         size_t data_len = data->blksz * data->blocks;
 440
 441         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 442                 __func__, cmd->opcode, cmd->arg);
 443
 444         resp_type = sd_response_type(cmd);
 445         if (resp_type < 0)
 446                 return resp_type;
 447
 448         if (!uhs)
 449                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 450
 451         rtsx_pci_init_cmd(pcr);
 452         sd_cmd_set_sd_cmd(pcr, cmd);
 453         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 454         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 455                         DMA_DONE_INT, DMA_DONE_INT);
 456         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 457                 0xFF, (u8)(data_len >> 24));
 458         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 459                 0xFF, (u8)(data_len >> 16));
 460         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 461                 0xFF, (u8)(data_len >> 8));
 462         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 463         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 464                 0x03 | DMA_PACK_SIZE_MASK,
 465                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 466         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 467                         0x01, RING_BUFFER);
 468         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
 469         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 470                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
 471         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 472                         SD_TRANSFER_END, SD_TRANSFER_END);
 473         rtsx_pci_send_cmd_no_wait(pcr);
 474
 475         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
 476         if (err < 0) {
 477                 sd_print_debug_regs(host);
 478                 sd_clear_error(host);
 479                 return err;
 480         }
 481
 482         return 0;
 483 }
 484
 485 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
 486         struct mmc_request *mrq)
 487 {
 488         struct rtsx_pcr *pcr = host->pcr;
 489         struct mmc_host *mmc = host->mmc;
 490         struct mmc_card *card = mmc->card;
 491         struct mmc_command *cmd = mrq->cmd;
 492         struct mmc_data *data = mrq->data;
 493         int uhs = mmc_card_uhs(card);
 494         u8 cfg2;
 495         int err;
 496         size_t data_len = data->blksz * data->blocks;
 497
 498         sd_send_cmd_get_rsp(host, cmd);
 499         if (cmd->error)
 500                 return cmd->error;
 501
 502         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 503                 __func__, cmd->opcode, cmd->arg);
 504
 505         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 506                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 507
 508         if (!uhs)
 509                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 510
 511         rtsx_pci_init_cmd(pcr);
 512         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 513         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 514                         DMA_DONE_INT, DMA_DONE_INT);
 515         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 516                 0xFF, (u8)(data_len >> 24));
 517         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 518                 0xFF, (u8)(data_len >> 16));
 519         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 520                 0xFF, (u8)(data_len >> 8));
 521         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 522         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 523                 0x03 | DMA_PACK_SIZE_MASK,
 524                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 525         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 526                         0x01, RING_BUFFER);
 527         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 528         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 529                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 530         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 531                         SD_TRANSFER_END, SD_TRANSFER_END);
 532         rtsx_pci_send_cmd_no_wait(pcr);
 533         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
 534         if (err < 0) {
 535                 sd_clear_error(host);
 536                 return err;
 537         }
 538
 539         return 0;
 540 }
 541
 542 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 543 {
 544         struct mmc_data *data = mrq->data;
 545
 546         if (host->sg_count < 0) {
 547                 data->error = host->sg_count;
 548                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
 549                         __func__, host->sg_count);
 550                 return data->error;
 551         }
 552
 553         if (data->flags & MMC_DATA_READ)
 554                 return sd_read_long_data(host, mrq);
 555
 556         return sd_write_long_data(host, mrq);
 557 }
 558
 559 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 560 {
 561         rtsx_pci_write_register(host->pcr, SD_CFG1,
 562                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 563 }
 564
 565 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 566 {
 567         rtsx_pci_write_register(host->pcr, SD_CFG1,
 568                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 569 }
 570
 571 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 572                 struct mmc_request *mrq)
 573 {
 574         struct mmc_command *cmd = mrq->cmd;
 575         struct mmc_data *data = mrq->data;
 576         u8 *buf;
 577
 578         buf = kzalloc(data->blksz, GFP_NOIO);
 579         if (!buf) {
 580                 cmd->error = -ENOMEM;
 581                 return;
 582         }
 583
 584         if (data->flags & MMC_DATA_READ) {
 585                 if (host->initial_mode)
 586                         sd_disable_initial_mode(host);
 587
 588                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
 589                                 data->blksz, 200);
 590
 591                 if (host->initial_mode)
 592                         sd_enable_initial_mode(host);
 593
 594                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 595         } else {
 596                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 597
 598                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
 599                                 data->blksz, 200);
 600         }
 601
 602         kfree(buf);
 603 }
 604
 605 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 606                 u8 sample_point, bool rx)
 607 {
 608         struct rtsx_pcr *pcr = host->pcr;
 609
 610         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 611                         __func__, rx ? "RX" : "TX", sample_point);
 612
 613         rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 614         if (rx)
 615                 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
 616                         PHASE_SELECT_MASK, sample_point);
 617         else
 618                 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
 619                         PHASE_SELECT_MASK, sample_point);
 620         rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 621         rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET,
 622                                 PHASE_NOT_RESET);
 623         rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
 624         rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 625
 626         return 0;
 627 }
 628
 629 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 630 {
 631         bit %= RTSX_PHASE_MAX;
 632         return phase_map & (1 << bit);
 633 }
 634
 635 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 636 {
 637         int i;
 638
 639         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 640                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 641                         return i;
 642         }
 643         return RTSX_PHASE_MAX;
 644 }
 645
 646 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 647 {
 648         int start = 0, len = 0;
 649         int start_final = 0, len_final = 0;
 650         u8 final_phase = 0xFF;
 651
 652         if (phase_map == 0) {
 653                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 654                 return final_phase;
 655         }
 656
 657         while (start < RTSX_PHASE_MAX) {
 658                 len = sd_get_phase_len(phase_map, start);
 659                 if (len_final < len) {
 660                         start_final = start;
 661                         len_final = len;
 662                 }
 663                 start += len ? len : 1;
 664         }
 665
 666         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 667         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 668                 phase_map, len_final, final_phase);
 669
 670         return final_phase;
 671 }
 672
 673 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 674 {
 675         int err, i;
 676         u8 val = 0;
 677
 678         for (i = 0; i < 100; i++) {
 679                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 680                 if (val & SD_DATA_IDLE)
 681                         return;
 682
 683                 udelay(100);
 684         }
 685 }
 686
 687 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 688                 u8 opcode, u8 sample_point)
 689 {
 690         int err;
 691         struct mmc_command cmd = {};
 692         struct rtsx_pcr *pcr = host->pcr;
 693
 694         sd_change_phase(host, sample_point, true);
 695
 696         rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
 697                 SD_RSP_80CLK_TIMEOUT_EN);
 698
 699         cmd.opcode = opcode;
 700         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
 701         if (err < 0) {
 702                 /* Wait till SD DATA IDLE */
 703                 sd_wait_data_idle(host);
 704                 sd_clear_error(host);
 705                 rtsx_pci_write_register(pcr, SD_CFG3,
 706                         SD_RSP_80CLK_TIMEOUT_EN, 0);
 707                 return err;
 708         }
 709
 710         rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
 711         return 0;
 712 }
 713
 714 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 715                 u8 opcode, u32 *phase_map)
 716 {
 717         int err, i;
 718         u32 raw_phase_map = 0;
 719
 720         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 721                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 722                 if (err == 0)
 723                         raw_phase_map |= 1 << i;
 724         }
 725
 726         if (phase_map)
 727                 *phase_map = raw_phase_map;
 728
 729         return 0;
 730 }
 731
 732 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 733 {
 734         int err, i;
 735         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 736         u8 final_phase;
 737
 738         for (i = 0; i < RX_TUNING_CNT; i++) {
 739                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 740                 if (err < 0)
 741                         return err;
 742
 743                 if (raw_phase_map[i] == 0)
 744                         break;
 745         }
 746
 747         phase_map = 0xFFFFFFFF;
 748         for (i = 0; i < RX_TUNING_CNT; i++) {
 749                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 750                                 i, raw_phase_map[i]);
 751                 phase_map &= raw_phase_map[i];
 752         }
 753         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 754
 755         if (phase_map) {
 756                 final_phase = sd_search_final_phase(host, phase_map);
 757                 if (final_phase == 0xFF)
 758                         return -EINVAL;
 759
 760                 err = sd_change_phase(host, final_phase, true);
 761                 if (err < 0)
 762                         return err;
 763         } else {
 764                 return -EINVAL;
 765         }
 766
 767         return 0;
 768 }
 769
 770 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
 771         struct mmc_data *data)
 772 {
 773         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
 774 }
 775
 776 static inline int sd_rw_cmd(struct mmc_command *cmd)
 777 {
 778         return mmc_op_multi(cmd->opcode) ||
 779                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 780                 (cmd->opcode == MMC_WRITE_BLOCK);
 781 }
 782
 783 static void sd_request(struct work_struct *work)
 784 {
 785         struct realtek_pci_sdmmc *host = container_of(work,
 786                         struct realtek_pci_sdmmc, work);
 787         struct rtsx_pcr *pcr = host->pcr;
 788
 789         struct mmc_host *mmc = host->mmc;
 790         struct mmc_request *mrq = host->mrq;
 791         struct mmc_command *cmd = mrq->cmd;
 792         struct mmc_data *data = mrq->data;
 793
 794         unsigned int data_size = 0;
 795         int err;
 796
 797         if (host->eject || !sd_get_cd_int(host)) {
 798                 cmd->error = -ENOMEDIUM;
 799                 goto finish;
 800         }
 801
 802         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 803         if (err) {
 804                 cmd->error = err;
 805                 goto finish;
 806         }
 807
 808         mutex_lock(&pcr->pcr_mutex);
 809
 810         rtsx_pci_start_run(pcr);
 811
 812         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 813                         host->initial_mode, host->double_clk, host->vpclk);
 814         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 815         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 816                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 817
 818         mutex_lock(&host->host_mutex);
 819         host->mrq = mrq;
 820         mutex_unlock(&host->host_mutex);
 821
 822         if (mrq->data)
 823                 data_size = data->blocks * data->blksz;
 824
 825         if (!data_size) {
 826                 sd_send_cmd_get_rsp(host, cmd);
 827         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
 828                 cmd->error = sd_rw_multi(host, mrq);
 829                 if (!host->using_cookie)
 830                         sdmmc_post_req(host->mmc, host->mrq, 0);
 831
 832                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
 833                         sd_send_cmd_get_rsp(host, mrq->stop);
 834         } else {
 835                 sd_normal_rw(host, mrq);
 836         }
 837
 838         if (mrq->data) {
 839                 if (cmd->error || data->error)
 840                         data->bytes_xfered = 0;
 841                 else
 842                         data->bytes_xfered = data->blocks * data->blksz;
 843         }
 844
 845         mutex_unlock(&pcr->pcr_mutex);
 846
 847 finish:
 848         if (cmd->error) {
 849                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
 850                         cmd->opcode, cmd->arg, cmd->error);
 851         }
 852
 853         mutex_lock(&host->host_mutex);
 854         host->mrq = NULL;
 855         mutex_unlock(&host->host_mutex);
 856
 857         mmc_request_done(mmc, mrq);
 858 }
 859
 860 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 861 {
 862         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 863         struct mmc_data *data = mrq->data;
 864
 865         mutex_lock(&host->host_mutex);
 866         host->mrq = mrq;
 867         mutex_unlock(&host->host_mutex);
 868
 869         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
 870                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 871
 872         schedule_work(&host->work);
 873 }
 874
 875 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 876                 unsigned char bus_width)
 877 {
 878         int err = 0;
 879         u8 width[] = {
 880                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 881                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 882                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 883         };
 884
 885         if (bus_width <= MMC_BUS_WIDTH_8)
 886                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 887                                 0x03, width[bus_width]);
 888
 889         return err;
 890 }
 891
 892 static int sd_power_on(struct realtek_pci_sdmmc *host)
 893 {
 894         struct rtsx_pcr *pcr = host->pcr;
 895         int err;
 896
 897         if (host->power_state == SDMMC_POWER_ON)
 898                 return 0;
 899
 900         rtsx_pci_init_cmd(pcr);
 901         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 902         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 903                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 904         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 905                         SD_CLK_EN, SD_CLK_EN);
 906         err = rtsx_pci_send_cmd(pcr, 100);
 907         if (err < 0)
 908                 return err;
 909
 910         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 911         if (err < 0)
 912                 return err;
 913
 914         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 915         if (err < 0)
 916                 return err;
 917
 918         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 919         if (err < 0)
 920                 return err;
 921
 922         host->power_state = SDMMC_POWER_ON;
 923         return 0;
 924 }
 925
 926 static int sd_power_off(struct realtek_pci_sdmmc *host)
 927 {
 928         struct rtsx_pcr *pcr = host->pcr;
 929         int err;
 930
 931         host->power_state = SDMMC_POWER_OFF;
 932
 933         rtsx_pci_init_cmd(pcr);
 934
 935         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 936         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 937
 938         err = rtsx_pci_send_cmd(pcr, 100);
 939         if (err < 0)
 940                 return err;
 941
 942         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 943         if (err < 0)
 944                 return err;
 945
 946         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 947 }
 948
 949 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 950                 unsigned char power_mode)
 951 {
 952         int err;
 953
 954         if (power_mode == MMC_POWER_OFF)
 955                 err = sd_power_off(host);
 956         else
 957                 err = sd_power_on(host);
 958
 959         return err;
 960 }
 961
 962 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 963 {
 964         struct rtsx_pcr *pcr = host->pcr;
 965         int err = 0;
 966
 967         rtsx_pci_init_cmd(pcr);
 968
 969         switch (timing) {
 970         case MMC_TIMING_UHS_SDR104:
 971         case MMC_TIMING_UHS_SDR50:
 972                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 973                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 974                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 975                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 976                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 977                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 978                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 979                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 980                 break;
 981
 982         case MMC_TIMING_MMC_DDR52:
 983         case MMC_TIMING_UHS_DDR50:
 984                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 985                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 986                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
 987                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 988                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 989                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 990                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 991                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 992                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
 993                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
 994                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
 995                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
 996                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
 997                 break;
 998
 999         case MMC_TIMING_MMC_HS:
1000         case MMC_TIMING_SD_HS:
1001                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1002                                 0x0C, SD_20_MODE);
1003                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1004                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1005                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1006                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1007                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1008                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1009                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1010                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1011                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1012                 break;
1013
1014         default:
1015                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1016                                 SD_CFG1, 0x0C, SD_20_MODE);
1017                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1018                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1019                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1020                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1021                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1022                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1023                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1024                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1025                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1026                 break;
1027         }
1028
1029         err = rtsx_pci_send_cmd(pcr, 100);
1030
1031         return err;
1032 }
1033
1034 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1035 {
1036         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1037         struct rtsx_pcr *pcr = host->pcr;
1038
1039         if (host->eject)
1040                 return;
1041
1042         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1043                 return;
1044
1045         mutex_lock(&pcr->pcr_mutex);
1046
1047         rtsx_pci_start_run(pcr);
1048
1049         sd_set_bus_width(host, ios->bus_width);
1050         sd_set_power_mode(host, ios->power_mode);
1051         sd_set_timing(host, ios->timing);
1052
1053         host->vpclk = false;
1054         host->double_clk = true;
1055
1056         switch (ios->timing) {
1057         case MMC_TIMING_UHS_SDR104:
1058         case MMC_TIMING_UHS_SDR50:
1059                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1060                 host->vpclk = true;
1061                 host->double_clk = false;
1062                 break;
1063         case MMC_TIMING_MMC_DDR52:
1064         case MMC_TIMING_UHS_DDR50:
1065         case MMC_TIMING_UHS_SDR25:
1066                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1067                 break;
1068         default:
1069                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1070                 break;
1071         }
1072
1073         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1074
1075         host->clock = ios->clock;
1076         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1077                         host->initial_mode, host->double_clk, host->vpclk);
1078
1079         mutex_unlock(&pcr->pcr_mutex);
1080 }
1081
1082 static int sdmmc_get_ro(struct mmc_host *mmc)
1083 {
1084         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1085         struct rtsx_pcr *pcr = host->pcr;
1086         int ro = 0;
1087         u32 val;
1088
1089         if (host->eject)
1090                 return -ENOMEDIUM;
1091
1092         mutex_lock(&pcr->pcr_mutex);
1093
1094         rtsx_pci_start_run(pcr);
1095
1096         /* Check SD mechanical write-protect switch */
1097         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1098         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1099         if (val & SD_WRITE_PROTECT)
1100                 ro = 1;
1101
1102         mutex_unlock(&pcr->pcr_mutex);
1103
1104         return ro;
1105 }
1106
1107 static int sdmmc_get_cd(struct mmc_host *mmc)
1108 {
1109         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1110         struct rtsx_pcr *pcr = host->pcr;
1111         int cd = 0;
1112         u32 val;
1113
1114         if (host->eject)
1115                 return cd;
1116
1117         mutex_lock(&pcr->pcr_mutex);
1118
1119         rtsx_pci_start_run(pcr);
1120
1121         /* Check SD card detect */
1122         val = rtsx_pci_card_exist(pcr);
1123         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1124         if (val & SD_EXIST)
1125                 cd = 1;
1126
1127         mutex_unlock(&pcr->pcr_mutex);
1128
1129         return cd;
1130 }
1131
1132 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1133 {
1134         struct rtsx_pcr *pcr = host->pcr;
1135         int err;
1136         u8 stat;
1137
1138         /* Reference to Signal Voltage Switch Sequence in SD spec.
1139          * Wait for a period of time so that the card can drive SD_CMD and
1140          * SD_DAT[3:0] to low after sending back CMD11 response.
1141          */
1142         mdelay(1);
1143
1144         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1145          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1146          * abort the voltage switch sequence;
1147          */
1148         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1149         if (err < 0)
1150                 return err;
1151
1152         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1153                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1154                 return -EINVAL;
1155
1156         /* Stop toggle SD clock */
1157         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1158                         0xFF, SD_CLK_FORCE_STOP);
1159         if (err < 0)
1160                 return err;
1161
1162         return 0;
1163 }
1164
1165 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1166 {
1167         struct rtsx_pcr *pcr = host->pcr;
1168         int err;
1169         u8 stat, mask, val;
1170
1171         /* Wait 1.8V output of voltage regulator in card stable */
1172         msleep(50);
1173
1174         /* Toggle SD clock again */
1175         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1176         if (err < 0)
1177                 return err;
1178
1179         /* Wait for a period of time so that the card can drive
1180          * SD_DAT[3:0] to high at 1.8V
1181          */
1182         msleep(20);
1183
1184         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1185         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1186         if (err < 0)
1187                 return err;
1188
1189         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1190                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1191         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1192                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1193         if ((stat & mask) != val) {
1194                 dev_dbg(sdmmc_dev(host),
1195                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1196                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1197                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1198                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1199                 return -EINVAL;
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1206 {
1207         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1208         struct rtsx_pcr *pcr = host->pcr;
1209         int err = 0;
1210         u8 voltage;
1211
1212         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1213                         __func__, ios->signal_voltage);
1214
1215         if (host->eject)
1216                 return -ENOMEDIUM;
1217
1218         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1219         if (err)
1220                 return err;
1221
1222         mutex_lock(&pcr->pcr_mutex);
1223
1224         rtsx_pci_start_run(pcr);
1225
1226         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1227                 voltage = OUTPUT_3V3;
1228         else
1229                 voltage = OUTPUT_1V8;
1230
1231         if (voltage == OUTPUT_1V8) {
1232                 err = sd_wait_voltage_stable_1(host);
1233                 if (err < 0)
1234                         goto out;
1235         }
1236
1237         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1238         if (err < 0)
1239                 goto out;
1240
1241         if (voltage == OUTPUT_1V8) {
1242                 err = sd_wait_voltage_stable_2(host);
1243                 if (err < 0)
1244                         goto out;
1245         }
1246
1247 out:
1248         /* Stop toggle SD clock in idle */
1249         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1250                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1251
1252         mutex_unlock(&pcr->pcr_mutex);
1253
1254         return err;
1255 }
1256
1257 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1258 {
1259         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1260         struct rtsx_pcr *pcr = host->pcr;
1261         int err = 0;
1262
1263         if (host->eject)
1264                 return -ENOMEDIUM;
1265
1266         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1267         if (err)
1268                 return err;
1269
1270         mutex_lock(&pcr->pcr_mutex);
1271
1272         rtsx_pci_start_run(pcr);
1273
1274         /* Set initial TX phase */
1275         switch (mmc->ios.timing) {
1276         case MMC_TIMING_UHS_SDR104:
1277                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1278                 break;
1279
1280         case MMC_TIMING_UHS_SDR50:
1281                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1282                 break;
1283
1284         case MMC_TIMING_UHS_DDR50:
1285                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1286                 break;
1287
1288         default:
1289                 err = 0;
1290         }
1291
1292         if (err)
1293                 goto out;
1294
1295         /* Tuning RX phase */
1296         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1297                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1298                 err = sd_tuning_rx(host, opcode);
1299         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1300                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1301
1302 out:
1303         mutex_unlock(&pcr->pcr_mutex);
1304
1305         return err;
1306 }
1307
1308 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1309         .pre_req = sdmmc_pre_req,
1310         .post_req = sdmmc_post_req,
1311         .request = sdmmc_request,
1312         .set_ios = sdmmc_set_ios,
1313         .get_ro = sdmmc_get_ro,
1314         .get_cd = sdmmc_get_cd,
1315         .start_signal_voltage_switch = sdmmc_switch_voltage,
1316         .execute_tuning = sdmmc_execute_tuning,
1317 };
1318
1319 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1320 {
1321         struct mmc_host *mmc = host->mmc;
1322         struct rtsx_pcr *pcr = host->pcr;
1323
1324         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1325
1326         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1327                 mmc->caps |= MMC_CAP_UHS_SDR50;
1328         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1329                 mmc->caps |= MMC_CAP_UHS_SDR104;
1330         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1331                 mmc->caps |= MMC_CAP_UHS_DDR50;
1332         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1333                 mmc->caps |= MMC_CAP_1_8V_DDR;
1334         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1335                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1336 }
1337
1338 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1339 {
1340         struct mmc_host *mmc = host->mmc;
1341
1342         mmc->f_min = 250000;
1343         mmc->f_max = 208000000;
1344         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1345         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1346                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1347                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1348         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1349         mmc->max_current_330 = 400;
1350         mmc->max_current_180 = 800;
1351         mmc->ops = &realtek_pci_sdmmc_ops;
1352
1353         init_extra_caps(host);
1354
1355         mmc->max_segs = 256;
1356         mmc->max_seg_size = 65536;
1357         mmc->max_blk_size = 512;
1358         mmc->max_blk_count = 65535;
1359         mmc->max_req_size = 524288;
1360 }
1361
1362 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1363 {
1364         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1365
1366         host->cookie = -1;
1367         mmc_detect_change(host->mmc, 0);
1368 }
1369
1370 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1371 {
1372         struct mmc_host *mmc;
1373         struct realtek_pci_sdmmc *host;
1374         struct rtsx_pcr *pcr;
1375         struct pcr_handle *handle = pdev->dev.platform_data;
1376
1377         if (!handle)
1378                 return -ENXIO;
1379
1380         pcr = handle->pcr;
1381         if (!pcr)
1382                 return -ENXIO;
1383
1384         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1385
1386         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1387         if (!mmc)
1388                 return -ENOMEM;
1389
1390         host = mmc_priv(mmc);
1391         host->pcr = pcr;
1392         host->mmc = mmc;
1393         host->pdev = pdev;
1394         host->cookie = -1;
1395         host->power_state = SDMMC_POWER_OFF;
1396         INIT_WORK(&host->work, sd_request);
1397         platform_set_drvdata(pdev, host);
1398         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1399         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1400
1401         mutex_init(&host->host_mutex);
1402
1403         realtek_init_host(host);
1404
1405         mmc_add_host(mmc);
1406
1407         return 0;
1408 }
1409
1410 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1411 {
1412         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1413         struct rtsx_pcr *pcr;
1414         struct mmc_host *mmc;
1415
1416         if (!host)
1417                 return 0;
1418
1419         pcr = host->pcr;
1420         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1421         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1422         mmc = host->mmc;
1423
1424         cancel_work_sync(&host->work);
1425
1426         mutex_lock(&host->host_mutex);
1427         if (host->mrq) {
1428                 dev_dbg(&(pdev->dev),
1429                         "%s: Controller removed during transfer\n",
1430                         mmc_hostname(mmc));
1431
1432                 rtsx_pci_complete_unfinished_transfer(pcr);
1433
1434                 host->mrq->cmd->error = -ENOMEDIUM;
1435                 if (host->mrq->stop)
1436                         host->mrq->stop->error = -ENOMEDIUM;
1437                 mmc_request_done(mmc, host->mrq);
1438         }
1439         mutex_unlock(&host->host_mutex);
1440
1441         mmc_remove_host(mmc);
1442         host->eject = true;
1443
1444         flush_work(&host->work);
1445
1446         mmc_free_host(mmc);
1447
1448         dev_dbg(&(pdev->dev),
1449                 ": Realtek PCI-E SDMMC controller has been removed\n");
1450
1451         return 0;
1452 }
1453
1454 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1455         {
1456                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1457         }, {
1458                 /* sentinel */
1459         }
1460 };
1461 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1462
1463 static struct platform_driver rtsx_pci_sdmmc_driver = {
1464         .probe          = rtsx_pci_sdmmc_drv_probe,
1465         .remove         = rtsx_pci_sdmmc_drv_remove,
1466         .id_table       = rtsx_pci_sdmmc_ids,
1467         .driver         = {
1468                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1469         },
1470 };
1471 module_platform_driver(rtsx_pci_sdmmc_driver);
1472
1473 MODULE_LICENSE("GPL");
1474 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1475 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");