drivers/mmc/host/sdhci-msm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
   4  *
   5  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/of_device.h>
  10 #include <linux/delay.h>
  11 #include <linux/mmc/mmc.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/slab.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/regulator/consumer.h>
  16
  17 #include "sdhci-pltfm.h"
  18
  19 #define CORE_MCI_VERSION                0x50
  20 #define CORE_VERSION_MAJOR_SHIFT        28
  21 #define CORE_VERSION_MAJOR_MASK         (0xf << CORE_VERSION_MAJOR_SHIFT)
  22 #define CORE_VERSION_MINOR_MASK         0xff
  23
  24 #define CORE_MCI_GENERICS               0x70
  25 #define SWITCHABLE_SIGNALING_VOLTAGE    BIT(29)
  26
  27 #define HC_MODE_EN              0x1
  28 #define CORE_POWER              0x0
  29 #define CORE_SW_RST             BIT(7)
  30 #define FF_CLK_SW_RST_DIS       BIT(13)
  31
  32 #define CORE_PWRCTL_BUS_OFF     BIT(0)
  33 #define CORE_PWRCTL_BUS_ON      BIT(1)
  34 #define CORE_PWRCTL_IO_LOW      BIT(2)
  35 #define CORE_PWRCTL_IO_HIGH     BIT(3)
  36 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
  37 #define CORE_PWRCTL_IO_SUCCESS  BIT(2)
  38 #define REQ_BUS_OFF             BIT(0)
  39 #define REQ_BUS_ON              BIT(1)
  40 #define REQ_IO_LOW              BIT(2)
  41 #define REQ_IO_HIGH             BIT(3)
  42 #define INT_MASK                0xf
  43 #define MAX_PHASES              16
  44 #define CORE_DLL_LOCK           BIT(7)
  45 #define CORE_DDR_DLL_LOCK       BIT(11)
  46 #define CORE_DLL_EN             BIT(16)
  47 #define CORE_CDR_EN             BIT(17)
  48 #define CORE_CK_OUT_EN          BIT(18)
  49 #define CORE_CDR_EXT_EN         BIT(19)
  50 #define CORE_DLL_PDN            BIT(29)
  51 #define CORE_DLL_RST            BIT(30)
  52 #define CORE_CMD_DAT_TRACK_SEL  BIT(0)
  53
  54 #define CORE_DDR_CAL_EN         BIT(0)
  55 #define CORE_FLL_CYCLE_CNT      BIT(18)
  56 #define CORE_DLL_CLOCK_DISABLE  BIT(21)
  57
  58 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
  59 #define CORE_CLK_PWRSAVE        BIT(1)
  60 #define CORE_HC_MCLK_SEL_DFLT   (2 << 8)
  61 #define CORE_HC_MCLK_SEL_HS400  (3 << 8)
  62 #define CORE_HC_MCLK_SEL_MASK   (3 << 8)
  63 #define CORE_IO_PAD_PWR_SWITCH_EN       (1 << 15)
  64 #define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
  65 #define CORE_HC_SELECT_IN_EN    BIT(18)
  66 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
  67 #define CORE_HC_SELECT_IN_MASK  (7 << 19)
  68
  69 #define CORE_3_0V_SUPPORT       (1 << 25)
  70 #define CORE_1_8V_SUPPORT       (1 << 26)
  71 #define CORE_VOLT_SUPPORT       (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
  72
  73 #define CORE_CSR_CDC_CTLR_CFG0          0x130
  74 #define CORE_SW_TRIG_FULL_CALIB         BIT(16)
  75 #define CORE_HW_AUTOCAL_ENA             BIT(17)
  76
  77 #define CORE_CSR_CDC_CTLR_CFG1          0x134
  78 #define CORE_CSR_CDC_CAL_TIMER_CFG0     0x138
  79 #define CORE_TIMER_ENA                  BIT(16)
  80
  81 #define CORE_CSR_CDC_CAL_TIMER_CFG1     0x13C
  82 #define CORE_CSR_CDC_REFCOUNT_CFG       0x140
  83 #define CORE_CSR_CDC_COARSE_CAL_CFG     0x144
  84 #define CORE_CDC_OFFSET_CFG             0x14C
  85 #define CORE_CSR_CDC_DELAY_CFG          0x150
  86 #define CORE_CDC_SLAVE_DDA_CFG          0x160
  87 #define CORE_CSR_CDC_STATUS0            0x164
  88 #define CORE_CALIBRATION_DONE           BIT(0)
  89
  90 #define CORE_CDC_ERROR_CODE_MASK        0x7000000
  91
  92 #define CORE_CSR_CDC_GEN_CFG            0x178
  93 #define CORE_CDC_SWITCH_BYPASS_OFF      BIT(0)
  94 #define CORE_CDC_SWITCH_RC_EN           BIT(1)
  95
  96 #define CORE_CDC_T4_DLY_SEL             BIT(0)
  97 #define CORE_CMDIN_RCLK_EN              BIT(1)
  98 #define CORE_START_CDC_TRAFFIC          BIT(6)
  99
 100 #define CORE_PWRSAVE_DLL        BIT(3)
 101
 102 #define DDR_CONFIG_POR_VAL      0x80040853
 103
 104
 105 #define INVALID_TUNING_PHASE    -1
 106 #define SDHCI_MSM_MIN_CLOCK     400000
 107 #define CORE_FREQ_100MHZ        (100 * 1000 * 1000)
 108
 109 #define CDR_SELEXT_SHIFT        20
 110 #define CDR_SELEXT_MASK         (0xf << CDR_SELEXT_SHIFT)
 111 #define CMUX_SHIFT_PHASE_SHIFT  24
 112 #define CMUX_SHIFT_PHASE_MASK   (7 << CMUX_SHIFT_PHASE_SHIFT)
 113
 114 #define MSM_MMC_AUTOSUSPEND_DELAY_MS    50
 115
 116 /* Timeout value to avoid infinite waiting for pwr_irq */
 117 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
 118
 119 #define msm_host_readl(msm_host, host, offset) \
 120         msm_host->var_ops->msm_readl_relaxed(host, offset)
 121
 122 #define msm_host_writel(msm_host, val, host, offset) \
 123         msm_host->var_ops->msm_writel_relaxed(val, host, offset)
 124
 125 struct sdhci_msm_offset {
 126         u32 core_hc_mode;
 127         u32 core_mci_data_cnt;
 128         u32 core_mci_status;
 129         u32 core_mci_fifo_cnt;
 130         u32 core_mci_version;
 131         u32 core_generics;
 132         u32 core_testbus_config;
 133         u32 core_testbus_sel2_bit;
 134         u32 core_testbus_ena;
 135         u32 core_testbus_sel2;
 136         u32 core_pwrctl_status;
 137         u32 core_pwrctl_mask;
 138         u32 core_pwrctl_clear;
 139         u32 core_pwrctl_ctl;
 140         u32 core_sdcc_debug_reg;
 141         u32 core_dll_config;
 142         u32 core_dll_status;
 143         u32 core_vendor_spec;
 144         u32 core_vendor_spec_adma_err_addr0;
 145         u32 core_vendor_spec_adma_err_addr1;
 146         u32 core_vendor_spec_func2;
 147         u32 core_vendor_spec_capabilities0;
 148         u32 core_ddr_200_cfg;
 149         u32 core_vendor_spec3;
 150         u32 core_dll_config_2;
 151         u32 core_ddr_config;
 152         u32 core_ddr_config_2;
 153 };
 154
 155 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
 156         .core_mci_data_cnt = 0x35c,
 157         .core_mci_status = 0x324,
 158         .core_mci_fifo_cnt = 0x308,
 159         .core_mci_version = 0x318,
 160         .core_generics = 0x320,
 161         .core_testbus_config = 0x32c,
 162         .core_testbus_sel2_bit = 3,
 163         .core_testbus_ena = (1 << 31),
 164         .core_testbus_sel2 = (1 << 3),
 165         .core_pwrctl_status = 0x240,
 166         .core_pwrctl_mask = 0x244,
 167         .core_pwrctl_clear = 0x248,
 168         .core_pwrctl_ctl = 0x24c,
 169         .core_sdcc_debug_reg = 0x358,
 170         .core_dll_config = 0x200,
 171         .core_dll_status = 0x208,
 172         .core_vendor_spec = 0x20c,
 173         .core_vendor_spec_adma_err_addr0 = 0x214,
 174         .core_vendor_spec_adma_err_addr1 = 0x218,
 175         .core_vendor_spec_func2 = 0x210,
 176         .core_vendor_spec_capabilities0 = 0x21c,
 177         .core_ddr_200_cfg = 0x224,
 178         .core_vendor_spec3 = 0x250,
 179         .core_dll_config_2 = 0x254,
 180         .core_ddr_config = 0x258,
 181         .core_ddr_config_2 = 0x25c,
 182 };
 183
 184 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
 185         .core_hc_mode = 0x78,
 186         .core_mci_data_cnt = 0x30,
 187         .core_mci_status = 0x34,
 188         .core_mci_fifo_cnt = 0x44,
 189         .core_mci_version = 0x050,
 190         .core_generics = 0x70,
 191         .core_testbus_config = 0x0cc,
 192         .core_testbus_sel2_bit = 4,
 193         .core_testbus_ena = (1 << 3),
 194         .core_testbus_sel2 = (1 << 4),
 195         .core_pwrctl_status = 0xdc,
 196         .core_pwrctl_mask = 0xe0,
 197         .core_pwrctl_clear = 0xe4,
 198         .core_pwrctl_ctl = 0xe8,
 199         .core_sdcc_debug_reg = 0x124,
 200         .core_dll_config = 0x100,
 201         .core_dll_status = 0x108,
 202         .core_vendor_spec = 0x10c,
 203         .core_vendor_spec_adma_err_addr0 = 0x114,
 204         .core_vendor_spec_adma_err_addr1 = 0x118,
 205         .core_vendor_spec_func2 = 0x110,
 206         .core_vendor_spec_capabilities0 = 0x11c,
 207         .core_ddr_200_cfg = 0x184,
 208         .core_vendor_spec3 = 0x1b0,
 209         .core_dll_config_2 = 0x1b4,
 210         .core_ddr_config = 0x1b8,
 211         .core_ddr_config_2 = 0x1bc,
 212 };
 213
 214 struct sdhci_msm_variant_ops {
 215         u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
 216         void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
 217                         u32 offset);
 218 };
 219
 220 /*
 221  * From V5, register spaces have changed. Wrap this info in a structure
 222  * and choose the data_structure based on version info mentioned in DT.
 223  */
 224 struct sdhci_msm_variant_info {
 225         bool mci_removed;
 226         bool restore_dll_config;
 227         const struct sdhci_msm_variant_ops *var_ops;
 228         const struct sdhci_msm_offset *offset;
 229 };
 230
 231 struct sdhci_msm_host {
 232         struct platform_device *pdev;
 233         void __iomem *core_mem; /* MSM SDCC mapped address */
 234         int pwr_irq;            /* power irq */
 235         struct clk *bus_clk;    /* SDHC bus voter clock */
 236         struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
 237         struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
 238         unsigned long clk_rate;
 239         struct mmc_host *mmc;
 240         bool use_14lpp_dll_reset;
 241         bool tuning_done;
 242         bool calibration_done;
 243         u8 saved_tuning_phase;
 244         bool use_cdclp533;
 245         u32 curr_pwr_state;
 246         u32 curr_io_level;
 247         wait_queue_head_t pwr_irq_wait;
 248         bool pwr_irq_flag;
 249         u32 caps_0;
 250         bool mci_removed;
 251         bool restore_dll_config;
 252         const struct sdhci_msm_variant_ops *var_ops;
 253         const struct sdhci_msm_offset *offset;
 254         bool use_cdr;
 255         u32 transfer_mode;
 256 };
 257
 258 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
 259 {
 260         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 261         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 262
 263         return msm_host->offset;
 264 }
 265
 266 /*
 267  * APIs to read/write to vendor specific registers which were there in the
 268  * core_mem region before MCI was removed.
 269  */
 270 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
 271                 u32 offset)
 272 {
 273         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 274         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 275
 276         return readl_relaxed(msm_host->core_mem + offset);
 277 }
 278
 279 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
 280                 u32 offset)
 281 {
 282         return readl_relaxed(host->ioaddr + offset);
 283 }
 284
 285 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
 286                 struct sdhci_host *host, u32 offset)
 287 {
 288         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 289         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 290
 291         writel_relaxed(val, msm_host->core_mem + offset);
 292 }
 293
 294 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
 295                 struct sdhci_host *host, u32 offset)
 296 {
 297         writel_relaxed(val, host->ioaddr + offset);
 298 }
 299
 300 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
 301                                                     unsigned int clock)
 302 {
 303         struct mmc_ios ios = host->mmc->ios;
 304         /*
 305          * The SDHC requires internal clock frequency to be double the
 306          * actual clock that will be set for DDR mode. The controller
 307          * uses the faster clock(100/400MHz) for some of its parts and
 308          * send the actual required clock (50/200MHz) to the card.
 309          */
 310         if (ios.timing == MMC_TIMING_UHS_DDR50 ||
 311             ios.timing == MMC_TIMING_MMC_DDR52 ||
 312             ios.timing == MMC_TIMING_MMC_HS400 ||
 313             host->flags & SDHCI_HS400_TUNING)
 314                 clock *= 2;
 315         return clock;
 316 }
 317
 318 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
 319                                             unsigned int clock)
 320 {
 321         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 322         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 323         struct mmc_ios curr_ios = host->mmc->ios;
 324         struct clk *core_clk = msm_host->bulk_clks[0].clk;
 325         int rc;
 326
 327         clock = msm_get_clock_rate_for_bus_mode(host, clock);
 328         rc = clk_set_rate(core_clk, clock);
 329         if (rc) {
 330                 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
 331                        mmc_hostname(host->mmc), clock,
 332                        curr_ios.timing);
 333                 return;
 334         }
 335         msm_host->clk_rate = clock;
 336         pr_debug("%s: Setting clock at rate %lu at timing %d\n",
 337                  mmc_hostname(host->mmc), clk_get_rate(core_clk),
 338                  curr_ios.timing);
 339 }
 340
 341 /* Platform specific tuning */
 342 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
 343 {
 344         u32 wait_cnt = 50;
 345         u8 ck_out_en;
 346         struct mmc_host *mmc = host->mmc;
 347         const struct sdhci_msm_offset *msm_offset =
 348                                         sdhci_priv_msm_offset(host);
 349
 350         /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
 351         ck_out_en = !!(readl_relaxed(host->ioaddr +
 352                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 353
 354         while (ck_out_en != poll) {
 355                 if (--wait_cnt == 0) {
 356                         dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
 357                                mmc_hostname(mmc), poll);
 358                         return -ETIMEDOUT;
 359                 }
 360                 udelay(1);
 361
 362                 ck_out_en = !!(readl_relaxed(host->ioaddr +
 363                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 370 {
 371         int rc;
 372         static const u8 grey_coded_phase_table[] = {
 373                 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 374                 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 375         };
 376         unsigned long flags;
 377         u32 config;
 378         struct mmc_host *mmc = host->mmc;
 379         const struct sdhci_msm_offset *msm_offset =
 380                                         sdhci_priv_msm_offset(host);
 381
 382         if (phase > 0xf)
 383                 return -EINVAL;
 384
 385         spin_lock_irqsave(&host->lock, flags);
 386
 387         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 388         config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 389         config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 390         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 391
 392         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 393         rc = msm_dll_poll_ck_out_en(host, 0);
 394         if (rc)
 395                 goto err_out;
 396
 397         /*
 398          * Write the selected DLL clock output phase (0 ... 15)
 399          * to CDR_SELEXT bit field of DLL_CONFIG register.
 400          */
 401         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 402         config &= ~CDR_SELEXT_MASK;
 403         config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 404         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 405
 406         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 407         config |= CORE_CK_OUT_EN;
 408         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 409
 410         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 411         rc = msm_dll_poll_ck_out_en(host, 1);
 412         if (rc)
 413                 goto err_out;
 414
 415         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 416         config |= CORE_CDR_EN;
 417         config &= ~CORE_CDR_EXT_EN;
 418         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 419         goto out;
 420
 421 err_out:
 422         dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 423                mmc_hostname(mmc), phase);
 424 out:
 425         spin_unlock_irqrestore(&host->lock, flags);
 426         return rc;
 427 }
 428
 429 /*
 430  * Find out the greatest range of consecuitive selected
 431  * DLL clock output phases that can be used as sampling
 432  * setting for SD3.0 UHS-I card read operation (in SDR104
 433  * timing mode) or for eMMC4.5 card read operation (in
 434  * HS400/HS200 timing mode).
 435  * Select the 3/4 of the range and configure the DLL with the
 436  * selected DLL clock output phase.
 437  */
 438
 439 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 440                                            u8 *phase_table, u8 total_phases)
 441 {
 442         int ret;
 443         u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 444         u8 phases_per_row[MAX_PHASES] = { 0 };
 445         int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 446         int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 447         bool phase_0_found = false, phase_15_found = false;
 448         struct mmc_host *mmc = host->mmc;
 449
 450         if (!total_phases || (total_phases > MAX_PHASES)) {
 451                 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 452                        mmc_hostname(mmc), total_phases);
 453                 return -EINVAL;
 454         }
 455
 456         for (cnt = 0; cnt < total_phases; cnt++) {
 457                 ranges[row_index][col_index] = phase_table[cnt];
 458                 phases_per_row[row_index] += 1;
 459                 col_index++;
 460
 461                 if ((cnt + 1) == total_phases) {
 462                         continue;
 463                 /* check if next phase in phase_table is consecutive or not */
 464                 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 465                         row_index++;
 466                         col_index = 0;
 467                 }
 468         }
 469
 470         if (row_index >= MAX_PHASES)
 471                 return -EINVAL;
 472
 473         /* Check if phase-0 is present in first valid window? */
 474         if (!ranges[0][0]) {
 475                 phase_0_found = true;
 476                 phase_0_raw_index = 0;
 477                 /* Check if cycle exist between 2 valid windows */
 478                 for (cnt = 1; cnt <= row_index; cnt++) {
 479                         if (phases_per_row[cnt]) {
 480                                 for (i = 0; i < phases_per_row[cnt]; i++) {
 481                                         if (ranges[cnt][i] == 15) {
 482                                                 phase_15_found = true;
 483                                                 phase_15_raw_index = cnt;
 484                                                 break;
 485                                         }
 486                                 }
 487                         }
 488                 }
 489         }
 490
 491         /* If 2 valid windows form cycle then merge them as single window */
 492         if (phase_0_found && phase_15_found) {
 493                 /* number of phases in raw where phase 0 is present */
 494                 u8 phases_0 = phases_per_row[phase_0_raw_index];
 495                 /* number of phases in raw where phase 15 is present */
 496                 u8 phases_15 = phases_per_row[phase_15_raw_index];
 497
 498                 if (phases_0 + phases_15 >= MAX_PHASES)
 499                         /*
 500                          * If there are more than 1 phase windows then total
 501                          * number of phases in both the windows should not be
 502                          * more than or equal to MAX_PHASES.
 503                          */
 504                         return -EINVAL;
 505
 506                 /* Merge 2 cyclic windows */
 507                 i = phases_15;
 508                 for (cnt = 0; cnt < phases_0; cnt++) {
 509                         ranges[phase_15_raw_index][i] =
 510                             ranges[phase_0_raw_index][cnt];
 511                         if (++i >= MAX_PHASES)
 512                                 break;
 513                 }
 514
 515                 phases_per_row[phase_0_raw_index] = 0;
 516                 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 517         }
 518
 519         for (cnt = 0; cnt <= row_index; cnt++) {
 520                 if (phases_per_row[cnt] > curr_max) {
 521                         curr_max = phases_per_row[cnt];
 522                         selected_row_index = cnt;
 523                 }
 524         }
 525
 526         i = (curr_max * 3) / 4;
 527         if (i)
 528                 i--;
 529
 530         ret = ranges[selected_row_index][i];
 531
 532         if (ret >= MAX_PHASES) {
 533                 ret = -EINVAL;
 534                 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 535                        mmc_hostname(mmc), ret);
 536         }
 537
 538         return ret;
 539 }
 540
 541 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 542 {
 543         u32 mclk_freq = 0, config;
 544         const struct sdhci_msm_offset *msm_offset =
 545                                         sdhci_priv_msm_offset(host);
 546
 547         /* Program the MCLK value to MCLK_FREQ bit field */
 548         if (host->clock <= 112000000)
 549                 mclk_freq = 0;
 550         else if (host->clock <= 125000000)
 551                 mclk_freq = 1;
 552         else if (host->clock <= 137000000)
 553                 mclk_freq = 2;
 554         else if (host->clock <= 150000000)
 555                 mclk_freq = 3;
 556         else if (host->clock <= 162000000)
 557                 mclk_freq = 4;
 558         else if (host->clock <= 175000000)
 559                 mclk_freq = 5;
 560         else if (host->clock <= 187000000)
 561                 mclk_freq = 6;
 562         else if (host->clock <= 200000000)
 563                 mclk_freq = 7;
 564
 565         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 566         config &= ~CMUX_SHIFT_PHASE_MASK;
 567         config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 568         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 569 }
 570
 571 /* Initialize the DLL (Programmable Delay Line) */
 572 static int msm_init_cm_dll(struct sdhci_host *host)
 573 {
 574         struct mmc_host *mmc = host->mmc;
 575         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 576         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 577         int wait_cnt = 50;
 578         unsigned long flags, xo_clk = 0;
 579         u32 config;
 580         const struct sdhci_msm_offset *msm_offset =
 581                                         msm_host->offset;
 582
 583         if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
 584                 xo_clk = clk_get_rate(msm_host->xo_clk);
 585
 586         spin_lock_irqsave(&host->lock, flags);
 587
 588         /*
 589          * Make sure that clock is always enabled when DLL
 590          * tuning is in progress. Keeping PWRSAVE ON may
 591          * turn off the clock.
 592          */
 593         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 594         config &= ~CORE_CLK_PWRSAVE;
 595         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 596
 597         if (msm_host->use_14lpp_dll_reset) {
 598                 config = readl_relaxed(host->ioaddr +
 599                                 msm_offset->core_dll_config);
 600                 config &= ~CORE_CK_OUT_EN;
 601                 writel_relaxed(config, host->ioaddr +
 602                                 msm_offset->core_dll_config);
 603
 604                 config = readl_relaxed(host->ioaddr +
 605                                 msm_offset->core_dll_config_2);
 606                 config |= CORE_DLL_CLOCK_DISABLE;
 607                 writel_relaxed(config, host->ioaddr +
 608                                 msm_offset->core_dll_config_2);
 609         }
 610
 611         config = readl_relaxed(host->ioaddr +
 612                         msm_offset->core_dll_config);
 613         config |= CORE_DLL_RST;
 614         writel_relaxed(config, host->ioaddr +
 615                         msm_offset->core_dll_config);
 616
 617         config = readl_relaxed(host->ioaddr +
 618                         msm_offset->core_dll_config);
 619         config |= CORE_DLL_PDN;
 620         writel_relaxed(config, host->ioaddr +
 621                         msm_offset->core_dll_config);
 622         msm_cm_dll_set_freq(host);
 623
 624         if (msm_host->use_14lpp_dll_reset &&
 625             !IS_ERR_OR_NULL(msm_host->xo_clk)) {
 626                 u32 mclk_freq = 0;
 627
 628                 config = readl_relaxed(host->ioaddr +
 629                                 msm_offset->core_dll_config_2);
 630                 config &= CORE_FLL_CYCLE_CNT;
 631                 if (config)
 632                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
 633                                         xo_clk);
 634                 else
 635                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
 636                                         xo_clk);
 637
 638                 config = readl_relaxed(host->ioaddr +
 639                                 msm_offset->core_dll_config_2);
 640                 config &= ~(0xFF << 10);
 641                 config |= mclk_freq << 10;
 642
 643                 writel_relaxed(config, host->ioaddr +
 644                                 msm_offset->core_dll_config_2);
 645                 /* wait for 5us before enabling DLL clock */
 646                 udelay(5);
 647         }
 648
 649         config = readl_relaxed(host->ioaddr +
 650                         msm_offset->core_dll_config);
 651         config &= ~CORE_DLL_RST;
 652         writel_relaxed(config, host->ioaddr +
 653                         msm_offset->core_dll_config);
 654
 655         config = readl_relaxed(host->ioaddr +
 656                         msm_offset->core_dll_config);
 657         config &= ~CORE_DLL_PDN;
 658         writel_relaxed(config, host->ioaddr +
 659                         msm_offset->core_dll_config);
 660
 661         if (msm_host->use_14lpp_dll_reset) {
 662                 msm_cm_dll_set_freq(host);
 663                 config = readl_relaxed(host->ioaddr +
 664                                 msm_offset->core_dll_config_2);
 665                 config &= ~CORE_DLL_CLOCK_DISABLE;
 666                 writel_relaxed(config, host->ioaddr +
 667                                 msm_offset->core_dll_config_2);
 668         }
 669
 670         config = readl_relaxed(host->ioaddr +
 671                         msm_offset->core_dll_config);
 672         config |= CORE_DLL_EN;
 673         writel_relaxed(config, host->ioaddr +
 674                         msm_offset->core_dll_config);
 675
 676         config = readl_relaxed(host->ioaddr +
 677                         msm_offset->core_dll_config);
 678         config |= CORE_CK_OUT_EN;
 679         writel_relaxed(config, host->ioaddr +
 680                         msm_offset->core_dll_config);
 681
 682         /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 683         while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
 684                  CORE_DLL_LOCK)) {
 685                 /* max. wait for 50us sec for LOCK bit to be set */
 686                 if (--wait_cnt == 0) {
 687                         dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 688                                mmc_hostname(mmc));
 689                         spin_unlock_irqrestore(&host->lock, flags);
 690                         return -ETIMEDOUT;
 691                 }
 692                 udelay(1);
 693         }
 694
 695         spin_unlock_irqrestore(&host->lock, flags);
 696         return 0;
 697 }
 698
 699 static void msm_hc_select_default(struct sdhci_host *host)
 700 {
 701         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 702         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 703         u32 config;
 704         const struct sdhci_msm_offset *msm_offset =
 705                                         msm_host->offset;
 706
 707         if (!msm_host->use_cdclp533) {
 708                 config = readl_relaxed(host->ioaddr +
 709                                 msm_offset->core_vendor_spec3);
 710                 config &= ~CORE_PWRSAVE_DLL;
 711                 writel_relaxed(config, host->ioaddr +
 712                                 msm_offset->core_vendor_spec3);
 713         }
 714
 715         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 716         config &= ~CORE_HC_MCLK_SEL_MASK;
 717         config |= CORE_HC_MCLK_SEL_DFLT;
 718         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 719
 720         /*
 721          * Disable HC_SELECT_IN to be able to use the UHS mode select
 722          * configuration from Host Control2 register for all other
 723          * modes.
 724          * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
 725          * in VENDOR_SPEC_FUNC
 726          */
 727         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 728         config &= ~CORE_HC_SELECT_IN_EN;
 729         config &= ~CORE_HC_SELECT_IN_MASK;
 730         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 731
 732         /*
 733          * Make sure above writes impacting free running MCLK are completed
 734          * before changing the clk_rate at GCC.
 735          */
 736         wmb();
 737 }
 738
 739 static void msm_hc_select_hs400(struct sdhci_host *host)
 740 {
 741         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 742         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 743         struct mmc_ios ios = host->mmc->ios;
 744         u32 config, dll_lock;
 745         int rc;
 746         const struct sdhci_msm_offset *msm_offset =
 747                                         msm_host->offset;
 748
 749         /* Select the divided clock (free running MCLK/2) */
 750         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 751         config &= ~CORE_HC_MCLK_SEL_MASK;
 752         config |= CORE_HC_MCLK_SEL_HS400;
 753
 754         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 755         /*
 756          * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
 757          * register
 758          */
 759         if ((msm_host->tuning_done || ios.enhanced_strobe) &&
 760             !msm_host->calibration_done) {
 761                 config = readl_relaxed(host->ioaddr +
 762                                 msm_offset->core_vendor_spec);
 763                 config |= CORE_HC_SELECT_IN_HS400;
 764                 config |= CORE_HC_SELECT_IN_EN;
 765                 writel_relaxed(config, host->ioaddr +
 766                                 msm_offset->core_vendor_spec);
 767         }
 768         if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
 769                 /*
 770                  * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
 771                  * core_dll_status to be set. This should get set
 772                  * within 15 us at 200 MHz.
 773                  */
 774                 rc = readl_relaxed_poll_timeout(host->ioaddr +
 775                                                 msm_offset->core_dll_status,
 776                                                 dll_lock,
 777                                                 (dll_lock &
 778                                                 (CORE_DLL_LOCK |
 779                                                 CORE_DDR_DLL_LOCK)), 10,
 780                                                 1000);
 781                 if (rc == -ETIMEDOUT)
 782                         pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
 783                                mmc_hostname(host->mmc), dll_lock);
 784         }
 785         /*
 786          * Make sure above writes impacting free running MCLK are completed
 787          * before changing the clk_rate at GCC.
 788          */
 789         wmb();
 790 }
 791
 792 /*
 793  * sdhci_msm_hc_select_mode :- In general all timing modes are
 794  * controlled via UHS mode select in Host Control2 register.
 795  * eMMC specific HS200/HS400 doesn't have their respective modes
 796  * defined here, hence we use these values.
 797  *
 798  * HS200 - SDR104 (Since they both are equivalent in functionality)
 799  * HS400 - This involves multiple configurations
 800  *              Initially SDR104 - when tuning is required as HS200
 801  *              Then when switching to DDR @ 400MHz (HS400) we use
 802  *              the vendor specific HC_SELECT_IN to control the mode.
 803  *
 804  * In addition to controlling the modes we also need to select the
 805  * correct input clock for DLL depending on the mode.
 806  *
 807  * HS400 - divided clock (free running MCLK/2)
 808  * All other modes - default (free running MCLK)
 809  */
 810 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
 811 {
 812         struct mmc_ios ios = host->mmc->ios;
 813
 814         if (ios.timing == MMC_TIMING_MMC_HS400 ||
 815             host->flags & SDHCI_HS400_TUNING)
 816                 msm_hc_select_hs400(host);
 817         else
 818                 msm_hc_select_default(host);
 819 }
 820
 821 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
 822 {
 823         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 824         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 825         u32 config, calib_done;
 826         int ret;
 827         const struct sdhci_msm_offset *msm_offset =
 828                                         msm_host->offset;
 829
 830         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 831
 832         /*
 833          * Retuning in HS400 (DDR mode) will fail, just reset the
 834          * tuning block and restore the saved tuning phase.
 835          */
 836         ret = msm_init_cm_dll(host);
 837         if (ret)
 838                 goto out;
 839
 840         /* Set the selected phase in delay line hw block */
 841         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
 842         if (ret)
 843                 goto out;
 844
 845         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 846         config |= CORE_CMD_DAT_TRACK_SEL;
 847         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 848
 849         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 850         config &= ~CORE_CDC_T4_DLY_SEL;
 851         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 852
 853         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 854         config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
 855         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 856
 857         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 858         config |= CORE_CDC_SWITCH_RC_EN;
 859         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 860
 861         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 862         config &= ~CORE_START_CDC_TRAFFIC;
 863         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 864
 865         /* Perform CDC Register Initialization Sequence */
 866
 867         writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 868         writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
 869         writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 870         writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
 871         writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
 872         writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
 873         writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
 874         writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
 875         writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
 876
 877         /* CDC HW Calibration */
 878
 879         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 880         config |= CORE_SW_TRIG_FULL_CALIB;
 881         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 882
 883         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 884         config &= ~CORE_SW_TRIG_FULL_CALIB;
 885         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 886
 887         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 888         config |= CORE_HW_AUTOCAL_ENA;
 889         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 890
 891         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 892         config |= CORE_TIMER_ENA;
 893         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 894
 895         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
 896                                          calib_done,
 897                                          (calib_done & CORE_CALIBRATION_DONE),
 898                                          1, 50);
 899
 900         if (ret == -ETIMEDOUT) {
 901                 pr_err("%s: %s: CDC calibration was not completed\n",
 902                        mmc_hostname(host->mmc), __func__);
 903                 goto out;
 904         }
 905
 906         ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
 907                         & CORE_CDC_ERROR_CODE_MASK;
 908         if (ret) {
 909                 pr_err("%s: %s: CDC error code %d\n",
 910                        mmc_hostname(host->mmc), __func__, ret);
 911                 ret = -EINVAL;
 912                 goto out;
 913         }
 914
 915         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 916         config |= CORE_START_CDC_TRAFFIC;
 917         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 918 out:
 919         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 920                  __func__, ret);
 921         return ret;
 922 }
 923
 924 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
 925 {
 926         struct mmc_host *mmc = host->mmc;
 927         u32 dll_status, config;
 928         int ret;
 929         const struct sdhci_msm_offset *msm_offset =
 930                                         sdhci_priv_msm_offset(host);
 931
 932         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 933
 934         /*
 935          * Currently the core_ddr_config register defaults to desired
 936          * configuration on reset. Currently reprogramming the power on
 937          * reset (POR) value in case it might have been modified by
 938          * bootloaders. In the future, if this changes, then the desired
 939          * values will need to be programmed appropriately.
 940          */
 941         writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr +
 942                         msm_offset->core_ddr_config);
 943
 944         if (mmc->ios.enhanced_strobe) {
 945                 config = readl_relaxed(host->ioaddr +
 946                                 msm_offset->core_ddr_200_cfg);
 947                 config |= CORE_CMDIN_RCLK_EN;
 948                 writel_relaxed(config, host->ioaddr +
 949                                 msm_offset->core_ddr_200_cfg);
 950         }
 951
 952         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
 953         config |= CORE_DDR_CAL_EN;
 954         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
 955
 956         ret = readl_relaxed_poll_timeout(host->ioaddr +
 957                                         msm_offset->core_dll_status,
 958                                         dll_status,
 959                                         (dll_status & CORE_DDR_DLL_LOCK),
 960                                         10, 1000);
 961
 962         if (ret == -ETIMEDOUT) {
 963                 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
 964                        mmc_hostname(host->mmc), __func__);
 965                 goto out;
 966         }
 967
 968         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
 969         config |= CORE_PWRSAVE_DLL;
 970         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
 971
 972         /*
 973          * Drain writebuffer to ensure above DLL calibration
 974          * and PWRSAVE DLL is enabled.
 975          */
 976         wmb();
 977 out:
 978         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 979                  __func__, ret);
 980         return ret;
 981 }
 982
 983 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
 984 {
 985         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 986         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 987         struct mmc_host *mmc = host->mmc;
 988         int ret;
 989         u32 config;
 990         const struct sdhci_msm_offset *msm_offset =
 991                                         msm_host->offset;
 992
 993         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 994
 995         /*
 996          * Retuning in HS400 (DDR mode) will fail, just reset the
 997          * tuning block and restore the saved tuning phase.
 998          */
 999         ret = msm_init_cm_dll(host);
1000         if (ret)
1001                 goto out;
1002
1003         if (!mmc->ios.enhanced_strobe) {
1004                 /* Set the selected phase in delay line hw block */
1005                 ret = msm_config_cm_dll_phase(host,
1006                                               msm_host->saved_tuning_phase);
1007                 if (ret)
1008                         goto out;
1009                 config = readl_relaxed(host->ioaddr +
1010                                 msm_offset->core_dll_config);
1011                 config |= CORE_CMD_DAT_TRACK_SEL;
1012                 writel_relaxed(config, host->ioaddr +
1013                                 msm_offset->core_dll_config);
1014         }
1015
1016         if (msm_host->use_cdclp533)
1017                 ret = sdhci_msm_cdclp533_calibration(host);
1018         else
1019                 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1020 out:
1021         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1022                  __func__, ret);
1023         return ret;
1024 }
1025
1026 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1027 {
1028         struct mmc_ios *ios = &host->mmc->ios;
1029
1030         /*
1031          * Tuning is required for SDR104, HS200 and HS400 cards and
1032          * if clock frequency is greater than 100MHz in these modes.
1033          */
1034         if (host->clock <= CORE_FREQ_100MHZ ||
1035             !(ios->timing == MMC_TIMING_MMC_HS400 ||
1036             ios->timing == MMC_TIMING_MMC_HS200 ||
1037             ios->timing == MMC_TIMING_UHS_SDR104) ||
1038             ios->enhanced_strobe)
1039                 return false;
1040
1041         return true;
1042 }
1043
1044 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1045 {
1046         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1047         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1048         int ret;
1049
1050         /*
1051          * SDR DLL comes into picture only for timing modes which needs
1052          * tuning.
1053          */
1054         if (!sdhci_msm_is_tuning_needed(host))
1055                 return 0;
1056
1057         /* Reset the tuning block */
1058         ret = msm_init_cm_dll(host);
1059         if (ret)
1060                 return ret;
1061
1062         /* Restore the tuning block */
1063         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1064
1065         return ret;
1066 }
1067
1068 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1069 {
1070         const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1071         u32 config, oldconfig = readl_relaxed(host->ioaddr +
1072                                               msm_offset->core_dll_config);
1073
1074         config = oldconfig;
1075         if (enable) {
1076                 config |= CORE_CDR_EN;
1077                 config &= ~CORE_CDR_EXT_EN;
1078         } else {
1079                 config &= ~CORE_CDR_EN;
1080                 config |= CORE_CDR_EXT_EN;
1081         }
1082
1083         if (config != oldconfig) {
1084                 writel_relaxed(config, host->ioaddr +
1085                                msm_offset->core_dll_config);
1086         }
1087 }
1088
1089 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1090 {
1091         struct sdhci_host *host = mmc_priv(mmc);
1092         int tuning_seq_cnt = 3;
1093         u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1094         int rc;
1095         struct mmc_ios ios = host->mmc->ios;
1096         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1097         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1098
1099         if (!sdhci_msm_is_tuning_needed(host)) {
1100                 msm_host->use_cdr = false;
1101                 sdhci_msm_set_cdr(host, false);
1102                 return 0;
1103         }
1104
1105         /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1106         msm_host->use_cdr = true;
1107
1108         /*
1109          * For HS400 tuning in HS200 timing requires:
1110          * - select MCLK/2 in VENDOR_SPEC
1111          * - program MCLK to 400MHz (or nearest supported) in GCC
1112          */
1113         if (host->flags & SDHCI_HS400_TUNING) {
1114                 sdhci_msm_hc_select_mode(host);
1115                 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1116                 host->flags &= ~SDHCI_HS400_TUNING;
1117         }
1118
1119 retry:
1120         /* First of all reset the tuning block */
1121         rc = msm_init_cm_dll(host);
1122         if (rc)
1123                 return rc;
1124
1125         phase = 0;
1126         do {
1127                 /* Set the phase in delay line hw block */
1128                 rc = msm_config_cm_dll_phase(host, phase);
1129                 if (rc)
1130                         return rc;
1131
1132                 rc = mmc_send_tuning(mmc, opcode, NULL);
1133                 if (!rc) {
1134                         /* Tuning is successful at this tuning point */
1135                         tuned_phases[tuned_phase_cnt++] = phase;
1136                         dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1137                                  mmc_hostname(mmc), phase);
1138                 }
1139         } while (++phase < ARRAY_SIZE(tuned_phases));
1140
1141         if (tuned_phase_cnt) {
1142                 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1143                                                      tuned_phase_cnt);
1144                 if (rc < 0)
1145                         return rc;
1146                 else
1147                         phase = rc;
1148
1149                 /*
1150                  * Finally set the selected phase in delay
1151                  * line hw block.
1152                  */
1153                 rc = msm_config_cm_dll_phase(host, phase);
1154                 if (rc)
1155                         return rc;
1156                 msm_host->saved_tuning_phase = phase;
1157                 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1158                          mmc_hostname(mmc), phase);
1159         } else {
1160                 if (--tuning_seq_cnt)
1161                         goto retry;
1162                 /* Tuning failed */
1163                 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1164                        mmc_hostname(mmc));
1165                 rc = -EIO;
1166         }
1167
1168         if (!rc)
1169                 msm_host->tuning_done = true;
1170         return rc;
1171 }
1172
1173 /*
1174  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1175  * This needs to be done for both tuning and enhanced_strobe mode.
1176  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1177  * fixed feedback clock is used.
1178  */
1179 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1180 {
1181         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1182         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1183         int ret;
1184
1185         if (host->clock > CORE_FREQ_100MHZ &&
1186             (msm_host->tuning_done || ios->enhanced_strobe) &&
1187             !msm_host->calibration_done) {
1188                 ret = sdhci_msm_hs400_dll_calibration(host);
1189                 if (!ret)
1190                         msm_host->calibration_done = true;
1191                 else
1192                         pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1193                                mmc_hostname(host->mmc), ret);
1194         }
1195 }
1196
1197 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1198                                         unsigned int uhs)
1199 {
1200         struct mmc_host *mmc = host->mmc;
1201         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1202         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1203         u16 ctrl_2;
1204         u32 config;
1205         const struct sdhci_msm_offset *msm_offset =
1206                                         msm_host->offset;
1207
1208         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1209         /* Select Bus Speed Mode for host */
1210         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1211         switch (uhs) {
1212         case MMC_TIMING_UHS_SDR12:
1213                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1214                 break;
1215         case MMC_TIMING_UHS_SDR25:
1216                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1217                 break;
1218         case MMC_TIMING_UHS_SDR50:
1219                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1220                 break;
1221         case MMC_TIMING_MMC_HS400:
1222         case MMC_TIMING_MMC_HS200:
1223         case MMC_TIMING_UHS_SDR104:
1224                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1225                 break;
1226         case MMC_TIMING_UHS_DDR50:
1227         case MMC_TIMING_MMC_DDR52:
1228                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1229                 break;
1230         }
1231
1232         /*
1233          * When clock frequency is less than 100MHz, the feedback clock must be
1234          * provided and DLL must not be used so that tuning can be skipped. To
1235          * provide feedback clock, the mode selection can be any value less
1236          * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1237          */
1238         if (host->clock <= CORE_FREQ_100MHZ) {
1239                 if (uhs == MMC_TIMING_MMC_HS400 ||
1240                     uhs == MMC_TIMING_MMC_HS200 ||
1241                     uhs == MMC_TIMING_UHS_SDR104)
1242                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1243                 /*
1244                  * DLL is not required for clock <= 100MHz
1245                  * Thus, make sure DLL it is disabled when not required
1246                  */
1247                 config = readl_relaxed(host->ioaddr +
1248                                 msm_offset->core_dll_config);
1249                 config |= CORE_DLL_RST;
1250                 writel_relaxed(config, host->ioaddr +
1251                                 msm_offset->core_dll_config);
1252
1253                 config = readl_relaxed(host->ioaddr +
1254                                 msm_offset->core_dll_config);
1255                 config |= CORE_DLL_PDN;
1256                 writel_relaxed(config, host->ioaddr +
1257                                 msm_offset->core_dll_config);
1258
1259                 /*
1260                  * The DLL needs to be restored and CDCLP533 recalibrated
1261                  * when the clock frequency is set back to 400MHz.
1262                  */
1263                 msm_host->calibration_done = false;
1264         }
1265
1266         dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1267                 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1268         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1269
1270         if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1271                 sdhci_msm_hs400(host, &mmc->ios);
1272 }
1273
1274 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1275 {
1276         init_waitqueue_head(&msm_host->pwr_irq_wait);
1277 }
1278
1279 static inline void sdhci_msm_complete_pwr_irq_wait(
1280                 struct sdhci_msm_host *msm_host)
1281 {
1282         wake_up(&msm_host->pwr_irq_wait);
1283 }
1284
1285 /*
1286  * sdhci_msm_check_power_status API should be called when registers writes
1287  * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1288  * To what state the register writes will change the IO lines should be passed
1289  * as the argument req_type. This API will check whether the IO line's state
1290  * is already the expected state and will wait for power irq only if
1291  * power irq is expected to be trigerred based on the current IO line state
1292  * and expected IO line state.
1293  */
1294 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1295 {
1296         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1297         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1298         bool done = false;
1299         u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1300         const struct sdhci_msm_offset *msm_offset =
1301                                         msm_host->offset;
1302
1303         pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1304                         mmc_hostname(host->mmc), __func__, req_type,
1305                         msm_host->curr_pwr_state, msm_host->curr_io_level);
1306
1307         /*
1308          * The power interrupt will not be generated for signal voltage
1309          * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1310          * Since sdhci-msm-v5, this bit has been removed and SW must consider
1311          * it as always set.
1312          */
1313         if (!msm_host->mci_removed)
1314                 val = msm_host_readl(msm_host, host,
1315                                 msm_offset->core_generics);
1316         if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1317             !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1318                 return;
1319         }
1320
1321         /*
1322          * The IRQ for request type IO High/LOW will be generated when -
1323          * there is a state change in 1.8V enable bit (bit 3) of
1324          * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1325          * which indicates 3.3V IO voltage. So, when MMC core layer tries
1326          * to set it to 3.3V before card detection happens, the
1327          * IRQ doesn't get triggered as there is no state change in this bit.
1328          * The driver already handles this case by changing the IO voltage
1329          * level to high as part of controller power up sequence. Hence, check
1330          * for host->pwr to handle a case where IO voltage high request is
1331          * issued even before controller power up.
1332          */
1333         if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1334                 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1335                                 mmc_hostname(host->mmc), req_type);
1336                 return;
1337         }
1338         if ((req_type & msm_host->curr_pwr_state) ||
1339                         (req_type & msm_host->curr_io_level))
1340                 done = true;
1341         /*
1342          * This is needed here to handle cases where register writes will
1343          * not change the current bus state or io level of the controller.
1344          * In this case, no power irq will be triggerred and we should
1345          * not wait.
1346          */
1347         if (!done) {
1348                 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1349                                 msm_host->pwr_irq_flag,
1350                                 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1351                         dev_warn(&msm_host->pdev->dev,
1352                                  "%s: pwr_irq for req: (%d) timed out\n",
1353                                  mmc_hostname(host->mmc), req_type);
1354         }
1355         pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1356                         __func__, req_type);
1357 }
1358
1359 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1360 {
1361         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1362         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1363         const struct sdhci_msm_offset *msm_offset =
1364                                         msm_host->offset;
1365
1366         pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1367                 mmc_hostname(host->mmc),
1368                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1369                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1370                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1371 }
1372
1373 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1374 {
1375         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1376         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1377         u32 irq_status, irq_ack = 0;
1378         int retry = 10;
1379         u32 pwr_state = 0, io_level = 0;
1380         u32 config;
1381         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1382
1383         irq_status = msm_host_readl(msm_host, host,
1384                         msm_offset->core_pwrctl_status);
1385         irq_status &= INT_MASK;
1386
1387         msm_host_writel(msm_host, irq_status, host,
1388                         msm_offset->core_pwrctl_clear);
1389
1390         /*
1391          * There is a rare HW scenario where the first clear pulse could be
1392          * lost when actual reset and clear/read of status register is
1393          * happening at a time. Hence, retry for at least 10 times to make
1394          * sure status register is cleared. Otherwise, this will result in
1395          * a spurious power IRQ resulting in system instability.
1396          */
1397         while (irq_status & msm_host_readl(msm_host, host,
1398                                 msm_offset->core_pwrctl_status)) {
1399                 if (retry == 0) {
1400                         pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1401                                         mmc_hostname(host->mmc), irq_status);
1402                         sdhci_msm_dump_pwr_ctrl_regs(host);
1403                         WARN_ON(1);
1404                         break;
1405                 }
1406                 msm_host_writel(msm_host, irq_status, host,
1407                         msm_offset->core_pwrctl_clear);
1408                 retry--;
1409                 udelay(10);
1410         }
1411
1412         /* Handle BUS ON/OFF*/
1413         if (irq_status & CORE_PWRCTL_BUS_ON) {
1414                 pwr_state = REQ_BUS_ON;
1415                 io_level = REQ_IO_HIGH;
1416                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1417         }
1418         if (irq_status & CORE_PWRCTL_BUS_OFF) {
1419                 pwr_state = REQ_BUS_OFF;
1420                 io_level = REQ_IO_LOW;
1421                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1422         }
1423         /* Handle IO LOW/HIGH */
1424         if (irq_status & CORE_PWRCTL_IO_LOW) {
1425                 io_level = REQ_IO_LOW;
1426                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1427         }
1428         if (irq_status & CORE_PWRCTL_IO_HIGH) {
1429                 io_level = REQ_IO_HIGH;
1430                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1431         }
1432
1433         /*
1434          * The driver has to acknowledge the interrupt, switch voltages and
1435          * report back if it succeded or not to this register. The voltage
1436          * switches are handled by the sdhci core, so just report success.
1437          */
1438         msm_host_writel(msm_host, irq_ack, host,
1439                         msm_offset->core_pwrctl_ctl);
1440
1441         /*
1442          * If we don't have info regarding the voltage levels supported by
1443          * regulators, don't change the IO PAD PWR SWITCH.
1444          */
1445         if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1446                 u32 new_config;
1447                 /*
1448                  * We should unset IO PAD PWR switch only if the register write
1449                  * can set IO lines high and the regulator also switches to 3 V.
1450                  * Else, we should keep the IO PAD PWR switch set.
1451                  * This is applicable to certain targets where eMMC vccq supply
1452                  * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1453                  * IO PAD PWR switch must be kept set to reflect actual
1454                  * regulator voltage. This way, during initialization of
1455                  * controllers with only 1.8V, we will set the IO PAD bit
1456                  * without waiting for a REQ_IO_LOW.
1457                  */
1458                 config = readl_relaxed(host->ioaddr +
1459                                 msm_offset->core_vendor_spec);
1460                 new_config = config;
1461
1462                 if ((io_level & REQ_IO_HIGH) &&
1463                                 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1464                         new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1465                 else if ((io_level & REQ_IO_LOW) ||
1466                                 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1467                         new_config |= CORE_IO_PAD_PWR_SWITCH;
1468
1469                 if (config ^ new_config)
1470                         writel_relaxed(new_config, host->ioaddr +
1471                                         msm_offset->core_vendor_spec);
1472         }
1473
1474         if (pwr_state)
1475                 msm_host->curr_pwr_state = pwr_state;
1476         if (io_level)
1477                 msm_host->curr_io_level = io_level;
1478
1479         pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1480                 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1481                 irq_ack);
1482 }
1483
1484 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1485 {
1486         struct sdhci_host *host = (struct sdhci_host *)data;
1487         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1488         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1489
1490         sdhci_msm_handle_pwr_irq(host, irq);
1491         msm_host->pwr_irq_flag = 1;
1492         sdhci_msm_complete_pwr_irq_wait(msm_host);
1493
1494
1495         return IRQ_HANDLED;
1496 }
1497
1498 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1499 {
1500         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1501         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1502         struct clk *core_clk = msm_host->bulk_clks[0].clk;
1503
1504         return clk_round_rate(core_clk, ULONG_MAX);
1505 }
1506
1507 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1508 {
1509         return SDHCI_MSM_MIN_CLOCK;
1510 }
1511
1512 /**
1513  * __sdhci_msm_set_clock - sdhci_msm clock control.
1514  *
1515  * Description:
1516  * MSM controller does not use internal divider and
1517  * instead directly control the GCC clock as per
1518  * HW recommendation.
1519  **/
1520 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1521 {
1522         u16 clk;
1523         /*
1524          * Keep actual_clock as zero -
1525          * - since there is no divider used so no need of having actual_clock.
1526          * - MSM controller uses SDCLK for data timeout calculation. If
1527          *   actual_clock is zero, host->clock is taken for calculation.
1528          */
1529         host->mmc->actual_clock = 0;
1530
1531         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1532
1533         if (clock == 0)
1534                 return;
1535
1536         /*
1537          * MSM controller do not use clock divider.
1538          * Thus read SDHCI_CLOCK_CONTROL and only enable
1539          * clock with no divider value programmed.
1540          */
1541         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1542         sdhci_enable_clk(host, clk);
1543 }
1544
1545 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1546 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1547 {
1548         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1549         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1550
1551         if (!clock) {
1552                 msm_host->clk_rate = clock;
1553                 goto out;
1554         }
1555
1556         sdhci_msm_hc_select_mode(host);
1557
1558         msm_set_clock_rate_for_bus_mode(host, clock);
1559 out:
1560         __sdhci_msm_set_clock(host, clock);
1561 }
1562
1563 /*
1564  * Platform specific register write functions. This is so that, if any
1565  * register write needs to be followed up by platform specific actions,
1566  * they can be added here. These functions can go to sleep when writes
1567  * to certain registers are done.
1568  * These functions are relying on sdhci_set_ios not using spinlock.
1569  */
1570 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1571 {
1572         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1573         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1574         u32 req_type = 0;
1575
1576         switch (reg) {
1577         case SDHCI_HOST_CONTROL2:
1578                 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1579                         REQ_IO_HIGH;
1580                 break;
1581         case SDHCI_SOFTWARE_RESET:
1582                 if (host->pwr && (val & SDHCI_RESET_ALL))
1583                         req_type = REQ_BUS_OFF;
1584                 break;
1585         case SDHCI_POWER_CONTROL:
1586                 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1587                 break;
1588         case SDHCI_TRANSFER_MODE:
1589                 msm_host->transfer_mode = val;
1590                 break;
1591         case SDHCI_COMMAND:
1592                 if (!msm_host->use_cdr)
1593                         break;
1594                 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1595                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
1596                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
1597                         sdhci_msm_set_cdr(host, true);
1598                 else
1599                         sdhci_msm_set_cdr(host, false);
1600                 break;
1601         }
1602
1603         if (req_type) {
1604                 msm_host->pwr_irq_flag = 0;
1605                 /*
1606                  * Since this register write may trigger a power irq, ensure
1607                  * all previous register writes are complete by this point.
1608                  */
1609                 mb();
1610         }
1611         return req_type;
1612 }
1613
1614 /* This function may sleep*/
1615 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1616 {
1617         u32 req_type = 0;
1618
1619         req_type = __sdhci_msm_check_write(host, val, reg);
1620         writew_relaxed(val, host->ioaddr + reg);
1621
1622         if (req_type)
1623                 sdhci_msm_check_power_status(host, req_type);
1624 }
1625
1626 /* This function may sleep*/
1627 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1628 {
1629         u32 req_type = 0;
1630
1631         req_type = __sdhci_msm_check_write(host, val, reg);
1632
1633         writeb_relaxed(val, host->ioaddr + reg);
1634
1635         if (req_type)
1636                 sdhci_msm_check_power_status(host, req_type);
1637 }
1638
1639 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1640 {
1641         struct mmc_host *mmc = msm_host->mmc;
1642         struct regulator *supply = mmc->supply.vqmmc;
1643         u32 caps = 0, config;
1644         struct sdhci_host *host = mmc_priv(mmc);
1645         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1646
1647         if (!IS_ERR(mmc->supply.vqmmc)) {
1648                 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1649                         caps |= CORE_1_8V_SUPPORT;
1650                 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1651                         caps |= CORE_3_0V_SUPPORT;
1652
1653                 if (!caps)
1654                         pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1655                                         mmc_hostname(mmc));
1656         }
1657
1658         if (caps) {
1659                 /*
1660                  * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
1661                  * bit can be used as required later on.
1662                  */
1663                 u32 io_level = msm_host->curr_io_level;
1664
1665                 config = readl_relaxed(host->ioaddr +
1666                                 msm_offset->core_vendor_spec);
1667                 config |= CORE_IO_PAD_PWR_SWITCH_EN;
1668
1669                 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
1670                         config &= ~CORE_IO_PAD_PWR_SWITCH;
1671                 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
1672                         config |= CORE_IO_PAD_PWR_SWITCH;
1673
1674                 writel_relaxed(config,
1675                                 host->ioaddr + msm_offset->core_vendor_spec);
1676         }
1677         msm_host->caps_0 |= caps;
1678         pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
1679 }
1680
1681 static const struct sdhci_msm_variant_ops mci_var_ops = {
1682         .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
1683         .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
1684 };
1685
1686 static const struct sdhci_msm_variant_ops v5_var_ops = {
1687         .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
1688         .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
1689 };
1690
1691 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
1692         .var_ops = &mci_var_ops,
1693         .offset = &sdhci_msm_mci_offset,
1694 };
1695
1696 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
1697         .mci_removed = true,
1698         .var_ops = &v5_var_ops,
1699         .offset = &sdhci_msm_v5_offset,
1700 };
1701
1702 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
1703         .mci_removed = true,
1704         .restore_dll_config = true,
1705         .var_ops = &v5_var_ops,
1706         .offset = &sdhci_msm_v5_offset,
1707 };
1708
1709 static const struct of_device_id sdhci_msm_dt_match[] = {
1710         {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
1711         {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
1712         {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
1713         {},
1714 };
1715
1716 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1717
1718 static const struct sdhci_ops sdhci_msm_ops = {
1719         .reset = sdhci_reset,
1720         .set_clock = sdhci_msm_set_clock,
1721         .get_min_clock = sdhci_msm_get_min_clock,
1722         .get_max_clock = sdhci_msm_get_max_clock,
1723         .set_bus_width = sdhci_set_bus_width,
1724         .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1725         .write_w = sdhci_msm_writew,
1726         .write_b = sdhci_msm_writeb,
1727 };
1728
1729 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1730         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1731                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1732                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1733         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1734         .ops = &sdhci_msm_ops,
1735 };
1736
1737 static int sdhci_msm_probe(struct platform_device *pdev)
1738 {
1739         struct sdhci_host *host;
1740         struct sdhci_pltfm_host *pltfm_host;
1741         struct sdhci_msm_host *msm_host;
1742         struct resource *core_memres;
1743         struct clk *clk;
1744         int ret;
1745         u16 host_version, core_minor;
1746         u32 core_version, config;
1747         u8 core_major;
1748         const struct sdhci_msm_offset *msm_offset;
1749         const struct sdhci_msm_variant_info *var_info;
1750
1751         host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1752         if (IS_ERR(host))
1753                 return PTR_ERR(host);
1754
1755         host->sdma_boundary = 0;
1756         pltfm_host = sdhci_priv(host);
1757         msm_host = sdhci_pltfm_priv(pltfm_host);
1758         msm_host->mmc = host->mmc;
1759         msm_host->pdev = pdev;
1760
1761         ret = mmc_of_parse(host->mmc);
1762         if (ret)
1763                 goto pltfm_free;
1764
1765         /*
1766          * Based on the compatible string, load the required msm host info from
1767          * the data associated with the version info.
1768          */
1769         var_info = of_device_get_match_data(&pdev->dev);
1770
1771         msm_host->mci_removed = var_info->mci_removed;
1772         msm_host->restore_dll_config = var_info->restore_dll_config;
1773         msm_host->var_ops = var_info->var_ops;
1774         msm_host->offset = var_info->offset;
1775
1776         msm_offset = msm_host->offset;
1777
1778         sdhci_get_of_property(pdev);
1779
1780         msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1781
1782         /* Setup SDCC bus voter clock. */
1783         msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1784         if (!IS_ERR(msm_host->bus_clk)) {
1785                 /* Vote for max. clk rate for max. performance */
1786                 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1787                 if (ret)
1788                         goto pltfm_free;
1789                 ret = clk_prepare_enable(msm_host->bus_clk);
1790                 if (ret)
1791                         goto pltfm_free;
1792         }
1793
1794         /* Setup main peripheral bus clock */
1795         clk = devm_clk_get(&pdev->dev, "iface");
1796         if (IS_ERR(clk)) {
1797                 ret = PTR_ERR(clk);
1798                 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1799                 goto bus_clk_disable;
1800         }
1801         msm_host->bulk_clks[1].clk = clk;
1802
1803         /* Setup SDC MMC clock */
1804         clk = devm_clk_get(&pdev->dev, "core");
1805         if (IS_ERR(clk)) {
1806                 ret = PTR_ERR(clk);
1807                 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1808                 goto bus_clk_disable;
1809         }
1810         msm_host->bulk_clks[0].clk = clk;
1811
1812         /* Vote for maximum clock rate for maximum performance */
1813         ret = clk_set_rate(clk, INT_MAX);
1814         if (ret)
1815                 dev_warn(&pdev->dev, "core clock boost failed\n");
1816
1817         clk = devm_clk_get(&pdev->dev, "cal");
1818         if (IS_ERR(clk))
1819                 clk = NULL;
1820         msm_host->bulk_clks[2].clk = clk;
1821
1822         clk = devm_clk_get(&pdev->dev, "sleep");
1823         if (IS_ERR(clk))
1824                 clk = NULL;
1825         msm_host->bulk_clks[3].clk = clk;
1826
1827         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1828                                       msm_host->bulk_clks);
1829         if (ret)
1830                 goto bus_clk_disable;
1831
1832         /*
1833          * xo clock is needed for FLL feature of cm_dll.
1834          * In case if xo clock is not mentioned in DT, warn and proceed.
1835          */
1836         msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1837         if (IS_ERR(msm_host->xo_clk)) {
1838                 ret = PTR_ERR(msm_host->xo_clk);
1839                 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1840         }
1841
1842         if (!msm_host->mci_removed) {
1843                 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1844                 msm_host->core_mem = devm_ioremap_resource(&pdev->dev,
1845                                 core_memres);
1846
1847                 if (IS_ERR(msm_host->core_mem)) {
1848                         ret = PTR_ERR(msm_host->core_mem);
1849                         goto clk_disable;
1850                 }
1851         }
1852
1853         /* Reset the vendor spec register to power on reset state */
1854         writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1855                         host->ioaddr + msm_offset->core_vendor_spec);
1856
1857         if (!msm_host->mci_removed) {
1858                 /* Set HC_MODE_EN bit in HC_MODE register */
1859                 msm_host_writel(msm_host, HC_MODE_EN, host,
1860                                 msm_offset->core_hc_mode);
1861                 config = msm_host_readl(msm_host, host,
1862                                 msm_offset->core_hc_mode);
1863                 config |= FF_CLK_SW_RST_DIS;
1864                 msm_host_writel(msm_host, config, host,
1865                                 msm_offset->core_hc_mode);
1866         }
1867
1868         host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1869         dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1870                 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1871                                SDHCI_VENDOR_VER_SHIFT));
1872
1873         core_version = msm_host_readl(msm_host, host,
1874                         msm_offset->core_mci_version);
1875         core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1876                       CORE_VERSION_MAJOR_SHIFT;
1877         core_minor = core_version & CORE_VERSION_MINOR_MASK;
1878         dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1879                 core_version, core_major, core_minor);
1880
1881         if (core_major == 1 && core_minor >= 0x42)
1882                 msm_host->use_14lpp_dll_reset = true;
1883
1884         /*
1885          * SDCC 5 controller with major version 1, minor version 0x34 and later
1886          * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1887          */
1888         if (core_major == 1 && core_minor < 0x34)
1889                 msm_host->use_cdclp533 = true;
1890
1891         /*
1892          * Support for some capabilities is not advertised by newer
1893          * controller versions and must be explicitly enabled.
1894          */
1895         if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1896                 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1897                 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1898                 writel_relaxed(config, host->ioaddr +
1899                                 msm_offset->core_vendor_spec_capabilities0);
1900         }
1901
1902         /*
1903          * Power on reset state may trigger power irq if previous status of
1904          * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1905          * interrupt in GIC, any pending power irq interrupt should be
1906          * acknowledged. Otherwise power irq interrupt handler would be
1907          * fired prematurely.
1908          */
1909         sdhci_msm_handle_pwr_irq(host, 0);
1910
1911         /*
1912          * Ensure that above writes are propogated before interrupt enablement
1913          * in GIC.
1914          */
1915         mb();
1916
1917         /* Setup IRQ for handling power/voltage tasks with PMIC */
1918         msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1919         if (msm_host->pwr_irq < 0) {
1920                 ret = msm_host->pwr_irq;
1921                 goto clk_disable;
1922         }
1923
1924         sdhci_msm_init_pwr_irq_wait(msm_host);
1925         /* Enable pwr irq interrupts */
1926         msm_host_writel(msm_host, INT_MASK, host,
1927                 msm_offset->core_pwrctl_mask);
1928
1929         ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1930                                         sdhci_msm_pwr_irq, IRQF_ONESHOT,
1931                                         dev_name(&pdev->dev), host);
1932         if (ret) {
1933                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1934                 goto clk_disable;
1935         }
1936
1937         pm_runtime_get_noresume(&pdev->dev);
1938         pm_runtime_set_active(&pdev->dev);
1939         pm_runtime_enable(&pdev->dev);
1940         pm_runtime_set_autosuspend_delay(&pdev->dev,
1941                                          MSM_MMC_AUTOSUSPEND_DELAY_MS);
1942         pm_runtime_use_autosuspend(&pdev->dev);
1943
1944         host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1945         ret = sdhci_add_host(host);
1946         if (ret)
1947                 goto pm_runtime_disable;
1948         sdhci_msm_set_regulator_caps(msm_host);
1949
1950         pm_runtime_mark_last_busy(&pdev->dev);
1951         pm_runtime_put_autosuspend(&pdev->dev);
1952
1953         return 0;
1954
1955 pm_runtime_disable:
1956         pm_runtime_disable(&pdev->dev);
1957         pm_runtime_set_suspended(&pdev->dev);
1958         pm_runtime_put_noidle(&pdev->dev);
1959 clk_disable:
1960         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1961                                    msm_host->bulk_clks);
1962 bus_clk_disable:
1963         if (!IS_ERR(msm_host->bus_clk))
1964                 clk_disable_unprepare(msm_host->bus_clk);
1965 pltfm_free:
1966         sdhci_pltfm_free(pdev);
1967         return ret;
1968 }
1969
1970 static int sdhci_msm_remove(struct platform_device *pdev)
1971 {
1972         struct sdhci_host *host = platform_get_drvdata(pdev);
1973         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1974         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1975         int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1976                     0xffffffff);
1977
1978         sdhci_remove_host(host, dead);
1979
1980         pm_runtime_get_sync(&pdev->dev);
1981         pm_runtime_disable(&pdev->dev);
1982         pm_runtime_put_noidle(&pdev->dev);
1983
1984         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1985                                    msm_host->bulk_clks);
1986         if (!IS_ERR(msm_host->bus_clk))
1987                 clk_disable_unprepare(msm_host->bus_clk);
1988         sdhci_pltfm_free(pdev);
1989         return 0;
1990 }
1991
1992 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
1993 {
1994         struct sdhci_host *host = dev_get_drvdata(dev);
1995         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1996         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1997
1998         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1999                                    msm_host->bulk_clks);
2000
2001         return 0;
2002 }
2003
2004 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2005 {
2006         struct sdhci_host *host = dev_get_drvdata(dev);
2007         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2008         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2009         int ret;
2010
2011         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2012                                        msm_host->bulk_clks);
2013         if (ret)
2014                 return ret;
2015         /*
2016          * Whenever core-clock is gated dynamically, it's needed to
2017          * restore the SDR DLL settings when the clock is ungated.
2018          */
2019         if (msm_host->restore_dll_config && msm_host->clk_rate)
2020                 return sdhci_msm_restore_sdr_dll_config(host);
2021
2022         return 0;
2023 }
2024
2025 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2026         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2027                                 pm_runtime_force_resume)
2028         SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2029                            sdhci_msm_runtime_resume,
2030                            NULL)
2031 };
2032
2033 static struct platform_driver sdhci_msm_driver = {
2034         .probe = sdhci_msm_probe,
2035         .remove = sdhci_msm_remove,
2036         .driver = {
2037                    .name = "sdhci_msm",
2038                    .of_match_table = sdhci_msm_dt_match,
2039                    .pm = &sdhci_msm_pm_ops,
2040         },
2041 };
2042
2043 module_platform_driver(sdhci_msm_driver);
2044
2045 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2046 MODULE_LICENSE("GPL v2");