1 // SPDX-License-Identifier: GPL-2.0-only
3 * Atmel SDMMC controller driver.
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
10 #include <linux/delay.h>
11 #include <linux/err.h>
13 #include <linux/kernel.h>
14 #include <linux/mmc/host.h>
15 #include <linux/mmc/slot-gpio.h>
16 #include <linux/module.h>
18 #include <linux/of_device.h>
20 #include <linux/pm_runtime.h>
22 #include "sdhci-pltfm.h"
24 #define SDMMC_MC1R 0x204
25 #define SDMMC_MC1R_DDR BIT(3)
26 #define SDMMC_MC1R_FCD BIT(7)
27 #define SDMMC_CACR 0x230
28 #define SDMMC_CACR_CAPWREN BIT(0)
29 #define SDMMC_CACR_KEY (0x46 << 8)
30 #define SDMMC_CALCR 0x240
31 #define SDMMC_CALCR_EN BIT(0)
32 #define SDMMC_CALCR_ALWYSON BIT(4)
34 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
36 struct sdhci_at91_soc_data {
37 const struct sdhci_pltfm_data *pdata;
38 bool baseclk_is_generated_internally;
39 unsigned int divider_for_baseclk;
42 struct sdhci_at91_priv {
43 const struct sdhci_at91_soc_data *soc_data;
51 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
55 mc1r = readb(host->ioaddr + SDMMC_MC1R);
56 mc1r |= SDMMC_MC1R_FCD;
57 writeb(mc1r, host->ioaddr + SDMMC_MC1R);
60 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
63 unsigned long timeout;
65 host->mmc->actual_clock = 0;
68 * There is no requirement to disable the internal clock before
69 * changing the SD clock configuration. Moreover, disabling the
70 * internal clock, changing the configuration and re-enabling the
71 * internal clock causes some bugs. It can prevent to get the internal
72 * clock stable flag ready and an unexpected switch to the base clock
75 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
76 clk &= SDHCI_CLOCK_INT_EN;
77 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
82 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
84 clk |= SDHCI_CLOCK_INT_EN;
85 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
89 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
90 & SDHCI_CLOCK_INT_STABLE)) {
92 pr_err("%s: Internal clock never stabilised.\n",
93 mmc_hostname(host->mmc));
100 clk |= SDHCI_CLOCK_CARD_EN;
101 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
105 * In this specific implementation of the SDHCI controller, the power register
106 * needs to have a valid voltage set even when the power supply is managed by
107 * an external regulator.
109 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
112 if (!IS_ERR(host->mmc->supply.vmmc)) {
113 struct mmc_host *mmc = host->mmc;
115 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
117 sdhci_set_power_noreg(host, mode, vdd);
120 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
123 if (timing == MMC_TIMING_MMC_DDR52)
124 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
125 sdhci_set_uhs_signaling(host, timing);
128 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
130 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
131 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
133 sdhci_reset(host, mask);
135 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
136 || mmc_gpio_get_cd(host->mmc) >= 0)
137 sdhci_at91_set_force_card_detect(host);
139 if (priv->cal_always_on && (mask & SDHCI_RESET_ALL))
140 sdhci_writel(host, SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN,
144 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
145 .set_clock = sdhci_at91_set_clock,
146 .set_bus_width = sdhci_set_bus_width,
147 .reset = sdhci_at91_reset,
148 .set_uhs_signaling = sdhci_at91_set_uhs_signaling,
149 .set_power = sdhci_at91_set_power,
152 static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = {
153 .ops = &sdhci_at91_sama5d2_ops,
156 static const struct sdhci_at91_soc_data soc_data_sama5d2 = {
157 .pdata = &sdhci_sama5d2_pdata,
158 .baseclk_is_generated_internally = false,
161 static const struct sdhci_at91_soc_data soc_data_sam9x60 = {
162 .pdata = &sdhci_sama5d2_pdata,
163 .baseclk_is_generated_internally = true,
164 .divider_for_baseclk = 2,
167 static const struct of_device_id sdhci_at91_dt_match[] = {
168 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
169 { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 },
172 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
174 static int sdhci_at91_set_clks_presets(struct device *dev)
176 struct sdhci_host *host = dev_get_drvdata(dev);
177 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
178 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
179 unsigned int caps0, caps1;
180 unsigned int clk_base, clk_mul;
181 unsigned int gck_rate, clk_base_rate;
182 unsigned int preset_div;
184 clk_prepare_enable(priv->hclock);
185 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
186 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
188 gck_rate = clk_get_rate(priv->gck);
189 if (priv->soc_data->baseclk_is_generated_internally)
190 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk;
192 clk_base_rate = clk_get_rate(priv->mainck);
194 clk_base = clk_base_rate / 1000000;
195 clk_mul = gck_rate / clk_base_rate - 1;
197 caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK;
198 caps0 |= (clk_base << SDHCI_CLOCK_BASE_SHIFT) & SDHCI_CLOCK_V3_BASE_MASK;
199 caps1 &= ~SDHCI_CLOCK_MUL_MASK;
200 caps1 |= (clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK;
201 /* Set capabilities in r/w mode. */
202 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
203 writel(caps0, host->ioaddr + SDHCI_CAPABILITIES);
204 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
205 /* Set capabilities in ro mode. */
206 writel(0, host->ioaddr + SDMMC_CACR);
208 dev_info(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n",
209 clk_mul, gck_rate, clk_base_rate);
212 * We have to set preset values because it depends on the clk_mul
213 * value. Moreover, SDR104 is supported in a degraded mode since the
214 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
215 * reason, we need to use presets to support SDR104.
217 preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1;
218 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
219 host->ioaddr + SDHCI_PRESET_FOR_SDR12);
220 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
221 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
222 host->ioaddr + SDHCI_PRESET_FOR_SDR25);
223 preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1;
224 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
225 host->ioaddr + SDHCI_PRESET_FOR_SDR50);
226 preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1;
227 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
228 host->ioaddr + SDHCI_PRESET_FOR_SDR104);
229 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
230 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
231 host->ioaddr + SDHCI_PRESET_FOR_DDR50);
233 clk_prepare_enable(priv->mainck);
234 clk_prepare_enable(priv->gck);
239 #ifdef CONFIG_PM_SLEEP
240 static int sdhci_at91_suspend(struct device *dev)
242 struct sdhci_host *host = dev_get_drvdata(dev);
243 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
244 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
247 ret = pm_runtime_force_suspend(dev);
249 priv->restore_needed = true;
253 #endif /* CONFIG_PM_SLEEP */
256 static int sdhci_at91_runtime_suspend(struct device *dev)
258 struct sdhci_host *host = dev_get_drvdata(dev);
259 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
260 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
263 ret = sdhci_runtime_suspend_host(host);
265 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
266 mmc_retune_needed(host->mmc);
268 clk_disable_unprepare(priv->gck);
269 clk_disable_unprepare(priv->hclock);
270 clk_disable_unprepare(priv->mainck);
275 static int sdhci_at91_runtime_resume(struct device *dev)
277 struct sdhci_host *host = dev_get_drvdata(dev);
278 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
279 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
282 if (priv->restore_needed) {
283 ret = sdhci_at91_set_clks_presets(dev);
287 priv->restore_needed = false;
291 ret = clk_prepare_enable(priv->mainck);
293 dev_err(dev, "can't enable mainck\n");
297 ret = clk_prepare_enable(priv->hclock);
299 dev_err(dev, "can't enable hclock\n");
303 ret = clk_prepare_enable(priv->gck);
305 dev_err(dev, "can't enable gck\n");
310 return sdhci_runtime_resume_host(host, 0);
312 #endif /* CONFIG_PM */
314 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
315 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
316 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
317 sdhci_at91_runtime_resume,
321 static int sdhci_at91_probe(struct platform_device *pdev)
323 const struct of_device_id *match;
324 const struct sdhci_at91_soc_data *soc_data;
325 struct sdhci_host *host;
326 struct sdhci_pltfm_host *pltfm_host;
327 struct sdhci_at91_priv *priv;
330 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
333 soc_data = match->data;
335 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv));
337 return PTR_ERR(host);
339 pltfm_host = sdhci_priv(host);
340 priv = sdhci_pltfm_priv(pltfm_host);
341 priv->soc_data = soc_data;
343 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
344 if (IS_ERR(priv->mainck)) {
345 if (soc_data->baseclk_is_generated_internally) {
348 dev_err(&pdev->dev, "failed to get baseclk\n");
349 ret = PTR_ERR(priv->mainck);
350 goto sdhci_pltfm_free;
354 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
355 if (IS_ERR(priv->hclock)) {
356 dev_err(&pdev->dev, "failed to get hclock\n");
357 ret = PTR_ERR(priv->hclock);
358 goto sdhci_pltfm_free;
361 priv->gck = devm_clk_get(&pdev->dev, "multclk");
362 if (IS_ERR(priv->gck)) {
363 dev_err(&pdev->dev, "failed to get multclk\n");
364 ret = PTR_ERR(priv->gck);
365 goto sdhci_pltfm_free;
368 ret = sdhci_at91_set_clks_presets(&pdev->dev);
370 goto sdhci_pltfm_free;
372 priv->restore_needed = false;
375 * if SDCAL pin is wrongly connected, we must enable
376 * the analog calibration cell permanently.
378 priv->cal_always_on =
379 device_property_read_bool(&pdev->dev,
380 "microchip,sdcal-inverted");
382 ret = mmc_of_parse(host->mmc);
384 goto clocks_disable_unprepare;
386 sdhci_get_of_property(pdev);
388 pm_runtime_get_noresume(&pdev->dev);
389 pm_runtime_set_active(&pdev->dev);
390 pm_runtime_enable(&pdev->dev);
391 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
392 pm_runtime_use_autosuspend(&pdev->dev);
394 /* HS200 is broken at this moment */
395 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
397 ret = sdhci_add_host(host);
399 goto pm_runtime_disable;
402 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
403 * the assumption that all the clocks of the controller are disabled.
404 * It means we can't get irq from it when it is runtime suspended.
405 * For that reason, it is not planned to wake-up on a card detect irq
406 * from the controller.
407 * If we want to use runtime PM and to be able to wake-up on card
408 * insertion, we have to use a GPIO for the card detection or we can
409 * use polling. Be aware that using polling will resume/suspend the
410 * controller between each attempt.
411 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
412 * to enable polling via device tree with broken-cd property.
414 if (mmc_card_is_removable(host->mmc) &&
415 mmc_gpio_get_cd(host->mmc) < 0) {
416 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
417 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
421 * If the device attached to the MMC bus is not removable, it is safer
422 * to set the Force Card Detect bit. People often don't connect the
423 * card detect signal and use this pin for another purpose. If the card
424 * detect pin is not muxed to SDHCI controller, a default value is
425 * used. This value can be different from a SoC revision to another
426 * one. Problems come when this default value is not card present. To
427 * avoid this case, if the device is non removable then the card
428 * detection procedure using the SDMCC_CD signal is bypassed.
429 * This bit is reset when a software reset for all command is performed
430 * so we need to implement our own reset function to set back this bit.
432 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
434 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
435 || mmc_gpio_get_cd(host->mmc) >= 0)
436 sdhci_at91_set_force_card_detect(host);
438 pm_runtime_put_autosuspend(&pdev->dev);
443 pm_runtime_disable(&pdev->dev);
444 pm_runtime_set_suspended(&pdev->dev);
445 pm_runtime_put_noidle(&pdev->dev);
446 clocks_disable_unprepare:
447 clk_disable_unprepare(priv->gck);
448 clk_disable_unprepare(priv->mainck);
449 clk_disable_unprepare(priv->hclock);
451 sdhci_pltfm_free(pdev);
455 static int sdhci_at91_remove(struct platform_device *pdev)
457 struct sdhci_host *host = platform_get_drvdata(pdev);
458 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
459 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
460 struct clk *gck = priv->gck;
461 struct clk *hclock = priv->hclock;
462 struct clk *mainck = priv->mainck;
464 pm_runtime_get_sync(&pdev->dev);
465 pm_runtime_disable(&pdev->dev);
466 pm_runtime_put_noidle(&pdev->dev);
468 sdhci_pltfm_unregister(pdev);
470 clk_disable_unprepare(gck);
471 clk_disable_unprepare(hclock);
472 clk_disable_unprepare(mainck);
477 static struct platform_driver sdhci_at91_driver = {
479 .name = "sdhci-at91",
480 .of_match_table = sdhci_at91_dt_match,
481 .pm = &sdhci_at91_dev_pm_ops,
483 .probe = sdhci_at91_probe,
484 .remove = sdhci_at91_remove,
487 module_platform_driver(sdhci_at91_driver);
489 MODULE_DESCRIPTION("SDHCI driver for at91");
490 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
491 MODULE_LICENSE("GPL v2");