1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale eSDHC controller driver.
5 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
6 * Copyright (c) 2009 MontaVista Software, Inc.
8 * Authors: Xiaobo Xie <X.Xie@freescale.com>
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 #include <linux/err.h>
15 #include <linux/of_address.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/sys_soc.h>
19 #include <linux/clk.h>
20 #include <linux/ktime.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/mmc.h>
24 #include "sdhci-pltfm.h"
25 #include "sdhci-esdhc.h"
27 #define VENDOR_V_22 0x12
28 #define VENDOR_V_23 0x13
30 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1)
32 struct esdhc_clk_fixup {
33 const unsigned int sd_dflt_max_clk;
34 const unsigned int max_clk[MMC_TIMING_NUM];
37 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
38 .sd_dflt_max_clk = 25000000,
39 .max_clk[MMC_TIMING_MMC_HS] = 46500000,
40 .max_clk[MMC_TIMING_SD_HS] = 46500000,
43 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
44 .sd_dflt_max_clk = 25000000,
45 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
46 .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
49 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = {
50 .sd_dflt_max_clk = 25000000,
51 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
52 .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
55 static const struct esdhc_clk_fixup p1010_esdhc_clk = {
56 .sd_dflt_max_clk = 20000000,
57 .max_clk[MMC_TIMING_LEGACY] = 20000000,
58 .max_clk[MMC_TIMING_MMC_HS] = 42000000,
59 .max_clk[MMC_TIMING_SD_HS] = 40000000,
62 static const struct of_device_id sdhci_esdhc_of_match[] = {
63 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
64 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
65 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
66 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
67 { .compatible = "fsl,mpc8379-esdhc" },
68 { .compatible = "fsl,mpc8536-esdhc" },
69 { .compatible = "fsl,esdhc" },
72 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
77 bool quirk_incorrect_hostver;
78 bool quirk_limited_clk_division;
79 bool quirk_unreliable_pulse_detection;
80 bool quirk_fixup_tuning;
81 bool quirk_ignore_data_inhibit;
82 unsigned int peripheral_clock;
83 const struct esdhc_clk_fixup *clk_fixup;
88 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
89 * to make it compatible with SD spec.
91 * @host: pointer to sdhci_host
92 * @spec_reg: SD spec register address
93 * @value: 32bit eSDHC register value on spec_reg address
95 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
96 * registers are 32 bits. There are differences in register size, register
97 * address, register function, bit position and function between eSDHC spec
100 * Return a fixed up register value
102 static u32 esdhc_readl_fixup(struct sdhci_host *host,
103 int spec_reg, u32 value)
105 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
106 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
110 * The bit of ADMA flag in eSDHC is not compatible with standard
111 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
112 * supported by eSDHC.
113 * And for many FSL eSDHC controller, the reset value of field
114 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
115 * only these vendor version is greater than 2.2/0x12 support ADMA.
117 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
118 if (esdhc->vendor_ver > VENDOR_V_22) {
119 ret = value | SDHCI_CAN_DO_ADMA2;
124 * The DAT[3:0] line signal levels and the CMD line signal level are
125 * not compatible with standard SDHC register. The line signal levels
126 * DAT[7:0] are at bits 31:24 and the command line signal level is at
127 * bit 23. All other bits are the same as in the standard SDHC
130 if (spec_reg == SDHCI_PRESENT_STATE) {
131 ret = value & 0x000fffff;
132 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
133 ret |= (value << 1) & SDHCI_CMD_LVL;
138 * DTS properties of mmc host are used to enable each speed mode
139 * according to soc and board capability. So clean up
140 * SDR50/SDR104/DDR50 support bits here.
142 if (spec_reg == SDHCI_CAPABILITIES_1) {
143 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
144 SDHCI_SUPPORT_DDR50);
149 * Some controllers have unreliable Data Line Active
150 * bit for commands with busy signal. This affects
151 * Command Inhibit (data) bit. Just ignore it since
152 * MMC core driver has already polled card status
153 * with CMD13 after any command with busy siganl.
155 if ((spec_reg == SDHCI_PRESENT_STATE) &&
156 (esdhc->quirk_ignore_data_inhibit == true)) {
157 ret = value & ~SDHCI_DATA_INHIBIT;
165 static u16 esdhc_readw_fixup(struct sdhci_host *host,
166 int spec_reg, u32 value)
168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
169 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
171 int shift = (spec_reg & 0x2) * 8;
173 if (spec_reg == SDHCI_HOST_VERSION)
174 ret = value & 0xffff;
176 ret = (value >> shift) & 0xffff;
177 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
178 * vendor version and spec version information.
180 if ((spec_reg == SDHCI_HOST_VERSION) &&
181 (esdhc->quirk_incorrect_hostver))
182 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
186 static u8 esdhc_readb_fixup(struct sdhci_host *host,
187 int spec_reg, u32 value)
191 int shift = (spec_reg & 0x3) * 8;
193 ret = (value >> shift) & 0xff;
196 * "DMA select" locates at offset 0x28 in SD specification, but on
197 * P5020 or P3041, it locates at 0x29.
199 if (spec_reg == SDHCI_HOST_CONTROL) {
200 /* DMA select is 22,23 bits in Protocol Control Register */
201 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
202 /* fixup the result */
203 ret &= ~SDHCI_CTRL_DMA_MASK;
210 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
211 * written into eSDHC register.
213 * @host: pointer to sdhci_host
214 * @spec_reg: SD spec register address
215 * @value: 8/16/32bit SD spec register value that would be written
216 * @old_value: 32bit eSDHC register value on spec_reg address
218 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
219 * registers are 32 bits. There are differences in register size, register
220 * address, register function, bit position and function between eSDHC spec
223 * Return a fixed up register value
225 static u32 esdhc_writel_fixup(struct sdhci_host *host,
226 int spec_reg, u32 value, u32 old_value)
231 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
232 * when SYSCTL[RSTD] is set for some special operations.
233 * No any impact on other operation.
235 if (spec_reg == SDHCI_INT_ENABLE)
236 ret = value | SDHCI_INT_BLK_GAP;
243 static u32 esdhc_writew_fixup(struct sdhci_host *host,
244 int spec_reg, u16 value, u32 old_value)
246 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
247 int shift = (spec_reg & 0x2) * 8;
251 case SDHCI_TRANSFER_MODE:
253 * Postpone this write, we must do it together with a
254 * command write that is down below. Return old value.
256 pltfm_host->xfer_mode_shadow = value;
259 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
263 ret = old_value & (~(0xffff << shift));
264 ret |= (value << shift);
266 if (spec_reg == SDHCI_BLOCK_SIZE) {
268 * Two last DMA bits are reserved, and first one is used for
269 * non-standard blksz of 4096 bytes that we don't support
270 * yet. So clear the DMA boundary bits.
272 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
277 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
278 int spec_reg, u8 value, u32 old_value)
283 int shift = (spec_reg & 0x3) * 8;
286 * eSDHC doesn't have a standard power control register, so we do
287 * nothing here to avoid incorrect operation.
289 if (spec_reg == SDHCI_POWER_CONTROL)
292 * "DMA select" location is offset 0x28 in SD specification, but on
293 * P5020 or P3041, it's located at 0x29.
295 if (spec_reg == SDHCI_HOST_CONTROL) {
297 * If host control register is not standard, exit
300 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
303 /* DMA select is 22,23 bits in Protocol Control Register */
304 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
305 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
306 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
307 (old_value & SDHCI_CTRL_DMA_MASK);
308 ret = (ret & (~0xff)) | tmp;
310 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
311 ret &= ~ESDHC_HOST_CONTROL_RES;
315 ret = (old_value & (~(0xff << shift))) | (value << shift);
319 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
324 if (reg == SDHCI_CAPABILITIES_1)
325 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
327 value = ioread32be(host->ioaddr + reg);
329 ret = esdhc_readl_fixup(host, reg, value);
334 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
339 if (reg == SDHCI_CAPABILITIES_1)
340 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
342 value = ioread32(host->ioaddr + reg);
344 ret = esdhc_readl_fixup(host, reg, value);
349 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
353 int base = reg & ~0x3;
355 value = ioread32be(host->ioaddr + base);
356 ret = esdhc_readw_fixup(host, reg, value);
360 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
364 int base = reg & ~0x3;
366 value = ioread32(host->ioaddr + base);
367 ret = esdhc_readw_fixup(host, reg, value);
371 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
375 int base = reg & ~0x3;
377 value = ioread32be(host->ioaddr + base);
378 ret = esdhc_readb_fixup(host, reg, value);
382 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
386 int base = reg & ~0x3;
388 value = ioread32(host->ioaddr + base);
389 ret = esdhc_readb_fixup(host, reg, value);
393 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
397 value = esdhc_writel_fixup(host, reg, val, 0);
398 iowrite32be(value, host->ioaddr + reg);
401 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
405 value = esdhc_writel_fixup(host, reg, val, 0);
406 iowrite32(value, host->ioaddr + reg);
409 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
411 int base = reg & ~0x3;
415 value = ioread32be(host->ioaddr + base);
416 ret = esdhc_writew_fixup(host, reg, val, value);
417 if (reg != SDHCI_TRANSFER_MODE)
418 iowrite32be(ret, host->ioaddr + base);
421 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
423 int base = reg & ~0x3;
427 value = ioread32(host->ioaddr + base);
428 ret = esdhc_writew_fixup(host, reg, val, value);
429 if (reg != SDHCI_TRANSFER_MODE)
430 iowrite32(ret, host->ioaddr + base);
433 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
435 int base = reg & ~0x3;
439 value = ioread32be(host->ioaddr + base);
440 ret = esdhc_writeb_fixup(host, reg, val, value);
441 iowrite32be(ret, host->ioaddr + base);
444 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
446 int base = reg & ~0x3;
450 value = ioread32(host->ioaddr + base);
451 ret = esdhc_writeb_fixup(host, reg, val, value);
452 iowrite32(ret, host->ioaddr + base);
456 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
457 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
458 * and Block Gap Event(IRQSTAT[BGE]) are also set.
459 * For Continue, apply soft reset for data(SYSCTL[RSTD]);
460 * and re-issue the entire read transaction from beginning.
462 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
464 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
465 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
470 applicable = (intmask & SDHCI_INT_DATA_END) &&
471 (intmask & SDHCI_INT_BLK_GAP) &&
472 (esdhc->vendor_ver == VENDOR_V_23);
476 host->data->error = 0;
477 dmastart = sg_dma_address(host->data->sg);
478 dmanow = dmastart + host->data->bytes_xfered;
480 * Force update to the next DMA block boundary.
482 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
483 SDHCI_DEFAULT_BOUNDARY_SIZE;
484 host->data->bytes_xfered = dmanow - dmastart;
485 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
488 static int esdhc_of_enable_dma(struct sdhci_host *host)
491 struct device *dev = mmc_dev(host->mmc);
493 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||
494 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc"))
495 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
497 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
498 value |= ESDHC_DMA_SNOOP;
499 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
503 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
505 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
506 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
508 if (esdhc->peripheral_clock)
509 return esdhc->peripheral_clock;
511 return pltfm_host->clock;
514 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
516 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
517 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
520 if (esdhc->peripheral_clock)
521 clock = esdhc->peripheral_clock;
523 clock = pltfm_host->clock;
524 return clock / 256 / 16;
527 static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
532 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
535 val |= ESDHC_CLOCK_SDCLKEN;
537 val &= ~ESDHC_CLOCK_SDCLKEN;
539 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
542 timeout = ktime_add_ms(ktime_get(), 20);
543 val = ESDHC_CLOCK_STABLE;
545 bool timedout = ktime_after(ktime_get(), timeout);
547 if (sdhci_readl(host, ESDHC_PRSSTAT) & val)
550 pr_err("%s: Internal clock never stabilised.\n",
551 mmc_hostname(host->mmc));
558 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
560 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
561 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
569 host->mmc->actual_clock = 0;
572 esdhc_clock_enable(host, false);
576 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
577 if (esdhc->vendor_ver < VENDOR_V_23)
580 if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
581 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
582 fixup = esdhc->clk_fixup->sd_dflt_max_clk;
583 else if (esdhc->clk_fixup)
584 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
586 if (fixup && clock > fixup)
589 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
590 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
591 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
592 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
594 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
597 while (host->max_clk / pre_div / div > clock && div < 16)
600 if (esdhc->quirk_limited_clk_division &&
601 clock == MMC_HS200_MAX_DTR &&
602 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
603 host->flags & SDHCI_HS400_TUNING)) {
604 division = pre_div * div;
608 } else if (division <= 8) {
611 } else if (division <= 12) {
615 pr_warn("%s: using unsupported clock division.\n",
616 mmc_hostname(host->mmc));
620 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
621 clock, host->max_clk / pre_div / div);
622 host->mmc->actual_clock = host->max_clk / pre_div / div;
623 esdhc->div_ratio = pre_div * div;
627 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
628 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
629 | (div << ESDHC_DIVIDER_SHIFT)
630 | (pre_div << ESDHC_PREDIV_SHIFT));
631 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
633 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
634 clock == MMC_HS200_MAX_DTR) {
635 temp = sdhci_readl(host, ESDHC_TBCTL);
636 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
637 temp = sdhci_readl(host, ESDHC_SDCLKCTL);
638 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
639 esdhc_clock_enable(host, true);
641 temp = sdhci_readl(host, ESDHC_DLLCFG0);
642 temp |= ESDHC_DLL_ENABLE;
643 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
644 temp |= ESDHC_DLL_FREQ_SEL;
645 sdhci_writel(host, temp, ESDHC_DLLCFG0);
646 temp = sdhci_readl(host, ESDHC_TBCTL);
647 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
649 esdhc_clock_enable(host, false);
650 temp = sdhci_readl(host, ESDHC_DMA_SYSCTL);
651 temp |= ESDHC_FLUSH_ASYNC_FIFO;
652 sdhci_writel(host, temp, ESDHC_DMA_SYSCTL);
656 timeout = ktime_add_ms(ktime_get(), 20);
658 bool timedout = ktime_after(ktime_get(), timeout);
660 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
663 pr_err("%s: Internal clock never stabilised.\n",
664 mmc_hostname(host->mmc));
670 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
671 temp |= ESDHC_CLOCK_SDCLKEN;
672 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
675 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
679 ctrl = sdhci_readl(host, ESDHC_PROCTL);
680 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
682 case MMC_BUS_WIDTH_8:
683 ctrl |= ESDHC_CTRL_8BITBUS;
686 case MMC_BUS_WIDTH_4:
687 ctrl |= ESDHC_CTRL_4BITBUS;
694 sdhci_writel(host, ctrl, ESDHC_PROCTL);
697 static void esdhc_reset(struct sdhci_host *host, u8 mask)
699 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
700 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
703 sdhci_reset(host, mask);
705 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
706 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
708 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc"))
711 if (mask & SDHCI_RESET_ALL) {
712 val = sdhci_readl(host, ESDHC_TBCTL);
714 sdhci_writel(host, val, ESDHC_TBCTL);
716 if (esdhc->quirk_unreliable_pulse_detection) {
717 val = sdhci_readl(host, ESDHC_DLLCFG1);
718 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
719 sdhci_writel(host, val, ESDHC_DLLCFG1);
724 /* The SCFG, Supplemental Configuration Unit, provides SoC specific
725 * configuration and status registers for the device. There is a
726 * SDHC IO VSEL control register on SCFG for some platforms. It's
727 * used to support SDHC IO voltage switching.
729 static const struct of_device_id scfg_device_ids[] = {
730 { .compatible = "fsl,t1040-scfg", },
731 { .compatible = "fsl,ls1012a-scfg", },
732 { .compatible = "fsl,ls1046a-scfg", },
736 /* SDHC IO VSEL control register definition */
737 #define SCFG_SDHCIOVSELCR 0x408
738 #define SDHCIOVSELCR_TGLEN 0x80000000
739 #define SDHCIOVSELCR_VSELVAL 0x60000000
740 #define SDHCIOVSELCR_SDHC_VS 0x00000001
742 static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
745 struct sdhci_host *host = mmc_priv(mmc);
746 struct device_node *scfg_node;
747 void __iomem *scfg_base = NULL;
752 * Signal Voltage Switching is only applicable for Host Controllers
755 if (host->version < SDHCI_SPEC_300)
758 val = sdhci_readl(host, ESDHC_PROCTL);
760 switch (ios->signal_voltage) {
761 case MMC_SIGNAL_VOLTAGE_330:
762 val &= ~ESDHC_VOLT_SEL;
763 sdhci_writel(host, val, ESDHC_PROCTL);
765 case MMC_SIGNAL_VOLTAGE_180:
766 scfg_node = of_find_matching_node(NULL, scfg_device_ids);
768 scfg_base = of_iomap(scfg_node, 0);
770 sdhciovselcr = SDHCIOVSELCR_TGLEN |
771 SDHCIOVSELCR_VSELVAL;
772 iowrite32be(sdhciovselcr,
773 scfg_base + SCFG_SDHCIOVSELCR);
775 val |= ESDHC_VOLT_SEL;
776 sdhci_writel(host, val, ESDHC_PROCTL);
779 sdhciovselcr = SDHCIOVSELCR_TGLEN |
780 SDHCIOVSELCR_SDHC_VS;
781 iowrite32be(sdhciovselcr,
782 scfg_base + SCFG_SDHCIOVSELCR);
785 val |= ESDHC_VOLT_SEL;
786 sdhci_writel(host, val, ESDHC_PROCTL);
794 static struct soc_device_attribute soc_fixup_tuning[] = {
795 { .family = "QorIQ T1040", .revision = "1.0", },
796 { .family = "QorIQ T2080", .revision = "1.0", },
797 { .family = "QorIQ T1023", .revision = "1.0", },
798 { .family = "QorIQ LS1021A", .revision = "1.0", },
799 { .family = "QorIQ LS1080A", .revision = "1.0", },
800 { .family = "QorIQ LS2080A", .revision = "1.0", },
801 { .family = "QorIQ LS1012A", .revision = "1.0", },
802 { .family = "QorIQ LS1043A", .revision = "1.*", },
803 { .family = "QorIQ LS1046A", .revision = "1.0", },
807 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
811 esdhc_clock_enable(host, false);
813 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
814 val |= ESDHC_FLUSH_ASYNC_FIFO;
815 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
817 val = sdhci_readl(host, ESDHC_TBCTL);
822 sdhci_writel(host, val, ESDHC_TBCTL);
824 esdhc_clock_enable(host, true);
827 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
829 struct sdhci_host *host = mmc_priv(mmc);
830 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
831 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
837 /* For tuning mode, the sd clock divisor value
838 * must be larger than 3 according to reference manual.
840 clk = esdhc->peripheral_clock / 3;
841 if (host->clock > clk)
842 esdhc_of_set_clock(host, clk);
844 if (esdhc->quirk_limited_clk_division &&
845 host->flags & SDHCI_HS400_TUNING)
846 esdhc_of_set_clock(host, host->clock);
848 esdhc_tuning_block_enable(host, true);
850 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
851 ret = sdhci_execute_tuning(mmc, opcode);
854 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
855 val |= ESDHC_FLW_CTL_BG;
856 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
859 if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) {
861 /* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and
862 * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO
864 val = sdhci_readl(host, ESDHC_TBPTR);
865 val = (val & ~((0x7f << 8) | 0x7f)) |
866 (3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8);
867 sdhci_writel(host, val, ESDHC_TBPTR);
869 /* program the software tuning mode by setting
870 * TBCTL[TB_MODE]=2'h3
872 val = sdhci_readl(host, ESDHC_TBCTL);
874 sdhci_writel(host, val, ESDHC_TBCTL);
875 sdhci_execute_tuning(mmc, opcode);
880 static void esdhc_set_uhs_signaling(struct sdhci_host *host,
883 if (timing == MMC_TIMING_MMC_HS400)
884 esdhc_tuning_block_enable(host, true);
886 sdhci_set_uhs_signaling(host, timing);
889 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask)
893 if (of_find_compatible_node(NULL, NULL,
894 "fsl,p2020-esdhc")) {
895 command = SDHCI_GET_CMD(sdhci_readw(host,
897 if (command == MMC_WRITE_MULTIPLE_BLOCK &&
898 sdhci_readw(host, SDHCI_BLOCK_COUNT) &&
899 intmask & SDHCI_INT_DATA_END) {
900 intmask &= ~SDHCI_INT_DATA_END;
901 sdhci_writel(host, SDHCI_INT_DATA_END,
908 #ifdef CONFIG_PM_SLEEP
909 static u32 esdhc_proctl;
910 static int esdhc_of_suspend(struct device *dev)
912 struct sdhci_host *host = dev_get_drvdata(dev);
914 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
916 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
917 mmc_retune_needed(host->mmc);
919 return sdhci_suspend_host(host);
922 static int esdhc_of_resume(struct device *dev)
924 struct sdhci_host *host = dev_get_drvdata(dev);
925 int ret = sdhci_resume_host(host);
928 /* Isn't this already done by sdhci_resume_host() ? --rmk */
929 esdhc_of_enable_dma(host);
930 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
936 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
940 static const struct sdhci_ops sdhci_esdhc_be_ops = {
941 .read_l = esdhc_be_readl,
942 .read_w = esdhc_be_readw,
943 .read_b = esdhc_be_readb,
944 .write_l = esdhc_be_writel,
945 .write_w = esdhc_be_writew,
946 .write_b = esdhc_be_writeb,
947 .set_clock = esdhc_of_set_clock,
948 .enable_dma = esdhc_of_enable_dma,
949 .get_max_clock = esdhc_of_get_max_clock,
950 .get_min_clock = esdhc_of_get_min_clock,
951 .adma_workaround = esdhc_of_adma_workaround,
952 .set_bus_width = esdhc_pltfm_set_bus_width,
953 .reset = esdhc_reset,
954 .set_uhs_signaling = esdhc_set_uhs_signaling,
958 static const struct sdhci_ops sdhci_esdhc_le_ops = {
959 .read_l = esdhc_le_readl,
960 .read_w = esdhc_le_readw,
961 .read_b = esdhc_le_readb,
962 .write_l = esdhc_le_writel,
963 .write_w = esdhc_le_writew,
964 .write_b = esdhc_le_writeb,
965 .set_clock = esdhc_of_set_clock,
966 .enable_dma = esdhc_of_enable_dma,
967 .get_max_clock = esdhc_of_get_max_clock,
968 .get_min_clock = esdhc_of_get_min_clock,
969 .adma_workaround = esdhc_of_adma_workaround,
970 .set_bus_width = esdhc_pltfm_set_bus_width,
971 .reset = esdhc_reset,
972 .set_uhs_signaling = esdhc_set_uhs_signaling,
976 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
977 .quirks = ESDHC_DEFAULT_QUIRKS |
979 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
981 SDHCI_QUIRK_NO_CARD_NO_RESET |
982 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
983 .ops = &sdhci_esdhc_be_ops,
986 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
987 .quirks = ESDHC_DEFAULT_QUIRKS |
988 SDHCI_QUIRK_NO_CARD_NO_RESET |
989 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
990 .ops = &sdhci_esdhc_le_ops,
993 static struct soc_device_attribute soc_incorrect_hostver[] = {
994 { .family = "QorIQ T4240", .revision = "1.0", },
995 { .family = "QorIQ T4240", .revision = "2.0", },
999 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
1000 { .family = "QorIQ LX2160A", .revision = "1.0", },
1001 { .family = "QorIQ LX2160A", .revision = "2.0", },
1002 { .family = "QorIQ LS1028A", .revision = "1.0", },
1006 static struct soc_device_attribute soc_unreliable_pulse_detection[] = {
1007 { .family = "QorIQ LX2160A", .revision = "1.0", },
1011 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
1013 const struct of_device_id *match;
1014 struct sdhci_pltfm_host *pltfm_host;
1015 struct sdhci_esdhc *esdhc;
1016 struct device_node *np;
1021 pltfm_host = sdhci_priv(host);
1022 esdhc = sdhci_pltfm_priv(pltfm_host);
1024 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
1025 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
1026 SDHCI_VENDOR_VER_SHIFT;
1027 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
1028 if (soc_device_match(soc_incorrect_hostver))
1029 esdhc->quirk_incorrect_hostver = true;
1031 esdhc->quirk_incorrect_hostver = false;
1033 if (soc_device_match(soc_fixup_sdhc_clkdivs))
1034 esdhc->quirk_limited_clk_division = true;
1036 esdhc->quirk_limited_clk_division = false;
1038 if (soc_device_match(soc_unreliable_pulse_detection))
1039 esdhc->quirk_unreliable_pulse_detection = true;
1041 esdhc->quirk_unreliable_pulse_detection = false;
1043 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
1045 esdhc->clk_fixup = match->data;
1046 np = pdev->dev.of_node;
1047 clk = of_clk_get(np, 0);
1050 * esdhc->peripheral_clock would be assigned with a value
1051 * which is eSDHC base clock when use periperal clock.
1052 * For some platforms, the clock value got by common clk
1053 * API is peripheral clock while the eSDHC base clock is
1054 * 1/2 peripheral clock.
1056 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||
1057 of_device_is_compatible(np, "fsl,ls1028a-esdhc"))
1058 esdhc->peripheral_clock = clk_get_rate(clk) / 2;
1060 esdhc->peripheral_clock = clk_get_rate(clk);
1065 if (esdhc->peripheral_clock) {
1066 esdhc_clock_enable(host, false);
1067 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
1068 val |= ESDHC_PERIPHERAL_CLK_SEL;
1069 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
1070 esdhc_clock_enable(host, true);
1074 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc)
1076 esdhc_tuning_block_enable(mmc_priv(mmc), false);
1080 static int sdhci_esdhc_probe(struct platform_device *pdev)
1082 struct sdhci_host *host;
1083 struct device_node *np;
1084 struct sdhci_pltfm_host *pltfm_host;
1085 struct sdhci_esdhc *esdhc;
1088 np = pdev->dev.of_node;
1090 if (of_property_read_bool(np, "little-endian"))
1091 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
1092 sizeof(struct sdhci_esdhc));
1094 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
1095 sizeof(struct sdhci_esdhc));
1098 return PTR_ERR(host);
1100 host->mmc_host_ops.start_signal_voltage_switch =
1101 esdhc_signal_voltage_switch;
1102 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
1103 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr;
1104 host->tuning_delay = 1;
1106 esdhc_init(pdev, host);
1108 sdhci_get_of_property(pdev);
1110 pltfm_host = sdhci_priv(host);
1111 esdhc = sdhci_pltfm_priv(pltfm_host);
1112 if (soc_device_match(soc_fixup_tuning))
1113 esdhc->quirk_fixup_tuning = true;
1115 esdhc->quirk_fixup_tuning = false;
1117 if (esdhc->vendor_ver == VENDOR_V_22)
1118 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
1120 if (esdhc->vendor_ver > VENDOR_V_22)
1121 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1123 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
1124 host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
1125 host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1128 if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
1129 of_device_is_compatible(np, "fsl,p5020-esdhc") ||
1130 of_device_is_compatible(np, "fsl,p4080-esdhc") ||
1131 of_device_is_compatible(np, "fsl,p1020-esdhc") ||
1132 of_device_is_compatible(np, "fsl,t1040-esdhc"))
1133 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1135 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
1136 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1138 esdhc->quirk_ignore_data_inhibit = false;
1139 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
1141 * Freescale messed up with P2020 as it has a non-standard
1142 * host control register
1144 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
1145 esdhc->quirk_ignore_data_inhibit = true;
1148 /* call to generic mmc_of_parse to support additional capabilities */
1149 ret = mmc_of_parse(host->mmc);
1153 mmc_of_parse_voltage(np, &host->ocr_mask);
1155 ret = sdhci_add_host(host);
1161 sdhci_pltfm_free(pdev);
1165 static struct platform_driver sdhci_esdhc_driver = {
1167 .name = "sdhci-esdhc",
1168 .of_match_table = sdhci_esdhc_of_match,
1169 .pm = &esdhc_of_dev_pm_ops,
1171 .probe = sdhci_esdhc_probe,
1172 .remove = sdhci_pltfm_unregister,
1175 module_platform_driver(sdhci_esdhc_driver);
1177 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
1178 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
1179 "Anton Vorontsov <avorontsov@ru.mvista.com>");
1180 MODULE_LICENSE("GPL v2");