drivers/mmc/host/sdhci-omap.c

   1 /**
   2  * SDHCI Controller driver for TI's OMAP SoCs
   3  *
   4  * Copyright (C) 2017 Texas Instruments
   5  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 of
   9  * the License as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/mmc/slot-gpio.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/regulator/consumer.h>
  28
  29 #include "sdhci-pltfm.h"
  30
  31 #define SDHCI_OMAP_CON          0x12c
  32 #define CON_DW8                 BIT(5)
  33 #define CON_DMA_MASTER          BIT(20)
  34 #define CON_DDR                 BIT(19)
  35 #define CON_CLKEXTFREE          BIT(16)
  36 #define CON_PADEN               BIT(15)
  37 #define CON_INIT                BIT(1)
  38 #define CON_OD                  BIT(0)
  39
  40 #define SDHCI_OMAP_DLL          0x0134
  41 #define DLL_SWT                 BIT(20)
  42 #define DLL_FORCE_SR_C_SHIFT    13
  43 #define DLL_FORCE_SR_C_MASK     (0x7f << DLL_FORCE_SR_C_SHIFT)
  44 #define DLL_FORCE_VALUE         BIT(12)
  45 #define DLL_CALIB               BIT(1)
  46
  47 #define SDHCI_OMAP_CMD          0x20c
  48
  49 #define SDHCI_OMAP_PSTATE       0x0224
  50 #define PSTATE_DLEV_DAT0        BIT(20)
  51 #define PSTATE_DATI             BIT(1)
  52
  53 #define SDHCI_OMAP_HCTL         0x228
  54 #define HCTL_SDBP               BIT(8)
  55 #define HCTL_SDVS_SHIFT         9
  56 #define HCTL_SDVS_MASK          (0x7 << HCTL_SDVS_SHIFT)
  57 #define HCTL_SDVS_33            (0x7 << HCTL_SDVS_SHIFT)
  58 #define HCTL_SDVS_30            (0x6 << HCTL_SDVS_SHIFT)
  59 #define HCTL_SDVS_18            (0x5 << HCTL_SDVS_SHIFT)
  60
  61 #define SDHCI_OMAP_SYSCTL       0x22c
  62 #define SYSCTL_CEN              BIT(2)
  63 #define SYSCTL_CLKD_SHIFT       6
  64 #define SYSCTL_CLKD_MASK        0x3ff
  65
  66 #define SDHCI_OMAP_STAT         0x230
  67
  68 #define SDHCI_OMAP_IE           0x234
  69 #define INT_CC_EN               BIT(0)
  70
  71 #define SDHCI_OMAP_AC12         0x23c
  72 #define AC12_V1V8_SIGEN         BIT(19)
  73 #define AC12_SCLK_SEL           BIT(23)
  74
  75 #define SDHCI_OMAP_CAPA         0x240
  76 #define CAPA_VS33               BIT(24)
  77 #define CAPA_VS30               BIT(25)
  78 #define CAPA_VS18               BIT(26)
  79
  80 #define SDHCI_OMAP_CAPA2        0x0244
  81 #define CAPA2_TSDR50            BIT(13)
  82
  83 #define SDHCI_OMAP_TIMEOUT      1               /* 1 msec */
  84
  85 #define SYSCTL_CLKD_MAX         0x3FF
  86
  87 #define IOV_1V8                 1800000         /* 180000 uV */
  88 #define IOV_3V0                 3000000         /* 300000 uV */
  89 #define IOV_3V3                 3300000         /* 330000 uV */
  90
  91 #define MAX_PHASE_DELAY         0x7C
  92
  93 struct sdhci_omap_data {
  94         u32 offset;
  95 };
  96
  97 struct sdhci_omap_host {
  98         void __iomem            *base;
  99         struct device           *dev;
 100         struct  regulator       *pbias;
 101         bool                    pbias_enabled;
 102         struct sdhci_host       *host;
 103         u8                      bus_mode;
 104         u8                      power_mode;
 105 };
 106
 107 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
 108                                    unsigned int offset)
 109 {
 110         return readl(host->base + offset);
 111 }
 112
 113 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
 114                                      unsigned int offset, u32 data)
 115 {
 116         writel(data, host->base + offset);
 117 }
 118
 119 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
 120                                 bool power_on, unsigned int iov)
 121 {
 122         int ret;
 123         struct device *dev = omap_host->dev;
 124
 125         if (IS_ERR(omap_host->pbias))
 126                 return 0;
 127
 128         if (power_on) {
 129                 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
 130                 if (ret) {
 131                         dev_err(dev, "pbias set voltage failed\n");
 132                         return ret;
 133                 }
 134
 135                 if (omap_host->pbias_enabled)
 136                         return 0;
 137
 138                 ret = regulator_enable(omap_host->pbias);
 139                 if (ret) {
 140                         dev_err(dev, "pbias reg enable fail\n");
 141                         return ret;
 142                 }
 143
 144                 omap_host->pbias_enabled = true;
 145         } else {
 146                 if (!omap_host->pbias_enabled)
 147                         return 0;
 148
 149                 ret = regulator_disable(omap_host->pbias);
 150                 if (ret) {
 151                         dev_err(dev, "pbias reg disable fail\n");
 152                         return ret;
 153                 }
 154                 omap_host->pbias_enabled = false;
 155         }
 156
 157         return 0;
 158 }
 159
 160 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
 161                                  unsigned int iov)
 162 {
 163         int ret;
 164         struct sdhci_host *host = omap_host->host;
 165         struct mmc_host *mmc = host->mmc;
 166
 167         ret = sdhci_omap_set_pbias(omap_host, false, 0);
 168         if (ret)
 169                 return ret;
 170
 171         if (!IS_ERR(mmc->supply.vqmmc)) {
 172                 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
 173                 if (ret) {
 174                         dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
 175                         return ret;
 176                 }
 177         }
 178
 179         ret = sdhci_omap_set_pbias(omap_host, true, iov);
 180         if (ret)
 181                 return ret;
 182
 183         return 0;
 184 }
 185
 186 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
 187                                       unsigned char signal_voltage)
 188 {
 189         u32 reg;
 190         ktime_t timeout;
 191
 192         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
 193         reg &= ~HCTL_SDVS_MASK;
 194
 195         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 196                 reg |= HCTL_SDVS_33;
 197         else
 198                 reg |= HCTL_SDVS_18;
 199
 200         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 201
 202         reg |= HCTL_SDBP;
 203         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 204
 205         /* wait 1ms */
 206         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 207         while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)) {
 208                 if (WARN_ON(ktime_after(ktime_get(), timeout)))
 209                         return;
 210                 usleep_range(5, 10);
 211         }
 212 }
 213
 214 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
 215                                       int count)
 216 {
 217         int i;
 218         u32 reg;
 219
 220         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 221         reg |= DLL_FORCE_VALUE;
 222         reg &= ~DLL_FORCE_SR_C_MASK;
 223         reg |= (count << DLL_FORCE_SR_C_SHIFT);
 224         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 225
 226         reg |= DLL_CALIB;
 227         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 228         for (i = 0; i < 1000; i++) {
 229                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 230                 if (reg & DLL_CALIB)
 231                         break;
 232         }
 233         reg &= ~DLL_CALIB;
 234         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 235 }
 236
 237 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
 238 {
 239         u32 reg;
 240
 241         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 242         reg &= ~AC12_SCLK_SEL;
 243         sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 244
 245         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 246         reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
 247         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 248 }
 249
 250 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
 251 {
 252         struct sdhci_host *host = mmc_priv(mmc);
 253         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 254         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 255         struct device *dev = omap_host->dev;
 256         struct mmc_ios *ios = &mmc->ios;
 257         u32 start_window = 0, max_window = 0;
 258         u8 cur_match, prev_match = 0;
 259         u32 length = 0, max_len = 0;
 260         u32 phase_delay = 0;
 261         int ret = 0;
 262         u32 reg;
 263
 264         pltfm_host = sdhci_priv(host);
 265         omap_host = sdhci_pltfm_priv(pltfm_host);
 266         dev = omap_host->dev;
 267
 268         /* clock tuning is not needed for upto 52MHz */
 269         if (ios->clock <= 52000000)
 270                 return 0;
 271
 272         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
 273         if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
 274                 return 0;
 275
 276         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 277         reg |= DLL_SWT;
 278         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 279
 280         while (phase_delay <= MAX_PHASE_DELAY) {
 281                 sdhci_omap_set_dll(omap_host, phase_delay);
 282
 283                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 284                 if (cur_match) {
 285                         if (prev_match) {
 286                                 length++;
 287                         } else {
 288                                 start_window = phase_delay;
 289                                 length = 1;
 290                         }
 291                 }
 292
 293                 if (length > max_len) {
 294                         max_window = start_window;
 295                         max_len = length;
 296                 }
 297
 298                 prev_match = cur_match;
 299                 phase_delay += 4;
 300         }
 301
 302         if (!max_len) {
 303                 dev_err(dev, "Unable to find match\n");
 304                 ret = -EIO;
 305                 goto tuning_error;
 306         }
 307
 308         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 309         if (!(reg & AC12_SCLK_SEL)) {
 310                 ret = -EIO;
 311                 goto tuning_error;
 312         }
 313
 314         phase_delay = max_window + 4 * (max_len >> 1);
 315         sdhci_omap_set_dll(omap_host, phase_delay);
 316
 317         goto ret;
 318
 319 tuning_error:
 320         dev_err(dev, "Tuning failed\n");
 321         sdhci_omap_disable_tuning(omap_host);
 322
 323 ret:
 324         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 325         return ret;
 326 }
 327
 328 static int sdhci_omap_card_busy(struct mmc_host *mmc)
 329 {
 330         u32 reg, ac12;
 331         int ret = false;
 332         struct sdhci_host *host = mmc_priv(mmc);
 333         struct sdhci_pltfm_host *pltfm_host;
 334         struct sdhci_omap_host *omap_host;
 335         u32 ier = host->ier;
 336
 337         pltfm_host = sdhci_priv(host);
 338         omap_host = sdhci_pltfm_priv(pltfm_host);
 339
 340         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 341         ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 342         reg &= ~CON_CLKEXTFREE;
 343         if (ac12 & AC12_V1V8_SIGEN)
 344                 reg |= CON_CLKEXTFREE;
 345         reg |= CON_PADEN;
 346         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 347
 348         disable_irq(host->irq);
 349         ier |= SDHCI_INT_CARD_INT;
 350         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 351         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 352
 353         /*
 354          * Delay is required for PSTATE to correctly reflect
 355          * DLEV/CLEV values after PADEN is set.
 356          */
 357         usleep_range(50, 100);
 358         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
 359         if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
 360                 ret = true;
 361
 362         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 363         reg &= ~(CON_CLKEXTFREE | CON_PADEN);
 364         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 365
 366         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 367         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 368         enable_irq(host->irq);
 369
 370         return ret;
 371 }
 372
 373 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
 374                                                   struct mmc_ios *ios)
 375 {
 376         u32 reg;
 377         int ret;
 378         unsigned int iov;
 379         struct sdhci_host *host = mmc_priv(mmc);
 380         struct sdhci_pltfm_host *pltfm_host;
 381         struct sdhci_omap_host *omap_host;
 382         struct device *dev;
 383
 384         pltfm_host = sdhci_priv(host);
 385         omap_host = sdhci_pltfm_priv(pltfm_host);
 386         dev = omap_host->dev;
 387
 388         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 389                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 390                 if (!(reg & CAPA_VS33))
 391                         return -EOPNOTSUPP;
 392
 393                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 394
 395                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 396                 reg &= ~AC12_V1V8_SIGEN;
 397                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 398
 399                 iov = IOV_3V3;
 400         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 401                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 402                 if (!(reg & CAPA_VS18))
 403                         return -EOPNOTSUPP;
 404
 405                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 406
 407                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 408                 reg |= AC12_V1V8_SIGEN;
 409                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 410
 411                 iov = IOV_1V8;
 412         } else {
 413                 return -EOPNOTSUPP;
 414         }
 415
 416         ret = sdhci_omap_enable_iov(omap_host, iov);
 417         if (ret) {
 418                 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
 419                 return ret;
 420         }
 421
 422         dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
 423         return 0;
 424 }
 425
 426 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
 427                                       u8 power_mode)
 428 {
 429         if (omap_host->bus_mode == MMC_POWER_OFF)
 430                 sdhci_omap_disable_tuning(omap_host);
 431         omap_host->power_mode = power_mode;
 432 }
 433
 434 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
 435                                     unsigned int mode)
 436 {
 437         u32 reg;
 438
 439         if (omap_host->bus_mode == mode)
 440                 return;
 441
 442         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 443         if (mode == MMC_BUSMODE_OPENDRAIN)
 444                 reg |= CON_OD;
 445         else
 446                 reg &= ~CON_OD;
 447         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 448
 449         omap_host->bus_mode = mode;
 450 }
 451
 452 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 453 {
 454         struct sdhci_host *host = mmc_priv(mmc);
 455         struct sdhci_pltfm_host *pltfm_host;
 456         struct sdhci_omap_host *omap_host;
 457
 458         pltfm_host = sdhci_priv(host);
 459         omap_host = sdhci_pltfm_priv(pltfm_host);
 460
 461         sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
 462         sdhci_set_ios(mmc, ios);
 463         sdhci_omap_set_power_mode(omap_host, ios->power_mode);
 464 }
 465
 466 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
 467                                    unsigned int clock)
 468 {
 469         u16 dsor;
 470
 471         dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
 472         if (dsor > SYSCTL_CLKD_MAX)
 473                 dsor = SYSCTL_CLKD_MAX;
 474
 475         return dsor;
 476 }
 477
 478 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
 479 {
 480         u32 reg;
 481
 482         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 483         reg |= SYSCTL_CEN;
 484         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 485 }
 486
 487 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
 488 {
 489         u32 reg;
 490
 491         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 492         reg &= ~SYSCTL_CEN;
 493         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 494 }
 495
 496 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
 497 {
 498         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 499         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 500         unsigned long clkdiv;
 501
 502         sdhci_omap_stop_clock(omap_host);
 503
 504         if (!clock)
 505                 return;
 506
 507         clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
 508         clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
 509         sdhci_enable_clk(host, clkdiv);
 510
 511         sdhci_omap_start_clock(omap_host);
 512 }
 513
 514 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
 515                           unsigned short vdd)
 516 {
 517         struct mmc_host *mmc = host->mmc;
 518
 519         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 520 }
 521
 522 static int sdhci_omap_enable_dma(struct sdhci_host *host)
 523 {
 524         u32 reg;
 525         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 526         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 527
 528         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 529         reg |= CON_DMA_MASTER;
 530         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 531
 532         return 0;
 533 }
 534
 535 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
 536 {
 537         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 538
 539         return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
 540 }
 541
 542 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
 543 {
 544         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 545         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 546         u32 reg;
 547
 548         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 549         if (width == MMC_BUS_WIDTH_8)
 550                 reg |= CON_DW8;
 551         else
 552                 reg &= ~CON_DW8;
 553         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 554
 555         sdhci_set_bus_width(host, width);
 556 }
 557
 558 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 559 {
 560         u32 reg;
 561         ktime_t timeout;
 562         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 563         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 564
 565         if (omap_host->power_mode == power_mode)
 566                 return;
 567
 568         if (power_mode != MMC_POWER_ON)
 569                 return;
 570
 571         disable_irq(host->irq);
 572
 573         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 574         reg |= CON_INIT;
 575         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 576         sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
 577
 578         /* wait 1ms */
 579         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 580         while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)) {
 581                 if (WARN_ON(ktime_after(ktime_get(), timeout)))
 582                         return;
 583                 usleep_range(5, 10);
 584         }
 585
 586         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 587         reg &= ~CON_INIT;
 588         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 589         sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
 590
 591         enable_irq(host->irq);
 592 }
 593
 594 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
 595                                          unsigned int timing)
 596 {
 597         u32 reg;
 598         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 599         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 600
 601         sdhci_omap_stop_clock(omap_host);
 602
 603         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 604         if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
 605                 reg |= CON_DDR;
 606         else
 607                 reg &= ~CON_DDR;
 608         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 609
 610         sdhci_set_uhs_signaling(host, timing);
 611         sdhci_omap_start_clock(omap_host);
 612 }
 613
 614 static struct sdhci_ops sdhci_omap_ops = {
 615         .set_clock = sdhci_omap_set_clock,
 616         .set_power = sdhci_omap_set_power,
 617         .enable_dma = sdhci_omap_enable_dma,
 618         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 619         .get_min_clock = sdhci_omap_get_min_clock,
 620         .set_bus_width = sdhci_omap_set_bus_width,
 621         .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
 622         .reset = sdhci_reset,
 623         .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
 624 };
 625
 626 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
 627 {
 628         u32 reg;
 629         int ret = 0;
 630         struct device *dev = omap_host->dev;
 631         struct regulator *vqmmc;
 632
 633         vqmmc = regulator_get(dev, "vqmmc");
 634         if (IS_ERR(vqmmc)) {
 635                 ret = PTR_ERR(vqmmc);
 636                 goto reg_put;
 637         }
 638
 639         /* voltage capabilities might be set by boot loader, clear it */
 640         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 641         reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
 642
 643         if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
 644                 reg |= CAPA_VS33;
 645         if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
 646                 reg |= CAPA_VS18;
 647
 648         sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
 649
 650 reg_put:
 651         regulator_put(vqmmc);
 652
 653         return ret;
 654 }
 655
 656 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
 657         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 658                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 659                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 660                   SDHCI_QUIRK_NO_HISPD_BIT |
 661                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 662         .quirks2 = SDHCI_QUIRK2_NO_1_8_V |
 663                    SDHCI_QUIRK2_ACMD23_BROKEN |
 664                    SDHCI_QUIRK2_RSP_136_HAS_CRC,
 665         .ops = &sdhci_omap_ops,
 666 };
 667
 668 static const struct sdhci_omap_data dra7_data = {
 669         .offset = 0x200,
 670 };
 671
 672 static const struct of_device_id omap_sdhci_match[] = {
 673         { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
 674         {},
 675 };
 676 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
 677
 678 static int sdhci_omap_probe(struct platform_device *pdev)
 679 {
 680         int ret;
 681         u32 offset;
 682         struct device *dev = &pdev->dev;
 683         struct sdhci_host *host;
 684         struct sdhci_pltfm_host *pltfm_host;
 685         struct sdhci_omap_host *omap_host;
 686         struct mmc_host *mmc;
 687         const struct of_device_id *match;
 688         struct sdhci_omap_data *data;
 689
 690         match = of_match_device(omap_sdhci_match, dev);
 691         if (!match)
 692                 return -EINVAL;
 693
 694         data = (struct sdhci_omap_data *)match->data;
 695         if (!data) {
 696                 dev_err(dev, "no sdhci omap data\n");
 697                 return -EINVAL;
 698         }
 699         offset = data->offset;
 700
 701         host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
 702                                 sizeof(*omap_host));
 703         if (IS_ERR(host)) {
 704                 dev_err(dev, "Failed sdhci_pltfm_init\n");
 705                 return PTR_ERR(host);
 706         }
 707
 708         pltfm_host = sdhci_priv(host);
 709         omap_host = sdhci_pltfm_priv(pltfm_host);
 710         omap_host->host = host;
 711         omap_host->base = host->ioaddr;
 712         omap_host->dev = dev;
 713         omap_host->power_mode = MMC_POWER_UNDEFINED;
 714         host->ioaddr += offset;
 715
 716         mmc = host->mmc;
 717         ret = mmc_of_parse(mmc);
 718         if (ret)
 719                 goto err_pltfm_free;
 720
 721         pltfm_host->clk = devm_clk_get(dev, "fck");
 722         if (IS_ERR(pltfm_host->clk)) {
 723                 ret = PTR_ERR(pltfm_host->clk);
 724                 goto err_pltfm_free;
 725         }
 726
 727         ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
 728         if (ret) {
 729                 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
 730                 goto err_pltfm_free;
 731         }
 732
 733         omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
 734         if (IS_ERR(omap_host->pbias)) {
 735                 ret = PTR_ERR(omap_host->pbias);
 736                 if (ret != -ENODEV)
 737                         goto err_pltfm_free;
 738                 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
 739         }
 740         omap_host->pbias_enabled = false;
 741
 742         /*
 743          * omap_device_pm_domain has callbacks to enable the main
 744          * functional clock, interface clock and also configure the
 745          * SYSCONFIG register of omap devices. The callback will be invoked
 746          * as part of pm_runtime_get_sync.
 747          */
 748         pm_runtime_enable(dev);
 749         ret = pm_runtime_get_sync(dev);
 750         if (ret < 0) {
 751                 dev_err(dev, "pm_runtime_get_sync failed\n");
 752                 pm_runtime_put_noidle(dev);
 753                 goto err_rpm_disable;
 754         }
 755
 756         ret = sdhci_omap_set_capabilities(omap_host);
 757         if (ret) {
 758                 dev_err(dev, "failed to set system capabilities\n");
 759                 goto err_put_sync;
 760         }
 761
 762         host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
 763         host->mmc_host_ops.start_signal_voltage_switch =
 764                                         sdhci_omap_start_signal_voltage_switch;
 765         host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
 766         host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
 767         host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
 768
 769         sdhci_read_caps(host);
 770         host->caps |= SDHCI_CAN_DO_ADMA2;
 771
 772         ret = sdhci_add_host(host);
 773         if (ret)
 774                 goto err_put_sync;
 775
 776         return 0;
 777
 778 err_put_sync:
 779         pm_runtime_put_sync(dev);
 780
 781 err_rpm_disable:
 782         pm_runtime_disable(dev);
 783
 784 err_pltfm_free:
 785         sdhci_pltfm_free(pdev);
 786         return ret;
 787 }
 788
 789 static int sdhci_omap_remove(struct platform_device *pdev)
 790 {
 791         struct device *dev = &pdev->dev;
 792         struct sdhci_host *host = platform_get_drvdata(pdev);
 793
 794         sdhci_remove_host(host, true);
 795         pm_runtime_put_sync(dev);
 796         pm_runtime_disable(dev);
 797         sdhci_pltfm_free(pdev);
 798
 799         return 0;
 800 }
 801
 802 static struct platform_driver sdhci_omap_driver = {
 803         .probe = sdhci_omap_probe,
 804         .remove = sdhci_omap_remove,
 805         .driver = {
 806                    .name = "sdhci-omap",
 807                    .of_match_table = omap_sdhci_match,
 808                   },
 809 };
 810
 811 module_platform_driver(sdhci_omap_driver);
 812
 813 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
 814 MODULE_AUTHOR("Texas Instruments Inc.");
 815 MODULE_LICENSE("GPL v2");
 816 MODULE_ALIAS("platform:sdhci_omap");