1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
10 * Thanks to the following companies for their support:
12 * - JMicron (hardware and technical support)
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/device.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/scatterlist.h>
27 #include <linux/gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
36 #include "sdhci-pci.h"
38 static void sdhci_pci_hw_reset(struct sdhci_host *host);
40 #ifdef CONFIG_PM_SLEEP
41 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
43 mmc_pm_flag_t pm_flags = 0;
44 bool cap_cd_wake = false;
47 for (i = 0; i < chip->num_slots; i++) {
48 struct sdhci_pci_slot *slot = chip->slots[i];
51 pm_flags |= slot->host->mmc->pm_flags;
52 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
57 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
58 return device_wakeup_enable(&chip->pdev->dev);
59 else if (!cap_cd_wake)
60 return device_wakeup_disable(&chip->pdev->dev);
65 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
69 sdhci_pci_init_wakeup(chip);
71 for (i = 0; i < chip->num_slots; i++) {
72 struct sdhci_pci_slot *slot = chip->slots[i];
73 struct sdhci_host *host;
80 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
81 mmc_retune_needed(host->mmc);
83 ret = sdhci_suspend_host(host);
87 if (device_may_wakeup(&chip->pdev->dev))
88 mmc_gpio_set_cd_wake(host->mmc, true);
95 sdhci_resume_host(chip->slots[i]->host);
99 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
101 struct sdhci_pci_slot *slot;
104 for (i = 0; i < chip->num_slots; i++) {
105 slot = chip->slots[i];
109 ret = sdhci_resume_host(slot->host);
113 mmc_gpio_set_cd_wake(slot->host->mmc, false);
119 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
123 ret = cqhci_suspend(chip->slots[0]->host->mmc);
127 return sdhci_pci_suspend_host(chip);
130 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
134 ret = sdhci_pci_resume_host(chip);
138 return cqhci_resume(chip->slots[0]->host->mmc);
143 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
145 struct sdhci_pci_slot *slot;
146 struct sdhci_host *host;
149 for (i = 0; i < chip->num_slots; i++) {
150 slot = chip->slots[i];
156 ret = sdhci_runtime_suspend_host(host);
158 goto err_pci_runtime_suspend;
160 if (chip->rpm_retune &&
161 host->tuning_mode != SDHCI_TUNING_MODE_3)
162 mmc_retune_needed(host->mmc);
167 err_pci_runtime_suspend:
169 sdhci_runtime_resume_host(chip->slots[i]->host);
173 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
175 struct sdhci_pci_slot *slot;
178 for (i = 0; i < chip->num_slots; i++) {
179 slot = chip->slots[i];
183 ret = sdhci_runtime_resume_host(slot->host);
191 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
195 ret = cqhci_suspend(chip->slots[0]->host->mmc);
199 return sdhci_pci_runtime_suspend_host(chip);
202 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
206 ret = sdhci_pci_runtime_resume_host(chip);
210 return cqhci_resume(chip->slots[0]->host->mmc);
214 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
219 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
222 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
227 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
229 sdhci_dumpregs(mmc_priv(mmc));
232 /*****************************************************************************\
234 * Hardware specific quirk handling *
236 \*****************************************************************************/
238 static int ricoh_probe(struct sdhci_pci_chip *chip)
240 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
241 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
242 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
246 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
249 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
250 & SDHCI_TIMEOUT_CLK_MASK) |
252 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
253 & SDHCI_CLOCK_BASE_MASK) |
255 SDHCI_TIMEOUT_CLK_UNIT |
262 #ifdef CONFIG_PM_SLEEP
263 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
265 /* Apply a delay to allow controller to settle */
266 /* Otherwise it becomes confused if card state changed
269 return sdhci_pci_resume_host(chip);
273 static const struct sdhci_pci_fixes sdhci_ricoh = {
274 .probe = ricoh_probe,
275 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
276 SDHCI_QUIRK_FORCE_DMA |
277 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
280 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
281 .probe_slot = ricoh_mmc_probe_slot,
282 #ifdef CONFIG_PM_SLEEP
283 .resume = ricoh_mmc_resume,
285 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
286 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
287 SDHCI_QUIRK_NO_CARD_NO_RESET |
288 SDHCI_QUIRK_MISSING_CAPS
291 static const struct sdhci_pci_fixes sdhci_ene_712 = {
292 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
293 SDHCI_QUIRK_BROKEN_DMA,
296 static const struct sdhci_pci_fixes sdhci_ene_714 = {
297 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
298 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
299 SDHCI_QUIRK_BROKEN_DMA,
302 static const struct sdhci_pci_fixes sdhci_cafe = {
303 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
304 SDHCI_QUIRK_NO_BUSY_IRQ |
305 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
306 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
309 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
310 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
313 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
315 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
320 * ADMA operation is disabled for Moorestown platform due to
323 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
326 * slots number is fixed here for MRST as SDIO3/5 are never used and
327 * have hardware bugs.
333 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
335 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
341 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
343 struct sdhci_pci_slot *slot = dev_id;
344 struct sdhci_host *host = slot->host;
346 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
350 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
352 int err, irq, gpio = slot->cd_gpio;
354 slot->cd_gpio = -EINVAL;
355 slot->cd_irq = -EINVAL;
357 if (!gpio_is_valid(gpio))
360 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
364 err = gpio_direction_input(gpio);
368 irq = gpio_to_irq(gpio);
372 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
373 IRQF_TRIGGER_FALLING, "sd_cd", slot);
377 slot->cd_gpio = gpio;
383 devm_gpio_free(&slot->chip->pdev->dev, gpio);
385 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
388 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
390 if (slot->cd_irq >= 0)
391 free_irq(slot->cd_irq, slot);
396 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
400 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
406 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
408 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
409 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
413 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
415 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
419 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
420 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
421 .probe_slot = mrst_hc_probe_slot,
424 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
425 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
426 .probe = mrst_hc_probe,
429 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
430 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
431 .allow_runtime_pm = true,
432 .own_cd_for_runtime_pm = true,
435 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
436 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
437 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
438 .allow_runtime_pm = true,
439 .probe_slot = mfd_sdio_probe_slot,
442 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
443 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
444 .allow_runtime_pm = true,
445 .probe_slot = mfd_emmc_probe_slot,
448 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
449 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
450 .probe_slot = pch_hc_probe_slot,
455 INTEL_DSM_V18_SWITCH = 3,
456 INTEL_DSM_DRV_STRENGTH = 9,
457 INTEL_DSM_D3_RETUNE = 10,
466 static const guid_t intel_dsm_guid =
467 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
468 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
470 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
471 unsigned int fn, u32 *result)
473 union acpi_object *obj;
477 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
481 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
486 len = min_t(size_t, obj->buffer.length, 4);
489 memcpy(result, obj->buffer.pointer, len);
496 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
497 unsigned int fn, u32 *result)
499 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
502 return __intel_dsm(intel_host, dev, fn, result);
505 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
506 struct mmc_host *mmc)
511 intel_host->d3_retune = true;
513 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
515 pr_debug("%s: DSM not supported, error %d\n",
516 mmc_hostname(mmc), err);
520 pr_debug("%s: DSM function mask %#x\n",
521 mmc_hostname(mmc), intel_host->dsm_fns);
523 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
524 intel_host->drv_strength = err ? 0 : val;
526 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
527 intel_host->d3_retune = err ? true : !!val;
530 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
534 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
536 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
537 /* For eMMC, minimum is 1us but give it 9us for good measure */
540 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
541 /* For eMMC, minimum is 200us but give it 300us for good measure */
542 usleep_range(300, 1000);
545 static int intel_select_drive_strength(struct mmc_card *card,
546 unsigned int max_dtr, int host_drv,
547 int card_drv, int *drv_type)
549 struct sdhci_host *host = mmc_priv(card->host);
550 struct sdhci_pci_slot *slot = sdhci_priv(host);
551 struct intel_host *intel_host = sdhci_pci_priv(slot);
553 return intel_host->drv_strength;
556 static int bxt_get_cd(struct mmc_host *mmc)
558 int gpio_cd = mmc_gpio_get_cd(mmc);
559 struct sdhci_host *host = mmc_priv(mmc);
566 spin_lock_irqsave(&host->lock, flags);
568 if (host->flags & SDHCI_DEVICE_DEAD)
571 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
573 spin_unlock_irqrestore(&host->lock, flags);
578 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
579 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
581 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
587 sdhci_set_power(host, mode, vdd);
589 if (mode == MMC_POWER_OFF)
593 * Bus power might not enable after D3 -> D0 transition due to the
594 * present state not yet having propagated. Retry for up to 2ms.
596 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
597 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
598 if (reg & SDHCI_POWER_ON)
600 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
601 reg |= SDHCI_POWER_ON;
602 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
606 #define INTEL_HS400_ES_REG 0x78
607 #define INTEL_HS400_ES_BIT BIT(0)
609 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
612 struct sdhci_host *host = mmc_priv(mmc);
615 val = sdhci_readl(host, INTEL_HS400_ES_REG);
616 if (ios->enhanced_strobe)
617 val |= INTEL_HS400_ES_BIT;
619 val &= ~INTEL_HS400_ES_BIT;
620 sdhci_writel(host, val, INTEL_HS400_ES_REG);
623 static void sdhci_intel_voltage_switch(struct sdhci_host *host)
625 struct sdhci_pci_slot *slot = sdhci_priv(host);
626 struct intel_host *intel_host = sdhci_pci_priv(slot);
627 struct device *dev = &slot->chip->pdev->dev;
631 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
632 pr_debug("%s: %s DSM error %d result %u\n",
633 mmc_hostname(host->mmc), __func__, err, result);
636 static const struct sdhci_ops sdhci_intel_byt_ops = {
637 .set_clock = sdhci_set_clock,
638 .set_power = sdhci_intel_set_power,
639 .enable_dma = sdhci_pci_enable_dma,
640 .set_bus_width = sdhci_set_bus_width,
641 .reset = sdhci_reset,
642 .set_uhs_signaling = sdhci_set_uhs_signaling,
643 .hw_reset = sdhci_pci_hw_reset,
644 .voltage_switch = sdhci_intel_voltage_switch,
647 static const struct sdhci_ops sdhci_intel_glk_ops = {
648 .set_clock = sdhci_set_clock,
649 .set_power = sdhci_intel_set_power,
650 .enable_dma = sdhci_pci_enable_dma,
651 .set_bus_width = sdhci_set_bus_width,
652 .reset = sdhci_reset,
653 .set_uhs_signaling = sdhci_set_uhs_signaling,
654 .hw_reset = sdhci_pci_hw_reset,
655 .voltage_switch = sdhci_intel_voltage_switch,
656 .irq = sdhci_cqhci_irq,
659 static void byt_read_dsm(struct sdhci_pci_slot *slot)
661 struct intel_host *intel_host = sdhci_pci_priv(slot);
662 struct device *dev = &slot->chip->pdev->dev;
663 struct mmc_host *mmc = slot->host->mmc;
665 intel_dsm_init(intel_host, dev, mmc);
666 slot->chip->rpm_retune = intel_host->d3_retune;
669 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
671 int err = sdhci_execute_tuning(mmc, opcode);
672 struct sdhci_host *host = mmc_priv(mmc);
678 * Tuning can leave the IP in an active state (Buffer Read Enable bit
679 * set) which prevents the entry to low power states (i.e. S0i3). Data
680 * reset will clear it.
682 sdhci_reset(host, SDHCI_RESET_DATA);
687 static void byt_probe_slot(struct sdhci_pci_slot *slot)
689 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
693 ops->execute_tuning = intel_execute_tuning;
696 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
698 byt_probe_slot(slot);
699 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
700 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
701 MMC_CAP_CMD_DURING_TFR |
702 MMC_CAP_WAIT_WHILE_BUSY;
703 slot->hw_reset = sdhci_pci_int_hw_reset;
704 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
705 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
706 slot->host->mmc_host_ops.select_drive_strength =
707 intel_select_drive_strength;
711 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
713 int ret = byt_emmc_probe_slot(slot);
715 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
717 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
718 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
719 slot->host->mmc_host_ops.hs400_enhanced_strobe =
720 intel_hs400_enhanced_strobe;
721 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
727 static const struct cqhci_host_ops glk_cqhci_ops = {
728 .enable = sdhci_cqe_enable,
729 .disable = sdhci_cqe_disable,
730 .dumpregs = sdhci_pci_dumpregs,
733 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
735 struct device *dev = &slot->chip->pdev->dev;
736 struct sdhci_host *host = slot->host;
737 struct cqhci_host *cq_host;
741 ret = sdhci_setup_host(host);
745 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
751 cq_host->mmio = host->ioaddr + 0x200;
752 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
753 cq_host->ops = &glk_cqhci_ops;
755 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
757 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
759 ret = cqhci_init(cq_host, host->mmc, dma64);
763 ret = __sdhci_add_host(host);
770 sdhci_cleanup_host(host);
775 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
778 unsigned long long max_freq;
780 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
781 "MXFQ", NULL, &max_freq);
782 if (ACPI_FAILURE(status)) {
783 dev_err(&slot->chip->pdev->dev,
784 "MXFQ not found in acpi table\n");
788 slot->host->mmc->f_max = max_freq * 1000000;
793 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
799 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
803 byt_probe_slot(slot);
805 err = ni_set_max_freq(slot);
809 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
810 MMC_CAP_WAIT_WHILE_BUSY;
814 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
816 byt_probe_slot(slot);
817 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
818 MMC_CAP_WAIT_WHILE_BUSY;
822 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
824 byt_probe_slot(slot);
825 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
826 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
828 slot->cd_override_level = true;
829 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
830 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
831 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
832 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
833 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
838 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
839 .allow_runtime_pm = true,
840 .probe_slot = byt_emmc_probe_slot,
841 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
842 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
843 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
844 SDHCI_QUIRK2_STOP_WITH_TC,
845 .ops = &sdhci_intel_byt_ops,
846 .priv_size = sizeof(struct intel_host),
849 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
850 .allow_runtime_pm = true,
851 .probe_slot = glk_emmc_probe_slot,
852 .add_host = glk_emmc_add_host,
853 #ifdef CONFIG_PM_SLEEP
854 .suspend = sdhci_cqhci_suspend,
855 .resume = sdhci_cqhci_resume,
858 .runtime_suspend = sdhci_cqhci_runtime_suspend,
859 .runtime_resume = sdhci_cqhci_runtime_resume,
861 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
862 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
863 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
864 SDHCI_QUIRK2_STOP_WITH_TC,
865 .ops = &sdhci_intel_glk_ops,
866 .priv_size = sizeof(struct intel_host),
869 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
870 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
871 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
872 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
873 .allow_runtime_pm = true,
874 .probe_slot = ni_byt_sdio_probe_slot,
875 .ops = &sdhci_intel_byt_ops,
876 .priv_size = sizeof(struct intel_host),
879 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
880 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
881 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
882 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
883 .allow_runtime_pm = true,
884 .probe_slot = byt_sdio_probe_slot,
885 .ops = &sdhci_intel_byt_ops,
886 .priv_size = sizeof(struct intel_host),
889 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
890 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
891 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
892 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
893 SDHCI_QUIRK2_STOP_WITH_TC,
894 .allow_runtime_pm = true,
895 .own_cd_for_runtime_pm = true,
896 .probe_slot = byt_sd_probe_slot,
897 .ops = &sdhci_intel_byt_ops,
898 .priv_size = sizeof(struct intel_host),
901 /* Define Host controllers for Intel Merrifield platform */
902 #define INTEL_MRFLD_EMMC_0 0
903 #define INTEL_MRFLD_EMMC_1 1
904 #define INTEL_MRFLD_SD 2
905 #define INTEL_MRFLD_SDIO 3
908 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
910 struct acpi_device *device, *child;
912 device = ACPI_COMPANION(&slot->chip->pdev->dev);
916 acpi_device_fix_up_power(device);
917 list_for_each_entry(child, &device->children, node)
918 if (child->status.present && child->status.enabled)
919 acpi_device_fix_up_power(child);
922 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
925 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
927 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
930 case INTEL_MRFLD_EMMC_0:
931 case INTEL_MRFLD_EMMC_1:
932 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
937 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
939 case INTEL_MRFLD_SDIO:
940 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
941 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
942 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
943 MMC_CAP_POWER_OFF_CARD;
949 intel_mrfld_mmc_fix_up_power_slot(slot);
953 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
954 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
955 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
956 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
957 .allow_runtime_pm = true,
958 .probe_slot = intel_mrfld_mmc_probe_slot,
961 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
966 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
971 * Turn PMOS on [bit 0], set over current detection to 2.4 V
972 * [bit 1:2] and enable over current debouncing [bit 6].
979 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
982 static int jmicron_probe(struct sdhci_pci_chip *chip)
987 if (chip->pdev->revision == 0) {
988 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
989 SDHCI_QUIRK_32BIT_DMA_SIZE |
990 SDHCI_QUIRK_32BIT_ADMA_SIZE |
991 SDHCI_QUIRK_RESET_AFTER_REQUEST |
992 SDHCI_QUIRK_BROKEN_SMALL_PIO;
996 * JMicron chips can have two interfaces to the same hardware
997 * in order to work around limitations in Microsoft's driver.
998 * We need to make sure we only bind to one of them.
1000 * This code assumes two things:
1002 * 1. The PCI code adds subfunctions in order.
1004 * 2. The MMC interface has a lower subfunction number
1005 * than the SD interface.
1007 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1008 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1009 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1010 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1013 struct pci_dev *sd_dev;
1016 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1017 mmcdev, sd_dev)) != NULL) {
1018 if ((PCI_SLOT(chip->pdev->devfn) ==
1019 PCI_SLOT(sd_dev->devfn)) &&
1020 (chip->pdev->bus == sd_dev->bus))
1025 pci_dev_put(sd_dev);
1026 dev_info(&chip->pdev->dev, "Refusing to bind to "
1027 "secondary interface.\n");
1033 * JMicron chips need a bit of a nudge to enable the power
1036 ret = jmicron_pmos(chip, 1);
1038 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1042 /* quirk for unsable RO-detection on JM388 chips */
1043 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1044 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1045 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1050 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1054 scratch = readb(host->ioaddr + 0xC0);
1061 writeb(scratch, host->ioaddr + 0xC0);
1064 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1066 if (slot->chip->pdev->revision == 0) {
1069 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1070 version = (version & SDHCI_VENDOR_VER_MASK) >>
1071 SDHCI_VENDOR_VER_SHIFT;
1074 * Older versions of the chip have lots of nasty glitches
1075 * in the ADMA engine. It's best just to avoid it
1079 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1082 /* JM388 MMC doesn't support 1.8V while SD supports it */
1083 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1084 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1085 MMC_VDD_29_30 | MMC_VDD_30_31 |
1086 MMC_VDD_165_195; /* allow 1.8V */
1087 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1088 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1092 * The secondary interface requires a bit set to get the
1095 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1096 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1097 jmicron_enable_mmc(slot->host, 1);
1099 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1104 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1109 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1110 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1111 jmicron_enable_mmc(slot->host, 0);
1114 #ifdef CONFIG_PM_SLEEP
1115 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1119 ret = sdhci_pci_suspend_host(chip);
1123 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1124 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1125 for (i = 0; i < chip->num_slots; i++)
1126 jmicron_enable_mmc(chip->slots[i]->host, 0);
1132 static int jmicron_resume(struct sdhci_pci_chip *chip)
1136 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1137 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1138 for (i = 0; i < chip->num_slots; i++)
1139 jmicron_enable_mmc(chip->slots[i]->host, 1);
1142 ret = jmicron_pmos(chip, 1);
1144 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1148 return sdhci_pci_resume_host(chip);
1152 static const struct sdhci_pci_fixes sdhci_o2 = {
1153 .probe = sdhci_pci_o2_probe,
1154 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1155 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1156 .probe_slot = sdhci_pci_o2_probe_slot,
1157 #ifdef CONFIG_PM_SLEEP
1158 .resume = sdhci_pci_o2_resume,
1162 static const struct sdhci_pci_fixes sdhci_jmicron = {
1163 .probe = jmicron_probe,
1165 .probe_slot = jmicron_probe_slot,
1166 .remove_slot = jmicron_remove_slot,
1168 #ifdef CONFIG_PM_SLEEP
1169 .suspend = jmicron_suspend,
1170 .resume = jmicron_resume,
1174 /* SysKonnect CardBus2SDIO extra registers */
1175 #define SYSKT_CTRL 0x200
1176 #define SYSKT_RDFIFO_STAT 0x204
1177 #define SYSKT_WRFIFO_STAT 0x208
1178 #define SYSKT_POWER_DATA 0x20c
1179 #define SYSKT_POWER_330 0xef
1180 #define SYSKT_POWER_300 0xf8
1181 #define SYSKT_POWER_184 0xcc
1182 #define SYSKT_POWER_CMD 0x20d
1183 #define SYSKT_POWER_START (1 << 7)
1184 #define SYSKT_POWER_STATUS 0x20e
1185 #define SYSKT_POWER_STATUS_OK (1 << 0)
1186 #define SYSKT_BOARD_REV 0x210
1187 #define SYSKT_CHIP_REV 0x211
1188 #define SYSKT_CONF_DATA 0x212
1189 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1190 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1191 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1193 static int syskt_probe(struct sdhci_pci_chip *chip)
1195 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1196 chip->pdev->class &= ~0x0000FF;
1197 chip->pdev->class |= PCI_SDHCI_IFDMA;
1202 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1206 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1207 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1208 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1209 "board rev %d.%d, chip rev %d.%d\n",
1210 board_rev >> 4, board_rev & 0xf,
1211 chip_rev >> 4, chip_rev & 0xf);
1212 if (chip_rev >= 0x20)
1213 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1215 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1216 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1218 tm = 10; /* Wait max 1 ms */
1220 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1221 if (ps & SYSKT_POWER_STATUS_OK)
1226 dev_err(&slot->chip->pdev->dev,
1227 "power regulator never stabilized");
1228 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1235 static const struct sdhci_pci_fixes sdhci_syskt = {
1236 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1237 .probe = syskt_probe,
1238 .probe_slot = syskt_probe_slot,
1241 static int via_probe(struct sdhci_pci_chip *chip)
1243 if (chip->pdev->revision == 0x10)
1244 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1249 static const struct sdhci_pci_fixes sdhci_via = {
1253 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1255 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1259 static const struct sdhci_pci_fixes sdhci_rtsx = {
1260 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1261 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1262 SDHCI_QUIRK2_BROKEN_DDR50,
1263 .probe_slot = rtsx_probe_slot,
1266 /*AMD chipset generation*/
1267 enum amd_chipset_gen {
1268 AMD_CHIPSET_BEFORE_ML,
1271 AMD_CHIPSET_UNKNOWN,
1275 #define AMD_SD_AUTO_PATTERN 0xB8
1276 #define AMD_MSLEEP_DURATION 4
1277 #define AMD_SD_MISC_CONTROL 0xD0
1278 #define AMD_MAX_TUNE_VALUE 0x0B
1279 #define AMD_AUTO_TUNE_SEL 0x10800
1280 #define AMD_FIFO_PTR 0x30
1281 #define AMD_BIT_MASK 0x1F
1283 static void amd_tuning_reset(struct sdhci_host *host)
1287 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1288 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1289 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1291 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1292 val &= ~SDHCI_CTRL_EXEC_TUNING;
1293 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1296 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1300 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1301 val &= ~AMD_BIT_MASK;
1302 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1303 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1306 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1310 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1311 val |= AMD_FIFO_PTR;
1312 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1315 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1317 struct sdhci_pci_slot *slot = sdhci_priv(host);
1318 struct pci_dev *pdev = slot->chip->pdev;
1320 u8 valid_win_max = 0;
1321 u8 valid_win_end = 0;
1322 u8 ctrl, tune_around;
1324 amd_tuning_reset(host);
1326 for (tune_around = 0; tune_around < 12; tune_around++) {
1327 amd_config_tuning_phase(pdev, tune_around);
1329 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1331 msleep(AMD_MSLEEP_DURATION);
1332 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1333 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1334 } else if (++valid_win > valid_win_max) {
1335 valid_win_max = valid_win;
1336 valid_win_end = tune_around;
1340 if (!valid_win_max) {
1341 dev_err(&pdev->dev, "no tuning point found\n");
1345 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1347 amd_enable_manual_tuning(pdev);
1349 host->mmc->retune_period = 0;
1354 static int amd_probe(struct sdhci_pci_chip *chip)
1356 struct pci_dev *smbus_dev;
1357 enum amd_chipset_gen gen;
1359 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1360 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1362 gen = AMD_CHIPSET_BEFORE_ML;
1364 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1365 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1367 if (smbus_dev->revision < 0x51)
1368 gen = AMD_CHIPSET_CZ;
1370 gen = AMD_CHIPSET_NL;
1372 gen = AMD_CHIPSET_UNKNOWN;
1376 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1377 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1382 static const struct sdhci_ops amd_sdhci_pci_ops = {
1383 .set_clock = sdhci_set_clock,
1384 .enable_dma = sdhci_pci_enable_dma,
1385 .set_bus_width = sdhci_set_bus_width,
1386 .reset = sdhci_reset,
1387 .set_uhs_signaling = sdhci_set_uhs_signaling,
1388 .platform_execute_tuning = amd_execute_tuning,
1391 static const struct sdhci_pci_fixes sdhci_amd = {
1393 .ops = &amd_sdhci_pci_ops,
1396 static const struct pci_device_id pci_ids[] = {
1397 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1398 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1399 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1400 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1401 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1402 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1403 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1404 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1405 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1406 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1407 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1408 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1409 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1410 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1411 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1412 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1413 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1414 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1415 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1416 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1417 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1418 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1419 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1420 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1421 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1422 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1423 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1424 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1425 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1426 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1427 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1428 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1429 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1430 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1431 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1432 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1433 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1434 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1435 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1436 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1437 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1438 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1439 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1440 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1441 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1442 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1443 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1444 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1445 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1446 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1447 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1448 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1449 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1450 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1451 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1452 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1453 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1454 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1455 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1456 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1457 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1458 SDHCI_PCI_DEVICE(O2, 8120, o2),
1459 SDHCI_PCI_DEVICE(O2, 8220, o2),
1460 SDHCI_PCI_DEVICE(O2, 8221, o2),
1461 SDHCI_PCI_DEVICE(O2, 8320, o2),
1462 SDHCI_PCI_DEVICE(O2, 8321, o2),
1463 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1464 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1465 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1466 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1467 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1468 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1469 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1470 /* Generic SD host controller */
1471 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1472 { /* end: all zeroes */ },
1475 MODULE_DEVICE_TABLE(pci, pci_ids);
1477 /*****************************************************************************\
1479 * SDHCI core callbacks *
1481 \*****************************************************************************/
1483 int sdhci_pci_enable_dma(struct sdhci_host *host)
1485 struct sdhci_pci_slot *slot;
1486 struct pci_dev *pdev;
1488 slot = sdhci_priv(host);
1489 pdev = slot->chip->pdev;
1491 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1492 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1493 (host->flags & SDHCI_USE_SDMA)) {
1494 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1495 "doesn't fully claim to support it.\n");
1498 pci_set_master(pdev);
1503 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1505 struct sdhci_pci_slot *slot = sdhci_priv(host);
1506 int rst_n_gpio = slot->rst_n_gpio;
1508 if (!gpio_is_valid(rst_n_gpio))
1510 gpio_set_value_cansleep(rst_n_gpio, 0);
1511 /* For eMMC, minimum is 1us but give it 10us for good measure */
1513 gpio_set_value_cansleep(rst_n_gpio, 1);
1514 /* For eMMC, minimum is 200us but give it 300us for good measure */
1515 usleep_range(300, 1000);
1518 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1520 struct sdhci_pci_slot *slot = sdhci_priv(host);
1523 slot->hw_reset(host);
1526 static const struct sdhci_ops sdhci_pci_ops = {
1527 .set_clock = sdhci_set_clock,
1528 .enable_dma = sdhci_pci_enable_dma,
1529 .set_bus_width = sdhci_set_bus_width,
1530 .reset = sdhci_reset,
1531 .set_uhs_signaling = sdhci_set_uhs_signaling,
1532 .hw_reset = sdhci_pci_hw_reset,
1535 /*****************************************************************************\
1539 \*****************************************************************************/
1541 #ifdef CONFIG_PM_SLEEP
1542 static int sdhci_pci_suspend(struct device *dev)
1544 struct pci_dev *pdev = to_pci_dev(dev);
1545 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1550 if (chip->fixes && chip->fixes->suspend)
1551 return chip->fixes->suspend(chip);
1553 return sdhci_pci_suspend_host(chip);
1556 static int sdhci_pci_resume(struct device *dev)
1558 struct pci_dev *pdev = to_pci_dev(dev);
1559 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1564 if (chip->fixes && chip->fixes->resume)
1565 return chip->fixes->resume(chip);
1567 return sdhci_pci_resume_host(chip);
1572 static int sdhci_pci_runtime_suspend(struct device *dev)
1574 struct pci_dev *pdev = to_pci_dev(dev);
1575 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1580 if (chip->fixes && chip->fixes->runtime_suspend)
1581 return chip->fixes->runtime_suspend(chip);
1583 return sdhci_pci_runtime_suspend_host(chip);
1586 static int sdhci_pci_runtime_resume(struct device *dev)
1588 struct pci_dev *pdev = to_pci_dev(dev);
1589 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1594 if (chip->fixes && chip->fixes->runtime_resume)
1595 return chip->fixes->runtime_resume(chip);
1597 return sdhci_pci_runtime_resume_host(chip);
1601 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1602 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1603 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1604 sdhci_pci_runtime_resume, NULL)
1607 /*****************************************************************************\
1609 * Device probing/removal *
1611 \*****************************************************************************/
1613 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1614 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1617 struct sdhci_pci_slot *slot;
1618 struct sdhci_host *host;
1619 int ret, bar = first_bar + slotno;
1620 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1622 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1623 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1624 return ERR_PTR(-ENODEV);
1627 if (pci_resource_len(pdev, bar) < 0x100) {
1628 dev_err(&pdev->dev, "Invalid iomem size. You may "
1629 "experience problems.\n");
1632 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1633 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1634 return ERR_PTR(-ENODEV);
1637 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1638 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1639 return ERR_PTR(-ENODEV);
1642 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1644 dev_err(&pdev->dev, "cannot allocate host\n");
1645 return ERR_CAST(host);
1648 slot = sdhci_priv(host);
1652 slot->rst_n_gpio = -EINVAL;
1653 slot->cd_gpio = -EINVAL;
1656 /* Retrieve platform data if there is any */
1657 if (*sdhci_pci_get_data)
1658 slot->data = sdhci_pci_get_data(pdev, slotno);
1661 if (slot->data->setup) {
1662 ret = slot->data->setup(slot->data);
1664 dev_err(&pdev->dev, "platform setup failed\n");
1668 slot->rst_n_gpio = slot->data->rst_n_gpio;
1669 slot->cd_gpio = slot->data->cd_gpio;
1672 host->hw_name = "PCI";
1673 host->ops = chip->fixes && chip->fixes->ops ?
1676 host->quirks = chip->quirks;
1677 host->quirks2 = chip->quirks2;
1679 host->irq = pdev->irq;
1681 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1683 dev_err(&pdev->dev, "cannot request region\n");
1687 host->ioaddr = pcim_iomap_table(pdev)[bar];
1689 if (chip->fixes && chip->fixes->probe_slot) {
1690 ret = chip->fixes->probe_slot(slot);
1695 if (gpio_is_valid(slot->rst_n_gpio)) {
1696 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1697 gpio_direction_output(slot->rst_n_gpio, 1);
1698 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1699 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1701 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1702 slot->rst_n_gpio = -EINVAL;
1706 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
1707 host->mmc->slotno = slotno;
1708 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1710 if (device_can_wakeup(&pdev->dev))
1711 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1713 if (host->mmc->caps & MMC_CAP_CD_WAKE)
1714 device_init_wakeup(&pdev->dev, true);
1716 if (slot->cd_idx >= 0) {
1717 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1718 slot->cd_override_level, 0, NULL);
1719 if (ret == -EPROBE_DEFER)
1723 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1728 if (chip->fixes && chip->fixes->add_host)
1729 ret = chip->fixes->add_host(slot);
1731 ret = sdhci_add_host(host);
1735 sdhci_pci_add_own_cd(slot);
1738 * Check if the chip needs a separate GPIO for card detect to wake up
1739 * from runtime suspend. If it is not there, don't allow runtime PM.
1740 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1742 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1743 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1744 chip->allow_runtime_pm = false;
1749 if (chip->fixes && chip->fixes->remove_slot)
1750 chip->fixes->remove_slot(slot, 0);
1753 if (slot->data && slot->data->cleanup)
1754 slot->data->cleanup(slot->data);
1757 sdhci_free_host(host);
1759 return ERR_PTR(ret);
1762 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1767 sdhci_pci_remove_own_cd(slot);
1770 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1771 if (scratch == (u32)-1)
1774 sdhci_remove_host(slot->host, dead);
1776 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1777 slot->chip->fixes->remove_slot(slot, dead);
1779 if (slot->data && slot->data->cleanup)
1780 slot->data->cleanup(slot->data);
1782 sdhci_free_host(slot->host);
1785 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1787 pm_suspend_ignore_children(dev, 1);
1788 pm_runtime_set_autosuspend_delay(dev, 50);
1789 pm_runtime_use_autosuspend(dev);
1790 pm_runtime_allow(dev);
1791 /* Stay active until mmc core scans for a card */
1792 pm_runtime_put_noidle(dev);
1795 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1797 pm_runtime_forbid(dev);
1798 pm_runtime_get_noresume(dev);
1801 static int sdhci_pci_probe(struct pci_dev *pdev,
1802 const struct pci_device_id *ent)
1804 struct sdhci_pci_chip *chip;
1805 struct sdhci_pci_slot *slot;
1807 u8 slots, first_bar;
1810 BUG_ON(pdev == NULL);
1811 BUG_ON(ent == NULL);
1813 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1814 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1816 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1820 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1821 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1825 BUG_ON(slots > MAX_SLOTS);
1827 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1831 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1833 if (first_bar > 5) {
1834 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1838 ret = pcim_enable_device(pdev);
1842 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1847 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1849 chip->quirks = chip->fixes->quirks;
1850 chip->quirks2 = chip->fixes->quirks2;
1851 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1853 chip->num_slots = slots;
1854 chip->pm_retune = true;
1855 chip->rpm_retune = true;
1857 pci_set_drvdata(pdev, chip);
1859 if (chip->fixes && chip->fixes->probe) {
1860 ret = chip->fixes->probe(chip);
1865 slots = chip->num_slots; /* Quirk may have changed this */
1867 for (i = 0; i < slots; i++) {
1868 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1870 for (i--; i >= 0; i--)
1871 sdhci_pci_remove_slot(chip->slots[i]);
1872 return PTR_ERR(slot);
1875 chip->slots[i] = slot;
1878 if (chip->allow_runtime_pm)
1879 sdhci_pci_runtime_pm_allow(&pdev->dev);
1884 static void sdhci_pci_remove(struct pci_dev *pdev)
1887 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1889 if (chip->allow_runtime_pm)
1890 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1892 for (i = 0; i < chip->num_slots; i++)
1893 sdhci_pci_remove_slot(chip->slots[i]);
1896 static struct pci_driver sdhci_driver = {
1897 .name = "sdhci-pci",
1898 .id_table = pci_ids,
1899 .probe = sdhci_pci_probe,
1900 .remove = sdhci_pci_remove,
1902 .pm = &sdhci_pci_pm_ops
1906 module_pci_driver(sdhci_driver);
1908 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1909 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1910 MODULE_LICENSE("GPL");