1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
10 * Thanks to the following companies for their support:
12 * - JMicron (hardware and technical support)
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/device.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/scatterlist.h>
27 #include <linux/gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
36 #include "sdhci-pci.h"
38 static void sdhci_pci_hw_reset(struct sdhci_host *host);
40 #ifdef CONFIG_PM_SLEEP
41 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
43 mmc_pm_flag_t pm_flags = 0;
46 for (i = 0; i < chip->num_slots; i++) {
47 struct sdhci_pci_slot *slot = chip->slots[i];
50 pm_flags |= slot->host->mmc->pm_flags;
53 return device_set_wakeup_enable(&chip->pdev->dev,
54 (pm_flags & MMC_PM_KEEP_POWER) &&
55 (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
58 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
62 sdhci_pci_init_wakeup(chip);
64 for (i = 0; i < chip->num_slots; i++) {
65 struct sdhci_pci_slot *slot = chip->slots[i];
66 struct sdhci_host *host;
73 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
74 mmc_retune_needed(host->mmc);
76 ret = sdhci_suspend_host(host);
85 sdhci_resume_host(chip->slots[i]->host);
89 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
91 struct sdhci_pci_slot *slot;
94 for (i = 0; i < chip->num_slots; i++) {
95 slot = chip->slots[i];
99 ret = sdhci_resume_host(slot->host);
107 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
111 ret = cqhci_suspend(chip->slots[0]->host->mmc);
115 return sdhci_pci_suspend_host(chip);
118 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
122 ret = sdhci_pci_resume_host(chip);
126 return cqhci_resume(chip->slots[0]->host->mmc);
131 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
133 struct sdhci_pci_slot *slot;
134 struct sdhci_host *host;
137 for (i = 0; i < chip->num_slots; i++) {
138 slot = chip->slots[i];
144 ret = sdhci_runtime_suspend_host(host);
146 goto err_pci_runtime_suspend;
148 if (chip->rpm_retune &&
149 host->tuning_mode != SDHCI_TUNING_MODE_3)
150 mmc_retune_needed(host->mmc);
155 err_pci_runtime_suspend:
157 sdhci_runtime_resume_host(chip->slots[i]->host);
161 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
163 struct sdhci_pci_slot *slot;
166 for (i = 0; i < chip->num_slots; i++) {
167 slot = chip->slots[i];
171 ret = sdhci_runtime_resume_host(slot->host);
179 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
183 ret = cqhci_suspend(chip->slots[0]->host->mmc);
187 return sdhci_pci_runtime_suspend_host(chip);
190 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
194 ret = sdhci_pci_runtime_resume_host(chip);
198 return cqhci_resume(chip->slots[0]->host->mmc);
202 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
207 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
210 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
215 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
217 sdhci_dumpregs(mmc_priv(mmc));
220 /*****************************************************************************\
222 * Hardware specific quirk handling *
224 \*****************************************************************************/
226 static int ricoh_probe(struct sdhci_pci_chip *chip)
228 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
229 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
230 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
234 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
237 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
238 & SDHCI_TIMEOUT_CLK_MASK) |
240 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
241 & SDHCI_CLOCK_BASE_MASK) |
243 SDHCI_TIMEOUT_CLK_UNIT |
250 #ifdef CONFIG_PM_SLEEP
251 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
253 /* Apply a delay to allow controller to settle */
254 /* Otherwise it becomes confused if card state changed
257 return sdhci_pci_resume_host(chip);
261 static const struct sdhci_pci_fixes sdhci_ricoh = {
262 .probe = ricoh_probe,
263 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
264 SDHCI_QUIRK_FORCE_DMA |
265 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
268 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
269 .probe_slot = ricoh_mmc_probe_slot,
270 #ifdef CONFIG_PM_SLEEP
271 .resume = ricoh_mmc_resume,
273 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
274 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
275 SDHCI_QUIRK_NO_CARD_NO_RESET |
276 SDHCI_QUIRK_MISSING_CAPS
279 static const struct sdhci_pci_fixes sdhci_ene_712 = {
280 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
281 SDHCI_QUIRK_BROKEN_DMA,
284 static const struct sdhci_pci_fixes sdhci_ene_714 = {
285 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
286 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
287 SDHCI_QUIRK_BROKEN_DMA,
290 static const struct sdhci_pci_fixes sdhci_cafe = {
291 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
292 SDHCI_QUIRK_NO_BUSY_IRQ |
293 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
294 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
297 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
298 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
301 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
303 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
308 * ADMA operation is disabled for Moorestown platform due to
311 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
314 * slots number is fixed here for MRST as SDIO3/5 are never used and
315 * have hardware bugs.
321 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
323 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
329 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
331 struct sdhci_pci_slot *slot = dev_id;
332 struct sdhci_host *host = slot->host;
334 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
338 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
340 int err, irq, gpio = slot->cd_gpio;
342 slot->cd_gpio = -EINVAL;
343 slot->cd_irq = -EINVAL;
345 if (!gpio_is_valid(gpio))
348 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
352 err = gpio_direction_input(gpio);
356 irq = gpio_to_irq(gpio);
360 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
361 IRQF_TRIGGER_FALLING, "sd_cd", slot);
365 slot->cd_gpio = gpio;
371 devm_gpio_free(&slot->chip->pdev->dev, gpio);
373 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
376 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
378 if (slot->cd_irq >= 0)
379 free_irq(slot->cd_irq, slot);
384 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
388 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
394 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
396 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
397 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
401 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
403 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
407 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
408 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
409 .probe_slot = mrst_hc_probe_slot,
412 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
413 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
414 .probe = mrst_hc_probe,
417 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
418 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
419 .allow_runtime_pm = true,
420 .own_cd_for_runtime_pm = true,
423 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
424 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
425 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
426 .allow_runtime_pm = true,
427 .probe_slot = mfd_sdio_probe_slot,
430 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
431 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
432 .allow_runtime_pm = true,
433 .probe_slot = mfd_emmc_probe_slot,
436 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
437 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
438 .probe_slot = pch_hc_probe_slot,
443 INTEL_DSM_V18_SWITCH = 3,
444 INTEL_DSM_DRV_STRENGTH = 9,
445 INTEL_DSM_D3_RETUNE = 10,
454 static const guid_t intel_dsm_guid =
455 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
456 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
458 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
459 unsigned int fn, u32 *result)
461 union acpi_object *obj;
465 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
469 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
474 len = min_t(size_t, obj->buffer.length, 4);
477 memcpy(result, obj->buffer.pointer, len);
484 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
485 unsigned int fn, u32 *result)
487 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
490 return __intel_dsm(intel_host, dev, fn, result);
493 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
494 struct mmc_host *mmc)
499 intel_host->d3_retune = true;
501 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
503 pr_debug("%s: DSM not supported, error %d\n",
504 mmc_hostname(mmc), err);
508 pr_debug("%s: DSM function mask %#x\n",
509 mmc_hostname(mmc), intel_host->dsm_fns);
511 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
512 intel_host->drv_strength = err ? 0 : val;
514 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
515 intel_host->d3_retune = err ? true : !!val;
518 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
522 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
524 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
525 /* For eMMC, minimum is 1us but give it 9us for good measure */
528 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
529 /* For eMMC, minimum is 200us but give it 300us for good measure */
530 usleep_range(300, 1000);
533 static int intel_select_drive_strength(struct mmc_card *card,
534 unsigned int max_dtr, int host_drv,
535 int card_drv, int *drv_type)
537 struct sdhci_host *host = mmc_priv(card->host);
538 struct sdhci_pci_slot *slot = sdhci_priv(host);
539 struct intel_host *intel_host = sdhci_pci_priv(slot);
541 return intel_host->drv_strength;
544 static int bxt_get_cd(struct mmc_host *mmc)
546 int gpio_cd = mmc_gpio_get_cd(mmc);
547 struct sdhci_host *host = mmc_priv(mmc);
554 spin_lock_irqsave(&host->lock, flags);
556 if (host->flags & SDHCI_DEVICE_DEAD)
559 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
561 spin_unlock_irqrestore(&host->lock, flags);
566 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
567 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
569 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
575 sdhci_set_power(host, mode, vdd);
577 if (mode == MMC_POWER_OFF)
581 * Bus power might not enable after D3 -> D0 transition due to the
582 * present state not yet having propagated. Retry for up to 2ms.
584 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
585 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
586 if (reg & SDHCI_POWER_ON)
588 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
589 reg |= SDHCI_POWER_ON;
590 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
594 #define INTEL_HS400_ES_REG 0x78
595 #define INTEL_HS400_ES_BIT BIT(0)
597 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
600 struct sdhci_host *host = mmc_priv(mmc);
603 val = sdhci_readl(host, INTEL_HS400_ES_REG);
604 if (ios->enhanced_strobe)
605 val |= INTEL_HS400_ES_BIT;
607 val &= ~INTEL_HS400_ES_BIT;
608 sdhci_writel(host, val, INTEL_HS400_ES_REG);
611 static void sdhci_intel_voltage_switch(struct sdhci_host *host)
613 struct sdhci_pci_slot *slot = sdhci_priv(host);
614 struct intel_host *intel_host = sdhci_pci_priv(slot);
615 struct device *dev = &slot->chip->pdev->dev;
619 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
620 pr_debug("%s: %s DSM error %d result %u\n",
621 mmc_hostname(host->mmc), __func__, err, result);
624 static const struct sdhci_ops sdhci_intel_byt_ops = {
625 .set_clock = sdhci_set_clock,
626 .set_power = sdhci_intel_set_power,
627 .enable_dma = sdhci_pci_enable_dma,
628 .set_bus_width = sdhci_set_bus_width,
629 .reset = sdhci_reset,
630 .set_uhs_signaling = sdhci_set_uhs_signaling,
631 .hw_reset = sdhci_pci_hw_reset,
632 .voltage_switch = sdhci_intel_voltage_switch,
635 static const struct sdhci_ops sdhci_intel_glk_ops = {
636 .set_clock = sdhci_set_clock,
637 .set_power = sdhci_intel_set_power,
638 .enable_dma = sdhci_pci_enable_dma,
639 .set_bus_width = sdhci_set_bus_width,
640 .reset = sdhci_reset,
641 .set_uhs_signaling = sdhci_set_uhs_signaling,
642 .hw_reset = sdhci_pci_hw_reset,
643 .voltage_switch = sdhci_intel_voltage_switch,
644 .irq = sdhci_cqhci_irq,
647 static void byt_read_dsm(struct sdhci_pci_slot *slot)
649 struct intel_host *intel_host = sdhci_pci_priv(slot);
650 struct device *dev = &slot->chip->pdev->dev;
651 struct mmc_host *mmc = slot->host->mmc;
653 intel_dsm_init(intel_host, dev, mmc);
654 slot->chip->rpm_retune = intel_host->d3_retune;
657 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
660 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
661 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
662 MMC_CAP_CMD_DURING_TFR |
663 MMC_CAP_WAIT_WHILE_BUSY;
664 slot->hw_reset = sdhci_pci_int_hw_reset;
665 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
666 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
667 slot->host->mmc_host_ops.select_drive_strength =
668 intel_select_drive_strength;
672 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
674 int ret = byt_emmc_probe_slot(slot);
676 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
678 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
679 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
680 slot->host->mmc_host_ops.hs400_enhanced_strobe =
681 intel_hs400_enhanced_strobe;
682 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
688 static void glk_cqe_enable(struct mmc_host *mmc)
690 struct sdhci_host *host = mmc_priv(mmc);
694 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
695 * the case after tuning, so ensure the buffer is drained.
697 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
698 while (reg & SDHCI_DATA_AVAILABLE) {
699 sdhci_readl(host, SDHCI_BUFFER);
700 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
703 sdhci_cqe_enable(mmc);
706 static const struct cqhci_host_ops glk_cqhci_ops = {
707 .enable = glk_cqe_enable,
708 .disable = sdhci_cqe_disable,
709 .dumpregs = sdhci_pci_dumpregs,
712 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
714 struct device *dev = &slot->chip->pdev->dev;
715 struct sdhci_host *host = slot->host;
716 struct cqhci_host *cq_host;
720 ret = sdhci_setup_host(host);
724 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
730 cq_host->mmio = host->ioaddr + 0x200;
731 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
732 cq_host->ops = &glk_cqhci_ops;
734 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
736 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
738 ret = cqhci_init(cq_host, host->mmc, dma64);
742 ret = __sdhci_add_host(host);
749 sdhci_cleanup_host(host);
754 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
757 unsigned long long max_freq;
759 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
760 "MXFQ", NULL, &max_freq);
761 if (ACPI_FAILURE(status)) {
762 dev_err(&slot->chip->pdev->dev,
763 "MXFQ not found in acpi table\n");
767 slot->host->mmc->f_max = max_freq * 1000000;
772 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
778 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
784 err = ni_set_max_freq(slot);
788 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
789 MMC_CAP_WAIT_WHILE_BUSY;
793 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
796 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
797 MMC_CAP_WAIT_WHILE_BUSY;
801 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
804 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
805 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
807 slot->cd_override_level = true;
808 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
809 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
810 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
811 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
812 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
817 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
818 .allow_runtime_pm = true,
819 .probe_slot = byt_emmc_probe_slot,
820 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
821 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
822 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
823 SDHCI_QUIRK2_STOP_WITH_TC,
824 .ops = &sdhci_intel_byt_ops,
825 .priv_size = sizeof(struct intel_host),
828 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
829 .allow_runtime_pm = true,
830 .probe_slot = glk_emmc_probe_slot,
831 .add_host = glk_emmc_add_host,
832 #ifdef CONFIG_PM_SLEEP
833 .suspend = sdhci_cqhci_suspend,
834 .resume = sdhci_cqhci_resume,
837 .runtime_suspend = sdhci_cqhci_runtime_suspend,
838 .runtime_resume = sdhci_cqhci_runtime_resume,
840 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
841 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
842 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
843 SDHCI_QUIRK2_STOP_WITH_TC,
844 .ops = &sdhci_intel_glk_ops,
845 .priv_size = sizeof(struct intel_host),
848 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
849 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
850 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
851 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
852 .allow_runtime_pm = true,
853 .probe_slot = ni_byt_sdio_probe_slot,
854 .ops = &sdhci_intel_byt_ops,
855 .priv_size = sizeof(struct intel_host),
858 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
859 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
860 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
861 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
862 .allow_runtime_pm = true,
863 .probe_slot = byt_sdio_probe_slot,
864 .ops = &sdhci_intel_byt_ops,
865 .priv_size = sizeof(struct intel_host),
868 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
869 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
870 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
871 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
872 SDHCI_QUIRK2_STOP_WITH_TC,
873 .allow_runtime_pm = true,
874 .own_cd_for_runtime_pm = true,
875 .probe_slot = byt_sd_probe_slot,
876 .ops = &sdhci_intel_byt_ops,
877 .priv_size = sizeof(struct intel_host),
880 /* Define Host controllers for Intel Merrifield platform */
881 #define INTEL_MRFLD_EMMC_0 0
882 #define INTEL_MRFLD_EMMC_1 1
883 #define INTEL_MRFLD_SD 2
884 #define INTEL_MRFLD_SDIO 3
887 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
889 struct acpi_device *device, *child;
891 device = ACPI_COMPANION(&slot->chip->pdev->dev);
895 acpi_device_fix_up_power(device);
896 list_for_each_entry(child, &device->children, node)
897 if (child->status.present && child->status.enabled)
898 acpi_device_fix_up_power(child);
901 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
904 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
906 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
909 case INTEL_MRFLD_EMMC_0:
910 case INTEL_MRFLD_EMMC_1:
911 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
916 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
918 case INTEL_MRFLD_SDIO:
919 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
920 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
921 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
922 MMC_CAP_POWER_OFF_CARD;
928 intel_mrfld_mmc_fix_up_power_slot(slot);
932 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
933 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
934 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
935 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
936 .allow_runtime_pm = true,
937 .probe_slot = intel_mrfld_mmc_probe_slot,
940 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
945 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
950 * Turn PMOS on [bit 0], set over current detection to 2.4 V
951 * [bit 1:2] and enable over current debouncing [bit 6].
958 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
961 static int jmicron_probe(struct sdhci_pci_chip *chip)
966 if (chip->pdev->revision == 0) {
967 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
968 SDHCI_QUIRK_32BIT_DMA_SIZE |
969 SDHCI_QUIRK_32BIT_ADMA_SIZE |
970 SDHCI_QUIRK_RESET_AFTER_REQUEST |
971 SDHCI_QUIRK_BROKEN_SMALL_PIO;
975 * JMicron chips can have two interfaces to the same hardware
976 * in order to work around limitations in Microsoft's driver.
977 * We need to make sure we only bind to one of them.
979 * This code assumes two things:
981 * 1. The PCI code adds subfunctions in order.
983 * 2. The MMC interface has a lower subfunction number
984 * than the SD interface.
986 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
987 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
988 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
989 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
992 struct pci_dev *sd_dev;
995 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
996 mmcdev, sd_dev)) != NULL) {
997 if ((PCI_SLOT(chip->pdev->devfn) ==
998 PCI_SLOT(sd_dev->devfn)) &&
999 (chip->pdev->bus == sd_dev->bus))
1004 pci_dev_put(sd_dev);
1005 dev_info(&chip->pdev->dev, "Refusing to bind to "
1006 "secondary interface.\n");
1012 * JMicron chips need a bit of a nudge to enable the power
1015 ret = jmicron_pmos(chip, 1);
1017 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1021 /* quirk for unsable RO-detection on JM388 chips */
1022 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1023 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1024 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1029 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1033 scratch = readb(host->ioaddr + 0xC0);
1040 writeb(scratch, host->ioaddr + 0xC0);
1043 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1045 if (slot->chip->pdev->revision == 0) {
1048 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1049 version = (version & SDHCI_VENDOR_VER_MASK) >>
1050 SDHCI_VENDOR_VER_SHIFT;
1053 * Older versions of the chip have lots of nasty glitches
1054 * in the ADMA engine. It's best just to avoid it
1058 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1061 /* JM388 MMC doesn't support 1.8V while SD supports it */
1062 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1063 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1064 MMC_VDD_29_30 | MMC_VDD_30_31 |
1065 MMC_VDD_165_195; /* allow 1.8V */
1066 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1067 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1071 * The secondary interface requires a bit set to get the
1074 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1075 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1076 jmicron_enable_mmc(slot->host, 1);
1078 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1083 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1088 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1089 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1090 jmicron_enable_mmc(slot->host, 0);
1093 #ifdef CONFIG_PM_SLEEP
1094 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1098 ret = sdhci_pci_suspend_host(chip);
1102 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1103 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1104 for (i = 0; i < chip->num_slots; i++)
1105 jmicron_enable_mmc(chip->slots[i]->host, 0);
1111 static int jmicron_resume(struct sdhci_pci_chip *chip)
1115 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1116 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1117 for (i = 0; i < chip->num_slots; i++)
1118 jmicron_enable_mmc(chip->slots[i]->host, 1);
1121 ret = jmicron_pmos(chip, 1);
1123 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1127 return sdhci_pci_resume_host(chip);
1131 static const struct sdhci_pci_fixes sdhci_o2 = {
1132 .probe = sdhci_pci_o2_probe,
1133 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1134 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1135 .probe_slot = sdhci_pci_o2_probe_slot,
1136 #ifdef CONFIG_PM_SLEEP
1137 .resume = sdhci_pci_o2_resume,
1141 static const struct sdhci_pci_fixes sdhci_jmicron = {
1142 .probe = jmicron_probe,
1144 .probe_slot = jmicron_probe_slot,
1145 .remove_slot = jmicron_remove_slot,
1147 #ifdef CONFIG_PM_SLEEP
1148 .suspend = jmicron_suspend,
1149 .resume = jmicron_resume,
1153 /* SysKonnect CardBus2SDIO extra registers */
1154 #define SYSKT_CTRL 0x200
1155 #define SYSKT_RDFIFO_STAT 0x204
1156 #define SYSKT_WRFIFO_STAT 0x208
1157 #define SYSKT_POWER_DATA 0x20c
1158 #define SYSKT_POWER_330 0xef
1159 #define SYSKT_POWER_300 0xf8
1160 #define SYSKT_POWER_184 0xcc
1161 #define SYSKT_POWER_CMD 0x20d
1162 #define SYSKT_POWER_START (1 << 7)
1163 #define SYSKT_POWER_STATUS 0x20e
1164 #define SYSKT_POWER_STATUS_OK (1 << 0)
1165 #define SYSKT_BOARD_REV 0x210
1166 #define SYSKT_CHIP_REV 0x211
1167 #define SYSKT_CONF_DATA 0x212
1168 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1169 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1170 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1172 static int syskt_probe(struct sdhci_pci_chip *chip)
1174 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1175 chip->pdev->class &= ~0x0000FF;
1176 chip->pdev->class |= PCI_SDHCI_IFDMA;
1181 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1185 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1186 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1187 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1188 "board rev %d.%d, chip rev %d.%d\n",
1189 board_rev >> 4, board_rev & 0xf,
1190 chip_rev >> 4, chip_rev & 0xf);
1191 if (chip_rev >= 0x20)
1192 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1194 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1195 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1197 tm = 10; /* Wait max 1 ms */
1199 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1200 if (ps & SYSKT_POWER_STATUS_OK)
1205 dev_err(&slot->chip->pdev->dev,
1206 "power regulator never stabilized");
1207 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1214 static const struct sdhci_pci_fixes sdhci_syskt = {
1215 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1216 .probe = syskt_probe,
1217 .probe_slot = syskt_probe_slot,
1220 static int via_probe(struct sdhci_pci_chip *chip)
1222 if (chip->pdev->revision == 0x10)
1223 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1228 static const struct sdhci_pci_fixes sdhci_via = {
1232 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1234 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1238 static const struct sdhci_pci_fixes sdhci_rtsx = {
1239 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1240 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1241 SDHCI_QUIRK2_BROKEN_DDR50,
1242 .probe_slot = rtsx_probe_slot,
1245 /*AMD chipset generation*/
1246 enum amd_chipset_gen {
1247 AMD_CHIPSET_BEFORE_ML,
1250 AMD_CHIPSET_UNKNOWN,
1254 #define AMD_SD_AUTO_PATTERN 0xB8
1255 #define AMD_MSLEEP_DURATION 4
1256 #define AMD_SD_MISC_CONTROL 0xD0
1257 #define AMD_MAX_TUNE_VALUE 0x0B
1258 #define AMD_AUTO_TUNE_SEL 0x10800
1259 #define AMD_FIFO_PTR 0x30
1260 #define AMD_BIT_MASK 0x1F
1262 static void amd_tuning_reset(struct sdhci_host *host)
1266 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1267 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1268 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1270 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1271 val &= ~SDHCI_CTRL_EXEC_TUNING;
1272 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1275 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1279 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1280 val &= ~AMD_BIT_MASK;
1281 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1282 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1285 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1289 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1290 val |= AMD_FIFO_PTR;
1291 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1294 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1296 struct sdhci_pci_slot *slot = sdhci_priv(host);
1297 struct pci_dev *pdev = slot->chip->pdev;
1299 u8 valid_win_max = 0;
1300 u8 valid_win_end = 0;
1301 u8 ctrl, tune_around;
1303 amd_tuning_reset(host);
1305 for (tune_around = 0; tune_around < 12; tune_around++) {
1306 amd_config_tuning_phase(pdev, tune_around);
1308 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1310 msleep(AMD_MSLEEP_DURATION);
1311 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1312 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1313 } else if (++valid_win > valid_win_max) {
1314 valid_win_max = valid_win;
1315 valid_win_end = tune_around;
1319 if (!valid_win_max) {
1320 dev_err(&pdev->dev, "no tuning point found\n");
1324 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1326 amd_enable_manual_tuning(pdev);
1328 host->mmc->retune_period = 0;
1333 static int amd_probe(struct sdhci_pci_chip *chip)
1335 struct pci_dev *smbus_dev;
1336 enum amd_chipset_gen gen;
1338 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1339 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1341 gen = AMD_CHIPSET_BEFORE_ML;
1343 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1344 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1346 if (smbus_dev->revision < 0x51)
1347 gen = AMD_CHIPSET_CZ;
1349 gen = AMD_CHIPSET_NL;
1351 gen = AMD_CHIPSET_UNKNOWN;
1355 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1356 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1361 static const struct sdhci_ops amd_sdhci_pci_ops = {
1362 .set_clock = sdhci_set_clock,
1363 .enable_dma = sdhci_pci_enable_dma,
1364 .set_bus_width = sdhci_set_bus_width,
1365 .reset = sdhci_reset,
1366 .set_uhs_signaling = sdhci_set_uhs_signaling,
1367 .platform_execute_tuning = amd_execute_tuning,
1370 static const struct sdhci_pci_fixes sdhci_amd = {
1372 .ops = &amd_sdhci_pci_ops,
1375 static const struct pci_device_id pci_ids[] = {
1376 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1377 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1378 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1379 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1380 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1381 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1382 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1383 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1384 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1385 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1386 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1387 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1388 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1389 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1390 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1391 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1392 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1393 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1394 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1395 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1396 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1397 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1398 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1399 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1400 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1401 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1402 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1403 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1404 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1405 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1406 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1407 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1408 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1409 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1410 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1411 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1412 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1413 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1414 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1415 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1416 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1417 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1418 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1419 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1420 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1421 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1422 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1423 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1424 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1425 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1426 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1427 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1428 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1429 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1430 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1431 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1432 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1433 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1434 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1435 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1436 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1437 SDHCI_PCI_DEVICE(O2, 8120, o2),
1438 SDHCI_PCI_DEVICE(O2, 8220, o2),
1439 SDHCI_PCI_DEVICE(O2, 8221, o2),
1440 SDHCI_PCI_DEVICE(O2, 8320, o2),
1441 SDHCI_PCI_DEVICE(O2, 8321, o2),
1442 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1443 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1444 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1445 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1446 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1447 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1448 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1449 /* Generic SD host controller */
1450 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1451 { /* end: all zeroes */ },
1454 MODULE_DEVICE_TABLE(pci, pci_ids);
1456 /*****************************************************************************\
1458 * SDHCI core callbacks *
1460 \*****************************************************************************/
1462 int sdhci_pci_enable_dma(struct sdhci_host *host)
1464 struct sdhci_pci_slot *slot;
1465 struct pci_dev *pdev;
1467 slot = sdhci_priv(host);
1468 pdev = slot->chip->pdev;
1470 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1471 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1472 (host->flags & SDHCI_USE_SDMA)) {
1473 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1474 "doesn't fully claim to support it.\n");
1477 pci_set_master(pdev);
1482 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1484 struct sdhci_pci_slot *slot = sdhci_priv(host);
1485 int rst_n_gpio = slot->rst_n_gpio;
1487 if (!gpio_is_valid(rst_n_gpio))
1489 gpio_set_value_cansleep(rst_n_gpio, 0);
1490 /* For eMMC, minimum is 1us but give it 10us for good measure */
1492 gpio_set_value_cansleep(rst_n_gpio, 1);
1493 /* For eMMC, minimum is 200us but give it 300us for good measure */
1494 usleep_range(300, 1000);
1497 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1499 struct sdhci_pci_slot *slot = sdhci_priv(host);
1502 slot->hw_reset(host);
1505 static const struct sdhci_ops sdhci_pci_ops = {
1506 .set_clock = sdhci_set_clock,
1507 .enable_dma = sdhci_pci_enable_dma,
1508 .set_bus_width = sdhci_set_bus_width,
1509 .reset = sdhci_reset,
1510 .set_uhs_signaling = sdhci_set_uhs_signaling,
1511 .hw_reset = sdhci_pci_hw_reset,
1514 /*****************************************************************************\
1518 \*****************************************************************************/
1520 #ifdef CONFIG_PM_SLEEP
1521 static int sdhci_pci_suspend(struct device *dev)
1523 struct pci_dev *pdev = to_pci_dev(dev);
1524 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1529 if (chip->fixes && chip->fixes->suspend)
1530 return chip->fixes->suspend(chip);
1532 return sdhci_pci_suspend_host(chip);
1535 static int sdhci_pci_resume(struct device *dev)
1537 struct pci_dev *pdev = to_pci_dev(dev);
1538 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1543 if (chip->fixes && chip->fixes->resume)
1544 return chip->fixes->resume(chip);
1546 return sdhci_pci_resume_host(chip);
1551 static int sdhci_pci_runtime_suspend(struct device *dev)
1553 struct pci_dev *pdev = to_pci_dev(dev);
1554 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1559 if (chip->fixes && chip->fixes->runtime_suspend)
1560 return chip->fixes->runtime_suspend(chip);
1562 return sdhci_pci_runtime_suspend_host(chip);
1565 static int sdhci_pci_runtime_resume(struct device *dev)
1567 struct pci_dev *pdev = to_pci_dev(dev);
1568 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1573 if (chip->fixes && chip->fixes->runtime_resume)
1574 return chip->fixes->runtime_resume(chip);
1576 return sdhci_pci_runtime_resume_host(chip);
1580 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1581 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1582 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1583 sdhci_pci_runtime_resume, NULL)
1586 /*****************************************************************************\
1588 * Device probing/removal *
1590 \*****************************************************************************/
1592 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1593 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1596 struct sdhci_pci_slot *slot;
1597 struct sdhci_host *host;
1598 int ret, bar = first_bar + slotno;
1599 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1601 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1602 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1603 return ERR_PTR(-ENODEV);
1606 if (pci_resource_len(pdev, bar) < 0x100) {
1607 dev_err(&pdev->dev, "Invalid iomem size. You may "
1608 "experience problems.\n");
1611 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1612 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1613 return ERR_PTR(-ENODEV);
1616 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1617 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1618 return ERR_PTR(-ENODEV);
1621 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1623 dev_err(&pdev->dev, "cannot allocate host\n");
1624 return ERR_CAST(host);
1627 slot = sdhci_priv(host);
1631 slot->rst_n_gpio = -EINVAL;
1632 slot->cd_gpio = -EINVAL;
1635 /* Retrieve platform data if there is any */
1636 if (*sdhci_pci_get_data)
1637 slot->data = sdhci_pci_get_data(pdev, slotno);
1640 if (slot->data->setup) {
1641 ret = slot->data->setup(slot->data);
1643 dev_err(&pdev->dev, "platform setup failed\n");
1647 slot->rst_n_gpio = slot->data->rst_n_gpio;
1648 slot->cd_gpio = slot->data->cd_gpio;
1651 host->hw_name = "PCI";
1652 host->ops = chip->fixes && chip->fixes->ops ?
1655 host->quirks = chip->quirks;
1656 host->quirks2 = chip->quirks2;
1658 host->irq = pdev->irq;
1660 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1662 dev_err(&pdev->dev, "cannot request region\n");
1666 host->ioaddr = pcim_iomap_table(pdev)[bar];
1668 if (chip->fixes && chip->fixes->probe_slot) {
1669 ret = chip->fixes->probe_slot(slot);
1674 if (gpio_is_valid(slot->rst_n_gpio)) {
1675 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1676 gpio_direction_output(slot->rst_n_gpio, 1);
1677 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1678 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1680 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1681 slot->rst_n_gpio = -EINVAL;
1685 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
1686 host->mmc->slotno = slotno;
1687 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1689 if (device_can_wakeup(&pdev->dev))
1690 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1692 if (slot->cd_idx >= 0) {
1693 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1694 slot->cd_override_level, 0, NULL);
1695 if (ret == -EPROBE_DEFER)
1699 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1704 if (chip->fixes && chip->fixes->add_host)
1705 ret = chip->fixes->add_host(slot);
1707 ret = sdhci_add_host(host);
1711 sdhci_pci_add_own_cd(slot);
1714 * Check if the chip needs a separate GPIO for card detect to wake up
1715 * from runtime suspend. If it is not there, don't allow runtime PM.
1716 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1718 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1719 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1720 chip->allow_runtime_pm = false;
1725 if (chip->fixes && chip->fixes->remove_slot)
1726 chip->fixes->remove_slot(slot, 0);
1729 if (slot->data && slot->data->cleanup)
1730 slot->data->cleanup(slot->data);
1733 sdhci_free_host(host);
1735 return ERR_PTR(ret);
1738 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1743 sdhci_pci_remove_own_cd(slot);
1746 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1747 if (scratch == (u32)-1)
1750 sdhci_remove_host(slot->host, dead);
1752 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1753 slot->chip->fixes->remove_slot(slot, dead);
1755 if (slot->data && slot->data->cleanup)
1756 slot->data->cleanup(slot->data);
1758 sdhci_free_host(slot->host);
1761 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1763 pm_suspend_ignore_children(dev, 1);
1764 pm_runtime_set_autosuspend_delay(dev, 50);
1765 pm_runtime_use_autosuspend(dev);
1766 pm_runtime_allow(dev);
1767 /* Stay active until mmc core scans for a card */
1768 pm_runtime_put_noidle(dev);
1771 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1773 pm_runtime_forbid(dev);
1774 pm_runtime_get_noresume(dev);
1777 static int sdhci_pci_probe(struct pci_dev *pdev,
1778 const struct pci_device_id *ent)
1780 struct sdhci_pci_chip *chip;
1781 struct sdhci_pci_slot *slot;
1783 u8 slots, first_bar;
1786 BUG_ON(pdev == NULL);
1787 BUG_ON(ent == NULL);
1789 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1790 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1792 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1796 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1797 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1801 BUG_ON(slots > MAX_SLOTS);
1803 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1807 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1809 if (first_bar > 5) {
1810 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1814 ret = pcim_enable_device(pdev);
1818 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1823 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1825 chip->quirks = chip->fixes->quirks;
1826 chip->quirks2 = chip->fixes->quirks2;
1827 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1829 chip->num_slots = slots;
1830 chip->pm_retune = true;
1831 chip->rpm_retune = true;
1833 pci_set_drvdata(pdev, chip);
1835 if (chip->fixes && chip->fixes->probe) {
1836 ret = chip->fixes->probe(chip);
1841 slots = chip->num_slots; /* Quirk may have changed this */
1843 for (i = 0; i < slots; i++) {
1844 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1846 for (i--; i >= 0; i--)
1847 sdhci_pci_remove_slot(chip->slots[i]);
1848 return PTR_ERR(slot);
1851 chip->slots[i] = slot;
1854 if (chip->allow_runtime_pm)
1855 sdhci_pci_runtime_pm_allow(&pdev->dev);
1860 static void sdhci_pci_remove(struct pci_dev *pdev)
1863 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1865 if (chip->allow_runtime_pm)
1866 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1868 for (i = 0; i < chip->num_slots; i++)
1869 sdhci_pci_remove_slot(chip->slots[i]);
1872 static struct pci_driver sdhci_driver = {
1873 .name = "sdhci-pci",
1874 .id_table = pci_ids,
1875 .probe = sdhci_pci_probe,
1876 .remove = sdhci_pci_remove,
1878 .pm = &sdhci_pci_pm_ops
1882 module_pci_driver(sdhci_driver);
1884 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1885 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1886 MODULE_LICENSE("GPL");