1 // SPDX-License-Identifier: GPL-2.0
3 // Secure Digital Host Controller
5 // Copyright (C) 2018 Spreadtrum, Inc.
6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/highmem.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_gpio.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/slab.h>
21 #include "sdhci-pltfm.h"
23 /* SDHCI_ARGUMENT2 register high 16bit */
24 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
26 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200
27 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
28 #define SDHCI_SPRD_DLL_EN BIT(21)
29 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
30 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
31 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
33 #define SDHCI_SPRD_REG_32_DLL_DLY 0x204
35 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
36 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
37 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
38 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
39 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
41 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
42 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
43 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
45 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C
46 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
47 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
49 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
51 /* SDHCI_HOST_CONTROL2 */
52 #define SDHCI_SPRD_CTRL_HS200 0x0005
53 #define SDHCI_SPRD_CTRL_HS400 0x0006
54 #define SDHCI_SPRD_CTRL_HS400ES 0x0007
57 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
58 * reserved, and only used on Spreadtrum's design, the hardware cannot work
59 * if this bit is cleared.
63 #define SDHCI_HW_RESET_CARD BIT(3)
65 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF
66 #define SDHCI_SPRD_CLK_MAX_DIV 1023
68 #define SDHCI_SPRD_CLK_DEF_RATE 26000000
69 #define SDHCI_SPRD_PHY_DLL_CLK 52000000
71 struct sdhci_sprd_host {
74 struct clk *clk_enable;
75 struct clk *clk_2x_enable;
76 struct pinctrl *pinctrl;
77 struct pinctrl_state *pins_uhs;
78 struct pinctrl_state *pins_default;
80 int flags; /* backup of host attribute */
81 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
84 struct sdhci_sprd_phy_cfg {
89 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
90 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
91 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
92 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
93 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
94 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
95 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
96 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
97 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
98 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
101 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
103 static void sdhci_sprd_init_config(struct sdhci_host *host)
107 /* set dll backup mode */
108 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
109 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
110 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
113 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
115 if (unlikely(reg == SDHCI_MAX_CURRENT))
116 return SDHCI_SPRD_MAX_CUR;
118 return readl_relaxed(host->ioaddr + reg);
121 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
123 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
124 if (unlikely(reg == SDHCI_MAX_CURRENT))
127 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
128 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
130 writel_relaxed(val, host->ioaddr + reg);
133 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
135 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
136 if (unlikely(reg == SDHCI_BLOCK_COUNT))
139 writew_relaxed(val, host->ioaddr + reg);
142 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
145 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
146 * standard specification, sdhci_reset() write this register directly
147 * without checking other reserved bits, that will clear BIT(3) which
148 * is defined as hardware reset on Spreadtrum's platform and clearing
149 * it by mistake will lead the card not work. So here we need to work
152 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
153 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
154 val |= SDHCI_HW_RESET_CARD;
157 writeb_relaxed(val, host->ioaddr + reg);
160 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
162 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
164 ctrl &= ~SDHCI_CLOCK_CARD_EN;
165 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
168 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
172 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
173 ctrl |= SDHCI_CLOCK_CARD_EN;
174 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
178 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
182 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
184 dll_dly_offset |= mask;
186 dll_dly_offset &= ~mask;
187 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
190 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
194 /* select 2x clock source */
195 if (base_clk <= clk * 2)
198 div = (u32) (base_clk / (clk * 2));
200 if ((base_clk / div) > (clk * 2))
203 if (div > SDHCI_SPRD_CLK_MAX_DIV)
204 div = SDHCI_SPRD_CLK_MAX_DIV;
214 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
217 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
220 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
222 clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
223 sdhci_enable_clk(host, clk);
225 /* enable auto gate sdhc_enable_auto_gate */
226 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
227 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
228 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
229 if (mask != (val & mask)) {
231 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
235 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
239 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
240 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
241 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
243 usleep_range(1000, 1250);
245 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
246 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
247 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
248 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
250 usleep_range(1000, 1250);
252 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
253 tmp |= SDHCI_SPRD_DLL_EN;
254 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
256 usleep_range(1000, 1250);
259 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
261 bool en = false, clk_changed = false;
264 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
265 } else if (clock != host->clock) {
266 sdhci_sprd_sd_clk_off(host);
267 _sdhci_sprd_set_clock(host, clock);
271 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
272 SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
275 _sdhci_sprd_set_clock(host, clock);
279 * According to the Spreadtrum SD host specification, when we changed
280 * the clock to be more than 52M, we should enable the PHY DLL which
281 * is used to track the clock frequency to make the clock work more
282 * stable. Otherwise deviation may occur of the higher clock.
284 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
285 sdhci_sprd_enable_phy_dll(host);
288 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
290 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
292 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
295 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
300 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
303 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
304 struct mmc_host *mmc = host->mmc;
305 u32 *p = sprd_host->phy_delay;
308 if (timing == host->timing)
311 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
312 /* Select Bus Speed Mode for host */
313 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
315 case MMC_TIMING_UHS_SDR12:
316 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
318 case MMC_TIMING_MMC_HS:
319 case MMC_TIMING_SD_HS:
320 case MMC_TIMING_UHS_SDR25:
321 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
323 case MMC_TIMING_UHS_SDR50:
324 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
326 case MMC_TIMING_UHS_SDR104:
327 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
329 case MMC_TIMING_UHS_DDR50:
330 case MMC_TIMING_MMC_DDR52:
331 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
333 case MMC_TIMING_MMC_HS200:
334 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
336 case MMC_TIMING_MMC_HS400:
337 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
343 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
345 if (!mmc->ios.enhanced_strobe)
346 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
349 static void sdhci_sprd_hw_reset(struct sdhci_host *host)
354 * Note: don't use sdhci_writeb() API here since it is redirected to
355 * sdhci_sprd_writeb() in which we have a workaround for
356 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
359 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
360 val &= ~SDHCI_HW_RESET_CARD;
361 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
363 usleep_range(10, 20);
365 val |= SDHCI_HW_RESET_CARD;
366 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
367 usleep_range(300, 500);
370 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
372 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
376 static struct sdhci_ops sdhci_sprd_ops = {
377 .read_l = sdhci_sprd_readl,
378 .write_l = sdhci_sprd_writel,
379 .write_b = sdhci_sprd_writeb,
380 .set_clock = sdhci_sprd_set_clock,
381 .get_max_clock = sdhci_sprd_get_max_clock,
382 .get_min_clock = sdhci_sprd_get_min_clock,
383 .set_bus_width = sdhci_set_bus_width,
384 .reset = sdhci_reset,
385 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
386 .hw_reset = sdhci_sprd_hw_reset,
387 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
390 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
392 struct sdhci_host *host = mmc_priv(mmc);
393 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
395 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
398 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
399 * block count register which doesn't support stuff bits of
400 * CMD23 argument on Spreadtrum's sd host controller.
402 if (host->version >= SDHCI_SPEC_410 &&
403 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
404 (host->flags & SDHCI_AUTO_CMD23))
405 host->flags &= ~SDHCI_AUTO_CMD23;
407 sdhci_request(mmc, mrq);
410 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
412 struct sdhci_host *host = mmc_priv(mmc);
413 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
416 if (!IS_ERR(mmc->supply.vqmmc)) {
417 ret = mmc_regulator_set_vqmmc(mmc, ios);
419 pr_err("%s: Switching signalling voltage failed\n",
425 if (IS_ERR(sprd_host->pinctrl))
428 switch (ios->signal_voltage) {
429 case MMC_SIGNAL_VOLTAGE_180:
430 ret = pinctrl_select_state(sprd_host->pinctrl,
431 sprd_host->pins_uhs);
433 pr_err("%s: failed to select uhs pin state\n",
441 case MMC_SIGNAL_VOLTAGE_330:
442 ret = pinctrl_select_state(sprd_host->pinctrl,
443 sprd_host->pins_default);
445 pr_err("%s: failed to select default pin state\n",
452 /* Wait for 300 ~ 500 us for pin state stable */
453 usleep_range(300, 500);
454 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
459 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
462 struct sdhci_host *host = mmc_priv(mmc);
463 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
464 u32 *p = sprd_host->phy_delay;
467 if (!ios->enhanced_strobe)
470 sdhci_sprd_sd_clk_off(host);
472 /* Set HS400 enhanced strobe mode */
473 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
474 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
475 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
476 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
478 sdhci_sprd_sd_clk_on(host);
480 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
481 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
482 SDHCI_SPRD_REG_32_DLL_DLY);
485 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
486 struct device_node *np)
488 u32 *p = sprd_host->phy_delay;
492 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
493 ret = of_property_read_u32_array(np,
494 sdhci_sprd_phy_cfgs[i].property, val, 4);
498 index = sdhci_sprd_phy_cfgs[i].timing;
499 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
503 static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
504 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
505 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
506 SDHCI_QUIRK2_USE_32BIT_BLK_CNT,
507 .ops = &sdhci_sprd_ops,
510 static int sdhci_sprd_probe(struct platform_device *pdev)
512 struct sdhci_host *host;
513 struct sdhci_sprd_host *sprd_host;
517 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
519 return PTR_ERR(host);
521 host->dma_mask = DMA_BIT_MASK(64);
522 pdev->dev.dma_mask = &host->dma_mask;
523 host->mmc_host_ops.request = sdhci_sprd_request;
524 host->mmc_host_ops.hs400_enhanced_strobe =
525 sdhci_sprd_hs400_enhanced_strobe;
527 * We can not use the standard ops to change and detect the voltage
528 * signal for Spreadtrum SD host controller, since our voltage regulator
529 * for I/O is fixed in hardware, that means we do not need control
530 * the standard SD host controller to change the I/O voltage.
532 host->mmc_host_ops.start_signal_voltage_switch =
533 sdhci_sprd_voltage_switch;
535 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
536 MMC_CAP_ERASE | MMC_CAP_CMD23;
537 ret = mmc_of_parse(host->mmc);
541 sprd_host = TO_SPRD_HOST(host);
542 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
544 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
545 if (!IS_ERR(sprd_host->pinctrl)) {
546 sprd_host->pins_uhs =
547 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
548 if (IS_ERR(sprd_host->pins_uhs)) {
549 ret = PTR_ERR(sprd_host->pins_uhs);
553 sprd_host->pins_default =
554 pinctrl_lookup_state(sprd_host->pinctrl, "default");
555 if (IS_ERR(sprd_host->pins_default)) {
556 ret = PTR_ERR(sprd_host->pins_default);
561 clk = devm_clk_get(&pdev->dev, "sdio");
566 sprd_host->clk_sdio = clk;
567 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
568 if (!sprd_host->base_rate)
569 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
571 clk = devm_clk_get(&pdev->dev, "enable");
576 sprd_host->clk_enable = clk;
578 clk = devm_clk_get(&pdev->dev, "2x_enable");
580 sprd_host->clk_2x_enable = clk;
582 ret = clk_prepare_enable(sprd_host->clk_sdio);
586 ret = clk_prepare_enable(sprd_host->clk_enable);
590 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
594 sdhci_sprd_init_config(host);
595 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
596 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
597 SDHCI_VENDOR_VER_SHIFT);
599 pm_runtime_get_noresume(&pdev->dev);
600 pm_runtime_set_active(&pdev->dev);
601 pm_runtime_enable(&pdev->dev);
602 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
603 pm_runtime_use_autosuspend(&pdev->dev);
604 pm_suspend_ignore_children(&pdev->dev, 1);
606 sdhci_enable_v4_mode(host);
608 ret = sdhci_setup_host(host);
610 goto pm_runtime_disable;
612 sprd_host->flags = host->flags;
614 ret = __sdhci_add_host(host);
616 goto err_cleanup_host;
618 pm_runtime_mark_last_busy(&pdev->dev);
619 pm_runtime_put_autosuspend(&pdev->dev);
624 sdhci_cleanup_host(host);
627 pm_runtime_put_noidle(&pdev->dev);
628 pm_runtime_disable(&pdev->dev);
629 pm_runtime_set_suspended(&pdev->dev);
631 clk_disable_unprepare(sprd_host->clk_2x_enable);
634 clk_disable_unprepare(sprd_host->clk_enable);
637 clk_disable_unprepare(sprd_host->clk_sdio);
640 sdhci_pltfm_free(pdev);
644 static int sdhci_sprd_remove(struct platform_device *pdev)
646 struct sdhci_host *host = platform_get_drvdata(pdev);
647 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
648 struct mmc_host *mmc = host->mmc;
650 mmc_remove_host(mmc);
651 clk_disable_unprepare(sprd_host->clk_sdio);
652 clk_disable_unprepare(sprd_host->clk_enable);
653 clk_disable_unprepare(sprd_host->clk_2x_enable);
660 static const struct of_device_id sdhci_sprd_of_match[] = {
661 { .compatible = "sprd,sdhci-r11", },
664 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
667 static int sdhci_sprd_runtime_suspend(struct device *dev)
669 struct sdhci_host *host = dev_get_drvdata(dev);
670 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
672 sdhci_runtime_suspend_host(host);
674 clk_disable_unprepare(sprd_host->clk_sdio);
675 clk_disable_unprepare(sprd_host->clk_enable);
676 clk_disable_unprepare(sprd_host->clk_2x_enable);
681 static int sdhci_sprd_runtime_resume(struct device *dev)
683 struct sdhci_host *host = dev_get_drvdata(dev);
684 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
687 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
691 ret = clk_prepare_enable(sprd_host->clk_enable);
695 ret = clk_prepare_enable(sprd_host->clk_sdio);
699 sdhci_runtime_resume_host(host);
703 clk_disable_unprepare(sprd_host->clk_enable);
706 clk_disable_unprepare(sprd_host->clk_2x_enable);
712 static const struct dev_pm_ops sdhci_sprd_pm_ops = {
713 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
714 pm_runtime_force_resume)
715 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
716 sdhci_sprd_runtime_resume, NULL)
719 static struct platform_driver sdhci_sprd_driver = {
720 .probe = sdhci_sprd_probe,
721 .remove = sdhci_sprd_remove,
723 .name = "sdhci_sprd_r11",
724 .of_match_table = of_match_ptr(sdhci_sprd_of_match),
725 .pm = &sdhci_sprd_pm_ops,
728 module_platform_driver(sdhci_sprd_driver);
730 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
731 MODULE_LICENSE("GPL v2");
732 MODULE_ALIAS("platform:sdhci-sprd-r11");