1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010 Google, Inc.
6 #include <linux/delay.h>
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/iopoll.h>
11 #include <linux/platform_device.h>
12 #include <linux/clk.h>
15 #include <linux/of_device.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19 #include <linux/mmc/card.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/slot-gpio.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/ktime.h>
26 #include "sdhci-pltfm.h"
29 /* Tegra SDHOST controller vendor register definitions */
30 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
31 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
32 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
33 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000
34 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24
35 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
36 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
37 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
39 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104
40 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31)
42 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c
43 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00
44 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8
46 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
47 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
48 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
49 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
50 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
52 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0
53 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31)
55 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc
56 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31)
58 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0
59 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000
60 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000
61 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18
62 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0
63 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6
64 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000
65 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13
68 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7
70 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4
71 #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8
72 #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC
73 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF
74 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8
75 #define TUNING_WORD_BIT_SIZE 32
77 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
78 #define SDHCI_AUTO_CAL_START BIT(31)
79 #define SDHCI_AUTO_CAL_ENABLE BIT(29)
80 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff
82 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0
83 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f
84 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7
85 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31)
86 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000
88 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec
89 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31)
91 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
92 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
93 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
94 #define NVQUIRK_ENABLE_SDR50 BIT(3)
95 #define NVQUIRK_ENABLE_SDR104 BIT(4)
96 #define NVQUIRK_ENABLE_DDR50 BIT(5)
97 #define NVQUIRK_HAS_PADCALIB BIT(6)
98 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7)
99 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8)
100 #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9)
102 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
103 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000
105 struct sdhci_tegra_soc_data {
106 const struct sdhci_pltfm_data *pdata;
112 /* Magic pull up and pull down pad calibration offsets */
113 struct sdhci_tegra_autocal_offsets {
116 u32 pull_up_3v3_timeout;
117 u32 pull_down_3v3_timeout;
120 u32 pull_up_1v8_timeout;
121 u32 pull_down_1v8_timeout;
123 u32 pull_down_sdr104;
129 const struct sdhci_tegra_soc_data *soc_data;
130 struct gpio_desc *power_gpio;
132 bool pad_calib_required;
133 bool pad_control_available;
135 struct reset_control *rst;
136 struct pinctrl *pinctrl_sdmmc;
137 struct pinctrl_state *pinctrl_state_3v3;
138 struct pinctrl_state *pinctrl_state_1v8;
139 struct pinctrl_state *pinctrl_state_3v3_drv;
140 struct pinctrl_state *pinctrl_state_1v8_drv;
142 struct sdhci_tegra_autocal_offsets autocal_offsets;
149 unsigned long curr_clk_rate;
153 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
155 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
156 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
157 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
159 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
160 (reg == SDHCI_HOST_VERSION))) {
161 /* Erratum: Version register is invalid in HW. */
162 return SDHCI_SPEC_200;
165 return readw(host->ioaddr + reg);
168 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
170 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
173 case SDHCI_TRANSFER_MODE:
175 * Postpone this write, we must do it together with a
176 * command write that is down below.
178 pltfm_host->xfer_mode_shadow = val;
181 writel((val << 16) | pltfm_host->xfer_mode_shadow,
182 host->ioaddr + SDHCI_TRANSFER_MODE);
186 writew(val, host->ioaddr + reg);
189 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
191 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
192 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
193 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
195 /* Seems like we're getting spurious timeout and crc errors, so
196 * disable signalling of them. In case of real errors software
197 * timers should take care of eventually detecting them.
199 if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
200 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
202 writel(val, host->ioaddr + reg);
204 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
205 (reg == SDHCI_INT_ENABLE))) {
206 /* Erratum: Must enable block gap interrupt detection */
207 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
208 if (val & SDHCI_INT_CARD_INT)
212 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
216 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
221 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
222 status = !!(reg & SDHCI_CLOCK_CARD_EN);
224 if (status == enable)
228 reg |= SDHCI_CLOCK_CARD_EN;
230 reg &= ~SDHCI_CLOCK_CARD_EN;
232 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
237 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
239 bool is_tuning_cmd = 0;
243 if (reg == SDHCI_COMMAND) {
244 cmd = SDHCI_GET_CMD(val);
245 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK ||
246 cmd == MMC_SEND_TUNING_BLOCK_HS200;
250 clk_enabled = tegra_sdhci_configure_card_clk(host, 0);
252 writew(val, host->ioaddr + reg);
256 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
257 tegra_sdhci_configure_card_clk(host, clk_enabled);
261 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
264 * Write-enable shall be assumed if GPIO is missing in a board's
265 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on
268 return mmc_gpio_get_ro(host->mmc);
271 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
273 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
274 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
275 int has_1v8, has_3v3;
278 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad
279 * voltage configuration in order to perform voltage switching. This
280 * means that valid pinctrl info is required on SDHCI instances capable
281 * of performing voltage switching. Whether or not an SDHCI instance is
282 * capable of voltage switching is determined based on the regulator.
285 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
288 if (IS_ERR(host->mmc->supply.vqmmc))
291 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
294 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
297 if (has_1v8 == 1 && has_3v3 == 1)
298 return tegra_host->pad_control_available;
300 /* Fixed voltage, no pad control required. */
304 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
306 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
307 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
308 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
309 bool card_clk_enabled = false;
313 * Touching the tap values is a bit tricky on some SoC generations.
314 * The quirk enables a workaround for a glitch that sometimes occurs if
315 * the tap values are changed.
318 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)
319 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
321 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
322 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
323 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
324 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
326 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&
329 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
330 tegra_sdhci_configure_card_clk(host, card_clk_enabled);
334 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
337 struct sdhci_host *host = mmc_priv(mmc);
340 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
342 if (ios->enhanced_strobe)
343 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
345 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
347 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
351 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
353 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
354 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
355 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
356 u32 misc_ctrl, clk_ctrl, pad_ctrl;
358 sdhci_reset(host, mask);
360 if (!(mask & SDHCI_RESET_ALL))
363 tegra_sdhci_set_tap(host, tegra_host->default_tap);
365 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
366 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
368 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
369 SDHCI_MISC_CTRL_ENABLE_SDR50 |
370 SDHCI_MISC_CTRL_ENABLE_DDR50 |
371 SDHCI_MISC_CTRL_ENABLE_SDR104);
373 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK |
374 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE);
376 if (tegra_sdhci_is_pad_and_regulator_valid(host)) {
377 /* Erratum: Enable SDHCI spec v3.00 support */
378 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
379 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
380 /* Advertise UHS modes as supported by host */
381 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
382 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
383 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
384 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
385 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
386 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
387 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
388 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
391 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT;
393 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
394 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
396 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {
397 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
398 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK;
399 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL;
400 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
402 tegra_host->pad_calib_required = true;
405 tegra_host->ddr_signaling = false;
408 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable)
413 * Enable or disable the additional I/O pad used by the drive strength
414 * calibration process.
416 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
419 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
421 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
423 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
429 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
434 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
435 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK;
437 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
440 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
443 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
444 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
445 struct sdhci_tegra_autocal_offsets *offsets =
446 &tegra_host->autocal_offsets;
447 struct pinctrl_state *pinctrl_drvupdn = NULL;
449 u8 drvup = 0, drvdn = 0;
452 if (!state_drvupdn) {
453 /* PADS Drive Strength */
454 if (voltage == MMC_SIGNAL_VOLTAGE_180) {
455 if (tegra_host->pinctrl_state_1v8_drv) {
457 tegra_host->pinctrl_state_1v8_drv;
459 drvup = offsets->pull_up_1v8_timeout;
460 drvdn = offsets->pull_down_1v8_timeout;
463 if (tegra_host->pinctrl_state_3v3_drv) {
465 tegra_host->pinctrl_state_3v3_drv;
467 drvup = offsets->pull_up_3v3_timeout;
468 drvdn = offsets->pull_down_3v3_timeout;
472 if (pinctrl_drvupdn != NULL) {
473 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
476 dev_err(mmc_dev(host->mmc),
477 "failed pads drvupdn, ret: %d\n", ret);
478 } else if ((drvup) || (drvdn)) {
479 reg = sdhci_readl(host,
480 SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
481 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
482 reg |= (drvup << 20) | (drvdn << 12);
483 sdhci_writel(host, reg,
484 SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
488 /* Dual Voltage PADS Voltage selection */
489 if (!tegra_host->pad_control_available)
492 if (voltage == MMC_SIGNAL_VOLTAGE_180) {
493 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
494 tegra_host->pinctrl_state_1v8);
496 dev_err(mmc_dev(host->mmc),
497 "setting 1.8V failed, ret: %d\n", ret);
499 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
500 tegra_host->pinctrl_state_3v3);
502 dev_err(mmc_dev(host->mmc),
503 "setting 3.3V failed, ret: %d\n", ret);
510 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
512 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
513 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
514 struct sdhci_tegra_autocal_offsets offsets =
515 tegra_host->autocal_offsets;
516 struct mmc_ios *ios = &host->mmc->ios;
517 bool card_clk_enabled;
522 switch (ios->timing) {
523 case MMC_TIMING_UHS_SDR104:
524 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
526 case MMC_TIMING_MMC_HS400:
527 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400;
530 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
531 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8;
533 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
536 /* Set initial offset before auto-calibration */
537 tegra_sdhci_set_pad_autocal_offset(host, pdpu);
539 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
541 tegra_sdhci_configure_cal_pad(host, true);
543 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
544 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
545 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
549 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
550 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE),
553 tegra_sdhci_configure_cal_pad(host, false);
555 tegra_sdhci_configure_card_clk(host, card_clk_enabled);
558 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
560 /* Disable automatic cal and use fixed Drive Strengths */
561 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
562 reg &= ~SDHCI_AUTO_CAL_ENABLE;
563 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
565 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
567 dev_err(mmc_dev(host->mmc),
568 "Setting drive strengths failed: %d\n", ret);
572 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
574 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
575 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
576 struct sdhci_tegra_autocal_offsets *autocal =
577 &tegra_host->autocal_offsets;
580 err = device_property_read_u32(host->mmc->parent,
581 "nvidia,pad-autocal-pull-up-offset-3v3",
582 &autocal->pull_up_3v3);
584 autocal->pull_up_3v3 = 0;
586 err = device_property_read_u32(host->mmc->parent,
587 "nvidia,pad-autocal-pull-down-offset-3v3",
588 &autocal->pull_down_3v3);
590 autocal->pull_down_3v3 = 0;
592 err = device_property_read_u32(host->mmc->parent,
593 "nvidia,pad-autocal-pull-up-offset-1v8",
594 &autocal->pull_up_1v8);
596 autocal->pull_up_1v8 = 0;
598 err = device_property_read_u32(host->mmc->parent,
599 "nvidia,pad-autocal-pull-down-offset-1v8",
600 &autocal->pull_down_1v8);
602 autocal->pull_down_1v8 = 0;
604 err = device_property_read_u32(host->mmc->parent,
605 "nvidia,pad-autocal-pull-up-offset-3v3-timeout",
606 &autocal->pull_up_3v3_timeout);
608 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
609 (tegra_host->pinctrl_state_3v3_drv == NULL))
610 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
611 mmc_hostname(host->mmc));
612 autocal->pull_up_3v3_timeout = 0;
615 err = device_property_read_u32(host->mmc->parent,
616 "nvidia,pad-autocal-pull-down-offset-3v3-timeout",
617 &autocal->pull_down_3v3_timeout);
619 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
620 (tegra_host->pinctrl_state_3v3_drv == NULL))
621 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
622 mmc_hostname(host->mmc));
623 autocal->pull_down_3v3_timeout = 0;
626 err = device_property_read_u32(host->mmc->parent,
627 "nvidia,pad-autocal-pull-up-offset-1v8-timeout",
628 &autocal->pull_up_1v8_timeout);
630 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
631 (tegra_host->pinctrl_state_1v8_drv == NULL))
632 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
633 mmc_hostname(host->mmc));
634 autocal->pull_up_1v8_timeout = 0;
637 err = device_property_read_u32(host->mmc->parent,
638 "nvidia,pad-autocal-pull-down-offset-1v8-timeout",
639 &autocal->pull_down_1v8_timeout);
641 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
642 (tegra_host->pinctrl_state_1v8_drv == NULL))
643 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
644 mmc_hostname(host->mmc));
645 autocal->pull_down_1v8_timeout = 0;
648 err = device_property_read_u32(host->mmc->parent,
649 "nvidia,pad-autocal-pull-up-offset-sdr104",
650 &autocal->pull_up_sdr104);
652 autocal->pull_up_sdr104 = autocal->pull_up_1v8;
654 err = device_property_read_u32(host->mmc->parent,
655 "nvidia,pad-autocal-pull-down-offset-sdr104",
656 &autocal->pull_down_sdr104);
658 autocal->pull_down_sdr104 = autocal->pull_down_1v8;
660 err = device_property_read_u32(host->mmc->parent,
661 "nvidia,pad-autocal-pull-up-offset-hs400",
662 &autocal->pull_up_hs400);
664 autocal->pull_up_hs400 = autocal->pull_up_1v8;
666 err = device_property_read_u32(host->mmc->parent,
667 "nvidia,pad-autocal-pull-down-offset-hs400",
668 &autocal->pull_down_hs400);
670 autocal->pull_down_hs400 = autocal->pull_down_1v8;
673 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
675 struct sdhci_host *host = mmc_priv(mmc);
676 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
677 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
678 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib);
680 /* 100 ms calibration interval is specified in the TRM */
681 if (ktime_to_ms(since_calib) > 100) {
682 tegra_sdhci_pad_autocalib(host);
683 tegra_host->last_calib = ktime_get();
686 sdhci_request(mmc, mrq);
689 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host)
691 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
692 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
695 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap",
696 &tegra_host->default_tap);
698 tegra_host->default_tap = 0;
700 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim",
701 &tegra_host->default_trim);
703 tegra_host->default_trim = 0;
705 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim",
706 &tegra_host->dqs_trim);
708 tegra_host->dqs_trim = 0x11;
711 static void tegra_sdhci_parse_dt(struct sdhci_host *host)
713 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
714 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
716 if (device_property_read_bool(host->mmc->parent, "supports-cqe"))
717 tegra_host->enable_hwcq = true;
719 tegra_host->enable_hwcq = false;
721 tegra_sdhci_parse_pad_autocal_dt(host);
722 tegra_sdhci_parse_tap_and_trim(host);
725 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
727 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
728 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
729 unsigned long host_clk;
732 return sdhci_set_clock(host, clock);
735 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI
736 * divider to be configured to divided the host clock by two. The SDHCI
737 * clock divider is calculated as part of sdhci_set_clock() by
738 * sdhci_calc_clk(). The divider is calculated from host->max_clk and
739 * the requested clock rate.
741 * By setting the host->max_clk to clock * 2 the divider calculation
742 * will always result in the correct value for DDR50/52 modes,
743 * regardless of clock rate rounding, which may happen if the value
744 * from clk_get_rate() is used.
746 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
747 clk_set_rate(pltfm_host->clk, host_clk);
748 tegra_host->curr_clk_rate = host_clk;
749 if (tegra_host->ddr_signaling)
750 host->max_clk = host_clk;
752 host->max_clk = clk_get_rate(pltfm_host->clk);
754 sdhci_set_clock(host, clock);
756 if (tegra_host->pad_calib_required) {
757 tegra_sdhci_pad_autocalib(host);
758 tegra_host->pad_calib_required = false;
762 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
764 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
766 return clk_round_rate(pltfm_host->clk, UINT_MAX);
769 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim)
773 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
774 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK;
775 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT;
776 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
779 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host)
784 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
785 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
786 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
788 /* 1 ms sleep, 5 ms timeout */
789 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA,
790 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE),
793 dev_err(mmc_dev(host->mmc),
794 "HS400 delay line calibration timed out\n");
797 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up,
798 u8 thd_low, u8 fixed_tap)
800 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
801 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
803 u8 word, bit, edge1, tap, window;
805 bool start_fail = false;
806 bool start_pass = false;
807 bool end_pass = false;
808 bool first_fail = false;
809 bool first_pass = false;
810 u8 start_pass_tap = 0;
812 u8 first_fail_tap = 0;
813 u8 first_pass_tap = 0;
814 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE;
817 * Read auto-tuned results and extract good valid passing window by
818 * filtering out un-wanted bubble/partial/merged windows.
820 for (word = 0; word < total_tuning_words; word++) {
821 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
822 val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK;
824 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
825 tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0);
827 while (bit < TUNING_WORD_BIT_SIZE) {
828 tap = word * TUNING_WORD_BIT_SIZE + bit;
829 tap_result = tun_status & (1 << bit);
830 if (!tap_result && !start_fail) {
833 first_fail_tap = tap;
837 } else if (tap_result && start_fail && !start_pass) {
838 start_pass_tap = tap;
841 first_pass_tap = tap;
845 } else if (!tap_result && start_fail && start_pass &&
847 end_pass_tap = tap - 1;
849 } else if (tap_result && start_pass && start_fail &&
851 window = end_pass_tap - start_pass_tap;
852 /* discard merged window and bubble window */
853 if (window >= thd_up || window < thd_low) {
854 start_pass_tap = tap;
857 /* set tap at middle of valid window */
858 tap = start_pass_tap + window / 2;
859 tegra_host->tuned_tap_delay = tap;
869 WARN(1, "no edge detected, continue with hw tuned delay.\n");
870 } else if (first_pass) {
871 /* set tap location at fixed tap relative to the first edge */
872 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2;
873 if (edge1 - 1 > fixed_tap)
874 tegra_host->tuned_tap_delay = edge1 - fixed_tap;
876 tegra_host->tuned_tap_delay = edge1 + fixed_tap;
880 static void tegra_sdhci_post_tuning(struct sdhci_host *host)
882 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
883 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
884 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
885 u32 avg_tap_dly, val, min_tap_dly, max_tap_dly;
886 u8 fixed_tap, start_tap, end_tap, window_width;
887 u8 thdupper, thdlower;
889 u32 clk_rate_mhz, period_ps, bestcase, worstcase;
891 /* retain HW tuned tap to use incase if no correction is needed */
892 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
893 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >>
894 SDHCI_CLOCK_CTRL_TAP_SHIFT;
895 if (soc_data->min_tap_delay && soc_data->max_tap_delay) {
896 min_tap_dly = soc_data->min_tap_delay;
897 max_tap_dly = soc_data->max_tap_delay;
898 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC;
899 period_ps = USEC_PER_SEC / clk_rate_mhz;
900 bestcase = period_ps / min_tap_dly;
901 worstcase = period_ps / max_tap_dly;
903 * Upper and Lower bound thresholds used to detect merged and
906 thdupper = (2 * worstcase + bestcase) / 2;
907 thdlower = worstcase / 4;
909 * fixed tap is used when HW tuning result contains single edge
910 * and tap is set at fixed tap delay relative to the first edge
912 avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly);
913 fixed_tap = avg_tap_dly / 2;
915 val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1);
916 start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
917 end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) &
918 SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
919 window_width = end_tap - start_tap;
920 num_iter = host->tuning_loop_count;
922 * partial window includes edges of the tuning range.
923 * merged window includes more taps so window width is higher
924 * than upper threshold.
926 if (start_tap == 0 || (end_tap == (num_iter - 1)) ||
927 (end_tap == num_iter - 2) || window_width >= thdupper) {
928 pr_debug("%s: Apply tuning correction\n",
929 mmc_hostname(host->mmc));
930 tegra_sdhci_tap_correction(host, thdupper, thdlower,
935 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
938 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode)
940 struct sdhci_host *host = mmc_priv(mmc);
943 err = sdhci_execute_tuning(mmc, opcode);
944 if (!err && !host->tuning_err)
945 tegra_sdhci_post_tuning(host);
950 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
953 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
954 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
955 bool set_default_tap = false;
956 bool set_dqs_trim = false;
957 bool do_hs400_dll_cal = false;
961 tegra_host->ddr_signaling = false;
963 case MMC_TIMING_UHS_SDR50:
965 case MMC_TIMING_UHS_SDR104:
966 case MMC_TIMING_MMC_HS200:
967 /* Don't set default tap on tunable modes. */
970 case MMC_TIMING_MMC_HS400:
972 do_hs400_dll_cal = true;
975 case MMC_TIMING_MMC_DDR52:
976 case MMC_TIMING_UHS_DDR50:
977 tegra_host->ddr_signaling = true;
978 set_default_tap = true;
981 set_default_tap = true;
985 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
986 val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK |
987 SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK |
988 SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK);
989 val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT |
990 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT |
991 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT);
992 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
993 sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0);
995 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256;
997 sdhci_set_uhs_signaling(host, timing);
999 tegra_sdhci_pad_autocalib(host);
1001 if (tegra_host->tuned_tap_delay && !set_default_tap)
1002 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
1004 tegra_sdhci_set_tap(host, tegra_host->default_tap);
1007 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
1009 if (do_hs400_dll_cal)
1010 tegra_sdhci_hs400_dll_cal(host);
1013 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
1015 unsigned int min, max;
1018 * Start search for minimum tap value at 10, as smaller values are
1019 * may wrongly be reported as working but fail at higher speeds,
1020 * according to the TRM.
1024 tegra_sdhci_set_tap(host, min);
1025 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1030 /* Find the maximum tap value that still passes. */
1033 tegra_sdhci_set_tap(host, max);
1034 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1041 /* The TRM states the ideal tap value is at 75% in the passing range. */
1042 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
1044 return mmc_send_tuning(host->mmc, opcode, NULL);
1047 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
1048 struct mmc_ios *ios)
1050 struct sdhci_host *host = mmc_priv(mmc);
1051 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1052 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1055 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1056 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1059 ret = sdhci_start_signal_voltage_switch(mmc, ios);
1060 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1061 ret = sdhci_start_signal_voltage_switch(mmc, ios);
1064 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1067 if (tegra_host->pad_calib_required)
1068 tegra_sdhci_pad_autocalib(host);
1073 static int tegra_sdhci_init_pinctrl_info(struct device *dev,
1074 struct sdhci_tegra *tegra_host)
1076 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
1077 if (IS_ERR(tegra_host->pinctrl_sdmmc)) {
1078 dev_dbg(dev, "No pinctrl info, err: %ld\n",
1079 PTR_ERR(tegra_host->pinctrl_sdmmc));
1083 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
1084 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
1085 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) {
1086 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV)
1087 tegra_host->pinctrl_state_1v8_drv = NULL;
1090 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
1091 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
1092 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) {
1093 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV)
1094 tegra_host->pinctrl_state_3v3_drv = NULL;
1097 tegra_host->pinctrl_state_3v3 =
1098 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
1099 if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
1100 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n",
1101 PTR_ERR(tegra_host->pinctrl_state_3v3));
1105 tegra_host->pinctrl_state_1v8 =
1106 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8");
1107 if (IS_ERR(tegra_host->pinctrl_state_1v8)) {
1108 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n",
1109 PTR_ERR(tegra_host->pinctrl_state_1v8));
1113 tegra_host->pad_control_available = true;
1118 static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
1120 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1121 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1122 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1124 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1125 tegra_host->pad_calib_required = true;
1128 static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg)
1130 struct mmc_host *mmc = cq_host->mmc;
1136 * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to
1137 * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need
1138 * to be re-configured.
1139 * Tegra CQHCI/SDHCI prevents write access to block size register when
1140 * CQE is unhalted. So handling CQE resume sequence here to configure
1141 * SDHCI block registers prior to exiting CQE halt state.
1143 if (reg == CQHCI_CTL && !(val & CQHCI_HALT) &&
1144 cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) {
1145 sdhci_cqe_enable(mmc);
1146 writel(val, cq_host->mmio + reg);
1147 timeout = ktime_add_us(ktime_get(), 50);
1149 timed_out = ktime_compare(ktime_get(), timeout) > 0;
1150 ctrl = cqhci_readl(cq_host, CQHCI_CTL);
1151 if (!(ctrl & CQHCI_HALT) || timed_out)
1155 * CQE usually resumes very quick, but incase if Tegra CQE
1156 * doesn't resume retry unhalt.
1159 writel(val, cq_host->mmio + reg);
1161 writel(val, cq_host->mmio + reg);
1165 static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc,
1166 struct mmc_request *mrq, u64 *data)
1168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc));
1169 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1170 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1172 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING &&
1173 mrq->cmd->flags & MMC_RSP_R1B)
1174 *data |= CQHCI_CMD_TIMING(1);
1177 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc)
1179 struct cqhci_host *cq_host = mmc->cqe_private;
1183 * Tegra CQHCI/SDMMC design prevents write access to sdhci block size
1184 * register when CQE is enabled and unhalted.
1185 * CQHCI driver enables CQE prior to activation, so disable CQE before
1186 * programming block size in sdhci controller and enable it back.
1188 if (!cq_host->activated) {
1189 val = cqhci_readl(cq_host, CQHCI_CFG);
1190 if (val & CQHCI_ENABLE)
1191 cqhci_writel(cq_host, (val & ~CQHCI_ENABLE),
1193 sdhci_cqe_enable(mmc);
1194 if (val & CQHCI_ENABLE)
1195 cqhci_writel(cq_host, val, CQHCI_CFG);
1199 * CMD CRC errors are seen sometimes with some eMMC devices when status
1200 * command is sent during transfer of last data block which is the
1201 * default case as send status command block counter (CBC) is 1.
1202 * Recommended fix to set CBC to 0 allowing send status command only
1203 * when data lines are idle.
1205 val = cqhci_readl(cq_host, CQHCI_SSC1);
1206 val &= ~CQHCI_SSC1_CBC_MASK;
1207 cqhci_writel(cq_host, val, CQHCI_SSC1);
1210 static void sdhci_tegra_dumpregs(struct mmc_host *mmc)
1212 sdhci_dumpregs(mmc_priv(mmc));
1215 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask)
1220 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1223 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1228 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = {
1229 .write_l = tegra_cqhci_writel,
1230 .enable = sdhci_tegra_cqe_enable,
1231 .disable = sdhci_cqe_disable,
1232 .dumpregs = sdhci_tegra_dumpregs,
1233 .update_dcmd_desc = sdhci_tegra_update_dcmd_desc,
1236 static const struct sdhci_ops tegra_sdhci_ops = {
1237 .get_ro = tegra_sdhci_get_ro,
1238 .read_w = tegra_sdhci_readw,
1239 .write_l = tegra_sdhci_writel,
1240 .set_clock = tegra_sdhci_set_clock,
1241 .set_bus_width = sdhci_set_bus_width,
1242 .reset = tegra_sdhci_reset,
1243 .platform_execute_tuning = tegra_sdhci_execute_tuning,
1244 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1245 .voltage_switch = tegra_sdhci_voltage_switch,
1246 .get_max_clock = tegra_sdhci_get_max_clock,
1249 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
1250 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1251 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1252 SDHCI_QUIRK_NO_HISPD_BIT |
1253 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1254 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1255 .ops = &tegra_sdhci_ops,
1258 static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
1259 .pdata = &sdhci_tegra20_pdata,
1260 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1261 NVQUIRK_ENABLE_BLOCK_GAP_DET,
1264 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
1265 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1266 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1267 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1268 SDHCI_QUIRK_NO_HISPD_BIT |
1269 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1270 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1271 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1272 SDHCI_QUIRK2_BROKEN_HS200 |
1274 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1275 * though no command operation was in progress."
1277 * The exact reason is unknown, as the same hardware seems
1278 * to support Auto CMD23 on a downstream 3.1 kernel.
1280 SDHCI_QUIRK2_ACMD23_BROKEN,
1281 .ops = &tegra_sdhci_ops,
1284 static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
1285 .pdata = &sdhci_tegra30_pdata,
1286 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
1287 NVQUIRK_ENABLE_SDR50 |
1288 NVQUIRK_ENABLE_SDR104 |
1289 NVQUIRK_HAS_PADCALIB,
1292 static const struct sdhci_ops tegra114_sdhci_ops = {
1293 .get_ro = tegra_sdhci_get_ro,
1294 .read_w = tegra_sdhci_readw,
1295 .write_w = tegra_sdhci_writew,
1296 .write_l = tegra_sdhci_writel,
1297 .set_clock = tegra_sdhci_set_clock,
1298 .set_bus_width = sdhci_set_bus_width,
1299 .reset = tegra_sdhci_reset,
1300 .platform_execute_tuning = tegra_sdhci_execute_tuning,
1301 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1302 .voltage_switch = tegra_sdhci_voltage_switch,
1303 .get_max_clock = tegra_sdhci_get_max_clock,
1306 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
1307 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1308 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1309 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1310 SDHCI_QUIRK_NO_HISPD_BIT |
1311 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1312 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1313 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1314 .ops = &tegra114_sdhci_ops,
1317 static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
1318 .pdata = &sdhci_tegra114_pdata,
1321 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
1322 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1323 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1324 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1325 SDHCI_QUIRK_NO_HISPD_BIT |
1326 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1327 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1328 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1330 * The TRM states that the SD/MMC controller found on
1331 * Tegra124 can address 34 bits (the maximum supported by
1332 * the Tegra memory controller), but tests show that DMA
1333 * to or from above 4 GiB doesn't work. This is possibly
1334 * caused by missing programming, though it's not obvious
1335 * what sequence is required. Mark 64-bit DMA broken for
1336 * now to fix this for existing users (e.g. Nyan boards).
1338 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1339 .ops = &tegra114_sdhci_ops,
1342 static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
1343 .pdata = &sdhci_tegra124_pdata,
1346 static const struct sdhci_ops tegra210_sdhci_ops = {
1347 .get_ro = tegra_sdhci_get_ro,
1348 .read_w = tegra_sdhci_readw,
1349 .write_w = tegra210_sdhci_writew,
1350 .write_l = tegra_sdhci_writel,
1351 .set_clock = tegra_sdhci_set_clock,
1352 .set_bus_width = sdhci_set_bus_width,
1353 .reset = tegra_sdhci_reset,
1354 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1355 .voltage_switch = tegra_sdhci_voltage_switch,
1356 .get_max_clock = tegra_sdhci_get_max_clock,
1359 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
1360 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1361 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1362 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1363 SDHCI_QUIRK_NO_HISPD_BIT |
1364 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1365 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1366 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1367 .ops = &tegra210_sdhci_ops,
1370 static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
1371 .pdata = &sdhci_tegra210_pdata,
1372 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1373 NVQUIRK_HAS_PADCALIB |
1374 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1375 NVQUIRK_ENABLE_SDR50 |
1376 NVQUIRK_ENABLE_SDR104,
1377 .min_tap_delay = 106,
1378 .max_tap_delay = 185,
1381 static const struct sdhci_ops tegra186_sdhci_ops = {
1382 .get_ro = tegra_sdhci_get_ro,
1383 .read_w = tegra_sdhci_readw,
1384 .write_l = tegra_sdhci_writel,
1385 .set_clock = tegra_sdhci_set_clock,
1386 .set_bus_width = sdhci_set_bus_width,
1387 .reset = tegra_sdhci_reset,
1388 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1389 .voltage_switch = tegra_sdhci_voltage_switch,
1390 .get_max_clock = tegra_sdhci_get_max_clock,
1391 .irq = sdhci_tegra_cqhci_irq,
1394 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
1395 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1396 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1397 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1398 SDHCI_QUIRK_NO_HISPD_BIT |
1399 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1400 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1401 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1402 /* SDHCI controllers on Tegra186 support 40-bit addressing.
1403 * IOVA addresses are 48-bit wide on Tegra186.
1404 * With 64-bit dma mask used for SDHCI, accesses can
1405 * be broken. Disable 64-bit dma, which would fall back
1406 * to 32-bit dma mask. Ideally 40-bit dma mask would work,
1407 * But it is not supported as of now.
1409 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1410 .ops = &tegra186_sdhci_ops,
1413 static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
1414 .pdata = &sdhci_tegra186_pdata,
1415 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1416 NVQUIRK_HAS_PADCALIB |
1417 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1418 NVQUIRK_ENABLE_SDR50 |
1419 NVQUIRK_ENABLE_SDR104 |
1420 NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING,
1421 .min_tap_delay = 84,
1422 .max_tap_delay = 136,
1425 static const struct sdhci_tegra_soc_data soc_data_tegra194 = {
1426 .pdata = &sdhci_tegra186_pdata,
1427 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1428 NVQUIRK_HAS_PADCALIB |
1429 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1430 NVQUIRK_ENABLE_SDR50 |
1431 NVQUIRK_ENABLE_SDR104,
1432 .min_tap_delay = 96,
1433 .max_tap_delay = 139,
1436 static const struct of_device_id sdhci_tegra_dt_match[] = {
1437 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1438 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1439 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1440 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1441 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1442 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1443 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1446 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
1448 static int sdhci_tegra_add_host(struct sdhci_host *host)
1450 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1451 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1452 struct cqhci_host *cq_host;
1456 if (!tegra_host->enable_hwcq)
1457 return sdhci_add_host(host);
1459 sdhci_enable_v4_mode(host);
1461 ret = sdhci_setup_host(host);
1465 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1467 cq_host = devm_kzalloc(host->mmc->parent,
1468 sizeof(*cq_host), GFP_KERNEL);
1474 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR;
1475 cq_host->ops = &sdhci_tegra_cqhci_ops;
1477 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1479 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1481 ret = cqhci_init(cq_host, host->mmc, dma64);
1485 ret = __sdhci_add_host(host);
1492 sdhci_cleanup_host(host);
1496 static int sdhci_tegra_probe(struct platform_device *pdev)
1498 const struct of_device_id *match;
1499 const struct sdhci_tegra_soc_data *soc_data;
1500 struct sdhci_host *host;
1501 struct sdhci_pltfm_host *pltfm_host;
1502 struct sdhci_tegra *tegra_host;
1506 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
1509 soc_data = match->data;
1511 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
1513 return PTR_ERR(host);
1514 pltfm_host = sdhci_priv(host);
1516 tegra_host = sdhci_pltfm_priv(pltfm_host);
1517 tegra_host->ddr_signaling = false;
1518 tegra_host->pad_calib_required = false;
1519 tegra_host->pad_control_available = false;
1520 tegra_host->soc_data = soc_data;
1522 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
1523 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
1525 host->mmc_host_ops.start_signal_voltage_switch =
1526 sdhci_tegra_start_signal_voltage_switch;
1529 /* Hook to periodically rerun pad calibration */
1530 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1531 host->mmc_host_ops.request = tegra_sdhci_request;
1533 host->mmc_host_ops.hs400_enhanced_strobe =
1534 tegra_sdhci_hs400_enhanced_strobe;
1536 if (!host->ops->platform_execute_tuning)
1537 host->mmc_host_ops.execute_tuning =
1538 tegra_sdhci_execute_hw_tuning;
1540 rc = mmc_of_parse(host->mmc);
1544 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
1545 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1547 tegra_sdhci_parse_dt(host);
1549 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
1551 if (IS_ERR(tegra_host->power_gpio)) {
1552 rc = PTR_ERR(tegra_host->power_gpio);
1556 clk = devm_clk_get(mmc_dev(host->mmc), NULL);
1560 if (rc != -EPROBE_DEFER)
1561 dev_err(&pdev->dev, "failed to get clock: %d\n", rc);
1565 clk_prepare_enable(clk);
1566 pltfm_host->clk = clk;
1568 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
1570 if (IS_ERR(tegra_host->rst)) {
1571 rc = PTR_ERR(tegra_host->rst);
1572 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
1576 rc = reset_control_assert(tegra_host->rst);
1580 usleep_range(2000, 4000);
1582 rc = reset_control_deassert(tegra_host->rst);
1586 usleep_range(2000, 4000);
1588 rc = sdhci_tegra_add_host(host);
1595 reset_control_assert(tegra_host->rst);
1597 clk_disable_unprepare(pltfm_host->clk);
1601 sdhci_pltfm_free(pdev);
1605 static int sdhci_tegra_remove(struct platform_device *pdev)
1607 struct sdhci_host *host = platform_get_drvdata(pdev);
1608 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1609 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1611 sdhci_remove_host(host, 0);
1613 reset_control_assert(tegra_host->rst);
1614 usleep_range(2000, 4000);
1615 clk_disable_unprepare(pltfm_host->clk);
1617 sdhci_pltfm_free(pdev);
1622 #ifdef CONFIG_PM_SLEEP
1623 static int __maybe_unused sdhci_tegra_suspend(struct device *dev)
1625 struct sdhci_host *host = dev_get_drvdata(dev);
1626 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1629 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1630 ret = cqhci_suspend(host->mmc);
1635 ret = sdhci_suspend_host(host);
1637 cqhci_resume(host->mmc);
1641 clk_disable_unprepare(pltfm_host->clk);
1645 static int __maybe_unused sdhci_tegra_resume(struct device *dev)
1647 struct sdhci_host *host = dev_get_drvdata(dev);
1648 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1651 ret = clk_prepare_enable(pltfm_host->clk);
1655 ret = sdhci_resume_host(host);
1659 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1660 ret = cqhci_resume(host->mmc);
1668 sdhci_suspend_host(host);
1670 clk_disable_unprepare(pltfm_host->clk);
1675 static SIMPLE_DEV_PM_OPS(sdhci_tegra_dev_pm_ops, sdhci_tegra_suspend,
1676 sdhci_tegra_resume);
1678 static struct platform_driver sdhci_tegra_driver = {
1680 .name = "sdhci-tegra",
1681 .of_match_table = sdhci_tegra_dt_match,
1682 .pm = &sdhci_tegra_dev_pm_ops,
1684 .probe = sdhci_tegra_probe,
1685 .remove = sdhci_tegra_remove,
1688 module_platform_driver(sdhci_tegra_driver);
1690 MODULE_DESCRIPTION("SDHCI driver for Tegra");
1691 MODULE_AUTHOR("Google, Inc.");
1692 MODULE_LICENSE("GPL v2");