drivers/mmc/host/sdhci_am654.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/module.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/property.h>
  12 #include <linux/regmap.h>
  13
  14 #include "sdhci-pltfm.h"
  15
  16 /* CTL_CFG Registers */
  17 #define CTL_CFG_2               0x14
  18
  19 #define SLOTTYPE_MASK           GENMASK(31, 30)
  20 #define SLOTTYPE_EMBEDDED       BIT(30)
  21
  22 /* PHY Registers */
  23 #define PHY_CTRL1       0x100
  24 #define PHY_CTRL2       0x104
  25 #define PHY_CTRL3       0x108
  26 #define PHY_CTRL4       0x10C
  27 #define PHY_CTRL5       0x110
  28 #define PHY_CTRL6       0x114
  29 #define PHY_STAT1       0x130
  30 #define PHY_STAT2       0x134
  31
  32 #define IOMUX_ENABLE_SHIFT      31
  33 #define IOMUX_ENABLE_MASK       BIT(IOMUX_ENABLE_SHIFT)
  34 #define OTAPDLYENA_SHIFT        20
  35 #define OTAPDLYENA_MASK         BIT(OTAPDLYENA_SHIFT)
  36 #define OTAPDLYSEL_SHIFT        12
  37 #define OTAPDLYSEL_MASK         GENMASK(15, 12)
  38 #define STRBSEL_SHIFT           24
  39 #define STRBSEL_MASK            GENMASK(27, 24)
  40 #define SEL50_SHIFT             8
  41 #define SEL50_MASK              BIT(SEL50_SHIFT)
  42 #define SEL100_SHIFT            9
  43 #define SEL100_MASK             BIT(SEL100_SHIFT)
  44 #define DLL_TRIM_ICP_SHIFT      4
  45 #define DLL_TRIM_ICP_MASK       GENMASK(7, 4)
  46 #define DR_TY_SHIFT             20
  47 #define DR_TY_MASK              GENMASK(22, 20)
  48 #define ENDLL_SHIFT             1
  49 #define ENDLL_MASK              BIT(ENDLL_SHIFT)
  50 #define DLLRDY_SHIFT            0
  51 #define DLLRDY_MASK             BIT(DLLRDY_SHIFT)
  52 #define PDB_SHIFT               0
  53 #define PDB_MASK                BIT(PDB_SHIFT)
  54 #define CALDONE_SHIFT           1
  55 #define CALDONE_MASK            BIT(CALDONE_SHIFT)
  56 #define RETRIM_SHIFT            17
  57 #define RETRIM_MASK             BIT(RETRIM_SHIFT)
  58
  59 #define DRIVER_STRENGTH_50_OHM  0x0
  60 #define DRIVER_STRENGTH_33_OHM  0x1
  61 #define DRIVER_STRENGTH_66_OHM  0x2
  62 #define DRIVER_STRENGTH_100_OHM 0x3
  63 #define DRIVER_STRENGTH_40_OHM  0x4
  64
  65 #define CLOCK_TOO_SLOW_HZ       400000
  66
  67 static struct regmap_config sdhci_am654_regmap_config = {
  68         .reg_bits = 32,
  69         .val_bits = 32,
  70         .reg_stride = 4,
  71         .fast_io = true,
  72 };
  73
  74 struct sdhci_am654_data {
  75         struct regmap *base;
  76         int otap_del_sel;
  77         int trm_icp;
  78         int drv_strength;
  79         bool dll_on;
  80 };
  81
  82 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
  83 {
  84         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  85         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
  86         int sel50, sel100;
  87         u32 mask, val;
  88         int ret;
  89
  90         if (sdhci_am654->dll_on) {
  91                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
  92                                    ENDLL_MASK, 0);
  93
  94                 sdhci_am654->dll_on = false;
  95         }
  96
  97         sdhci_set_clock(host, clock);
  98
  99         if (clock > CLOCK_TOO_SLOW_HZ) {
 100                 /* Setup DLL Output TAP delay */
 101                 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 102                 val = (1 << OTAPDLYENA_SHIFT) |
 103                       (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
 104                 regmap_update_bits(sdhci_am654->base, PHY_CTRL4,
 105                                    mask, val);
 106                 switch (clock) {
 107                 case 200000000:
 108                         sel50 = 0;
 109                         sel100 = 0;
 110                         break;
 111                 case 100000000:
 112                         sel50 = 0;
 113                         sel100 = 1;
 114                         break;
 115                 default:
 116                         sel50 = 1;
 117                         sel100 = 0;
 118                 }
 119
 120                 /* Configure PHY DLL frequency */
 121                 mask = SEL50_MASK | SEL100_MASK;
 122                 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
 123                 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
 124                                    mask, val);
 125                 /* Configure DLL TRIM */
 126                 mask = DLL_TRIM_ICP_MASK;
 127                 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
 128
 129                 /* Configure DLL driver strength */
 130                 mask |= DR_TY_MASK;
 131                 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
 132                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 133                                    mask, val);
 134                 /* Enable DLL */
 135                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 136                                    ENDLL_MASK, 0x1 << ENDLL_SHIFT);
 137                 /*
 138                  * Poll for DLL ready. Use a one second timeout.
 139                  * Works in all experiments done so far
 140                  */
 141                 ret = regmap_read_poll_timeout(sdhci_am654->base,
 142                                          PHY_STAT1, val,
 143                                          val & DLLRDY_MASK,
 144                                          1000, 1000000);
 145
 146                 sdhci_am654->dll_on = true;
 147         }
 148 }
 149
 150 static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode,
 151                                   unsigned short vdd)
 152 {
 153         if (!IS_ERR(host->mmc->supply.vmmc)) {
 154                 struct mmc_host *mmc = host->mmc;
 155
 156                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 157         }
 158         sdhci_set_power_noreg(host, mode, vdd);
 159 }
 160
 161 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
 162 {
 163         unsigned char timing = host->mmc->ios.timing;
 164
 165         if (reg == SDHCI_HOST_CONTROL) {
 166                 switch (timing) {
 167                 /*
 168                  * According to the data manual, HISPD bit
 169                  * should not be set in these speed modes.
 170                  */
 171                 case MMC_TIMING_SD_HS:
 172                 case MMC_TIMING_MMC_HS:
 173                 case MMC_TIMING_UHS_SDR12:
 174                 case MMC_TIMING_UHS_SDR25:
 175                         val &= ~SDHCI_CTRL_HISPD;
 176                 }
 177         }
 178
 179         writeb(val, host->ioaddr + reg);
 180 }
 181
 182 static struct sdhci_ops sdhci_am654_ops = {
 183         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 184         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 185         .set_uhs_signaling = sdhci_set_uhs_signaling,
 186         .set_bus_width = sdhci_set_bus_width,
 187         .set_power = sdhci_am654_set_power,
 188         .set_clock = sdhci_am654_set_clock,
 189         .write_b = sdhci_am654_write_b,
 190         .reset = sdhci_reset,
 191 };
 192
 193 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
 194         .ops = &sdhci_am654_ops,
 195         .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
 196                   SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 197         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 198 };
 199
 200 static int sdhci_am654_init(struct sdhci_host *host)
 201 {
 202         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 203         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 204         u32 ctl_cfg_2 = 0;
 205         u32 mask;
 206         u32 val;
 207         int ret;
 208
 209         /* Reset OTAP to default value */
 210         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 211         regmap_update_bits(sdhci_am654->base, PHY_CTRL4,
 212                                    mask, 0x0);
 213
 214         regmap_read(sdhci_am654->base, PHY_STAT1, &val);
 215         if (~val & CALDONE_MASK) {
 216                 /* Calibrate IO lines */
 217                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 218                                    PDB_MASK, PDB_MASK);
 219                 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1,
 220                                                val, val & CALDONE_MASK, 1, 20);
 221                 if (ret)
 222                         return ret;
 223         }
 224
 225         /* Enable pins by setting IO mux to 0 */
 226         regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 227                            IOMUX_ENABLE_MASK, 0);
 228
 229         /* Set slot type based on SD or eMMC */
 230         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
 231                 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
 232
 233         regmap_update_bits(sdhci_am654->base, CTL_CFG_2,
 234                            SLOTTYPE_MASK, ctl_cfg_2);
 235
 236         return sdhci_add_host(host);
 237 }
 238
 239 static int sdhci_am654_get_of_property(struct platform_device *pdev,
 240                                         struct sdhci_am654_data *sdhci_am654)
 241 {
 242         struct device *dev = &pdev->dev;
 243         int drv_strength;
 244         int ret;
 245
 246         ret = device_property_read_u32(dev, "ti,trm-icp",
 247                                        &sdhci_am654->trm_icp);
 248         if (ret)
 249                 return ret;
 250
 251         ret = device_property_read_u32(dev, "ti,otap-del-sel",
 252                                        &sdhci_am654->otap_del_sel);
 253         if (ret)
 254                 return ret;
 255
 256         ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
 257                                        &drv_strength);
 258         if (ret)
 259                 return ret;
 260
 261         switch (drv_strength) {
 262         case 50:
 263                 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
 264                 break;
 265         case 33:
 266                 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
 267                 break;
 268         case 66:
 269                 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
 270                 break;
 271         case 100:
 272                 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
 273                 break;
 274         case 40:
 275                 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
 276                 break;
 277         default:
 278                 dev_err(dev, "Invalid driver strength\n");
 279                 return -EINVAL;
 280         }
 281
 282         sdhci_get_of_property(pdev);
 283
 284         return 0;
 285 }
 286
 287 static int sdhci_am654_probe(struct platform_device *pdev)
 288 {
 289         struct sdhci_pltfm_host *pltfm_host;
 290         struct sdhci_am654_data *sdhci_am654;
 291         struct sdhci_host *host;
 292         struct resource *res;
 293         struct clk *clk_xin;
 294         struct device *dev = &pdev->dev;
 295         void __iomem *base;
 296         int ret;
 297
 298         host = sdhci_pltfm_init(pdev, &sdhci_am654_pdata, sizeof(*sdhci_am654));
 299         if (IS_ERR(host))
 300                 return PTR_ERR(host);
 301
 302         pltfm_host = sdhci_priv(host);
 303         sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 304
 305         clk_xin = devm_clk_get(dev, "clk_xin");
 306         if (IS_ERR(clk_xin)) {
 307                 dev_err(dev, "clk_xin clock not found.\n");
 308                 ret = PTR_ERR(clk_xin);
 309                 goto err_pltfm_free;
 310         }
 311
 312         pltfm_host->clk = clk_xin;
 313
 314         /* Clocks are enabled using pm_runtime */
 315         pm_runtime_enable(dev);
 316         ret = pm_runtime_get_sync(dev);
 317         if (ret < 0) {
 318                 pm_runtime_put_noidle(dev);
 319                 goto pm_runtime_disable;
 320         }
 321
 322         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 323         base = devm_ioremap_resource(dev, res);
 324         if (IS_ERR(base)) {
 325                 ret = PTR_ERR(base);
 326                 goto pm_runtime_put;
 327         }
 328
 329         sdhci_am654->base = devm_regmap_init_mmio(dev, base,
 330                                                   &sdhci_am654_regmap_config);
 331         if (IS_ERR(sdhci_am654->base)) {
 332                 dev_err(dev, "Failed to initialize regmap\n");
 333                 ret = PTR_ERR(sdhci_am654->base);
 334                 goto pm_runtime_put;
 335         }
 336
 337         ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
 338         if (ret)
 339                 goto pm_runtime_put;
 340
 341         ret = mmc_of_parse(host->mmc);
 342         if (ret) {
 343                 dev_err(dev, "parsing dt failed (%d)\n", ret);
 344                 goto pm_runtime_put;
 345         }
 346
 347         ret = sdhci_am654_init(host);
 348         if (ret)
 349                 goto pm_runtime_put;
 350
 351         return 0;
 352
 353 pm_runtime_put:
 354         pm_runtime_put_sync(dev);
 355 pm_runtime_disable:
 356         pm_runtime_disable(dev);
 357 err_pltfm_free:
 358         sdhci_pltfm_free(pdev);
 359         return ret;
 360 }
 361
 362 static int sdhci_am654_remove(struct platform_device *pdev)
 363 {
 364         struct sdhci_host *host = platform_get_drvdata(pdev);
 365         int ret;
 366
 367         sdhci_remove_host(host, true);
 368         ret = pm_runtime_put_sync(&pdev->dev);
 369         if (ret < 0)
 370                 return ret;
 371
 372         pm_runtime_disable(&pdev->dev);
 373         sdhci_pltfm_free(pdev);
 374
 375         return 0;
 376 }
 377
 378 static const struct of_device_id sdhci_am654_of_match[] = {
 379         { .compatible = "ti,am654-sdhci-5.1" },
 380         { /* sentinel */ }
 381 };
 382
 383 static struct platform_driver sdhci_am654_driver = {
 384         .driver = {
 385                 .name = "sdhci-am654",
 386                 .of_match_table = sdhci_am654_of_match,
 387         },
 388         .probe = sdhci_am654_probe,
 389         .remove = sdhci_am654_remove,
 390 };
 391
 392 module_platform_driver(sdhci_am654_driver);
 393
 394 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
 395 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
 396 MODULE_LICENSE("GPL");