2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
28 #include <asm/byteorder.h>
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
53 * Status Register bit description. Used by flash devices that don't
54 * support DQ polling (e.g. HyperFlash)
56 #define CFI_SR_DRB BIT(7)
57 #define CFI_SR_ESB BIT(5)
58 #define CFI_SR_PSB BIT(4)
59 #define CFI_SR_WBASB BIT(3)
60 #define CFI_SR_SLSB BIT(1)
62 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
63 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
65 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
67 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
68 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
69 static void cfi_amdstd_sync (struct mtd_info *);
70 static int cfi_amdstd_suspend (struct mtd_info *);
71 static void cfi_amdstd_resume (struct mtd_info *);
72 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
73 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
74 size_t *, struct otp_info *);
75 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
76 size_t *, struct otp_info *);
77 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
78 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
80 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
82 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
84 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
86 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
87 size_t *retlen, const u_char *buf);
89 static void cfi_amdstd_destroy(struct mtd_info *);
91 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
92 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
94 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
95 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
98 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
99 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
101 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
102 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
103 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
105 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
106 .probe = NULL, /* Not usable directly */
107 .destroy = cfi_amdstd_destroy,
108 .name = "cfi_cmdset_0002",
109 .module = THIS_MODULE
113 * Use status register to poll for Erase/write completion when DQ is not
114 * supported. This is indicated by Bit[1:0] of SoftwareFeatures field in
115 * CFI Primary Vendor-Specific Extended Query table 1.5
117 static int cfi_use_status_reg(struct cfi_private *cfi)
119 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
120 u8 poll_mask = CFI_POLL_STATUS_REG | CFI_POLL_DQ;
122 return extp->MinorVersion >= '5' &&
123 (extp->SoftwareFeatures & poll_mask) == CFI_POLL_STATUS_REG;
126 static void cfi_check_err_status(struct map_info *map, struct flchip *chip,
129 struct cfi_private *cfi = map->fldrv_priv;
132 if (!cfi_use_status_reg(cfi))
135 cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
136 cfi->device_type, NULL);
137 status = map_read(map, adr);
139 if (map_word_bitsset(map, status, CMD(0x3a))) {
140 unsigned long chipstatus = MERGESTATUS(status);
142 if (chipstatus & CFI_SR_ESB)
143 pr_err("%s erase operation failed, status %lx\n",
144 map->name, chipstatus);
145 if (chipstatus & CFI_SR_PSB)
146 pr_err("%s program operation failed, status %lx\n",
147 map->name, chipstatus);
148 if (chipstatus & CFI_SR_WBASB)
149 pr_err("%s buffer program command aborted, status %lx\n",
150 map->name, chipstatus);
151 if (chipstatus & CFI_SR_SLSB)
152 pr_err("%s sector write protected, status %lx\n",
153 map->name, chipstatus);
157 /* #define DEBUG_CFI_FEATURES */
160 #ifdef DEBUG_CFI_FEATURES
161 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
163 const char* erase_suspend[3] = {
164 "Not supported", "Read only", "Read/write"
166 const char* top_bottom[6] = {
167 "No WP", "8x8KiB sectors at top & bottom, no WP",
168 "Bottom boot", "Top boot",
169 "Uniform, Bottom WP", "Uniform, Top WP"
172 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
173 printk(" Address sensitive unlock: %s\n",
174 (extp->SiliconRevision & 1) ? "Not required" : "Required");
176 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
177 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
179 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
181 if (extp->BlkProt == 0)
182 printk(" Block protection: Not supported\n");
184 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
187 printk(" Temporary block unprotect: %s\n",
188 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
189 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
190 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
191 printk(" Burst mode: %s\n",
192 extp->BurstMode ? "Supported" : "Not supported");
193 if (extp->PageMode == 0)
194 printk(" Page mode: Not supported\n");
196 printk(" Page mode: %d word page\n", extp->PageMode << 2);
198 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
199 extp->VppMin >> 4, extp->VppMin & 0xf);
200 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
201 extp->VppMax >> 4, extp->VppMax & 0xf);
203 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
204 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
206 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
210 #ifdef AMD_BOOTLOC_BUG
211 /* Wheee. Bring me the head of someone at AMD. */
212 static void fixup_amd_bootblock(struct mtd_info *mtd)
214 struct map_info *map = mtd->priv;
215 struct cfi_private *cfi = map->fldrv_priv;
216 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
217 __u8 major = extp->MajorVersion;
218 __u8 minor = extp->MinorVersion;
220 if (((major << 8) | minor) < 0x3131) {
221 /* CFI version 1.0 => don't trust bootloc */
223 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
224 map->name, cfi->mfr, cfi->id);
226 /* AFAICS all 29LV400 with a bottom boot block have a device ID
227 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
228 * These were badly detected as they have the 0x80 bit set
229 * so treat them as a special case.
231 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
233 /* Macronix added CFI to their 2nd generation
234 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
235 * Fujitsu, Spansion, EON, ESI and older Macronix)
238 * Therefore also check the manufacturer.
239 * This reduces the risk of false detection due to
240 * the 8-bit device ID.
242 (cfi->mfr == CFI_MFR_MACRONIX)) {
243 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
244 " detected\n", map->name);
245 extp->TopBottom = 2; /* bottom boot */
247 if (cfi->id & 0x80) {
248 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
249 extp->TopBottom = 3; /* top boot */
251 extp->TopBottom = 2; /* bottom boot */
254 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
255 " deduced %s from Device ID\n", map->name, major, minor,
256 extp->TopBottom == 2 ? "bottom" : "top");
261 #if !FORCE_WORD_WRITE
262 static void fixup_use_write_buffers(struct mtd_info *mtd)
264 struct map_info *map = mtd->priv;
265 struct cfi_private *cfi = map->fldrv_priv;
266 if (cfi->cfiq->BufWriteTimeoutTyp) {
267 pr_debug("Using buffer write method\n");
268 mtd->_write = cfi_amdstd_write_buffers;
271 #endif /* !FORCE_WORD_WRITE */
273 /* Atmel chips don't use the same PRI format as AMD chips */
274 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
276 struct map_info *map = mtd->priv;
277 struct cfi_private *cfi = map->fldrv_priv;
278 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
279 struct cfi_pri_atmel atmel_pri;
281 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
282 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
284 if (atmel_pri.Features & 0x02)
285 extp->EraseSuspend = 2;
287 /* Some chips got it backwards... */
288 if (cfi->id == AT49BV6416) {
289 if (atmel_pri.BottomBoot)
294 if (atmel_pri.BottomBoot)
300 /* burst write mode not supported */
301 cfi->cfiq->BufWriteTimeoutTyp = 0;
302 cfi->cfiq->BufWriteTimeoutMax = 0;
305 static void fixup_use_secsi(struct mtd_info *mtd)
307 /* Setup for chips with a secsi area */
308 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
309 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
312 static void fixup_use_erase_chip(struct mtd_info *mtd)
314 struct map_info *map = mtd->priv;
315 struct cfi_private *cfi = map->fldrv_priv;
316 if ((cfi->cfiq->NumEraseRegions == 1) &&
317 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
318 mtd->_erase = cfi_amdstd_erase_chip;
324 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
327 static void fixup_use_atmel_lock(struct mtd_info *mtd)
329 mtd->_lock = cfi_atmel_lock;
330 mtd->_unlock = cfi_atmel_unlock;
331 mtd->flags |= MTD_POWERUP_LOCK;
334 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
336 struct map_info *map = mtd->priv;
337 struct cfi_private *cfi = map->fldrv_priv;
340 * These flashes report two separate eraseblock regions based on the
341 * sector_erase-size and block_erase-size, although they both operate on the
342 * same memory. This is not allowed according to CFI, so we just pick the
345 cfi->cfiq->NumEraseRegions = 1;
348 static void fixup_sst39vf(struct mtd_info *mtd)
350 struct map_info *map = mtd->priv;
351 struct cfi_private *cfi = map->fldrv_priv;
353 fixup_old_sst_eraseregion(mtd);
355 cfi->addr_unlock1 = 0x5555;
356 cfi->addr_unlock2 = 0x2AAA;
359 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
361 struct map_info *map = mtd->priv;
362 struct cfi_private *cfi = map->fldrv_priv;
364 fixup_old_sst_eraseregion(mtd);
366 cfi->addr_unlock1 = 0x555;
367 cfi->addr_unlock2 = 0x2AA;
369 cfi->sector_erase_cmd = CMD(0x50);
372 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
374 struct map_info *map = mtd->priv;
375 struct cfi_private *cfi = map->fldrv_priv;
377 fixup_sst39vf_rev_b(mtd);
380 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
381 * it should report a size of 8KBytes (0x0020*256).
383 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
384 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n",
388 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
390 struct map_info *map = mtd->priv;
391 struct cfi_private *cfi = map->fldrv_priv;
393 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
394 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
395 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n",
400 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
402 struct map_info *map = mtd->priv;
403 struct cfi_private *cfi = map->fldrv_priv;
405 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
406 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
407 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n",
412 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
414 struct map_info *map = mtd->priv;
415 struct cfi_private *cfi = map->fldrv_priv;
418 * S29NS512P flash uses more than 8bits to report number of sectors,
419 * which is not permitted by CFI.
421 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
422 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n",
426 /* Used to fix CFI-Tables of chips without Extended Query Tables */
427 static struct cfi_fixup cfi_nopri_fixup_table[] = {
428 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
429 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
430 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
431 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
432 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
433 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
434 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
435 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
439 static struct cfi_fixup cfi_fixup_table[] = {
440 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
441 #ifdef AMD_BOOTLOC_BUG
442 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
443 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
444 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
446 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
447 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
448 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
449 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
450 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
451 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
452 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
453 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
454 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
455 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
456 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
457 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
458 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
459 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
460 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
461 #if !FORCE_WORD_WRITE
462 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
466 static struct cfi_fixup jedec_fixup_table[] = {
467 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
468 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
469 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
473 static struct cfi_fixup fixup_table[] = {
474 /* The CFI vendor ids and the JEDEC vendor IDs appear
475 * to be common. It is like the devices id's are as
476 * well. This table is to pick all cases where
477 * we know that is the case.
479 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
480 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
485 static void cfi_fixup_major_minor(struct cfi_private *cfi,
486 struct cfi_pri_amdstd *extp)
488 if (cfi->mfr == CFI_MFR_SAMSUNG) {
489 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
490 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
492 * Samsung K8P2815UQB and K8D6x16UxM chips
493 * report major=0 / minor=0.
494 * K8D3x16UxC chips report major=3 / minor=3.
496 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
497 " Extended Query version to 1.%c\n",
499 extp->MajorVersion = '1';
504 * SST 38VF640x chips report major=0xFF / minor=0xFF.
506 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
507 extp->MajorVersion = '1';
508 extp->MinorVersion = '0';
512 static int is_m29ew(struct cfi_private *cfi)
514 if (cfi->mfr == CFI_MFR_INTEL &&
515 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
516 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
522 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
523 * Some revisions of the M29EW suffer from erase suspend hang ups. In
524 * particular, it can occur when the sequence
525 * Erase Confirm -> Suspend -> Program -> Resume
526 * causes a lockup due to internal timing issues. The consequence is that the
527 * erase cannot be resumed without inserting a dummy command after programming
528 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
529 * that writes an F0 command code before the RESUME command.
531 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
534 struct cfi_private *cfi = map->fldrv_priv;
535 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
537 map_write(map, CMD(0xF0), adr);
541 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
543 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
544 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
545 * command is issued after an ERASE RESUME operation without waiting for a
546 * minimum delay. The result is that once the ERASE seems to be completed
547 * (no bits are toggling), the contents of the Flash memory block on which
548 * the erase was ongoing could be inconsistent with the expected values
549 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
550 * values), causing a consequent failure of the ERASE operation.
551 * The occurrence of this issue could be high, especially when file system
552 * operations on the Flash are intensive. As a result, it is recommended
553 * that a patch be applied. Intensive file system operations can cause many
554 * calls to the garbage routine to free Flash space (also by erasing physical
555 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
556 * commands can occur. The problem disappears when a delay is inserted after
557 * the RESUME command by using the udelay() function available in Linux.
558 * The DELAY value must be tuned based on the customer's platform.
559 * The maximum value that fixes the problem in all cases is 500us.
560 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
562 * We have chosen 500µs because this latency is acceptable.
564 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
567 * Resolving the Delay After Resume Issue see Micron TN-13-07
568 * Worst case delay must be 500µs but 30-50µs should be ok as well
574 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
576 struct cfi_private *cfi = map->fldrv_priv;
577 struct device_node __maybe_unused *np = map->device_node;
578 struct mtd_info *mtd;
581 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
585 mtd->type = MTD_NORFLASH;
587 /* Fill in the default mtd operations */
588 mtd->_erase = cfi_amdstd_erase_varsize;
589 mtd->_write = cfi_amdstd_write_words;
590 mtd->_read = cfi_amdstd_read;
591 mtd->_sync = cfi_amdstd_sync;
592 mtd->_suspend = cfi_amdstd_suspend;
593 mtd->_resume = cfi_amdstd_resume;
594 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
595 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
596 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
597 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
598 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
599 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
600 mtd->flags = MTD_CAP_NORFLASH;
601 mtd->name = map->name;
603 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
605 pr_debug("MTD %s(): write buffer size %d\n", __func__,
608 mtd->_panic_write = cfi_amdstd_panic_write;
609 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
611 if (cfi->cfi_mode==CFI_MODE_CFI){
612 unsigned char bootloc;
613 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
614 struct cfi_pri_amdstd *extp;
616 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
619 * It's a real CFI chip, not one for which the probe
620 * routine faked a CFI structure.
622 cfi_fixup_major_minor(cfi, extp);
625 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
626 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
627 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
628 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
629 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
631 if (extp->MajorVersion != '1' ||
632 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
633 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
634 "version %c.%c (%#02x/%#02x).\n",
635 extp->MajorVersion, extp->MinorVersion,
636 extp->MajorVersion, extp->MinorVersion);
642 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
643 extp->MajorVersion, extp->MinorVersion);
645 /* Install our own private info structure */
646 cfi->cmdset_priv = extp;
648 /* Apply cfi device specific fixups */
649 cfi_fixup(mtd, cfi_fixup_table);
651 #ifdef DEBUG_CFI_FEATURES
652 /* Tell the user about it in lots of lovely detail */
653 cfi_tell_features(extp);
657 if (np && of_property_read_bool(
658 np, "use-advanced-sector-protection")
659 && extp->BlkProtUnprot == 8) {
660 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
661 mtd->_lock = cfi_ppb_lock;
662 mtd->_unlock = cfi_ppb_unlock;
663 mtd->_is_locked = cfi_ppb_is_locked;
667 bootloc = extp->TopBottom;
668 if ((bootloc < 2) || (bootloc > 5)) {
669 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
670 "bank location (%d). Assuming bottom.\n",
675 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
676 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
678 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
679 int j = (cfi->cfiq->NumEraseRegions-1)-i;
681 swap(cfi->cfiq->EraseRegionInfo[i],
682 cfi->cfiq->EraseRegionInfo[j]);
685 /* Set the default CFI lock/unlock addresses */
686 cfi->addr_unlock1 = 0x555;
687 cfi->addr_unlock2 = 0x2aa;
689 cfi_fixup(mtd, cfi_nopri_fixup_table);
691 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
697 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
698 /* Apply jedec specific fixups */
699 cfi_fixup(mtd, jedec_fixup_table);
701 /* Apply generic fixups */
702 cfi_fixup(mtd, fixup_table);
704 for (i=0; i< cfi->numchips; i++) {
705 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
706 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
707 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
709 * First calculate the timeout max according to timeout field
710 * of struct cfi_ident that probed from chip's CFI aera, if
711 * available. Specify a minimum of 2000us, in case the CFI data
714 if (cfi->cfiq->BufWriteTimeoutTyp &&
715 cfi->cfiq->BufWriteTimeoutMax)
716 cfi->chips[i].buffer_write_time_max =
717 1 << (cfi->cfiq->BufWriteTimeoutTyp +
718 cfi->cfiq->BufWriteTimeoutMax);
720 cfi->chips[i].buffer_write_time_max = 0;
722 cfi->chips[i].buffer_write_time_max =
723 max(cfi->chips[i].buffer_write_time_max, 2000);
725 cfi->chips[i].ref_point_counter = 0;
726 init_waitqueue_head(&(cfi->chips[i].wq));
729 map->fldrv = &cfi_amdstd_chipdrv;
731 return cfi_amdstd_setup(mtd);
733 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
734 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
735 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
736 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
737 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
739 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
741 struct map_info *map = mtd->priv;
742 struct cfi_private *cfi = map->fldrv_priv;
743 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
744 unsigned long offset = 0;
747 printk(KERN_NOTICE "number of %s chips: %d\n",
748 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
749 /* Select the correct geometry setup */
750 mtd->size = devsize * cfi->numchips;
752 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
753 mtd->eraseregions = kmalloc_array(mtd->numeraseregions,
754 sizeof(struct mtd_erase_region_info),
756 if (!mtd->eraseregions)
759 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
760 unsigned long ernum, ersize;
761 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
762 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
764 if (mtd->erasesize < ersize) {
765 mtd->erasesize = ersize;
767 for (j=0; j<cfi->numchips; j++) {
768 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
769 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
770 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
772 offset += (ersize * ernum);
774 if (offset != devsize) {
776 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
780 __module_get(THIS_MODULE);
781 register_reboot_notifier(&mtd->reboot_notifier);
785 kfree(mtd->eraseregions);
787 kfree(cfi->cmdset_priv);
793 * Return true if the chip is ready.
795 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
796 * non-suspended sector) and is indicated by no toggle bits toggling.
798 * Note that anything more complicated than checking if no bits are toggling
799 * (including checking DQ5 for an error status) is tricky to get working
800 * correctly and is therefore not done (particularly with interleaved chips
801 * as each chip must be checked independently of the others).
803 static int __xipram chip_ready(struct map_info *map, struct flchip *chip,
806 struct cfi_private *cfi = map->fldrv_priv;
809 if (cfi_use_status_reg(cfi)) {
810 map_word ready = CMD(CFI_SR_DRB);
812 * For chips that support status register, check device
815 cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
816 cfi->device_type, NULL);
817 d = map_read(map, addr);
819 return map_word_andequal(map, d, ready, ready);
822 d = map_read(map, addr);
823 t = map_read(map, addr);
825 return map_word_equal(map, d, t);
829 * Return true if the chip is ready and has the correct value.
831 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
832 * non-suspended sector) and it is indicated by no bits toggling.
834 * Error are indicated by toggling bits or bits held with the wrong value,
835 * or with bits toggling.
837 * Note that anything more complicated than checking if no bits are toggling
838 * (including checking DQ5 for an error status) is tricky to get working
839 * correctly and is therefore not done (particularly with interleaved chips
840 * as each chip must be checked independently of the others).
843 static int __xipram chip_good(struct map_info *map, struct flchip *chip,
844 unsigned long addr, map_word expected)
846 struct cfi_private *cfi = map->fldrv_priv;
849 if (cfi_use_status_reg(cfi)) {
850 map_word ready = CMD(CFI_SR_DRB);
851 map_word err = CMD(CFI_SR_PSB | CFI_SR_ESB);
853 * For chips that support status register, check device
854 * ready bit and Erase/Program status bit to know if
855 * operation succeeded.
857 cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
858 cfi->device_type, NULL);
859 curd = map_read(map, addr);
861 if (map_word_andequal(map, curd, ready, ready))
862 return !map_word_bitsset(map, curd, err);
867 oldd = map_read(map, addr);
868 curd = map_read(map, addr);
870 return map_word_equal(map, oldd, curd) &&
871 map_word_equal(map, curd, expected);
874 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
876 DECLARE_WAITQUEUE(wait, current);
877 struct cfi_private *cfi = map->fldrv_priv;
879 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
882 timeo = jiffies + HZ;
884 switch (chip->state) {
888 if (chip_ready(map, chip, adr))
891 if (time_after(jiffies, timeo)) {
892 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
895 mutex_unlock(&chip->mutex);
897 mutex_lock(&chip->mutex);
898 /* Someone else might have been playing with it. */
908 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
909 !(mode == FL_READY || mode == FL_POINT ||
910 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
913 /* Do not allow suspend iff read/write to EB address */
914 if ((adr & chip->in_progress_block_mask) ==
915 chip->in_progress_block_addr)
919 /* It's harmless to issue the Erase-Suspend and Erase-Resume
920 * commands when the erase algorithm isn't in progress. */
921 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
922 chip->oldstate = FL_ERASING;
923 chip->state = FL_ERASE_SUSPENDING;
924 chip->erase_suspended = 1;
926 if (chip_ready(map, chip, adr))
929 if (time_after(jiffies, timeo)) {
930 /* Should have suspended the erase by now.
931 * Send an Erase-Resume command as either
932 * there was an error (so leave the erase
933 * routine to recover from it) or we trying to
934 * use the erase-in-progress sector. */
935 put_chip(map, chip, adr);
936 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
940 mutex_unlock(&chip->mutex);
942 mutex_lock(&chip->mutex);
943 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
944 So we can just loop here. */
946 chip->state = FL_READY;
949 case FL_XIP_WHILE_ERASING:
950 if (mode != FL_READY && mode != FL_POINT &&
951 (!cfip || !(cfip->EraseSuspend&2)))
953 chip->oldstate = chip->state;
954 chip->state = FL_READY;
958 /* The machine is rebooting */
962 /* Only if there's no operation suspended... */
963 if (mode == FL_READY && chip->oldstate == FL_READY)
969 set_current_state(TASK_UNINTERRUPTIBLE);
970 add_wait_queue(&chip->wq, &wait);
971 mutex_unlock(&chip->mutex);
973 remove_wait_queue(&chip->wq, &wait);
974 mutex_lock(&chip->mutex);
980 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
982 struct cfi_private *cfi = map->fldrv_priv;
984 switch(chip->oldstate) {
986 cfi_fixup_m29ew_erase_suspend(map,
987 chip->in_progress_block_addr);
988 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
989 cfi_fixup_m29ew_delay_after_resume(cfi);
990 chip->oldstate = FL_READY;
991 chip->state = FL_ERASING;
994 case FL_XIP_WHILE_ERASING:
995 chip->state = chip->oldstate;
996 chip->oldstate = FL_READY;
1003 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
1008 #ifdef CONFIG_MTD_XIP
1011 * No interrupt what so ever can be serviced while the flash isn't in array
1012 * mode. This is ensured by the xip_disable() and xip_enable() functions
1013 * enclosing any code path where the flash is known not to be in array mode.
1014 * And within a XIP disabled code path, only functions marked with __xipram
1015 * may be called and nothing else (it's a good thing to inspect generated
1016 * assembly to make sure inline functions were actually inlined and that gcc
1017 * didn't emit calls to its own support functions). Also configuring MTD CFI
1018 * support to a single buswidth and a single interleave is also recommended.
1021 static void xip_disable(struct map_info *map, struct flchip *chip,
1024 /* TODO: chips with no XIP use should ignore and return */
1025 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
1026 local_irq_disable();
1029 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
1032 struct cfi_private *cfi = map->fldrv_priv;
1034 if (chip->state != FL_POINT && chip->state != FL_READY) {
1035 map_write(map, CMD(0xf0), adr);
1036 chip->state = FL_READY;
1038 (void) map_read(map, adr);
1044 * When a delay is required for the flash operation to complete, the
1045 * xip_udelay() function is polling for both the given timeout and pending
1046 * (but still masked) hardware interrupts. Whenever there is an interrupt
1047 * pending then the flash erase operation is suspended, array mode restored
1048 * and interrupts unmasked. Task scheduling might also happen at that
1049 * point. The CPU eventually returns from the interrupt or the call to
1050 * schedule() and the suspended flash operation is resumed for the remaining
1051 * of the delay period.
1053 * Warning: this function _will_ fool interrupt latency tracing tools.
1056 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
1057 unsigned long adr, int usec)
1059 struct cfi_private *cfi = map->fldrv_priv;
1060 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
1061 map_word status, OK = CMD(0x80);
1062 unsigned long suspended, start = xip_currtime();
1067 if (xip_irqpending() && extp &&
1068 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
1069 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
1071 * Let's suspend the erase operation when supported.
1072 * Note that we currently don't try to suspend
1073 * interleaved chips if there is already another
1074 * operation suspended (imagine what happens
1075 * when one chip was already done with the current
1076 * operation while another chip suspended it, then
1077 * we resume the whole thing at once). Yes, it
1080 map_write(map, CMD(0xb0), adr);
1081 usec -= xip_elapsed_since(start);
1082 suspended = xip_currtime();
1084 if (xip_elapsed_since(suspended) > 100000) {
1086 * The chip doesn't want to suspend
1087 * after waiting for 100 msecs.
1088 * This is a critical error but there
1089 * is not much we can do here.
1093 status = map_read(map, adr);
1094 } while (!map_word_andequal(map, status, OK, OK));
1096 /* Suspend succeeded */
1097 oldstate = chip->state;
1098 if (!map_word_bitsset(map, status, CMD(0x40)))
1100 chip->state = FL_XIP_WHILE_ERASING;
1101 chip->erase_suspended = 1;
1102 map_write(map, CMD(0xf0), adr);
1103 (void) map_read(map, adr);
1106 mutex_unlock(&chip->mutex);
1111 * We're back. However someone else might have
1112 * decided to go write to the chip if we are in
1113 * a suspended erase state. If so let's wait
1116 mutex_lock(&chip->mutex);
1117 while (chip->state != FL_XIP_WHILE_ERASING) {
1118 DECLARE_WAITQUEUE(wait, current);
1119 set_current_state(TASK_UNINTERRUPTIBLE);
1120 add_wait_queue(&chip->wq, &wait);
1121 mutex_unlock(&chip->mutex);
1123 remove_wait_queue(&chip->wq, &wait);
1124 mutex_lock(&chip->mutex);
1126 /* Disallow XIP again */
1127 local_irq_disable();
1129 /* Correct Erase Suspend Hangups for M29EW */
1130 cfi_fixup_m29ew_erase_suspend(map, adr);
1131 /* Resume the write or erase operation */
1132 map_write(map, cfi->sector_erase_cmd, adr);
1133 chip->state = oldstate;
1134 start = xip_currtime();
1135 } else if (usec >= 1000000/HZ) {
1137 * Try to save on CPU power when waiting delay
1138 * is at least a system timer tick period.
1139 * No need to be extremely accurate here.
1143 status = map_read(map, adr);
1144 } while (!map_word_andequal(map, status, OK, OK)
1145 && xip_elapsed_since(start) < usec);
1148 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1151 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1152 * the flash is actively programming or erasing since we have to poll for
1153 * the operation to complete anyway. We can't do that in a generic way with
1154 * a XIP setup so do it before the actual flash operation in this case
1155 * and stub it out from INVALIDATE_CACHE_UDELAY.
1157 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1158 INVALIDATE_CACHED_RANGE(map, from, size)
1160 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1161 UDELAY(map, chip, adr, usec)
1166 * Activating this XIP support changes the way the code works a bit. For
1167 * example the code to suspend the current process when concurrent access
1168 * happens is never executed because xip_udelay() will always return with the
1169 * same chip state as it was entered with. This is why there is no care for
1170 * the presence of add_wait_queue() or schedule() calls from within a couple
1171 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1172 * The queueing and scheduling are always happening within xip_udelay().
1174 * Similarly, get_chip() and put_chip() just happen to always be executed
1175 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1176 * is in array mode, therefore never executing many cases therein and not
1177 * causing any problem with XIP.
1182 #define xip_disable(map, chip, adr)
1183 #define xip_enable(map, chip, adr)
1184 #define XIP_INVAL_CACHED_RANGE(x...)
1186 #define UDELAY(map, chip, adr, usec) \
1188 mutex_unlock(&chip->mutex); \
1190 mutex_lock(&chip->mutex); \
1193 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1195 mutex_unlock(&chip->mutex); \
1196 INVALIDATE_CACHED_RANGE(map, adr, len); \
1198 mutex_lock(&chip->mutex); \
1203 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1205 unsigned long cmd_addr;
1206 struct cfi_private *cfi = map->fldrv_priv;
1211 /* Ensure cmd read/writes are aligned. */
1212 cmd_addr = adr & ~(map_bankwidth(map)-1);
1214 mutex_lock(&chip->mutex);
1215 ret = get_chip(map, chip, cmd_addr, FL_READY);
1217 mutex_unlock(&chip->mutex);
1221 if (chip->state != FL_POINT && chip->state != FL_READY) {
1222 map_write(map, CMD(0xf0), cmd_addr);
1223 chip->state = FL_READY;
1226 map_copy_from(map, buf, adr, len);
1228 put_chip(map, chip, cmd_addr);
1230 mutex_unlock(&chip->mutex);
1235 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1237 struct map_info *map = mtd->priv;
1238 struct cfi_private *cfi = map->fldrv_priv;
1243 /* ofs: offset within the first chip that the first read should start */
1244 chipnum = (from >> cfi->chipshift);
1245 ofs = from - (chipnum << cfi->chipshift);
1248 unsigned long thislen;
1250 if (chipnum >= cfi->numchips)
1253 if ((len + ofs -1) >> cfi->chipshift)
1254 thislen = (1<<cfi->chipshift) - ofs;
1258 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1272 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1273 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1275 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1276 loff_t adr, size_t len)
1278 struct cfi_private *cfi = map->fldrv_priv;
1280 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1281 cfi->device_type, NULL);
1282 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1283 cfi->device_type, NULL);
1284 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1285 cfi->device_type, NULL);
1287 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1290 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1291 loff_t adr, size_t len)
1293 struct cfi_private *cfi = map->fldrv_priv;
1295 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1296 cfi->device_type, NULL);
1297 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1298 cfi->device_type, NULL);
1299 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1300 cfi->device_type, NULL);
1301 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1302 cfi->device_type, NULL);
1304 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1307 static inline int do_read_secsi_onechip(struct map_info *map,
1308 struct flchip *chip, loff_t adr,
1309 size_t len, u_char *buf,
1312 DECLARE_WAITQUEUE(wait, current);
1315 mutex_lock(&chip->mutex);
1317 if (chip->state != FL_READY){
1318 set_current_state(TASK_UNINTERRUPTIBLE);
1319 add_wait_queue(&chip->wq, &wait);
1321 mutex_unlock(&chip->mutex);
1324 remove_wait_queue(&chip->wq, &wait);
1331 chip->state = FL_READY;
1333 otp_enter(map, chip, adr, len);
1334 map_copy_from(map, buf, adr, len);
1335 otp_exit(map, chip, adr, len);
1338 mutex_unlock(&chip->mutex);
1343 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1345 struct map_info *map = mtd->priv;
1346 struct cfi_private *cfi = map->fldrv_priv;
1351 /* ofs: offset within the first chip that the first read should start */
1352 /* 8 secsi bytes per chip */
1357 unsigned long thislen;
1359 if (chipnum >= cfi->numchips)
1362 if ((len + ofs -1) >> 3)
1363 thislen = (1<<3) - ofs;
1367 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1382 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1383 unsigned long adr, map_word datum,
1386 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1387 size_t len, u_char *buf, size_t grouplen)
1391 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1392 int gap = adr - bus_ofs;
1393 int n = min_t(int, len, map_bankwidth(map) - gap);
1394 map_word datum = map_word_ff(map);
1396 if (n != map_bankwidth(map)) {
1397 /* partial write of a word, load old contents */
1398 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1399 datum = map_read(map, bus_ofs);
1400 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1403 datum = map_word_load_partial(map, datum, buf, gap, n);
1404 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1416 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1417 size_t len, u_char *buf, size_t grouplen)
1419 struct cfi_private *cfi = map->fldrv_priv;
1421 unsigned long timeo;
1424 /* make sure area matches group boundaries */
1425 if ((adr != 0) || (len != grouplen))
1428 mutex_lock(&chip->mutex);
1429 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1431 mutex_unlock(&chip->mutex);
1434 chip->state = FL_LOCKING;
1436 /* Enter lock register command */
1437 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1438 cfi->device_type, NULL);
1439 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1440 cfi->device_type, NULL);
1441 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1442 cfi->device_type, NULL);
1444 /* read lock register */
1445 lockreg = cfi_read_query(map, 0);
1447 /* set bit 0 to protect extended memory block */
1450 /* set bit 0 to protect extended memory block */
1451 /* write lock register */
1452 map_write(map, CMD(0xA0), chip->start);
1453 map_write(map, CMD(lockreg), chip->start);
1455 /* wait for chip to become ready */
1456 timeo = jiffies + msecs_to_jiffies(2);
1458 if (chip_ready(map, chip, adr))
1461 if (time_after(jiffies, timeo)) {
1462 pr_err("Waiting for chip to be ready timed out.\n");
1466 UDELAY(map, chip, 0, 1);
1469 /* exit protection commands */
1470 map_write(map, CMD(0x90), chip->start);
1471 map_write(map, CMD(0x00), chip->start);
1473 chip->state = FL_READY;
1474 put_chip(map, chip, chip->start);
1475 mutex_unlock(&chip->mutex);
1480 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1481 size_t *retlen, u_char *buf,
1482 otp_op_t action, int user_regs)
1484 struct map_info *map = mtd->priv;
1485 struct cfi_private *cfi = map->fldrv_priv;
1486 int ofs_factor = cfi->interleave * cfi->device_type;
1489 struct flchip *chip;
1490 uint8_t otp, lockreg;
1493 size_t user_size, factory_size, otpsize;
1494 loff_t user_offset, factory_offset, otpoffset;
1495 int user_locked = 0, otplocked;
1499 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1500 chip = &cfi->chips[chipnum];
1504 /* Micron M29EW family */
1505 if (is_m29ew(cfi)) {
1508 /* check whether secsi area is factory locked
1510 mutex_lock(&chip->mutex);
1511 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1513 mutex_unlock(&chip->mutex);
1516 cfi_qry_mode_on(base, map, cfi);
1517 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1518 cfi_qry_mode_off(base, map, cfi);
1519 put_chip(map, chip, base);
1520 mutex_unlock(&chip->mutex);
1523 /* factory locked */
1525 factory_size = 0x100;
1527 /* customer lockable */
1531 mutex_lock(&chip->mutex);
1532 ret = get_chip(map, chip, base, FL_LOCKING);
1534 mutex_unlock(&chip->mutex);
1538 /* Enter lock register command */
1539 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1540 chip->start, map, cfi,
1541 cfi->device_type, NULL);
1542 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1543 chip->start, map, cfi,
1544 cfi->device_type, NULL);
1545 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1546 chip->start, map, cfi,
1547 cfi->device_type, NULL);
1548 /* read lock register */
1549 lockreg = cfi_read_query(map, 0);
1550 /* exit protection commands */
1551 map_write(map, CMD(0x90), chip->start);
1552 map_write(map, CMD(0x00), chip->start);
1553 put_chip(map, chip, chip->start);
1554 mutex_unlock(&chip->mutex);
1556 user_locked = ((lockreg & 0x01) == 0x00);
1560 otpsize = user_regs ? user_size : factory_size;
1563 otpoffset = user_regs ? user_offset : factory_offset;
1564 otplocked = user_regs ? user_locked : 1;
1567 /* return otpinfo */
1568 struct otp_info *otpinfo;
1569 len -= sizeof(*otpinfo);
1572 otpinfo = (struct otp_info *)buf;
1573 otpinfo->start = from;
1574 otpinfo->length = otpsize;
1575 otpinfo->locked = otplocked;
1576 buf += sizeof(*otpinfo);
1577 *retlen += sizeof(*otpinfo);
1579 } else if ((from < otpsize) && (len > 0)) {
1581 size = (len < otpsize - from) ? len : otpsize - from;
1582 ret = action(map, chip, otpoffset + from, size, buf,
1598 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1599 size_t *retlen, struct otp_info *buf)
1601 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1605 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1606 size_t *retlen, struct otp_info *buf)
1608 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1612 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1613 size_t len, size_t *retlen,
1616 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1617 buf, do_read_secsi_onechip, 0);
1620 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1621 size_t len, size_t *retlen,
1624 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1625 buf, do_read_secsi_onechip, 1);
1628 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1629 size_t len, size_t *retlen,
1632 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1636 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1640 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1644 static int __xipram do_write_oneword_once(struct map_info *map,
1645 struct flchip *chip,
1646 unsigned long adr, map_word datum,
1647 int mode, struct cfi_private *cfi)
1649 unsigned long timeo = jiffies + HZ;
1651 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1652 * have a max write time of a few hundreds usec). However, we should
1653 * use the maximum timeout value given by the chip at probe time
1654 * instead. Unfortunately, struct flchip does have a field for
1655 * maximum timeout, only for typical which can be far too short
1656 * depending of the conditions. The ' + 1' is to avoid having a
1657 * timeout of 0 jiffies if HZ is smaller than 1000.
1659 unsigned long uWriteTimeout = (HZ / 1000) + 1;
1662 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1663 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1664 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1665 map_write(map, datum, adr);
1668 INVALIDATE_CACHE_UDELAY(map, chip,
1669 adr, map_bankwidth(map),
1670 chip->word_write_time);
1672 /* See comment above for timeout value. */
1673 timeo = jiffies + uWriteTimeout;
1675 if (chip->state != mode) {
1676 /* Someone's suspended the write. Sleep */
1677 DECLARE_WAITQUEUE(wait, current);
1679 set_current_state(TASK_UNINTERRUPTIBLE);
1680 add_wait_queue(&chip->wq, &wait);
1681 mutex_unlock(&chip->mutex);
1683 remove_wait_queue(&chip->wq, &wait);
1684 timeo = jiffies + (HZ / 2); /* FIXME */
1685 mutex_lock(&chip->mutex);
1690 * We check "time_after" and "!chip_good" before checking
1691 * "chip_good" to avoid the failure due to scheduling.
1693 if (time_after(jiffies, timeo) &&
1694 !chip_good(map, chip, adr, datum)) {
1695 xip_enable(map, chip, adr);
1696 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1697 xip_disable(map, chip, adr);
1702 if (chip_good(map, chip, adr, datum))
1705 /* Latency issues. Drop the lock, wait a while and retry */
1706 UDELAY(map, chip, adr, 1);
1712 static int __xipram do_write_oneword_start(struct map_info *map,
1713 struct flchip *chip,
1714 unsigned long adr, int mode)
1718 mutex_lock(&chip->mutex);
1720 ret = get_chip(map, chip, adr, mode);
1722 mutex_unlock(&chip->mutex);
1726 if (mode == FL_OTP_WRITE)
1727 otp_enter(map, chip, adr, map_bankwidth(map));
1732 static void __xipram do_write_oneword_done(struct map_info *map,
1733 struct flchip *chip,
1734 unsigned long adr, int mode)
1736 if (mode == FL_OTP_WRITE)
1737 otp_exit(map, chip, adr, map_bankwidth(map));
1739 chip->state = FL_READY;
1741 put_chip(map, chip, adr);
1743 mutex_unlock(&chip->mutex);
1746 static int __xipram do_write_oneword_retry(struct map_info *map,
1747 struct flchip *chip,
1748 unsigned long adr, map_word datum,
1751 struct cfi_private *cfi = map->fldrv_priv;
1757 * Check for a NOP for the case when the datum to write is already
1758 * present - it saves time and works around buggy chips that corrupt
1759 * data at other locations when 0xff is written to a location that
1760 * already contains 0xff.
1762 oldd = map_read(map, adr);
1763 if (map_word_equal(map, oldd, datum)) {
1764 pr_debug("MTD %s(): NOP\n", __func__);
1768 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1770 xip_disable(map, chip, adr);
1773 ret = do_write_oneword_once(map, chip, adr, datum, mode, cfi);
1775 /* reset on all failures. */
1776 cfi_check_err_status(map, chip, adr);
1777 map_write(map, CMD(0xF0), chip->start);
1778 /* FIXME - should have reset delay before continuing */
1780 if (++retry_cnt <= MAX_RETRIES) {
1785 xip_enable(map, chip, adr);
1790 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1791 unsigned long adr, map_word datum,
1798 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", __func__, adr,
1801 ret = do_write_oneword_start(map, chip, adr, mode);
1805 ret = do_write_oneword_retry(map, chip, adr, datum, mode);
1807 do_write_oneword_done(map, chip, adr, mode);
1813 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1814 size_t *retlen, const u_char *buf)
1816 struct map_info *map = mtd->priv;
1817 struct cfi_private *cfi = map->fldrv_priv;
1820 unsigned long ofs, chipstart;
1821 DECLARE_WAITQUEUE(wait, current);
1823 chipnum = to >> cfi->chipshift;
1824 ofs = to - (chipnum << cfi->chipshift);
1825 chipstart = cfi->chips[chipnum].start;
1827 /* If it's not bus-aligned, do the first byte write */
1828 if (ofs & (map_bankwidth(map)-1)) {
1829 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1830 int i = ofs - bus_ofs;
1835 mutex_lock(&cfi->chips[chipnum].mutex);
1837 if (cfi->chips[chipnum].state != FL_READY) {
1838 set_current_state(TASK_UNINTERRUPTIBLE);
1839 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1841 mutex_unlock(&cfi->chips[chipnum].mutex);
1844 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1848 /* Load 'tmp_buf' with old contents of flash */
1849 tmp_buf = map_read(map, bus_ofs+chipstart);
1851 mutex_unlock(&cfi->chips[chipnum].mutex);
1853 /* Number of bytes to copy from buffer */
1854 n = min_t(int, len, map_bankwidth(map)-i);
1856 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1858 ret = do_write_oneword(map, &cfi->chips[chipnum],
1859 bus_ofs, tmp_buf, FL_WRITING);
1868 if (ofs >> cfi->chipshift) {
1871 if (chipnum == cfi->numchips)
1876 /* We are now aligned, write as much as possible */
1877 while(len >= map_bankwidth(map)) {
1880 datum = map_word_load(map, buf);
1882 ret = do_write_oneword(map, &cfi->chips[chipnum],
1883 ofs, datum, FL_WRITING);
1887 ofs += map_bankwidth(map);
1888 buf += map_bankwidth(map);
1889 (*retlen) += map_bankwidth(map);
1890 len -= map_bankwidth(map);
1892 if (ofs >> cfi->chipshift) {
1895 if (chipnum == cfi->numchips)
1897 chipstart = cfi->chips[chipnum].start;
1901 /* Write the trailing bytes if any */
1902 if (len & (map_bankwidth(map)-1)) {
1906 mutex_lock(&cfi->chips[chipnum].mutex);
1908 if (cfi->chips[chipnum].state != FL_READY) {
1909 set_current_state(TASK_UNINTERRUPTIBLE);
1910 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1912 mutex_unlock(&cfi->chips[chipnum].mutex);
1915 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1919 tmp_buf = map_read(map, ofs + chipstart);
1921 mutex_unlock(&cfi->chips[chipnum].mutex);
1923 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1925 ret = do_write_oneword(map, &cfi->chips[chipnum],
1926 ofs, tmp_buf, FL_WRITING);
1936 #if !FORCE_WORD_WRITE
1937 static int __xipram do_write_buffer_wait(struct map_info *map,
1938 struct flchip *chip, unsigned long adr,
1941 unsigned long timeo;
1942 unsigned long u_write_timeout;
1946 * Timeout is calculated according to CFI data, if available.
1947 * See more comments in cfi_cmdset_0002().
1949 u_write_timeout = usecs_to_jiffies(chip->buffer_write_time_max);
1950 timeo = jiffies + u_write_timeout;
1953 if (chip->state != FL_WRITING) {
1954 /* Someone's suspended the write. Sleep */
1955 DECLARE_WAITQUEUE(wait, current);
1957 set_current_state(TASK_UNINTERRUPTIBLE);
1958 add_wait_queue(&chip->wq, &wait);
1959 mutex_unlock(&chip->mutex);
1961 remove_wait_queue(&chip->wq, &wait);
1962 timeo = jiffies + (HZ / 2); /* FIXME */
1963 mutex_lock(&chip->mutex);
1968 * We check "time_after" and "!chip_good" before checking
1969 * "chip_good" to avoid the failure due to scheduling.
1971 if (time_after(jiffies, timeo) &&
1972 !chip_good(map, chip, adr, datum)) {
1977 if (chip_good(map, chip, adr, datum))
1980 /* Latency issues. Drop the lock, wait a while and retry */
1981 UDELAY(map, chip, adr, 1);
1987 static void __xipram do_write_buffer_reset(struct map_info *map,
1988 struct flchip *chip,
1989 struct cfi_private *cfi)
1992 * Recovery from write-buffer programming failures requires
1993 * the write-to-buffer-reset sequence. Since the last part
1994 * of the sequence also works as a normal reset, we can run
1995 * the same commands regardless of why we are here.
1997 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
1999 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2000 cfi->device_type, NULL);
2001 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2002 cfi->device_type, NULL);
2003 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
2004 cfi->device_type, NULL);
2006 /* FIXME - should have reset delay before continuing */
2010 * FIXME: interleaved mode not tested, and probably not supported!
2012 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
2013 unsigned long adr, const u_char *buf,
2016 struct cfi_private *cfi = map->fldrv_priv;
2018 unsigned long cmd_adr;
2025 mutex_lock(&chip->mutex);
2026 ret = get_chip(map, chip, adr, FL_WRITING);
2028 mutex_unlock(&chip->mutex);
2032 datum = map_word_load(map, buf);
2034 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
2035 __func__, adr, datum.x[0]);
2037 XIP_INVAL_CACHED_RANGE(map, adr, len);
2039 xip_disable(map, chip, cmd_adr);
2041 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2042 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2044 /* Write Buffer Load */
2045 map_write(map, CMD(0x25), cmd_adr);
2047 chip->state = FL_WRITING_TO_BUFFER;
2049 /* Write length of data to come */
2050 words = len / map_bankwidth(map);
2051 map_write(map, CMD(words - 1), cmd_adr);
2054 while(z < words * map_bankwidth(map)) {
2055 datum = map_word_load(map, buf);
2056 map_write(map, datum, adr + z);
2058 z += map_bankwidth(map);
2059 buf += map_bankwidth(map);
2061 z -= map_bankwidth(map);
2065 /* Write Buffer Program Confirm: GO GO GO */
2066 map_write(map, CMD(0x29), cmd_adr);
2067 chip->state = FL_WRITING;
2069 INVALIDATE_CACHE_UDELAY(map, chip,
2070 adr, map_bankwidth(map),
2071 chip->word_write_time);
2073 ret = do_write_buffer_wait(map, chip, adr, datum);
2075 cfi_check_err_status(map, chip, adr);
2076 do_write_buffer_reset(map, chip, cfi);
2077 pr_err("MTD %s(): software timeout, address:0x%.8lx.\n",
2081 xip_enable(map, chip, adr);
2083 chip->state = FL_READY;
2085 put_chip(map, chip, adr);
2086 mutex_unlock(&chip->mutex);
2092 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
2093 size_t *retlen, const u_char *buf)
2095 struct map_info *map = mtd->priv;
2096 struct cfi_private *cfi = map->fldrv_priv;
2097 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
2102 chipnum = to >> cfi->chipshift;
2103 ofs = to - (chipnum << cfi->chipshift);
2105 /* If it's not bus-aligned, do the first word write */
2106 if (ofs & (map_bankwidth(map)-1)) {
2107 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
2108 if (local_len > len)
2110 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
2111 local_len, retlen, buf);
2118 if (ofs >> cfi->chipshift) {
2121 if (chipnum == cfi->numchips)
2126 /* Write buffer is worth it only if more than one word to write... */
2127 while (len >= map_bankwidth(map) * 2) {
2128 /* We must not cross write block boundaries */
2129 int size = wbufsize - (ofs & (wbufsize-1));
2133 if (size % map_bankwidth(map))
2134 size -= size % map_bankwidth(map);
2136 ret = do_write_buffer(map, &cfi->chips[chipnum],
2146 if (ofs >> cfi->chipshift) {
2149 if (chipnum == cfi->numchips)
2155 size_t retlen_dregs = 0;
2157 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
2158 len, &retlen_dregs, buf);
2160 *retlen += retlen_dregs;
2166 #endif /* !FORCE_WORD_WRITE */
2169 * Wait for the flash chip to become ready to write data
2171 * This is only called during the panic_write() path. When panic_write()
2172 * is called, the kernel is in the process of a panic, and will soon be
2173 * dead. Therefore we don't take any locks, and attempt to get access
2174 * to the chip as soon as possible.
2176 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2179 struct cfi_private *cfi = map->fldrv_priv;
2184 * If the driver thinks the chip is idle, and no toggle bits
2185 * are changing, then the chip is actually idle for sure.
2187 if (chip->state == FL_READY && chip_ready(map, chip, adr))
2191 * Try several times to reset the chip and then wait for it
2192 * to become idle. The upper limit of a few milliseconds of
2193 * delay isn't a big problem: the kernel is dying anyway. It
2194 * is more important to save the messages.
2196 while (retries > 0) {
2197 const unsigned long timeo = (HZ / 1000) + 1;
2199 /* send the reset command */
2200 map_write(map, CMD(0xF0), chip->start);
2202 /* wait for the chip to become ready */
2203 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2204 if (chip_ready(map, chip, adr))
2213 /* the chip never became ready */
2218 * Write out one word of data to a single flash chip during a kernel panic
2220 * This is only called during the panic_write() path. When panic_write()
2221 * is called, the kernel is in the process of a panic, and will soon be
2222 * dead. Therefore we don't take any locks, and attempt to get access
2223 * to the chip as soon as possible.
2225 * The implementation of this routine is intentionally similar to
2226 * do_write_oneword(), in order to ease code maintenance.
2228 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2229 unsigned long adr, map_word datum)
2231 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2232 struct cfi_private *cfi = map->fldrv_priv;
2240 ret = cfi_amdstd_panic_wait(map, chip, adr);
2244 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2245 __func__, adr, datum.x[0]);
2248 * Check for a NOP for the case when the datum to write is already
2249 * present - it saves time and works around buggy chips that corrupt
2250 * data at other locations when 0xff is written to a location that
2251 * already contains 0xff.
2253 oldd = map_read(map, adr);
2254 if (map_word_equal(map, oldd, datum)) {
2255 pr_debug("MTD %s(): NOP\n", __func__);
2262 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2263 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2264 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2265 map_write(map, datum, adr);
2267 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2268 if (chip_ready(map, chip, adr))
2274 if (!chip_good(map, chip, adr, datum)) {
2275 /* reset on all failures. */
2276 cfi_check_err_status(map, chip, adr);
2277 map_write(map, CMD(0xF0), chip->start);
2278 /* FIXME - should have reset delay before continuing */
2280 if (++retry_cnt <= MAX_RETRIES)
2292 * Write out some data during a kernel panic
2294 * This is used by the mtdoops driver to save the dying messages from a
2295 * kernel which has panic'd.
2297 * This routine ignores all of the locking used throughout the rest of the
2298 * driver, in order to ensure that the data gets written out no matter what
2299 * state this driver (and the flash chip itself) was in when the kernel crashed.
2301 * The implementation of this routine is intentionally similar to
2302 * cfi_amdstd_write_words(), in order to ease code maintenance.
2304 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2305 size_t *retlen, const u_char *buf)
2307 struct map_info *map = mtd->priv;
2308 struct cfi_private *cfi = map->fldrv_priv;
2309 unsigned long ofs, chipstart;
2313 chipnum = to >> cfi->chipshift;
2314 ofs = to - (chipnum << cfi->chipshift);
2315 chipstart = cfi->chips[chipnum].start;
2317 /* If it's not bus aligned, do the first byte write */
2318 if (ofs & (map_bankwidth(map) - 1)) {
2319 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2320 int i = ofs - bus_ofs;
2324 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2328 /* Load 'tmp_buf' with old contents of flash */
2329 tmp_buf = map_read(map, bus_ofs + chipstart);
2331 /* Number of bytes to copy from buffer */
2332 n = min_t(int, len, map_bankwidth(map) - i);
2334 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2336 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2346 if (ofs >> cfi->chipshift) {
2349 if (chipnum == cfi->numchips)
2354 /* We are now aligned, write as much as possible */
2355 while (len >= map_bankwidth(map)) {
2358 datum = map_word_load(map, buf);
2360 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2365 ofs += map_bankwidth(map);
2366 buf += map_bankwidth(map);
2367 (*retlen) += map_bankwidth(map);
2368 len -= map_bankwidth(map);
2370 if (ofs >> cfi->chipshift) {
2373 if (chipnum == cfi->numchips)
2376 chipstart = cfi->chips[chipnum].start;
2380 /* Write the trailing bytes if any */
2381 if (len & (map_bankwidth(map) - 1)) {
2384 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2388 tmp_buf = map_read(map, ofs + chipstart);
2390 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2392 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2405 * Handle devices with one erase region, that only implement
2406 * the chip erase command.
2408 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2410 struct cfi_private *cfi = map->fldrv_priv;
2411 unsigned long timeo = jiffies + HZ;
2412 unsigned long int adr;
2413 DECLARE_WAITQUEUE(wait, current);
2417 adr = cfi->addr_unlock1;
2419 mutex_lock(&chip->mutex);
2420 ret = get_chip(map, chip, adr, FL_ERASING);
2422 mutex_unlock(&chip->mutex);
2426 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2427 __func__, chip->start);
2429 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2431 xip_disable(map, chip, adr);
2434 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2435 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2436 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2437 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2438 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2439 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2441 chip->state = FL_ERASING;
2442 chip->erase_suspended = 0;
2443 chip->in_progress_block_addr = adr;
2444 chip->in_progress_block_mask = ~(map->size - 1);
2446 INVALIDATE_CACHE_UDELAY(map, chip,
2448 chip->erase_time*500);
2450 timeo = jiffies + (HZ*20);
2453 if (chip->state != FL_ERASING) {
2454 /* Someone's suspended the erase. Sleep */
2455 set_current_state(TASK_UNINTERRUPTIBLE);
2456 add_wait_queue(&chip->wq, &wait);
2457 mutex_unlock(&chip->mutex);
2459 remove_wait_queue(&chip->wq, &wait);
2460 mutex_lock(&chip->mutex);
2463 if (chip->erase_suspended) {
2464 /* This erase was suspended and resumed.
2465 Adjust the timeout */
2466 timeo = jiffies + (HZ*20); /* FIXME */
2467 chip->erase_suspended = 0;
2470 if (chip_good(map, chip, adr, map_word_ff(map)))
2473 if (time_after(jiffies, timeo)) {
2474 printk(KERN_WARNING "MTD %s(): software timeout\n",
2480 /* Latency issues. Drop the lock, wait a while and retry */
2481 UDELAY(map, chip, adr, 1000000/HZ);
2483 /* Did we succeed? */
2485 /* reset on all failures. */
2486 cfi_check_err_status(map, chip, adr);
2487 map_write(map, CMD(0xF0), chip->start);
2488 /* FIXME - should have reset delay before continuing */
2490 if (++retry_cnt <= MAX_RETRIES) {
2496 chip->state = FL_READY;
2497 xip_enable(map, chip, adr);
2499 put_chip(map, chip, adr);
2500 mutex_unlock(&chip->mutex);
2506 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2508 struct cfi_private *cfi = map->fldrv_priv;
2509 unsigned long timeo = jiffies + HZ;
2510 DECLARE_WAITQUEUE(wait, current);
2516 mutex_lock(&chip->mutex);
2517 ret = get_chip(map, chip, adr, FL_ERASING);
2519 mutex_unlock(&chip->mutex);
2523 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2526 XIP_INVAL_CACHED_RANGE(map, adr, len);
2528 xip_disable(map, chip, adr);
2531 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2532 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2533 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2534 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2535 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2536 map_write(map, cfi->sector_erase_cmd, adr);
2538 chip->state = FL_ERASING;
2539 chip->erase_suspended = 0;
2540 chip->in_progress_block_addr = adr;
2541 chip->in_progress_block_mask = ~(len - 1);
2543 INVALIDATE_CACHE_UDELAY(map, chip,
2545 chip->erase_time*500);
2547 timeo = jiffies + (HZ*20);
2550 if (chip->state != FL_ERASING) {
2551 /* Someone's suspended the erase. Sleep */
2552 set_current_state(TASK_UNINTERRUPTIBLE);
2553 add_wait_queue(&chip->wq, &wait);
2554 mutex_unlock(&chip->mutex);
2556 remove_wait_queue(&chip->wq, &wait);
2557 mutex_lock(&chip->mutex);
2560 if (chip->erase_suspended) {
2561 /* This erase was suspended and resumed.
2562 Adjust the timeout */
2563 timeo = jiffies + (HZ*20); /* FIXME */
2564 chip->erase_suspended = 0;
2567 if (chip_good(map, chip, adr, map_word_ff(map)))
2570 if (time_after(jiffies, timeo)) {
2571 printk(KERN_WARNING "MTD %s(): software timeout\n",
2577 /* Latency issues. Drop the lock, wait a while and retry */
2578 UDELAY(map, chip, adr, 1000000/HZ);
2580 /* Did we succeed? */
2582 /* reset on all failures. */
2583 cfi_check_err_status(map, chip, adr);
2584 map_write(map, CMD(0xF0), chip->start);
2585 /* FIXME - should have reset delay before continuing */
2587 if (++retry_cnt <= MAX_RETRIES) {
2593 chip->state = FL_READY;
2594 xip_enable(map, chip, adr);
2596 put_chip(map, chip, adr);
2597 mutex_unlock(&chip->mutex);
2602 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2604 return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr,
2609 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2611 struct map_info *map = mtd->priv;
2612 struct cfi_private *cfi = map->fldrv_priv;
2614 if (instr->addr != 0)
2617 if (instr->len != mtd->size)
2620 return do_erase_chip(map, &cfi->chips[0]);
2623 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2624 unsigned long adr, int len, void *thunk)
2626 struct cfi_private *cfi = map->fldrv_priv;
2629 mutex_lock(&chip->mutex);
2630 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2633 chip->state = FL_LOCKING;
2635 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2637 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2638 cfi->device_type, NULL);
2639 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2640 cfi->device_type, NULL);
2641 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2642 cfi->device_type, NULL);
2643 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2644 cfi->device_type, NULL);
2645 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2646 cfi->device_type, NULL);
2647 map_write(map, CMD(0x40), chip->start + adr);
2649 chip->state = FL_READY;
2650 put_chip(map, chip, adr + chip->start);
2654 mutex_unlock(&chip->mutex);
2658 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2659 unsigned long adr, int len, void *thunk)
2661 struct cfi_private *cfi = map->fldrv_priv;
2664 mutex_lock(&chip->mutex);
2665 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2668 chip->state = FL_UNLOCKING;
2670 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2672 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2673 cfi->device_type, NULL);
2674 map_write(map, CMD(0x70), adr);
2676 chip->state = FL_READY;
2677 put_chip(map, chip, adr + chip->start);
2681 mutex_unlock(&chip->mutex);
2685 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2687 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2690 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2692 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2696 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2700 struct flchip *chip;
2705 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2706 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2707 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2709 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2710 struct flchip *chip,
2711 unsigned long adr, int len, void *thunk)
2713 struct cfi_private *cfi = map->fldrv_priv;
2714 unsigned long timeo;
2718 mutex_lock(&chip->mutex);
2719 ret = get_chip(map, chip, adr, FL_LOCKING);
2721 mutex_unlock(&chip->mutex);
2725 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2727 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2728 cfi->device_type, NULL);
2729 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2730 cfi->device_type, NULL);
2731 /* PPB entry command */
2732 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2733 cfi->device_type, NULL);
2735 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2736 chip->state = FL_LOCKING;
2737 map_write(map, CMD(0xA0), adr);
2738 map_write(map, CMD(0x00), adr);
2739 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2741 * Unlocking of one specific sector is not supported, so we
2742 * have to unlock all sectors of this device instead
2744 chip->state = FL_UNLOCKING;
2745 map_write(map, CMD(0x80), chip->start);
2746 map_write(map, CMD(0x30), chip->start);
2747 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2748 chip->state = FL_JEDEC_QUERY;
2749 /* Return locked status: 0->locked, 1->unlocked */
2750 ret = !cfi_read_query(map, adr);
2755 * Wait for some time as unlocking of all sectors takes quite long
2757 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2759 if (chip_ready(map, chip, adr))
2762 if (time_after(jiffies, timeo)) {
2763 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2768 UDELAY(map, chip, adr, 1);
2771 /* Exit BC commands */
2772 map_write(map, CMD(0x90), chip->start);
2773 map_write(map, CMD(0x00), chip->start);
2775 chip->state = FL_READY;
2776 put_chip(map, chip, adr);
2777 mutex_unlock(&chip->mutex);
2782 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2785 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2786 DO_XXLOCK_ONEBLOCK_LOCK);
2789 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2792 struct mtd_erase_region_info *regions = mtd->eraseregions;
2793 struct map_info *map = mtd->priv;
2794 struct cfi_private *cfi = map->fldrv_priv;
2795 struct ppb_lock *sect;
2806 * PPB unlocking always unlocks all sectors of the flash chip.
2807 * We need to re-lock all previously locked sectors. So lets
2808 * first check the locking status of all sectors and save
2809 * it for future use.
2812 for (i = 0; i < mtd->numeraseregions; i++)
2813 max_sectors += regions[i].numblocks;
2815 sect = kcalloc(max_sectors, sizeof(struct ppb_lock), GFP_KERNEL);
2820 * This code to walk all sectors is a slightly modified version
2821 * of the cfi_varsize_frob() code.
2831 int size = regions[i].erasesize;
2834 * Only test sectors that shall not be unlocked. The other
2835 * sectors shall be unlocked, so lets keep their locking
2836 * status at "unlocked" (locked=0) for the final re-locking.
2838 if ((offset < ofs) || (offset >= (ofs + len))) {
2839 sect[sectors].chip = &cfi->chips[chipnum];
2840 sect[sectors].adr = adr;
2841 sect[sectors].locked = do_ppb_xxlock(
2842 map, &cfi->chips[chipnum], adr, 0,
2843 DO_XXLOCK_ONEBLOCK_GETLOCK);
2850 if (offset == regions[i].offset + size * regions[i].numblocks)
2853 if (adr >> cfi->chipshift) {
2854 if (offset >= (ofs + len))
2859 if (chipnum >= cfi->numchips)
2864 if (sectors >= max_sectors) {
2865 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2872 /* Now unlock the whole chip */
2873 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2874 DO_XXLOCK_ONEBLOCK_UNLOCK);
2881 * PPB unlocking always unlocks all sectors of the flash chip.
2882 * We need to re-lock all previously locked sectors.
2884 for (i = 0; i < sectors; i++) {
2886 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
2887 DO_XXLOCK_ONEBLOCK_LOCK);
2894 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2897 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2898 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2901 static void cfi_amdstd_sync (struct mtd_info *mtd)
2903 struct map_info *map = mtd->priv;
2904 struct cfi_private *cfi = map->fldrv_priv;
2906 struct flchip *chip;
2908 DECLARE_WAITQUEUE(wait, current);
2910 for (i=0; !ret && i<cfi->numchips; i++) {
2911 chip = &cfi->chips[i];
2914 mutex_lock(&chip->mutex);
2916 switch(chip->state) {
2920 case FL_JEDEC_QUERY:
2921 chip->oldstate = chip->state;
2922 chip->state = FL_SYNCING;
2923 /* No need to wake_up() on this state change -
2924 * as the whole point is that nobody can do anything
2925 * with the chip now anyway.
2929 mutex_unlock(&chip->mutex);
2933 /* Not an idle state */
2934 set_current_state(TASK_UNINTERRUPTIBLE);
2935 add_wait_queue(&chip->wq, &wait);
2937 mutex_unlock(&chip->mutex);
2941 remove_wait_queue(&chip->wq, &wait);
2947 /* Unlock the chips again */
2949 for (i--; i >=0; i--) {
2950 chip = &cfi->chips[i];
2952 mutex_lock(&chip->mutex);
2954 if (chip->state == FL_SYNCING) {
2955 chip->state = chip->oldstate;
2958 mutex_unlock(&chip->mutex);
2963 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2965 struct map_info *map = mtd->priv;
2966 struct cfi_private *cfi = map->fldrv_priv;
2968 struct flchip *chip;
2971 for (i=0; !ret && i<cfi->numchips; i++) {
2972 chip = &cfi->chips[i];
2974 mutex_lock(&chip->mutex);
2976 switch(chip->state) {
2980 case FL_JEDEC_QUERY:
2981 chip->oldstate = chip->state;
2982 chip->state = FL_PM_SUSPENDED;
2983 /* No need to wake_up() on this state change -
2984 * as the whole point is that nobody can do anything
2985 * with the chip now anyway.
2987 case FL_PM_SUSPENDED:
2994 mutex_unlock(&chip->mutex);
2997 /* Unlock the chips again */
3000 for (i--; i >=0; i--) {
3001 chip = &cfi->chips[i];
3003 mutex_lock(&chip->mutex);
3005 if (chip->state == FL_PM_SUSPENDED) {
3006 chip->state = chip->oldstate;
3009 mutex_unlock(&chip->mutex);
3017 static void cfi_amdstd_resume(struct mtd_info *mtd)
3019 struct map_info *map = mtd->priv;
3020 struct cfi_private *cfi = map->fldrv_priv;
3022 struct flchip *chip;
3024 for (i=0; i<cfi->numchips; i++) {
3026 chip = &cfi->chips[i];
3028 mutex_lock(&chip->mutex);
3030 if (chip->state == FL_PM_SUSPENDED) {
3031 chip->state = FL_READY;
3032 map_write(map, CMD(0xF0), chip->start);
3036 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
3038 mutex_unlock(&chip->mutex);
3044 * Ensure that the flash device is put back into read array mode before
3045 * unloading the driver or rebooting. On some systems, rebooting while
3046 * the flash is in query/program/erase mode will prevent the CPU from
3047 * fetching the bootloader code, requiring a hard reset or power cycle.
3049 static int cfi_amdstd_reset(struct mtd_info *mtd)
3051 struct map_info *map = mtd->priv;
3052 struct cfi_private *cfi = map->fldrv_priv;
3054 struct flchip *chip;
3056 for (i = 0; i < cfi->numchips; i++) {
3058 chip = &cfi->chips[i];
3060 mutex_lock(&chip->mutex);
3062 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
3064 map_write(map, CMD(0xF0), chip->start);
3065 chip->state = FL_SHUTDOWN;
3066 put_chip(map, chip, chip->start);
3069 mutex_unlock(&chip->mutex);
3076 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
3079 struct mtd_info *mtd;
3081 mtd = container_of(nb, struct mtd_info, reboot_notifier);
3082 cfi_amdstd_reset(mtd);
3087 static void cfi_amdstd_destroy(struct mtd_info *mtd)
3089 struct map_info *map = mtd->priv;
3090 struct cfi_private *cfi = map->fldrv_priv;
3092 cfi_amdstd_reset(mtd);
3093 unregister_reboot_notifier(&mtd->reboot_notifier);
3094 kfree(cfi->cmdset_priv);
3097 kfree(mtd->eraseregions);
3100 MODULE_LICENSE("GPL");
3101 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
3102 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
3103 MODULE_ALIAS("cfi_cmdset_0006");
3104 MODULE_ALIAS("cfi_cmdset_0701");