2 * drivers/mtd/nand/fsmc_nand.c
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
12 * Based on drivers/mtd/nand/nomadik_nand.c
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/resource.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/nand_ecc.h>
33 #include <linux/platform_device.h>
35 #include <linux/mtd/partitions.h>
37 #include <linux/slab.h>
38 #include <linux/amba/bus.h>
39 #include <mtd/mtd-abi.h>
41 #define FSMC_NAND_BW8 1
42 #define FSMC_NAND_BW16 2
44 #define FSMC_MAX_NOR_BANKS 4
45 #define FSMC_MAX_NAND_BANKS 4
47 #define FSMC_FLASH_WIDTH8 1
48 #define FSMC_FLASH_WIDTH16 2
50 /* fsmc controller registers for NOR flash */
52 /* ctrl register definitions */
53 #define BANK_ENABLE (1 << 0)
54 #define MUXED (1 << 1)
55 #define NOR_DEV (2 << 2)
56 #define WIDTH_8 (0 << 4)
57 #define WIDTH_16 (1 << 4)
58 #define RSTPWRDWN (1 << 6)
59 #define WPROT (1 << 7)
60 #define WRT_ENABLE (1 << 12)
61 #define WAIT_ENB (1 << 13)
64 /* ctrl_tim register definitions */
66 #define FSMC_NOR_BANK_SZ 0x8
67 #define FSMC_NOR_REG_SIZE 0x40
69 #define FSMC_NOR_REG(base, bank, reg) (base + \
70 FSMC_NOR_BANK_SZ * (bank) + \
73 /* fsmc controller registers for NAND flash */
75 /* pc register definitions */
76 #define FSMC_RESET (1 << 0)
77 #define FSMC_WAITON (1 << 1)
78 #define FSMC_ENABLE (1 << 2)
79 #define FSMC_DEVTYPE_NAND (1 << 3)
80 #define FSMC_DEVWID_8 (0 << 4)
81 #define FSMC_DEVWID_16 (1 << 4)
82 #define FSMC_ECCEN (1 << 6)
83 #define FSMC_ECCPLEN_512 (0 << 7)
84 #define FSMC_ECCPLEN_256 (1 << 7)
85 #define FSMC_TCLR_1 (1)
86 #define FSMC_TCLR_SHIFT (9)
87 #define FSMC_TCLR_MASK (0xF)
88 #define FSMC_TAR_1 (1)
89 #define FSMC_TAR_SHIFT (13)
90 #define FSMC_TAR_MASK (0xF)
92 /* sts register definitions */
93 #define FSMC_CODE_RDY (1 << 15)
95 /* comm register definitions */
97 #define FSMC_TSET_SHIFT 0
98 #define FSMC_TSET_MASK 0xFF
99 #define FSMC_TWAIT_6 6
100 #define FSMC_TWAIT_SHIFT 8
101 #define FSMC_TWAIT_MASK 0xFF
102 #define FSMC_THOLD_4 4
103 #define FSMC_THOLD_SHIFT 16
104 #define FSMC_THOLD_MASK 0xFF
105 #define FSMC_THIZ_1 1
106 #define FSMC_THIZ_SHIFT 24
107 #define FSMC_THIZ_MASK 0xFF
113 #define FSMC_NAND_BANK_SZ 0x20
115 #define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
116 (FSMC_NAND_BANK_SZ * (bank)) + \
119 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
121 struct fsmc_nand_timings {
136 * fsmc_nand_platform_data - platform specific NAND controller config
137 * @nand_timings: timing setup for the physical NAND interface
138 * @partitions: partition table for the platform, use a default fallback
140 * @nr_partitions: the number of partitions in the previous entry
141 * @options: different options for the driver
143 * @bank: default bank
144 * @select_bank: callback to select a certain bank, this is
145 * platform-specific. If the controller only supports one bank
146 * this may be set to NULL
148 struct fsmc_nand_platform_data {
149 struct fsmc_nand_timings *nand_timings;
150 struct mtd_partition *partitions;
151 unsigned int nr_partitions;
152 unsigned int options;
156 enum access_mode mode;
158 void (*select_bank)(uint32_t bank, uint32_t busw);
160 /* priv structures for dma accesses */
162 void *write_dma_priv;
165 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
166 struct mtd_oob_region *oobregion)
168 struct nand_chip *chip = mtd_to_nand(mtd);
170 if (section >= chip->ecc.steps)
173 oobregion->offset = (section * 16) + 2;
174 oobregion->length = 3;
179 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
180 struct mtd_oob_region *oobregion)
182 struct nand_chip *chip = mtd_to_nand(mtd);
184 if (section >= chip->ecc.steps)
187 oobregion->offset = (section * 16) + 8;
189 if (section < chip->ecc.steps - 1)
190 oobregion->length = 8;
192 oobregion->length = mtd->oobsize - oobregion->offset;
197 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
198 .ecc = fsmc_ecc1_ooblayout_ecc,
199 .free = fsmc_ecc1_ooblayout_free,
203 * ECC placement definitions in oobfree type format.
204 * There are 13 bytes of ecc for every 512 byte block and it has to be read
205 * consecutively and immediately after the 512 byte data block for hardware to
206 * generate the error bit offsets in 512 byte data.
208 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
209 struct mtd_oob_region *oobregion)
211 struct nand_chip *chip = mtd_to_nand(mtd);
213 if (section >= chip->ecc.steps)
216 oobregion->length = chip->ecc.bytes;
218 if (!section && mtd->writesize <= 512)
219 oobregion->offset = 0;
221 oobregion->offset = (section * 16) + 2;
226 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
227 struct mtd_oob_region *oobregion)
229 struct nand_chip *chip = mtd_to_nand(mtd);
231 if (section >= chip->ecc.steps)
234 oobregion->offset = (section * 16) + 15;
236 if (section < chip->ecc.steps - 1)
237 oobregion->length = 3;
239 oobregion->length = mtd->oobsize - oobregion->offset;
244 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
245 .ecc = fsmc_ecc4_ooblayout_ecc,
246 .free = fsmc_ecc4_ooblayout_free,
250 * struct fsmc_nand_data - structure for FSMC NAND device state
252 * @pid: Part ID on the AMBA PrimeCell format
253 * @mtd: MTD info for a NAND flash.
254 * @nand: Chip related info for a NAND flash.
255 * @partitions: Partition info for a NAND Flash.
256 * @nr_partitions: Total number of partition of a NAND flash.
258 * @bank: Bank number for probed device.
259 * @clk: Clock structure for FSMC.
261 * @read_dma_chan: DMA channel for read access
262 * @write_dma_chan: DMA channel for write access to NAND
263 * @dma_access_complete: Completion structure
265 * @data_pa: NAND Physical port for Data.
266 * @data_va: NAND port for Data.
267 * @cmd_va: NAND port for Command.
268 * @addr_va: NAND port for Address.
269 * @regs_va: FSMC regs base address.
271 struct fsmc_nand_data {
273 struct nand_chip nand;
274 struct mtd_partition *partitions;
275 unsigned int nr_partitions;
279 enum access_mode mode;
282 /* DMA related objects */
283 struct dma_chan *read_dma_chan;
284 struct dma_chan *write_dma_chan;
285 struct completion dma_access_complete;
287 struct fsmc_nand_timings *dev_timings;
290 void __iomem *data_va;
291 void __iomem *cmd_va;
292 void __iomem *addr_va;
293 void __iomem *regs_va;
295 void (*select_chip)(uint32_t bank, uint32_t busw);
298 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
300 return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
303 /* Assert CS signal based on chipnr */
304 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
306 struct nand_chip *chip = mtd_to_nand(mtd);
307 struct fsmc_nand_data *host;
309 host = mtd_to_fsmc(mtd);
313 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
319 if (host->select_chip)
320 host->select_chip(chipnr,
321 chip->options & NAND_BUSWIDTH_16);
325 dev_err(host->dev, "unsupported chip-select %d\n", chipnr);
330 * fsmc_cmd_ctrl - For facilitaing Hardware access
331 * This routine allows hardware specific access to control-lines(ALE,CLE)
333 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
335 struct nand_chip *this = mtd_to_nand(mtd);
336 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
337 void __iomem *regs = host->regs_va;
338 unsigned int bank = host->bank;
340 if (ctrl & NAND_CTRL_CHANGE) {
343 if (ctrl & NAND_CLE) {
344 this->IO_ADDR_R = host->cmd_va;
345 this->IO_ADDR_W = host->cmd_va;
346 } else if (ctrl & NAND_ALE) {
347 this->IO_ADDR_R = host->addr_va;
348 this->IO_ADDR_W = host->addr_va;
350 this->IO_ADDR_R = host->data_va;
351 this->IO_ADDR_W = host->data_va;
354 pc = readl(FSMC_NAND_REG(regs, bank, PC));
359 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
364 if (cmd != NAND_CMD_NONE)
365 writeb_relaxed(cmd, this->IO_ADDR_W);
369 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
371 * This routine initializes timing parameters related to NAND memory access in
374 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
375 uint32_t busw, struct fsmc_nand_timings *timings)
377 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
378 uint32_t tclr, tar, thiz, thold, twait, tset;
379 struct fsmc_nand_timings *tims;
380 struct fsmc_nand_timings default_timings = {
384 .thold = FSMC_THOLD_4,
385 .twait = FSMC_TWAIT_6,
392 tims = &default_timings;
394 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
395 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
396 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
397 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
398 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
399 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
402 writel_relaxed(value | FSMC_DEVWID_16,
403 FSMC_NAND_REG(regs, bank, PC));
405 writel_relaxed(value | FSMC_DEVWID_8,
406 FSMC_NAND_REG(regs, bank, PC));
408 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
409 FSMC_NAND_REG(regs, bank, PC));
410 writel_relaxed(thiz | thold | twait | tset,
411 FSMC_NAND_REG(regs, bank, COMM));
412 writel_relaxed(thiz | thold | twait | tset,
413 FSMC_NAND_REG(regs, bank, ATTRIB));
417 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
419 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
421 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
422 void __iomem *regs = host->regs_va;
423 uint32_t bank = host->bank;
425 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
426 FSMC_NAND_REG(regs, bank, PC));
427 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
428 FSMC_NAND_REG(regs, bank, PC));
429 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
430 FSMC_NAND_REG(regs, bank, PC));
434 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
435 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
438 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
441 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
442 void __iomem *regs = host->regs_va;
443 uint32_t bank = host->bank;
445 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
448 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
452 } while (!time_after_eq(jiffies, deadline));
454 if (time_after_eq(jiffies, deadline)) {
455 dev_err(host->dev, "calculate ecc timed out\n");
459 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
460 ecc[0] = (uint8_t) (ecc_tmp >> 0);
461 ecc[1] = (uint8_t) (ecc_tmp >> 8);
462 ecc[2] = (uint8_t) (ecc_tmp >> 16);
463 ecc[3] = (uint8_t) (ecc_tmp >> 24);
465 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
466 ecc[4] = (uint8_t) (ecc_tmp >> 0);
467 ecc[5] = (uint8_t) (ecc_tmp >> 8);
468 ecc[6] = (uint8_t) (ecc_tmp >> 16);
469 ecc[7] = (uint8_t) (ecc_tmp >> 24);
471 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
472 ecc[8] = (uint8_t) (ecc_tmp >> 0);
473 ecc[9] = (uint8_t) (ecc_tmp >> 8);
474 ecc[10] = (uint8_t) (ecc_tmp >> 16);
475 ecc[11] = (uint8_t) (ecc_tmp >> 24);
477 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
478 ecc[12] = (uint8_t) (ecc_tmp >> 16);
484 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
485 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
488 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
491 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
492 void __iomem *regs = host->regs_va;
493 uint32_t bank = host->bank;
496 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
497 ecc[0] = (uint8_t) (ecc_tmp >> 0);
498 ecc[1] = (uint8_t) (ecc_tmp >> 8);
499 ecc[2] = (uint8_t) (ecc_tmp >> 16);
504 /* Count the number of 0's in buff upto a max of max_bits */
505 static int count_written_bits(uint8_t *buff, int size, int max_bits)
507 int k, written_bits = 0;
509 for (k = 0; k < size; k++) {
510 written_bits += hweight8(~buff[k]);
511 if (written_bits > max_bits)
518 static void dma_complete(void *param)
520 struct fsmc_nand_data *host = param;
522 complete(&host->dma_access_complete);
525 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
526 enum dma_data_direction direction)
528 struct dma_chan *chan;
529 struct dma_device *dma_dev;
530 struct dma_async_tx_descriptor *tx;
531 dma_addr_t dma_dst, dma_src, dma_addr;
533 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
535 unsigned long time_left;
537 if (direction == DMA_TO_DEVICE)
538 chan = host->write_dma_chan;
539 else if (direction == DMA_FROM_DEVICE)
540 chan = host->read_dma_chan;
544 dma_dev = chan->device;
545 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
547 if (direction == DMA_TO_DEVICE) {
549 dma_dst = host->data_pa;
551 dma_src = host->data_pa;
555 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
558 dev_err(host->dev, "device_prep_dma_memcpy error\n");
563 tx->callback = dma_complete;
564 tx->callback_param = host;
565 cookie = tx->tx_submit(tx);
567 ret = dma_submit_error(cookie);
569 dev_err(host->dev, "dma_submit_error %d\n", cookie);
573 dma_async_issue_pending(chan);
576 wait_for_completion_timeout(&host->dma_access_complete,
577 msecs_to_jiffies(3000));
578 if (time_left == 0) {
579 dmaengine_terminate_all(chan);
580 dev_err(host->dev, "wait_for_completion_timeout\n");
588 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
594 * fsmc_write_buf - write buffer to chip
595 * @mtd: MTD device structure
597 * @len: number of bytes to write
599 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
602 struct nand_chip *chip = mtd_to_nand(mtd);
604 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
605 IS_ALIGNED(len, sizeof(uint32_t))) {
606 uint32_t *p = (uint32_t *)buf;
608 for (i = 0; i < len; i++)
609 writel_relaxed(p[i], chip->IO_ADDR_W);
611 for (i = 0; i < len; i++)
612 writeb_relaxed(buf[i], chip->IO_ADDR_W);
617 * fsmc_read_buf - read chip data into buffer
618 * @mtd: MTD device structure
619 * @buf: buffer to store date
620 * @len: number of bytes to read
622 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
625 struct nand_chip *chip = mtd_to_nand(mtd);
627 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
628 IS_ALIGNED(len, sizeof(uint32_t))) {
629 uint32_t *p = (uint32_t *)buf;
631 for (i = 0; i < len; i++)
632 p[i] = readl_relaxed(chip->IO_ADDR_R);
634 for (i = 0; i < len; i++)
635 buf[i] = readb_relaxed(chip->IO_ADDR_R);
640 * fsmc_read_buf_dma - read chip data into buffer
641 * @mtd: MTD device structure
642 * @buf: buffer to store date
643 * @len: number of bytes to read
645 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
647 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
649 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
653 * fsmc_write_buf_dma - write buffer to chip
654 * @mtd: MTD device structure
656 * @len: number of bytes to write
658 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
661 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
663 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
667 * fsmc_read_page_hwecc
668 * @mtd: mtd info structure
669 * @chip: nand chip info structure
670 * @buf: buffer to store read data
671 * @oob_required: caller expects OOB data read to chip->oob_poi
672 * @page: page number to read
674 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
675 * performed in a strict sequence as follows:
676 * data(512 byte) -> ecc(13 byte)
677 * After this read, fsmc hardware generates and reports error data bits(up to a
680 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
681 uint8_t *buf, int oob_required, int page)
683 int i, j, s, stat, eccsize = chip->ecc.size;
684 int eccbytes = chip->ecc.bytes;
685 int eccsteps = chip->ecc.steps;
687 uint8_t *ecc_calc = chip->buffers->ecccalc;
688 uint8_t *ecc_code = chip->buffers->ecccode;
689 int off, len, group = 0;
691 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
692 * end up reading 14 bytes (7 words) from oob. The local array is
693 * to maintain word alignment
696 uint8_t *oob = (uint8_t *)&ecc_oob[0];
697 unsigned int max_bitflips = 0;
699 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
700 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
701 chip->ecc.hwctl(mtd, NAND_ECC_READ);
702 chip->read_buf(mtd, p, eccsize);
704 for (j = 0; j < eccbytes;) {
705 struct mtd_oob_region oobregion;
708 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
712 off = oobregion.offset;
713 len = oobregion.length;
716 * length is intentionally kept a higher multiple of 2
717 * to read at least 13 bytes even in case of 16 bit NAND
720 if (chip->options & NAND_BUSWIDTH_16)
721 len = roundup(len, 2);
723 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
724 chip->read_buf(mtd, oob + j, len);
728 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
729 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
731 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
733 mtd->ecc_stats.failed++;
735 mtd->ecc_stats.corrected += stat;
736 max_bitflips = max_t(unsigned int, max_bitflips, stat);
744 * fsmc_bch8_correct_data
745 * @mtd: mtd info structure
746 * @dat: buffer of read data
747 * @read_ecc: ecc read from device spare area
748 * @calc_ecc: ecc calculated from read data
750 * calc_ecc is a 104 bit information containing maximum of 8 error
751 * offset informations of 13 bits each in 512 bytes of read data.
753 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
754 uint8_t *read_ecc, uint8_t *calc_ecc)
756 struct nand_chip *chip = mtd_to_nand(mtd);
757 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
758 void __iomem *regs = host->regs_va;
759 unsigned int bank = host->bank;
762 uint32_t ecc1, ecc2, ecc3, ecc4;
764 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
766 /* no bit flipping */
767 if (likely(num_err == 0))
770 /* too many errors */
771 if (unlikely(num_err > 8)) {
773 * This is a temporary erase check. A newly erased page read
774 * would result in an ecc error because the oob data is also
775 * erased to FF and the calculated ecc for an FF data is not
777 * This is a workaround to skip performing correction in case
781 * For every page, each bit written as 0 is counted until these
782 * number of bits are greater than 8 (the maximum correction
783 * capability of FSMC for each 512 + 13 bytes)
786 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
787 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
789 if ((bits_ecc + bits_data) <= 8) {
791 memset(dat, 0xff, chip->ecc.size);
799 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
800 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
802 * calc_ecc is a 104 bit information containing maximum of 8 error
803 * offset informations of 13 bits each. calc_ecc is copied into a
804 * uint64_t array and error offset indexes are populated in err_idx
807 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
808 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
809 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
810 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
812 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
813 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
814 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
815 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
816 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
817 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
818 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
819 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
823 change_bit(0, (unsigned long *)&err_idx[i]);
824 change_bit(1, (unsigned long *)&err_idx[i]);
826 if (err_idx[i] < chip->ecc.size * 8) {
827 change_bit(err_idx[i], (unsigned long *)dat);
834 static bool filter(struct dma_chan *chan, void *slave)
836 chan->private = slave;
840 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
841 struct device_node *np)
843 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
847 /* Set default NAND width to 8 bits */
849 if (!of_property_read_u32(np, "bank-width", &val)) {
852 } else if (val != 1) {
853 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
857 if (of_get_property(np, "nand-skip-bbtscan", NULL))
858 pdata->options = NAND_SKIP_BBTSCAN;
860 pdata->nand_timings = devm_kzalloc(&pdev->dev,
861 sizeof(*pdata->nand_timings), GFP_KERNEL);
862 if (!pdata->nand_timings)
864 ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
865 sizeof(*pdata->nand_timings));
867 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
868 pdata->nand_timings = NULL;
871 /* Set default NAND bank to 0 */
873 if (!of_property_read_u32(np, "bank", &val)) {
875 dev_err(&pdev->dev, "invalid bank %u\n", val);
884 * fsmc_nand_probe - Probe function
885 * @pdev: platform device structure
887 static int __init fsmc_nand_probe(struct platform_device *pdev)
889 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
890 struct device_node __maybe_unused *np = pdev->dev.of_node;
891 struct fsmc_nand_data *host;
892 struct mtd_info *mtd;
893 struct nand_chip *nand;
894 struct resource *res;
900 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
904 pdev->dev.platform_data = pdata;
905 ret = fsmc_nand_probe_config_dt(pdev, np);
907 dev_err(&pdev->dev, "no platform data\n");
911 /* Allocate memory for the device structure (and zero it) */
912 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
916 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
917 host->data_va = devm_ioremap_resource(&pdev->dev, res);
918 if (IS_ERR(host->data_va))
919 return PTR_ERR(host->data_va);
921 host->data_pa = (dma_addr_t)res->start;
923 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
924 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
925 if (IS_ERR(host->addr_va))
926 return PTR_ERR(host->addr_va);
928 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
929 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
930 if (IS_ERR(host->cmd_va))
931 return PTR_ERR(host->cmd_va);
933 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
934 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
935 if (IS_ERR(host->regs_va))
936 return PTR_ERR(host->regs_va);
938 host->clk = clk_get(&pdev->dev, NULL);
939 if (IS_ERR(host->clk)) {
940 dev_err(&pdev->dev, "failed to fetch block clock\n");
941 return PTR_ERR(host->clk);
944 ret = clk_prepare_enable(host->clk);
946 goto err_clk_prepare_enable;
949 * This device ID is actually a common AMBA ID as used on the
950 * AMBA PrimeCell bus. However it is not a PrimeCell.
952 for (pid = 0, i = 0; i < 4; i++)
953 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
955 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
956 "revision %02x, config %02x\n",
957 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
958 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
960 host->bank = pdata->bank;
961 host->select_chip = pdata->select_bank;
962 host->partitions = pdata->partitions;
963 host->nr_partitions = pdata->nr_partitions;
964 host->dev = &pdev->dev;
965 host->dev_timings = pdata->nand_timings;
966 host->mode = pdata->mode;
968 if (host->mode == USE_DMA_ACCESS)
969 init_completion(&host->dma_access_complete);
971 /* Link all private pointers */
972 mtd = nand_to_mtd(&host->nand);
974 nand_set_controller_data(nand, host);
975 nand_set_flash_node(nand, np);
977 mtd->dev.parent = &pdev->dev;
978 nand->IO_ADDR_R = host->data_va;
979 nand->IO_ADDR_W = host->data_va;
980 nand->cmd_ctrl = fsmc_cmd_ctrl;
981 nand->chip_delay = 30;
984 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
985 * can overwrite this value if the DT provides a different value.
987 nand->ecc.mode = NAND_ECC_HW;
988 nand->ecc.hwctl = fsmc_enable_hwecc;
989 nand->ecc.size = 512;
990 nand->options = pdata->options;
991 nand->select_chip = fsmc_select_chip;
992 nand->badblockbits = 7;
993 nand_set_flash_node(nand, np);
995 if (pdata->width == FSMC_NAND_BW16)
996 nand->options |= NAND_BUSWIDTH_16;
998 switch (host->mode) {
1001 dma_cap_set(DMA_MEMCPY, mask);
1002 host->read_dma_chan = dma_request_channel(mask, filter,
1003 pdata->read_dma_priv);
1004 if (!host->read_dma_chan) {
1005 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1006 goto err_req_read_chnl;
1008 host->write_dma_chan = dma_request_channel(mask, filter,
1009 pdata->write_dma_priv);
1010 if (!host->write_dma_chan) {
1011 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1012 goto err_req_write_chnl;
1014 nand->read_buf = fsmc_read_buf_dma;
1015 nand->write_buf = fsmc_write_buf_dma;
1019 case USE_WORD_ACCESS:
1020 nand->read_buf = fsmc_read_buf;
1021 nand->write_buf = fsmc_write_buf;
1025 fsmc_nand_setup(host->regs_va, host->bank,
1026 nand->options & NAND_BUSWIDTH_16,
1029 if (AMBA_REV_BITS(host->pid) >= 8) {
1030 nand->ecc.read_page = fsmc_read_page_hwecc;
1031 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1032 nand->ecc.correct = fsmc_bch8_correct_data;
1033 nand->ecc.bytes = 13;
1034 nand->ecc.strength = 8;
1038 * Scan to find existence of the device
1040 ret = nand_scan_ident(mtd, 1, NULL);
1042 dev_err(&pdev->dev, "No NAND Device found!\n");
1043 goto err_scan_ident;
1046 if (AMBA_REV_BITS(host->pid) >= 8) {
1047 switch (mtd->oobsize) {
1055 dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1061 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1063 switch (nand->ecc.mode) {
1065 dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1066 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1067 nand->ecc.correct = nand_correct_data;
1068 nand->ecc.bytes = 3;
1069 nand->ecc.strength = 1;
1073 if (nand->ecc.algo == NAND_ECC_BCH) {
1074 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1079 dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1084 * Don't set layout for BCH4 SW ECC. This will be
1085 * generated later in nand_bch_init() later.
1087 if (nand->ecc.mode == NAND_ECC_HW) {
1088 switch (mtd->oobsize) {
1092 mtd_set_ooblayout(mtd,
1093 &fsmc_ecc1_ooblayout_ops);
1096 dev_warn(&pdev->dev,
1097 "No oob scheme defined for oobsize %d\n",
1105 /* Second stage of scan to fill MTD data-structures */
1106 ret = nand_scan_tail(mtd);
1111 * The partition information can is accessed by (in the same precedence)
1113 * command line through Bootloader,
1115 * default partition information present in driver.
1118 * Check for partition info passed
1121 ret = mtd_device_register(mtd, host->partitions, host->nr_partitions);
1125 platform_set_drvdata(pdev, host);
1126 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1131 if (host->mode == USE_DMA_ACCESS)
1132 dma_release_channel(host->write_dma_chan);
1134 if (host->mode == USE_DMA_ACCESS)
1135 dma_release_channel(host->read_dma_chan);
1137 clk_disable_unprepare(host->clk);
1138 err_clk_prepare_enable:
1146 static int fsmc_nand_remove(struct platform_device *pdev)
1148 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1151 nand_release(nand_to_mtd(&host->nand));
1153 if (host->mode == USE_DMA_ACCESS) {
1154 dma_release_channel(host->write_dma_chan);
1155 dma_release_channel(host->read_dma_chan);
1157 clk_disable_unprepare(host->clk);
1164 #ifdef CONFIG_PM_SLEEP
1165 static int fsmc_nand_suspend(struct device *dev)
1167 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1169 clk_disable_unprepare(host->clk);
1173 static int fsmc_nand_resume(struct device *dev)
1175 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1177 clk_prepare_enable(host->clk);
1178 fsmc_nand_setup(host->regs_va, host->bank,
1179 host->nand.options & NAND_BUSWIDTH_16,
1186 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1189 static const struct of_device_id fsmc_nand_id_table[] = {
1190 { .compatible = "st,spear600-fsmc-nand" },
1191 { .compatible = "stericsson,fsmc-nand" },
1194 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1197 static struct platform_driver fsmc_nand_driver = {
1198 .remove = fsmc_nand_remove,
1200 .name = "fsmc-nand",
1201 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1202 .pm = &fsmc_nand_pm_ops,
1206 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1208 MODULE_LICENSE("GPL");
1209 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1210 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");