2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
37 #define DRIVER_NAME "mxc_nand"
39 /* Addresses for NFC registers */
40 #define NFC_BUF_SIZE 0xE00
41 #define NFC_BUF_ADDR 0xE04
42 #define NFC_FLASH_ADDR 0xE06
43 #define NFC_FLASH_CMD 0xE08
44 #define NFC_CONFIG 0xE0A
45 #define NFC_ECC_STATUS_RESULT 0xE0C
46 #define NFC_RSLTMAIN_AREA 0xE0E
47 #define NFC_RSLTSPARE_AREA 0xE10
48 #define NFC_WRPROT 0xE12
49 #define NFC_UNLOCKSTART_BLKADDR 0xE14
50 #define NFC_UNLOCKEND_BLKADDR 0xE16
51 #define NFC_NF_WRPRST 0xE18
52 #define NFC_CONFIG1 0xE1A
53 #define NFC_CONFIG2 0xE1C
55 /* Addresses for NFC RAM BUFFER Main area 0 */
56 #define MAIN_AREA0 0x000
57 #define MAIN_AREA1 0x200
58 #define MAIN_AREA2 0x400
59 #define MAIN_AREA3 0x600
61 /* Addresses for NFC SPARE BUFFER Spare area 0 */
62 #define SPARE_AREA0 0x800
63 #define SPARE_AREA1 0x810
64 #define SPARE_AREA2 0x820
65 #define SPARE_AREA3 0x830
67 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
68 * for Command operation */
71 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
72 * for Address operation */
75 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
76 * for Input operation */
79 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
80 * for Data Output operation */
81 #define NFC_OUTPUT 0x8
83 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
84 * for Read ID operation */
87 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
88 * for Read Status operation */
89 #define NFC_STATUS 0x20
91 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
93 #define NFC_INT 0x8000
95 #define NFC_SP_EN (1 << 2)
96 #define NFC_ECC_EN (1 << 3)
97 #define NFC_INT_MSK (1 << 4)
98 #define NFC_BIG (1 << 5)
99 #define NFC_RST (1 << 6)
100 #define NFC_CE (1 << 7)
101 #define NFC_ONE_CYCLE (1 << 8)
103 struct mxc_nand_host {
105 struct nand_chip nand;
106 struct mtd_partition *parts;
116 wait_queue_head_t irq_waitq;
119 unsigned int buf_start;
123 /* Define delays in microsec for NAND device operations */
124 #define TROP_US_DELAY 2000
126 /* OOB placement block for use with hardware ecc generation */
127 static struct nand_ecclayout nand_hw_eccoob_smallpage = {
129 .eccpos = {6, 7, 8, 9, 10},
130 .oobfree = {{0, 5}, {12, 4}, }
133 static struct nand_ecclayout nand_hw_eccoob_largepage = {
135 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
136 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
137 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
140 #ifdef CONFIG_MTD_PARTITIONS
141 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
144 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
146 struct mxc_nand_host *host = dev_id;
150 tmp = readw(host->regs + NFC_CONFIG1);
151 tmp |= NFC_INT_MSK; /* Disable interrupt */
152 writew(tmp, host->regs + NFC_CONFIG1);
154 wake_up(&host->irq_waitq);
159 /* This function polls the NANDFC to wait for the basic operation to
160 * complete by checking the INT bit of config2 register.
162 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
168 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
170 tmp = readw(host->regs + NFC_CONFIG1);
171 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
172 writew(tmp, host->regs + NFC_CONFIG1);
174 wait_event(host->irq_waitq,
175 readw(host->regs + NFC_CONFIG2) & NFC_INT);
177 tmp = readw(host->regs + NFC_CONFIG2);
179 writew(tmp, host->regs + NFC_CONFIG2);
182 while (max_retries-- > 0) {
183 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
184 tmp = readw(host->regs + NFC_CONFIG2);
186 writew(tmp, host->regs + NFC_CONFIG2);
192 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
197 /* This function issues the specified command to the NAND device and
198 * waits for completion. */
199 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
201 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
203 writew(cmd, host->regs + NFC_FLASH_CMD);
204 writew(NFC_CMD, host->regs + NFC_CONFIG2);
206 /* Wait for operation to complete */
207 wait_op_done(host, TROP_US_DELAY, useirq);
210 /* This function sends an address (or partial address) to the
211 * NAND device. The address is used to select the source/destination for
213 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
215 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
217 writew(addr, host->regs + NFC_FLASH_ADDR);
218 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
220 /* Wait for operation to complete */
221 wait_op_done(host, TROP_US_DELAY, islast);
224 static void send_page(struct mxc_nand_host *host, unsigned int ops)
228 if (host->pagesize_2k)
233 for (i = 0; i < bufs; i++) {
235 /* NANDFC buffer 0 is used for page read/write */
236 writew(i, host->regs + NFC_BUF_ADDR);
238 writew(ops, host->regs + NFC_CONFIG2);
240 /* Wait for operation to complete */
241 wait_op_done(host, TROP_US_DELAY, true);
245 /* Request the NANDFC to perform a read of the NAND device ID. */
246 static void send_read_id(struct mxc_nand_host *host)
248 struct nand_chip *this = &host->nand;
251 /* NANDFC buffer 0 is used for device ID output */
252 writew(0x0, host->regs + NFC_BUF_ADDR);
254 /* Read ID into main buffer */
255 tmp = readw(host->regs + NFC_CONFIG1);
257 writew(tmp, host->regs + NFC_CONFIG1);
259 writew(NFC_ID, host->regs + NFC_CONFIG2);
261 /* Wait for operation to complete */
262 wait_op_done(host, TROP_US_DELAY, true);
264 if (this->options & NAND_BUSWIDTH_16) {
265 void __iomem *main_buf = host->regs + MAIN_AREA0;
266 /* compress the ID info */
267 writeb(readb(main_buf + 2), main_buf + 1);
268 writeb(readb(main_buf + 4), main_buf + 2);
269 writeb(readb(main_buf + 6), main_buf + 3);
270 writeb(readb(main_buf + 8), main_buf + 4);
271 writeb(readb(main_buf + 10), main_buf + 5);
273 memcpy(host->data_buf, host->regs + MAIN_AREA0, 16);
276 /* This function requests the NANDFC to perform a read of the
277 * NAND device status and returns the current status. */
278 static uint16_t get_dev_status(struct mxc_nand_host *host)
280 void __iomem *main_buf = host->regs + MAIN_AREA1;
283 /* Issue status request to NAND device */
285 /* store the main area1 first word, later do recovery */
286 store = readl(main_buf);
287 /* NANDFC buffer 1 is used for device status to prevent
288 * corruption of read/write buffer on status requests. */
289 writew(1, host->regs + NFC_BUF_ADDR);
291 /* Read status into main buffer */
292 tmp = readw(host->regs + NFC_CONFIG1);
294 writew(tmp, host->regs + NFC_CONFIG1);
296 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
298 /* Wait for operation to complete */
299 wait_op_done(host, TROP_US_DELAY, true);
301 /* Status is placed in first word of main buffer */
302 /* get status, then recovery area 1 data */
303 ret = readw(main_buf);
304 writel(store, main_buf);
309 /* This functions is used by upper layer to checks if device is ready */
310 static int mxc_nand_dev_ready(struct mtd_info *mtd)
313 * NFC handles R/B internally. Therefore, this function
314 * always returns status as ready.
319 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
322 * If HW ECC is enabled, we turn it on during init. There is
323 * no need to enable again here.
327 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
328 u_char *read_ecc, u_char *calc_ecc)
330 struct nand_chip *nand_chip = mtd->priv;
331 struct mxc_nand_host *host = nand_chip->priv;
334 * 1-Bit errors are automatically corrected in HW. No need for
335 * additional correction. 2-Bit errors cannot be corrected by
336 * HW ECC, so we need to return failure
338 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
340 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
341 DEBUG(MTD_DEBUG_LEVEL0,
342 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
349 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
355 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
357 struct nand_chip *nand_chip = mtd->priv;
358 struct mxc_nand_host *host = nand_chip->priv;
361 /* Check for status request */
362 if (host->status_request)
363 return get_dev_status(host) & 0xFF;
365 ret = *(uint8_t *)(host->data_buf + host->buf_start);
371 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
373 struct nand_chip *nand_chip = mtd->priv;
374 struct mxc_nand_host *host = nand_chip->priv;
377 ret = *(uint16_t *)(host->data_buf + host->buf_start);
378 host->buf_start += 2;
383 /* Write data of length len to buffer buf. The data to be
384 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
385 * Operation by the NFC, the data is written to NAND Flash */
386 static void mxc_nand_write_buf(struct mtd_info *mtd,
387 const u_char *buf, int len)
389 struct nand_chip *nand_chip = mtd->priv;
390 struct mxc_nand_host *host = nand_chip->priv;
391 u16 col = host->buf_start;
392 int n = mtd->oobsize + mtd->writesize - col;
396 memcpy(host->data_buf + col, buf, n);
398 host->buf_start += n;
401 /* Read the data buffer from the NAND Flash. To read the data from NAND
402 * Flash first the data output cycle is initiated by the NFC, which copies
403 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
405 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
407 struct nand_chip *nand_chip = mtd->priv;
408 struct mxc_nand_host *host = nand_chip->priv;
409 u16 col = host->buf_start;
410 int n = mtd->oobsize + mtd->writesize - col;
414 memcpy(buf, host->data_buf + col, len);
416 host->buf_start += len;
419 /* Used by the upper layer to verify the data in NAND Flash
420 * with the data in the buf. */
421 static int mxc_nand_verify_buf(struct mtd_info *mtd,
422 const u_char *buf, int len)
427 /* This function is used by upper layer for select and
428 * deselect of the NAND chip */
429 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
431 struct nand_chip *nand_chip = mtd->priv;
432 struct mxc_nand_host *host = nand_chip->priv;
436 /* Disable the NFC clock */
438 clk_disable(host->clk);
443 /* Enable the NFC clock */
444 if (!host->clk_act) {
445 clk_enable(host->clk);
456 * Function to transfer data to/from spare area.
458 static void copy_spare(struct mtd_info *mtd, bool bfrom)
460 struct nand_chip *this = mtd->priv;
461 struct mxc_nand_host *host = this->priv;
463 u16 n = mtd->writesize >> 9;
464 u8 *d = host->data_buf + mtd->writesize;
465 u8 *s = host->regs + SPARE_AREA0;
466 u16 t = host->spare_len;
468 j = (mtd->oobsize / n >> 1) << 1;
471 for (i = 0; i < n - 1; i++)
472 memcpy(d + i * j, s + i * t, j);
474 /* the last section */
475 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
477 for (i = 0; i < n - 1; i++)
478 memcpy(&s[i * t], &d[i * j], j);
480 /* the last section */
481 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
485 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
487 struct nand_chip *nand_chip = mtd->priv;
488 struct mxc_nand_host *host = nand_chip->priv;
490 /* Write out column address, if necessary */
493 * MXC NANDFC can only perform full page+spare or
494 * spare-only read/write. When the upper layers
495 * layers perform a read/write buf operation,
496 * we will used the saved column adress to index into
499 send_addr(host, 0, page_addr == -1);
500 if (host->pagesize_2k)
501 /* another col addr cycle for 2k page */
502 send_addr(host, 0, false);
505 /* Write out page address, if necessary */
506 if (page_addr != -1) {
507 /* paddr_0 - p_addr_7 */
508 send_addr(host, (page_addr & 0xff), false);
510 if (host->pagesize_2k) {
511 if (mtd->size >= 0x10000000) {
512 /* paddr_8 - paddr_15 */
513 send_addr(host, (page_addr >> 8) & 0xff, false);
514 send_addr(host, (page_addr >> 16) & 0xff, true);
516 /* paddr_8 - paddr_15 */
517 send_addr(host, (page_addr >> 8) & 0xff, true);
519 /* One more address cycle for higher density devices */
520 if (mtd->size >= 0x4000000) {
521 /* paddr_8 - paddr_15 */
522 send_addr(host, (page_addr >> 8) & 0xff, false);
523 send_addr(host, (page_addr >> 16) & 0xff, true);
525 /* paddr_8 - paddr_15 */
526 send_addr(host, (page_addr >> 8) & 0xff, true);
531 /* Used by the upper layer to write command to NAND Flash for
532 * different operations to be carried out on NAND Flash */
533 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
534 int column, int page_addr)
536 struct nand_chip *nand_chip = mtd->priv;
537 struct mxc_nand_host *host = nand_chip->priv;
539 DEBUG(MTD_DEBUG_LEVEL3,
540 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
541 command, column, page_addr);
543 /* Reset command state information */
544 host->status_request = false;
546 /* Command pre-processing step */
549 case NAND_CMD_STATUS:
551 host->status_request = true;
553 send_cmd(host, command, true);
554 mxc_do_addr_cycle(mtd, column, page_addr);
558 case NAND_CMD_READOOB:
559 if (command == NAND_CMD_READ0)
560 host->buf_start = column;
562 host->buf_start = column + mtd->writesize;
564 if (host->pagesize_2k)
565 command = NAND_CMD_READ0; /* only READ0 is valid */
567 send_cmd(host, command, false);
568 mxc_do_addr_cycle(mtd, column, page_addr);
570 if (host->pagesize_2k)
571 send_cmd(host, NAND_CMD_READSTART, true);
573 send_page(host, NFC_OUTPUT);
575 memcpy(host->data_buf, host->regs + MAIN_AREA0, mtd->writesize);
576 copy_spare(mtd, true);
580 if (column >= mtd->writesize) {
582 * FIXME: before send SEQIN command for write OOB,
583 * We must read one page out.
584 * For K9F1GXX has no READ1 command to set current HW
585 * pointer to spare area, we must write the whole page
586 * including OOB together.
588 if (host->pagesize_2k)
589 /* call ourself to read a page */
590 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
593 host->buf_start = column;
595 /* Set program pointer to spare region */
596 if (!host->pagesize_2k)
597 send_cmd(host, NAND_CMD_READOOB, false);
599 host->buf_start = column;
601 /* Set program pointer to page start */
602 if (!host->pagesize_2k)
603 send_cmd(host, NAND_CMD_READ0, false);
606 send_cmd(host, command, false);
607 mxc_do_addr_cycle(mtd, column, page_addr);
610 case NAND_CMD_PAGEPROG:
611 memcpy(host->regs + MAIN_AREA0, host->data_buf, mtd->writesize);
612 copy_spare(mtd, false);
613 send_page(host, NFC_INPUT);
614 send_cmd(host, command, true);
615 mxc_do_addr_cycle(mtd, column, page_addr);
618 case NAND_CMD_READID:
619 send_cmd(host, command, true);
620 mxc_do_addr_cycle(mtd, column, page_addr);
624 case NAND_CMD_ERASE1:
625 case NAND_CMD_ERASE2:
626 send_cmd(host, command, false);
627 mxc_do_addr_cycle(mtd, column, page_addr);
633 static int __init mxcnd_probe(struct platform_device *pdev)
635 struct nand_chip *this;
636 struct mtd_info *mtd;
637 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
638 struct mxc_nand_host *host;
639 struct resource *res;
641 int err = 0, nr_parts = 0;
643 /* Allocate memory for MTD device structure and private data */
644 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
645 NAND_MAX_OOBSIZE, GFP_KERNEL);
649 host->data_buf = (uint8_t *)(host + 1);
650 host->spare_len = 16;
652 host->dev = &pdev->dev;
653 /* structures must be linked */
657 mtd->owner = THIS_MODULE;
658 mtd->dev.parent = &pdev->dev;
659 mtd->name = "mxc_nand";
661 /* 50 us command delay time */
662 this->chip_delay = 5;
665 this->dev_ready = mxc_nand_dev_ready;
666 this->cmdfunc = mxc_nand_command;
667 this->select_chip = mxc_nand_select_chip;
668 this->read_byte = mxc_nand_read_byte;
669 this->read_word = mxc_nand_read_word;
670 this->write_buf = mxc_nand_write_buf;
671 this->read_buf = mxc_nand_read_buf;
672 this->verify_buf = mxc_nand_verify_buf;
674 host->clk = clk_get(&pdev->dev, "nfc");
675 if (IS_ERR(host->clk)) {
676 err = PTR_ERR(host->clk);
680 clk_enable(host->clk);
683 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
689 host->regs = ioremap(res->start, resource_size(res));
695 tmp = readw(host->regs + NFC_CONFIG1);
697 writew(tmp, host->regs + NFC_CONFIG1);
699 init_waitqueue_head(&host->irq_waitq);
701 host->irq = platform_get_irq(pdev, 0);
703 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
708 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
710 /* preset operation */
711 /* Unlock the internal RAM Buffer */
712 writew(0x2, host->regs + NFC_CONFIG);
714 /* Blocks to be unlocked */
715 writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
716 writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
718 /* Unlock Block Command for given address range */
719 writew(0x4, host->regs + NFC_WRPROT);
721 this->ecc.size = 512;
723 this->ecc.layout = &nand_hw_eccoob_smallpage;
726 this->ecc.calculate = mxc_nand_calculate_ecc;
727 this->ecc.hwctl = mxc_nand_enable_hwecc;
728 this->ecc.correct = mxc_nand_correct_data;
729 this->ecc.mode = NAND_ECC_HW;
730 tmp = readw(host->regs + NFC_CONFIG1);
732 writew(tmp, host->regs + NFC_CONFIG1);
734 this->ecc.mode = NAND_ECC_SOFT;
735 tmp = readw(host->regs + NFC_CONFIG1);
737 writew(tmp, host->regs + NFC_CONFIG1);
740 /* NAND bus width determines access funtions used by upper layer */
741 if (pdata->width == 2)
742 this->options |= NAND_BUSWIDTH_16;
744 /* first scan to find the device and get the page size */
745 if (nand_scan_ident(mtd, 1)) {
750 if (mtd->writesize == 2048) {
751 host->pagesize_2k = 1;
752 this->ecc.layout = &nand_hw_eccoob_largepage;
755 /* second phase scan */
756 if (nand_scan_tail(mtd)) {
761 /* Register the partitions */
762 #ifdef CONFIG_MTD_PARTITIONS
764 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
766 add_mtd_partitions(mtd, host->parts, nr_parts);
770 pr_info("Registering %s as whole device\n", mtd->name);
774 platform_set_drvdata(pdev, host);
779 free_irq(host->irq, host);
790 static int __exit mxcnd_remove(struct platform_device *pdev)
792 struct mxc_nand_host *host = platform_get_drvdata(pdev);
796 platform_set_drvdata(pdev, NULL);
798 nand_release(&host->mtd);
799 free_irq(host->irq, host);
807 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
809 struct mtd_info *mtd = platform_get_drvdata(pdev);
810 struct nand_chip *nand_chip = mtd->priv;
811 struct mxc_nand_host *host = nand_chip->priv;
814 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
816 ret = mtd->suspend(mtd);
817 /* Disable the NFC clock */
818 clk_disable(host->clk);
824 static int mxcnd_resume(struct platform_device *pdev)
826 struct mtd_info *mtd = platform_get_drvdata(pdev);
827 struct nand_chip *nand_chip = mtd->priv;
828 struct mxc_nand_host *host = nand_chip->priv;
831 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
834 /* Enable the NFC clock */
835 clk_enable(host->clk);
843 # define mxcnd_suspend NULL
844 # define mxcnd_resume NULL
845 #endif /* CONFIG_PM */
847 static struct platform_driver mxcnd_driver = {
851 .remove = __exit_p(mxcnd_remove),
852 .suspend = mxcnd_suspend,
853 .resume = mxcnd_resume,
856 static int __init mxc_nd_init(void)
858 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
861 static void __exit mxc_nd_cleanup(void)
863 /* Unregister the device structure */
864 platform_driver_unregister(&mxcnd_driver);
867 module_init(mxc_nd_init);
868 module_exit(mxc_nd_cleanup);
870 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
871 MODULE_DESCRIPTION("MXC NAND MTD driver");
872 MODULE_LICENSE("GPL");