1 // SPDX-License-Identifier: GPL-2.0
3 * NAND Flash Controller Device Driver for DT
5 * Copyright © 2011, Picochip.
11 #include <linux/ioport.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
21 struct denali_controller controller;
22 struct clk *clk; /* core clock */
23 struct clk *clk_x; /* bus interface clock */
24 struct clk *clk_ecc; /* ECC circuit clock */
27 struct denali_dt_data {
28 unsigned int revision;
30 const struct nand_ecc_caps *ecc_caps;
33 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
35 static const struct denali_dt_data denali_socfpga_data = {
36 .caps = DENALI_CAP_HW_ECC_FIXUP,
37 .ecc_caps = &denali_socfpga_ecc_caps,
40 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
42 static const struct denali_dt_data denali_uniphier_v5a_data = {
43 .caps = DENALI_CAP_HW_ECC_FIXUP |
45 .ecc_caps = &denali_uniphier_v5a_ecc_caps,
48 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
50 static const struct denali_dt_data denali_uniphier_v5b_data = {
52 .caps = DENALI_CAP_HW_ECC_FIXUP |
54 .ecc_caps = &denali_uniphier_v5b_ecc_caps,
57 static const struct of_device_id denali_nand_dt_ids[] = {
59 .compatible = "altr,socfpga-denali-nand",
60 .data = &denali_socfpga_data,
63 .compatible = "socionext,uniphier-denali-nand-v5a",
64 .data = &denali_uniphier_v5a_data,
67 .compatible = "socionext,uniphier-denali-nand-v5b",
68 .data = &denali_uniphier_v5b_data,
72 MODULE_DEVICE_TABLE(of, denali_nand_dt_ids);
74 static int denali_dt_chip_init(struct denali_controller *denali,
75 struct device_node *chip_np)
77 struct denali_chip *dchip;
81 nsels = of_property_count_u32_elems(chip_np, "reg");
85 dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels),
92 for (i = 0; i < nsels; i++) {
93 ret = of_property_read_u32_index(chip_np, "reg", i, &bank);
97 dchip->sels[i].bank = bank;
99 nand_set_flash_node(&dchip->chip, chip_np);
102 return denali_chip_init(denali, dchip);
105 /* Backward compatibility for old platforms */
106 static int denali_dt_legacy_chip_init(struct denali_controller *denali)
108 struct denali_chip *dchip;
111 nsels = denali->nbanks;
113 dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels),
118 dchip->nsels = nsels;
120 for (i = 0; i < nsels; i++)
121 dchip->sels[i].bank = i;
123 nand_set_flash_node(&dchip->chip, denali->dev->of_node);
125 return denali_chip_init(denali, dchip);
129 * Check the DT binding.
130 * The new binding expects chip subnodes in the controller node.
131 * So, #address-cells = <1>; #size-cells = <0>; are required.
132 * Check the #size-cells to distinguish the binding.
134 static bool denali_dt_is_legacy_binding(struct device_node *np)
139 ret = of_property_read_u32(np, "#size-cells", &cells);
146 static int denali_dt_probe(struct platform_device *pdev)
148 struct device *dev = &pdev->dev;
149 struct resource *res;
150 struct denali_dt *dt;
151 const struct denali_dt_data *data;
152 struct denali_controller *denali;
153 struct device_node *np;
156 dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL);
159 denali = &dt->controller;
161 data = of_device_get_match_data(dev);
163 denali->revision = data->revision;
164 denali->caps = data->caps;
165 denali->ecc_caps = data->ecc_caps;
169 denali->irq = platform_get_irq(pdev, 0);
170 if (denali->irq < 0) {
171 dev_err(dev, "no irq defined\n");
175 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg");
176 denali->reg = devm_ioremap_resource(dev, res);
177 if (IS_ERR(denali->reg))
178 return PTR_ERR(denali->reg);
180 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
181 denali->host = devm_ioremap_resource(dev, res);
182 if (IS_ERR(denali->host))
183 return PTR_ERR(denali->host);
185 dt->clk = devm_clk_get(dev, "nand");
187 return PTR_ERR(dt->clk);
189 dt->clk_x = devm_clk_get(dev, "nand_x");
190 if (IS_ERR(dt->clk_x))
191 return PTR_ERR(dt->clk_x);
193 dt->clk_ecc = devm_clk_get(dev, "ecc");
194 if (IS_ERR(dt->clk_ecc))
195 return PTR_ERR(dt->clk_ecc);
197 ret = clk_prepare_enable(dt->clk);
201 ret = clk_prepare_enable(dt->clk_x);
203 goto out_disable_clk;
205 ret = clk_prepare_enable(dt->clk_ecc);
207 goto out_disable_clk_x;
209 denali->clk_rate = clk_get_rate(dt->clk);
210 denali->clk_x_rate = clk_get_rate(dt->clk_x);
212 ret = denali_init(denali);
214 goto out_disable_clk_ecc;
216 if (denali_dt_is_legacy_binding(dev->of_node)) {
217 ret = denali_dt_legacy_chip_init(denali);
219 goto out_remove_denali;
221 for_each_child_of_node(dev->of_node, np) {
222 ret = denali_dt_chip_init(denali, np);
225 goto out_remove_denali;
230 platform_set_drvdata(pdev, dt);
235 denali_remove(denali);
237 clk_disable_unprepare(dt->clk_ecc);
239 clk_disable_unprepare(dt->clk_x);
241 clk_disable_unprepare(dt->clk);
246 static int denali_dt_remove(struct platform_device *pdev)
248 struct denali_dt *dt = platform_get_drvdata(pdev);
250 denali_remove(&dt->controller);
251 clk_disable_unprepare(dt->clk_ecc);
252 clk_disable_unprepare(dt->clk_x);
253 clk_disable_unprepare(dt->clk);
258 static struct platform_driver denali_dt_driver = {
259 .probe = denali_dt_probe,
260 .remove = denali_dt_remove,
262 .name = "denali-nand-dt",
263 .of_match_table = denali_nand_dt_ids,
266 module_platform_driver(denali_dt_driver);
268 MODULE_LICENSE("GPL v2");
269 MODULE_AUTHOR("Jamie Iles");
270 MODULE_DESCRIPTION("DT driver for Denali NAND controller");