drivers/mtd/nand/raw/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/delay.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/sched.h>
  20 #include <linux/mtd/mtd.h>
  21 #include <linux/mtd/rawnand.h>
  22 #include <linux/mtd/partitions.h>
  23 #include <linux/omap-dma.h>
  24 #include <linux/io.h>
  25 #include <linux/slab.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28
  29 #include <linux/mtd/nand_bch.h>
  30 #include <linux/platform_data/elm.h>
  31
  32 #include <linux/omap-gpmc.h>
  33 #include <linux/platform_data/mtd-nand-omap2.h>
  34
  35 #define DRIVER_NAME     "omap2-nand"
  36 #define OMAP_NAND_TIMEOUT_MS    5000
  37
  38 #define NAND_Ecc_P1e            (1 << 0)
  39 #define NAND_Ecc_P2e            (1 << 1)
  40 #define NAND_Ecc_P4e            (1 << 2)
  41 #define NAND_Ecc_P8e            (1 << 3)
  42 #define NAND_Ecc_P16e           (1 << 4)
  43 #define NAND_Ecc_P32e           (1 << 5)
  44 #define NAND_Ecc_P64e           (1 << 6)
  45 #define NAND_Ecc_P128e          (1 << 7)
  46 #define NAND_Ecc_P256e          (1 << 8)
  47 #define NAND_Ecc_P512e          (1 << 9)
  48 #define NAND_Ecc_P1024e         (1 << 10)
  49 #define NAND_Ecc_P2048e         (1 << 11)
  50
  51 #define NAND_Ecc_P1o            (1 << 16)
  52 #define NAND_Ecc_P2o            (1 << 17)
  53 #define NAND_Ecc_P4o            (1 << 18)
  54 #define NAND_Ecc_P8o            (1 << 19)
  55 #define NAND_Ecc_P16o           (1 << 20)
  56 #define NAND_Ecc_P32o           (1 << 21)
  57 #define NAND_Ecc_P64o           (1 << 22)
  58 #define NAND_Ecc_P128o          (1 << 23)
  59 #define NAND_Ecc_P256o          (1 << 24)
  60 #define NAND_Ecc_P512o          (1 << 25)
  61 #define NAND_Ecc_P1024o         (1 << 26)
  62 #define NAND_Ecc_P2048o         (1 << 27)
  63
  64 #define TF(value)       (value ? 1 : 0)
  65
  66 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  67 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  68 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  69 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  70 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  71 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  72 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  73 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  74
  75 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  76 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  77 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  78 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  79 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  80 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  81 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  82 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  83
  84 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  85 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  86 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  87 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  88 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  89 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  90 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  91 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  92
  93 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  94 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  95 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  96 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  97 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  98 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  99 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
 100 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
 101
 102 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
 103 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
 104
 105 #define PREFETCH_CONFIG1_CS_SHIFT       24
 106 #define ECC_CONFIG_CS_SHIFT             1
 107 #define CS_MASK                         0x7
 108 #define ENABLE_PREFETCH                 (0x1 << 7)
 109 #define DMA_MPU_MODE_SHIFT              2
 110 #define ECCSIZE0_SHIFT                  12
 111 #define ECCSIZE1_SHIFT                  22
 112 #define ECC1RESULTSIZE                  0x1
 113 #define ECCCLEAR                        0x100
 114 #define ECC1                            0x1
 115 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 116 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 117 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 118 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 119 #define STATUS_BUFF_EMPTY               0x00000001
 120
 121 #define SECTOR_BYTES            512
 122 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
 123 #define BCH4_BIT_PAD            4
 124
 125 /* GPMC ecc engine settings for read */
 126 #define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
 127 #define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
 128 #define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
 129 #define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
 130 #define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
 131
 132 /* GPMC ecc engine settings for write */
 133 #define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
 134 #define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
 135 #define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
 136
 137 #define BADBLOCK_MARKER_LENGTH          2
 138
 139 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
 140                                 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
 141                                 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
 142                                 0x07, 0x0e};
 143 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
 144         0xac, 0x6b, 0xff, 0x99, 0x7b};
 145 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
 146
 147 struct omap_nand_info {
 148         struct nand_chip                nand;
 149         struct platform_device          *pdev;
 150
 151         int                             gpmc_cs;
 152         bool                            dev_ready;
 153         enum nand_io                    xfer_type;
 154         int                             devsize;
 155         enum omap_ecc                   ecc_opt;
 156         struct device_node              *elm_of_node;
 157
 158         unsigned long                   phys_base;
 159         struct completion               comp;
 160         struct dma_chan                 *dma;
 161         int                             gpmc_irq_fifo;
 162         int                             gpmc_irq_count;
 163         enum {
 164                 OMAP_NAND_IO_READ = 0,  /* read */
 165                 OMAP_NAND_IO_WRITE,     /* write */
 166         } iomode;
 167         u_char                          *buf;
 168         int                                     buf_len;
 169         /* Interface to GPMC */
 170         struct gpmc_nand_regs           reg;
 171         struct gpmc_nand_ops            *ops;
 172         bool                            flash_bbt;
 173         /* fields specific for BCHx_HW ECC scheme */
 174         struct device                   *elm_dev;
 175         /* NAND ready gpio */
 176         struct gpio_desc                *ready_gpiod;
 177 };
 178
 179 static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd)
 180 {
 181         return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand);
 182 }
 183
 184 /**
 185  * omap_prefetch_enable - configures and starts prefetch transfer
 186  * @cs: cs (chip select) number
 187  * @fifo_th: fifo threshold to be used for read/ write
 188  * @dma_mode: dma mode enable (1) or disable (0)
 189  * @u32_count: number of bytes to be transferred
 190  * @is_write: prefetch read(0) or write post(1) mode
 191  */
 192 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
 193         unsigned int u32_count, int is_write, struct omap_nand_info *info)
 194 {
 195         u32 val;
 196
 197         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 198                 return -1;
 199
 200         if (readl(info->reg.gpmc_prefetch_control))
 201                 return -EBUSY;
 202
 203         /* Set the amount of bytes to be prefetched */
 204         writel(u32_count, info->reg.gpmc_prefetch_config2);
 205
 206         /* Set dma/mpu mode, the prefetch read / post write and
 207          * enable the engine. Set which cs is has requested for.
 208          */
 209         val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
 210                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
 211                 (dma_mode << DMA_MPU_MODE_SHIFT) | (is_write & 0x1));
 212         writel(val, info->reg.gpmc_prefetch_config1);
 213
 214         /*  Start the prefetch engine */
 215         writel(0x1, info->reg.gpmc_prefetch_control);
 216
 217         return 0;
 218 }
 219
 220 /**
 221  * omap_prefetch_reset - disables and stops the prefetch engine
 222  */
 223 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
 224 {
 225         u32 config1;
 226
 227         /* check if the same module/cs is trying to reset */
 228         config1 = readl(info->reg.gpmc_prefetch_config1);
 229         if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
 230                 return -EINVAL;
 231
 232         /* Stop the PFPW engine */
 233         writel(0x0, info->reg.gpmc_prefetch_control);
 234
 235         /* Reset/disable the PFPW engine */
 236         writel(0x0, info->reg.gpmc_prefetch_config1);
 237
 238         return 0;
 239 }
 240
 241 /**
 242  * omap_hwcontrol - hardware specific access to control-lines
 243  * @chip: NAND chip object
 244  * @cmd: command to device
 245  * @ctrl:
 246  * NAND_NCE: bit 0 -> don't care
 247  * NAND_CLE: bit 1 -> Command Latch
 248  * NAND_ALE: bit 2 -> Address Latch
 249  *
 250  * NOTE: boards may use different bits for these!!
 251  */
 252 static void omap_hwcontrol(struct nand_chip *chip, int cmd, unsigned int ctrl)
 253 {
 254         struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
 255
 256         if (cmd != NAND_CMD_NONE) {
 257                 if (ctrl & NAND_CLE)
 258                         writeb(cmd, info->reg.gpmc_nand_command);
 259
 260                 else if (ctrl & NAND_ALE)
 261                         writeb(cmd, info->reg.gpmc_nand_address);
 262
 263                 else /* NAND_NCE */
 264                         writeb(cmd, info->reg.gpmc_nand_data);
 265         }
 266 }
 267
 268 /**
 269  * omap_read_buf8 - read data from NAND controller into buffer
 270  * @mtd: MTD device structure
 271  * @buf: buffer to store date
 272  * @len: number of bytes to read
 273  */
 274 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 275 {
 276         struct nand_chip *nand = mtd_to_nand(mtd);
 277
 278         ioread8_rep(nand->legacy.IO_ADDR_R, buf, len);
 279 }
 280
 281 /**
 282  * omap_write_buf8 - write buffer to NAND controller
 283  * @mtd: MTD device structure
 284  * @buf: data buffer
 285  * @len: number of bytes to write
 286  */
 287 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 288 {
 289         struct omap_nand_info *info = mtd_to_omap(mtd);
 290         u_char *p = (u_char *)buf;
 291         bool status;
 292
 293         while (len--) {
 294                 iowrite8(*p++, info->nand.legacy.IO_ADDR_W);
 295                 /* wait until buffer is available for write */
 296                 do {
 297                         status = info->ops->nand_writebuffer_empty();
 298                 } while (!status);
 299         }
 300 }
 301
 302 /**
 303  * omap_read_buf16 - read data from NAND controller into buffer
 304  * @mtd: MTD device structure
 305  * @buf: buffer to store date
 306  * @len: number of bytes to read
 307  */
 308 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 309 {
 310         struct nand_chip *nand = mtd_to_nand(mtd);
 311
 312         ioread16_rep(nand->legacy.IO_ADDR_R, buf, len / 2);
 313 }
 314
 315 /**
 316  * omap_write_buf16 - write buffer to NAND controller
 317  * @mtd: MTD device structure
 318  * @buf: data buffer
 319  * @len: number of bytes to write
 320  */
 321 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 322 {
 323         struct omap_nand_info *info = mtd_to_omap(mtd);
 324         u16 *p = (u16 *) buf;
 325         bool status;
 326         /* FIXME try bursts of writesw() or DMA ... */
 327         len >>= 1;
 328
 329         while (len--) {
 330                 iowrite16(*p++, info->nand.legacy.IO_ADDR_W);
 331                 /* wait until buffer is available for write */
 332                 do {
 333                         status = info->ops->nand_writebuffer_empty();
 334                 } while (!status);
 335         }
 336 }
 337
 338 /**
 339  * omap_read_buf_pref - read data from NAND controller into buffer
 340  * @chip: NAND chip object
 341  * @buf: buffer to store date
 342  * @len: number of bytes to read
 343  */
 344 static void omap_read_buf_pref(struct nand_chip *chip, u_char *buf, int len)
 345 {
 346         struct mtd_info *mtd = nand_to_mtd(chip);
 347         struct omap_nand_info *info = mtd_to_omap(mtd);
 348         uint32_t r_count = 0;
 349         int ret = 0;
 350         u32 *p = (u32 *)buf;
 351
 352         /* take care of subpage reads */
 353         if (len % 4) {
 354                 if (info->nand.options & NAND_BUSWIDTH_16)
 355                         omap_read_buf16(mtd, buf, len % 4);
 356                 else
 357                         omap_read_buf8(mtd, buf, len % 4);
 358                 p = (u32 *) (buf + len % 4);
 359                 len -= len % 4;
 360         }
 361
 362         /* configure and start prefetch transfer */
 363         ret = omap_prefetch_enable(info->gpmc_cs,
 364                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
 365         if (ret) {
 366                 /* PFPW engine is busy, use cpu copy method */
 367                 if (info->nand.options & NAND_BUSWIDTH_16)
 368                         omap_read_buf16(mtd, (u_char *)p, len);
 369                 else
 370                         omap_read_buf8(mtd, (u_char *)p, len);
 371         } else {
 372                 do {
 373                         r_count = readl(info->reg.gpmc_prefetch_status);
 374                         r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
 375                         r_count = r_count >> 2;
 376                         ioread32_rep(info->nand.legacy.IO_ADDR_R, p, r_count);
 377                         p += r_count;
 378                         len -= r_count << 2;
 379                 } while (len);
 380                 /* disable and stop the PFPW engine */
 381                 omap_prefetch_reset(info->gpmc_cs, info);
 382         }
 383 }
 384
 385 /**
 386  * omap_write_buf_pref - write buffer to NAND controller
 387  * @chip: NAND chip object
 388  * @buf: data buffer
 389  * @len: number of bytes to write
 390  */
 391 static void omap_write_buf_pref(struct nand_chip *chip, const u_char *buf,
 392                                 int len)
 393 {
 394         struct mtd_info *mtd = nand_to_mtd(chip);
 395         struct omap_nand_info *info = mtd_to_omap(mtd);
 396         uint32_t w_count = 0;
 397         int i = 0, ret = 0;
 398         u16 *p = (u16 *)buf;
 399         unsigned long tim, limit;
 400         u32 val;
 401
 402         /* take care of subpage writes */
 403         if (len % 2 != 0) {
 404                 writeb(*buf, info->nand.legacy.IO_ADDR_W);
 405                 p = (u16 *)(buf + 1);
 406                 len--;
 407         }
 408
 409         /*  configure and start prefetch transfer */
 410         ret = omap_prefetch_enable(info->gpmc_cs,
 411                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
 412         if (ret) {
 413                 /* PFPW engine is busy, use cpu copy method */
 414                 if (info->nand.options & NAND_BUSWIDTH_16)
 415                         omap_write_buf16(mtd, (u_char *)p, len);
 416                 else
 417                         omap_write_buf8(mtd, (u_char *)p, len);
 418         } else {
 419                 while (len) {
 420                         w_count = readl(info->reg.gpmc_prefetch_status);
 421                         w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
 422                         w_count = w_count >> 1;
 423                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 424                                 iowrite16(*p++, info->nand.legacy.IO_ADDR_W);
 425                 }
 426                 /* wait for data to flushed-out before reset the prefetch */
 427                 tim = 0;
 428                 limit = (loops_per_jiffy *
 429                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 430                 do {
 431                         cpu_relax();
 432                         val = readl(info->reg.gpmc_prefetch_status);
 433                         val = PREFETCH_STATUS_COUNT(val);
 434                 } while (val && (tim++ < limit));
 435
 436                 /* disable and stop the PFPW engine */
 437                 omap_prefetch_reset(info->gpmc_cs, info);
 438         }
 439 }
 440
 441 /*
 442  * omap_nand_dma_callback: callback on the completion of dma transfer
 443  * @data: pointer to completion data structure
 444  */
 445 static void omap_nand_dma_callback(void *data)
 446 {
 447         complete((struct completion *) data);
 448 }
 449
 450 /*
 451  * omap_nand_dma_transfer: configure and start dma transfer
 452  * @mtd: MTD device structure
 453  * @addr: virtual address in RAM of source/destination
 454  * @len: number of data bytes to be transferred
 455  * @is_write: flag for read/write operation
 456  */
 457 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 458                                         unsigned int len, int is_write)
 459 {
 460         struct omap_nand_info *info = mtd_to_omap(mtd);
 461         struct dma_async_tx_descriptor *tx;
 462         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 463                                                         DMA_FROM_DEVICE;
 464         struct scatterlist sg;
 465         unsigned long tim, limit;
 466         unsigned n;
 467         int ret;
 468         u32 val;
 469
 470         if (!virt_addr_valid(addr))
 471                 goto out_copy;
 472
 473         sg_init_one(&sg, addr, len);
 474         n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
 475         if (n == 0) {
 476                 dev_err(&info->pdev->dev,
 477                         "Couldn't DMA map a %d byte buffer\n", len);
 478                 goto out_copy;
 479         }
 480
 481         tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
 482                 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 483                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 484         if (!tx)
 485                 goto out_copy_unmap;
 486
 487         tx->callback = omap_nand_dma_callback;
 488         tx->callback_param = &info->comp;
 489         dmaengine_submit(tx);
 490
 491         init_completion(&info->comp);
 492
 493         /* setup and start DMA using dma_addr */
 494         dma_async_issue_pending(info->dma);
 495
 496         /*  configure and start prefetch transfer */
 497         ret = omap_prefetch_enable(info->gpmc_cs,
 498                 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
 499         if (ret)
 500                 /* PFPW engine is busy, use cpu copy method */
 501                 goto out_copy_unmap;
 502
 503         wait_for_completion(&info->comp);
 504         tim = 0;
 505         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 506
 507         do {
 508                 cpu_relax();
 509                 val = readl(info->reg.gpmc_prefetch_status);
 510                 val = PREFETCH_STATUS_COUNT(val);
 511         } while (val && (tim++ < limit));
 512
 513         /* disable and stop the PFPW engine */
 514         omap_prefetch_reset(info->gpmc_cs, info);
 515
 516         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 517         return 0;
 518
 519 out_copy_unmap:
 520         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 521 out_copy:
 522         if (info->nand.options & NAND_BUSWIDTH_16)
 523                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 524                         : omap_write_buf16(mtd, (u_char *) addr, len);
 525         else
 526                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 527                         : omap_write_buf8(mtd, (u_char *) addr, len);
 528         return 0;
 529 }
 530
 531 /**
 532  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 533  * @chip: NAND chip object
 534  * @buf: buffer to store date
 535  * @len: number of bytes to read
 536  */
 537 static void omap_read_buf_dma_pref(struct nand_chip *chip, u_char *buf,
 538                                    int len)
 539 {
 540         struct mtd_info *mtd = nand_to_mtd(chip);
 541
 542         if (len <= mtd->oobsize)
 543                 omap_read_buf_pref(chip, buf, len);
 544         else
 545                 /* start transfer in DMA mode */
 546                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 547 }
 548
 549 /**
 550  * omap_write_buf_dma_pref - write buffer to NAND controller
 551  * @chip: NAND chip object
 552  * @buf: data buffer
 553  * @len: number of bytes to write
 554  */
 555 static void omap_write_buf_dma_pref(struct nand_chip *chip, const u_char *buf,
 556                                     int len)
 557 {
 558         struct mtd_info *mtd = nand_to_mtd(chip);
 559
 560         if (len <= mtd->oobsize)
 561                 omap_write_buf_pref(chip, buf, len);
 562         else
 563                 /* start transfer in DMA mode */
 564                 omap_nand_dma_transfer(mtd, (u_char *)buf, len, 0x1);
 565 }
 566
 567 /*
 568  * omap_nand_irq - GPMC irq handler
 569  * @this_irq: gpmc irq number
 570  * @dev: omap_nand_info structure pointer is passed here
 571  */
 572 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 573 {
 574         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 575         u32 bytes;
 576
 577         bytes = readl(info->reg.gpmc_prefetch_status);
 578         bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
 579         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 580         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 581                 if (this_irq == info->gpmc_irq_count)
 582                         goto done;
 583
 584                 if (info->buf_len && (info->buf_len < bytes))
 585                         bytes = info->buf_len;
 586                 else if (!info->buf_len)
 587                         bytes = 0;
 588                 iowrite32_rep(info->nand.legacy.IO_ADDR_W, (u32 *)info->buf,
 589                               bytes >> 2);
 590                 info->buf = info->buf + bytes;
 591                 info->buf_len -= bytes;
 592
 593         } else {
 594                 ioread32_rep(info->nand.legacy.IO_ADDR_R, (u32 *)info->buf,
 595                              bytes >> 2);
 596                 info->buf = info->buf + bytes;
 597
 598                 if (this_irq == info->gpmc_irq_count)
 599                         goto done;
 600         }
 601
 602         return IRQ_HANDLED;
 603
 604 done:
 605         complete(&info->comp);
 606
 607         disable_irq_nosync(info->gpmc_irq_fifo);
 608         disable_irq_nosync(info->gpmc_irq_count);
 609
 610         return IRQ_HANDLED;
 611 }
 612
 613 /*
 614  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 615  * @chip: NAND chip object
 616  * @buf: buffer to store date
 617  * @len: number of bytes to read
 618  */
 619 static void omap_read_buf_irq_pref(struct nand_chip *chip, u_char *buf,
 620                                    int len)
 621 {
 622         struct mtd_info *mtd = nand_to_mtd(chip);
 623         struct omap_nand_info *info = mtd_to_omap(mtd);
 624         int ret = 0;
 625
 626         if (len <= mtd->oobsize) {
 627                 omap_read_buf_pref(chip, buf, len);
 628                 return;
 629         }
 630
 631         info->iomode = OMAP_NAND_IO_READ;
 632         info->buf = buf;
 633         init_completion(&info->comp);
 634
 635         /*  configure and start prefetch transfer */
 636         ret = omap_prefetch_enable(info->gpmc_cs,
 637                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
 638         if (ret)
 639                 /* PFPW engine is busy, use cpu copy method */
 640                 goto out_copy;
 641
 642         info->buf_len = len;
 643
 644         enable_irq(info->gpmc_irq_count);
 645         enable_irq(info->gpmc_irq_fifo);
 646
 647         /* waiting for read to complete */
 648         wait_for_completion(&info->comp);
 649
 650         /* disable and stop the PFPW engine */
 651         omap_prefetch_reset(info->gpmc_cs, info);
 652         return;
 653
 654 out_copy:
 655         if (info->nand.options & NAND_BUSWIDTH_16)
 656                 omap_read_buf16(mtd, buf, len);
 657         else
 658                 omap_read_buf8(mtd, buf, len);
 659 }
 660
 661 /*
 662  * omap_write_buf_irq_pref - write buffer to NAND controller
 663  * @chip: NAND chip object
 664  * @buf: data buffer
 665  * @len: number of bytes to write
 666  */
 667 static void omap_write_buf_irq_pref(struct nand_chip *chip, const u_char *buf,
 668                                     int len)
 669 {
 670         struct mtd_info *mtd = nand_to_mtd(chip);
 671         struct omap_nand_info *info = mtd_to_omap(mtd);
 672         int ret = 0;
 673         unsigned long tim, limit;
 674         u32 val;
 675
 676         if (len <= mtd->oobsize) {
 677                 omap_write_buf_pref(chip, buf, len);
 678                 return;
 679         }
 680
 681         info->iomode = OMAP_NAND_IO_WRITE;
 682         info->buf = (u_char *) buf;
 683         init_completion(&info->comp);
 684
 685         /* configure and start prefetch transfer : size=24 */
 686         ret = omap_prefetch_enable(info->gpmc_cs,
 687                 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
 688         if (ret)
 689                 /* PFPW engine is busy, use cpu copy method */
 690                 goto out_copy;
 691
 692         info->buf_len = len;
 693
 694         enable_irq(info->gpmc_irq_count);
 695         enable_irq(info->gpmc_irq_fifo);
 696
 697         /* waiting for write to complete */
 698         wait_for_completion(&info->comp);
 699
 700         /* wait for data to flushed-out before reset the prefetch */
 701         tim = 0;
 702         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 703         do {
 704                 val = readl(info->reg.gpmc_prefetch_status);
 705                 val = PREFETCH_STATUS_COUNT(val);
 706                 cpu_relax();
 707         } while (val && (tim++ < limit));
 708
 709         /* disable and stop the PFPW engine */
 710         omap_prefetch_reset(info->gpmc_cs, info);
 711         return;
 712
 713 out_copy:
 714         if (info->nand.options & NAND_BUSWIDTH_16)
 715                 omap_write_buf16(mtd, buf, len);
 716         else
 717                 omap_write_buf8(mtd, buf, len);
 718 }
 719
 720 /**
 721  * gen_true_ecc - This function will generate true ECC value
 722  * @ecc_buf: buffer to store ecc code
 723  *
 724  * This generated true ECC value can be used when correcting
 725  * data read from NAND flash memory core
 726  */
 727 static void gen_true_ecc(u8 *ecc_buf)
 728 {
 729         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 730                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 731
 732         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 733                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 734         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 735                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 736         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 737                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 738 }
 739
 740 /**
 741  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 742  * @ecc_data1:  ecc code from nand spare area
 743  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 744  * @page_data:  page data
 745  *
 746  * This function compares two ECC's and indicates if there is an error.
 747  * If the error can be corrected it will be corrected to the buffer.
 748  * If there is no error, %0 is returned. If there is an error but it
 749  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 750  */
 751 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 752                             u8 *ecc_data2,      /* read from register */
 753                             u8 *page_data)
 754 {
 755         uint    i;
 756         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 757         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 758         u8      ecc_bit[24];
 759         u8      ecc_sum = 0;
 760         u8      find_bit = 0;
 761         uint    find_byte = 0;
 762         int     isEccFF;
 763
 764         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 765
 766         gen_true_ecc(ecc_data1);
 767         gen_true_ecc(ecc_data2);
 768
 769         for (i = 0; i <= 2; i++) {
 770                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 771                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 772         }
 773
 774         for (i = 0; i < 8; i++) {
 775                 tmp0_bit[i]     = *ecc_data1 % 2;
 776                 *ecc_data1      = *ecc_data1 / 2;
 777         }
 778
 779         for (i = 0; i < 8; i++) {
 780                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 781                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 782         }
 783
 784         for (i = 0; i < 8; i++) {
 785                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 786                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 787         }
 788
 789         for (i = 0; i < 8; i++) {
 790                 comp0_bit[i]     = *ecc_data2 % 2;
 791                 *ecc_data2       = *ecc_data2 / 2;
 792         }
 793
 794         for (i = 0; i < 8; i++) {
 795                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 796                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 797         }
 798
 799         for (i = 0; i < 8; i++) {
 800                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 801                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 802         }
 803
 804         for (i = 0; i < 6; i++)
 805                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 806
 807         for (i = 0; i < 8; i++)
 808                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 809
 810         for (i = 0; i < 8; i++)
 811                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 812
 813         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 814         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 815
 816         for (i = 0; i < 24; i++)
 817                 ecc_sum += ecc_bit[i];
 818
 819         switch (ecc_sum) {
 820         case 0:
 821                 /* Not reached because this function is not called if
 822                  *  ECC values are equal
 823                  */
 824                 return 0;
 825
 826         case 1:
 827                 /* Uncorrectable error */
 828                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 829                 return -EBADMSG;
 830
 831         case 11:
 832                 /* UN-Correctable error */
 833                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 834                 return -EBADMSG;
 835
 836         case 12:
 837                 /* Correctable error */
 838                 find_byte = (ecc_bit[23] << 8) +
 839                             (ecc_bit[21] << 7) +
 840                             (ecc_bit[19] << 6) +
 841                             (ecc_bit[17] << 5) +
 842                             (ecc_bit[15] << 4) +
 843                             (ecc_bit[13] << 3) +
 844                             (ecc_bit[11] << 2) +
 845                             (ecc_bit[9]  << 1) +
 846                             ecc_bit[7];
 847
 848                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 849
 850                 pr_debug("Correcting single bit ECC error at offset: "
 851                                 "%d, bit: %d\n", find_byte, find_bit);
 852
 853                 page_data[find_byte] ^= (1 << find_bit);
 854
 855                 return 1;
 856         default:
 857                 if (isEccFF) {
 858                         if (ecc_data2[0] == 0 &&
 859                             ecc_data2[1] == 0 &&
 860                             ecc_data2[2] == 0)
 861                                 return 0;
 862                 }
 863                 pr_debug("UNCORRECTED_ERROR default\n");
 864                 return -EBADMSG;
 865         }
 866 }
 867
 868 /**
 869  * omap_correct_data - Compares the ECC read with HW generated ECC
 870  * @chip: NAND chip object
 871  * @dat: page data
 872  * @read_ecc: ecc read from nand flash
 873  * @calc_ecc: ecc read from HW ECC registers
 874  *
 875  * Compares the ecc read from nand spare area with ECC registers values
 876  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 877  * detection and correction. If there are no errors, %0 is returned. If
 878  * there were errors and all of the errors were corrected, the number of
 879  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 880  * returned.
 881  */
 882 static int omap_correct_data(struct nand_chip *chip, u_char *dat,
 883                              u_char *read_ecc, u_char *calc_ecc)
 884 {
 885         struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
 886         int blockCnt = 0, i = 0, ret = 0;
 887         int stat = 0;
 888
 889         /* Ex NAND_ECC_HW12_2048 */
 890         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 891                         (info->nand.ecc.size  == 2048))
 892                 blockCnt = 4;
 893         else
 894                 blockCnt = 1;
 895
 896         for (i = 0; i < blockCnt; i++) {
 897                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 898                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 899                         if (ret < 0)
 900                                 return ret;
 901                         /* keep track of the number of corrected errors */
 902                         stat += ret;
 903                 }
 904                 read_ecc += 3;
 905                 calc_ecc += 3;
 906                 dat      += 512;
 907         }
 908         return stat;
 909 }
 910
 911 /**
 912  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 913  * @chip: NAND chip object
 914  * @dat: The pointer to data on which ecc is computed
 915  * @ecc_code: The ecc_code buffer
 916  *
 917  * Using noninverted ECC can be considered ugly since writing a blank
 918  * page ie. padding will clear the ECC bytes. This is no problem as long
 919  * nobody is trying to write data on the seemingly unused page. Reading
 920  * an erased page will produce an ECC mismatch between generated and read
 921  * ECC bytes that has to be dealt with separately.
 922  */
 923 static int omap_calculate_ecc(struct nand_chip *chip, const u_char *dat,
 924                               u_char *ecc_code)
 925 {
 926         struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
 927         u32 val;
 928
 929         val = readl(info->reg.gpmc_ecc_config);
 930         if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
 931                 return -EINVAL;
 932
 933         /* read ecc result */
 934         val = readl(info->reg.gpmc_ecc1_result);
 935         *ecc_code++ = val;          /* P128e, ..., P1e */
 936         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
 937         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 938         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 939
 940         return 0;
 941 }
 942
 943 /**
 944  * omap_enable_hwecc - This function enables the hardware ecc functionality
 945  * @mtd: MTD device structure
 946  * @mode: Read/Write mode
 947  */
 948 static void omap_enable_hwecc(struct nand_chip *chip, int mode)
 949 {
 950         struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
 951         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 952         u32 val;
 953
 954         /* clear ecc and enable bits */
 955         val = ECCCLEAR | ECC1;
 956         writel(val, info->reg.gpmc_ecc_control);
 957
 958         /* program ecc and result sizes */
 959         val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
 960                          ECC1RESULTSIZE);
 961         writel(val, info->reg.gpmc_ecc_size_config);
 962
 963         switch (mode) {
 964         case NAND_ECC_READ:
 965         case NAND_ECC_WRITE:
 966                 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
 967                 break;
 968         case NAND_ECC_READSYN:
 969                 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
 970                 break;
 971         default:
 972                 dev_info(&info->pdev->dev,
 973                         "error: unrecognized Mode[%d]!\n", mode);
 974                 break;
 975         }
 976
 977         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 978         val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 979         writel(val, info->reg.gpmc_ecc_config);
 980 }
 981
 982 /**
 983  * omap_wait - wait until the command is done
 984  * @this: NAND Chip structure
 985  *
 986  * Wait function is called during Program and erase operations and
 987  * the way it is called from MTD layer, we should wait till the NAND
 988  * chip is ready after the programming/erase operation has completed.
 989  *
 990  * Erase can take up to 400ms and program up to 20ms according to
 991  * general NAND and SmartMedia specs
 992  */
 993 static int omap_wait(struct nand_chip *this)
 994 {
 995         struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(this));
 996         unsigned long timeo = jiffies;
 997         int status, state = this->state;
 998
 999         if (state == FL_ERASING)
1000                 timeo += msecs_to_jiffies(400);
1001         else
1002                 timeo += msecs_to_jiffies(20);
1003
1004         writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1005         while (time_before(jiffies, timeo)) {
1006                 status = readb(info->reg.gpmc_nand_data);
1007                 if (status & NAND_STATUS_READY)
1008                         break;
1009                 cond_resched();
1010         }
1011
1012         status = readb(info->reg.gpmc_nand_data);
1013         return status;
1014 }
1015
1016 /**
1017  * omap_dev_ready - checks the NAND Ready GPIO line
1018  * @mtd: MTD device structure
1019  *
1020  * Returns true if ready and false if busy.
1021  */
1022 static int omap_dev_ready(struct nand_chip *chip)
1023 {
1024         struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1025
1026         return gpiod_get_value(info->ready_gpiod);
1027 }
1028
1029 /**
1030  * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1031  * @mtd: MTD device structure
1032  * @mode: Read/Write mode
1033  *
1034  * When using BCH with SW correction (i.e. no ELM), sector size is set
1035  * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1036  * for both reading and writing with:
1037  * eccsize0 = 0  (no additional protected byte in spare area)
1038  * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1039  */
1040 static void __maybe_unused omap_enable_hwecc_bch(struct nand_chip *chip,
1041                                                  int mode)
1042 {
1043         unsigned int bch_type;
1044         unsigned int dev_width, nsectors;
1045         struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1046         enum omap_ecc ecc_opt = info->ecc_opt;
1047         u32 val, wr_mode;
1048         unsigned int ecc_size1, ecc_size0;
1049
1050         /* GPMC configurations for calculating ECC */
1051         switch (ecc_opt) {
1052         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1053                 bch_type = 0;
1054                 nsectors = 1;
1055                 wr_mode   = BCH_WRAPMODE_6;
1056                 ecc_size0 = BCH_ECC_SIZE0;
1057                 ecc_size1 = BCH_ECC_SIZE1;
1058                 break;
1059         case OMAP_ECC_BCH4_CODE_HW:
1060                 bch_type = 0;
1061                 nsectors = chip->ecc.steps;
1062                 if (mode == NAND_ECC_READ) {
1063                         wr_mode   = BCH_WRAPMODE_1;
1064                         ecc_size0 = BCH4R_ECC_SIZE0;
1065                         ecc_size1 = BCH4R_ECC_SIZE1;
1066                 } else {
1067                         wr_mode   = BCH_WRAPMODE_6;
1068                         ecc_size0 = BCH_ECC_SIZE0;
1069                         ecc_size1 = BCH_ECC_SIZE1;
1070                 }
1071                 break;
1072         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1073                 bch_type = 1;
1074                 nsectors = 1;
1075                 wr_mode   = BCH_WRAPMODE_6;
1076                 ecc_size0 = BCH_ECC_SIZE0;
1077                 ecc_size1 = BCH_ECC_SIZE1;
1078                 break;
1079         case OMAP_ECC_BCH8_CODE_HW:
1080                 bch_type = 1;
1081                 nsectors = chip->ecc.steps;
1082                 if (mode == NAND_ECC_READ) {
1083                         wr_mode   = BCH_WRAPMODE_1;
1084                         ecc_size0 = BCH8R_ECC_SIZE0;
1085                         ecc_size1 = BCH8R_ECC_SIZE1;
1086                 } else {
1087                         wr_mode   = BCH_WRAPMODE_6;
1088                         ecc_size0 = BCH_ECC_SIZE0;
1089                         ecc_size1 = BCH_ECC_SIZE1;
1090                 }
1091                 break;
1092         case OMAP_ECC_BCH16_CODE_HW:
1093                 bch_type = 0x2;
1094                 nsectors = chip->ecc.steps;
1095                 if (mode == NAND_ECC_READ) {
1096                         wr_mode   = 0x01;
1097                         ecc_size0 = 52; /* ECC bits in nibbles per sector */
1098                         ecc_size1 = 0;  /* non-ECC bits in nibbles per sector */
1099                 } else {
1100                         wr_mode   = 0x01;
1101                         ecc_size0 = 0;  /* extra bits in nibbles per sector */
1102                         ecc_size1 = 52; /* OOB bits in nibbles per sector */
1103                 }
1104                 break;
1105         default:
1106                 return;
1107         }
1108
1109         writel(ECC1, info->reg.gpmc_ecc_control);
1110
1111         /* Configure ecc size for BCH */
1112         val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1113         writel(val, info->reg.gpmc_ecc_size_config);
1114
1115         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1116
1117         /* BCH configuration */
1118         val = ((1                        << 16) | /* enable BCH */
1119                (bch_type                 << 12) | /* BCH4/BCH8/BCH16 */
1120                (wr_mode                  <<  8) | /* wrap mode */
1121                (dev_width                <<  7) | /* bus width */
1122                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1123                (info->gpmc_cs            <<  1) | /* ECC CS */
1124                (0x1));                            /* enable ECC */
1125
1126         writel(val, info->reg.gpmc_ecc_config);
1127
1128         /* Clear ecc and enable bits */
1129         writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1130 }
1131
1132 static u8  bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1133 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1134                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
1135
1136 /**
1137  * _omap_calculate_ecc_bch - Generate ECC bytes for one sector
1138  * @mtd:        MTD device structure
1139  * @dat:        The pointer to data on which ecc is computed
1140  * @ecc_code:   The ecc_code buffer
1141  * @i:          The sector number (for a multi sector page)
1142  *
1143  * Support calculating of BCH4/8/16 ECC vectors for one sector
1144  * within a page. Sector number is in @i.
1145  */
1146 static int _omap_calculate_ecc_bch(struct mtd_info *mtd,
1147                                    const u_char *dat, u_char *ecc_calc, int i)
1148 {
1149         struct omap_nand_info *info = mtd_to_omap(mtd);
1150         int eccbytes    = info->nand.ecc.bytes;
1151         struct gpmc_nand_regs   *gpmc_regs = &info->reg;
1152         u8 *ecc_code;
1153         unsigned long bch_val1, bch_val2, bch_val3, bch_val4;
1154         u32 val;
1155         int j;
1156
1157         ecc_code = ecc_calc;
1158         switch (info->ecc_opt) {
1159         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1160         case OMAP_ECC_BCH8_CODE_HW:
1161                 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1162                 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1163                 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1164                 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1165                 *ecc_code++ = (bch_val4 & 0xFF);
1166                 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1167                 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1168                 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1169                 *ecc_code++ = (bch_val3 & 0xFF);
1170                 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1171                 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1172                 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1173                 *ecc_code++ = (bch_val2 & 0xFF);
1174                 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1175                 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1176                 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1177                 *ecc_code++ = (bch_val1 & 0xFF);
1178                 break;
1179         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1180         case OMAP_ECC_BCH4_CODE_HW:
1181                 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1182                 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1183                 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1184                 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1185                 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1186                         ((bch_val1 >> 28) & 0xF);
1187                 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1188                 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1189                 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1190                 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1191                 break;
1192         case OMAP_ECC_BCH16_CODE_HW:
1193                 val = readl(gpmc_regs->gpmc_bch_result6[i]);
1194                 ecc_code[0]  = ((val >>  8) & 0xFF);
1195                 ecc_code[1]  = ((val >>  0) & 0xFF);
1196                 val = readl(gpmc_regs->gpmc_bch_result5[i]);
1197                 ecc_code[2]  = ((val >> 24) & 0xFF);
1198                 ecc_code[3]  = ((val >> 16) & 0xFF);
1199                 ecc_code[4]  = ((val >>  8) & 0xFF);
1200                 ecc_code[5]  = ((val >>  0) & 0xFF);
1201                 val = readl(gpmc_regs->gpmc_bch_result4[i]);
1202                 ecc_code[6]  = ((val >> 24) & 0xFF);
1203                 ecc_code[7]  = ((val >> 16) & 0xFF);
1204                 ecc_code[8]  = ((val >>  8) & 0xFF);
1205                 ecc_code[9]  = ((val >>  0) & 0xFF);
1206                 val = readl(gpmc_regs->gpmc_bch_result3[i]);
1207                 ecc_code[10] = ((val >> 24) & 0xFF);
1208                 ecc_code[11] = ((val >> 16) & 0xFF);
1209                 ecc_code[12] = ((val >>  8) & 0xFF);
1210                 ecc_code[13] = ((val >>  0) & 0xFF);
1211                 val = readl(gpmc_regs->gpmc_bch_result2[i]);
1212                 ecc_code[14] = ((val >> 24) & 0xFF);
1213                 ecc_code[15] = ((val >> 16) & 0xFF);
1214                 ecc_code[16] = ((val >>  8) & 0xFF);
1215                 ecc_code[17] = ((val >>  0) & 0xFF);
1216                 val = readl(gpmc_regs->gpmc_bch_result1[i]);
1217                 ecc_code[18] = ((val >> 24) & 0xFF);
1218                 ecc_code[19] = ((val >> 16) & 0xFF);
1219                 ecc_code[20] = ((val >>  8) & 0xFF);
1220                 ecc_code[21] = ((val >>  0) & 0xFF);
1221                 val = readl(gpmc_regs->gpmc_bch_result0[i]);
1222                 ecc_code[22] = ((val >> 24) & 0xFF);
1223                 ecc_code[23] = ((val >> 16) & 0xFF);
1224                 ecc_code[24] = ((val >>  8) & 0xFF);
1225                 ecc_code[25] = ((val >>  0) & 0xFF);
1226                 break;
1227         default:
1228                 return -EINVAL;
1229         }
1230
1231         /* ECC scheme specific syndrome customizations */
1232         switch (info->ecc_opt) {
1233         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1234                 /* Add constant polynomial to remainder, so that
1235                  * ECC of blank pages results in 0x0 on reading back
1236                  */
1237                 for (j = 0; j < eccbytes; j++)
1238                         ecc_calc[j] ^= bch4_polynomial[j];
1239                 break;
1240         case OMAP_ECC_BCH4_CODE_HW:
1241                 /* Set  8th ECC byte as 0x0 for ROM compatibility */
1242                 ecc_calc[eccbytes - 1] = 0x0;
1243                 break;
1244         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1245                 /* Add constant polynomial to remainder, so that
1246                  * ECC of blank pages results in 0x0 on reading back
1247                  */
1248                 for (j = 0; j < eccbytes; j++)
1249                         ecc_calc[j] ^= bch8_polynomial[j];
1250                 break;
1251         case OMAP_ECC_BCH8_CODE_HW:
1252                 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1253                 ecc_calc[eccbytes - 1] = 0x0;
1254                 break;
1255         case OMAP_ECC_BCH16_CODE_HW:
1256                 break;
1257         default:
1258                 return -EINVAL;
1259         }
1260
1261         return 0;
1262 }
1263
1264 /**
1265  * omap_calculate_ecc_bch_sw - ECC generator for sector for SW based correction
1266  * @chip:       NAND chip object
1267  * @dat:        The pointer to data on which ecc is computed
1268  * @ecc_code:   The ecc_code buffer
1269  *
1270  * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
1271  * when SW based correction is required as ECC is required for one sector
1272  * at a time.
1273  */
1274 static int omap_calculate_ecc_bch_sw(struct nand_chip *chip,
1275                                      const u_char *dat, u_char *ecc_calc)
1276 {
1277         return _omap_calculate_ecc_bch(nand_to_mtd(chip), dat, ecc_calc, 0);
1278 }
1279
1280 /**
1281  * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
1282  * @mtd:        MTD device structure
1283  * @dat:        The pointer to data on which ecc is computed
1284  * @ecc_code:   The ecc_code buffer
1285  *
1286  * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
1287  */
1288 static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd,
1289                                         const u_char *dat, u_char *ecc_calc)
1290 {
1291         struct omap_nand_info *info = mtd_to_omap(mtd);
1292         int eccbytes = info->nand.ecc.bytes;
1293         unsigned long nsectors;
1294         int i, ret;
1295
1296         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1297         for (i = 0; i < nsectors; i++) {
1298                 ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i);
1299                 if (ret)
1300                         return ret;
1301
1302                 ecc_calc += eccbytes;
1303         }
1304
1305         return 0;
1306 }
1307
1308 /**
1309  * erased_sector_bitflips - count bit flips
1310  * @data:       data sector buffer
1311  * @oob:        oob buffer
1312  * @info:       omap_nand_info
1313  *
1314  * Check the bit flips in erased page falls below correctable level.
1315  * If falls below, report the page as erased with correctable bit
1316  * flip, else report as uncorrectable page.
1317  */
1318 static int erased_sector_bitflips(u_char *data, u_char *oob,
1319                 struct omap_nand_info *info)
1320 {
1321         int flip_bits = 0, i;
1322
1323         for (i = 0; i < info->nand.ecc.size; i++) {
1324                 flip_bits += hweight8(~data[i]);
1325                 if (flip_bits > info->nand.ecc.strength)
1326                         return 0;
1327         }
1328
1329         for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1330                 flip_bits += hweight8(~oob[i]);
1331                 if (flip_bits > info->nand.ecc.strength)
1332                         return 0;
1333         }
1334
1335         /*
1336          * Bit flips falls in correctable level.
1337          * Fill data area with 0xFF
1338          */
1339         if (flip_bits) {
1340                 memset(data, 0xFF, info->nand.ecc.size);
1341                 memset(oob, 0xFF, info->nand.ecc.bytes);
1342         }
1343
1344         return flip_bits;
1345 }
1346
1347 /**
1348  * omap_elm_correct_data - corrects page data area in case error reported
1349  * @chip:       NAND chip object
1350  * @data:       page data
1351  * @read_ecc:   ecc read from nand flash
1352  * @calc_ecc:   ecc read from HW ECC registers
1353  *
1354  * Calculated ecc vector reported as zero in case of non-error pages.
1355  * In case of non-zero ecc vector, first filter out erased-pages, and
1356  * then process data via ELM to detect bit-flips.
1357  */
1358 static int omap_elm_correct_data(struct nand_chip *chip, u_char *data,
1359                                  u_char *read_ecc, u_char *calc_ecc)
1360 {
1361         struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1362         struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1363         int eccsteps = info->nand.ecc.steps;
1364         int i , j, stat = 0;
1365         int eccflag, actual_eccbytes;
1366         struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1367         u_char *ecc_vec = calc_ecc;
1368         u_char *spare_ecc = read_ecc;
1369         u_char *erased_ecc_vec;
1370         u_char *buf;
1371         int bitflip_count;
1372         bool is_error_reported = false;
1373         u32 bit_pos, byte_pos, error_max, pos;
1374         int err;
1375
1376         switch (info->ecc_opt) {
1377         case OMAP_ECC_BCH4_CODE_HW:
1378                 /* omit  7th ECC byte reserved for ROM code compatibility */
1379                 actual_eccbytes = ecc->bytes - 1;
1380                 erased_ecc_vec = bch4_vector;
1381                 break;
1382         case OMAP_ECC_BCH8_CODE_HW:
1383                 /* omit 14th ECC byte reserved for ROM code compatibility */
1384                 actual_eccbytes = ecc->bytes - 1;
1385                 erased_ecc_vec = bch8_vector;
1386                 break;
1387         case OMAP_ECC_BCH16_CODE_HW:
1388                 actual_eccbytes = ecc->bytes;
1389                 erased_ecc_vec = bch16_vector;
1390                 break;
1391         default:
1392                 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1393                 return -EINVAL;
1394         }
1395
1396         /* Initialize elm error vector to zero */
1397         memset(err_vec, 0, sizeof(err_vec));
1398
1399         for (i = 0; i < eccsteps ; i++) {
1400                 eccflag = 0;    /* initialize eccflag */
1401
1402                 /*
1403                  * Check any error reported,
1404                  * In case of error, non zero ecc reported.
1405                  */
1406                 for (j = 0; j < actual_eccbytes; j++) {
1407                         if (calc_ecc[j] != 0) {
1408                                 eccflag = 1; /* non zero ecc, error present */
1409                                 break;
1410                         }
1411                 }
1412
1413                 if (eccflag == 1) {
1414                         if (memcmp(calc_ecc, erased_ecc_vec,
1415                                                 actual_eccbytes) == 0) {
1416                                 /*
1417                                  * calc_ecc[] matches pattern for ECC(all 0xff)
1418                                  * so this is definitely an erased-page
1419                                  */
1420                         } else {
1421                                 buf = &data[info->nand.ecc.size * i];
1422                                 /*
1423                                  * count number of 0-bits in read_buf.
1424                                  * This check can be removed once a similar
1425                                  * check is introduced in generic NAND driver
1426                                  */
1427                                 bitflip_count = erased_sector_bitflips(
1428                                                 buf, read_ecc, info);
1429                                 if (bitflip_count) {
1430                                         /*
1431                                          * number of 0-bits within ECC limits
1432                                          * So this may be an erased-page
1433                                          */
1434                                         stat += bitflip_count;
1435                                 } else {
1436                                         /*
1437                                          * Too many 0-bits. It may be a
1438                                          * - programmed-page, OR
1439                                          * - erased-page with many bit-flips
1440                                          * So this page requires check by ELM
1441                                          */
1442                                         err_vec[i].error_reported = true;
1443                                         is_error_reported = true;
1444                                 }
1445                         }
1446                 }
1447
1448                 /* Update the ecc vector */
1449                 calc_ecc += ecc->bytes;
1450                 read_ecc += ecc->bytes;
1451         }
1452
1453         /* Check if any error reported */
1454         if (!is_error_reported)
1455                 return stat;
1456
1457         /* Decode BCH error using ELM module */
1458         elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1459
1460         err = 0;
1461         for (i = 0; i < eccsteps; i++) {
1462                 if (err_vec[i].error_uncorrectable) {
1463                         dev_err(&info->pdev->dev,
1464                                 "uncorrectable bit-flips found\n");
1465                         err = -EBADMSG;
1466                 } else if (err_vec[i].error_reported) {
1467                         for (j = 0; j < err_vec[i].error_count; j++) {
1468                                 switch (info->ecc_opt) {
1469                                 case OMAP_ECC_BCH4_CODE_HW:
1470                                         /* Add 4 bits to take care of padding */
1471                                         pos = err_vec[i].error_loc[j] +
1472                                                 BCH4_BIT_PAD;
1473                                         break;
1474                                 case OMAP_ECC_BCH8_CODE_HW:
1475                                 case OMAP_ECC_BCH16_CODE_HW:
1476                                         pos = err_vec[i].error_loc[j];
1477                                         break;
1478                                 default:
1479                                         return -EINVAL;
1480                                 }
1481                                 error_max = (ecc->size + actual_eccbytes) * 8;
1482                                 /* Calculate bit position of error */
1483                                 bit_pos = pos % 8;
1484
1485                                 /* Calculate byte position of error */
1486                                 byte_pos = (error_max - pos - 1) / 8;
1487
1488                                 if (pos < error_max) {
1489                                         if (byte_pos < 512) {
1490                                                 pr_debug("bitflip@dat[%d]=%x\n",
1491                                                      byte_pos, data[byte_pos]);
1492                                                 data[byte_pos] ^= 1 << bit_pos;
1493                                         } else {
1494                                                 pr_debug("bitflip@oob[%d]=%x\n",
1495                                                         (byte_pos - 512),
1496                                                      spare_ecc[byte_pos - 512]);
1497                                                 spare_ecc[byte_pos - 512] ^=
1498                                                         1 << bit_pos;
1499                                         }
1500                                 } else {
1501                                         dev_err(&info->pdev->dev,
1502                                                 "invalid bit-flip @ %d:%d\n",
1503                                                 byte_pos, bit_pos);
1504                                         err = -EBADMSG;
1505                                 }
1506                         }
1507                 }
1508
1509                 /* Update number of correctable errors */
1510                 stat += err_vec[i].error_count;
1511
1512                 /* Update page data with sector size */
1513                 data += ecc->size;
1514                 spare_ecc += ecc->bytes;
1515         }
1516
1517         return (err) ? err : stat;
1518 }
1519
1520 /**
1521  * omap_write_page_bch - BCH ecc based write page function for entire page
1522  * @chip:               nand chip info structure
1523  * @buf:                data buffer
1524  * @oob_required:       must write chip->oob_poi to OOB
1525  * @page:               page
1526  *
1527  * Custom write page method evolved to support multi sector writing in one shot
1528  */
1529 static int omap_write_page_bch(struct nand_chip *chip, const uint8_t *buf,
1530                                int oob_required, int page)
1531 {
1532         struct mtd_info *mtd = nand_to_mtd(chip);
1533         int ret;
1534         uint8_t *ecc_calc = chip->ecc.calc_buf;
1535
1536         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1537
1538         /* Enable GPMC ecc engine */
1539         chip->ecc.hwctl(chip, NAND_ECC_WRITE);
1540
1541         /* Write data */
1542         chip->legacy.write_buf(chip, buf, mtd->writesize);
1543
1544         /* Update ecc vector from GPMC result registers */
1545         omap_calculate_ecc_bch_multi(mtd, buf, &ecc_calc[0]);
1546
1547         ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
1548                                          chip->ecc.total);
1549         if (ret)
1550                 return ret;
1551
1552         /* Write ecc vector to OOB area */
1553         chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
1554
1555         return nand_prog_page_end_op(chip);
1556 }
1557
1558 /**
1559  * omap_write_subpage_bch - BCH hardware ECC based subpage write
1560  * @chip:       nand chip info structure
1561  * @offset:     column address of subpage within the page
1562  * @data_len:   data length
1563  * @buf:        data buffer
1564  * @oob_required: must write chip->oob_poi to OOB
1565  * @page: page number to write
1566  *
1567  * OMAP optimized subpage write method.
1568  */
1569 static int omap_write_subpage_bch(struct nand_chip *chip, u32 offset,
1570                                   u32 data_len, const u8 *buf,
1571                                   int oob_required, int page)
1572 {
1573         struct mtd_info *mtd = nand_to_mtd(chip);
1574         u8 *ecc_calc = chip->ecc.calc_buf;
1575         int ecc_size      = chip->ecc.size;
1576         int ecc_bytes     = chip->ecc.bytes;
1577         int ecc_steps     = chip->ecc.steps;
1578         u32 start_step = offset / ecc_size;
1579         u32 end_step   = (offset + data_len - 1) / ecc_size;
1580         int step, ret = 0;
1581
1582         /*
1583          * Write entire page at one go as it would be optimal
1584          * as ECC is calculated by hardware.
1585          * ECC is calculated for all subpages but we choose
1586          * only what we want.
1587          */
1588         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1589
1590         /* Enable GPMC ECC engine */
1591         chip->ecc.hwctl(chip, NAND_ECC_WRITE);
1592
1593         /* Write data */
1594         chip->legacy.write_buf(chip, buf, mtd->writesize);
1595
1596         for (step = 0; step < ecc_steps; step++) {
1597                 /* mask ECC of un-touched subpages by padding 0xFF */
1598                 if (step < start_step || step > end_step)
1599                         memset(ecc_calc, 0xff, ecc_bytes);
1600                 else
1601                         ret = _omap_calculate_ecc_bch(mtd, buf, ecc_calc, step);
1602
1603                 if (ret)
1604                         return ret;
1605
1606                 buf += ecc_size;
1607                 ecc_calc += ecc_bytes;
1608         }
1609
1610         /* copy calculated ECC for whole page to chip->buffer->oob */
1611         /* this include masked-value(0xFF) for unwritten subpages */
1612         ecc_calc = chip->ecc.calc_buf;
1613         ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
1614                                          chip->ecc.total);
1615         if (ret)
1616                 return ret;
1617
1618         /* write OOB buffer to NAND device */
1619         chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
1620
1621         return nand_prog_page_end_op(chip);
1622 }
1623
1624 /**
1625  * omap_read_page_bch - BCH ecc based page read function for entire page
1626  * @chip:               nand chip info structure
1627  * @buf:                buffer to store read data
1628  * @oob_required:       caller requires OOB data read to chip->oob_poi
1629  * @page:               page number to read
1630  *
1631  * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1632  * used for error correction.
1633  * Custom method evolved to support ELM error correction & multi sector
1634  * reading. On reading page data area is read along with OOB data with
1635  * ecc engine enabled. ecc vector updated after read of OOB data.
1636  * For non error pages ecc vector reported as zero.
1637  */
1638 static int omap_read_page_bch(struct nand_chip *chip, uint8_t *buf,
1639                               int oob_required, int page)
1640 {
1641         struct mtd_info *mtd = nand_to_mtd(chip);
1642         uint8_t *ecc_calc = chip->ecc.calc_buf;
1643         uint8_t *ecc_code = chip->ecc.code_buf;
1644         int stat, ret;
1645         unsigned int max_bitflips = 0;
1646
1647         nand_read_page_op(chip, page, 0, NULL, 0);
1648
1649         /* Enable GPMC ecc engine */
1650         chip->ecc.hwctl(chip, NAND_ECC_READ);
1651
1652         /* Read data */
1653         chip->legacy.read_buf(chip, buf, mtd->writesize);
1654
1655         /* Read oob bytes */
1656         nand_change_read_column_op(chip,
1657                                    mtd->writesize + BADBLOCK_MARKER_LENGTH,
1658                                    chip->oob_poi + BADBLOCK_MARKER_LENGTH,
1659                                    chip->ecc.total, false);
1660
1661         /* Calculate ecc bytes */
1662         omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc);
1663
1664         ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1665                                          chip->ecc.total);
1666         if (ret)
1667                 return ret;
1668
1669         stat = chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
1670
1671         if (stat < 0) {
1672                 mtd->ecc_stats.failed++;
1673         } else {
1674                 mtd->ecc_stats.corrected += stat;
1675                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1676         }
1677
1678         return max_bitflips;
1679 }
1680
1681 /**
1682  * is_elm_present - checks for presence of ELM module by scanning DT nodes
1683  * @omap_nand_info: NAND device structure containing platform data
1684  */
1685 static bool is_elm_present(struct omap_nand_info *info,
1686                            struct device_node *elm_node)
1687 {
1688         struct platform_device *pdev;
1689
1690         /* check whether elm-id is passed via DT */
1691         if (!elm_node) {
1692                 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1693                 return false;
1694         }
1695         pdev = of_find_device_by_node(elm_node);
1696         /* check whether ELM device is registered */
1697         if (!pdev) {
1698                 dev_err(&info->pdev->dev, "ELM device not found\n");
1699                 return false;
1700         }
1701         /* ELM module available, now configure it */
1702         info->elm_dev = &pdev->dev;
1703         return true;
1704 }
1705
1706 static bool omap2_nand_ecc_check(struct omap_nand_info *info)
1707 {
1708         bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1709
1710         switch (info->ecc_opt) {
1711         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1712         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1713                 ecc_needs_omap_bch = false;
1714                 ecc_needs_bch = true;
1715                 ecc_needs_elm = false;
1716                 break;
1717         case OMAP_ECC_BCH4_CODE_HW:
1718         case OMAP_ECC_BCH8_CODE_HW:
1719         case OMAP_ECC_BCH16_CODE_HW:
1720                 ecc_needs_omap_bch = true;
1721                 ecc_needs_bch = false;
1722                 ecc_needs_elm = true;
1723                 break;
1724         default:
1725                 ecc_needs_omap_bch = false;
1726                 ecc_needs_bch = false;
1727                 ecc_needs_elm = false;
1728                 break;
1729         }
1730
1731         if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) {
1732                 dev_err(&info->pdev->dev,
1733                         "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1734                 return false;
1735         }
1736         if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1737                 dev_err(&info->pdev->dev,
1738                         "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1739                 return false;
1740         }
1741         if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
1742                 dev_err(&info->pdev->dev, "ELM not available\n");
1743                 return false;
1744         }
1745
1746         return true;
1747 }
1748
1749 static const char * const nand_xfer_types[] = {
1750         [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1751         [NAND_OMAP_POLLED] = "polled",
1752         [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1753         [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1754 };
1755
1756 static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info)
1757 {
1758         struct device_node *child = dev->of_node;
1759         int i;
1760         const char *s;
1761         u32 cs;
1762
1763         if (of_property_read_u32(child, "reg", &cs) < 0) {
1764                 dev_err(dev, "reg not found in DT\n");
1765                 return -EINVAL;
1766         }
1767
1768         info->gpmc_cs = cs;
1769
1770         /* detect availability of ELM module. Won't be present pre-OMAP4 */
1771         info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1772         if (!info->elm_of_node) {
1773                 info->elm_of_node = of_parse_phandle(child, "elm_id", 0);
1774                 if (!info->elm_of_node)
1775                         dev_dbg(dev, "ti,elm-id not in DT\n");
1776         }
1777
1778         /* select ecc-scheme for NAND */
1779         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1780                 dev_err(dev, "ti,nand-ecc-opt not found\n");
1781                 return -EINVAL;
1782         }
1783
1784         if (!strcmp(s, "sw")) {
1785                 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1786         } else if (!strcmp(s, "ham1") ||
1787                    !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) {
1788                 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW;
1789         } else if (!strcmp(s, "bch4")) {
1790                 if (info->elm_of_node)
1791                         info->ecc_opt = OMAP_ECC_BCH4_CODE_HW;
1792                 else
1793                         info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1794         } else if (!strcmp(s, "bch8")) {
1795                 if (info->elm_of_node)
1796                         info->ecc_opt = OMAP_ECC_BCH8_CODE_HW;
1797                 else
1798                         info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1799         } else if (!strcmp(s, "bch16")) {
1800                 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW;
1801         } else {
1802                 dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n");
1803                 return -EINVAL;
1804         }
1805
1806         /* select data transfer mode */
1807         if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) {
1808                 for (i = 0; i < ARRAY_SIZE(nand_xfer_types); i++) {
1809                         if (!strcasecmp(s, nand_xfer_types[i])) {
1810                                 info->xfer_type = i;
1811                                 return 0;
1812                         }
1813                 }
1814
1815                 dev_err(dev, "unrecognized value for ti,nand-xfer-type\n");
1816                 return -EINVAL;
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int omap_ooblayout_ecc(struct mtd_info *mtd, int section,
1823                               struct mtd_oob_region *oobregion)
1824 {
1825         struct omap_nand_info *info = mtd_to_omap(mtd);
1826         struct nand_chip *chip = &info->nand;
1827         int off = BADBLOCK_MARKER_LENGTH;
1828
1829         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1830             !(chip->options & NAND_BUSWIDTH_16))
1831                 off = 1;
1832
1833         if (section)
1834                 return -ERANGE;
1835
1836         oobregion->offset = off;
1837         oobregion->length = chip->ecc.total;
1838
1839         return 0;
1840 }
1841
1842 static int omap_ooblayout_free(struct mtd_info *mtd, int section,
1843                                struct mtd_oob_region *oobregion)
1844 {
1845         struct omap_nand_info *info = mtd_to_omap(mtd);
1846         struct nand_chip *chip = &info->nand;
1847         int off = BADBLOCK_MARKER_LENGTH;
1848
1849         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1850             !(chip->options & NAND_BUSWIDTH_16))
1851                 off = 1;
1852
1853         if (section)
1854                 return -ERANGE;
1855
1856         off += chip->ecc.total;
1857         if (off >= mtd->oobsize)
1858                 return -ERANGE;
1859
1860         oobregion->offset = off;
1861         oobregion->length = mtd->oobsize - off;
1862
1863         return 0;
1864 }
1865
1866 static const struct mtd_ooblayout_ops omap_ooblayout_ops = {
1867         .ecc = omap_ooblayout_ecc,
1868         .free = omap_ooblayout_free,
1869 };
1870
1871 static int omap_sw_ooblayout_ecc(struct mtd_info *mtd, int section,
1872                                  struct mtd_oob_region *oobregion)
1873 {
1874         struct nand_chip *chip = mtd_to_nand(mtd);
1875         int off = BADBLOCK_MARKER_LENGTH;
1876
1877         if (section >= chip->ecc.steps)
1878                 return -ERANGE;
1879
1880         /*
1881          * When SW correction is employed, one OMAP specific marker byte is
1882          * reserved after each ECC step.
1883          */
1884         oobregion->offset = off + (section * (chip->ecc.bytes + 1));
1885         oobregion->length = chip->ecc.bytes;
1886
1887         return 0;
1888 }
1889
1890 static int omap_sw_ooblayout_free(struct mtd_info *mtd, int section,
1891                                   struct mtd_oob_region *oobregion)
1892 {
1893         struct nand_chip *chip = mtd_to_nand(mtd);
1894         int off = BADBLOCK_MARKER_LENGTH;
1895
1896         if (section)
1897                 return -ERANGE;
1898
1899         /*
1900          * When SW correction is employed, one OMAP specific marker byte is
1901          * reserved after each ECC step.
1902          */
1903         off += ((chip->ecc.bytes + 1) * chip->ecc.steps);
1904         if (off >= mtd->oobsize)
1905                 return -ERANGE;
1906
1907         oobregion->offset = off;
1908         oobregion->length = mtd->oobsize - off;
1909
1910         return 0;
1911 }
1912
1913 static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = {
1914         .ecc = omap_sw_ooblayout_ecc,
1915         .free = omap_sw_ooblayout_free,
1916 };
1917
1918 static int omap_nand_attach_chip(struct nand_chip *chip)
1919 {
1920         struct mtd_info *mtd = nand_to_mtd(chip);
1921         struct omap_nand_info *info = mtd_to_omap(mtd);
1922         struct device *dev = &info->pdev->dev;
1923         int min_oobbytes = BADBLOCK_MARKER_LENGTH;
1924         int oobbytes_per_step;
1925         dma_cap_mask_t mask;
1926         int err;
1927
1928         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1929                 chip->bbt_options |= NAND_BBT_NO_OOB;
1930         else
1931                 chip->options |= NAND_SKIP_BBTSCAN;
1932
1933         /* Re-populate low-level callbacks based on xfer modes */
1934         switch (info->xfer_type) {
1935         case NAND_OMAP_PREFETCH_POLLED:
1936                 chip->legacy.read_buf = omap_read_buf_pref;
1937                 chip->legacy.write_buf = omap_write_buf_pref;
1938                 break;
1939
1940         case NAND_OMAP_POLLED:
1941                 /* Use nand_base defaults for {read,write}_buf */
1942                 break;
1943
1944         case NAND_OMAP_PREFETCH_DMA:
1945                 dma_cap_zero(mask);
1946                 dma_cap_set(DMA_SLAVE, mask);
1947                 info->dma = dma_request_chan(dev->parent, "rxtx");
1948
1949                 if (IS_ERR(info->dma)) {
1950                         dev_err(dev, "DMA engine request failed\n");
1951                         return PTR_ERR(info->dma);
1952                 } else {
1953                         struct dma_slave_config cfg;
1954
1955                         memset(&cfg, 0, sizeof(cfg));
1956                         cfg.src_addr = info->phys_base;
1957                         cfg.dst_addr = info->phys_base;
1958                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1959                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1960                         cfg.src_maxburst = 16;
1961                         cfg.dst_maxburst = 16;
1962                         err = dmaengine_slave_config(info->dma, &cfg);
1963                         if (err) {
1964                                 dev_err(dev,
1965                                         "DMA engine slave config failed: %d\n",
1966                                         err);
1967                                 return err;
1968                         }
1969                         chip->legacy.read_buf = omap_read_buf_dma_pref;
1970                         chip->legacy.write_buf = omap_write_buf_dma_pref;
1971                 }
1972                 break;
1973
1974         case NAND_OMAP_PREFETCH_IRQ:
1975                 info->gpmc_irq_fifo = platform_get_irq(info->pdev, 0);
1976                 if (info->gpmc_irq_fifo <= 0) {
1977                         dev_err(dev, "Error getting fifo IRQ\n");
1978                         return -ENODEV;
1979                 }
1980                 err = devm_request_irq(dev, info->gpmc_irq_fifo,
1981                                        omap_nand_irq, IRQF_SHARED,
1982                                        "gpmc-nand-fifo", info);
1983                 if (err) {
1984                         dev_err(dev, "Requesting IRQ %d, error %d\n",
1985                                 info->gpmc_irq_fifo, err);
1986                         info->gpmc_irq_fifo = 0;
1987                         return err;
1988                 }
1989
1990                 info->gpmc_irq_count = platform_get_irq(info->pdev, 1);
1991                 if (info->gpmc_irq_count <= 0) {
1992                         dev_err(dev, "Error getting IRQ count\n");
1993                         return -ENODEV;
1994                 }
1995                 err = devm_request_irq(dev, info->gpmc_irq_count,
1996                                        omap_nand_irq, IRQF_SHARED,
1997                                        "gpmc-nand-count", info);
1998                 if (err) {
1999                         dev_err(dev, "Requesting IRQ %d, error %d\n",
2000                                 info->gpmc_irq_count, err);
2001                         info->gpmc_irq_count = 0;
2002                         return err;
2003                 }
2004
2005                 chip->legacy.read_buf = omap_read_buf_irq_pref;
2006                 chip->legacy.write_buf = omap_write_buf_irq_pref;
2007
2008                 break;
2009
2010         default:
2011                 dev_err(dev, "xfer_type %d not supported!\n", info->xfer_type);
2012                 return -EINVAL;
2013         }
2014
2015         if (!omap2_nand_ecc_check(info))
2016                 return -EINVAL;
2017
2018         /*
2019          * Bail out earlier to let NAND_ECC_SOFT code create its own
2020          * ooblayout instead of using ours.
2021          */
2022         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
2023                 chip->ecc.mode = NAND_ECC_SOFT;
2024                 chip->ecc.algo = NAND_ECC_HAMMING;
2025                 return 0;
2026         }
2027
2028         /* Populate MTD interface based on ECC scheme */
2029         switch (info->ecc_opt) {
2030         case OMAP_ECC_HAM1_CODE_HW:
2031                 dev_info(dev, "nand: using OMAP_ECC_HAM1_CODE_HW\n");
2032                 chip->ecc.mode          = NAND_ECC_HW;
2033                 chip->ecc.bytes         = 3;
2034                 chip->ecc.size          = 512;
2035                 chip->ecc.strength      = 1;
2036                 chip->ecc.calculate     = omap_calculate_ecc;
2037                 chip->ecc.hwctl         = omap_enable_hwecc;
2038                 chip->ecc.correct       = omap_correct_data;
2039                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2040                 oobbytes_per_step       = chip->ecc.bytes;
2041
2042                 if (!(chip->options & NAND_BUSWIDTH_16))
2043                         min_oobbytes    = 1;
2044
2045                 break;
2046
2047         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
2048                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
2049                 chip->ecc.mode          = NAND_ECC_HW;
2050                 chip->ecc.size          = 512;
2051                 chip->ecc.bytes         = 7;
2052                 chip->ecc.strength      = 4;
2053                 chip->ecc.hwctl         = omap_enable_hwecc_bch;
2054                 chip->ecc.correct       = nand_bch_correct_data;
2055                 chip->ecc.calculate     = omap_calculate_ecc_bch_sw;
2056                 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2057                 /* Reserve one byte for the OMAP marker */
2058                 oobbytes_per_step       = chip->ecc.bytes + 1;
2059                 /* Software BCH library is used for locating errors */
2060                 chip->ecc.priv          = nand_bch_init(mtd);
2061                 if (!chip->ecc.priv) {
2062                         dev_err(dev, "Unable to use BCH library\n");
2063                         return -EINVAL;
2064                 }
2065                 break;
2066
2067         case OMAP_ECC_BCH4_CODE_HW:
2068                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
2069                 chip->ecc.mode          = NAND_ECC_HW;
2070                 chip->ecc.size          = 512;
2071                 /* 14th bit is kept reserved for ROM-code compatibility */
2072                 chip->ecc.bytes         = 7 + 1;
2073                 chip->ecc.strength      = 4;
2074                 chip->ecc.hwctl         = omap_enable_hwecc_bch;
2075                 chip->ecc.correct       = omap_elm_correct_data;
2076                 chip->ecc.read_page     = omap_read_page_bch;
2077                 chip->ecc.write_page    = omap_write_page_bch;
2078                 chip->ecc.write_subpage = omap_write_subpage_bch;
2079                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2080                 oobbytes_per_step       = chip->ecc.bytes;
2081
2082                 err = elm_config(info->elm_dev, BCH4_ECC,
2083                                  mtd->writesize / chip->ecc.size,
2084                                  chip->ecc.size, chip->ecc.bytes);
2085                 if (err < 0)
2086                         return err;
2087                 break;
2088
2089         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
2090                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
2091                 chip->ecc.mode          = NAND_ECC_HW;
2092                 chip->ecc.size          = 512;
2093                 chip->ecc.bytes         = 13;
2094                 chip->ecc.strength      = 8;
2095                 chip->ecc.hwctl         = omap_enable_hwecc_bch;
2096                 chip->ecc.correct       = nand_bch_correct_data;
2097                 chip->ecc.calculate     = omap_calculate_ecc_bch_sw;
2098                 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2099                 /* Reserve one byte for the OMAP marker */
2100                 oobbytes_per_step       = chip->ecc.bytes + 1;
2101                 /* Software BCH library is used for locating errors */
2102                 chip->ecc.priv          = nand_bch_init(mtd);
2103                 if (!chip->ecc.priv) {
2104                         dev_err(dev, "unable to use BCH library\n");
2105                         return -EINVAL;
2106                 }
2107                 break;
2108
2109         case OMAP_ECC_BCH8_CODE_HW:
2110                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
2111                 chip->ecc.mode          = NAND_ECC_HW;
2112                 chip->ecc.size          = 512;
2113                 /* 14th bit is kept reserved for ROM-code compatibility */
2114                 chip->ecc.bytes         = 13 + 1;
2115                 chip->ecc.strength      = 8;
2116                 chip->ecc.hwctl         = omap_enable_hwecc_bch;
2117                 chip->ecc.correct       = omap_elm_correct_data;
2118                 chip->ecc.read_page     = omap_read_page_bch;
2119                 chip->ecc.write_page    = omap_write_page_bch;
2120                 chip->ecc.write_subpage = omap_write_subpage_bch;
2121                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2122                 oobbytes_per_step       = chip->ecc.bytes;
2123
2124                 err = elm_config(info->elm_dev, BCH8_ECC,
2125                                  mtd->writesize / chip->ecc.size,
2126                                  chip->ecc.size, chip->ecc.bytes);
2127                 if (err < 0)
2128                         return err;
2129
2130                 break;
2131
2132         case OMAP_ECC_BCH16_CODE_HW:
2133                 pr_info("Using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
2134                 chip->ecc.mode          = NAND_ECC_HW;
2135                 chip->ecc.size          = 512;
2136                 chip->ecc.bytes         = 26;
2137                 chip->ecc.strength      = 16;
2138                 chip->ecc.hwctl         = omap_enable_hwecc_bch;
2139                 chip->ecc.correct       = omap_elm_correct_data;
2140                 chip->ecc.read_page     = omap_read_page_bch;
2141                 chip->ecc.write_page    = omap_write_page_bch;
2142                 chip->ecc.write_subpage = omap_write_subpage_bch;
2143                 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2144                 oobbytes_per_step       = chip->ecc.bytes;
2145
2146                 err = elm_config(info->elm_dev, BCH16_ECC,
2147                                  mtd->writesize / chip->ecc.size,
2148                                  chip->ecc.size, chip->ecc.bytes);
2149                 if (err < 0)
2150                         return err;
2151
2152                 break;
2153         default:
2154                 dev_err(dev, "Invalid or unsupported ECC scheme\n");
2155                 return -EINVAL;
2156         }
2157
2158         /* Check if NAND device's OOB is enough to store ECC signatures */
2159         min_oobbytes += (oobbytes_per_step *
2160                          (mtd->writesize / chip->ecc.size));
2161         if (mtd->oobsize < min_oobbytes) {
2162                 dev_err(dev,
2163                         "Not enough OOB bytes: required = %d, available=%d\n",
2164                         min_oobbytes, mtd->oobsize);
2165                 return -EINVAL;
2166         }
2167
2168         return 0;
2169 }
2170
2171 static const struct nand_controller_ops omap_nand_controller_ops = {
2172         .attach_chip = omap_nand_attach_chip,
2173 };
2174
2175 /* Shared among all NAND instances to synchronize access to the ECC Engine */
2176 static struct nand_controller omap_gpmc_controller;
2177 static bool omap_gpmc_controller_initialized;
2178
2179 static int omap_nand_probe(struct platform_device *pdev)
2180 {
2181         struct omap_nand_info           *info;
2182         struct mtd_info                 *mtd;
2183         struct nand_chip                *nand_chip;
2184         int                             err;
2185         struct resource                 *res;
2186         struct device                   *dev = &pdev->dev;
2187
2188         info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
2189                                 GFP_KERNEL);
2190         if (!info)
2191                 return -ENOMEM;
2192
2193         info->pdev = pdev;
2194
2195         err = omap_get_dt_info(dev, info);
2196         if (err)
2197                 return err;
2198
2199         info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
2200         if (!info->ops) {
2201                 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
2202                 return -ENODEV;
2203         }
2204
2205         nand_chip               = &info->nand;
2206         mtd                     = nand_to_mtd(nand_chip);
2207         mtd->dev.parent         = &pdev->dev;
2208         nand_chip->ecc.priv     = NULL;
2209         nand_set_flash_node(nand_chip, dev->of_node);
2210
2211         if (!mtd->name) {
2212                 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
2213                                            "omap2-nand.%d", info->gpmc_cs);
2214                 if (!mtd->name) {
2215                         dev_err(&pdev->dev, "Failed to set MTD name\n");
2216                         return -ENOMEM;
2217                 }
2218         }
2219
2220         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2221         nand_chip->legacy.IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
2222         if (IS_ERR(nand_chip->legacy.IO_ADDR_R))
2223                 return PTR_ERR(nand_chip->legacy.IO_ADDR_R);
2224
2225         info->phys_base = res->start;
2226
2227         if (!omap_gpmc_controller_initialized) {
2228                 omap_gpmc_controller.ops = &omap_nand_controller_ops;
2229                 nand_controller_init(&omap_gpmc_controller);
2230                 omap_gpmc_controller_initialized = true;
2231         }
2232
2233         nand_chip->controller = &omap_gpmc_controller;
2234
2235         nand_chip->legacy.IO_ADDR_W = nand_chip->legacy.IO_ADDR_R;
2236         nand_chip->legacy.cmd_ctrl  = omap_hwcontrol;
2237
2238         info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb",
2239                                                     GPIOD_IN);
2240         if (IS_ERR(info->ready_gpiod)) {
2241                 dev_err(dev, "failed to get ready gpio\n");
2242                 return PTR_ERR(info->ready_gpiod);
2243         }
2244
2245         /*
2246          * If RDY/BSY line is connected to OMAP then use the omap ready
2247          * function and the generic nand_wait function which reads the status
2248          * register after monitoring the RDY/BSY line. Otherwise use a standard
2249          * chip delay which is slightly more than tR (AC Timing) of the NAND
2250          * device and read status register until you get a failure or success
2251          */
2252         if (info->ready_gpiod) {
2253                 nand_chip->legacy.dev_ready = omap_dev_ready;
2254                 nand_chip->legacy.chip_delay = 0;
2255         } else {
2256                 nand_chip->legacy.waitfunc = omap_wait;
2257                 nand_chip->legacy.chip_delay = 50;
2258         }
2259
2260         if (info->flash_bbt)
2261                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2262
2263         /* scan NAND device connected to chip controller */
2264         nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
2265
2266         err = nand_scan(nand_chip, 1);
2267         if (err)
2268                 goto return_error;
2269
2270         err = mtd_device_register(mtd, NULL, 0);
2271         if (err)
2272                 goto cleanup_nand;
2273
2274         platform_set_drvdata(pdev, mtd);
2275
2276         return 0;
2277
2278 cleanup_nand:
2279         nand_cleanup(nand_chip);
2280
2281 return_error:
2282         if (!IS_ERR_OR_NULL(info->dma))
2283                 dma_release_channel(info->dma);
2284         if (nand_chip->ecc.priv) {
2285                 nand_bch_free(nand_chip->ecc.priv);
2286                 nand_chip->ecc.priv = NULL;
2287         }
2288         return err;
2289 }
2290
2291 static int omap_nand_remove(struct platform_device *pdev)
2292 {
2293         struct mtd_info *mtd = platform_get_drvdata(pdev);
2294         struct nand_chip *nand_chip = mtd_to_nand(mtd);
2295         struct omap_nand_info *info = mtd_to_omap(mtd);
2296         if (nand_chip->ecc.priv) {
2297                 nand_bch_free(nand_chip->ecc.priv);
2298                 nand_chip->ecc.priv = NULL;
2299         }
2300         if (info->dma)
2301                 dma_release_channel(info->dma);
2302         nand_release(nand_chip);
2303         return 0;
2304 }
2305
2306 static const struct of_device_id omap_nand_ids[] = {
2307         { .compatible = "ti,omap2-nand", },
2308         {},
2309 };
2310 MODULE_DEVICE_TABLE(of, omap_nand_ids);
2311
2312 static struct platform_driver omap_nand_driver = {
2313         .probe          = omap_nand_probe,
2314         .remove         = omap_nand_remove,
2315         .driver         = {
2316                 .name   = DRIVER_NAME,
2317                 .of_match_table = of_match_ptr(omap_nand_ids),
2318         },
2319 };
2320
2321 module_platform_driver(omap_nand_driver);
2322
2323 MODULE_ALIAS("platform:" DRIVER_NAME);
2324 MODULE_LICENSE("GPL");
2325 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");