2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
20 #include <linux/slab.h>
21 #include <linux/sort.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/of_platform.h>
25 #include <linux/spi/flash.h>
26 #include <linux/mtd/spi-nor.h>
28 /* Define max times to check status register before we give up. */
31 * For everything but full-chip erase; probably could be much smaller, but kept
32 * around for safety for now
34 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
37 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
40 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
42 #define SPI_NOR_MAX_ID_LEN 6
43 #define SPI_NOR_MAX_ADDR_WIDTH 4
49 * This array stores the ID bytes.
50 * The first three bytes are the JEDIC ID.
51 * JEDEC ID zero means "no ID" (mostly older chips).
53 u8 id[SPI_NOR_MAX_ID_LEN];
56 /* The size listed here is what works with SPINOR_OP_SE, which isn't
57 * necessarily called a "sector" by the vendor.
66 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
67 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
68 #define SST_WRITE BIT(2) /* use SST byte programming */
69 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
70 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
71 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
72 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
73 #define USE_FSR BIT(7) /* use flag status register */
74 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
75 #define SPI_NOR_HAS_TB BIT(9) /*
76 * Flash SR has Top/Bottom (TB) protect
77 * bit. Must be used with
80 #define SPI_S3AN BIT(10) /*
81 * Xilinx Spartan 3AN In-System Flash
82 * (MFR cannot be used for probing
83 * because it has the same value as
86 #define SPI_NOR_4B_OPCODES BIT(11) /*
87 * Use dedicated 4byte address op codes
88 * to support memory size above 128Mib.
90 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
91 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
92 #define USE_CLSR BIT(14) /* use CLSR command */
94 int (*quad_enable)(struct spi_nor *nor);
97 #define JEDEC_MFR(info) ((info)->id[0])
99 static const struct flash_info *spi_nor_match_id(const char *name);
102 * Read the status register, returning its value in the location
103 * Return the status register value.
104 * Returns negative if error occurred.
106 static int read_sr(struct spi_nor *nor)
111 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
113 pr_err("error %d reading SR\n", (int) ret);
121 * Read the flag status register, returning its value in the location
122 * Return the status register value.
123 * Returns negative if error occurred.
125 static int read_fsr(struct spi_nor *nor)
130 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
132 pr_err("error %d reading FSR\n", ret);
140 * Read configuration register, returning its value in the
141 * location. Return the configuration register value.
142 * Returns negative if error occurred.
144 static int read_cr(struct spi_nor *nor)
149 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
151 dev_err(nor->dev, "error %d reading CR\n", ret);
159 * Write status register 1 byte
160 * Returns negative if error occurred.
162 static inline int write_sr(struct spi_nor *nor, u8 val)
164 nor->cmd_buf[0] = val;
165 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
169 * Set write enable latch with Write Enable command.
170 * Returns negative if error occurred.
172 static inline int write_enable(struct spi_nor *nor)
174 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
178 * Send write disable instruction to the chip.
180 static inline int write_disable(struct spi_nor *nor)
182 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
185 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
191 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
195 for (i = 0; i < size; i++)
196 if (table[i][0] == opcode)
199 /* No conversion found, keep input op code. */
203 static inline u8 spi_nor_convert_3to4_read(u8 opcode)
205 static const u8 spi_nor_3to4_read[][2] = {
206 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
207 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
208 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
209 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
210 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
211 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
213 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
214 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
215 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
218 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
219 ARRAY_SIZE(spi_nor_3to4_read));
222 static inline u8 spi_nor_convert_3to4_program(u8 opcode)
224 static const u8 spi_nor_3to4_program[][2] = {
225 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
226 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
227 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
230 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
231 ARRAY_SIZE(spi_nor_3to4_program));
234 static inline u8 spi_nor_convert_3to4_erase(u8 opcode)
236 static const u8 spi_nor_3to4_erase[][2] = {
237 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
238 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
239 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
242 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
243 ARRAY_SIZE(spi_nor_3to4_erase));
246 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
247 const struct flash_info *info)
249 /* Do some manufacturer fixups first */
250 switch (JEDEC_MFR(info)) {
251 case SNOR_MFR_SPANSION:
252 /* No small sector erase for 4-byte command set */
253 nor->erase_opcode = SPINOR_OP_SE;
254 nor->mtd.erasesize = info->sector_size;
261 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
262 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
263 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
265 if (!spi_nor_has_uniform_erase(nor)) {
266 struct spi_nor_erase_map *map = &nor->erase_map;
267 struct spi_nor_erase_type *erase;
270 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
271 erase = &map->erase_type[i];
273 spi_nor_convert_3to4_erase(erase->opcode);
278 /* Enable/disable 4-byte addressing mode. */
279 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
283 bool need_wren = false;
286 switch (JEDEC_MFR(info)) {
287 case SNOR_MFR_MICRON:
288 /* Some Micron need WREN command; all will accept it */
290 case SNOR_MFR_MACRONIX:
291 case SNOR_MFR_WINBOND:
295 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
296 status = nor->write_reg(nor, cmd, NULL, 0);
300 if (!status && !enable &&
301 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
303 * On Winbond W25Q256FV, leaving 4byte mode causes
304 * the Extended Address Register to be set to 1, so all
305 * 3-byte-address reads come from the second 16M.
306 * We must clear the register to enable normal behavior.
310 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
317 nor->cmd_buf[0] = enable << 7;
318 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
322 static int s3an_sr_ready(struct spi_nor *nor)
327 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
329 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
333 return !!(val & XSR_RDY);
336 static inline int spi_nor_sr_ready(struct spi_nor *nor)
338 int sr = read_sr(nor);
342 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
344 dev_err(nor->dev, "Erase Error occurred\n");
346 dev_err(nor->dev, "Programming Error occurred\n");
348 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
352 return !(sr & SR_WIP);
355 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
357 int fsr = read_fsr(nor);
361 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
363 dev_err(nor->dev, "Erase operation failed.\n");
365 dev_err(nor->dev, "Program operation failed.\n");
367 if (fsr & FSR_PT_ERR)
369 "Attempted to modify a protected sector.\n");
371 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
375 return fsr & FSR_READY;
378 static int spi_nor_ready(struct spi_nor *nor)
382 if (nor->flags & SNOR_F_READY_XSR_RDY)
383 sr = s3an_sr_ready(nor);
385 sr = spi_nor_sr_ready(nor);
388 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
395 * Service routine to read status register until ready, or timeout occurs.
396 * Returns non-zero if error.
398 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
399 unsigned long timeout_jiffies)
401 unsigned long deadline;
402 int timeout = 0, ret;
404 deadline = jiffies + timeout_jiffies;
407 if (time_after_eq(jiffies, deadline))
410 ret = spi_nor_ready(nor);
419 dev_err(nor->dev, "flash operation timed out\n");
424 static int spi_nor_wait_till_ready(struct spi_nor *nor)
426 return spi_nor_wait_till_ready_with_timeout(nor,
427 DEFAULT_READY_WAIT_JIFFIES);
431 * Erase the whole flash memory
433 * Returns 0 if successful, non-zero otherwise.
435 static int erase_chip(struct spi_nor *nor)
437 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
439 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
442 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
446 mutex_lock(&nor->lock);
449 ret = nor->prepare(nor, ops);
451 dev_err(nor->dev, "failed in the preparation.\n");
452 mutex_unlock(&nor->lock);
459 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
462 nor->unprepare(nor, ops);
463 mutex_unlock(&nor->lock);
467 * This code converts an address to the Default Address Mode, that has non
468 * power of two page sizes. We must support this mode because it is the default
469 * mode supported by Xilinx tools, it can access the whole flash area and
470 * changing over to the Power-of-two mode is irreversible and corrupts the
472 * Addr can safely be unsigned int, the biggest S3AN device is smaller than
475 static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
480 offset = addr % nor->page_size;
481 page = addr / nor->page_size;
482 page <<= (nor->page_size > 512) ? 10 : 9;
484 return page | offset;
488 * Initiate the erasure of a single sector
490 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
492 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
495 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
496 addr = spi_nor_s3an_addr_convert(nor, addr);
499 return nor->erase(nor, addr);
502 * Default implementation, if driver doesn't have a specialized HW
505 for (i = nor->addr_width - 1; i >= 0; i--) {
506 buf[i] = addr & 0xff;
510 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
514 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
515 * @erase: pointer to a structure that describes a SPI NOR erase type
516 * @dividend: dividend value
517 * @remainder: pointer to u32 remainder (will be updated)
519 * Return: the result of the division
521 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
522 u64 dividend, u32 *remainder)
524 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
525 *remainder = (u32)dividend & erase->size_mask;
526 return dividend >> erase->size_shift;
530 * spi_nor_find_best_erase_type() - find the best erase type for the given
531 * offset in the serial flash memory and the
532 * number of bytes to erase. The region in
533 * which the address fits is expected to be
535 * @map: the erase map of the SPI NOR
536 * @region: pointer to a structure that describes a SPI NOR erase region
537 * @addr: offset in the serial flash memory
538 * @len: number of bytes to erase
540 * Return: a pointer to the best fitted erase type, NULL otherwise.
542 static const struct spi_nor_erase_type *
543 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
544 const struct spi_nor_erase_region *region,
547 const struct spi_nor_erase_type *erase;
550 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
553 * Erase types are ordered by size, with the biggest erase type at
556 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
557 /* Does the erase region support the tested erase type? */
558 if (!(erase_mask & BIT(i)))
561 erase = &map->erase_type[i];
563 /* Don't erase more than what the user has asked for. */
564 if (erase->size > len)
567 /* Alignment is not mandatory for overlaid regions */
568 if (region->offset & SNOR_OVERLAID_REGION)
571 spi_nor_div_by_erase_size(erase, addr, &rem);
582 * spi_nor_region_next() - get the next spi nor region
583 * @region: pointer to a structure that describes a SPI NOR erase region
585 * Return: the next spi nor region or NULL if last region.
587 static struct spi_nor_erase_region *
588 spi_nor_region_next(struct spi_nor_erase_region *region)
590 if (spi_nor_region_is_last(region))
597 * spi_nor_find_erase_region() - find the region of the serial flash memory in
598 * which the offset fits
599 * @map: the erase map of the SPI NOR
600 * @addr: offset in the serial flash memory
602 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
605 static struct spi_nor_erase_region *
606 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
608 struct spi_nor_erase_region *region = map->regions;
609 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
610 u64 region_end = region_start + region->size;
612 while (addr < region_start || addr >= region_end) {
613 region = spi_nor_region_next(region);
615 return ERR_PTR(-EINVAL);
617 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
618 region_end = region_start + region->size;
625 * spi_nor_init_erase_cmd() - initialize an erase command
626 * @region: pointer to a structure that describes a SPI NOR erase region
627 * @erase: pointer to a structure that describes a SPI NOR erase type
629 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
632 static struct spi_nor_erase_command *
633 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
634 const struct spi_nor_erase_type *erase)
636 struct spi_nor_erase_command *cmd;
638 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
640 return ERR_PTR(-ENOMEM);
642 INIT_LIST_HEAD(&cmd->list);
643 cmd->opcode = erase->opcode;
646 if (region->offset & SNOR_OVERLAID_REGION)
647 cmd->size = region->size;
649 cmd->size = erase->size;
655 * spi_nor_destroy_erase_cmd_list() - destroy erase command list
656 * @erase_list: list of erase commands
658 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
660 struct spi_nor_erase_command *cmd, *next;
662 list_for_each_entry_safe(cmd, next, erase_list, list) {
663 list_del(&cmd->list);
669 * spi_nor_init_erase_cmd_list() - initialize erase command list
670 * @nor: pointer to a 'struct spi_nor'
671 * @erase_list: list of erase commands to be executed once we validate that the
672 * erase can be performed
673 * @addr: offset in the serial flash memory
674 * @len: number of bytes to erase
676 * Builds the list of best fitted erase commands and verifies if the erase can
679 * Return: 0 on success, -errno otherwise.
681 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
682 struct list_head *erase_list,
685 const struct spi_nor_erase_map *map = &nor->erase_map;
686 const struct spi_nor_erase_type *erase, *prev_erase = NULL;
687 struct spi_nor_erase_region *region;
688 struct spi_nor_erase_command *cmd = NULL;
692 region = spi_nor_find_erase_region(map, addr);
694 return PTR_ERR(region);
696 region_end = spi_nor_region_end(region);
699 erase = spi_nor_find_best_erase_type(map, region, addr, len);
701 goto destroy_erase_cmd_list;
703 if (prev_erase != erase ||
704 region->offset & SNOR_OVERLAID_REGION) {
705 cmd = spi_nor_init_erase_cmd(region, erase);
708 goto destroy_erase_cmd_list;
711 list_add_tail(&cmd->list, erase_list);
719 if (len && addr >= region_end) {
720 region = spi_nor_region_next(region);
722 goto destroy_erase_cmd_list;
723 region_end = spi_nor_region_end(region);
731 destroy_erase_cmd_list:
732 spi_nor_destroy_erase_cmd_list(erase_list);
737 * spi_nor_erase_multi_sectors() - perform a non-uniform erase
738 * @nor: pointer to a 'struct spi_nor'
739 * @addr: offset in the serial flash memory
740 * @len: number of bytes to erase
742 * Build a list of best fitted erase commands and execute it once we validate
743 * that the erase can be performed.
745 * Return: 0 on success, -errno otherwise.
747 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
749 LIST_HEAD(erase_list);
750 struct spi_nor_erase_command *cmd, *next;
753 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
757 list_for_each_entry_safe(cmd, next, &erase_list, list) {
758 nor->erase_opcode = cmd->opcode;
762 ret = spi_nor_erase_sector(nor, addr);
764 goto destroy_erase_cmd_list;
769 ret = spi_nor_wait_till_ready(nor);
771 goto destroy_erase_cmd_list;
773 list_del(&cmd->list);
779 destroy_erase_cmd_list:
780 spi_nor_destroy_erase_cmd_list(&erase_list);
785 * Erase an address range on the nor chip. The address range may extend
786 * one or more erase sectors. Return an error is there is a problem erasing.
788 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
790 struct spi_nor *nor = mtd_to_spi_nor(mtd);
795 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
796 (long long)instr->len);
798 if (spi_nor_has_uniform_erase(nor)) {
799 div_u64_rem(instr->len, mtd->erasesize, &rem);
807 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
811 /* whole-chip erase? */
812 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
813 unsigned long timeout;
817 if (erase_chip(nor)) {
823 * Scale the timeout linearly with the size of the flash, with
824 * a minimum calibrated to an old 2MB flash. We could try to
825 * pull these from CFI/SFDP, but these values should be good
828 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
829 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
830 (unsigned long)(mtd->size / SZ_2M));
831 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
835 /* REVISIT in some cases we could speed up erasing large regions
836 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
837 * to use "small sector erase", but that's not always optimal.
840 /* "sector"-at-a-time erase */
841 } else if (spi_nor_has_uniform_erase(nor)) {
845 ret = spi_nor_erase_sector(nor, addr);
849 addr += mtd->erasesize;
850 len -= mtd->erasesize;
852 ret = spi_nor_wait_till_ready(nor);
857 /* erase multiple sectors */
859 ret = spi_nor_erase_multi_sectors(nor, addr, len);
867 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
872 /* Write status register and ensure bits in mask match written values */
873 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
878 ret = write_sr(nor, status_new);
882 ret = spi_nor_wait_till_ready(nor);
890 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
893 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
896 struct mtd_info *mtd = &nor->mtd;
897 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
898 int shift = ffs(mask) - 1;
906 pow = ((sr & mask) ^ mask) >> shift;
907 *len = mtd->size >> pow;
908 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
911 *ofs = mtd->size - *len;
916 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
917 * @locked is false); 0 otherwise
919 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
928 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
931 /* Requested range is a sub-range of locked range */
932 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
934 /* Requested range does not overlap with locked range */
935 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
938 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
941 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
944 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
947 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
951 * Lock a region of the flash. Compatible with ST Micro and similar flash.
952 * Supports the block protection bits BP{0,1,2} in the status register
953 * (SR). Does not support these features found in newer SR bitfields:
954 * - SEC: sector/block protect - only handle SEC=0 (block protect)
955 * - CMP: complement protect - only support CMP=0 (range is not complemented)
957 * Support for the following is provided conditionally for some flash:
958 * - TB: top/bottom protect
960 * Sample table portion for 8MB flash (Winbond w25q64fw):
962 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
963 * --------------------------------------------------------------------------
964 * X | X | 0 | 0 | 0 | NONE | NONE
965 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
966 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
967 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
968 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
969 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
970 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
971 * X | X | 1 | 1 | 1 | 8 MB | ALL
972 * ------|-------|-------|-------|-------|---------------|-------------------
973 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
974 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
975 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
976 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
977 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
978 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
980 * Returns negative on errors, 0 on success.
982 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
984 struct mtd_info *mtd = &nor->mtd;
985 int status_old, status_new;
986 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
987 u8 shift = ffs(mask) - 1, pow, val;
989 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
992 status_old = read_sr(nor);
996 /* If nothing in our range is unlocked, we don't need to do anything */
997 if (stm_is_locked_sr(nor, ofs, len, status_old))
1000 /* If anything below us is unlocked, we can't use 'bottom' protection */
1001 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
1002 can_be_bottom = false;
1004 /* If anything above us is unlocked, we can't use 'top' protection */
1005 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
1009 if (!can_be_bottom && !can_be_top)
1012 /* Prefer top, if both are valid */
1013 use_top = can_be_top;
1015 /* lock_len: length of region that should end up locked */
1017 lock_len = mtd->size - ofs;
1019 lock_len = ofs + len;
1022 * Need smallest pow such that:
1024 * 1 / (2^pow) <= (len / size)
1026 * so (assuming power-of-2 size) we do:
1028 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
1030 pow = ilog2(mtd->size) - ilog2(lock_len);
1031 val = mask - (pow << shift);
1034 /* Don't "lock" with no region! */
1038 status_new = (status_old & ~mask & ~SR_TB) | val;
1040 /* Disallow further writes if WP pin is asserted */
1041 status_new |= SR_SRWD;
1044 status_new |= SR_TB;
1046 /* Don't bother if they're the same */
1047 if (status_new == status_old)
1050 /* Only modify protection if it will not unlock other areas */
1051 if ((status_new & mask) < (status_old & mask))
1054 return write_sr_and_check(nor, status_new, mask);
1058 * Unlock a region of the flash. See stm_lock() for more info
1060 * Returns negative on errors, 0 on success.
1062 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1064 struct mtd_info *mtd = &nor->mtd;
1065 int status_old, status_new;
1066 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1067 u8 shift = ffs(mask) - 1, pow, val;
1069 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1072 status_old = read_sr(nor);
1076 /* If nothing in our range is locked, we don't need to do anything */
1077 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
1080 /* If anything below us is locked, we can't use 'top' protection */
1081 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
1084 /* If anything above us is locked, we can't use 'bottom' protection */
1085 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1087 can_be_bottom = false;
1089 if (!can_be_bottom && !can_be_top)
1092 /* Prefer top, if both are valid */
1093 use_top = can_be_top;
1095 /* lock_len: length of region that should remain locked */
1097 lock_len = mtd->size - (ofs + len);
1102 * Need largest pow such that:
1104 * 1 / (2^pow) >= (len / size)
1106 * so (assuming power-of-2 size) we do:
1108 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
1110 pow = ilog2(mtd->size) - order_base_2(lock_len);
1111 if (lock_len == 0) {
1112 val = 0; /* fully unlocked */
1114 val = mask - (pow << shift);
1115 /* Some power-of-two sizes are not supported */
1120 status_new = (status_old & ~mask & ~SR_TB) | val;
1122 /* Don't protect status register if we're fully unlocked */
1124 status_new &= ~SR_SRWD;
1127 status_new |= SR_TB;
1129 /* Don't bother if they're the same */
1130 if (status_new == status_old)
1133 /* Only modify protection if it will not lock other areas */
1134 if ((status_new & mask) > (status_old & mask))
1137 return write_sr_and_check(nor, status_new, mask);
1141 * Check if a region of the flash is (completely) locked. See stm_lock() for
1144 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
1145 * negative on errors.
1147 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1151 status = read_sr(nor);
1155 return stm_is_locked_sr(nor, ofs, len, status);
1158 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1160 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1163 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
1167 ret = nor->flash_lock(nor, ofs, len);
1169 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
1173 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1175 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1178 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1182 ret = nor->flash_unlock(nor, ofs, len);
1184 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1188 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1190 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1193 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1197 ret = nor->flash_is_locked(nor, ofs, len);
1199 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1203 static int macronix_quad_enable(struct spi_nor *nor);
1205 /* Used when the "_ext_id" is two bytes at most */
1206 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
1208 ((_jedec_id) >> 16) & 0xff, \
1209 ((_jedec_id) >> 8) & 0xff, \
1210 (_jedec_id) & 0xff, \
1211 ((_ext_id) >> 8) & 0xff, \
1214 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
1215 .sector_size = (_sector_size), \
1216 .n_sectors = (_n_sectors), \
1220 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
1222 ((_jedec_id) >> 16) & 0xff, \
1223 ((_jedec_id) >> 8) & 0xff, \
1224 (_jedec_id) & 0xff, \
1225 ((_ext_id) >> 16) & 0xff, \
1226 ((_ext_id) >> 8) & 0xff, \
1230 .sector_size = (_sector_size), \
1231 .n_sectors = (_n_sectors), \
1235 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
1236 .sector_size = (_sector_size), \
1237 .n_sectors = (_n_sectors), \
1238 .page_size = (_page_size), \
1239 .addr_width = (_addr_width), \
1242 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
1244 ((_jedec_id) >> 16) & 0xff, \
1245 ((_jedec_id) >> 8) & 0xff, \
1246 (_jedec_id) & 0xff \
1249 .sector_size = (8*_page_size), \
1250 .n_sectors = (_n_sectors), \
1251 .page_size = _page_size, \
1253 .flags = SPI_NOR_NO_FR | SPI_S3AN,
1255 /* NOTE: double check command sets and memory organization when you add
1256 * more nor chips. This current list focusses on newer chips, which
1257 * have been converging on command sets which including JEDEC ID.
1259 * All newly added entries should describe *hardware* and should use SECT_4K
1260 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
1261 * scenarios excluding small sectors there is config option that can be
1262 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
1263 * For historical (and compatibility) reasons (before we got above config) some
1264 * old entries may be missing 4K flag.
1266 static const struct flash_info spi_nor_ids[] = {
1267 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
1268 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
1269 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
1271 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
1272 { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
1273 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
1274 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
1276 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
1277 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
1278 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
1279 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
1281 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
1283 /* EON -- en25xxx */
1284 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
1285 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
1286 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
1287 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
1288 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
1289 { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
1290 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
1291 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
1292 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
1295 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
1296 { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
1297 { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
1300 { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1301 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1302 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1303 { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1306 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
1310 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
1311 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1312 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1315 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
1316 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1317 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1320 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
1321 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1322 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1325 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
1326 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1327 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1330 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
1331 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1332 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1335 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
1336 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1337 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1340 "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
1341 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1342 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1343 .quad_enable = macronix_quad_enable,
1346 /* Intel/Numonyx -- xxxs33b */
1347 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
1348 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
1349 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
1352 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
1353 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
1354 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1355 { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
1356 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1357 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
1358 SECT_4K | SPI_NOR_DUAL_READ) },
1359 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
1360 SECT_4K | SPI_NOR_DUAL_READ) },
1361 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
1362 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1363 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
1364 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1365 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
1366 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1369 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
1370 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
1371 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
1372 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
1373 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
1374 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
1375 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
1376 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
1377 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
1378 { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
1379 { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
1380 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
1381 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
1382 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
1383 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1384 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
1385 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
1386 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1387 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1388 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1389 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
1392 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
1393 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1394 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1395 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1396 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1397 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1398 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1399 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1400 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
1401 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1402 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1403 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1404 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1405 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1408 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
1409 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
1410 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
1412 /* Spansion/Cypress -- single (large) sector size only, at least
1413 * for the chips listed here (without boot sectors).
1415 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1416 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1417 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
1418 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1419 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1420 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
1421 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
1422 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
1423 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1424 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1425 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1426 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
1427 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
1428 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
1429 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
1430 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
1431 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1432 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1433 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1434 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1435 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1436 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
1437 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
1438 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
1439 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
1440 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1441 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1442 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1444 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
1445 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1446 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1447 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
1448 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
1449 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
1450 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
1451 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
1452 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
1453 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
1454 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
1455 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1456 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1457 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1459 /* ST Microelectronics -- newer production may have feature updates */
1460 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
1461 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
1462 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
1463 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
1464 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
1465 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
1466 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
1467 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
1468 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1470 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
1471 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
1472 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
1473 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
1474 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
1475 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
1476 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
1477 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
1478 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
1480 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
1481 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
1482 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
1484 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
1485 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
1486 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1488 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
1489 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
1490 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
1491 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
1492 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1493 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
1495 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1496 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
1497 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1498 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1499 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1500 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1501 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1503 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
1504 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1505 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1507 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1508 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
1509 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
1510 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
1511 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1513 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
1514 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1515 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1518 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
1519 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1520 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1522 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1523 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1525 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
1526 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1527 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1530 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
1531 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1532 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1534 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1535 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1536 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1537 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1538 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
1539 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
1541 /* Catalyst / On Semiconductor -- non-JEDEC */
1542 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1543 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1544 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1545 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1546 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1548 /* Xilinx S3AN Internal Flash */
1549 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
1550 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
1551 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
1552 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
1553 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
1555 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
1556 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1557 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1561 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1564 u8 id[SPI_NOR_MAX_ID_LEN];
1565 const struct flash_info *info;
1567 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1569 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1570 return ERR_PTR(tmp);
1573 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1574 info = &spi_nor_ids[tmp];
1576 if (!memcmp(info->id, id, info->id_len))
1577 return &spi_nor_ids[tmp];
1580 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1581 id[0], id[1], id[2]);
1582 return ERR_PTR(-ENODEV);
1585 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1586 size_t *retlen, u_char *buf)
1588 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1591 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1593 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
1600 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
1601 addr = spi_nor_s3an_addr_convert(nor, addr);
1603 ret = nor->read(nor, addr, len, buf);
1605 /* We shouldn't see 0-length reads */
1621 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
1625 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1626 size_t *retlen, const u_char *buf)
1628 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1632 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1634 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1640 nor->sst_write_second = false;
1643 /* Start write from odd address. */
1645 nor->program_opcode = SPINOR_OP_BP;
1647 /* write one byte. */
1648 ret = nor->write(nor, to, 1, buf);
1651 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1653 ret = spi_nor_wait_till_ready(nor);
1659 /* Write out most of the data here. */
1660 for (; actual < len - 1; actual += 2) {
1661 nor->program_opcode = SPINOR_OP_AAI_WP;
1663 /* write two bytes. */
1664 ret = nor->write(nor, to, 2, buf + actual);
1667 WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
1669 ret = spi_nor_wait_till_ready(nor);
1673 nor->sst_write_second = true;
1675 nor->sst_write_second = false;
1678 ret = spi_nor_wait_till_ready(nor);
1682 /* Write out trailing byte if it exists. */
1683 if (actual != len) {
1686 nor->program_opcode = SPINOR_OP_BP;
1687 ret = nor->write(nor, to, 1, buf + actual);
1690 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1692 ret = spi_nor_wait_till_ready(nor);
1700 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1705 * Write an address range to the nor chip. Data must be written in
1706 * FLASH_PAGESIZE chunks. The address range may be any size provided
1707 * it is within the physical boundaries.
1709 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1710 size_t *retlen, const u_char *buf)
1712 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1713 size_t page_offset, page_remain, i;
1716 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1718 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1722 for (i = 0; i < len; ) {
1724 loff_t addr = to + i;
1727 * If page_size is a power of two, the offset can be quickly
1728 * calculated with an AND operation. On the other cases we
1729 * need to do a modulus operation (more expensive).
1730 * Power of two numbers have only one bit set and we can use
1731 * the instruction hweight32 to detect if we need to do a
1732 * modulus (do_div()) or not.
1734 if (hweight32(nor->page_size) == 1) {
1735 page_offset = addr & (nor->page_size - 1);
1737 uint64_t aux = addr;
1739 page_offset = do_div(aux, nor->page_size);
1741 /* the size of data remaining on the first page */
1742 page_remain = min_t(size_t,
1743 nor->page_size - page_offset, len - i);
1745 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
1746 addr = spi_nor_s3an_addr_convert(nor, addr);
1749 ret = nor->write(nor, addr, page_remain, buf + i);
1754 ret = spi_nor_wait_till_ready(nor);
1762 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1767 * macronix_quad_enable() - set QE bit in Status Register.
1768 * @nor: pointer to a 'struct spi_nor'
1770 * Set the Quad Enable (QE) bit in the Status Register.
1772 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1774 * Return: 0 on success, -errno otherwise.
1776 static int macronix_quad_enable(struct spi_nor *nor)
1783 if (val & SR_QUAD_EN_MX)
1788 write_sr(nor, val | SR_QUAD_EN_MX);
1790 ret = spi_nor_wait_till_ready(nor);
1795 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1796 dev_err(nor->dev, "Macronix Quad bit not set\n");
1804 * Write status Register and configuration register with 2 bytes
1805 * The first byte will be written to the status register, while the
1806 * second byte will be written to the configuration register.
1807 * Return negative if error occurred.
1809 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1815 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1818 "error while writing configuration register\n");
1822 ret = spi_nor_wait_till_ready(nor);
1825 "timeout while writing configuration register\n");
1833 * spansion_quad_enable() - set QE bit in Configuraiton Register.
1834 * @nor: pointer to a 'struct spi_nor'
1836 * Set the Quad Enable (QE) bit in the Configuration Register.
1837 * This function is kept for legacy purpose because it has been used for a
1838 * long time without anybody complaining but it should be considered as
1839 * deprecated and maybe buggy.
1840 * First, this function doesn't care about the previous values of the Status
1841 * and Configuration Registers when it sets the QE bit (bit 1) in the
1842 * Configuration Register: all other bits are cleared, which may have unwanted
1843 * side effects like removing some block protections.
1844 * Secondly, it uses the Read Configuration Register (35h) instruction though
1845 * some very old and few memories don't support this instruction. If a pull-up
1846 * resistor is present on the MISO/IO1 line, we might still be able to pass the
1847 * "read back" test because the QSPI memory doesn't recognize the command,
1848 * so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0xFF.
1850 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1853 * Return: 0 on success, -errno otherwise.
1855 static int spansion_quad_enable(struct spi_nor *nor)
1857 u8 sr_cr[2] = {0, CR_QUAD_EN_SPAN};
1860 ret = write_sr_cr(nor, sr_cr);
1864 /* read back and check it */
1866 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1867 dev_err(nor->dev, "Spansion Quad bit not set\n");
1875 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1876 * @nor: pointer to a 'struct spi_nor'
1878 * Set the Quad Enable (QE) bit in the Configuration Register.
1879 * This function should be used with QSPI memories not supporting the Read
1880 * Configuration Register (35h) instruction.
1882 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1885 * Return: 0 on success, -errno otherwise.
1887 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1892 /* Keep the current value of the Status Register. */
1895 dev_err(nor->dev, "error while reading status register\n");
1899 sr_cr[1] = CR_QUAD_EN_SPAN;
1901 return write_sr_cr(nor, sr_cr);
1905 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1906 * @nor: pointer to a 'struct spi_nor'
1908 * Set the Quad Enable (QE) bit in the Configuration Register.
1909 * This function should be used with QSPI memories supporting the Read
1910 * Configuration Register (35h) instruction.
1912 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1915 * Return: 0 on success, -errno otherwise.
1917 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1919 struct device *dev = nor->dev;
1923 /* Check current Quad Enable bit value. */
1926 dev_err(dev, "error while reading configuration register\n");
1930 if (ret & CR_QUAD_EN_SPAN)
1933 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1935 /* Keep the current value of the Status Register. */
1938 dev_err(dev, "error while reading status register\n");
1943 ret = write_sr_cr(nor, sr_cr);
1947 /* Read back and check it. */
1949 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1950 dev_err(nor->dev, "Spansion Quad bit not set\n");
1958 * sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1959 * @nor: pointer to a 'struct spi_nor'
1961 * Set the Quad Enable (QE) bit in the Status Register 2.
1963 * This is one of the procedures to set the QE bit described in the SFDP
1964 * (JESD216 rev B) specification but no manufacturer using this procedure has
1965 * been identified yet, hence the name of the function.
1967 * Return: 0 on success, -errno otherwise.
1969 static int sr2_bit7_quad_enable(struct spi_nor *nor)
1974 /* Check current Quad Enable bit value. */
1975 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1978 if (sr2 & SR2_QUAD_EN_BIT7)
1981 /* Update the Quad Enable bit. */
1982 sr2 |= SR2_QUAD_EN_BIT7;
1986 ret = nor->write_reg(nor, SPINOR_OP_WRSR2, &sr2, 1);
1988 dev_err(nor->dev, "error while writing status register 2\n");
1992 ret = spi_nor_wait_till_ready(nor);
1994 dev_err(nor->dev, "timeout while writing status register 2\n");
1998 /* Read back and check it. */
1999 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
2000 if (!(ret > 0 && (sr2 & SR2_QUAD_EN_BIT7))) {
2001 dev_err(nor->dev, "SR2 Quad bit not set\n");
2008 static int spi_nor_check(struct spi_nor *nor)
2010 if (!nor->dev || !nor->read || !nor->write ||
2011 !nor->read_reg || !nor->write_reg) {
2012 pr_err("spi-nor: please fill all the necessary fields!\n");
2019 static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
2024 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
2026 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
2030 nor->erase_opcode = SPINOR_OP_XSE;
2031 nor->program_opcode = SPINOR_OP_XPP;
2032 nor->read_opcode = SPINOR_OP_READ;
2033 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2036 * This flashes have a page size of 264 or 528 bytes (known as
2037 * Default addressing mode). It can be changed to a more standard
2038 * Power of two mode where the page size is 256/512. This comes
2039 * with a price: there is 3% less of space, the data is corrupted
2040 * and the page size cannot be changed back to default addressing
2043 * The current addressing mode can be read from the XRDSR register
2044 * and should not be changed, because is a destructive operation.
2046 if (val & XSR_PAGESIZE) {
2047 /* Flash in Power of 2 mode */
2048 nor->page_size = (nor->page_size == 264) ? 256 : 512;
2049 nor->mtd.writebufsize = nor->page_size;
2050 nor->mtd.size = 8 * nor->page_size * info->n_sectors;
2051 nor->mtd.erasesize = 8 * nor->page_size;
2053 /* Flash in Default addressing mode */
2054 nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
2060 struct spi_nor_read_command {
2064 enum spi_nor_protocol proto;
2067 struct spi_nor_pp_command {
2069 enum spi_nor_protocol proto;
2072 enum spi_nor_read_command_index {
2075 SNOR_CMD_READ_1_1_1_DTR,
2078 SNOR_CMD_READ_1_1_2,
2079 SNOR_CMD_READ_1_2_2,
2080 SNOR_CMD_READ_2_2_2,
2081 SNOR_CMD_READ_1_2_2_DTR,
2084 SNOR_CMD_READ_1_1_4,
2085 SNOR_CMD_READ_1_4_4,
2086 SNOR_CMD_READ_4_4_4,
2087 SNOR_CMD_READ_1_4_4_DTR,
2090 SNOR_CMD_READ_1_1_8,
2091 SNOR_CMD_READ_1_8_8,
2092 SNOR_CMD_READ_8_8_8,
2093 SNOR_CMD_READ_1_8_8_DTR,
2098 enum spi_nor_pp_command_index {
2114 struct spi_nor_flash_parameter {
2118 struct spi_nor_hwcaps hwcaps;
2119 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
2120 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
2122 int (*quad_enable)(struct spi_nor *nor);
2126 spi_nor_set_read_settings(struct spi_nor_read_command *read,
2130 enum spi_nor_protocol proto)
2132 read->num_mode_clocks = num_mode_clocks;
2133 read->num_wait_states = num_wait_states;
2134 read->opcode = opcode;
2135 read->proto = proto;
2139 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
2141 enum spi_nor_protocol proto)
2143 pp->opcode = opcode;
2148 * Serial Flash Discoverable Parameters (SFDP) parsing.
2152 * spi_nor_read_raw() - raw read of serial flash memory. read_opcode,
2153 * addr_width and read_dummy members of the struct spi_nor
2154 * should be previously
2156 * @nor: pointer to a 'struct spi_nor'
2157 * @addr: offset in the serial flash memory
2158 * @len: number of bytes to read
2159 * @buf: buffer where the data is copied into (dma-safe memory)
2161 * Return: 0 on success, -errno otherwise.
2163 static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf)
2168 ret = nor->read(nor, addr, len, buf);
2169 if (!ret || ret > len)
2182 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
2183 * @nor: pointer to a 'struct spi_nor'
2184 * @addr: offset in the SFDP area to start reading data from
2185 * @len: number of bytes to read
2186 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
2188 * Whatever the actual numbers of bytes for address and dummy cycles are
2189 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
2190 * followed by a 3-byte address and 8 dummy clock cycles.
2192 * Return: 0 on success, -errno otherwise.
2194 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
2195 size_t len, void *buf)
2197 u8 addr_width, read_opcode, read_dummy;
2200 read_opcode = nor->read_opcode;
2201 addr_width = nor->addr_width;
2202 read_dummy = nor->read_dummy;
2204 nor->read_opcode = SPINOR_OP_RDSFDP;
2205 nor->addr_width = 3;
2206 nor->read_dummy = 8;
2208 ret = spi_nor_read_raw(nor, addr, len, buf);
2210 nor->read_opcode = read_opcode;
2211 nor->addr_width = addr_width;
2212 nor->read_dummy = read_dummy;
2218 * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
2219 * @nor: pointer to a 'struct spi_nor'
2220 * @addr: offset in the SFDP area to start reading data from
2221 * @len: number of bytes to read
2222 * @buf: buffer where the SFDP data are copied into
2224 * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
2225 * guaranteed to be dma-safe.
2227 * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
2230 static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
2231 size_t len, void *buf)
2236 dma_safe_buf = kmalloc(len, GFP_KERNEL);
2240 ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
2241 memcpy(buf, dma_safe_buf, len);
2242 kfree(dma_safe_buf);
2247 struct sfdp_parameter_header {
2251 u8 length; /* in double words */
2252 u8 parameter_table_pointer[3]; /* byte address */
2256 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
2257 #define SFDP_PARAM_HEADER_PTP(p) \
2258 (((p)->parameter_table_pointer[2] << 16) | \
2259 ((p)->parameter_table_pointer[1] << 8) | \
2260 ((p)->parameter_table_pointer[0] << 0))
2262 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
2263 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
2265 #define SFDP_SIGNATURE 0x50444653U
2266 #define SFDP_JESD216_MAJOR 1
2267 #define SFDP_JESD216_MINOR 0
2268 #define SFDP_JESD216A_MINOR 5
2269 #define SFDP_JESD216B_MINOR 6
2271 struct sfdp_header {
2272 u32 signature; /* Ox50444653U <=> "SFDP" */
2275 u8 nph; /* 0-base number of parameter headers */
2278 /* Basic Flash Parameter Table. */
2279 struct sfdp_parameter_header bfpt_header;
2282 /* Basic Flash Parameter Table */
2285 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
2286 * They are indexed from 1 but C arrays are indexed from 0.
2288 #define BFPT_DWORD(i) ((i) - 1)
2289 #define BFPT_DWORD_MAX 16
2291 /* The first version of JESB216 defined only 9 DWORDs. */
2292 #define BFPT_DWORD_MAX_JESD216 9
2295 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
2296 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
2297 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
2298 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
2299 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
2300 #define BFPT_DWORD1_DTR BIT(19)
2301 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
2302 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
2303 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
2306 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
2307 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
2310 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
2311 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
2316 * (from JESD216 rev B)
2317 * Quad Enable Requirements (QER):
2318 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
2319 * reads based on instruction. DQ3/HOLD# functions are hold during
2320 * instruction phase.
2321 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
2322 * two data bytes where bit 1 of the second byte is one.
2324 * Writing only one byte to the status register has the side-effect of
2325 * clearing status register 2, including the QE bit. The 100b code is
2326 * used if writing one byte to the status register does not modify
2327 * status register 2.
2328 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
2329 * one data byte where bit 6 is one.
2331 * - 011b: QE is bit 7 of status register 2. It is set via Write status
2332 * register 2 instruction 3Eh with one data byte where bit 7 is one.
2334 * The status register 2 is read using instruction 3Fh.
2335 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
2336 * two data bytes where bit 1 of the second byte is one.
2338 * In contrast to the 001b code, writing one byte to the status
2339 * register does not modify status register 2.
2340 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
2341 * Read Status instruction 05h. Status register2 is read using
2342 * instruction 35h. QE is set via Writ Status instruction 01h with
2343 * two data bytes where bit 1 of the second byte is one.
2346 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
2347 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
2348 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
2349 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
2350 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
2351 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
2352 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
2355 u32 dwords[BFPT_DWORD_MAX];
2358 /* Fast Read settings. */
2361 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
2363 enum spi_nor_protocol proto)
2365 read->num_mode_clocks = (half >> 5) & 0x07;
2366 read->num_wait_states = (half >> 0) & 0x1f;
2367 read->opcode = (half >> 8) & 0xff;
2368 read->proto = proto;
2371 struct sfdp_bfpt_read {
2372 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
2376 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
2377 * whether the Fast Read x-y-z command is supported.
2379 u32 supported_dword;
2383 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
2384 * encodes the op code, the number of mode clocks and the number of wait
2385 * states to be used by Fast Read x-y-z command.
2390 /* The SPI protocol for this Fast Read x-y-z command. */
2391 enum spi_nor_protocol proto;
2394 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
2395 /* Fast Read 1-1-2 */
2397 SNOR_HWCAPS_READ_1_1_2,
2398 BFPT_DWORD(1), BIT(16), /* Supported bit */
2399 BFPT_DWORD(4), 0, /* Settings */
2403 /* Fast Read 1-2-2 */
2405 SNOR_HWCAPS_READ_1_2_2,
2406 BFPT_DWORD(1), BIT(20), /* Supported bit */
2407 BFPT_DWORD(4), 16, /* Settings */
2411 /* Fast Read 2-2-2 */
2413 SNOR_HWCAPS_READ_2_2_2,
2414 BFPT_DWORD(5), BIT(0), /* Supported bit */
2415 BFPT_DWORD(6), 16, /* Settings */
2419 /* Fast Read 1-1-4 */
2421 SNOR_HWCAPS_READ_1_1_4,
2422 BFPT_DWORD(1), BIT(22), /* Supported bit */
2423 BFPT_DWORD(3), 16, /* Settings */
2427 /* Fast Read 1-4-4 */
2429 SNOR_HWCAPS_READ_1_4_4,
2430 BFPT_DWORD(1), BIT(21), /* Supported bit */
2431 BFPT_DWORD(3), 0, /* Settings */
2435 /* Fast Read 4-4-4 */
2437 SNOR_HWCAPS_READ_4_4_4,
2438 BFPT_DWORD(5), BIT(4), /* Supported bit */
2439 BFPT_DWORD(7), 16, /* Settings */
2444 struct sfdp_bfpt_erase {
2446 * The half-word at offset <shift> in DWORD <dwoard> encodes the
2447 * op code and erase sector size to be used by Sector Erase commands.
2453 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
2454 /* Erase Type 1 in DWORD8 bits[15:0] */
2457 /* Erase Type 2 in DWORD8 bits[31:16] */
2458 {BFPT_DWORD(8), 16},
2460 /* Erase Type 3 in DWORD9 bits[15:0] */
2463 /* Erase Type 4 in DWORD9 bits[31:16] */
2464 {BFPT_DWORD(9), 16},
2467 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
2470 * spi_nor_set_erase_type() - set a SPI NOR erase type
2471 * @erase: pointer to a structure that describes a SPI NOR erase type
2472 * @size: the size of the sector/block erased by the erase type
2473 * @opcode: the SPI command op code to erase the sector/block
2475 static void spi_nor_set_erase_type(struct spi_nor_erase_type *erase,
2476 u32 size, u8 opcode)
2479 erase->opcode = opcode;
2480 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
2481 erase->size_shift = ffs(erase->size) - 1;
2482 erase->size_mask = (1 << erase->size_shift) - 1;
2486 * spi_nor_set_erase_settings_from_bfpt() - set erase type settings from BFPT
2487 * @erase: pointer to a structure that describes a SPI NOR erase type
2488 * @size: the size of the sector/block erased by the erase type
2489 * @opcode: the SPI command op code to erase the sector/block
2490 * @i: erase type index as sorted in the Basic Flash Parameter Table
2492 * The supported Erase Types will be sorted at init in ascending order, with
2493 * the smallest Erase Type size being the first member in the erase_type array
2494 * of the spi_nor_erase_map structure. Save the Erase Type index as sorted in
2495 * the Basic Flash Parameter Table since it will be used later on to
2496 * synchronize with the supported Erase Types defined in SFDP optional tables.
2499 spi_nor_set_erase_settings_from_bfpt(struct spi_nor_erase_type *erase,
2500 u32 size, u8 opcode, u8 i)
2503 spi_nor_set_erase_type(erase, size, opcode);
2507 * spi_nor_map_cmp_erase_type() - compare the map's erase types by size
2508 * @l: member in the left half of the map's erase_type array
2509 * @r: member in the right half of the map's erase_type array
2511 * Comparison function used in the sort() call to sort in ascending order the
2512 * map's erase types, the smallest erase type size being the first member in the
2513 * sorted erase_type array.
2515 * Return: the result of @l->size - @r->size
2517 static int spi_nor_map_cmp_erase_type(const void *l, const void *r)
2519 const struct spi_nor_erase_type *left = l, *right = r;
2521 return left->size - right->size;
2525 * spi_nor_sort_erase_mask() - sort erase mask
2526 * @map: the erase map of the SPI NOR
2527 * @erase_mask: the erase type mask to be sorted
2529 * Replicate the sort done for the map's erase types in BFPT: sort the erase
2530 * mask in ascending order with the smallest erase type size starting from
2531 * BIT(0) in the sorted erase mask.
2533 * Return: sorted erase mask.
2535 static u8 spi_nor_sort_erase_mask(struct spi_nor_erase_map *map, u8 erase_mask)
2537 struct spi_nor_erase_type *erase_type = map->erase_type;
2539 u8 sorted_erase_mask = 0;
2544 /* Replicate the sort done for the map's erase types. */
2545 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
2546 if (erase_type[i].size && erase_mask & BIT(erase_type[i].idx))
2547 sorted_erase_mask |= BIT(i);
2549 return sorted_erase_mask;
2553 * spi_nor_regions_sort_erase_types() - sort erase types in each region
2554 * @map: the erase map of the SPI NOR
2556 * Function assumes that the erase types defined in the erase map are already
2557 * sorted in ascending order, with the smallest erase type size being the first
2558 * member in the erase_type array. It replicates the sort done for the map's
2559 * erase types. Each region's erase bitmask will indicate which erase types are
2560 * supported from the sorted erase types defined in the erase map.
2561 * Sort the all region's erase type at init in order to speed up the process of
2562 * finding the best erase command at runtime.
2564 static void spi_nor_regions_sort_erase_types(struct spi_nor_erase_map *map)
2566 struct spi_nor_erase_region *region = map->regions;
2567 u8 region_erase_mask, sorted_erase_mask;
2570 region_erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
2572 sorted_erase_mask = spi_nor_sort_erase_mask(map,
2575 /* Overwrite erase mask. */
2576 region->offset = (region->offset & ~SNOR_ERASE_TYPE_MASK) |
2579 region = spi_nor_region_next(region);
2584 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2585 * @map: the erase map of the SPI NOR
2586 * @erase_mask: bitmask encoding erase types that can erase the entire
2588 * @flash_size: the spi nor flash memory size
2590 static void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2591 u8 erase_mask, u64 flash_size)
2593 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
2594 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
2596 map->uniform_region.size = flash_size;
2597 map->regions = &map->uniform_region;
2598 map->uniform_erase_type = erase_mask;
2602 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
2603 * @nor: pointer to a 'struct spi_nor'
2604 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
2605 * the Basic Flash Parameter Table length and version
2606 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2609 * The Basic Flash Parameter Table is the main and only mandatory table as
2610 * defined by the SFDP (JESD216) specification.
2611 * It provides us with the total size (memory density) of the data array and
2612 * the number of address bytes for Fast Read, Page Program and Sector Erase
2614 * For Fast READ commands, it also gives the number of mode clock cycles and
2615 * wait states (regrouped in the number of dummy clock cycles) for each
2616 * supported instruction op code.
2617 * For Page Program, the page size is now available since JESD216 rev A, however
2618 * the supported instruction op codes are still not provided.
2619 * For Sector Erase commands, this table stores the supported instruction op
2620 * codes and the associated sector sizes.
2621 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
2622 * rev A. The QER bits encode the manufacturer dependent procedure to be
2623 * executed to set the Quad Enable (QE) bit in some internal register of the
2624 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
2625 * sending any Quad SPI command to the memory. Actually, setting the QE bit
2626 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
2627 * and IO3 hence enabling 4 (Quad) I/O lines.
2629 * Return: 0 on success, -errno otherwise.
2631 static int spi_nor_parse_bfpt(struct spi_nor *nor,
2632 const struct sfdp_parameter_header *bfpt_header,
2633 struct spi_nor_flash_parameter *params)
2635 struct spi_nor_erase_map *map = &nor->erase_map;
2636 struct spi_nor_erase_type *erase_type = map->erase_type;
2637 struct sfdp_bfpt bfpt;
2644 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
2645 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
2648 /* Read the Basic Flash Parameter Table. */
2649 len = min_t(size_t, sizeof(bfpt),
2650 bfpt_header->length * sizeof(u32));
2651 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
2652 memset(&bfpt, 0, sizeof(bfpt));
2653 err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
2657 /* Fix endianness of the BFPT DWORDs. */
2658 for (i = 0; i < BFPT_DWORD_MAX; i++)
2659 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
2661 /* Number of address bytes. */
2662 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
2663 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
2664 nor->addr_width = 3;
2667 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
2668 nor->addr_width = 4;
2675 /* Flash Memory Density (in bits). */
2676 params->size = bfpt.dwords[BFPT_DWORD(2)];
2677 if (params->size & BIT(31)) {
2678 params->size &= ~BIT(31);
2681 * Prevent overflows on params->size. Anyway, a NOR of 2^64
2682 * bits is unlikely to exist so this error probably means
2683 * the BFPT we are reading is corrupted/wrong.
2685 if (params->size > 63)
2688 params->size = 1ULL << params->size;
2692 params->size >>= 3; /* Convert to bytes. */
2694 /* Fast Read settings. */
2695 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
2696 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
2697 struct spi_nor_read_command *read;
2699 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
2700 params->hwcaps.mask &= ~rd->hwcaps;
2704 params->hwcaps.mask |= rd->hwcaps;
2705 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
2706 read = ¶ms->reads[cmd];
2707 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
2708 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
2712 * Sector Erase settings. Reinitialize the uniform erase map using the
2713 * Erase Types defined in the bfpt table.
2716 memset(&nor->erase_map, 0, sizeof(nor->erase_map));
2717 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
2718 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
2722 half = bfpt.dwords[er->dword] >> er->shift;
2723 erasesize = half & 0xff;
2725 /* erasesize == 0 means this Erase Type is not supported. */
2729 erasesize = 1U << erasesize;
2730 opcode = (half >> 8) & 0xff;
2731 erase_mask |= BIT(i);
2732 spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize,
2735 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2737 * Sort all the map's Erase Types in ascending order with the smallest
2738 * erase size being the first member in the erase_type array.
2740 sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]),
2741 spi_nor_map_cmp_erase_type, NULL);
2743 * Sort the erase types in the uniform region in order to update the
2744 * uniform_erase_type bitmask. The bitmask will be used later on when
2745 * selecting the uniform erase.
2747 spi_nor_regions_sort_erase_types(map);
2748 map->uniform_erase_type = map->uniform_region.offset &
2749 SNOR_ERASE_TYPE_MASK;
2751 /* Stop here if not JESD216 rev A or later. */
2752 if (bfpt_header->length < BFPT_DWORD_MAX)
2755 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2756 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2757 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2758 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2759 params->page_size = 1U << params->page_size;
2761 /* Quad Enable Requirements. */
2762 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2763 case BFPT_DWORD15_QER_NONE:
2764 params->quad_enable = NULL;
2767 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2768 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2769 params->quad_enable = spansion_no_read_cr_quad_enable;
2772 case BFPT_DWORD15_QER_SR1_BIT6:
2773 params->quad_enable = macronix_quad_enable;
2776 case BFPT_DWORD15_QER_SR2_BIT7:
2777 params->quad_enable = sr2_bit7_quad_enable;
2780 case BFPT_DWORD15_QER_SR2_BIT1:
2781 params->quad_enable = spansion_read_cr_quad_enable;
2791 #define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)
2792 #define SMPT_CMD_ADDRESS_LEN_0 (0x0UL << 22)
2793 #define SMPT_CMD_ADDRESS_LEN_3 (0x1UL << 22)
2794 #define SMPT_CMD_ADDRESS_LEN_4 (0x2UL << 22)
2795 #define SMPT_CMD_ADDRESS_LEN_USE_CURRENT (0x3UL << 22)
2797 #define SMPT_CMD_READ_DUMMY_MASK GENMASK(19, 16)
2798 #define SMPT_CMD_READ_DUMMY_SHIFT 16
2799 #define SMPT_CMD_READ_DUMMY(_cmd) \
2800 (((_cmd) & SMPT_CMD_READ_DUMMY_MASK) >> SMPT_CMD_READ_DUMMY_SHIFT)
2801 #define SMPT_CMD_READ_DUMMY_IS_VARIABLE 0xfUL
2803 #define SMPT_CMD_READ_DATA_MASK GENMASK(31, 24)
2804 #define SMPT_CMD_READ_DATA_SHIFT 24
2805 #define SMPT_CMD_READ_DATA(_cmd) \
2806 (((_cmd) & SMPT_CMD_READ_DATA_MASK) >> SMPT_CMD_READ_DATA_SHIFT)
2808 #define SMPT_CMD_OPCODE_MASK GENMASK(15, 8)
2809 #define SMPT_CMD_OPCODE_SHIFT 8
2810 #define SMPT_CMD_OPCODE(_cmd) \
2811 (((_cmd) & SMPT_CMD_OPCODE_MASK) >> SMPT_CMD_OPCODE_SHIFT)
2813 #define SMPT_MAP_REGION_COUNT_MASK GENMASK(23, 16)
2814 #define SMPT_MAP_REGION_COUNT_SHIFT 16
2815 #define SMPT_MAP_REGION_COUNT(_header) \
2816 ((((_header) & SMPT_MAP_REGION_COUNT_MASK) >> \
2817 SMPT_MAP_REGION_COUNT_SHIFT) + 1)
2819 #define SMPT_MAP_ID_MASK GENMASK(15, 8)
2820 #define SMPT_MAP_ID_SHIFT 8
2821 #define SMPT_MAP_ID(_header) \
2822 (((_header) & SMPT_MAP_ID_MASK) >> SMPT_MAP_ID_SHIFT)
2824 #define SMPT_MAP_REGION_SIZE_MASK GENMASK(31, 8)
2825 #define SMPT_MAP_REGION_SIZE_SHIFT 8
2826 #define SMPT_MAP_REGION_SIZE(_region) \
2827 (((((_region) & SMPT_MAP_REGION_SIZE_MASK) >> \
2828 SMPT_MAP_REGION_SIZE_SHIFT) + 1) * 256)
2830 #define SMPT_MAP_REGION_ERASE_TYPE_MASK GENMASK(3, 0)
2831 #define SMPT_MAP_REGION_ERASE_TYPE(_region) \
2832 ((_region) & SMPT_MAP_REGION_ERASE_TYPE_MASK)
2834 #define SMPT_DESC_TYPE_MAP BIT(1)
2835 #define SMPT_DESC_END BIT(0)
2838 * spi_nor_smpt_addr_width() - return the address width used in the
2839 * configuration detection command.
2840 * @nor: pointer to a 'struct spi_nor'
2841 * @settings: configuration detection command descriptor, dword1
2843 static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings)
2845 switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) {
2846 case SMPT_CMD_ADDRESS_LEN_0:
2848 case SMPT_CMD_ADDRESS_LEN_3:
2850 case SMPT_CMD_ADDRESS_LEN_4:
2852 case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
2855 return nor->addr_width;
2860 * spi_nor_smpt_read_dummy() - return the configuration detection command read
2861 * latency, in clock cycles.
2862 * @nor: pointer to a 'struct spi_nor'
2863 * @settings: configuration detection command descriptor, dword1
2865 * Return: the number of dummy cycles for an SMPT read
2867 static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
2869 u8 read_dummy = SMPT_CMD_READ_DUMMY(settings);
2871 if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE)
2872 return nor->read_dummy;
2877 * spi_nor_get_map_in_use() - get the configuration map in use
2878 * @nor: pointer to a 'struct spi_nor'
2879 * @smpt: pointer to the sector map parameter table
2880 * @smpt_len: sector map parameter table length
2882 * Return: pointer to the map in use, ERR_PTR(-errno) otherwise.
2884 static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
2892 u8 addr_width, read_opcode, read_dummy;
2893 u8 read_data_mask, map_id;
2895 /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
2896 buf = kmalloc(sizeof(*buf), GFP_KERNEL);
2898 return ERR_PTR(-ENOMEM);
2900 addr_width = nor->addr_width;
2901 read_dummy = nor->read_dummy;
2902 read_opcode = nor->read_opcode;
2905 /* Determine if there are any optional Detection Command Descriptors */
2906 for (i = 0; i < smpt_len; i += 2) {
2907 if (smpt[i] & SMPT_DESC_TYPE_MAP)
2910 read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
2911 nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
2912 nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
2913 nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
2916 err = spi_nor_read_raw(nor, addr, 1, buf);
2923 * Build an index value that is used to select the Sector Map
2924 * Configuration that is currently in use.
2926 map_id = map_id << 1 | !!(*buf & read_data_mask);
2930 * If command descriptors are provided, they always precede map
2931 * descriptors in the table. There is no need to start the iteration
2932 * over smpt array all over again.
2934 * Find the matching configuration map.
2936 ret = ERR_PTR(-EINVAL);
2937 while (i < smpt_len) {
2938 if (SMPT_MAP_ID(smpt[i]) == map_id) {
2944 * If there are no more configuration map descriptors and no
2945 * configuration ID matched the configuration identifier, the
2946 * sector address map is unknown.
2948 if (smpt[i] & SMPT_DESC_END)
2951 /* increment the table index to the next map */
2952 i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1;
2958 nor->addr_width = addr_width;
2959 nor->read_dummy = read_dummy;
2960 nor->read_opcode = read_opcode;
2965 * spi_nor_region_check_overlay() - set overlay bit when the region is overlaid
2966 * @region: pointer to a structure that describes a SPI NOR erase region
2967 * @erase: pointer to a structure that describes a SPI NOR erase type
2968 * @erase_type: erase type bitmask
2971 spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
2972 const struct spi_nor_erase_type *erase,
2973 const u8 erase_type)
2977 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
2978 if (!(erase_type & BIT(i)))
2980 if (region->size & erase[i].size_mask) {
2981 spi_nor_region_mark_overlay(region);
2988 * spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map
2989 * @nor: pointer to a 'struct spi_nor'
2990 * @smpt: pointer to the sector map parameter table
2992 * Return: 0 on success, -errno otherwise.
2994 static int spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
2997 struct spi_nor_erase_map *map = &nor->erase_map;
2998 struct spi_nor_erase_type *erase = map->erase_type;
2999 struct spi_nor_erase_region *region;
3003 u8 uniform_erase_type, save_uniform_erase_type;
3004 u8 erase_type, regions_erase_type;
3006 region_count = SMPT_MAP_REGION_COUNT(*smpt);
3008 * The regions will be freed when the driver detaches from the
3011 region = devm_kcalloc(nor->dev, region_count, sizeof(*region),
3015 map->regions = region;
3017 uniform_erase_type = 0xff;
3018 regions_erase_type = 0;
3020 /* Populate regions. */
3021 for (i = 0; i < region_count; i++) {
3022 j = i + 1; /* index for the region dword */
3023 region[i].size = SMPT_MAP_REGION_SIZE(smpt[j]);
3024 erase_type = SMPT_MAP_REGION_ERASE_TYPE(smpt[j]);
3025 region[i].offset = offset | erase_type;
3027 spi_nor_region_check_overlay(®ion[i], erase, erase_type);
3030 * Save the erase types that are supported in all regions and
3031 * can erase the entire flash memory.
3033 uniform_erase_type &= erase_type;
3036 * regions_erase_type mask will indicate all the erase types
3037 * supported in this configuration map.
3039 regions_erase_type |= erase_type;
3041 offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) +
3045 save_uniform_erase_type = map->uniform_erase_type;
3046 map->uniform_erase_type = spi_nor_sort_erase_mask(map,
3047 uniform_erase_type);
3049 if (!regions_erase_type) {
3051 * Roll back to the previous uniform_erase_type mask, SMPT is
3054 map->uniform_erase_type = save_uniform_erase_type;
3059 * BFPT advertises all the erase types supported by all the possible
3060 * map configurations. Mask out the erase types that are not supported
3061 * by the current map configuration.
3063 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
3064 if (!(regions_erase_type & BIT(erase[i].idx)))
3065 spi_nor_set_erase_type(&erase[i], 0, 0xFF);
3067 spi_nor_region_mark_end(®ion[i - 1]);
3073 * spi_nor_parse_smpt() - parse Sector Map Parameter Table
3074 * @nor: pointer to a 'struct spi_nor'
3075 * @smpt_header: sector map parameter table header
3077 * This table is optional, but when available, we parse it to identify the
3078 * location and size of sectors within the main data array of the flash memory
3079 * device and to identify which Erase Types are supported by each sector.
3081 * Return: 0 on success, -errno otherwise.
3083 static int spi_nor_parse_smpt(struct spi_nor *nor,
3084 const struct sfdp_parameter_header *smpt_header)
3086 const u32 *sector_map;
3092 /* Read the Sector Map Parameter Table. */
3093 len = smpt_header->length * sizeof(*smpt);
3094 smpt = kzalloc(len, GFP_KERNEL);
3098 addr = SFDP_PARAM_HEADER_PTP(smpt_header);
3099 ret = spi_nor_read_sfdp(nor, addr, len, smpt);
3103 /* Fix endianness of the SMPT DWORDs. */
3104 for (i = 0; i < smpt_header->length; i++)
3105 smpt[i] = le32_to_cpu(smpt[i]);
3107 sector_map = spi_nor_get_map_in_use(nor, smpt, smpt_header->length);
3108 if (IS_ERR(sector_map)) {
3109 ret = PTR_ERR(sector_map);
3113 ret = spi_nor_init_non_uniform_erase_map(nor, sector_map);
3117 spi_nor_regions_sort_erase_types(&nor->erase_map);
3125 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
3126 * @nor: pointer to a 'struct spi_nor'
3127 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
3130 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
3131 * specification. This is a standard which tends to supported by almost all
3132 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
3133 * runtime the main parameters needed to perform basic SPI flash operations such
3134 * as Fast Read, Page Program or Sector Erase commands.
3136 * Return: 0 on success, -errno otherwise.
3138 static int spi_nor_parse_sfdp(struct spi_nor *nor,
3139 struct spi_nor_flash_parameter *params)
3141 const struct sfdp_parameter_header *param_header, *bfpt_header;
3142 struct sfdp_parameter_header *param_headers = NULL;
3143 struct sfdp_header header;
3144 struct device *dev = nor->dev;
3148 /* Get the SFDP header. */
3149 err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
3153 /* Check the SFDP header version. */
3154 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
3155 header.major != SFDP_JESD216_MAJOR)
3159 * Verify that the first and only mandatory parameter header is a
3160 * Basic Flash Parameter Table header as specified in JESD216.
3162 bfpt_header = &header.bfpt_header;
3163 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
3164 bfpt_header->major != SFDP_JESD216_MAJOR)
3168 * Allocate memory then read all parameter headers with a single
3169 * Read SFDP command. These parameter headers will actually be parsed
3170 * twice: a first time to get the latest revision of the basic flash
3171 * parameter table, then a second time to handle the supported optional
3173 * Hence we read the parameter headers once for all to reduce the
3174 * processing time. Also we use kmalloc() instead of devm_kmalloc()
3175 * because we don't need to keep these parameter headers: the allocated
3176 * memory is always released with kfree() before exiting this function.
3179 psize = header.nph * sizeof(*param_headers);
3181 param_headers = kmalloc(psize, GFP_KERNEL);
3185 err = spi_nor_read_sfdp(nor, sizeof(header),
3186 psize, param_headers);
3188 dev_err(dev, "failed to read SFDP parameter headers\n");
3194 * Check other parameter headers to get the latest revision of
3195 * the basic flash parameter table.
3197 for (i = 0; i < header.nph; i++) {
3198 param_header = ¶m_headers[i];
3200 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
3201 param_header->major == SFDP_JESD216_MAJOR &&
3202 (param_header->minor > bfpt_header->minor ||
3203 (param_header->minor == bfpt_header->minor &&
3204 param_header->length > bfpt_header->length)))
3205 bfpt_header = param_header;
3208 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
3212 /* Parse optional parameter tables. */
3213 for (i = 0; i < header.nph; i++) {
3214 param_header = ¶m_headers[i];
3216 switch (SFDP_PARAM_HEADER_ID(param_header)) {
3217 case SFDP_SECTOR_MAP_ID:
3218 err = spi_nor_parse_smpt(nor, param_header);
3226 dev_warn(dev, "Failed to parse optional parameter table: %04x\n",
3227 SFDP_PARAM_HEADER_ID(param_header));
3229 * Let's not drop all information we extracted so far
3230 * if optional table parsers fail. In case of failing,
3231 * each optional parser is responsible to roll back to
3232 * the previously known spi_nor data.
3239 kfree(param_headers);
3243 static int spi_nor_init_params(struct spi_nor *nor,
3244 const struct flash_info *info,
3245 struct spi_nor_flash_parameter *params)
3247 struct spi_nor_erase_map *map = &nor->erase_map;
3250 /* Set legacy flash parameters as default. */
3251 memset(params, 0, sizeof(*params));
3253 /* Set SPI NOR sizes. */
3254 params->size = info->sector_size * info->n_sectors;
3255 params->page_size = info->page_size;
3257 /* (Fast) Read settings. */
3258 params->hwcaps.mask |= SNOR_HWCAPS_READ;
3259 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
3260 0, 0, SPINOR_OP_READ,
3263 if (!(info->flags & SPI_NOR_NO_FR)) {
3264 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
3265 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
3266 0, 8, SPINOR_OP_READ_FAST,
3270 if (info->flags & SPI_NOR_DUAL_READ) {
3271 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
3272 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
3273 0, 8, SPINOR_OP_READ_1_1_2,
3277 if (info->flags & SPI_NOR_QUAD_READ) {
3278 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
3279 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
3280 0, 8, SPINOR_OP_READ_1_1_4,
3284 /* Page Program settings. */
3285 params->hwcaps.mask |= SNOR_HWCAPS_PP;
3286 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
3287 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
3290 * Sector Erase settings. Sort Erase Types in ascending order, with the
3291 * smallest erase size starting at BIT(0).
3295 if (info->flags & SECT_4K_PMC) {
3296 erase_mask |= BIT(i);
3297 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
3298 SPINOR_OP_BE_4K_PMC);
3300 } else if (info->flags & SECT_4K) {
3301 erase_mask |= BIT(i);
3302 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
3306 erase_mask |= BIT(i);
3307 spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
3309 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
3311 /* Select the procedure to set the Quad Enable bit. */
3312 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
3313 SNOR_HWCAPS_PP_QUAD)) {
3314 switch (JEDEC_MFR(info)) {
3315 case SNOR_MFR_MACRONIX:
3316 params->quad_enable = macronix_quad_enable;
3319 case SNOR_MFR_MICRON:
3323 /* Kept only for backward compatibility purpose. */
3324 params->quad_enable = spansion_quad_enable;
3329 * Some manufacturer like GigaDevice may use different
3330 * bit to set QE on different memories, so the MFR can't
3331 * indicate the quad_enable method for this case, we need
3332 * set it in flash info list.
3334 if (info->quad_enable)
3335 params->quad_enable = info->quad_enable;
3338 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
3339 !(info->flags & SPI_NOR_SKIP_SFDP)) {
3340 struct spi_nor_flash_parameter sfdp_params;
3341 struct spi_nor_erase_map prev_map;
3343 memcpy(&sfdp_params, params, sizeof(sfdp_params));
3344 memcpy(&prev_map, &nor->erase_map, sizeof(prev_map));
3346 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
3347 nor->addr_width = 0;
3348 /* restore previous erase map */
3349 memcpy(&nor->erase_map, &prev_map,
3350 sizeof(nor->erase_map));
3352 memcpy(params, &sfdp_params, sizeof(*params));
3359 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
3363 for (i = 0; i < size; i++)
3364 if (table[i][0] == (int)hwcaps)
3370 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
3372 static const int hwcaps_read2cmd[][2] = {
3373 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
3374 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
3375 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
3376 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
3377 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
3378 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
3379 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
3380 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
3381 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
3382 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
3383 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
3384 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
3385 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
3386 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
3387 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
3390 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
3391 ARRAY_SIZE(hwcaps_read2cmd));
3394 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
3396 static const int hwcaps_pp2cmd[][2] = {
3397 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
3398 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
3399 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
3400 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
3401 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
3402 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
3403 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
3406 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
3407 ARRAY_SIZE(hwcaps_pp2cmd));
3410 static int spi_nor_select_read(struct spi_nor *nor,
3411 const struct spi_nor_flash_parameter *params,
3414 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
3415 const struct spi_nor_read_command *read;
3420 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
3424 read = ¶ms->reads[cmd];
3425 nor->read_opcode = read->opcode;
3426 nor->read_proto = read->proto;
3429 * In the spi-nor framework, we don't need to make the difference
3430 * between mode clock cycles and wait state clock cycles.
3431 * Indeed, the value of the mode clock cycles is used by a QSPI
3432 * flash memory to know whether it should enter or leave its 0-4-4
3433 * (Continuous Read / XIP) mode.
3434 * eXecution In Place is out of the scope of the mtd sub-system.
3435 * Hence we choose to merge both mode and wait state clock cycles
3436 * into the so called dummy clock cycles.
3438 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
3442 static int spi_nor_select_pp(struct spi_nor *nor,
3443 const struct spi_nor_flash_parameter *params,
3446 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
3447 const struct spi_nor_pp_command *pp;
3452 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
3456 pp = ¶ms->page_programs[cmd];
3457 nor->program_opcode = pp->opcode;
3458 nor->write_proto = pp->proto;
3463 * spi_nor_select_uniform_erase() - select optimum uniform erase type
3464 * @map: the erase map of the SPI NOR
3465 * @wanted_size: the erase type size to search for. Contains the value of
3466 * info->sector_size or of the "small sector" size in case
3467 * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
3469 * Once the optimum uniform sector erase command is found, disable all the
3472 * Return: pointer to erase type on success, NULL otherwise.
3474 static const struct spi_nor_erase_type *
3475 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
3476 const u32 wanted_size)
3478 const struct spi_nor_erase_type *tested_erase, *erase = NULL;
3480 u8 uniform_erase_type = map->uniform_erase_type;
3482 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
3483 if (!(uniform_erase_type & BIT(i)))
3486 tested_erase = &map->erase_type[i];
3489 * If the current erase size is the one, stop here:
3490 * we have found the right uniform Sector Erase command.
3492 if (tested_erase->size == wanted_size) {
3493 erase = tested_erase;
3498 * Otherwise, the current erase size is still a valid canditate.
3499 * Select the biggest valid candidate.
3501 if (!erase && tested_erase->size)
3502 erase = tested_erase;
3503 /* keep iterating to find the wanted_size */
3509 /* Disable all other Sector Erase commands. */
3510 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
3511 map->uniform_erase_type |= BIT(erase - map->erase_type);
3515 static int spi_nor_select_erase(struct spi_nor *nor, u32 wanted_size)
3517 struct spi_nor_erase_map *map = &nor->erase_map;
3518 const struct spi_nor_erase_type *erase = NULL;
3519 struct mtd_info *mtd = &nor->mtd;
3523 * The previous implementation handling Sector Erase commands assumed
3524 * that the SPI flash memory has an uniform layout then used only one
3525 * of the supported erase sizes for all Sector Erase commands.
3526 * So to be backward compatible, the new implementation also tries to
3527 * manage the SPI flash memory as uniform with a single erase sector
3528 * size, when possible.
3530 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
3531 /* prefer "small sector" erase if possible */
3532 wanted_size = 4096u;
3535 if (spi_nor_has_uniform_erase(nor)) {
3536 erase = spi_nor_select_uniform_erase(map, wanted_size);
3539 nor->erase_opcode = erase->opcode;
3540 mtd->erasesize = erase->size;
3545 * For non-uniform SPI flash memory, set mtd->erasesize to the
3546 * maximum erase sector size. No need to set nor->erase_opcode.
3548 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
3549 if (map->erase_type[i].size) {
3550 erase = &map->erase_type[i];
3558 mtd->erasesize = erase->size;
3562 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
3563 const struct spi_nor_flash_parameter *params,
3564 const struct spi_nor_hwcaps *hwcaps)
3566 u32 ignored_mask, shared_mask;
3567 bool enable_quad_io;
3571 * Keep only the hardware capabilities supported by both the SPI
3572 * controller and the SPI flash memory.
3574 shared_mask = hwcaps->mask & params->hwcaps.mask;
3576 /* SPI n-n-n protocols are not supported yet. */
3577 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
3578 SNOR_HWCAPS_READ_4_4_4 |
3579 SNOR_HWCAPS_READ_8_8_8 |
3580 SNOR_HWCAPS_PP_4_4_4 |
3581 SNOR_HWCAPS_PP_8_8_8);
3582 if (shared_mask & ignored_mask) {
3584 "SPI n-n-n protocols are not supported yet.\n");
3585 shared_mask &= ~ignored_mask;
3588 /* Select the (Fast) Read command. */
3589 err = spi_nor_select_read(nor, params, shared_mask);
3592 "can't select read settings supported by both the SPI controller and memory.\n");
3596 /* Select the Page Program command. */
3597 err = spi_nor_select_pp(nor, params, shared_mask);
3600 "can't select write settings supported by both the SPI controller and memory.\n");
3604 /* Select the Sector Erase command. */
3605 err = spi_nor_select_erase(nor, info->sector_size);
3608 "can't select erase settings supported by both the SPI controller and memory.\n");
3612 /* Enable Quad I/O if needed. */
3613 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
3614 spi_nor_get_protocol_width(nor->write_proto) == 4);
3615 if (enable_quad_io && params->quad_enable)
3616 nor->quad_enable = params->quad_enable;
3618 nor->quad_enable = NULL;
3623 static int spi_nor_init(struct spi_nor *nor)
3628 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
3629 * with the software protection bits set
3631 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
3632 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
3633 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
3634 nor->info->flags & SPI_NOR_HAS_LOCK) {
3637 spi_nor_wait_till_ready(nor);
3640 if (nor->quad_enable) {
3641 err = nor->quad_enable(nor);
3643 dev_err(nor->dev, "quad mode not supported\n");
3648 if ((nor->addr_width == 4) &&
3649 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
3650 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
3652 * If the RESET# pin isn't hooked up properly, or the system
3653 * otherwise doesn't perform a reset command in the boot
3654 * sequence, it's impossible to 100% protect against unexpected
3655 * reboots (e.g., crashes). Warn the user (or hopefully, system
3656 * designer) that this is bad.
3658 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
3659 "enabling reset hack; may not recover from unexpected reboots\n");
3660 set_4byte(nor, nor->info, 1);
3666 /* mtd resume handler */
3667 static void spi_nor_resume(struct mtd_info *mtd)
3669 struct spi_nor *nor = mtd_to_spi_nor(mtd);
3670 struct device *dev = nor->dev;
3673 /* re-initialize the nor chip */
3674 ret = spi_nor_init(nor);
3676 dev_err(dev, "resume() failed\n");
3679 void spi_nor_restore(struct spi_nor *nor)
3681 /* restore the addressing mode */
3682 if ((nor->addr_width == 4) &&
3683 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
3684 !(nor->info->flags & SPI_NOR_4B_OPCODES) &&
3685 (nor->flags & SNOR_F_BROKEN_RESET))
3686 set_4byte(nor, nor->info, 0);
3688 EXPORT_SYMBOL_GPL(spi_nor_restore);
3690 int spi_nor_scan(struct spi_nor *nor, const char *name,
3691 const struct spi_nor_hwcaps *hwcaps)
3693 struct spi_nor_flash_parameter params;
3694 const struct flash_info *info = NULL;
3695 struct device *dev = nor->dev;
3696 struct mtd_info *mtd = &nor->mtd;
3697 struct device_node *np = spi_nor_get_flash_node(nor);
3701 ret = spi_nor_check(nor);
3705 /* Reset SPI protocol for all commands. */
3706 nor->reg_proto = SNOR_PROTO_1_1_1;
3707 nor->read_proto = SNOR_PROTO_1_1_1;
3708 nor->write_proto = SNOR_PROTO_1_1_1;
3711 info = spi_nor_match_id(name);
3712 /* Try to auto-detect if chip name wasn't specified or not found */
3714 info = spi_nor_read_id(nor);
3715 if (IS_ERR_OR_NULL(info))
3719 * If caller has specified name of flash model that can normally be
3720 * detected using JEDEC, let's verify it.
3722 if (name && info->id_len) {
3723 const struct flash_info *jinfo;
3725 jinfo = spi_nor_read_id(nor);
3726 if (IS_ERR(jinfo)) {
3727 return PTR_ERR(jinfo);
3728 } else if (jinfo != info) {
3730 * JEDEC knows better, so overwrite platform ID. We
3731 * can't trust partitions any longer, but we'll let
3732 * mtd apply them anyway, since some partitions may be
3733 * marked read-only, and we don't want to lose that
3734 * information, even if it's not 100% accurate.
3736 dev_warn(dev, "found %s, expected %s\n",
3737 jinfo->name, info->name);
3742 mutex_init(&nor->lock);
3745 * Make sure the XSR_RDY flag is set before calling
3746 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
3747 * with Atmel spi-nor
3749 if (info->flags & SPI_S3AN)
3750 nor->flags |= SNOR_F_READY_XSR_RDY;
3752 /* Parse the Serial Flash Discoverable Parameters table. */
3753 ret = spi_nor_init_params(nor, info, ¶ms);
3758 mtd->name = dev_name(dev);
3760 mtd->type = MTD_NORFLASH;
3762 mtd->flags = MTD_CAP_NORFLASH;
3763 mtd->size = params.size;
3764 mtd->_erase = spi_nor_erase;
3765 mtd->_read = spi_nor_read;
3766 mtd->_resume = spi_nor_resume;
3768 /* NOR protection support for STmicro/Micron chips and similar */
3769 if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
3770 info->flags & SPI_NOR_HAS_LOCK) {
3771 nor->flash_lock = stm_lock;
3772 nor->flash_unlock = stm_unlock;
3773 nor->flash_is_locked = stm_is_locked;
3776 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
3777 mtd->_lock = spi_nor_lock;
3778 mtd->_unlock = spi_nor_unlock;
3779 mtd->_is_locked = spi_nor_is_locked;
3782 /* sst nor chips use AAI word program */
3783 if (info->flags & SST_WRITE)
3784 mtd->_write = sst_write;
3786 mtd->_write = spi_nor_write;
3788 if (info->flags & USE_FSR)
3789 nor->flags |= SNOR_F_USE_FSR;
3790 if (info->flags & SPI_NOR_HAS_TB)
3791 nor->flags |= SNOR_F_HAS_SR_TB;
3792 if (info->flags & NO_CHIP_ERASE)
3793 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
3794 if (info->flags & USE_CLSR)
3795 nor->flags |= SNOR_F_USE_CLSR;
3797 if (info->flags & SPI_NOR_NO_ERASE)
3798 mtd->flags |= MTD_NO_ERASE;
3800 mtd->dev.parent = dev;
3801 nor->page_size = params.page_size;
3802 mtd->writebufsize = nor->page_size;
3805 /* If we were instantiated by DT, use it */
3806 if (of_property_read_bool(np, "m25p,fast-read"))
3807 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
3809 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
3811 /* If we weren't instantiated by DT, default to fast-read */
3812 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
3815 if (of_property_read_bool(np, "broken-flash-reset"))
3816 nor->flags |= SNOR_F_BROKEN_RESET;
3818 /* Some devices cannot do fast-read, no matter what DT tells us */
3819 if (info->flags & SPI_NOR_NO_FR)
3820 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
3823 * Configure the SPI memory:
3824 * - select op codes for (Fast) Read, Page Program and Sector Erase.
3825 * - set the number of dummy cycles (mode cycles + wait states).
3826 * - set the SPI protocols for register and memory accesses.
3827 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
3829 ret = spi_nor_setup(nor, info, ¶ms, hwcaps);
3833 if (nor->addr_width) {
3834 /* already configured from SFDP */
3835 } else if (info->addr_width) {
3836 nor->addr_width = info->addr_width;
3837 } else if (mtd->size > 0x1000000) {
3838 /* enable 4-byte addressing if the device exceeds 16MiB */
3839 nor->addr_width = 4;
3840 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
3841 info->flags & SPI_NOR_4B_OPCODES)
3842 spi_nor_set_4byte_opcodes(nor, info);
3844 nor->addr_width = 3;
3847 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
3848 dev_err(dev, "address width is too large: %u\n",
3853 if (info->flags & SPI_S3AN) {
3854 ret = s3an_nor_scan(info, nor);
3859 /* Send all the required SPI flash commands to initialize device */
3861 ret = spi_nor_init(nor);
3865 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
3866 (long long)mtd->size >> 10);
3869 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
3870 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
3871 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
3872 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
3874 if (mtd->numeraseregions)
3875 for (i = 0; i < mtd->numeraseregions; i++)
3877 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
3878 ".erasesize = 0x%.8x (%uKiB), "
3879 ".numblocks = %d }\n",
3880 i, (long long)mtd->eraseregions[i].offset,
3881 mtd->eraseregions[i].erasesize,
3882 mtd->eraseregions[i].erasesize / 1024,
3883 mtd->eraseregions[i].numblocks);
3886 EXPORT_SYMBOL_GPL(spi_nor_scan);
3888 static const struct flash_info *spi_nor_match_id(const char *name)
3890 const struct flash_info *id = spi_nor_ids;
3893 if (!strcmp(name, id->name))
3900 MODULE_LICENSE("GPL");
3901 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3902 MODULE_AUTHOR("Mike Lavender");
3903 MODULE_DESCRIPTION("framework for SPI NOR");