2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
26 /* Define max times to check status register before we give up. */
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
32 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
35 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
38 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
40 #define SPI_NOR_MAX_ID_LEN 6
41 #define SPI_NOR_MAX_ADDR_WIDTH 4
47 * This array stores the ID bytes.
48 * The first three bytes are the JEDIC ID.
49 * JEDEC ID zero means "no ID" (mostly older chips).
51 u8 id[SPI_NOR_MAX_ID_LEN];
54 /* The size listed here is what works with SPINOR_OP_SE, which isn't
55 * necessarily called a "sector" by the vendor.
64 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
65 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
66 #define SST_WRITE BIT(2) /* use SST byte programming */
67 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
68 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
69 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
70 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
71 #define USE_FSR BIT(7) /* use flag status register */
72 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
73 #define SPI_NOR_HAS_TB BIT(9) /*
74 * Flash SR has Top/Bottom (TB) protect
75 * bit. Must be used with
80 #define JEDEC_MFR(info) ((info)->id[0])
82 static const struct flash_info *spi_nor_match_id(const char *name);
85 * Read the status register, returning its value in the location
86 * Return the status register value.
87 * Returns negative if error occurred.
89 static int read_sr(struct spi_nor *nor)
94 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
96 pr_err("error %d reading SR\n", (int) ret);
104 * Read the flag status register, returning its value in the location
105 * Return the status register value.
106 * Returns negative if error occurred.
108 static int read_fsr(struct spi_nor *nor)
113 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
115 pr_err("error %d reading FSR\n", ret);
123 * Read configuration register, returning its value in the
124 * location. Return the configuration register value.
125 * Returns negative if error occured.
127 static int read_cr(struct spi_nor *nor)
132 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
134 dev_err(nor->dev, "error %d reading CR\n", ret);
142 * Dummy Cycle calculation for different type of read.
143 * It can be used to support more commands with
144 * different dummy cycle requirements.
146 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
148 switch (nor->flash_read) {
160 * Write status register 1 byte
161 * Returns negative if error occurred.
163 static inline int write_sr(struct spi_nor *nor, u8 val)
165 nor->cmd_buf[0] = val;
166 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
170 * Set write enable latch with Write Enable command.
171 * Returns negative if error occurred.
173 static inline int write_enable(struct spi_nor *nor)
175 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
179 * Send write disble instruction to the chip.
181 static inline int write_disable(struct spi_nor *nor)
183 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
186 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
191 /* Enable/disable 4-byte addressing mode. */
192 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
196 bool need_wren = false;
199 switch (JEDEC_MFR(info)) {
200 case SNOR_MFR_MICRON:
201 /* Some Micron need WREN command; all will accept it */
203 case SNOR_MFR_MACRONIX:
204 case SNOR_MFR_WINBOND:
208 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
209 status = nor->write_reg(nor, cmd, NULL, 0);
216 nor->cmd_buf[0] = enable << 7;
217 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
220 static inline int spi_nor_sr_ready(struct spi_nor *nor)
222 int sr = read_sr(nor);
226 return !(sr & SR_WIP);
229 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
231 int fsr = read_fsr(nor);
235 return fsr & FSR_READY;
238 static int spi_nor_ready(struct spi_nor *nor)
241 sr = spi_nor_sr_ready(nor);
244 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
251 * Service routine to read status register until ready, or timeout occurs.
252 * Returns non-zero if error.
254 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
255 unsigned long timeout_jiffies)
257 unsigned long deadline;
258 int timeout = 0, ret;
260 deadline = jiffies + timeout_jiffies;
263 if (time_after_eq(jiffies, deadline))
266 ret = spi_nor_ready(nor);
275 dev_err(nor->dev, "flash operation timed out\n");
280 static int spi_nor_wait_till_ready(struct spi_nor *nor)
282 return spi_nor_wait_till_ready_with_timeout(nor,
283 DEFAULT_READY_WAIT_JIFFIES);
287 * Erase the whole flash memory
289 * Returns 0 if successful, non-zero otherwise.
291 static int erase_chip(struct spi_nor *nor)
293 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
295 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
298 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
302 mutex_lock(&nor->lock);
305 ret = nor->prepare(nor, ops);
307 dev_err(nor->dev, "failed in the preparation.\n");
308 mutex_unlock(&nor->lock);
315 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
318 nor->unprepare(nor, ops);
319 mutex_unlock(&nor->lock);
323 * Initiate the erasure of a single sector
325 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
327 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
331 return nor->erase(nor, addr);
334 * Default implementation, if driver doesn't have a specialized HW
337 for (i = nor->addr_width - 1; i >= 0; i--) {
338 buf[i] = addr & 0xff;
342 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
346 * Erase an address range on the nor chip. The address range may extend
347 * one or more erase sectors. Return an error is there is a problem erasing.
349 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
351 struct spi_nor *nor = mtd_to_spi_nor(mtd);
356 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
357 (long long)instr->len);
359 div_u64_rem(instr->len, mtd->erasesize, &rem);
366 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
370 /* whole-chip erase? */
371 if (len == mtd->size) {
372 unsigned long timeout;
376 if (erase_chip(nor)) {
382 * Scale the timeout linearly with the size of the flash, with
383 * a minimum calibrated to an old 2MB flash. We could try to
384 * pull these from CFI/SFDP, but these values should be good
387 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
388 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
389 (unsigned long)(mtd->size / SZ_2M));
390 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
394 /* REVISIT in some cases we could speed up erasing large regions
395 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
396 * to use "small sector erase", but that's not always optimal.
399 /* "sector"-at-a-time erase */
404 ret = spi_nor_erase_sector(nor, addr);
408 addr += mtd->erasesize;
409 len -= mtd->erasesize;
411 ret = spi_nor_wait_till_ready(nor);
420 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
422 instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
423 mtd_erase_callback(instr);
428 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
431 struct mtd_info *mtd = &nor->mtd;
432 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
433 int shift = ffs(mask) - 1;
441 pow = ((sr & mask) ^ mask) >> shift;
442 *len = mtd->size >> pow;
443 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
446 *ofs = mtd->size - *len;
451 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
452 * @locked is false); 0 otherwise
454 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
463 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
466 /* Requested range is a sub-range of locked range */
467 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
469 /* Requested range does not overlap with locked range */
470 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
473 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
476 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
479 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
482 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
486 * Lock a region of the flash. Compatible with ST Micro and similar flash.
487 * Supports the block protection bits BP{0,1,2} in the status register
488 * (SR). Does not support these features found in newer SR bitfields:
489 * - SEC: sector/block protect - only handle SEC=0 (block protect)
490 * - CMP: complement protect - only support CMP=0 (range is not complemented)
492 * Support for the following is provided conditionally for some flash:
493 * - TB: top/bottom protect
495 * Sample table portion for 8MB flash (Winbond w25q64fw):
497 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
498 * --------------------------------------------------------------------------
499 * X | X | 0 | 0 | 0 | NONE | NONE
500 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
501 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
502 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
503 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
504 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
505 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
506 * X | X | 1 | 1 | 1 | 8 MB | ALL
507 * ------|-------|-------|-------|-------|---------------|-------------------
508 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
509 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
510 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
511 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
512 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
513 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
515 * Returns negative on errors, 0 on success.
517 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
519 struct mtd_info *mtd = &nor->mtd;
520 int status_old, status_new;
521 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
522 u8 shift = ffs(mask) - 1, pow, val;
524 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
528 status_old = read_sr(nor);
532 /* If nothing in our range is unlocked, we don't need to do anything */
533 if (stm_is_locked_sr(nor, ofs, len, status_old))
536 /* If anything below us is unlocked, we can't use 'bottom' protection */
537 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
538 can_be_bottom = false;
540 /* If anything above us is unlocked, we can't use 'top' protection */
541 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
545 if (!can_be_bottom && !can_be_top)
548 /* Prefer top, if both are valid */
549 use_top = can_be_top;
551 /* lock_len: length of region that should end up locked */
553 lock_len = mtd->size - ofs;
555 lock_len = ofs + len;
558 * Need smallest pow such that:
560 * 1 / (2^pow) <= (len / size)
562 * so (assuming power-of-2 size) we do:
564 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
566 pow = ilog2(mtd->size) - ilog2(lock_len);
567 val = mask - (pow << shift);
570 /* Don't "lock" with no region! */
574 status_new = (status_old & ~mask & ~SR_TB) | val;
576 /* Disallow further writes if WP pin is asserted */
577 status_new |= SR_SRWD;
582 /* Don't bother if they're the same */
583 if (status_new == status_old)
586 /* Only modify protection if it will not unlock other areas */
587 if ((status_new & mask) < (status_old & mask))
591 ret = write_sr(nor, status_new);
594 return spi_nor_wait_till_ready(nor);
598 * Unlock a region of the flash. See stm_lock() for more info
600 * Returns negative on errors, 0 on success.
602 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
604 struct mtd_info *mtd = &nor->mtd;
605 int status_old, status_new;
606 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
607 u8 shift = ffs(mask) - 1, pow, val;
609 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
613 status_old = read_sr(nor);
617 /* If nothing in our range is locked, we don't need to do anything */
618 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
621 /* If anything below us is locked, we can't use 'top' protection */
622 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
625 /* If anything above us is locked, we can't use 'bottom' protection */
626 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
628 can_be_bottom = false;
630 if (!can_be_bottom && !can_be_top)
633 /* Prefer top, if both are valid */
634 use_top = can_be_top;
636 /* lock_len: length of region that should remain locked */
638 lock_len = mtd->size - (ofs + len);
643 * Need largest pow such that:
645 * 1 / (2^pow) >= (len / size)
647 * so (assuming power-of-2 size) we do:
649 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
651 pow = ilog2(mtd->size) - order_base_2(lock_len);
653 val = 0; /* fully unlocked */
655 val = mask - (pow << shift);
656 /* Some power-of-two sizes are not supported */
661 status_new = (status_old & ~mask & ~SR_TB) | val;
663 /* Don't protect status register if we're fully unlocked */
665 status_new &= ~SR_SRWD;
670 /* Don't bother if they're the same */
671 if (status_new == status_old)
674 /* Only modify protection if it will not lock other areas */
675 if ((status_new & mask) > (status_old & mask))
679 ret = write_sr(nor, status_new);
682 return spi_nor_wait_till_ready(nor);
686 * Check if a region of the flash is (completely) locked. See stm_lock() for
689 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
690 * negative on errors.
692 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
696 status = read_sr(nor);
700 return stm_is_locked_sr(nor, ofs, len, status);
703 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
705 struct spi_nor *nor = mtd_to_spi_nor(mtd);
708 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
712 ret = nor->flash_lock(nor, ofs, len);
714 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
718 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
720 struct spi_nor *nor = mtd_to_spi_nor(mtd);
723 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
727 ret = nor->flash_unlock(nor, ofs, len);
729 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
733 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
735 struct spi_nor *nor = mtd_to_spi_nor(mtd);
738 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
742 ret = nor->flash_is_locked(nor, ofs, len);
744 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
748 /* Used when the "_ext_id" is two bytes at most */
749 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
751 ((_jedec_id) >> 16) & 0xff, \
752 ((_jedec_id) >> 8) & 0xff, \
753 (_jedec_id) & 0xff, \
754 ((_ext_id) >> 8) & 0xff, \
757 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
758 .sector_size = (_sector_size), \
759 .n_sectors = (_n_sectors), \
763 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
765 ((_jedec_id) >> 16) & 0xff, \
766 ((_jedec_id) >> 8) & 0xff, \
767 (_jedec_id) & 0xff, \
768 ((_ext_id) >> 16) & 0xff, \
769 ((_ext_id) >> 8) & 0xff, \
773 .sector_size = (_sector_size), \
774 .n_sectors = (_n_sectors), \
778 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
779 .sector_size = (_sector_size), \
780 .n_sectors = (_n_sectors), \
781 .page_size = (_page_size), \
782 .addr_width = (_addr_width), \
785 /* NOTE: double check command sets and memory organization when you add
786 * more nor chips. This current list focusses on newer chips, which
787 * have been converging on command sets which including JEDEC ID.
789 * All newly added entries should describe *hardware* and should use SECT_4K
790 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
791 * scenarios excluding small sectors there is config option that can be
792 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
793 * For historical (and compatibility) reasons (before we got above config) some
794 * old entries may be missing 4K flag.
796 static const struct flash_info spi_nor_ids[] = {
797 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
798 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
799 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
801 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
802 { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
803 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
804 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
806 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
807 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
808 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
809 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
811 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
814 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
815 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
816 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
817 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
818 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
819 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
820 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
821 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
824 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
827 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
828 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
829 { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
832 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
836 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
837 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
838 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
841 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
842 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
843 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
846 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
847 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
848 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
851 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
852 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
853 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
856 /* Intel/Numonyx -- xxxs33b */
857 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
858 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
859 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
862 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
865 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
866 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
867 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
868 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
869 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
870 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
871 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
872 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
873 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
874 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
875 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
876 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
877 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
878 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
879 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
880 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
883 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
884 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
885 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
886 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
887 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
888 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
889 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
890 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
891 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
892 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
893 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
894 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
897 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
898 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
899 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
901 /* Spansion -- single (large) sector size only, at least
902 * for the chips listed here (without boot sectors).
904 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
905 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
906 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
907 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
908 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
909 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
910 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
911 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
912 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
913 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
914 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
915 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
916 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
917 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
918 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
919 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
920 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
921 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
922 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
923 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
924 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
925 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
926 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
927 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
928 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
930 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
931 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
932 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
933 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
934 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
935 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
936 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
937 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
938 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
939 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
940 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
941 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
942 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
944 /* ST Microelectronics -- newer production may have feature updates */
945 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
946 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
947 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
948 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
949 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
950 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
951 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
952 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
953 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
955 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
956 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
957 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
958 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
959 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
960 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
961 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
962 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
963 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
965 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
966 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
967 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
969 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
970 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
971 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
973 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
974 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
975 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
976 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
977 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
978 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
980 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
981 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
982 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
983 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
984 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
985 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
986 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
987 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
988 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
990 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
991 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
992 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
994 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
995 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
997 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
998 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
999 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1002 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
1003 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1004 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1006 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1007 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1008 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1009 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
1011 /* Catalyst / On Semiconductor -- non-JEDEC */
1012 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1013 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1014 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1015 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1016 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1020 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1023 u8 id[SPI_NOR_MAX_ID_LEN];
1024 const struct flash_info *info;
1026 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1028 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1029 return ERR_PTR(tmp);
1032 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1033 info = &spi_nor_ids[tmp];
1035 if (!memcmp(info->id, id, info->id_len))
1036 return &spi_nor_ids[tmp];
1039 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1040 id[0], id[1], id[2]);
1041 return ERR_PTR(-ENODEV);
1044 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1045 size_t *retlen, u_char *buf)
1047 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1050 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1052 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
1057 ret = nor->read(nor, from, len, buf);
1059 /* We shouldn't see 0-length reads */
1075 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
1079 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1080 size_t *retlen, const u_char *buf)
1082 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1086 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1088 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1094 nor->sst_write_second = false;
1097 /* Start write from odd address. */
1099 nor->program_opcode = SPINOR_OP_BP;
1101 /* write one byte. */
1102 ret = nor->write(nor, to, 1, buf);
1105 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1107 ret = spi_nor_wait_till_ready(nor);
1113 /* Write out most of the data here. */
1114 for (; actual < len - 1; actual += 2) {
1115 nor->program_opcode = SPINOR_OP_AAI_WP;
1117 /* write two bytes. */
1118 ret = nor->write(nor, to, 2, buf + actual);
1121 WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
1123 ret = spi_nor_wait_till_ready(nor);
1127 nor->sst_write_second = true;
1129 nor->sst_write_second = false;
1132 ret = spi_nor_wait_till_ready(nor);
1136 /* Write out trailing byte if it exists. */
1137 if (actual != len) {
1140 nor->program_opcode = SPINOR_OP_BP;
1141 ret = nor->write(nor, to, 1, buf + actual);
1144 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1146 ret = spi_nor_wait_till_ready(nor);
1154 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1159 * Write an address range to the nor chip. Data must be written in
1160 * FLASH_PAGESIZE chunks. The address range may be any size provided
1161 * it is within the physical boundaries.
1163 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1164 size_t *retlen, const u_char *buf)
1166 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1167 size_t page_offset, page_remain, i;
1170 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1172 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1176 for (i = 0; i < len; ) {
1179 page_offset = (to + i) & (nor->page_size - 1);
1180 WARN_ONCE(page_offset,
1181 "Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.",
1183 /* the size of data remaining on the first page */
1184 page_remain = min_t(size_t,
1185 nor->page_size - page_offset, len - i);
1188 ret = nor->write(nor, to + i, page_remain, buf + i);
1193 ret = spi_nor_wait_till_ready(nor);
1198 if (written != page_remain) {
1200 "While writing %zu bytes written %zd bytes\n",
1201 page_remain, written);
1208 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1212 static int macronix_quad_enable(struct spi_nor *nor)
1221 write_sr(nor, val | SR_QUAD_EN_MX);
1223 if (spi_nor_wait_till_ready(nor))
1227 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1228 dev_err(nor->dev, "Macronix Quad bit not set\n");
1236 * Write status Register and configuration register with 2 bytes
1237 * The first byte will be written to the status register, while the
1238 * second byte will be written to the configuration register.
1239 * Return negative if error occured.
1241 static int write_sr_cr(struct spi_nor *nor, u16 val)
1243 nor->cmd_buf[0] = val & 0xff;
1244 nor->cmd_buf[1] = (val >> 8);
1246 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
1249 static int spansion_quad_enable(struct spi_nor *nor)
1252 int quad_en = CR_QUAD_EN_SPAN << 8;
1256 ret = write_sr_cr(nor, quad_en);
1259 "error while writing configuration register\n");
1263 ret = spi_nor_wait_till_ready(nor);
1266 "timeout while writing configuration register\n");
1270 /* read back and check it */
1272 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1273 dev_err(nor->dev, "Spansion Quad bit not set\n");
1280 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
1284 switch (JEDEC_MFR(info)) {
1285 case SNOR_MFR_MACRONIX:
1286 status = macronix_quad_enable(nor);
1288 dev_err(nor->dev, "Macronix quad-read not enabled\n");
1292 case SNOR_MFR_MICRON:
1295 status = spansion_quad_enable(nor);
1297 dev_err(nor->dev, "Spansion quad-read not enabled\n");
1304 static int spi_nor_check(struct spi_nor *nor)
1306 if (!nor->dev || !nor->read || !nor->write ||
1307 !nor->read_reg || !nor->write_reg) {
1308 pr_err("spi-nor: please fill all the necessary fields!\n");
1315 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
1317 const struct flash_info *info = NULL;
1318 struct device *dev = nor->dev;
1319 struct mtd_info *mtd = &nor->mtd;
1320 struct device_node *np = spi_nor_get_flash_node(nor);
1324 ret = spi_nor_check(nor);
1329 info = spi_nor_match_id(name);
1330 /* Try to auto-detect if chip name wasn't specified or not found */
1332 info = spi_nor_read_id(nor);
1333 if (IS_ERR_OR_NULL(info))
1337 * If caller has specified name of flash model that can normally be
1338 * detected using JEDEC, let's verify it.
1340 if (name && info->id_len) {
1341 const struct flash_info *jinfo;
1343 jinfo = spi_nor_read_id(nor);
1344 if (IS_ERR(jinfo)) {
1345 return PTR_ERR(jinfo);
1346 } else if (jinfo != info) {
1348 * JEDEC knows better, so overwrite platform ID. We
1349 * can't trust partitions any longer, but we'll let
1350 * mtd apply them anyway, since some partitions may be
1351 * marked read-only, and we don't want to lose that
1352 * information, even if it's not 100% accurate.
1354 dev_warn(dev, "found %s, expected %s\n",
1355 jinfo->name, info->name);
1360 mutex_init(&nor->lock);
1363 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
1364 * with the software protection bits set
1367 if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
1368 JEDEC_MFR(info) == SNOR_MFR_INTEL ||
1369 JEDEC_MFR(info) == SNOR_MFR_SST ||
1370 info->flags & SPI_NOR_HAS_LOCK) {
1373 spi_nor_wait_till_ready(nor);
1377 mtd->name = dev_name(dev);
1379 mtd->type = MTD_NORFLASH;
1381 mtd->flags = MTD_CAP_NORFLASH;
1382 mtd->size = info->sector_size * info->n_sectors;
1383 mtd->_erase = spi_nor_erase;
1384 mtd->_read = spi_nor_read;
1386 /* NOR protection support for STmicro/Micron chips and similar */
1387 if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
1388 info->flags & SPI_NOR_HAS_LOCK) {
1389 nor->flash_lock = stm_lock;
1390 nor->flash_unlock = stm_unlock;
1391 nor->flash_is_locked = stm_is_locked;
1394 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
1395 mtd->_lock = spi_nor_lock;
1396 mtd->_unlock = spi_nor_unlock;
1397 mtd->_is_locked = spi_nor_is_locked;
1400 /* sst nor chips use AAI word program */
1401 if (info->flags & SST_WRITE)
1402 mtd->_write = sst_write;
1404 mtd->_write = spi_nor_write;
1406 if (info->flags & USE_FSR)
1407 nor->flags |= SNOR_F_USE_FSR;
1408 if (info->flags & SPI_NOR_HAS_TB)
1409 nor->flags |= SNOR_F_HAS_SR_TB;
1411 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1412 /* prefer "small sector" erase if possible */
1413 if (info->flags & SECT_4K) {
1414 nor->erase_opcode = SPINOR_OP_BE_4K;
1415 mtd->erasesize = 4096;
1416 } else if (info->flags & SECT_4K_PMC) {
1417 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1418 mtd->erasesize = 4096;
1422 nor->erase_opcode = SPINOR_OP_SE;
1423 mtd->erasesize = info->sector_size;
1426 if (info->flags & SPI_NOR_NO_ERASE)
1427 mtd->flags |= MTD_NO_ERASE;
1429 mtd->dev.parent = dev;
1430 nor->page_size = info->page_size;
1431 mtd->writebufsize = nor->page_size;
1434 /* If we were instantiated by DT, use it */
1435 if (of_property_read_bool(np, "m25p,fast-read"))
1436 nor->flash_read = SPI_NOR_FAST;
1438 nor->flash_read = SPI_NOR_NORMAL;
1440 /* If we weren't instantiated by DT, default to fast-read */
1441 nor->flash_read = SPI_NOR_FAST;
1444 /* Some devices cannot do fast-read, no matter what DT tells us */
1445 if (info->flags & SPI_NOR_NO_FR)
1446 nor->flash_read = SPI_NOR_NORMAL;
1448 /* Quad/Dual-read mode takes precedence over fast/normal */
1449 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1450 ret = set_quad_mode(nor, info);
1452 dev_err(dev, "quad mode not supported\n");
1455 nor->flash_read = SPI_NOR_QUAD;
1456 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1457 nor->flash_read = SPI_NOR_DUAL;
1460 /* Default commands */
1461 switch (nor->flash_read) {
1463 nor->read_opcode = SPINOR_OP_READ_1_1_4;
1466 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1469 nor->read_opcode = SPINOR_OP_READ_FAST;
1471 case SPI_NOR_NORMAL:
1472 nor->read_opcode = SPINOR_OP_READ;
1475 dev_err(dev, "No Read opcode defined\n");
1479 nor->program_opcode = SPINOR_OP_PP;
1481 if (info->addr_width)
1482 nor->addr_width = info->addr_width;
1483 else if (mtd->size > 0x1000000) {
1484 /* enable 4-byte addressing if the device exceeds 16MiB */
1485 nor->addr_width = 4;
1486 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
1487 /* Dedicated 4-byte command set */
1488 switch (nor->flash_read) {
1490 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1493 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1496 nor->read_opcode = SPINOR_OP_READ4_FAST;
1498 case SPI_NOR_NORMAL:
1499 nor->read_opcode = SPINOR_OP_READ4;
1502 nor->program_opcode = SPINOR_OP_PP_4B;
1503 /* No small sector erase for 4-byte command set */
1504 nor->erase_opcode = SPINOR_OP_SE_4B;
1505 mtd->erasesize = info->sector_size;
1507 set_4byte(nor, info, 1);
1509 nor->addr_width = 3;
1512 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
1513 dev_err(dev, "address width is too large: %u\n",
1518 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1520 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
1521 (long long)mtd->size >> 10);
1524 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1525 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1526 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1527 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1529 if (mtd->numeraseregions)
1530 for (i = 0; i < mtd->numeraseregions; i++)
1532 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1533 ".erasesize = 0x%.8x (%uKiB), "
1534 ".numblocks = %d }\n",
1535 i, (long long)mtd->eraseregions[i].offset,
1536 mtd->eraseregions[i].erasesize,
1537 mtd->eraseregions[i].erasesize / 1024,
1538 mtd->eraseregions[i].numblocks);
1541 EXPORT_SYMBOL_GPL(spi_nor_scan);
1543 static const struct flash_info *spi_nor_match_id(const char *name)
1545 const struct flash_info *id = spi_nor_ids;
1548 if (!strcmp(name, id->name))
1555 MODULE_LICENSE("GPL");
1556 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1557 MODULE_AUTHOR("Mike Lavender");
1558 MODULE_DESCRIPTION("framework for SPI NOR");