2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
26 /* Define max times to check status register before we give up. */
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
32 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
35 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
38 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
40 #define SPI_NOR_MAX_ID_LEN 6
41 #define SPI_NOR_MAX_ADDR_WIDTH 4
47 * This array stores the ID bytes.
48 * The first three bytes are the JEDIC ID.
49 * JEDEC ID zero means "no ID" (mostly older chips).
51 u8 id[SPI_NOR_MAX_ID_LEN];
54 /* The size listed here is what works with SPINOR_OP_SE, which isn't
55 * necessarily called a "sector" by the vendor.
64 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
65 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
66 #define SST_WRITE BIT(2) /* use SST byte programming */
67 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
68 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
69 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
70 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
71 #define USE_FSR BIT(7) /* use flag status register */
72 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
73 #define SPI_NOR_HAS_TB BIT(9) /*
74 * Flash SR has Top/Bottom (TB) protect
75 * bit. Must be used with
78 #define SPI_S3AN BIT(10) /*
79 * Xilinx Spartan 3AN In-System Flash
80 * (MFR cannot be used for probing
81 * because it has the same value as
86 #define JEDEC_MFR(info) ((info)->id[0])
88 static const struct flash_info *spi_nor_match_id(const char *name);
91 * Read the status register, returning its value in the location
92 * Return the status register value.
93 * Returns negative if error occurred.
95 static int read_sr(struct spi_nor *nor)
100 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
102 pr_err("error %d reading SR\n", (int) ret);
110 * Read the flag status register, returning its value in the location
111 * Return the status register value.
112 * Returns negative if error occurred.
114 static int read_fsr(struct spi_nor *nor)
119 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
121 pr_err("error %d reading FSR\n", ret);
129 * Read configuration register, returning its value in the
130 * location. Return the configuration register value.
131 * Returns negative if error occured.
133 static int read_cr(struct spi_nor *nor)
138 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
140 dev_err(nor->dev, "error %d reading CR\n", ret);
148 * Dummy Cycle calculation for different type of read.
149 * It can be used to support more commands with
150 * different dummy cycle requirements.
152 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
154 switch (nor->flash_read) {
166 * Write status register 1 byte
167 * Returns negative if error occurred.
169 static inline int write_sr(struct spi_nor *nor, u8 val)
171 nor->cmd_buf[0] = val;
172 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
176 * Set write enable latch with Write Enable command.
177 * Returns negative if error occurred.
179 static inline int write_enable(struct spi_nor *nor)
181 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
185 * Send write disble instruction to the chip.
187 static inline int write_disable(struct spi_nor *nor)
189 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
192 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
197 /* Enable/disable 4-byte addressing mode. */
198 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
202 bool need_wren = false;
205 switch (JEDEC_MFR(info)) {
206 case SNOR_MFR_MICRON:
207 /* Some Micron need WREN command; all will accept it */
209 case SNOR_MFR_MACRONIX:
210 case SNOR_MFR_WINBOND:
214 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
215 status = nor->write_reg(nor, cmd, NULL, 0);
222 nor->cmd_buf[0] = enable << 7;
223 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
227 static int s3an_sr_ready(struct spi_nor *nor)
232 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
234 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
238 return !!(val & XSR_RDY);
241 static inline int spi_nor_sr_ready(struct spi_nor *nor)
243 int sr = read_sr(nor);
247 return !(sr & SR_WIP);
250 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
252 int fsr = read_fsr(nor);
256 return fsr & FSR_READY;
259 static int spi_nor_ready(struct spi_nor *nor)
263 if (nor->flags & SNOR_F_READY_XSR_RDY)
264 sr = s3an_sr_ready(nor);
266 sr = spi_nor_sr_ready(nor);
269 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
276 * Service routine to read status register until ready, or timeout occurs.
277 * Returns non-zero if error.
279 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
280 unsigned long timeout_jiffies)
282 unsigned long deadline;
283 int timeout = 0, ret;
285 deadline = jiffies + timeout_jiffies;
288 if (time_after_eq(jiffies, deadline))
291 ret = spi_nor_ready(nor);
300 dev_err(nor->dev, "flash operation timed out\n");
305 static int spi_nor_wait_till_ready(struct spi_nor *nor)
307 return spi_nor_wait_till_ready_with_timeout(nor,
308 DEFAULT_READY_WAIT_JIFFIES);
312 * Erase the whole flash memory
314 * Returns 0 if successful, non-zero otherwise.
316 static int erase_chip(struct spi_nor *nor)
318 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
320 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
323 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
327 mutex_lock(&nor->lock);
330 ret = nor->prepare(nor, ops);
332 dev_err(nor->dev, "failed in the preparation.\n");
333 mutex_unlock(&nor->lock);
340 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
343 nor->unprepare(nor, ops);
344 mutex_unlock(&nor->lock);
348 * This code converts an address to the Default Address Mode, that has non
349 * power of two page sizes. We must support this mode because it is the default
350 * mode supported by Xilinx tools, it can access the whole flash area and
351 * changing over to the Power-of-two mode is irreversible and corrupts the
353 * Addr can safely be unsigned int, the biggest S3AN device is smaller than
356 static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
358 unsigned int offset = addr;
360 offset %= nor->page_size;
362 return ((addr - offset) << 1) | offset;
366 * Initiate the erasure of a single sector
368 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
370 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
373 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
374 addr = spi_nor_s3an_addr_convert(nor, addr);
377 return nor->erase(nor, addr);
380 * Default implementation, if driver doesn't have a specialized HW
383 for (i = nor->addr_width - 1; i >= 0; i--) {
384 buf[i] = addr & 0xff;
388 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
392 * Erase an address range on the nor chip. The address range may extend
393 * one or more erase sectors. Return an error is there is a problem erasing.
395 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
397 struct spi_nor *nor = mtd_to_spi_nor(mtd);
402 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
403 (long long)instr->len);
405 div_u64_rem(instr->len, mtd->erasesize, &rem);
412 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
416 /* whole-chip erase? */
417 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
418 unsigned long timeout;
422 if (erase_chip(nor)) {
428 * Scale the timeout linearly with the size of the flash, with
429 * a minimum calibrated to an old 2MB flash. We could try to
430 * pull these from CFI/SFDP, but these values should be good
433 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
434 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
435 (unsigned long)(mtd->size / SZ_2M));
436 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
440 /* REVISIT in some cases we could speed up erasing large regions
441 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
442 * to use "small sector erase", but that's not always optimal.
445 /* "sector"-at-a-time erase */
450 ret = spi_nor_erase_sector(nor, addr);
454 addr += mtd->erasesize;
455 len -= mtd->erasesize;
457 ret = spi_nor_wait_till_ready(nor);
466 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
468 instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
469 mtd_erase_callback(instr);
474 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
477 struct mtd_info *mtd = &nor->mtd;
478 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
479 int shift = ffs(mask) - 1;
487 pow = ((sr & mask) ^ mask) >> shift;
488 *len = mtd->size >> pow;
489 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
492 *ofs = mtd->size - *len;
497 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
498 * @locked is false); 0 otherwise
500 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
509 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
512 /* Requested range is a sub-range of locked range */
513 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
515 /* Requested range does not overlap with locked range */
516 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
519 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
522 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
525 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
528 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
532 * Lock a region of the flash. Compatible with ST Micro and similar flash.
533 * Supports the block protection bits BP{0,1,2} in the status register
534 * (SR). Does not support these features found in newer SR bitfields:
535 * - SEC: sector/block protect - only handle SEC=0 (block protect)
536 * - CMP: complement protect - only support CMP=0 (range is not complemented)
538 * Support for the following is provided conditionally for some flash:
539 * - TB: top/bottom protect
541 * Sample table portion for 8MB flash (Winbond w25q64fw):
543 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
544 * --------------------------------------------------------------------------
545 * X | X | 0 | 0 | 0 | NONE | NONE
546 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
547 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
548 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
549 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
550 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
551 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
552 * X | X | 1 | 1 | 1 | 8 MB | ALL
553 * ------|-------|-------|-------|-------|---------------|-------------------
554 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
555 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
556 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
557 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
558 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
559 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
561 * Returns negative on errors, 0 on success.
563 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
565 struct mtd_info *mtd = &nor->mtd;
566 int status_old, status_new;
567 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
568 u8 shift = ffs(mask) - 1, pow, val;
570 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
574 status_old = read_sr(nor);
578 /* If nothing in our range is unlocked, we don't need to do anything */
579 if (stm_is_locked_sr(nor, ofs, len, status_old))
582 /* If anything below us is unlocked, we can't use 'bottom' protection */
583 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
584 can_be_bottom = false;
586 /* If anything above us is unlocked, we can't use 'top' protection */
587 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
591 if (!can_be_bottom && !can_be_top)
594 /* Prefer top, if both are valid */
595 use_top = can_be_top;
597 /* lock_len: length of region that should end up locked */
599 lock_len = mtd->size - ofs;
601 lock_len = ofs + len;
604 * Need smallest pow such that:
606 * 1 / (2^pow) <= (len / size)
608 * so (assuming power-of-2 size) we do:
610 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
612 pow = ilog2(mtd->size) - ilog2(lock_len);
613 val = mask - (pow << shift);
616 /* Don't "lock" with no region! */
620 status_new = (status_old & ~mask & ~SR_TB) | val;
622 /* Disallow further writes if WP pin is asserted */
623 status_new |= SR_SRWD;
628 /* Don't bother if they're the same */
629 if (status_new == status_old)
632 /* Only modify protection if it will not unlock other areas */
633 if ((status_new & mask) < (status_old & mask))
637 ret = write_sr(nor, status_new);
640 return spi_nor_wait_till_ready(nor);
644 * Unlock a region of the flash. See stm_lock() for more info
646 * Returns negative on errors, 0 on success.
648 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
650 struct mtd_info *mtd = &nor->mtd;
651 int status_old, status_new;
652 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
653 u8 shift = ffs(mask) - 1, pow, val;
655 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
659 status_old = read_sr(nor);
663 /* If nothing in our range is locked, we don't need to do anything */
664 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
667 /* If anything below us is locked, we can't use 'top' protection */
668 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
671 /* If anything above us is locked, we can't use 'bottom' protection */
672 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
674 can_be_bottom = false;
676 if (!can_be_bottom && !can_be_top)
679 /* Prefer top, if both are valid */
680 use_top = can_be_top;
682 /* lock_len: length of region that should remain locked */
684 lock_len = mtd->size - (ofs + len);
689 * Need largest pow such that:
691 * 1 / (2^pow) >= (len / size)
693 * so (assuming power-of-2 size) we do:
695 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
697 pow = ilog2(mtd->size) - order_base_2(lock_len);
699 val = 0; /* fully unlocked */
701 val = mask - (pow << shift);
702 /* Some power-of-two sizes are not supported */
707 status_new = (status_old & ~mask & ~SR_TB) | val;
709 /* Don't protect status register if we're fully unlocked */
711 status_new &= ~SR_SRWD;
716 /* Don't bother if they're the same */
717 if (status_new == status_old)
720 /* Only modify protection if it will not lock other areas */
721 if ((status_new & mask) > (status_old & mask))
725 ret = write_sr(nor, status_new);
728 return spi_nor_wait_till_ready(nor);
732 * Check if a region of the flash is (completely) locked. See stm_lock() for
735 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
736 * negative on errors.
738 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
742 status = read_sr(nor);
746 return stm_is_locked_sr(nor, ofs, len, status);
749 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
751 struct spi_nor *nor = mtd_to_spi_nor(mtd);
754 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
758 ret = nor->flash_lock(nor, ofs, len);
760 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
764 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
766 struct spi_nor *nor = mtd_to_spi_nor(mtd);
769 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
773 ret = nor->flash_unlock(nor, ofs, len);
775 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
779 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
781 struct spi_nor *nor = mtd_to_spi_nor(mtd);
784 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
788 ret = nor->flash_is_locked(nor, ofs, len);
790 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
794 /* Used when the "_ext_id" is two bytes at most */
795 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
797 ((_jedec_id) >> 16) & 0xff, \
798 ((_jedec_id) >> 8) & 0xff, \
799 (_jedec_id) & 0xff, \
800 ((_ext_id) >> 8) & 0xff, \
803 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
804 .sector_size = (_sector_size), \
805 .n_sectors = (_n_sectors), \
809 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
811 ((_jedec_id) >> 16) & 0xff, \
812 ((_jedec_id) >> 8) & 0xff, \
813 (_jedec_id) & 0xff, \
814 ((_ext_id) >> 16) & 0xff, \
815 ((_ext_id) >> 8) & 0xff, \
819 .sector_size = (_sector_size), \
820 .n_sectors = (_n_sectors), \
824 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
825 .sector_size = (_sector_size), \
826 .n_sectors = (_n_sectors), \
827 .page_size = (_page_size), \
828 .addr_width = (_addr_width), \
831 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
833 ((_jedec_id) >> 16) & 0xff, \
834 ((_jedec_id) >> 8) & 0xff, \
838 .sector_size = (8*_page_size), \
839 .n_sectors = (_n_sectors), \
840 .page_size = _page_size, \
842 .flags = SPI_NOR_NO_FR | SPI_S3AN,
844 /* NOTE: double check command sets and memory organization when you add
845 * more nor chips. This current list focusses on newer chips, which
846 * have been converging on command sets which including JEDEC ID.
848 * All newly added entries should describe *hardware* and should use SECT_4K
849 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
850 * scenarios excluding small sectors there is config option that can be
851 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
852 * For historical (and compatibility) reasons (before we got above config) some
853 * old entries may be missing 4K flag.
855 static const struct flash_info spi_nor_ids[] = {
856 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
857 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
858 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
860 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
861 { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
862 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
863 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
865 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
866 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
867 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
868 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
870 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
873 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
874 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
875 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
876 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
877 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
878 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
879 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
880 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
883 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
886 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
887 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
888 { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
891 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
895 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
896 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
897 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
900 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
901 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
902 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
905 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
906 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
907 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
910 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
911 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
912 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
915 /* Intel/Numonyx -- xxxs33b */
916 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
917 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
918 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
921 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
924 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
925 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
926 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
927 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
928 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
929 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
930 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
931 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
932 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
933 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
934 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
935 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
936 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
937 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
938 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
939 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
942 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
943 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
944 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
945 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
946 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
947 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
948 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
949 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
950 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
951 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
952 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
953 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
956 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
957 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
958 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
960 /* Spansion -- single (large) sector size only, at least
961 * for the chips listed here (without boot sectors).
963 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
964 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
965 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
966 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
967 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
968 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
969 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
970 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
971 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
972 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
973 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
974 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
975 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
976 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
977 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
978 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
979 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
980 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
981 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
982 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
983 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
984 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
985 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
986 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
987 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
989 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
990 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
991 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
992 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
993 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
994 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
995 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
996 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
997 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
998 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
999 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
1000 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1001 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1003 /* ST Microelectronics -- newer production may have feature updates */
1004 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
1005 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
1006 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
1007 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
1008 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
1009 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
1010 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
1011 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
1012 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1014 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
1015 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
1016 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
1017 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
1018 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
1019 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
1020 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
1021 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
1022 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
1024 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
1025 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
1026 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
1028 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
1029 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
1030 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1032 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
1033 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
1034 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
1035 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
1036 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1037 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
1039 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1040 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
1041 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1042 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1043 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1044 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1045 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1046 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1047 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1049 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
1050 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1051 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1053 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1054 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1056 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
1057 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1058 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1061 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
1062 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1063 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1065 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1066 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1067 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1068 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
1070 /* Catalyst / On Semiconductor -- non-JEDEC */
1071 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1072 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1073 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1074 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1075 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1077 /* Xilinx S3AN Internal Flash */
1078 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
1079 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
1080 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
1081 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
1082 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
1086 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1089 u8 id[SPI_NOR_MAX_ID_LEN];
1090 const struct flash_info *info;
1092 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1094 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1095 return ERR_PTR(tmp);
1098 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1099 info = &spi_nor_ids[tmp];
1101 if (!memcmp(info->id, id, info->id_len))
1102 return &spi_nor_ids[tmp];
1105 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1106 id[0], id[1], id[2]);
1107 return ERR_PTR(-ENODEV);
1110 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1111 size_t *retlen, u_char *buf)
1113 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1116 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1118 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
1125 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
1126 addr = spi_nor_s3an_addr_convert(nor, addr);
1128 ret = nor->read(nor, addr, len, buf);
1130 /* We shouldn't see 0-length reads */
1146 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
1150 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1151 size_t *retlen, const u_char *buf)
1153 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1157 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1159 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1165 nor->sst_write_second = false;
1168 /* Start write from odd address. */
1170 nor->program_opcode = SPINOR_OP_BP;
1172 /* write one byte. */
1173 ret = nor->write(nor, to, 1, buf);
1176 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1178 ret = spi_nor_wait_till_ready(nor);
1184 /* Write out most of the data here. */
1185 for (; actual < len - 1; actual += 2) {
1186 nor->program_opcode = SPINOR_OP_AAI_WP;
1188 /* write two bytes. */
1189 ret = nor->write(nor, to, 2, buf + actual);
1192 WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
1194 ret = spi_nor_wait_till_ready(nor);
1198 nor->sst_write_second = true;
1200 nor->sst_write_second = false;
1203 ret = spi_nor_wait_till_ready(nor);
1207 /* Write out trailing byte if it exists. */
1208 if (actual != len) {
1211 nor->program_opcode = SPINOR_OP_BP;
1212 ret = nor->write(nor, to, 1, buf + actual);
1215 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1217 ret = spi_nor_wait_till_ready(nor);
1225 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1230 * Write an address range to the nor chip. Data must be written in
1231 * FLASH_PAGESIZE chunks. The address range may be any size provided
1232 * it is within the physical boundaries.
1234 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1235 size_t *retlen, const u_char *buf)
1237 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1238 size_t page_offset, page_remain, i;
1241 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1243 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1247 for (i = 0; i < len; ) {
1249 loff_t addr = to + i;
1252 * If page_size is a power of two, the offset can be quickly
1253 * calculated with an AND operation. On the other cases we
1254 * need to do a modulus operation (more expensive).
1255 * Power of two numbers have only one bit set and we can use
1256 * the instruction hweight32 to detect if we need to do a
1257 * modulus (do_div()) or not.
1259 if (hweight32(nor->page_size) == 1) {
1260 page_offset = addr & (nor->page_size - 1);
1262 uint64_t aux = addr;
1264 page_offset = do_div(aux, nor->page_size);
1266 /* the size of data remaining on the first page */
1267 page_remain = min_t(size_t,
1268 nor->page_size - page_offset, len - i);
1270 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
1271 addr = spi_nor_s3an_addr_convert(nor, addr);
1274 ret = nor->write(nor, addr, page_remain, buf + i);
1279 ret = spi_nor_wait_till_ready(nor);
1284 if (written != page_remain) {
1286 "While writing %zu bytes written %zd bytes\n",
1287 page_remain, written);
1294 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1298 static int macronix_quad_enable(struct spi_nor *nor)
1305 if (val & SR_QUAD_EN_MX)
1310 write_sr(nor, val | SR_QUAD_EN_MX);
1312 if (spi_nor_wait_till_ready(nor))
1316 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1317 dev_err(nor->dev, "Macronix Quad bit not set\n");
1325 * Write status Register and configuration register with 2 bytes
1326 * The first byte will be written to the status register, while the
1327 * second byte will be written to the configuration register.
1328 * Return negative if error occured.
1330 static int write_sr_cr(struct spi_nor *nor, u16 val)
1332 nor->cmd_buf[0] = val & 0xff;
1333 nor->cmd_buf[1] = (val >> 8);
1335 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
1338 static int spansion_quad_enable(struct spi_nor *nor)
1341 int quad_en = CR_QUAD_EN_SPAN << 8;
1345 ret = write_sr_cr(nor, quad_en);
1348 "error while writing configuration register\n");
1352 ret = spi_nor_wait_till_ready(nor);
1355 "timeout while writing configuration register\n");
1359 /* read back and check it */
1361 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1362 dev_err(nor->dev, "Spansion Quad bit not set\n");
1369 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
1373 switch (JEDEC_MFR(info)) {
1374 case SNOR_MFR_MACRONIX:
1375 status = macronix_quad_enable(nor);
1377 dev_err(nor->dev, "Macronix quad-read not enabled\n");
1381 case SNOR_MFR_MICRON:
1384 status = spansion_quad_enable(nor);
1386 dev_err(nor->dev, "Spansion quad-read not enabled\n");
1393 static int spi_nor_check(struct spi_nor *nor)
1395 if (!nor->dev || !nor->read || !nor->write ||
1396 !nor->read_reg || !nor->write_reg) {
1397 pr_err("spi-nor: please fill all the necessary fields!\n");
1404 static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
1409 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
1411 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
1415 nor->erase_opcode = SPINOR_OP_XSE;
1416 nor->program_opcode = SPINOR_OP_XPP;
1417 nor->read_opcode = SPINOR_OP_READ;
1418 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
1421 * This flashes have a page size of 264 or 528 bytes (known as
1422 * Default addressing mode). It can be changed to a more standard
1423 * Power of two mode where the page size is 256/512. This comes
1424 * with a price: there is 3% less of space, the data is corrupted
1425 * and the page size cannot be changed back to default addressing
1428 * The current addressing mode can be read from the XRDSR register
1429 * and should not be changed, because is a destructive operation.
1431 if (val & XSR_PAGESIZE) {
1432 /* Flash in Power of 2 mode */
1433 nor->page_size = (nor->page_size == 264) ? 256 : 512;
1434 nor->mtd.writebufsize = nor->page_size;
1435 nor->mtd.size = 8 * nor->page_size * info->n_sectors;
1436 nor->mtd.erasesize = 8 * nor->page_size;
1438 /* Flash in Default addressing mode */
1439 nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
1445 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
1447 const struct flash_info *info = NULL;
1448 struct device *dev = nor->dev;
1449 struct mtd_info *mtd = &nor->mtd;
1450 struct device_node *np = spi_nor_get_flash_node(nor);
1454 ret = spi_nor_check(nor);
1459 info = spi_nor_match_id(name);
1460 /* Try to auto-detect if chip name wasn't specified or not found */
1462 info = spi_nor_read_id(nor);
1463 if (IS_ERR_OR_NULL(info))
1467 * If caller has specified name of flash model that can normally be
1468 * detected using JEDEC, let's verify it.
1470 if (name && info->id_len) {
1471 const struct flash_info *jinfo;
1473 jinfo = spi_nor_read_id(nor);
1474 if (IS_ERR(jinfo)) {
1475 return PTR_ERR(jinfo);
1476 } else if (jinfo != info) {
1478 * JEDEC knows better, so overwrite platform ID. We
1479 * can't trust partitions any longer, but we'll let
1480 * mtd apply them anyway, since some partitions may be
1481 * marked read-only, and we don't want to lose that
1482 * information, even if it's not 100% accurate.
1484 dev_warn(dev, "found %s, expected %s\n",
1485 jinfo->name, info->name);
1490 mutex_init(&nor->lock);
1493 * Make sure the XSR_RDY flag is set before calling
1494 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
1495 * with Atmel spi-nor
1497 if (info->flags & SPI_S3AN)
1498 nor->flags |= SNOR_F_READY_XSR_RDY;
1501 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
1502 * with the software protection bits set
1505 if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
1506 JEDEC_MFR(info) == SNOR_MFR_INTEL ||
1507 JEDEC_MFR(info) == SNOR_MFR_SST ||
1508 info->flags & SPI_NOR_HAS_LOCK) {
1511 spi_nor_wait_till_ready(nor);
1515 mtd->name = dev_name(dev);
1517 mtd->type = MTD_NORFLASH;
1519 mtd->flags = MTD_CAP_NORFLASH;
1520 mtd->size = info->sector_size * info->n_sectors;
1521 mtd->_erase = spi_nor_erase;
1522 mtd->_read = spi_nor_read;
1524 /* NOR protection support for STmicro/Micron chips and similar */
1525 if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
1526 info->flags & SPI_NOR_HAS_LOCK) {
1527 nor->flash_lock = stm_lock;
1528 nor->flash_unlock = stm_unlock;
1529 nor->flash_is_locked = stm_is_locked;
1532 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
1533 mtd->_lock = spi_nor_lock;
1534 mtd->_unlock = spi_nor_unlock;
1535 mtd->_is_locked = spi_nor_is_locked;
1538 /* sst nor chips use AAI word program */
1539 if (info->flags & SST_WRITE)
1540 mtd->_write = sst_write;
1542 mtd->_write = spi_nor_write;
1544 if (info->flags & USE_FSR)
1545 nor->flags |= SNOR_F_USE_FSR;
1546 if (info->flags & SPI_NOR_HAS_TB)
1547 nor->flags |= SNOR_F_HAS_SR_TB;
1549 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1550 /* prefer "small sector" erase if possible */
1551 if (info->flags & SECT_4K) {
1552 nor->erase_opcode = SPINOR_OP_BE_4K;
1553 mtd->erasesize = 4096;
1554 } else if (info->flags & SECT_4K_PMC) {
1555 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1556 mtd->erasesize = 4096;
1560 nor->erase_opcode = SPINOR_OP_SE;
1561 mtd->erasesize = info->sector_size;
1564 if (info->flags & SPI_NOR_NO_ERASE)
1565 mtd->flags |= MTD_NO_ERASE;
1567 mtd->dev.parent = dev;
1568 nor->page_size = info->page_size;
1569 mtd->writebufsize = nor->page_size;
1572 /* If we were instantiated by DT, use it */
1573 if (of_property_read_bool(np, "m25p,fast-read"))
1574 nor->flash_read = SPI_NOR_FAST;
1576 nor->flash_read = SPI_NOR_NORMAL;
1578 /* If we weren't instantiated by DT, default to fast-read */
1579 nor->flash_read = SPI_NOR_FAST;
1582 /* Some devices cannot do fast-read, no matter what DT tells us */
1583 if (info->flags & SPI_NOR_NO_FR)
1584 nor->flash_read = SPI_NOR_NORMAL;
1586 /* Quad/Dual-read mode takes precedence over fast/normal */
1587 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1588 ret = set_quad_mode(nor, info);
1590 dev_err(dev, "quad mode not supported\n");
1593 nor->flash_read = SPI_NOR_QUAD;
1594 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1595 nor->flash_read = SPI_NOR_DUAL;
1598 /* Default commands */
1599 switch (nor->flash_read) {
1601 nor->read_opcode = SPINOR_OP_READ_1_1_4;
1604 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1607 nor->read_opcode = SPINOR_OP_READ_FAST;
1609 case SPI_NOR_NORMAL:
1610 nor->read_opcode = SPINOR_OP_READ;
1613 dev_err(dev, "No Read opcode defined\n");
1617 nor->program_opcode = SPINOR_OP_PP;
1619 if (info->addr_width)
1620 nor->addr_width = info->addr_width;
1621 else if (mtd->size > 0x1000000) {
1622 /* enable 4-byte addressing if the device exceeds 16MiB */
1623 nor->addr_width = 4;
1624 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
1625 /* Dedicated 4-byte command set */
1626 switch (nor->flash_read) {
1628 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1631 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1634 nor->read_opcode = SPINOR_OP_READ4_FAST;
1636 case SPI_NOR_NORMAL:
1637 nor->read_opcode = SPINOR_OP_READ4;
1640 nor->program_opcode = SPINOR_OP_PP_4B;
1641 /* No small sector erase for 4-byte command set */
1642 nor->erase_opcode = SPINOR_OP_SE_4B;
1643 mtd->erasesize = info->sector_size;
1645 set_4byte(nor, info, 1);
1647 nor->addr_width = 3;
1650 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
1651 dev_err(dev, "address width is too large: %u\n",
1656 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1658 if (info->flags & SPI_S3AN) {
1659 ret = s3an_nor_scan(info, nor);
1664 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
1665 (long long)mtd->size >> 10);
1668 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1669 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1670 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1671 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1673 if (mtd->numeraseregions)
1674 for (i = 0; i < mtd->numeraseregions; i++)
1676 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1677 ".erasesize = 0x%.8x (%uKiB), "
1678 ".numblocks = %d }\n",
1679 i, (long long)mtd->eraseregions[i].offset,
1680 mtd->eraseregions[i].erasesize,
1681 mtd->eraseregions[i].erasesize / 1024,
1682 mtd->eraseregions[i].numblocks);
1685 EXPORT_SYMBOL_GPL(spi_nor_scan);
1687 static const struct flash_info *spi_nor_match_id(const char *name)
1689 const struct flash_info *id = spi_nor_ids;
1692 if (!strcmp(name, id->name))
1699 MODULE_LICENSE("GPL");
1700 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1701 MODULE_AUTHOR("Mike Lavender");
1702 MODULE_DESCRIPTION("framework for SPI NOR");