2 * PCI bus driver for Bosch C_CAN/D_CAN controller
4 * Copyright (C) 2012 Federico Vaga <federico.vaga@gmail.com>
6 * Borrowed from c_can_platform.c
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/pci.h>
18 #include <linux/can/dev.h>
22 #define PCI_DEVICE_ID_PCH_CAN 0x8818
23 #define PCH_PCI_SOFT_RESET 0x01fc
25 enum c_can_pci_reg_align {
31 struct c_can_pci_data {
32 /* Specify if is C_CAN or D_CAN */
33 enum c_can_dev_id type;
34 /* Set the register alignment in the memory */
35 enum c_can_pci_reg_align reg_align;
36 /* Set the frequency */
40 /* Callback for reset */
41 void (*init)(const struct c_can_priv *priv, bool enable);
45 * 16-bit c_can registers can be arranged differently in the memory
46 * architecture of different implementations. For example: 16-bit
47 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
48 * Handle the same by providing a common read/write interface.
50 static u16 c_can_pci_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
53 return readw(priv->base + priv->regs[index]);
56 static void c_can_pci_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
57 enum reg index, u16 val)
59 writew(val, priv->base + priv->regs[index]);
62 static u16 c_can_pci_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
65 return readw(priv->base + 2 * priv->regs[index]);
68 static void c_can_pci_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
69 enum reg index, u16 val)
71 writew(val, priv->base + 2 * priv->regs[index]);
74 static u16 c_can_pci_read_reg_32bit(const struct c_can_priv *priv,
77 return (u16)ioread32(priv->base + 2 * priv->regs[index]);
80 static void c_can_pci_write_reg_32bit(const struct c_can_priv *priv,
81 enum reg index, u16 val)
83 iowrite32((u32)val, priv->base + 2 * priv->regs[index]);
86 static u32 c_can_pci_read_reg32(const struct c_can_priv *priv, enum reg index)
90 val = priv->read_reg(priv, index);
91 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
96 static void c_can_pci_write_reg32(const struct c_can_priv *priv, enum reg index,
99 priv->write_reg(priv, index + 1, val >> 16);
100 priv->write_reg(priv, index, val);
103 static void c_can_pci_reset_pch(const struct c_can_priv *priv, bool enable)
106 u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET;
108 /* write to sw reset register */
114 static int c_can_pci_probe(struct pci_dev *pdev,
115 const struct pci_device_id *ent)
117 struct c_can_pci_data *c_can_pci_data = (void *)ent->driver_data;
118 struct c_can_priv *priv;
119 struct net_device *dev;
123 ret = pci_enable_device(pdev);
125 dev_err(&pdev->dev, "pci_enable_device FAILED\n");
129 ret = pci_request_regions(pdev, KBUILD_MODNAME);
131 dev_err(&pdev->dev, "pci_request_regions FAILED\n");
132 goto out_disable_device;
135 ret = pci_enable_msi(pdev);
137 dev_info(&pdev->dev, "MSI enabled\n");
138 pci_set_master(pdev);
141 addr = pci_iomap(pdev, c_can_pci_data->bar,
142 pci_resource_len(pdev, c_can_pci_data->bar));
145 "device has no PCI memory resources, "
146 "failing adapter\n");
148 goto out_release_regions;
151 /* allocate the c_can device */
152 dev = alloc_c_can_dev();
158 priv = netdev_priv(dev);
159 pci_set_drvdata(pdev, dev);
160 SET_NETDEV_DEV(dev, &pdev->dev);
162 dev->irq = pdev->irq;
164 priv->device = &pdev->dev;
166 if (!c_can_pci_data->freq) {
167 dev_err(&pdev->dev, "no clock frequency defined\n");
171 priv->can.clock.freq = c_can_pci_data->freq;
174 /* Configure CAN type */
175 switch (c_can_pci_data->type) {
177 priv->regs = reg_map_c_can;
180 priv->regs = reg_map_d_can;
181 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
188 priv->type = c_can_pci_data->type;
190 /* Configure access to registers */
191 switch (c_can_pci_data->reg_align) {
192 case C_CAN_REG_ALIGN_32:
193 priv->read_reg = c_can_pci_read_reg_aligned_to_32bit;
194 priv->write_reg = c_can_pci_write_reg_aligned_to_32bit;
196 case C_CAN_REG_ALIGN_16:
197 priv->read_reg = c_can_pci_read_reg_aligned_to_16bit;
198 priv->write_reg = c_can_pci_write_reg_aligned_to_16bit;
201 priv->read_reg = c_can_pci_read_reg_32bit;
202 priv->write_reg = c_can_pci_write_reg_32bit;
208 priv->read_reg32 = c_can_pci_read_reg32;
209 priv->write_reg32 = c_can_pci_write_reg32;
211 priv->raminit = c_can_pci_data->init;
213 ret = register_c_can_dev(dev);
215 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
216 KBUILD_MODNAME, ret);
220 dev_dbg(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
221 KBUILD_MODNAME, priv->regs, dev->irq);
228 pci_iounmap(pdev, addr);
230 pci_disable_msi(pdev);
231 pci_clear_master(pdev);
232 pci_release_regions(pdev);
234 pci_disable_device(pdev);
239 static void c_can_pci_remove(struct pci_dev *pdev)
241 struct net_device *dev = pci_get_drvdata(pdev);
242 struct c_can_priv *priv = netdev_priv(dev);
244 unregister_c_can_dev(dev);
248 pci_iounmap(pdev, priv->base);
249 pci_disable_msi(pdev);
250 pci_clear_master(pdev);
251 pci_release_regions(pdev);
252 pci_disable_device(pdev);
255 static struct c_can_pci_data c_can_sta2x11= {
257 .reg_align = C_CAN_REG_ALIGN_32,
258 .freq = 52000000, /* 52 Mhz */
262 static struct c_can_pci_data c_can_pch = {
264 .reg_align = C_CAN_REG_32,
265 .freq = 50000000, /* 50 MHz */
266 .init = c_can_pci_reset_pch,
270 #define C_CAN_ID(_vend, _dev, _driverdata) { \
271 PCI_DEVICE(_vend, _dev), \
272 .driver_data = (unsigned long)&_driverdata, \
275 static const struct pci_device_id c_can_pci_tbl[] = {
276 C_CAN_ID(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_CAN,
278 C_CAN_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_CAN,
282 static struct pci_driver c_can_pci_driver = {
283 .name = KBUILD_MODNAME,
284 .id_table = c_can_pci_tbl,
285 .probe = c_can_pci_probe,
286 .remove = c_can_pci_remove,
289 module_pci_driver(c_can_pci_driver);
291 MODULE_AUTHOR("Federico Vaga <federico.vaga@gmail.com>");
292 MODULE_LICENSE("GPL v2");
293 MODULE_DESCRIPTION("PCI CAN bus driver for Bosch C_CAN/D_CAN controller");
294 MODULE_DEVICE_TABLE(pci, c_can_pci_tbl);