drivers/net/can/flexcan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // flexcan.c - FLEXCAN CAN controller driver
   4 //
   5 // Copyright (c) 2005-2006 Varma Electronics Oy
   6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
   7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8 // Copyright (c) 2014 David Jander, Protonic Holland
   9 //
  10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12 #include <linux/netdevice.h>
  13 #include <linux/can.h>
  14 #include <linux/can/dev.h>
  15 #include <linux/can/error.h>
  16 #include <linux/can/led.h>
  17 #include <linux/can/rx-offload.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regulator/consumer.h>
  27
  28 #define DRV_NAME                        "flexcan"
  29
  30 /* 8 for RX fifo and 2 error handling */
  31 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  32
  33 /* FLEXCAN module configuration register (CANMCR) bits */
  34 #define FLEXCAN_MCR_MDIS                BIT(31)
  35 #define FLEXCAN_MCR_FRZ                 BIT(30)
  36 #define FLEXCAN_MCR_FEN                 BIT(29)
  37 #define FLEXCAN_MCR_HALT                BIT(28)
  38 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  39 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  40 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  41 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  42 #define FLEXCAN_MCR_SUPV                BIT(23)
  43 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  44 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  45 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  46 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  47 #define FLEXCAN_MCR_DOZE                BIT(18)
  48 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  49 #define FLEXCAN_MCR_IRMQ                BIT(16)
  50 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  51 #define FLEXCAN_MCR_AEN                 BIT(12)
  52 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  53 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  54 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  55 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  56 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  57 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  58
  59 /* FLEXCAN control register (CANCTRL) bits */
  60 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  61 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  62 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  63 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  64 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  65 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  66 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  67 #define FLEXCAN_CTRL_LPB                BIT(12)
  68 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  69 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  70 #define FLEXCAN_CTRL_SMP                BIT(7)
  71 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  72 #define FLEXCAN_CTRL_TSYN               BIT(5)
  73 #define FLEXCAN_CTRL_LBUF               BIT(4)
  74 #define FLEXCAN_CTRL_LOM                BIT(3)
  75 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  76 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  77 #define FLEXCAN_CTRL_ERR_STATE \
  78         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  79          FLEXCAN_CTRL_BOFF_MSK)
  80 #define FLEXCAN_CTRL_ERR_ALL \
  81         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  82
  83 /* FLEXCAN control register 2 (CTRL2) bits */
  84 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  85 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  86 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  87 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  88 #define FLEXCAN_CTRL2_MRP               BIT(18)
  89 #define FLEXCAN_CTRL2_RRS               BIT(17)
  90 #define FLEXCAN_CTRL2_EACEN             BIT(16)
  91
  92 /* FLEXCAN memory error control register (MECR) bits */
  93 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
  94 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
  95 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
  96 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
  97 #define FLEXCAN_MECR_HAERRIE            BIT(15)
  98 #define FLEXCAN_MECR_FAERRIE            BIT(14)
  99 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 100 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 101 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 102 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 103
 104 /* FLEXCAN error and status register (ESR) bits */
 105 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 106 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 107 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 108 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 109 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 110 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 111 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 112 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 113 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 114 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 115 #define FLEXCAN_ESR_IDLE                BIT(7)
 116 #define FLEXCAN_ESR_TXRX                BIT(6)
 117 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 118 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 119 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 120 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 121 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 122 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 123 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 124 #define FLEXCAN_ESR_ERR_BUS \
 125         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 126          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 127          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 128 #define FLEXCAN_ESR_ERR_STATE \
 129         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 130 #define FLEXCAN_ESR_ERR_ALL \
 131         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 132 #define FLEXCAN_ESR_ALL_INT \
 133         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 134          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 135
 136 /* FLEXCAN interrupt flag register (IFLAG) bits */
 137 /* Errata ERR005829 step7: Reserve first valid MB */
 138 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO         8
 139 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP    0
 140 #define FLEXCAN_TX_MB                           63
 141 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST       (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
 142 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST        (FLEXCAN_TX_MB - 1)
 143 #define FLEXCAN_IFLAG_MB(x)             BIT(x & 0x1f)
 144 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 145 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 146 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 147
 148 /* FLEXCAN message buffers */
 149 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 150 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 151 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 152 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 153 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 154 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 155 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 156
 157 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 158 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 159 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 160 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 161
 162 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 163 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 164 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 165 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 166 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 167
 168 #define FLEXCAN_TIMEOUT_US              (50)
 169
 170 /* FLEXCAN hardware feature flags
 171  *
 172  * Below is some version info we got:
 173  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 174  *                                Filter? connected?  Passive detection  ception in MB
 175  *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
 176  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
 177  *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
 178  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 179  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
 180  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
 181  * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
 182  *
 183  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 184  */
 185 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
 186 #define FLEXCAN_QUIRK_DISABLE_RXFG      BIT(2) /* Disable RX FIFO Global mask */
 187 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
 188 #define FLEXCAN_QUIRK_DISABLE_MECR      BIT(4) /* Disable Memory error detection */
 189 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
 190 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
 191 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN        BIT(7) /* default to BE register access */
 192
 193 /* Structure of the message buffer */
 194 struct flexcan_mb {
 195         u32 can_ctrl;
 196         u32 can_id;
 197         u32 data[2];
 198 };
 199
 200 /* Structure of the hardware registers */
 201 struct flexcan_regs {
 202         u32 mcr;                /* 0x00 */
 203         u32 ctrl;               /* 0x04 */
 204         u32 timer;              /* 0x08 */
 205         u32 _reserved1;         /* 0x0c */
 206         u32 rxgmask;            /* 0x10 */
 207         u32 rx14mask;           /* 0x14 */
 208         u32 rx15mask;           /* 0x18 */
 209         u32 ecr;                /* 0x1c */
 210         u32 esr;                /* 0x20 */
 211         u32 imask2;             /* 0x24 */
 212         u32 imask1;             /* 0x28 */
 213         u32 iflag2;             /* 0x2c */
 214         u32 iflag1;             /* 0x30 */
 215         union {                 /* 0x34 */
 216                 u32 gfwr_mx28;  /* MX28, MX53 */
 217                 u32 ctrl2;      /* MX6, VF610 */
 218         };
 219         u32 esr2;               /* 0x38 */
 220         u32 imeur;              /* 0x3c */
 221         u32 lrfr;               /* 0x40 */
 222         u32 crcr;               /* 0x44 */
 223         u32 rxfgmask;           /* 0x48 */
 224         u32 rxfir;              /* 0x4c */
 225         u32 _reserved3[12];     /* 0x50 */
 226         struct flexcan_mb mb[64];       /* 0x80 */
 227         /* FIFO-mode:
 228          *                      MB
 229          * 0x080...0x08f        0       RX message buffer
 230          * 0x090...0x0df        1-5     reserverd
 231          * 0x0e0...0x0ff        6-7     8 entry ID table
 232          *                              (mx25, mx28, mx35, mx53)
 233          * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 234          *                              size conf'ed via ctrl2::RFFN
 235          *                              (mx6, vf610)
 236          */
 237         u32 _reserved4[256];    /* 0x480 */
 238         u32 rximr[64];          /* 0x880 */
 239         u32 _reserved5[24];     /* 0x980 */
 240         u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 241         u32 _reserved6[63];     /* 0x9e4 */
 242         u32 mecr;               /* 0xae0 */
 243         u32 erriar;             /* 0xae4 */
 244         u32 erridpr;            /* 0xae8 */
 245         u32 errippr;            /* 0xaec */
 246         u32 rerrar;             /* 0xaf0 */
 247         u32 rerrdr;             /* 0xaf4 */
 248         u32 rerrsynr;           /* 0xaf8 */
 249         u32 errsr;              /* 0xafc */
 250 };
 251
 252 struct flexcan_devtype_data {
 253         u32 quirks;             /* quirks needed for different IP cores */
 254 };
 255
 256 struct flexcan_priv {
 257         struct can_priv can;
 258         struct can_rx_offload offload;
 259
 260         struct flexcan_regs __iomem *regs;
 261         struct flexcan_mb __iomem *tx_mb_reserved;
 262         u32 reg_ctrl_default;
 263         u32 reg_imask1_default;
 264         u32 reg_imask2_default;
 265
 266         struct clk *clk_ipg;
 267         struct clk *clk_per;
 268         const struct flexcan_devtype_data *devtype_data;
 269         struct regulator *reg_xceiver;
 270
 271         /* Read and Write APIs */
 272         u32 (*read)(void __iomem *addr);
 273         void (*write)(u32 val, void __iomem *addr);
 274 };
 275
 276 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 277         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 278                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 279                 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
 280 };
 281
 282 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 283         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 284                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 285 };
 286
 287 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 288         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 289 };
 290
 291 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 292         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 293                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 294 };
 295
 296 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 297         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 298                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 299                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 300 };
 301
 302 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 303         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 304                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 305                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 306 };
 307
 308 static const struct can_bittiming_const flexcan_bittiming_const = {
 309         .name = DRV_NAME,
 310         .tseg1_min = 4,
 311         .tseg1_max = 16,
 312         .tseg2_min = 2,
 313         .tseg2_max = 8,
 314         .sjw_max = 4,
 315         .brp_min = 1,
 316         .brp_max = 256,
 317         .brp_inc = 1,
 318 };
 319
 320 /* FlexCAN module is essentially modelled as a little-endian IP in most
 321  * SoCs, i.e the registers as well as the message buffer areas are
 322  * implemented in a little-endian fashion.
 323  *
 324  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 325  * module in a big-endian fashion (i.e the registers as well as the
 326  * message buffer areas are implemented in a big-endian way).
 327  *
 328  * In addition, the FlexCAN module can be found on SoCs having ARM or
 329  * PPC cores. So, we need to abstract off the register read/write
 330  * functions, ensuring that these cater to all the combinations of module
 331  * endianness and underlying CPU endianness.
 332  */
 333 static inline u32 flexcan_read_be(void __iomem *addr)
 334 {
 335         return ioread32be(addr);
 336 }
 337
 338 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 339 {
 340         iowrite32be(val, addr);
 341 }
 342
 343 static inline u32 flexcan_read_le(void __iomem *addr)
 344 {
 345         return ioread32(addr);
 346 }
 347
 348 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 349 {
 350         iowrite32(val, addr);
 351 }
 352
 353 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 354 {
 355         struct flexcan_regs __iomem *regs = priv->regs;
 356         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 357
 358         priv->write(reg_ctrl, &regs->ctrl);
 359 }
 360
 361 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 362 {
 363         struct flexcan_regs __iomem *regs = priv->regs;
 364         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 365
 366         priv->write(reg_ctrl, &regs->ctrl);
 367 }
 368
 369 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 370 {
 371         if (!priv->reg_xceiver)
 372                 return 0;
 373
 374         return regulator_enable(priv->reg_xceiver);
 375 }
 376
 377 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 378 {
 379         if (!priv->reg_xceiver)
 380                 return 0;
 381
 382         return regulator_disable(priv->reg_xceiver);
 383 }
 384
 385 static int flexcan_chip_enable(struct flexcan_priv *priv)
 386 {
 387         struct flexcan_regs __iomem *regs = priv->regs;
 388         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 389         u32 reg;
 390
 391         reg = priv->read(&regs->mcr);
 392         reg &= ~FLEXCAN_MCR_MDIS;
 393         priv->write(reg, &regs->mcr);
 394
 395         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 396                 udelay(10);
 397
 398         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 399                 return -ETIMEDOUT;
 400
 401         return 0;
 402 }
 403
 404 static int flexcan_chip_disable(struct flexcan_priv *priv)
 405 {
 406         struct flexcan_regs __iomem *regs = priv->regs;
 407         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 408         u32 reg;
 409
 410         reg = priv->read(&regs->mcr);
 411         reg |= FLEXCAN_MCR_MDIS;
 412         priv->write(reg, &regs->mcr);
 413
 414         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 415                 udelay(10);
 416
 417         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 418                 return -ETIMEDOUT;
 419
 420         return 0;
 421 }
 422
 423 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 424 {
 425         struct flexcan_regs __iomem *regs = priv->regs;
 426         unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 427         u32 reg;
 428
 429         reg = priv->read(&regs->mcr);
 430         reg |= FLEXCAN_MCR_HALT;
 431         priv->write(reg, &regs->mcr);
 432
 433         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 434                 udelay(100);
 435
 436         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 437                 return -ETIMEDOUT;
 438
 439         return 0;
 440 }
 441
 442 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 443 {
 444         struct flexcan_regs __iomem *regs = priv->regs;
 445         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 446         u32 reg;
 447
 448         reg = priv->read(&regs->mcr);
 449         reg &= ~FLEXCAN_MCR_HALT;
 450         priv->write(reg, &regs->mcr);
 451
 452         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 453                 udelay(10);
 454
 455         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 456                 return -ETIMEDOUT;
 457
 458         return 0;
 459 }
 460
 461 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 462 {
 463         struct flexcan_regs __iomem *regs = priv->regs;
 464         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 465
 466         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 467         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 468                 udelay(10);
 469
 470         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 471                 return -ETIMEDOUT;
 472
 473         return 0;
 474 }
 475
 476 static int __flexcan_get_berr_counter(const struct net_device *dev,
 477                                       struct can_berr_counter *bec)
 478 {
 479         const struct flexcan_priv *priv = netdev_priv(dev);
 480         struct flexcan_regs __iomem *regs = priv->regs;
 481         u32 reg = priv->read(&regs->ecr);
 482
 483         bec->txerr = (reg >> 0) & 0xff;
 484         bec->rxerr = (reg >> 8) & 0xff;
 485
 486         return 0;
 487 }
 488
 489 static int flexcan_get_berr_counter(const struct net_device *dev,
 490                                     struct can_berr_counter *bec)
 491 {
 492         const struct flexcan_priv *priv = netdev_priv(dev);
 493         int err;
 494
 495         err = clk_prepare_enable(priv->clk_ipg);
 496         if (err)
 497                 return err;
 498
 499         err = clk_prepare_enable(priv->clk_per);
 500         if (err)
 501                 goto out_disable_ipg;
 502
 503         err = __flexcan_get_berr_counter(dev, bec);
 504
 505         clk_disable_unprepare(priv->clk_per);
 506  out_disable_ipg:
 507         clk_disable_unprepare(priv->clk_ipg);
 508
 509         return err;
 510 }
 511
 512 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 513 {
 514         const struct flexcan_priv *priv = netdev_priv(dev);
 515         struct flexcan_regs __iomem *regs = priv->regs;
 516         struct can_frame *cf = (struct can_frame *)skb->data;
 517         u32 can_id;
 518         u32 data;
 519         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
 520
 521         if (can_dropped_invalid_skb(dev, skb))
 522                 return NETDEV_TX_OK;
 523
 524         netif_stop_queue(dev);
 525
 526         if (cf->can_id & CAN_EFF_FLAG) {
 527                 can_id = cf->can_id & CAN_EFF_MASK;
 528                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 529         } else {
 530                 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 531         }
 532
 533         if (cf->can_id & CAN_RTR_FLAG)
 534                 ctrl |= FLEXCAN_MB_CNT_RTR;
 535
 536         if (cf->can_dlc > 0) {
 537                 data = be32_to_cpup((__be32 *)&cf->data[0]);
 538                 priv->write(data, &regs->mb[FLEXCAN_TX_MB].data[0]);
 539         }
 540         if (cf->can_dlc > 4) {
 541                 data = be32_to_cpup((__be32 *)&cf->data[4]);
 542                 priv->write(data, &regs->mb[FLEXCAN_TX_MB].data[1]);
 543         }
 544
 545         can_put_echo_skb(skb, dev, 0);
 546
 547         priv->write(can_id, &regs->mb[FLEXCAN_TX_MB].can_id);
 548         priv->write(ctrl, &regs->mb[FLEXCAN_TX_MB].can_ctrl);
 549
 550         /* Errata ERR005829 step8:
 551          * Write twice INACTIVE(0x8) code to first MB.
 552          */
 553         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 554                       &priv->tx_mb_reserved->can_ctrl);
 555         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 556                       &priv->tx_mb_reserved->can_ctrl);
 557
 558         return NETDEV_TX_OK;
 559 }
 560
 561 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 562 {
 563         struct flexcan_priv *priv = netdev_priv(dev);
 564         struct flexcan_regs __iomem *regs = priv->regs;
 565         struct sk_buff *skb;
 566         struct can_frame *cf;
 567         bool rx_errors = false, tx_errors = false;
 568         u32 timestamp;
 569
 570         timestamp = priv->read(&regs->timer) << 16;
 571
 572         skb = alloc_can_err_skb(dev, &cf);
 573         if (unlikely(!skb))
 574                 return;
 575
 576         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 577
 578         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 579                 netdev_dbg(dev, "BIT1_ERR irq\n");
 580                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 581                 tx_errors = true;
 582         }
 583         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 584                 netdev_dbg(dev, "BIT0_ERR irq\n");
 585                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 586                 tx_errors = true;
 587         }
 588         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 589                 netdev_dbg(dev, "ACK_ERR irq\n");
 590                 cf->can_id |= CAN_ERR_ACK;
 591                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 592                 tx_errors = true;
 593         }
 594         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 595                 netdev_dbg(dev, "CRC_ERR irq\n");
 596                 cf->data[2] |= CAN_ERR_PROT_BIT;
 597                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 598                 rx_errors = true;
 599         }
 600         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 601                 netdev_dbg(dev, "FRM_ERR irq\n");
 602                 cf->data[2] |= CAN_ERR_PROT_FORM;
 603                 rx_errors = true;
 604         }
 605         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 606                 netdev_dbg(dev, "STF_ERR irq\n");
 607                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 608                 rx_errors = true;
 609         }
 610
 611         priv->can.can_stats.bus_error++;
 612         if (rx_errors)
 613                 dev->stats.rx_errors++;
 614         if (tx_errors)
 615                 dev->stats.tx_errors++;
 616
 617         can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 618 }
 619
 620 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 621 {
 622         struct flexcan_priv *priv = netdev_priv(dev);
 623         struct flexcan_regs __iomem *regs = priv->regs;
 624         struct sk_buff *skb;
 625         struct can_frame *cf;
 626         enum can_state new_state, rx_state, tx_state;
 627         int flt;
 628         struct can_berr_counter bec;
 629         u32 timestamp;
 630
 631         timestamp = priv->read(&regs->timer) << 16;
 632
 633         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 634         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 635                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 636                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 637                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 638                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 639                 new_state = max(tx_state, rx_state);
 640         } else {
 641                 __flexcan_get_berr_counter(dev, &bec);
 642                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 643                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 644                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 645                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 646         }
 647
 648         /* state hasn't changed */
 649         if (likely(new_state == priv->can.state))
 650                 return;
 651
 652         skb = alloc_can_err_skb(dev, &cf);
 653         if (unlikely(!skb))
 654                 return;
 655
 656         can_change_state(dev, cf, tx_state, rx_state);
 657
 658         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 659                 can_bus_off(dev);
 660
 661         can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 662 }
 663
 664 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 665 {
 666         return container_of(offload, struct flexcan_priv, offload);
 667 }
 668
 669 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 670                                          struct can_frame *cf,
 671                                          u32 *timestamp, unsigned int n)
 672 {
 673         struct flexcan_priv *priv = rx_offload_to_priv(offload);
 674         struct flexcan_regs __iomem *regs = priv->regs;
 675         struct flexcan_mb __iomem *mb = &regs->mb[n];
 676         u32 reg_ctrl, reg_id, reg_iflag1;
 677
 678         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 679                 u32 code;
 680
 681                 do {
 682                         reg_ctrl = priv->read(&mb->can_ctrl);
 683                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 684
 685                 /* is this MB empty? */
 686                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 687                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 688                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 689                         return 0;
 690
 691                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 692                         /* This MB was overrun, we lost data */
 693                         offload->dev->stats.rx_over_errors++;
 694                         offload->dev->stats.rx_errors++;
 695                 }
 696         } else {
 697                 reg_iflag1 = priv->read(&regs->iflag1);
 698                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 699                         return 0;
 700
 701                 reg_ctrl = priv->read(&mb->can_ctrl);
 702         }
 703
 704         /* increase timstamp to full 32 bit */
 705         *timestamp = reg_ctrl << 16;
 706
 707         reg_id = priv->read(&mb->can_id);
 708         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 709                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 710         else
 711                 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 712
 713         if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 714                 cf->can_id |= CAN_RTR_FLAG;
 715         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 716
 717         *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
 718         *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
 719
 720         /* mark as read */
 721         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 722                 /* Clear IRQ */
 723                 if (n < 32)
 724                         priv->write(BIT(n), &regs->iflag1);
 725                 else
 726                         priv->write(BIT(n - 32), &regs->iflag2);
 727         } else {
 728                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 729         }
 730
 731         /* Read the Free Running Timer. It is optional but recommended
 732          * to unlock Mailbox as soon as possible and make it available
 733          * for reception.
 734          */
 735         priv->read(&regs->timer);
 736
 737         return 1;
 738 }
 739
 740
 741 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 742 {
 743         struct flexcan_regs __iomem *regs = priv->regs;
 744         u32 iflag1, iflag2;
 745
 746         iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
 747                 ~FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB);
 748         iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
 749
 750         return (u64)iflag2 << 32 | iflag1;
 751 }
 752
 753 static irqreturn_t flexcan_irq(int irq, void *dev_id)
 754 {
 755         struct net_device *dev = dev_id;
 756         struct net_device_stats *stats = &dev->stats;
 757         struct flexcan_priv *priv = netdev_priv(dev);
 758         struct flexcan_regs __iomem *regs = priv->regs;
 759         irqreturn_t handled = IRQ_NONE;
 760         u32 reg_iflag2, reg_esr;
 761         enum can_state last_state = priv->can.state;
 762
 763         /* reception interrupt */
 764         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 765                 u64 reg_iflag;
 766                 int ret;
 767
 768                 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
 769                         handled = IRQ_HANDLED;
 770                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
 771                                                                    reg_iflag);
 772                         if (!ret)
 773                                 break;
 774                 }
 775         } else {
 776                 u32 reg_iflag1;
 777
 778                 reg_iflag1 = priv->read(&regs->iflag1);
 779                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
 780                         handled = IRQ_HANDLED;
 781                         can_rx_offload_irq_offload_fifo(&priv->offload);
 782                 }
 783
 784                 /* FIFO overflow interrupt */
 785                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 786                         handled = IRQ_HANDLED;
 787                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
 788                                     &regs->iflag1);
 789                         dev->stats.rx_over_errors++;
 790                         dev->stats.rx_errors++;
 791                 }
 792         }
 793
 794         reg_iflag2 = priv->read(&regs->iflag2);
 795
 796         /* transmission complete interrupt */
 797         if (reg_iflag2 & FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB)) {
 798                 u32 reg_ctrl = priv->read(&regs->mb[FLEXCAN_TX_MB].can_ctrl);
 799
 800                 handled = IRQ_HANDLED;
 801                 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
 802                                                                0, reg_ctrl << 16);
 803                 stats->tx_packets++;
 804                 can_led_event(dev, CAN_LED_EVENT_TX);
 805
 806                 /* after sending a RTR frame MB is in RX mode */
 807                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 808                             &regs->mb[FLEXCAN_TX_MB].can_ctrl);
 809                 priv->write(FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB), &regs->iflag2);
 810                 netif_wake_queue(dev);
 811         }
 812
 813         reg_esr = priv->read(&regs->esr);
 814
 815         /* ACK all bus error and state change IRQ sources */
 816         if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 817                 handled = IRQ_HANDLED;
 818                 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 819         }
 820
 821         /* state change interrupt or broken error state quirk fix is enabled */
 822         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 823             (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 824                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
 825                 flexcan_irq_state(dev, reg_esr);
 826
 827         /* bus error IRQ - handle if bus error reporting is activated */
 828         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
 829             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
 830                 flexcan_irq_bus_err(dev, reg_esr);
 831
 832         /* availability of error interrupt among state transitions in case
 833          * bus error reporting is de-activated and
 834          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
 835          *  +--------------------------------------------------------------+
 836          *  | +----------------------------------------------+ [stopped /  |
 837          *  | |                                              |  sleeping] -+
 838          *  +-+-> active <-> warning <-> passive -> bus off -+
 839          *        ___________^^^^^^^^^^^^_______________________________
 840          *        disabled(1)  enabled             disabled
 841          *
 842          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
 843          */
 844         if ((last_state != priv->can.state) &&
 845             (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
 846             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
 847                 switch (priv->can.state) {
 848                 case CAN_STATE_ERROR_ACTIVE:
 849                         if (priv->devtype_data->quirks &
 850                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
 851                                 flexcan_error_irq_enable(priv);
 852                         else
 853                                 flexcan_error_irq_disable(priv);
 854                         break;
 855
 856                 case CAN_STATE_ERROR_WARNING:
 857                         flexcan_error_irq_enable(priv);
 858                         break;
 859
 860                 case CAN_STATE_ERROR_PASSIVE:
 861                 case CAN_STATE_BUS_OFF:
 862                         flexcan_error_irq_disable(priv);
 863                         break;
 864
 865                 default:
 866                         break;
 867                 }
 868         }
 869
 870         return handled;
 871 }
 872
 873 static void flexcan_set_bittiming(struct net_device *dev)
 874 {
 875         const struct flexcan_priv *priv = netdev_priv(dev);
 876         const struct can_bittiming *bt = &priv->can.bittiming;
 877         struct flexcan_regs __iomem *regs = priv->regs;
 878         u32 reg;
 879
 880         reg = priv->read(&regs->ctrl);
 881         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 882                  FLEXCAN_CTRL_RJW(0x3) |
 883                  FLEXCAN_CTRL_PSEG1(0x7) |
 884                  FLEXCAN_CTRL_PSEG2(0x7) |
 885                  FLEXCAN_CTRL_PROPSEG(0x7) |
 886                  FLEXCAN_CTRL_LPB |
 887                  FLEXCAN_CTRL_SMP |
 888                  FLEXCAN_CTRL_LOM);
 889
 890         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
 891                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
 892                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
 893                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
 894                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
 895
 896         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 897                 reg |= FLEXCAN_CTRL_LPB;
 898         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 899                 reg |= FLEXCAN_CTRL_LOM;
 900         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
 901                 reg |= FLEXCAN_CTRL_SMP;
 902
 903         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
 904         priv->write(reg, &regs->ctrl);
 905
 906         /* print chip status */
 907         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
 908                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
 909 }
 910
 911 /* flexcan_chip_start
 912  *
 913  * this functions is entered with clocks enabled
 914  *
 915  */
 916 static int flexcan_chip_start(struct net_device *dev)
 917 {
 918         struct flexcan_priv *priv = netdev_priv(dev);
 919         struct flexcan_regs __iomem *regs = priv->regs;
 920         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
 921         int err, i;
 922
 923         /* enable module */
 924         err = flexcan_chip_enable(priv);
 925         if (err)
 926                 return err;
 927
 928         /* soft reset */
 929         err = flexcan_chip_softreset(priv);
 930         if (err)
 931                 goto out_chip_disable;
 932
 933         flexcan_set_bittiming(dev);
 934
 935         /* MCR
 936          *
 937          * enable freeze
 938          * enable fifo
 939          * halt now
 940          * only supervisor access
 941          * enable warning int
 942          * disable local echo
 943          * enable individual RX masking
 944          * choose format C
 945          * set max mailbox number
 946          */
 947         reg_mcr = priv->read(&regs->mcr);
 948         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
 949         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
 950                 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
 951                 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_MB);
 952
 953         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
 954                 reg_mcr &= ~FLEXCAN_MCR_FEN;
 955         else
 956                 reg_mcr |= FLEXCAN_MCR_FEN;
 957
 958         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 959         priv->write(reg_mcr, &regs->mcr);
 960
 961         /* CTRL
 962          *
 963          * disable timer sync feature
 964          *
 965          * disable auto busoff recovery
 966          * transmit lowest buffer first
 967          *
 968          * enable tx and rx warning interrupt
 969          * enable bus off interrupt
 970          * (== FLEXCAN_CTRL_ERR_STATE)
 971          */
 972         reg_ctrl = priv->read(&regs->ctrl);
 973         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
 974         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
 975                 FLEXCAN_CTRL_ERR_STATE;
 976
 977         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
 978          * on most Flexcan cores, too. Otherwise we don't get
 979          * any error warning or passive interrupts.
 980          */
 981         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
 982             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
 983                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
 984         else
 985                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
 986
 987         /* save for later use */
 988         priv->reg_ctrl_default = reg_ctrl;
 989         /* leave interrupts disabled for now */
 990         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
 991         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
 992         priv->write(reg_ctrl, &regs->ctrl);
 993
 994         if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
 995                 reg_ctrl2 = priv->read(&regs->ctrl2);
 996                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
 997                 priv->write(reg_ctrl2, &regs->ctrl2);
 998         }
 999
1000         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1001                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1002                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1003                                     &regs->mb[i].can_ctrl);
1004                 }
1005         } else {
1006                 /* clear and invalidate unused mailboxes first */
1007                 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i <= ARRAY_SIZE(regs->mb); i++) {
1008                         priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1009                                     &regs->mb[i].can_ctrl);
1010                 }
1011         }
1012
1013         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1014         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1015                     &priv->tx_mb_reserved->can_ctrl);
1016
1017         /* mark TX mailbox as INACTIVE */
1018         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1019                     &regs->mb[FLEXCAN_TX_MB].can_ctrl);
1020
1021         /* acceptance mask/acceptance code (accept everything) */
1022         priv->write(0x0, &regs->rxgmask);
1023         priv->write(0x0, &regs->rx14mask);
1024         priv->write(0x0, &regs->rx15mask);
1025
1026         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1027                 priv->write(0x0, &regs->rxfgmask);
1028
1029         /* clear acceptance filters */
1030         for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
1031                 priv->write(0, &regs->rximr[i]);
1032
1033         /* On Vybrid, disable memory error detection interrupts
1034          * and freeze mode.
1035          * This also works around errata e5295 which generates
1036          * false positive memory errors and put the device in
1037          * freeze mode.
1038          */
1039         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1040                 /* Follow the protocol as described in "Detection
1041                  * and Correction of Memory Errors" to write to
1042                  * MECR register
1043                  */
1044                 reg_ctrl2 = priv->read(&regs->ctrl2);
1045                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1046                 priv->write(reg_ctrl2, &regs->ctrl2);
1047
1048                 reg_mecr = priv->read(&regs->mecr);
1049                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1050                 priv->write(reg_mecr, &regs->mecr);
1051                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1052                               FLEXCAN_MECR_FANCEI_MSK);
1053                 priv->write(reg_mecr, &regs->mecr);
1054         }
1055
1056         err = flexcan_transceiver_enable(priv);
1057         if (err)
1058                 goto out_chip_disable;
1059
1060         /* synchronize with the can bus */
1061         err = flexcan_chip_unfreeze(priv);
1062         if (err)
1063                 goto out_transceiver_disable;
1064
1065         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1066
1067         /* enable interrupts atomically */
1068         disable_irq(dev->irq);
1069         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1070         priv->write(priv->reg_imask1_default, &regs->imask1);
1071         priv->write(priv->reg_imask2_default, &regs->imask2);
1072         enable_irq(dev->irq);
1073
1074         /* print chip status */
1075         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1076                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1077
1078         return 0;
1079
1080  out_transceiver_disable:
1081         flexcan_transceiver_disable(priv);
1082  out_chip_disable:
1083         flexcan_chip_disable(priv);
1084         return err;
1085 }
1086
1087 /* flexcan_chip_stop
1088  *
1089  * this functions is entered with clocks enabled
1090  */
1091 static void flexcan_chip_stop(struct net_device *dev)
1092 {
1093         struct flexcan_priv *priv = netdev_priv(dev);
1094         struct flexcan_regs __iomem *regs = priv->regs;
1095
1096         /* freeze + disable module */
1097         flexcan_chip_freeze(priv);
1098         flexcan_chip_disable(priv);
1099
1100         /* Disable all interrupts */
1101         priv->write(0, &regs->imask2);
1102         priv->write(0, &regs->imask1);
1103         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1104                     &regs->ctrl);
1105
1106         flexcan_transceiver_disable(priv);
1107         priv->can.state = CAN_STATE_STOPPED;
1108 }
1109
1110 static int flexcan_open(struct net_device *dev)
1111 {
1112         struct flexcan_priv *priv = netdev_priv(dev);
1113         int err;
1114
1115         err = clk_prepare_enable(priv->clk_ipg);
1116         if (err)
1117                 return err;
1118
1119         err = clk_prepare_enable(priv->clk_per);
1120         if (err)
1121                 goto out_disable_ipg;
1122
1123         err = open_candev(dev);
1124         if (err)
1125                 goto out_disable_per;
1126
1127         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1128         if (err)
1129                 goto out_close;
1130
1131         /* start chip and queuing */
1132         err = flexcan_chip_start(dev);
1133         if (err)
1134                 goto out_free_irq;
1135
1136         can_led_event(dev, CAN_LED_EVENT_OPEN);
1137
1138         can_rx_offload_enable(&priv->offload);
1139         netif_start_queue(dev);
1140
1141         return 0;
1142
1143  out_free_irq:
1144         free_irq(dev->irq, dev);
1145  out_close:
1146         close_candev(dev);
1147  out_disable_per:
1148         clk_disable_unprepare(priv->clk_per);
1149  out_disable_ipg:
1150         clk_disable_unprepare(priv->clk_ipg);
1151
1152         return err;
1153 }
1154
1155 static int flexcan_close(struct net_device *dev)
1156 {
1157         struct flexcan_priv *priv = netdev_priv(dev);
1158
1159         netif_stop_queue(dev);
1160         can_rx_offload_disable(&priv->offload);
1161         flexcan_chip_stop(dev);
1162
1163         free_irq(dev->irq, dev);
1164         clk_disable_unprepare(priv->clk_per);
1165         clk_disable_unprepare(priv->clk_ipg);
1166
1167         close_candev(dev);
1168
1169         can_led_event(dev, CAN_LED_EVENT_STOP);
1170
1171         return 0;
1172 }
1173
1174 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1175 {
1176         int err;
1177
1178         switch (mode) {
1179         case CAN_MODE_START:
1180                 err = flexcan_chip_start(dev);
1181                 if (err)
1182                         return err;
1183
1184                 netif_wake_queue(dev);
1185                 break;
1186
1187         default:
1188                 return -EOPNOTSUPP;
1189         }
1190
1191         return 0;
1192 }
1193
1194 static const struct net_device_ops flexcan_netdev_ops = {
1195         .ndo_open       = flexcan_open,
1196         .ndo_stop       = flexcan_close,
1197         .ndo_start_xmit = flexcan_start_xmit,
1198         .ndo_change_mtu = can_change_mtu,
1199 };
1200
1201 static int register_flexcandev(struct net_device *dev)
1202 {
1203         struct flexcan_priv *priv = netdev_priv(dev);
1204         struct flexcan_regs __iomem *regs = priv->regs;
1205         u32 reg, err;
1206
1207         err = clk_prepare_enable(priv->clk_ipg);
1208         if (err)
1209                 return err;
1210
1211         err = clk_prepare_enable(priv->clk_per);
1212         if (err)
1213                 goto out_disable_ipg;
1214
1215         /* select "bus clock", chip must be disabled */
1216         err = flexcan_chip_disable(priv);
1217         if (err)
1218                 goto out_disable_per;
1219         reg = priv->read(&regs->ctrl);
1220         reg |= FLEXCAN_CTRL_CLK_SRC;
1221         priv->write(reg, &regs->ctrl);
1222
1223         err = flexcan_chip_enable(priv);
1224         if (err)
1225                 goto out_chip_disable;
1226
1227         /* set freeze, halt and activate FIFO, restrict register access */
1228         reg = priv->read(&regs->mcr);
1229         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1230                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1231         priv->write(reg, &regs->mcr);
1232
1233         /* Currently we only support newer versions of this core
1234          * featuring a RX hardware FIFO (although this driver doesn't
1235          * make use of it on some cores). Older cores, found on some
1236          * Coldfire derivates are not tested.
1237          */
1238         reg = priv->read(&regs->mcr);
1239         if (!(reg & FLEXCAN_MCR_FEN)) {
1240                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1241                 err = -ENODEV;
1242                 goto out_chip_disable;
1243         }
1244
1245         err = register_candev(dev);
1246
1247         /* disable core and turn off clocks */
1248  out_chip_disable:
1249         flexcan_chip_disable(priv);
1250  out_disable_per:
1251         clk_disable_unprepare(priv->clk_per);
1252  out_disable_ipg:
1253         clk_disable_unprepare(priv->clk_ipg);
1254
1255         return err;
1256 }
1257
1258 static void unregister_flexcandev(struct net_device *dev)
1259 {
1260         unregister_candev(dev);
1261 }
1262
1263 static const struct of_device_id flexcan_of_match[] = {
1264         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1265         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1266         { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1267         { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1268         { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1269         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1270         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1271         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1272         { /* sentinel */ },
1273 };
1274 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1275
1276 static const struct platform_device_id flexcan_id_table[] = {
1277         { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1278         { /* sentinel */ },
1279 };
1280 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1281
1282 static int flexcan_probe(struct platform_device *pdev)
1283 {
1284         const struct of_device_id *of_id;
1285         const struct flexcan_devtype_data *devtype_data;
1286         struct net_device *dev;
1287         struct flexcan_priv *priv;
1288         struct regulator *reg_xceiver;
1289         struct resource *mem;
1290         struct clk *clk_ipg = NULL, *clk_per = NULL;
1291         struct flexcan_regs __iomem *regs;
1292         int err, irq;
1293         u32 clock_freq = 0;
1294
1295         reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1296         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1297                 return -EPROBE_DEFER;
1298         else if (IS_ERR(reg_xceiver))
1299                 reg_xceiver = NULL;
1300
1301         if (pdev->dev.of_node)
1302                 of_property_read_u32(pdev->dev.of_node,
1303                                      "clock-frequency", &clock_freq);
1304
1305         if (!clock_freq) {
1306                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1307                 if (IS_ERR(clk_ipg)) {
1308                         dev_err(&pdev->dev, "no ipg clock defined\n");
1309                         return PTR_ERR(clk_ipg);
1310                 }
1311
1312                 clk_per = devm_clk_get(&pdev->dev, "per");
1313                 if (IS_ERR(clk_per)) {
1314                         dev_err(&pdev->dev, "no per clock defined\n");
1315                         return PTR_ERR(clk_per);
1316                 }
1317                 clock_freq = clk_get_rate(clk_per);
1318         }
1319
1320         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1321         irq = platform_get_irq(pdev, 0);
1322         if (irq <= 0)
1323                 return -ENODEV;
1324
1325         regs = devm_ioremap_resource(&pdev->dev, mem);
1326         if (IS_ERR(regs))
1327                 return PTR_ERR(regs);
1328
1329         of_id = of_match_device(flexcan_of_match, &pdev->dev);
1330         if (of_id) {
1331                 devtype_data = of_id->data;
1332         } else if (platform_get_device_id(pdev)->driver_data) {
1333                 devtype_data = (struct flexcan_devtype_data *)
1334                         platform_get_device_id(pdev)->driver_data;
1335         } else {
1336                 return -ENODEV;
1337         }
1338
1339         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1340         if (!dev)
1341                 return -ENOMEM;
1342
1343         platform_set_drvdata(pdev, dev);
1344         SET_NETDEV_DEV(dev, &pdev->dev);
1345
1346         dev->netdev_ops = &flexcan_netdev_ops;
1347         dev->irq = irq;
1348         dev->flags |= IFF_ECHO;
1349
1350         priv = netdev_priv(dev);
1351
1352         if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1353             devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1354                 priv->read = flexcan_read_be;
1355                 priv->write = flexcan_write_be;
1356         } else {
1357                 priv->read = flexcan_read_le;
1358                 priv->write = flexcan_write_le;
1359         }
1360
1361         priv->can.clock.freq = clock_freq;
1362         priv->can.bittiming_const = &flexcan_bittiming_const;
1363         priv->can.do_set_mode = flexcan_set_mode;
1364         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1365         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1366                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1367                 CAN_CTRLMODE_BERR_REPORTING;
1368         priv->regs = regs;
1369         priv->clk_ipg = clk_ipg;
1370         priv->clk_per = clk_per;
1371         priv->devtype_data = devtype_data;
1372         priv->reg_xceiver = reg_xceiver;
1373
1374         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1375                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1376         else
1377                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1378
1379         priv->reg_imask1_default = 0;
1380         priv->reg_imask2_default = FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB);
1381
1382         priv->offload.mailbox_read = flexcan_mailbox_read;
1383
1384         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1385                 u64 imask;
1386
1387                 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1388                 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1389
1390                 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1391                 priv->reg_imask1_default |= imask;
1392                 priv->reg_imask2_default |= imask >> 32;
1393
1394                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1395         } else {
1396                 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1397                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1398                 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1399         }
1400         if (err)
1401                 goto failed_offload;
1402
1403         err = register_flexcandev(dev);
1404         if (err) {
1405                 dev_err(&pdev->dev, "registering netdev failed\n");
1406                 goto failed_register;
1407         }
1408
1409         devm_can_led_init(dev);
1410
1411         dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1412                  priv->regs, dev->irq);
1413
1414         return 0;
1415
1416  failed_offload:
1417  failed_register:
1418         free_candev(dev);
1419         return err;
1420 }
1421
1422 static int flexcan_remove(struct platform_device *pdev)
1423 {
1424         struct net_device *dev = platform_get_drvdata(pdev);
1425         struct flexcan_priv *priv = netdev_priv(dev);
1426
1427         unregister_flexcandev(dev);
1428         can_rx_offload_del(&priv->offload);
1429         free_candev(dev);
1430
1431         return 0;
1432 }
1433
1434 static int __maybe_unused flexcan_suspend(struct device *device)
1435 {
1436         struct net_device *dev = dev_get_drvdata(device);
1437         struct flexcan_priv *priv = netdev_priv(dev);
1438         int err;
1439
1440         if (netif_running(dev)) {
1441                 err = flexcan_chip_disable(priv);
1442                 if (err)
1443                         return err;
1444                 netif_stop_queue(dev);
1445                 netif_device_detach(dev);
1446         }
1447         priv->can.state = CAN_STATE_SLEEPING;
1448
1449         return 0;
1450 }
1451
1452 static int __maybe_unused flexcan_resume(struct device *device)
1453 {
1454         struct net_device *dev = dev_get_drvdata(device);
1455         struct flexcan_priv *priv = netdev_priv(dev);
1456         int err;
1457
1458         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1459         if (netif_running(dev)) {
1460                 netif_device_attach(dev);
1461                 netif_start_queue(dev);
1462                 err = flexcan_chip_enable(priv);
1463                 if (err)
1464                         return err;
1465         }
1466         return 0;
1467 }
1468
1469 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1470
1471 static struct platform_driver flexcan_driver = {
1472         .driver = {
1473                 .name = DRV_NAME,
1474                 .pm = &flexcan_pm_ops,
1475                 .of_match_table = flexcan_of_match,
1476         },
1477         .probe = flexcan_probe,
1478         .remove = flexcan_remove,
1479         .id_table = flexcan_id_table,
1480 };
1481
1482 module_platform_driver(flexcan_driver);
1483
1484 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1485               "Marc Kleine-Budde <kernel@pengutronix.de>");
1486 MODULE_LICENSE("GPL v2");
1487 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");