2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 * Your platform definition file should specify something like:
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .model = CAN_MCP251X_MCP2510,
42 * .power_enable = mcp251x_power_enable,
43 * .transceiver_enable = NULL,
46 * static struct spi_board_info spi_board_info[] = {
48 * .modalias = "mcp251x",
49 * .platform_data = &mcp251x_info,
51 * .max_speed_hz = 2*1000*1000,
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
61 #include <linux/can/core.h>
62 #include <linux/can/dev.h>
63 #include <linux/can/platform/mcp251x.h>
64 #include <linux/completion.h>
65 #include <linux/delay.h>
66 #include <linux/device.h>
67 #include <linux/dma-mapping.h>
68 #include <linux/freezer.h>
69 #include <linux/interrupt.h>
71 #include <linux/kernel.h>
72 #include <linux/module.h>
73 #include <linux/netdevice.h>
74 #include <linux/platform_device.h>
75 #include <linux/slab.h>
76 #include <linux/spi/spi.h>
77 #include <linux/uaccess.h>
79 /* SPI interface instruction set */
80 #define INSTRUCTION_WRITE 0x02
81 #define INSTRUCTION_READ 0x03
82 #define INSTRUCTION_BIT_MODIFY 0x05
83 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85 #define INSTRUCTION_RESET 0xC0
87 /* MPC251x registers */
90 # define CANCTRL_REQOP_MASK 0xe0
91 # define CANCTRL_REQOP_CONF 0x80
92 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
93 # define CANCTRL_REQOP_LOOPBACK 0x40
94 # define CANCTRL_REQOP_SLEEP 0x20
95 # define CANCTRL_REQOP_NORMAL 0x00
96 # define CANCTRL_OSM 0x08
97 # define CANCTRL_ABAT 0x10
101 # define CNF1_SJW_SHIFT 6
103 # define CNF2_BTLMODE 0x80
104 # define CNF2_SAM 0x40
105 # define CNF2_PS1_SHIFT 3
107 # define CNF3_SOF 0x08
108 # define CNF3_WAKFIL 0x04
109 # define CNF3_PHSEG2_MASK 0x07
111 # define CANINTE_MERRE 0x80
112 # define CANINTE_WAKIE 0x40
113 # define CANINTE_ERRIE 0x20
114 # define CANINTE_TX2IE 0x10
115 # define CANINTE_TX1IE 0x08
116 # define CANINTE_TX0IE 0x04
117 # define CANINTE_RX1IE 0x02
118 # define CANINTE_RX0IE 0x01
120 # define CANINTF_MERRF 0x80
121 # define CANINTF_WAKIF 0x40
122 # define CANINTF_ERRIF 0x20
123 # define CANINTF_TX2IF 0x10
124 # define CANINTF_TX1IF 0x08
125 # define CANINTF_TX0IF 0x04
126 # define CANINTF_RX1IF 0x02
127 # define CANINTF_RX0IF 0x01
129 # define EFLG_EWARN 0x01
130 # define EFLG_RXWAR 0x02
131 # define EFLG_TXWAR 0x04
132 # define EFLG_RXEP 0x08
133 # define EFLG_TXEP 0x10
134 # define EFLG_TXBO 0x20
135 # define EFLG_RX0OVR 0x40
136 # define EFLG_RX1OVR 0x80
137 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
138 # define TXBCTRL_ABTF 0x40
139 # define TXBCTRL_MLOA 0x20
140 # define TXBCTRL_TXERR 0x10
141 # define TXBCTRL_TXREQ 0x08
142 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
143 # define SIDH_SHIFT 3
144 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
145 # define SIDL_SID_MASK 7
146 # define SIDL_SID_SHIFT 5
147 # define SIDL_EXIDE_SHIFT 3
148 # define SIDL_EID_SHIFT 16
149 # define SIDL_EID_MASK 3
150 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
151 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
152 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
153 # define DLC_RTR_SHIFT 6
154 #define TXBCTRL_OFF 0
155 #define TXBSIDH_OFF 1
156 #define TXBSIDL_OFF 2
157 #define TXBEID8_OFF 3
158 #define TXBEID0_OFF 4
161 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
162 # define RXBCTRL_BUKT 0x04
163 # define RXBCTRL_RXM0 0x20
164 # define RXBCTRL_RXM1 0x40
165 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
166 # define RXBSIDH_SHIFT 3
167 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
168 # define RXBSIDL_IDE 0x08
169 # define RXBSIDL_EID 3
170 # define RXBSIDL_SHIFT 5
171 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
172 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
173 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
174 # define RXBDLC_LEN_MASK 0x0f
175 # define RXBDLC_RTR 0x40
176 #define RXBCTRL_OFF 0
177 #define RXBSIDH_OFF 1
178 #define RXBSIDL_OFF 2
179 #define RXBEID8_OFF 3
180 #define RXBEID0_OFF 4
183 #define RXFSIDH(n) ((n) * 4)
184 #define RXFSIDL(n) ((n) * 4 + 1)
185 #define RXFEID8(n) ((n) * 4 + 2)
186 #define RXFEID0(n) ((n) * 4 + 3)
187 #define RXMSIDH(n) ((n) * 4 + 0x20)
188 #define RXMSIDL(n) ((n) * 4 + 0x21)
189 #define RXMEID8(n) ((n) * 4 + 0x22)
190 #define RXMEID0(n) ((n) * 4 + 0x23)
192 #define GET_BYTE(val, byte) \
193 (((val) >> ((byte) * 8)) & 0xff)
194 #define SET_BYTE(val, byte) \
195 (((val) & 0xff) << ((byte) * 8))
198 * Buffer size required for the largest SPI transfer (i.e., reading a
201 #define CAN_FRAME_MAX_DATA_LEN 8
202 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
203 #define CAN_FRAME_MAX_BITS 128
205 #define TX_ECHO_SKB_MAX 1
207 #define DEVICE_NAME "mcp251x"
209 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
210 module_param(mcp251x_enable_dma, int, S_IRUGO);
211 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
213 static struct can_bittiming_const mcp251x_bittiming_const = {
225 struct mcp251x_priv {
227 struct net_device *net;
228 struct spi_device *spi;
230 struct mutex mcp_lock; /* SPI device lock */
234 dma_addr_t spi_tx_dma;
235 dma_addr_t spi_rx_dma;
237 struct sk_buff *tx_skb;
240 struct workqueue_struct *wq;
241 struct work_struct tx_work;
242 struct work_struct restart_work;
246 #define AFTER_SUSPEND_UP 1
247 #define AFTER_SUSPEND_DOWN 2
248 #define AFTER_SUSPEND_POWER 4
249 #define AFTER_SUSPEND_RESTART 8
253 static void mcp251x_clean(struct net_device *net)
255 struct mcp251x_priv *priv = netdev_priv(net);
257 if (priv->tx_skb || priv->tx_len)
258 net->stats.tx_errors++;
260 dev_kfree_skb(priv->tx_skb);
262 can_free_echo_skb(priv->net, 0);
268 * Note about handling of error return of mcp251x_spi_trans: accessing
269 * registers via SPI is not really different conceptually than using
270 * normal I/O assembler instructions, although it's much more
271 * complicated from a practical POV. So it's not advisable to always
272 * check the return value of this function. Imagine that every
273 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
274 * error();", it would be a great mess (well there are some situation
275 * when exception handling C++ like could be useful after all). So we
276 * just check that transfers are OK at the beginning of our
277 * conversation with the chip and to avoid doing really nasty things
278 * (like injecting bogus packets in the network stack).
280 static int mcp251x_spi_trans(struct spi_device *spi, int len)
282 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
283 struct spi_transfer t = {
284 .tx_buf = priv->spi_tx_buf,
285 .rx_buf = priv->spi_rx_buf,
289 struct spi_message m;
292 spi_message_init(&m);
294 if (mcp251x_enable_dma) {
295 t.tx_dma = priv->spi_tx_dma;
296 t.rx_dma = priv->spi_rx_dma;
300 spi_message_add_tail(&t, &m);
302 ret = spi_sync(spi, &m);
304 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
308 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
310 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
313 priv->spi_tx_buf[0] = INSTRUCTION_READ;
314 priv->spi_tx_buf[1] = reg;
316 mcp251x_spi_trans(spi, 3);
317 val = priv->spi_rx_buf[2];
322 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
323 uint8_t *v1, uint8_t *v2)
325 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
327 priv->spi_tx_buf[0] = INSTRUCTION_READ;
328 priv->spi_tx_buf[1] = reg;
330 mcp251x_spi_trans(spi, 4);
332 *v1 = priv->spi_rx_buf[2];
333 *v2 = priv->spi_rx_buf[3];
336 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
338 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
340 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
341 priv->spi_tx_buf[1] = reg;
342 priv->spi_tx_buf[2] = val;
344 mcp251x_spi_trans(spi, 3);
347 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
348 u8 mask, uint8_t val)
350 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
352 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
353 priv->spi_tx_buf[1] = reg;
354 priv->spi_tx_buf[2] = mask;
355 priv->spi_tx_buf[3] = val;
357 mcp251x_spi_trans(spi, 4);
360 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
361 int len, int tx_buf_idx)
363 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
364 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
366 if (pdata->model == CAN_MCP251X_MCP2510) {
369 for (i = 1; i < TXBDAT_OFF + len; i++)
370 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
373 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
374 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
378 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
381 u32 sid, eid, exide, rtr;
382 u8 buf[SPI_TRANSFER_BUF_LEN];
384 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
386 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
388 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
389 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
390 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
392 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
393 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
394 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
395 (exide << SIDL_EXIDE_SHIFT) |
396 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
397 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
398 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
399 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
400 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
401 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
402 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
405 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
408 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
409 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
411 if (pdata->model == CAN_MCP251X_MCP2510) {
414 for (i = 1; i < RXBDAT_OFF; i++)
415 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
417 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
418 for (; i < (RXBDAT_OFF + len); i++)
419 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
421 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
422 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
423 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
427 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
429 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
431 struct can_frame *frame;
432 u8 buf[SPI_TRANSFER_BUF_LEN];
434 skb = alloc_can_skb(priv->net, &frame);
436 dev_err(&spi->dev, "cannot allocate RX skb\n");
437 priv->net->stats.rx_dropped++;
441 mcp251x_hw_rx_frame(spi, buf, buf_idx);
442 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
443 /* Extended ID format */
444 frame->can_id = CAN_EFF_FLAG;
446 /* Extended ID part */
447 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
448 SET_BYTE(buf[RXBEID8_OFF], 1) |
449 SET_BYTE(buf[RXBEID0_OFF], 0) |
450 /* Standard ID part */
451 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
452 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
453 /* Remote transmission request */
454 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
455 frame->can_id |= CAN_RTR_FLAG;
457 /* Standard ID format */
459 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
460 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
463 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
464 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
466 priv->net->stats.rx_packets++;
467 priv->net->stats.rx_bytes += frame->can_dlc;
471 static void mcp251x_hw_sleep(struct spi_device *spi)
473 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
476 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
477 struct net_device *net)
479 struct mcp251x_priv *priv = netdev_priv(net);
480 struct spi_device *spi = priv->spi;
482 if (priv->tx_skb || priv->tx_len) {
483 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
484 return NETDEV_TX_BUSY;
487 if (can_dropped_invalid_skb(net, skb))
490 netif_stop_queue(net);
492 queue_work(priv->wq, &priv->tx_work);
497 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
499 struct mcp251x_priv *priv = netdev_priv(net);
504 /* We have to delay work since SPI I/O may sleep */
505 priv->can.state = CAN_STATE_ERROR_ACTIVE;
506 priv->restart_tx = 1;
507 if (priv->can.restart_ms == 0)
508 priv->after_suspend = AFTER_SUSPEND_RESTART;
509 queue_work(priv->wq, &priv->restart_work);
518 static int mcp251x_set_normal_mode(struct spi_device *spi)
520 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
521 unsigned long timeout;
523 /* Enable interrupts */
524 mcp251x_write_reg(spi, CANINTE,
525 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
526 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
528 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
529 /* Put device into loopback mode */
530 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
531 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
532 /* Put device into listen-only mode */
533 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
535 /* Put device into normal mode */
536 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
538 /* Wait for the device to enter normal mode */
539 timeout = jiffies + HZ;
540 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
542 if (time_after(jiffies, timeout)) {
543 dev_err(&spi->dev, "MCP251x didn't"
544 " enter in normal mode\n");
549 priv->can.state = CAN_STATE_ERROR_ACTIVE;
553 static int mcp251x_do_set_bittiming(struct net_device *net)
555 struct mcp251x_priv *priv = netdev_priv(net);
556 struct can_bittiming *bt = &priv->can.bittiming;
557 struct spi_device *spi = priv->spi;
559 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
561 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
562 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
564 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
566 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
567 (bt->phase_seg2 - 1));
568 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
569 mcp251x_read_reg(spi, CNF1),
570 mcp251x_read_reg(spi, CNF2),
571 mcp251x_read_reg(spi, CNF3));
576 static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
577 struct spi_device *spi)
579 mcp251x_do_set_bittiming(net);
581 mcp251x_write_reg(spi, RXBCTRL(0),
582 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
583 mcp251x_write_reg(spi, RXBCTRL(1),
584 RXBCTRL_RXM0 | RXBCTRL_RXM1);
588 static int mcp251x_hw_reset(struct spi_device *spi)
590 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
592 unsigned long timeout;
594 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
595 ret = spi_write(spi, priv->spi_tx_buf, 1);
597 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
601 /* Wait for reset to finish */
602 timeout = jiffies + HZ;
604 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
605 != CANCTRL_REQOP_CONF) {
607 if (time_after(jiffies, timeout)) {
608 dev_err(&spi->dev, "MCP251x didn't"
609 " enter in conf mode after reset\n");
616 static int mcp251x_hw_probe(struct spi_device *spi)
620 mcp251x_hw_reset(spi);
623 * Please note that these are "magic values" based on after
624 * reset defaults taken from data sheet which allows us to see
625 * if we really have a chip on the bus (we avoid common all
626 * zeroes or all ones situations)
628 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
629 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
631 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
633 /* Check for power up default values */
634 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
637 static void mcp251x_open_clean(struct net_device *net)
639 struct mcp251x_priv *priv = netdev_priv(net);
640 struct spi_device *spi = priv->spi;
641 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
643 free_irq(spi->irq, priv);
644 mcp251x_hw_sleep(spi);
645 if (pdata->transceiver_enable)
646 pdata->transceiver_enable(0);
650 static int mcp251x_stop(struct net_device *net)
652 struct mcp251x_priv *priv = netdev_priv(net);
653 struct spi_device *spi = priv->spi;
654 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
658 priv->force_quit = 1;
659 free_irq(spi->irq, priv);
660 destroy_workqueue(priv->wq);
663 mutex_lock(&priv->mcp_lock);
665 /* Disable and clear pending interrupts */
666 mcp251x_write_reg(spi, CANINTE, 0x00);
667 mcp251x_write_reg(spi, CANINTF, 0x00);
669 mcp251x_write_reg(spi, TXBCTRL(0), 0);
672 mcp251x_hw_sleep(spi);
674 if (pdata->transceiver_enable)
675 pdata->transceiver_enable(0);
677 priv->can.state = CAN_STATE_STOPPED;
679 mutex_unlock(&priv->mcp_lock);
684 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
687 struct can_frame *frame;
689 skb = alloc_can_err_skb(net, &frame);
691 frame->can_id = can_id;
692 frame->data[1] = data1;
696 "cannot allocate error skb\n");
700 static void mcp251x_tx_work_handler(struct work_struct *ws)
702 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
704 struct spi_device *spi = priv->spi;
705 struct net_device *net = priv->net;
706 struct can_frame *frame;
708 mutex_lock(&priv->mcp_lock);
710 if (priv->can.state == CAN_STATE_BUS_OFF) {
713 frame = (struct can_frame *)priv->tx_skb->data;
715 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
716 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
717 mcp251x_hw_tx(spi, frame, 0);
718 priv->tx_len = 1 + frame->can_dlc;
719 can_put_echo_skb(priv->tx_skb, net, 0);
723 mutex_unlock(&priv->mcp_lock);
726 static void mcp251x_restart_work_handler(struct work_struct *ws)
728 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
730 struct spi_device *spi = priv->spi;
731 struct net_device *net = priv->net;
733 mutex_lock(&priv->mcp_lock);
734 if (priv->after_suspend) {
736 mcp251x_hw_reset(spi);
737 mcp251x_setup(net, priv, spi);
738 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
739 mcp251x_set_normal_mode(spi);
740 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
741 netif_device_attach(net);
743 mcp251x_set_normal_mode(spi);
744 netif_wake_queue(net);
746 mcp251x_hw_sleep(spi);
748 priv->after_suspend = 0;
749 priv->force_quit = 0;
752 if (priv->restart_tx) {
753 priv->restart_tx = 0;
754 mcp251x_write_reg(spi, TXBCTRL(0), 0);
756 netif_wake_queue(net);
757 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
759 mutex_unlock(&priv->mcp_lock);
762 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
764 struct mcp251x_priv *priv = dev_id;
765 struct spi_device *spi = priv->spi;
766 struct net_device *net = priv->net;
768 mutex_lock(&priv->mcp_lock);
769 while (!priv->force_quit) {
770 enum can_state new_state;
772 int can_id = 0, data1 = 0;
774 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
776 if (intf & CANINTF_RX0IF) {
777 mcp251x_hw_rx(spi, 0);
778 /* Free one buffer ASAP */
779 mcp251x_write_bits(spi, CANINTF, intf & CANINTF_RX0IF,
783 if (intf & CANINTF_RX1IF)
784 mcp251x_hw_rx(spi, 1);
786 mcp251x_write_bits(spi, CANINTF, intf, 0x00);
788 mcp251x_write_reg(spi, EFLG, 0x00);
790 /* Update can state */
791 if (eflag & EFLG_TXBO) {
792 new_state = CAN_STATE_BUS_OFF;
793 can_id |= CAN_ERR_BUSOFF;
794 } else if (eflag & EFLG_TXEP) {
795 new_state = CAN_STATE_ERROR_PASSIVE;
796 can_id |= CAN_ERR_CRTL;
797 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
798 } else if (eflag & EFLG_RXEP) {
799 new_state = CAN_STATE_ERROR_PASSIVE;
800 can_id |= CAN_ERR_CRTL;
801 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
802 } else if (eflag & EFLG_TXWAR) {
803 new_state = CAN_STATE_ERROR_WARNING;
804 can_id |= CAN_ERR_CRTL;
805 data1 |= CAN_ERR_CRTL_TX_WARNING;
806 } else if (eflag & EFLG_RXWAR) {
807 new_state = CAN_STATE_ERROR_WARNING;
808 can_id |= CAN_ERR_CRTL;
809 data1 |= CAN_ERR_CRTL_RX_WARNING;
811 new_state = CAN_STATE_ERROR_ACTIVE;
814 /* Update can state statistics */
815 switch (priv->can.state) {
816 case CAN_STATE_ERROR_ACTIVE:
817 if (new_state >= CAN_STATE_ERROR_WARNING &&
818 new_state <= CAN_STATE_BUS_OFF)
819 priv->can.can_stats.error_warning++;
820 case CAN_STATE_ERROR_WARNING: /* fallthrough */
821 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
822 new_state <= CAN_STATE_BUS_OFF)
823 priv->can.can_stats.error_passive++;
828 priv->can.state = new_state;
830 if (intf & CANINTF_ERRIF) {
831 /* Handle overflow counters */
832 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
833 if (eflag & EFLG_RX0OVR) {
834 net->stats.rx_over_errors++;
835 net->stats.rx_errors++;
837 if (eflag & EFLG_RX1OVR) {
838 net->stats.rx_over_errors++;
839 net->stats.rx_errors++;
841 can_id |= CAN_ERR_CRTL;
842 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
844 mcp251x_error_skb(net, can_id, data1);
847 if (priv->can.state == CAN_STATE_BUS_OFF) {
848 if (priv->can.restart_ms == 0) {
849 priv->force_quit = 1;
851 mcp251x_hw_sleep(spi);
859 if (intf & (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)) {
860 net->stats.tx_packets++;
861 net->stats.tx_bytes += priv->tx_len - 1;
863 can_get_echo_skb(net, 0);
866 netif_wake_queue(net);
870 mutex_unlock(&priv->mcp_lock);
874 static int mcp251x_open(struct net_device *net)
876 struct mcp251x_priv *priv = netdev_priv(net);
877 struct spi_device *spi = priv->spi;
878 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
881 ret = open_candev(net);
883 dev_err(&spi->dev, "unable to set initial baudrate!\n");
887 mutex_lock(&priv->mcp_lock);
888 if (pdata->transceiver_enable)
889 pdata->transceiver_enable(1);
891 priv->force_quit = 0;
895 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
896 IRQF_TRIGGER_FALLING, DEVICE_NAME, priv);
898 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
899 if (pdata->transceiver_enable)
900 pdata->transceiver_enable(0);
905 priv->wq = create_freezeable_workqueue("mcp251x_wq");
906 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
907 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
909 ret = mcp251x_hw_reset(spi);
911 mcp251x_open_clean(net);
914 ret = mcp251x_setup(net, priv, spi);
916 mcp251x_open_clean(net);
919 ret = mcp251x_set_normal_mode(spi);
921 mcp251x_open_clean(net);
924 netif_wake_queue(net);
927 mutex_unlock(&priv->mcp_lock);
931 static const struct net_device_ops mcp251x_netdev_ops = {
932 .ndo_open = mcp251x_open,
933 .ndo_stop = mcp251x_stop,
934 .ndo_start_xmit = mcp251x_hard_start_xmit,
937 static int __devinit mcp251x_can_probe(struct spi_device *spi)
939 struct net_device *net;
940 struct mcp251x_priv *priv;
941 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
942 int model = spi_get_device_id(spi)->driver_data;
946 /* Platform data is required for osc freq */
950 pdata->model = model;
952 /* Allocate can/net device */
953 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
959 net->netdev_ops = &mcp251x_netdev_ops;
960 net->flags |= IFF_ECHO;
962 priv = netdev_priv(net);
963 priv->can.bittiming_const = &mcp251x_bittiming_const;
964 priv->can.do_set_mode = mcp251x_do_set_mode;
965 priv->can.clock.freq = pdata->oscillator_frequency / 2;
966 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
967 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
969 dev_set_drvdata(&spi->dev, priv);
972 mutex_init(&priv->mcp_lock);
974 /* If requested, allocate DMA buffers */
975 if (mcp251x_enable_dma) {
976 spi->dev.coherent_dma_mask = ~0;
979 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
980 * that much and share it between Tx and Rx DMA buffers.
982 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
987 if (priv->spi_tx_buf) {
988 priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf +
990 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
993 /* Fall back to non-DMA */
994 mcp251x_enable_dma = 0;
998 /* Allocate non-DMA buffers */
999 if (!mcp251x_enable_dma) {
1000 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1001 if (!priv->spi_tx_buf) {
1005 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1006 if (!priv->spi_rx_buf) {
1012 if (pdata->power_enable)
1013 pdata->power_enable(1);
1015 /* Call out to platform specific setup */
1016 if (pdata->board_specific_setup)
1017 pdata->board_specific_setup(spi);
1019 SET_NETDEV_DEV(net, &spi->dev);
1021 /* Configure the SPI bus */
1022 spi->mode = SPI_MODE_0;
1023 spi->bits_per_word = 8;
1026 /* Here is OK to not lock the MCP, no one knows about it yet */
1027 if (!mcp251x_hw_probe(spi)) {
1028 dev_info(&spi->dev, "Probe failed\n");
1031 mcp251x_hw_sleep(spi);
1033 if (pdata->transceiver_enable)
1034 pdata->transceiver_enable(0);
1036 ret = register_candev(net);
1038 dev_info(&spi->dev, "probed\n");
1042 if (!mcp251x_enable_dma)
1043 kfree(priv->spi_rx_buf);
1045 if (!mcp251x_enable_dma)
1046 kfree(priv->spi_tx_buf);
1049 if (mcp251x_enable_dma)
1050 dma_free_coherent(&spi->dev, PAGE_SIZE,
1051 priv->spi_tx_buf, priv->spi_tx_dma);
1053 if (pdata->power_enable)
1054 pdata->power_enable(0);
1055 dev_err(&spi->dev, "probe failed\n");
1060 static int __devexit mcp251x_can_remove(struct spi_device *spi)
1062 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1063 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1064 struct net_device *net = priv->net;
1066 unregister_candev(net);
1069 if (mcp251x_enable_dma) {
1070 dma_free_coherent(&spi->dev, PAGE_SIZE,
1071 priv->spi_tx_buf, priv->spi_tx_dma);
1073 kfree(priv->spi_tx_buf);
1074 kfree(priv->spi_rx_buf);
1077 if (pdata->power_enable)
1078 pdata->power_enable(0);
1084 static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1086 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1087 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1088 struct net_device *net = priv->net;
1090 priv->force_quit = 1;
1091 disable_irq(spi->irq);
1093 * Note: at this point neither IST nor workqueues are running.
1094 * open/stop cannot be called anyway so locking is not needed
1096 if (netif_running(net)) {
1097 netif_device_detach(net);
1099 mcp251x_hw_sleep(spi);
1100 if (pdata->transceiver_enable)
1101 pdata->transceiver_enable(0);
1102 priv->after_suspend = AFTER_SUSPEND_UP;
1104 priv->after_suspend = AFTER_SUSPEND_DOWN;
1107 if (pdata->power_enable) {
1108 pdata->power_enable(0);
1109 priv->after_suspend |= AFTER_SUSPEND_POWER;
1115 static int mcp251x_can_resume(struct spi_device *spi)
1117 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1118 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1120 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1121 pdata->power_enable(1);
1122 queue_work(priv->wq, &priv->restart_work);
1124 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1125 if (pdata->transceiver_enable)
1126 pdata->transceiver_enable(1);
1127 queue_work(priv->wq, &priv->restart_work);
1129 priv->after_suspend = 0;
1132 priv->force_quit = 0;
1133 enable_irq(spi->irq);
1137 #define mcp251x_can_suspend NULL
1138 #define mcp251x_can_resume NULL
1141 static struct spi_device_id mcp251x_id_table[] = {
1142 { "mcp251x", 0 /* Use pdata.model */ },
1143 { "mcp2510", CAN_MCP251X_MCP2510 },
1144 { "mcp2515", CAN_MCP251X_MCP2515 },
1148 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1150 static struct spi_driver mcp251x_can_driver = {
1152 .name = DEVICE_NAME,
1153 .bus = &spi_bus_type,
1154 .owner = THIS_MODULE,
1157 .id_table = mcp251x_id_table,
1158 .probe = mcp251x_can_probe,
1159 .remove = __devexit_p(mcp251x_can_remove),
1160 .suspend = mcp251x_can_suspend,
1161 .resume = mcp251x_can_resume,
1164 static int __init mcp251x_can_init(void)
1166 return spi_register_driver(&mcp251x_can_driver);
1169 static void __exit mcp251x_can_exit(void)
1171 spi_unregister_driver(&mcp251x_can_driver);
1174 module_init(mcp251x_can_init);
1175 module_exit(mcp251x_can_exit);
1177 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1178 "Christian Pellegrin <chripell@evolware.org>");
1179 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1180 MODULE_LICENSE("GPL v2");