2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_data/b53.h>
28 #include <linux/phy.h>
29 #include <linux/etherdevice.h>
30 #include <linux/if_bridge.h>
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80 /* BCM63xx MIB counters */
81 static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
129 static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169 static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
228 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
234 for (i = 0; i < 10; i++) {
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
241 usleep_range(100, 200);
247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
259 entry |= VA_VALID_25;
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
304 } else if (is5365(dev)) {
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
326 static void b53_set_forwarding(struct b53_device *dev, int enable)
328 struct dsa_switch *ds = dev->ds;
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
334 mgmt |= SM_SW_FWD_EN;
336 mgmt &= ~SM_SW_FWD_EN;
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
340 /* Include IMP port in dumb forwarding mode when no tagging protocol is
343 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
345 mgmt |= B53_MII_DUMB_FWDG_EN;
346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
350 static void b53_enable_vlan(struct b53_device *dev, bool enable)
352 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
358 if (is5325(dev) || is5365(dev)) {
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
361 } else if (is63xx(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
369 mgmt &= ~SM_SW_FWD_MODE;
372 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
373 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
374 vc4 &= ~VC4_ING_VID_CHECK_MASK;
375 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
376 vc5 |= VC5_DROP_VTABLE_MISS;
379 vc0 &= ~VC0_RESERVED_1;
381 if (is5325(dev) || is5365(dev))
382 vc1 |= VC1_RX_MCST_TAG_EN;
385 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
386 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
387 vc4 &= ~VC4_ING_VID_CHECK_MASK;
388 vc5 &= ~VC5_DROP_VTABLE_MISS;
390 if (is5325(dev) || is5365(dev))
391 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
393 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
395 if (is5325(dev) || is5365(dev))
396 vc1 &= ~VC1_RX_MCST_TAG_EN;
399 if (!is5325(dev) && !is5365(dev))
400 vc5 &= ~VC5_VID_FFF_EN;
402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
405 if (is5325(dev) || is5365(dev)) {
406 /* enable the high 8 bit vid check on 5325 */
407 if (is5325(dev) && enable)
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
415 } else if (is63xx(dev)) {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
420 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
425 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
428 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
431 u16 max_size = JMS_MIN_SIZE;
433 if (is5325(dev) || is5365(dev))
437 port_mask = dev->enabled_ports;
438 max_size = JMS_MAX_SIZE;
440 port_mask |= JPM_10_100_JUMBO_EN;
443 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
444 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
447 static int b53_flush_arl(struct b53_device *dev, u8 mask)
451 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
452 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
454 for (i = 0; i < 10; i++) {
457 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
460 if (!(fast_age_ctrl & FAST_AGE_DONE))
468 /* Only age dynamic entries (default behavior) */
469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
473 static int b53_fast_age_port(struct b53_device *dev, int port)
475 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
477 return b53_flush_arl(dev, FAST_AGE_PORT);
480 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
482 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
484 return b53_flush_arl(dev, FAST_AGE_VLAN);
487 static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
489 struct b53_device *dev = ds->priv;
493 /* Enable the IMP port to be in the same VLAN as the other ports
494 * on a per-port basis such that we only have Port i and IMP in
497 b53_for_each_port(dev, i) {
498 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
499 pvlan |= BIT(cpu_port);
500 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
504 static int b53_enable_port(struct dsa_switch *ds, int port,
505 struct phy_device *phy)
507 struct b53_device *dev = ds->priv;
508 unsigned int cpu_port = dev->cpu_port;
511 /* Clear the Rx and Tx disable bits and set to no spanning tree */
512 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
514 /* Set this port, and only this one to be in the default VLAN,
515 * if member of a bridge, restore its membership prior to
516 * bringing down this port.
518 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
521 pvlan |= dev->ports[port].vlan_ctl_mask;
522 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
524 b53_imp_vlan_setup(ds, cpu_port);
529 static void b53_disable_port(struct dsa_switch *ds, int port,
530 struct phy_device *phy)
532 struct b53_device *dev = ds->priv;
535 /* Disable Tx/Rx for the port */
536 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
537 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
538 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
541 static void b53_enable_cpu_port(struct b53_device *dev)
543 unsigned int cpu_port = dev->cpu_port;
546 /* BCM5325 CPU port is at 8 */
547 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
548 cpu_port = B53_CPU_PORT;
550 port_ctrl = PORT_CTRL_RX_BCST_EN |
551 PORT_CTRL_RX_MCST_EN |
552 PORT_CTRL_RX_UCST_EN;
553 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
556 static void b53_enable_mib(struct b53_device *dev)
560 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
561 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
562 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
565 static int b53_configure_vlan(struct b53_device *dev)
567 struct b53_vlan vl = { 0 };
570 /* clear all vlan entries */
571 if (is5325(dev) || is5365(dev)) {
572 for (i = 1; i < dev->num_vlans; i++)
573 b53_set_vlan_entry(dev, i, &vl);
575 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
578 b53_enable_vlan(dev, false);
580 b53_for_each_port(dev, i)
581 b53_write16(dev, B53_VLAN_PAGE,
582 B53_VLAN_PORT_DEF_TAG(i), 1);
584 if (!is5325(dev) && !is5365(dev))
585 b53_set_jumbo(dev, dev->enable_jumbo, false);
590 static void b53_switch_reset_gpio(struct b53_device *dev)
592 int gpio = dev->reset_gpio;
597 /* Reset sequence: RESET low(50ms)->high(20ms)
599 gpio_set_value(gpio, 0);
602 gpio_set_value(gpio, 1);
605 dev->current_page = 0xff;
608 static int b53_switch_reset(struct b53_device *dev)
610 unsigned int timeout = 1000;
613 b53_switch_reset_gpio(dev);
616 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
617 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
620 /* This is specific to 58xx devices here, do not use is58xx() which
621 * covers the larger Starfigther 2 family, including 7445/7278 which
622 * still use this driver as a library and need to perform the reset
625 if (dev->chip_id == BCM58XX_DEVICE_ID) {
626 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
627 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
628 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
631 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
635 usleep_range(1000, 2000);
636 } while (timeout-- > 0);
642 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
644 if (!(mgmt & SM_SW_FWD_EN)) {
645 mgmt &= ~SM_SW_FWD_MODE;
646 mgmt |= SM_SW_FWD_EN;
648 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
649 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
651 if (!(mgmt & SM_SW_FWD_EN)) {
652 dev_err(dev->dev, "Failed to enable switch!\n");
659 return b53_flush_arl(dev, FAST_AGE_STATIC);
662 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
664 struct b53_device *priv = ds->priv;
668 if (priv->ops->phy_read16)
669 ret = priv->ops->phy_read16(priv, addr, reg, &value);
671 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
674 return ret ? ret : value;
677 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
679 struct b53_device *priv = ds->priv;
681 if (priv->ops->phy_write16)
682 return priv->ops->phy_write16(priv, addr, reg, val);
684 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
687 static int b53_reset_switch(struct b53_device *priv)
690 priv->enable_jumbo = false;
692 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
693 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
695 return b53_switch_reset(priv);
698 static int b53_apply_config(struct b53_device *priv)
700 /* disable switching */
701 b53_set_forwarding(priv, 0);
703 b53_configure_vlan(priv);
705 /* enable switching */
706 b53_set_forwarding(priv, 1);
711 static void b53_reset_mib(struct b53_device *priv)
715 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
717 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
719 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
723 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
727 else if (is63xx(dev))
728 return b53_mibs_63xx;
729 else if (is58xx(dev))
730 return b53_mibs_58xx;
735 static unsigned int b53_get_mib_size(struct b53_device *dev)
738 return B53_MIBS_65_SIZE;
739 else if (is63xx(dev))
740 return B53_MIBS_63XX_SIZE;
741 else if (is58xx(dev))
742 return B53_MIBS_58XX_SIZE;
744 return B53_MIBS_SIZE;
747 void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
749 struct b53_device *dev = ds->priv;
750 const struct b53_mib_desc *mibs = b53_get_mib(dev);
751 unsigned int mib_size = b53_get_mib_size(dev);
754 for (i = 0; i < mib_size; i++)
755 memcpy(data + i * ETH_GSTRING_LEN,
756 mibs[i].name, ETH_GSTRING_LEN);
758 EXPORT_SYMBOL(b53_get_strings);
760 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
762 struct b53_device *dev = ds->priv;
763 const struct b53_mib_desc *mibs = b53_get_mib(dev);
764 unsigned int mib_size = b53_get_mib_size(dev);
765 const struct b53_mib_desc *s;
769 if (is5365(dev) && port == 5)
772 mutex_lock(&dev->stats_mutex);
774 for (i = 0; i < mib_size; i++) {
778 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
782 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
789 mutex_unlock(&dev->stats_mutex);
791 EXPORT_SYMBOL(b53_get_ethtool_stats);
793 int b53_get_sset_count(struct dsa_switch *ds)
795 struct b53_device *dev = ds->priv;
797 return b53_get_mib_size(dev);
799 EXPORT_SYMBOL(b53_get_sset_count);
801 static int b53_setup(struct dsa_switch *ds)
803 struct b53_device *dev = ds->priv;
807 ret = b53_reset_switch(dev);
809 dev_err(ds->dev, "failed to reset switch\n");
815 ret = b53_apply_config(dev);
817 dev_err(ds->dev, "failed to apply configuration\n");
819 for (port = 0; port < dev->num_ports; port++) {
820 if (BIT(port) & ds->enabled_port_mask)
821 b53_enable_port(ds, port, NULL);
822 else if (dsa_is_cpu_port(ds, port))
823 b53_enable_cpu_port(dev);
825 b53_disable_port(ds, port, NULL);
831 static void b53_adjust_link(struct dsa_switch *ds, int port,
832 struct phy_device *phydev)
834 struct b53_device *dev = ds->priv;
835 u8 rgmii_ctrl = 0, reg = 0, off;
837 if (!phy_is_pseudo_fixed_link(phydev))
840 /* Override the port settings */
841 if (port == dev->cpu_port) {
842 off = B53_PORT_OVERRIDE_CTRL;
843 reg = PORT_OVERRIDE_EN;
845 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
849 /* Set the link UP */
851 reg |= PORT_OVERRIDE_LINK;
853 if (phydev->duplex == DUPLEX_FULL)
854 reg |= PORT_OVERRIDE_FULL_DUPLEX;
856 switch (phydev->speed) {
858 reg |= PORT_OVERRIDE_SPEED_2000M;
861 reg |= PORT_OVERRIDE_SPEED_1000M;
864 reg |= PORT_OVERRIDE_SPEED_100M;
867 reg |= PORT_OVERRIDE_SPEED_10M;
870 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
874 /* Enable flow control on BCM5301x's CPU port */
875 if (is5301x(dev) && port == dev->cpu_port)
876 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
879 if (phydev->asym_pause)
880 reg |= PORT_OVERRIDE_TX_FLOW;
881 reg |= PORT_OVERRIDE_RX_FLOW;
884 b53_write8(dev, B53_CTRL_PAGE, off, reg);
886 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
888 off = B53_RGMII_CTRL_IMP;
890 off = B53_RGMII_CTRL_P(port);
892 /* Configure the port RGMII clock delay by DLL disabled and
893 * tx_clk aligned timing (restoring to reset defaults)
895 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
896 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
897 RGMII_CTRL_TIMING_SEL);
899 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
900 * sure that we enable the port TX clock internal delay to
901 * account for this internal delay that is inserted, otherwise
902 * the switch won't be able to receive correctly.
904 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
905 * any delay neither on transmission nor reception, so the
906 * BCM53125 must also be configured accordingly to account for
907 * the lack of delay and introduce
909 * The BCM53125 switch has its RX clock and TX clock control
910 * swapped, hence the reason why we modify the TX clock path in
913 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
914 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
915 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
916 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
917 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
918 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
920 dev_info(ds->dev, "Configured port %d for %s\n", port,
921 phy_modes(phydev->interface));
924 /* configure MII port if necessary */
926 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
929 /* reverse mii needs to be enabled */
930 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
931 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
932 reg | PORT_OVERRIDE_RV_MII_25);
933 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
936 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
938 "Failed to enable reverse MII mode\n");
942 } else if (is5301x(dev)) {
943 if (port != dev->cpu_port) {
944 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
947 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
948 gmii_po |= GMII_PO_LINK |
953 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
958 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
962 EXPORT_SYMBOL(b53_vlan_filtering);
964 int b53_vlan_prepare(struct dsa_switch *ds, int port,
965 const struct switchdev_obj_port_vlan *vlan,
966 struct switchdev_trans *trans)
968 struct b53_device *dev = ds->priv;
970 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
973 if (vlan->vid_end > dev->num_vlans)
976 b53_enable_vlan(dev, true);
980 EXPORT_SYMBOL(b53_vlan_prepare);
982 void b53_vlan_add(struct dsa_switch *ds, int port,
983 const struct switchdev_obj_port_vlan *vlan,
984 struct switchdev_trans *trans)
986 struct b53_device *dev = ds->priv;
987 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
988 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
989 unsigned int cpu_port = dev->cpu_port;
993 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
994 vl = &dev->vlans[vid];
996 b53_get_vlan_entry(dev, vid, vl);
998 vl->members |= BIT(port) | BIT(cpu_port);
1000 vl->untag |= BIT(port);
1002 vl->untag &= ~BIT(port);
1003 vl->untag &= ~BIT(cpu_port);
1005 b53_set_vlan_entry(dev, vid, vl);
1006 b53_fast_age_vlan(dev, vid);
1010 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1012 b53_fast_age_vlan(dev, vid);
1015 EXPORT_SYMBOL(b53_vlan_add);
1017 int b53_vlan_del(struct dsa_switch *ds, int port,
1018 const struct switchdev_obj_port_vlan *vlan)
1020 struct b53_device *dev = ds->priv;
1021 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1022 struct b53_vlan *vl;
1026 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1028 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1029 vl = &dev->vlans[vid];
1031 b53_get_vlan_entry(dev, vid, vl);
1033 vl->members &= ~BIT(port);
1036 if (is5325(dev) || is5365(dev))
1043 vl->untag &= ~(BIT(port));
1045 b53_set_vlan_entry(dev, vid, vl);
1046 b53_fast_age_vlan(dev, vid);
1049 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1050 b53_fast_age_vlan(dev, pvid);
1054 EXPORT_SYMBOL(b53_vlan_del);
1056 int b53_vlan_dump(struct dsa_switch *ds, int port,
1057 struct switchdev_obj_port_vlan *vlan,
1058 switchdev_obj_dump_cb_t *cb)
1060 struct b53_device *dev = ds->priv;
1061 u16 vid, vid_start = 0, pvid;
1062 struct b53_vlan *vl;
1065 if (is5325(dev) || is5365(dev))
1068 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1070 /* Use our software cache for dumps, since we do not have any HW
1071 * operation returning only the used/valid VLANs
1073 for (vid = vid_start; vid < dev->num_vlans; vid++) {
1074 vl = &dev->vlans[vid];
1079 if (!(vl->members & BIT(port)))
1082 vlan->vid_begin = vlan->vid_end = vid;
1085 if (vl->untag & BIT(port))
1086 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1088 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1090 err = cb(&vlan->obj);
1097 EXPORT_SYMBOL(b53_vlan_dump);
1099 /* Address Resolution Logic routines */
1100 static int b53_arl_op_wait(struct b53_device *dev)
1102 unsigned int timeout = 10;
1106 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1107 if (!(reg & ARLTBL_START_DONE))
1110 usleep_range(1000, 2000);
1111 } while (timeout--);
1113 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1118 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1125 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1126 reg |= ARLTBL_START_DONE;
1131 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1133 return b53_arl_op_wait(dev);
1136 static int b53_arl_read(struct b53_device *dev, u64 mac,
1137 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1143 ret = b53_arl_op_wait(dev);
1148 for (i = 0; i < dev->num_arl_entries; i++) {
1152 b53_read64(dev, B53_ARLIO_PAGE,
1153 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1154 b53_read32(dev, B53_ARLIO_PAGE,
1155 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1156 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1158 if (!(fwd_entry & ARLTBL_VALID))
1160 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1168 static int b53_arl_op(struct b53_device *dev, int op, int port,
1169 const unsigned char *addr, u16 vid, bool is_valid)
1171 struct b53_arl_entry ent;
1173 u64 mac, mac_vid = 0;
1177 /* Convert the array into a 64-bit MAC */
1178 mac = ether_addr_to_u64(addr);
1180 /* Perform a read for the given MAC and VID */
1181 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1182 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1184 /* Issue a read operation for this MAC */
1185 ret = b53_arl_rw_op(dev, 1);
1189 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1190 /* If this is a read, just finish now */
1194 /* We could not find a matching MAC, so reset to a new entry */
1200 memset(&ent, 0, sizeof(ent));
1202 ent.is_valid = is_valid;
1204 ent.is_static = true;
1205 memcpy(ent.mac, addr, ETH_ALEN);
1206 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1208 b53_write64(dev, B53_ARLIO_PAGE,
1209 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1210 b53_write32(dev, B53_ARLIO_PAGE,
1211 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1213 return b53_arl_rw_op(dev, 0);
1216 int b53_fdb_prepare(struct dsa_switch *ds, int port,
1217 const struct switchdev_obj_port_fdb *fdb,
1218 struct switchdev_trans *trans)
1220 struct b53_device *priv = ds->priv;
1222 /* 5325 and 5365 require some more massaging, but could
1223 * be supported eventually
1225 if (is5325(priv) || is5365(priv))
1230 EXPORT_SYMBOL(b53_fdb_prepare);
1232 void b53_fdb_add(struct dsa_switch *ds, int port,
1233 const struct switchdev_obj_port_fdb *fdb,
1234 struct switchdev_trans *trans)
1236 struct b53_device *priv = ds->priv;
1238 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1239 pr_err("%s: failed to add MAC address\n", __func__);
1241 EXPORT_SYMBOL(b53_fdb_add);
1243 int b53_fdb_del(struct dsa_switch *ds, int port,
1244 const struct switchdev_obj_port_fdb *fdb)
1246 struct b53_device *priv = ds->priv;
1248 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1250 EXPORT_SYMBOL(b53_fdb_del);
1252 static int b53_arl_search_wait(struct b53_device *dev)
1254 unsigned int timeout = 1000;
1258 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1259 if (!(reg & ARL_SRCH_STDN))
1262 if (reg & ARL_SRCH_VLID)
1265 usleep_range(1000, 2000);
1266 } while (timeout--);
1271 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1272 struct b53_arl_entry *ent)
1277 b53_read64(dev, B53_ARLIO_PAGE,
1278 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1279 b53_read32(dev, B53_ARLIO_PAGE,
1280 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1281 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1284 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1285 struct switchdev_obj_port_fdb *fdb,
1286 switchdev_obj_dump_cb_t *cb)
1291 if (port != ent->port)
1294 ether_addr_copy(fdb->addr, ent->mac);
1295 fdb->vid = ent->vid;
1296 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1298 return cb(&fdb->obj);
1301 int b53_fdb_dump(struct dsa_switch *ds, int port,
1302 struct switchdev_obj_port_fdb *fdb,
1303 switchdev_obj_dump_cb_t *cb)
1305 struct b53_device *priv = ds->priv;
1306 struct b53_arl_entry results[2];
1307 unsigned int count = 0;
1311 /* Start search operation */
1312 reg = ARL_SRCH_STDN;
1313 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1316 ret = b53_arl_search_wait(priv);
1320 b53_arl_search_rd(priv, 0, &results[0]);
1321 ret = b53_fdb_copy(port, &results[0], fdb, cb);
1325 if (priv->num_arl_entries > 2) {
1326 b53_arl_search_rd(priv, 1, &results[1]);
1327 ret = b53_fdb_copy(port, &results[1], fdb, cb);
1331 if (!results[0].is_valid && !results[1].is_valid)
1335 } while (count++ < 1024);
1339 EXPORT_SYMBOL(b53_fdb_dump);
1341 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1343 struct b53_device *dev = ds->priv;
1344 s8 cpu_port = ds->dst->cpu_dp->index;
1348 /* Make this port leave the all VLANs join since we will have proper
1349 * VLAN entries from now on
1352 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1354 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1355 reg &= ~BIT(cpu_port);
1356 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1359 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1361 b53_for_each_port(dev, i) {
1362 if (ds->ports[i].bridge_dev != br)
1365 /* Add this local port to the remote port VLAN control
1366 * membership and update the remote port bitmask
1368 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1370 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1371 dev->ports[i].vlan_ctl_mask = reg;
1376 /* Configure the local port VLAN control membership to include
1377 * remote ports and update the local port bitmask
1379 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1380 dev->ports[port].vlan_ctl_mask = pvlan;
1384 EXPORT_SYMBOL(b53_br_join);
1386 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1388 struct b53_device *dev = ds->priv;
1389 struct b53_vlan *vl = &dev->vlans[0];
1390 s8 cpu_port = ds->dst->cpu_dp->index;
1392 u16 pvlan, reg, pvid;
1394 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1396 b53_for_each_port(dev, i) {
1397 /* Don't touch the remaining ports */
1398 if (ds->ports[i].bridge_dev != br)
1401 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1403 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1404 dev->ports[port].vlan_ctl_mask = reg;
1406 /* Prevent self removal to preserve isolation */
1411 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1412 dev->ports[port].vlan_ctl_mask = pvlan;
1414 if (is5325(dev) || is5365(dev))
1419 /* Make this port join all VLANs without VLAN entries */
1421 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1423 if (!(reg & BIT(cpu_port)))
1424 reg |= BIT(cpu_port);
1425 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1427 b53_get_vlan_entry(dev, pvid, vl);
1428 vl->members |= BIT(port) | BIT(dev->cpu_port);
1429 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1430 b53_set_vlan_entry(dev, pvid, vl);
1433 EXPORT_SYMBOL(b53_br_leave);
1435 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1437 struct b53_device *dev = ds->priv;
1442 case BR_STATE_DISABLED:
1443 hw_state = PORT_CTRL_DIS_STATE;
1445 case BR_STATE_LISTENING:
1446 hw_state = PORT_CTRL_LISTEN_STATE;
1448 case BR_STATE_LEARNING:
1449 hw_state = PORT_CTRL_LEARN_STATE;
1451 case BR_STATE_FORWARDING:
1452 hw_state = PORT_CTRL_FWD_STATE;
1454 case BR_STATE_BLOCKING:
1455 hw_state = PORT_CTRL_BLOCK_STATE;
1458 dev_err(ds->dev, "invalid STP state: %d\n", state);
1462 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1463 reg &= ~PORT_CTRL_STP_STATE_MASK;
1465 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1467 EXPORT_SYMBOL(b53_br_set_stp_state);
1469 void b53_br_fast_age(struct dsa_switch *ds, int port)
1471 struct b53_device *dev = ds->priv;
1473 if (b53_fast_age_port(dev, port))
1474 dev_err(ds->dev, "fast ageing failed\n");
1476 EXPORT_SYMBOL(b53_br_fast_age);
1478 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1480 return DSA_TAG_PROTO_NONE;
1483 int b53_mirror_add(struct dsa_switch *ds, int port,
1484 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1486 struct b53_device *dev = ds->priv;
1490 loc = B53_IG_MIR_CTL;
1492 loc = B53_EG_MIR_CTL;
1494 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
1495 reg &= ~MIRROR_MASK;
1497 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1499 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
1500 reg &= ~CAP_PORT_MASK;
1501 reg |= mirror->to_local_port;
1503 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1507 EXPORT_SYMBOL(b53_mirror_add);
1509 void b53_mirror_del(struct dsa_switch *ds, int port,
1510 struct dsa_mall_mirror_tc_entry *mirror)
1512 struct b53_device *dev = ds->priv;
1513 bool loc_disable = false, other_loc_disable = false;
1516 if (mirror->ingress)
1517 loc = B53_IG_MIR_CTL;
1519 loc = B53_EG_MIR_CTL;
1521 /* Update the desired ingress/egress register */
1522 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
1524 if (!(reg & MIRROR_MASK))
1526 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1528 /* Now look at the other one to know if we can disable mirroring
1531 if (mirror->ingress)
1532 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
1534 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
1535 if (!(reg & MIRROR_MASK))
1536 other_loc_disable = true;
1538 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
1539 /* Both no longer have ports, let's disable mirroring */
1540 if (loc_disable && other_loc_disable) {
1542 reg &= ~mirror->to_local_port;
1544 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1546 EXPORT_SYMBOL(b53_mirror_del);
1548 static const struct dsa_switch_ops b53_switch_ops = {
1549 .get_tag_protocol = b53_get_tag_protocol,
1551 .get_strings = b53_get_strings,
1552 .get_ethtool_stats = b53_get_ethtool_stats,
1553 .get_sset_count = b53_get_sset_count,
1554 .phy_read = b53_phy_read16,
1555 .phy_write = b53_phy_write16,
1556 .adjust_link = b53_adjust_link,
1557 .port_enable = b53_enable_port,
1558 .port_disable = b53_disable_port,
1559 .port_bridge_join = b53_br_join,
1560 .port_bridge_leave = b53_br_leave,
1561 .port_stp_state_set = b53_br_set_stp_state,
1562 .port_fast_age = b53_br_fast_age,
1563 .port_vlan_filtering = b53_vlan_filtering,
1564 .port_vlan_prepare = b53_vlan_prepare,
1565 .port_vlan_add = b53_vlan_add,
1566 .port_vlan_del = b53_vlan_del,
1567 .port_vlan_dump = b53_vlan_dump,
1568 .port_fdb_prepare = b53_fdb_prepare,
1569 .port_fdb_dump = b53_fdb_dump,
1570 .port_fdb_add = b53_fdb_add,
1571 .port_fdb_del = b53_fdb_del,
1572 .port_mirror_add = b53_mirror_add,
1573 .port_mirror_del = b53_mirror_del,
1576 struct b53_chip_data {
1578 const char *dev_name;
1589 #define B53_VTA_REGS \
1590 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1591 #define B53_VTA_REGS_9798 \
1592 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1593 #define B53_VTA_REGS_63XX \
1594 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1596 static const struct b53_chip_data b53_switch_chips[] = {
1598 .chip_id = BCM5325_DEVICE_ID,
1599 .dev_name = "BCM5325",
1601 .enabled_ports = 0x1f,
1603 .cpu_port = B53_CPU_PORT_25,
1604 .duplex_reg = B53_DUPLEX_STAT_FE,
1607 .chip_id = BCM5365_DEVICE_ID,
1608 .dev_name = "BCM5365",
1610 .enabled_ports = 0x1f,
1612 .cpu_port = B53_CPU_PORT_25,
1613 .duplex_reg = B53_DUPLEX_STAT_FE,
1616 .chip_id = BCM5395_DEVICE_ID,
1617 .dev_name = "BCM5395",
1619 .enabled_ports = 0x1f,
1621 .cpu_port = B53_CPU_PORT,
1622 .vta_regs = B53_VTA_REGS,
1623 .duplex_reg = B53_DUPLEX_STAT_GE,
1624 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1625 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1628 .chip_id = BCM5397_DEVICE_ID,
1629 .dev_name = "BCM5397",
1631 .enabled_ports = 0x1f,
1633 .cpu_port = B53_CPU_PORT,
1634 .vta_regs = B53_VTA_REGS_9798,
1635 .duplex_reg = B53_DUPLEX_STAT_GE,
1636 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1637 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1640 .chip_id = BCM5398_DEVICE_ID,
1641 .dev_name = "BCM5398",
1643 .enabled_ports = 0x7f,
1645 .cpu_port = B53_CPU_PORT,
1646 .vta_regs = B53_VTA_REGS_9798,
1647 .duplex_reg = B53_DUPLEX_STAT_GE,
1648 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1649 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1652 .chip_id = BCM53115_DEVICE_ID,
1653 .dev_name = "BCM53115",
1655 .enabled_ports = 0x1f,
1657 .vta_regs = B53_VTA_REGS,
1658 .cpu_port = B53_CPU_PORT,
1659 .duplex_reg = B53_DUPLEX_STAT_GE,
1660 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1661 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1664 .chip_id = BCM53125_DEVICE_ID,
1665 .dev_name = "BCM53125",
1667 .enabled_ports = 0xff,
1669 .cpu_port = B53_CPU_PORT,
1670 .vta_regs = B53_VTA_REGS,
1671 .duplex_reg = B53_DUPLEX_STAT_GE,
1672 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1673 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1676 .chip_id = BCM53128_DEVICE_ID,
1677 .dev_name = "BCM53128",
1679 .enabled_ports = 0x1ff,
1681 .cpu_port = B53_CPU_PORT,
1682 .vta_regs = B53_VTA_REGS,
1683 .duplex_reg = B53_DUPLEX_STAT_GE,
1684 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1685 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1688 .chip_id = BCM63XX_DEVICE_ID,
1689 .dev_name = "BCM63xx",
1691 .enabled_ports = 0, /* pdata must provide them */
1693 .cpu_port = B53_CPU_PORT,
1694 .vta_regs = B53_VTA_REGS_63XX,
1695 .duplex_reg = B53_DUPLEX_STAT_63XX,
1696 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1697 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1700 .chip_id = BCM53010_DEVICE_ID,
1701 .dev_name = "BCM53010",
1703 .enabled_ports = 0x1f,
1705 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1706 .vta_regs = B53_VTA_REGS,
1707 .duplex_reg = B53_DUPLEX_STAT_GE,
1708 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1709 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1712 .chip_id = BCM53011_DEVICE_ID,
1713 .dev_name = "BCM53011",
1715 .enabled_ports = 0x1bf,
1717 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1718 .vta_regs = B53_VTA_REGS,
1719 .duplex_reg = B53_DUPLEX_STAT_GE,
1720 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1721 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1724 .chip_id = BCM53012_DEVICE_ID,
1725 .dev_name = "BCM53012",
1727 .enabled_ports = 0x1bf,
1729 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1730 .vta_regs = B53_VTA_REGS,
1731 .duplex_reg = B53_DUPLEX_STAT_GE,
1732 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1733 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1736 .chip_id = BCM53018_DEVICE_ID,
1737 .dev_name = "BCM53018",
1739 .enabled_ports = 0x1f,
1741 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1742 .vta_regs = B53_VTA_REGS,
1743 .duplex_reg = B53_DUPLEX_STAT_GE,
1744 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1745 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1748 .chip_id = BCM53019_DEVICE_ID,
1749 .dev_name = "BCM53019",
1751 .enabled_ports = 0x1f,
1753 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1754 .vta_regs = B53_VTA_REGS,
1755 .duplex_reg = B53_DUPLEX_STAT_GE,
1756 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1757 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1760 .chip_id = BCM58XX_DEVICE_ID,
1761 .dev_name = "BCM585xx/586xx/88312",
1763 .enabled_ports = 0x1ff,
1765 .cpu_port = B53_CPU_PORT,
1766 .vta_regs = B53_VTA_REGS,
1767 .duplex_reg = B53_DUPLEX_STAT_GE,
1768 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1769 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1772 .chip_id = BCM7445_DEVICE_ID,
1773 .dev_name = "BCM7445",
1775 .enabled_ports = 0x1ff,
1777 .cpu_port = B53_CPU_PORT,
1778 .vta_regs = B53_VTA_REGS,
1779 .duplex_reg = B53_DUPLEX_STAT_GE,
1780 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1781 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1784 .chip_id = BCM7278_DEVICE_ID,
1785 .dev_name = "BCM7278",
1787 .enabled_ports = 0x1ff,
1789 .cpu_port = B53_CPU_PORT,
1790 .vta_regs = B53_VTA_REGS,
1791 .duplex_reg = B53_DUPLEX_STAT_GE,
1792 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1793 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1797 static int b53_switch_init(struct b53_device *dev)
1802 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1803 const struct b53_chip_data *chip = &b53_switch_chips[i];
1805 if (chip->chip_id == dev->chip_id) {
1806 if (!dev->enabled_ports)
1807 dev->enabled_ports = chip->enabled_ports;
1808 dev->name = chip->dev_name;
1809 dev->duplex_reg = chip->duplex_reg;
1810 dev->vta_regs[0] = chip->vta_regs[0];
1811 dev->vta_regs[1] = chip->vta_regs[1];
1812 dev->vta_regs[2] = chip->vta_regs[2];
1813 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1814 dev->cpu_port = chip->cpu_port;
1815 dev->num_vlans = chip->vlans;
1816 dev->num_arl_entries = chip->arl_entries;
1821 /* check which BCM5325x version we have */
1825 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1827 /* check reserved bits */
1833 /* BCM5325F - do not use port 4 */
1834 dev->enabled_ports &= ~BIT(4);
1837 /* On the BCM47XX SoCs this is the supported internal switch.*/
1838 #ifndef CONFIG_BCM47XX
1845 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1848 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1849 /* use second IMP port if GMII is enabled */
1850 if (strap_value & SV_GMII_CTRL_115)
1854 /* cpu port is always last */
1855 dev->num_ports = dev->cpu_port + 1;
1856 dev->enabled_ports |= BIT(dev->cpu_port);
1858 dev->ports = devm_kzalloc(dev->dev,
1859 sizeof(struct b53_port) * dev->num_ports,
1864 dev->vlans = devm_kzalloc(dev->dev,
1865 sizeof(struct b53_vlan) * dev->num_vlans,
1870 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1871 if (dev->reset_gpio >= 0) {
1872 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1873 GPIOF_OUT_INIT_HIGH, "robo_reset");
1881 struct b53_device *b53_switch_alloc(struct device *base,
1882 const struct b53_io_ops *ops,
1885 struct dsa_switch *ds;
1886 struct b53_device *dev;
1888 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
1892 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1902 ds->ops = &b53_switch_ops;
1903 mutex_init(&dev->reg_mutex);
1904 mutex_init(&dev->stats_mutex);
1908 EXPORT_SYMBOL(b53_switch_alloc);
1910 int b53_switch_detect(struct b53_device *dev)
1917 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1923 /* BCM5325 and BCM5365 do not have this register so reads
1924 * return 0. But the read operation did succeed, so assume this
1927 * Next check if we can write to the 5325's VTA register; for
1928 * 5365 it is read only.
1930 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1931 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1934 dev->chip_id = BCM5325_DEVICE_ID;
1936 dev->chip_id = BCM5365_DEVICE_ID;
1938 case BCM5395_DEVICE_ID:
1939 case BCM5397_DEVICE_ID:
1940 case BCM5398_DEVICE_ID:
1944 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1949 case BCM53115_DEVICE_ID:
1950 case BCM53125_DEVICE_ID:
1951 case BCM53128_DEVICE_ID:
1952 case BCM53010_DEVICE_ID:
1953 case BCM53011_DEVICE_ID:
1954 case BCM53012_DEVICE_ID:
1955 case BCM53018_DEVICE_ID:
1956 case BCM53019_DEVICE_ID:
1957 dev->chip_id = id32;
1960 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1966 if (dev->chip_id == BCM5325_DEVICE_ID)
1967 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1970 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1973 EXPORT_SYMBOL(b53_switch_detect);
1975 int b53_switch_register(struct b53_device *dev)
1980 dev->chip_id = dev->pdata->chip_id;
1981 dev->enabled_ports = dev->pdata->enabled_ports;
1984 if (!dev->chip_id && b53_switch_detect(dev))
1987 ret = b53_switch_init(dev);
1991 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1993 return dsa_register_switch(dev->ds);
1995 EXPORT_SYMBOL(b53_switch_register);
1997 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1998 MODULE_DESCRIPTION("B53 switch library");
1999 MODULE_LICENSE("Dual BSD/GPL");