1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom Starfighter 2 DSA switch driver
5 * Copyright (C) 2014, Broadcom Corporation
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
20 #include <linux/of_net.h>
21 #include <linux/of_mdio.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_bridge.h>
25 #include <linux/brcmphy.h>
26 #include <linux/etherdevice.h>
27 #include <linux/platform_data/b53.h>
30 #include "bcm_sf2_regs.h"
31 #include "b53/b53_priv.h"
32 #include "b53/b53_regs.h"
34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
40 /* Enable the port memories */
41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
42 reg &= ~P_TXQ_PSM_VDD(port);
43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
45 /* Enable forwarding */
46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
48 /* Enable IMP port in dumb mode */
49 reg = core_readl(priv, CORE_SWITCH_CTRL);
50 reg |= MII_DUMB_FWDG_EN;
51 core_writel(priv, reg, CORE_SWITCH_CTRL);
53 /* Configure Traffic Class to QoS mapping, allow each priority to map
54 * to a different queue number
56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
58 reg |= i << (PRT_TO_QID_SHIFT * i);
59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
61 b53_brcm_hdr_setup(ds, port);
64 if (priv->type == BCM7445_DEVICE_ID)
65 offset = CORE_STS_OVERRIDE_IMP;
67 offset = CORE_STS_OVERRIDE_IMP2;
69 /* Force link status for IMP port */
70 reg = core_readl(priv, offset);
71 reg |= (MII_SW_OR | LINK_STS);
72 core_writel(priv, reg, offset);
74 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
75 reg = core_readl(priv, CORE_IMP_CTL);
76 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
77 reg &= ~(RX_DIS | TX_DIS);
78 core_writel(priv, reg, CORE_IMP_CTL);
80 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
81 reg &= ~(RX_DIS | TX_DIS);
82 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
86 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
88 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
91 reg = reg_readl(priv, REG_SPHY_CNTRL);
94 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
95 reg_writel(priv, reg, REG_SPHY_CNTRL);
97 reg = reg_readl(priv, REG_SPHY_CNTRL);
100 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
101 reg_writel(priv, reg, REG_SPHY_CNTRL);
105 reg_writel(priv, reg, REG_SPHY_CNTRL);
107 /* Use PHY-driven LED signaling */
109 reg = reg_readl(priv, REG_LED_CNTRL(0));
110 reg |= SPDLNK_SRC_SEL;
111 reg_writel(priv, reg, REG_LED_CNTRL(0));
115 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
125 /* Port 0 interrupts are located on the first bank */
126 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
129 off = P_IRQ_OFF(port);
133 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
136 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
146 /* Port 0 interrupts are located on the first bank */
147 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
148 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
151 off = P_IRQ_OFF(port);
155 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
156 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
159 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
160 struct phy_device *phy)
162 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
166 if (!dsa_is_user_port(ds, port))
169 /* Clear the memory power down */
170 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
171 reg &= ~P_TXQ_PSM_VDD(port);
172 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
174 /* Enable learning */
175 reg = core_readl(priv, CORE_DIS_LEARN);
177 core_writel(priv, reg, CORE_DIS_LEARN);
179 /* Enable Broadcom tags for that port if requested */
180 if (priv->brcm_tag_mask & BIT(port))
181 b53_brcm_hdr_setup(ds, port);
183 /* Configure Traffic Class to QoS mapping, allow each priority to map
184 * to a different queue number
186 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
187 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
188 reg |= i << (PRT_TO_QID_SHIFT * i);
189 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
191 /* Re-enable the GPHY and re-apply workarounds */
192 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
193 bcm_sf2_gphy_enable_set(ds, true);
195 /* if phy_stop() has been called before, phy
196 * will be in halted state, and phy_start()
199 * the resume path does not configure back
200 * autoneg settings, and since we hard reset
201 * the phy manually here, we need to reset the
202 * state machine also.
204 phy->state = PHY_READY;
209 /* Enable MoCA port interrupts to get notified */
210 if (port == priv->moca_port)
211 bcm_sf2_port_intr_enable(priv, port);
213 /* Set per-queue pause threshold to 32 */
214 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
216 /* Set ACB threshold to 24 */
217 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
218 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
219 SF2_NUM_EGRESS_QUEUES + i));
220 reg &= ~XOFF_THRESHOLD_MASK;
222 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
223 SF2_NUM_EGRESS_QUEUES + i));
226 return b53_enable_port(ds, port, phy);
229 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
231 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
234 /* Disable learning while in WoL mode */
235 if (priv->wol_ports_mask & (1 << port)) {
236 reg = core_readl(priv, CORE_DIS_LEARN);
238 core_writel(priv, reg, CORE_DIS_LEARN);
242 if (port == priv->moca_port)
243 bcm_sf2_port_intr_disable(priv, port);
245 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
246 bcm_sf2_gphy_enable_set(ds, false);
248 b53_disable_port(ds, port);
250 /* Power down the port memory */
251 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
252 reg |= P_TXQ_PSM_VDD(port);
253 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
257 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
263 reg = reg_readl(priv, REG_SWITCH_CNTRL);
264 reg |= MDIO_MASTER_SEL;
265 reg_writel(priv, reg, REG_SWITCH_CNTRL);
267 /* Page << 8 | offset */
270 core_writel(priv, addr, reg);
272 /* Page << 8 | offset */
273 reg = 0x80 << 8 | regnum << 1;
277 ret = core_readl(priv, reg);
279 core_writel(priv, val, reg);
281 reg = reg_readl(priv, REG_SWITCH_CNTRL);
282 reg &= ~MDIO_MASTER_SEL;
283 reg_writel(priv, reg, REG_SWITCH_CNTRL);
288 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
290 struct bcm_sf2_priv *priv = bus->priv;
292 /* Intercept reads from Broadcom pseudo-PHY address, else, send
293 * them to our master MDIO bus controller
295 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
296 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
298 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
301 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
304 struct bcm_sf2_priv *priv = bus->priv;
306 /* Intercept writes to the Broadcom pseudo-PHY address, else,
307 * send them to our master MDIO bus controller
309 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
310 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
312 return mdiobus_write_nested(priv->master_mii_bus, addr,
316 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
318 struct dsa_switch *ds = dev_id;
319 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
321 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
323 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
328 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
330 struct dsa_switch *ds = dev_id;
331 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
333 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
335 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
337 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
338 priv->port_sts[7].link = true;
339 dsa_port_phylink_mac_change(ds, 7, true);
341 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
342 priv->port_sts[7].link = false;
343 dsa_port_phylink_mac_change(ds, 7, false);
349 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
351 unsigned int timeout = 1000;
354 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
355 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
356 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
359 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
360 if (!(reg & SOFTWARE_RESET))
363 usleep_range(1000, 2000);
364 } while (timeout-- > 0);
372 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
374 intrl2_0_mask_set(priv, 0xffffffff);
375 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
376 intrl2_1_mask_set(priv, 0xffffffff);
377 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
380 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
381 struct device_node *dn)
383 struct device_node *port;
384 unsigned int port_num;
385 phy_interface_t mode;
388 priv->moca_port = -1;
390 for_each_available_child_of_node(dn, port) {
391 if (of_property_read_u32(port, "reg", &port_num))
394 /* Internal PHYs get assigned a specific 'phy-mode' property
395 * value: "internal" to help flag them before MDIO probing
396 * has completed, since they might be turned off at that
399 err = of_get_phy_mode(port, &mode);
403 if (mode == PHY_INTERFACE_MODE_INTERNAL)
404 priv->int_phy_mask |= 1 << port_num;
406 if (mode == PHY_INTERFACE_MODE_MOCA)
407 priv->moca_port = port_num;
409 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
410 priv->brcm_tag_mask |= 1 << port_num;
414 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
416 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
417 struct device_node *dn;
421 /* Find our integrated MDIO bus node */
422 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
423 priv->master_mii_bus = of_mdio_find_bus(dn);
424 if (!priv->master_mii_bus)
425 return -EPROBE_DEFER;
427 get_device(&priv->master_mii_bus->dev);
428 priv->master_mii_dn = dn;
430 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
431 if (!priv->slave_mii_bus)
434 priv->slave_mii_bus->priv = priv;
435 priv->slave_mii_bus->name = "sf2 slave mii";
436 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
437 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
438 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
440 priv->slave_mii_bus->dev.of_node = dn;
442 /* Include the pseudo-PHY address to divert reads towards our
443 * workaround. This is only required for 7445D0, since 7445E0
444 * disconnects the internal switch pseudo-PHY such that we can use the
445 * regular SWITCH_MDIO master controller instead.
447 * Here we flag the pseudo PHY as needing special treatment and would
448 * otherwise make all other PHY read/writes go to the master MDIO bus
449 * controller that comes with this switch backed by the "mdio-unimac"
452 if (of_machine_is_compatible("brcm,bcm7445d0"))
453 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
455 priv->indir_phy_mask = 0;
457 ds->phys_mii_mask = priv->indir_phy_mask;
458 ds->slave_mii_bus = priv->slave_mii_bus;
459 priv->slave_mii_bus->parent = ds->dev->parent;
460 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
462 err = of_mdiobus_register(priv->slave_mii_bus, dn);
469 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
471 mdiobus_unregister(priv->slave_mii_bus);
472 of_node_put(priv->master_mii_dn);
475 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
477 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
479 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
480 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
481 * the REG_PHY_REVISION register layout is.
484 return priv->hw_params.gphy_rev;
487 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
488 unsigned long *supported,
489 struct phylink_link_state *state)
491 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
492 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
494 if (!phy_interface_mode_is_rgmii(state->interface) &&
495 state->interface != PHY_INTERFACE_MODE_MII &&
496 state->interface != PHY_INTERFACE_MODE_REVMII &&
497 state->interface != PHY_INTERFACE_MODE_GMII &&
498 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
499 state->interface != PHY_INTERFACE_MODE_MOCA) {
500 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
501 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
503 "Unsupported interface: %d for port %d\n",
504 state->interface, port);
508 /* Allow all the expected bits */
509 phylink_set(mask, Autoneg);
510 phylink_set_port_modes(mask);
511 phylink_set(mask, Pause);
512 phylink_set(mask, Asym_Pause);
514 /* With the exclusion of MII and Reverse MII, we support Gigabit,
515 * including Half duplex
517 if (state->interface != PHY_INTERFACE_MODE_MII &&
518 state->interface != PHY_INTERFACE_MODE_REVMII) {
519 phylink_set(mask, 1000baseT_Full);
520 phylink_set(mask, 1000baseT_Half);
523 phylink_set(mask, 10baseT_Half);
524 phylink_set(mask, 10baseT_Full);
525 phylink_set(mask, 100baseT_Half);
526 phylink_set(mask, 100baseT_Full);
528 bitmap_and(supported, supported, mask,
529 __ETHTOOL_LINK_MODE_MASK_NBITS);
530 bitmap_and(state->advertising, state->advertising, mask,
531 __ETHTOOL_LINK_MODE_MASK_NBITS);
534 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
536 const struct phylink_link_state *state)
538 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
539 u32 id_mode_dis = 0, port_mode;
542 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
545 if (priv->type == BCM7445_DEVICE_ID)
546 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
548 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
550 switch (state->interface) {
551 case PHY_INTERFACE_MODE_RGMII:
554 case PHY_INTERFACE_MODE_RGMII_TXID:
555 port_mode = EXT_GPHY;
557 case PHY_INTERFACE_MODE_MII:
558 port_mode = EXT_EPHY;
560 case PHY_INTERFACE_MODE_REVMII:
561 port_mode = EXT_REVMII;
564 /* all other PHYs: internal and MoCA */
568 /* Clear id_mode_dis bit, and the existing port mode, let
569 * RGMII_MODE_EN bet set by mac_link_{up,down}
571 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
573 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
574 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
580 if (state->pause & MLO_PAUSE_TXRX_MASK) {
581 if (state->pause & MLO_PAUSE_TX)
586 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
589 /* Force link settings detected from the PHY */
591 switch (state->speed) {
593 reg |= SPDSTS_1000 << SPEED_SHIFT;
596 reg |= SPDSTS_100 << SPEED_SHIFT;
602 if (state->duplex == DUPLEX_FULL)
605 core_writel(priv, reg, offset);
608 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
609 phy_interface_t interface, bool link)
611 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
614 if (!phy_interface_mode_is_rgmii(interface) &&
615 interface != PHY_INTERFACE_MODE_MII &&
616 interface != PHY_INTERFACE_MODE_REVMII)
619 /* If the link is down, just disable the interface to conserve power */
620 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
622 reg |= RGMII_MODE_EN;
624 reg &= ~RGMII_MODE_EN;
625 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
628 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
630 phy_interface_t interface)
632 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
635 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
637 phy_interface_t interface,
638 struct phy_device *phydev)
640 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
641 struct ethtool_eee *p = &priv->dev->ports[port].eee;
643 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
645 if (mode == MLO_AN_PHY && phydev)
646 p->eee_enabled = b53_eee_init(ds, port, phydev);
649 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
650 struct phylink_link_state *status)
652 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
654 status->link = false;
656 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
657 * which means that we need to force the link at the port override
658 * level to get the data to flow. We do use what the interrupt handler
659 * did determine before.
661 * For the other ports, we just force the link status, since this is
662 * a fixed PHY device.
664 if (port == priv->moca_port) {
665 status->link = priv->port_sts[port].link;
666 /* For MoCA interfaces, also force a link down notification
667 * since some version of the user-space daemon (mocad) use
668 * cmd->autoneg to force the link, which messes up the PHY
669 * state machine and make it go in PHY_FORCING state instead.
672 netif_carrier_off(dsa_to_port(ds, port)->slave);
673 status->duplex = DUPLEX_FULL;
679 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
681 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
684 /* Enable ACB globally */
685 reg = acb_readl(priv, ACB_CONTROL);
686 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
687 acb_writel(priv, reg, ACB_CONTROL);
688 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
689 reg |= ACB_EN | ACB_ALGORITHM;
690 acb_writel(priv, reg, ACB_CONTROL);
693 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
695 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
698 bcm_sf2_intr_disable(priv);
700 /* Disable all ports physically present including the IMP
701 * port, the other ones have already been disabled during
704 for (port = 0; port < ds->num_ports; port++) {
705 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
706 bcm_sf2_port_disable(ds, port);
712 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
714 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
717 ret = bcm_sf2_sw_rst(priv);
719 pr_err("%s: failed to software reset switch\n", __func__);
723 ret = bcm_sf2_cfp_resume(ds);
727 if (priv->hw_params.num_gphy == 1)
728 bcm_sf2_gphy_enable_set(ds, true);
735 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
736 struct ethtool_wolinfo *wol)
738 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
739 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
740 struct ethtool_wolinfo pwol = { };
742 /* Get the parent device WoL settings */
743 if (p->ethtool_ops->get_wol)
744 p->ethtool_ops->get_wol(p, &pwol);
746 /* Advertise the parent device supported settings */
747 wol->supported = pwol.supported;
748 memset(&wol->sopass, 0, sizeof(wol->sopass));
750 if (pwol.wolopts & WAKE_MAGICSECURE)
751 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
753 if (priv->wol_ports_mask & (1 << port))
754 wol->wolopts = pwol.wolopts;
759 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
760 struct ethtool_wolinfo *wol)
762 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
763 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
764 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
765 struct ethtool_wolinfo pwol = { };
767 if (p->ethtool_ops->get_wol)
768 p->ethtool_ops->get_wol(p, &pwol);
769 if (wol->wolopts & ~pwol.supported)
773 priv->wol_ports_mask |= (1 << port);
775 priv->wol_ports_mask &= ~(1 << port);
777 /* If we have at least one port enabled, make sure the CPU port
778 * is also enabled. If the CPU port is the last one enabled, we disable
779 * it since this configuration does not make sense.
781 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
782 priv->wol_ports_mask |= (1 << cpu_port);
784 priv->wol_ports_mask &= ~(1 << cpu_port);
786 return p->ethtool_ops->set_wol(p, wol);
789 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
791 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
794 /* Enable all valid ports and disable those unused */
795 for (port = 0; port < priv->hw_params.num_ports; port++) {
796 /* IMP port receives special treatment */
797 if (dsa_is_user_port(ds, port))
798 bcm_sf2_port_setup(ds, port, NULL);
799 else if (dsa_is_cpu_port(ds, port))
800 bcm_sf2_imp_setup(ds, port);
802 bcm_sf2_port_disable(ds, port);
805 b53_configure_vlan(ds);
806 bcm_sf2_enable_acb(ds);
811 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
812 * register basis so we need to translate that into an address that the
813 * bus-glue understands.
815 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
817 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
820 struct bcm_sf2_priv *priv = dev->priv;
822 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
827 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
830 struct bcm_sf2_priv *priv = dev->priv;
832 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
837 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
840 struct bcm_sf2_priv *priv = dev->priv;
842 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
847 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
850 struct bcm_sf2_priv *priv = dev->priv;
852 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
857 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
860 struct bcm_sf2_priv *priv = dev->priv;
862 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
867 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
870 struct bcm_sf2_priv *priv = dev->priv;
872 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
877 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
880 struct bcm_sf2_priv *priv = dev->priv;
882 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
887 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
890 struct bcm_sf2_priv *priv = dev->priv;
892 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
897 static const struct b53_io_ops bcm_sf2_io_ops = {
898 .read8 = bcm_sf2_core_read8,
899 .read16 = bcm_sf2_core_read16,
900 .read32 = bcm_sf2_core_read32,
901 .read48 = bcm_sf2_core_read64,
902 .read64 = bcm_sf2_core_read64,
903 .write8 = bcm_sf2_core_write8,
904 .write16 = bcm_sf2_core_write16,
905 .write32 = bcm_sf2_core_write32,
906 .write48 = bcm_sf2_core_write64,
907 .write64 = bcm_sf2_core_write64,
910 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
911 u32 stringset, uint8_t *data)
913 int cnt = b53_get_sset_count(ds, port, stringset);
915 b53_get_strings(ds, port, stringset, data);
916 bcm_sf2_cfp_get_strings(ds, port, stringset,
917 data + cnt * ETH_GSTRING_LEN);
920 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
923 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
925 b53_get_ethtool_stats(ds, port, data);
926 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
929 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
932 int cnt = b53_get_sset_count(ds, port, sset);
937 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
942 static const struct dsa_switch_ops bcm_sf2_ops = {
943 .get_tag_protocol = b53_get_tag_protocol,
944 .setup = bcm_sf2_sw_setup,
945 .get_strings = bcm_sf2_sw_get_strings,
946 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
947 .get_sset_count = bcm_sf2_sw_get_sset_count,
948 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
949 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
950 .phylink_validate = bcm_sf2_sw_validate,
951 .phylink_mac_config = bcm_sf2_sw_mac_config,
952 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
953 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
954 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
955 .suspend = bcm_sf2_sw_suspend,
956 .resume = bcm_sf2_sw_resume,
957 .get_wol = bcm_sf2_sw_get_wol,
958 .set_wol = bcm_sf2_sw_set_wol,
959 .port_enable = bcm_sf2_port_setup,
960 .port_disable = bcm_sf2_port_disable,
961 .get_mac_eee = b53_get_mac_eee,
962 .set_mac_eee = b53_set_mac_eee,
963 .port_bridge_join = b53_br_join,
964 .port_bridge_leave = b53_br_leave,
965 .port_stp_state_set = b53_br_set_stp_state,
966 .port_fast_age = b53_br_fast_age,
967 .port_vlan_filtering = b53_vlan_filtering,
968 .port_vlan_prepare = b53_vlan_prepare,
969 .port_vlan_add = b53_vlan_add,
970 .port_vlan_del = b53_vlan_del,
971 .port_fdb_dump = b53_fdb_dump,
972 .port_fdb_add = b53_fdb_add,
973 .port_fdb_del = b53_fdb_del,
974 .get_rxnfc = bcm_sf2_get_rxnfc,
975 .set_rxnfc = bcm_sf2_set_rxnfc,
976 .port_mirror_add = b53_mirror_add,
977 .port_mirror_del = b53_mirror_del,
978 .port_mdb_prepare = b53_mdb_prepare,
979 .port_mdb_add = b53_mdb_add,
980 .port_mdb_del = b53_mdb_del,
983 struct bcm_sf2_of_data {
985 const u16 *reg_offsets;
986 unsigned int core_reg_align;
987 unsigned int num_cfp_rules;
990 /* Register offsets for the SWITCH_REG_* block */
991 static const u16 bcm_sf2_7445_reg_offsets[] = {
992 [REG_SWITCH_CNTRL] = 0x00,
993 [REG_SWITCH_STATUS] = 0x04,
994 [REG_DIR_DATA_WRITE] = 0x08,
995 [REG_DIR_DATA_READ] = 0x0C,
996 [REG_SWITCH_REVISION] = 0x18,
997 [REG_PHY_REVISION] = 0x1C,
998 [REG_SPHY_CNTRL] = 0x2C,
999 [REG_RGMII_0_CNTRL] = 0x34,
1000 [REG_RGMII_1_CNTRL] = 0x40,
1001 [REG_RGMII_2_CNTRL] = 0x4c,
1002 [REG_LED_0_CNTRL] = 0x90,
1003 [REG_LED_1_CNTRL] = 0x94,
1004 [REG_LED_2_CNTRL] = 0x98,
1007 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1008 .type = BCM7445_DEVICE_ID,
1009 .core_reg_align = 0,
1010 .reg_offsets = bcm_sf2_7445_reg_offsets,
1011 .num_cfp_rules = 256,
1014 static const u16 bcm_sf2_7278_reg_offsets[] = {
1015 [REG_SWITCH_CNTRL] = 0x00,
1016 [REG_SWITCH_STATUS] = 0x04,
1017 [REG_DIR_DATA_WRITE] = 0x08,
1018 [REG_DIR_DATA_READ] = 0x0c,
1019 [REG_SWITCH_REVISION] = 0x10,
1020 [REG_PHY_REVISION] = 0x14,
1021 [REG_SPHY_CNTRL] = 0x24,
1022 [REG_RGMII_0_CNTRL] = 0xe0,
1023 [REG_RGMII_1_CNTRL] = 0xec,
1024 [REG_RGMII_2_CNTRL] = 0xf8,
1025 [REG_LED_0_CNTRL] = 0x40,
1026 [REG_LED_1_CNTRL] = 0x4c,
1027 [REG_LED_2_CNTRL] = 0x58,
1030 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1031 .type = BCM7278_DEVICE_ID,
1032 .core_reg_align = 1,
1033 .reg_offsets = bcm_sf2_7278_reg_offsets,
1034 .num_cfp_rules = 128,
1037 static const struct of_device_id bcm_sf2_of_match[] = {
1038 { .compatible = "brcm,bcm7445-switch-v4.0",
1039 .data = &bcm_sf2_7445_data
1041 { .compatible = "brcm,bcm7278-switch-v4.0",
1042 .data = &bcm_sf2_7278_data
1044 { .compatible = "brcm,bcm7278-switch-v4.8",
1045 .data = &bcm_sf2_7278_data
1049 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1051 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1053 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1054 struct device_node *dn = pdev->dev.of_node;
1055 const struct of_device_id *of_id = NULL;
1056 const struct bcm_sf2_of_data *data;
1057 struct b53_platform_data *pdata;
1058 struct dsa_switch_ops *ops;
1059 struct bcm_sf2_priv *priv;
1060 struct b53_device *dev;
1061 struct dsa_switch *ds;
1062 void __iomem **base;
1067 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1071 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1075 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1079 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1083 of_id = of_match_node(bcm_sf2_of_match, dn);
1084 if (!of_id || !of_id->data)
1089 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1090 priv->type = data->type;
1091 priv->reg_offsets = data->reg_offsets;
1092 priv->core_reg_align = data->core_reg_align;
1093 priv->num_cfp_rules = data->num_cfp_rules;
1095 /* Auto-detection using standard registers will not work, so
1096 * provide an indication of what kind of device we are for
1097 * b53_common to work with
1099 pdata->chip_id = priv->type;
1104 ds->ops = &bcm_sf2_ops;
1106 /* Advertise the 8 egress queues */
1107 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1109 dev_set_drvdata(&pdev->dev, priv);
1111 spin_lock_init(&priv->indir_lock);
1112 mutex_init(&priv->cfp.lock);
1113 INIT_LIST_HEAD(&priv->cfp.rules_list);
1115 /* CFP rule #0 cannot be used for specific classifications, flag it as
1118 set_bit(0, priv->cfp.used);
1119 set_bit(0, priv->cfp.unique);
1121 bcm_sf2_identify_ports(priv, dn->child);
1123 priv->irq0 = irq_of_parse_and_map(dn, 0);
1124 priv->irq1 = irq_of_parse_and_map(dn, 1);
1127 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1128 *base = devm_platform_ioremap_resource(pdev, i);
1129 if (IS_ERR(*base)) {
1130 pr_err("unable to find register: %s\n", reg_names[i]);
1131 return PTR_ERR(*base);
1136 ret = bcm_sf2_sw_rst(priv);
1138 pr_err("unable to software reset switch: %d\n", ret);
1142 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1144 ret = bcm_sf2_mdio_register(ds);
1146 pr_err("failed to register MDIO bus\n");
1150 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1152 ret = bcm_sf2_cfp_rst(priv);
1154 pr_err("failed to reset CFP\n");
1158 /* Disable all interrupts and request them */
1159 bcm_sf2_intr_disable(priv);
1161 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1164 pr_err("failed to request switch_0 IRQ\n");
1168 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1171 pr_err("failed to request switch_1 IRQ\n");
1175 /* Reset the MIB counters */
1176 reg = core_readl(priv, CORE_GMNCFGCFG);
1178 core_writel(priv, reg, CORE_GMNCFGCFG);
1179 reg &= ~RST_MIB_CNT;
1180 core_writel(priv, reg, CORE_GMNCFGCFG);
1182 /* Get the maximum number of ports for this switch */
1183 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1184 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1185 priv->hw_params.num_ports = DSA_MAX_PORTS;
1187 /* Assume a single GPHY setup if we can't read that property */
1188 if (of_property_read_u32(dn, "brcm,num-gphy",
1189 &priv->hw_params.num_gphy))
1190 priv->hw_params.num_gphy = 1;
1192 rev = reg_readl(priv, REG_SWITCH_REVISION);
1193 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1194 SWITCH_TOP_REV_MASK;
1195 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1197 rev = reg_readl(priv, REG_PHY_REVISION);
1198 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1200 ret = b53_switch_register(dev);
1204 dev_info(&pdev->dev,
1205 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1206 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1207 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1208 priv->irq0, priv->irq1);
1213 bcm_sf2_mdio_unregister(priv);
1217 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1219 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1221 priv->wol_ports_mask = 0;
1222 dsa_unregister_switch(priv->dev->ds);
1223 bcm_sf2_cfp_exit(priv->dev->ds);
1224 /* Disable all ports and interrupts */
1225 bcm_sf2_sw_suspend(priv->dev->ds);
1226 bcm_sf2_mdio_unregister(priv);
1231 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1233 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1235 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1236 * successful MDIO bus scan to occur. If we did turn off the GPHY
1237 * before (e.g: port_disable), this will also power it back on.
1239 * Do not rely on kexec_in_progress, just power the PHY on.
1241 if (priv->hw_params.num_gphy == 1)
1242 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1245 #ifdef CONFIG_PM_SLEEP
1246 static int bcm_sf2_suspend(struct device *dev)
1248 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1250 return dsa_switch_suspend(priv->dev->ds);
1253 static int bcm_sf2_resume(struct device *dev)
1255 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1257 return dsa_switch_resume(priv->dev->ds);
1259 #endif /* CONFIG_PM_SLEEP */
1261 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1262 bcm_sf2_suspend, bcm_sf2_resume);
1265 static struct platform_driver bcm_sf2_driver = {
1266 .probe = bcm_sf2_sw_probe,
1267 .remove = bcm_sf2_sw_remove,
1268 .shutdown = bcm_sf2_sw_shutdown,
1271 .of_match_table = bcm_sf2_of_match,
1272 .pm = &bcm_sf2_pm_ops,
1275 module_platform_driver(bcm_sf2_driver);
1277 MODULE_AUTHOR("Broadcom Corporation");
1278 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1279 MODULE_LICENSE("GPL");
1280 MODULE_ALIAS("platform:brcm-sf2");