2 * Broadcom Starfighter 2 DSA switch driver
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
27 #include <linux/ethtool.h>
28 #include <linux/if_bridge.h>
29 #include <linux/brcmphy.h>
30 #include <linux/etherdevice.h>
31 #include <linux/platform_data/b53.h>
34 #include "bcm_sf2_regs.h"
35 #include "b53/b53_priv.h"
36 #include "b53/b53_regs.h"
38 static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds)
40 return DSA_TAG_PROTO_BRCM;
43 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
45 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
49 /* Enable the IMP Port to be in the same VLAN as the other ports
50 * on a per-port basis such that we only have Port i and IMP in
53 for (i = 0; i < priv->hw_params.num_ports; i++) {
54 if (!((1 << i) & ds->enabled_port_mask))
57 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
58 reg |= (1 << cpu_port);
59 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
63 static void bcm_sf2_brcm_hdr_setup(struct bcm_sf2_priv *priv, int port)
67 /* Resolve which bit controls the Broadcom tag */
83 /* Enable Broadcom tags for IMP port */
84 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
86 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
88 /* Enable reception Broadcom tag for CPU TX (switch RX) to
89 * allow us to tag outgoing frames
91 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
93 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
95 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
96 * allow delivering frames to the per-port net_devices
98 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
100 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
103 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
105 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
108 if (priv->type == BCM7445_DEVICE_ID)
109 offset = CORE_STS_OVERRIDE_IMP;
111 offset = CORE_STS_OVERRIDE_IMP2;
113 /* Enable the port memories */
114 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
115 reg &= ~P_TXQ_PSM_VDD(port);
116 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
118 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
119 reg = core_readl(priv, CORE_IMP_CTL);
120 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
121 reg &= ~(RX_DIS | TX_DIS);
122 core_writel(priv, reg, CORE_IMP_CTL);
124 /* Enable forwarding */
125 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
127 /* Enable IMP port in dumb mode */
128 reg = core_readl(priv, CORE_SWITCH_CTRL);
129 reg |= MII_DUMB_FWDG_EN;
130 core_writel(priv, reg, CORE_SWITCH_CTRL);
132 bcm_sf2_brcm_hdr_setup(priv, port);
134 /* Force link status for IMP port */
135 reg = core_readl(priv, offset);
136 reg |= (MII_SW_OR | LINK_STS);
137 core_writel(priv, reg, offset);
140 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
142 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
145 reg = core_readl(priv, CORE_EEE_EN_CTRL);
150 core_writel(priv, reg, CORE_EEE_EN_CTRL);
153 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
155 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
158 reg = reg_readl(priv, REG_SPHY_CNTRL);
161 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
162 reg_writel(priv, reg, REG_SPHY_CNTRL);
164 reg = reg_readl(priv, REG_SPHY_CNTRL);
167 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
168 reg_writel(priv, reg, REG_SPHY_CNTRL);
172 reg_writel(priv, reg, REG_SPHY_CNTRL);
174 /* Use PHY-driven LED signaling */
176 reg = reg_readl(priv, REG_LED_CNTRL(0));
177 reg |= SPDLNK_SRC_SEL;
178 reg_writel(priv, reg, REG_LED_CNTRL(0));
182 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
192 /* Port 0 interrupts are located on the first bank */
193 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
196 off = P_IRQ_OFF(port);
200 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
203 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
213 /* Port 0 interrupts are located on the first bank */
214 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
215 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
218 off = P_IRQ_OFF(port);
222 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
223 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
226 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
227 struct phy_device *phy)
229 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
230 s8 cpu_port = ds->dst->cpu_dp->index;
234 /* Clear the memory power down */
235 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
236 reg &= ~P_TXQ_PSM_VDD(port);
237 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
239 /* Enable Broadcom tags for that port if requested */
240 if (priv->brcm_tag_mask & BIT(port))
241 bcm_sf2_brcm_hdr_setup(priv, port);
243 /* Configure Traffic Class to QoS mapping, allow each priority to map
244 * to a different queue number
246 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
247 for (i = 0; i < 8; i++)
248 reg |= i << (PRT_TO_QID_SHIFT * i);
249 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
251 /* Clear the Rx and Tx disable bits and set to no spanning tree */
252 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
254 /* Re-enable the GPHY and re-apply workarounds */
255 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
256 bcm_sf2_gphy_enable_set(ds, true);
258 /* if phy_stop() has been called before, phy
259 * will be in halted state, and phy_start()
262 * the resume path does not configure back
263 * autoneg settings, and since we hard reset
264 * the phy manually here, we need to reset the
265 * state machine also.
267 phy->state = PHY_READY;
272 /* Enable MoCA port interrupts to get notified */
273 if (port == priv->moca_port)
274 bcm_sf2_port_intr_enable(priv, port);
276 /* Set this port, and only this one to be in the default VLAN,
277 * if member of a bridge, restore its membership prior to
278 * bringing down this port.
280 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
281 reg &= ~PORT_VLAN_CTRL_MASK;
283 reg |= priv->dev->ports[port].vlan_ctl_mask;
284 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
286 bcm_sf2_imp_vlan_setup(ds, cpu_port);
288 /* If EEE was enabled, restore it */
289 if (priv->port_sts[port].eee.eee_enabled)
290 bcm_sf2_eee_enable_set(ds, port, true);
295 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
296 struct phy_device *phy)
298 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
301 if (priv->wol_ports_mask & (1 << port))
304 if (port == priv->moca_port)
305 bcm_sf2_port_intr_disable(priv, port);
307 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
308 bcm_sf2_gphy_enable_set(ds, false);
310 if (dsa_is_cpu_port(ds, port))
313 off = CORE_G_PCTL_PORT(port);
315 reg = core_readl(priv, off);
316 reg |= RX_DIS | TX_DIS;
317 core_writel(priv, reg, off);
319 /* Power down the port memory */
320 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
321 reg |= P_TXQ_PSM_VDD(port);
322 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
325 /* Returns 0 if EEE was not enabled, or 1 otherwise
327 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
328 struct phy_device *phy)
332 ret = phy_init_eee(phy, 0);
336 bcm_sf2_eee_enable_set(ds, port, true);
341 static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
342 struct ethtool_eee *e)
344 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
345 struct ethtool_eee *p = &priv->port_sts[port].eee;
348 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
349 e->eee_enabled = p->eee_enabled;
350 e->eee_active = !!(reg & (1 << port));
355 static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
356 struct phy_device *phydev,
357 struct ethtool_eee *e)
359 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
360 struct ethtool_eee *p = &priv->port_sts[port].eee;
362 p->eee_enabled = e->eee_enabled;
363 bcm_sf2_eee_enable_set(ds, port, e->eee_enabled);
368 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
374 reg = reg_readl(priv, REG_SWITCH_CNTRL);
375 reg |= MDIO_MASTER_SEL;
376 reg_writel(priv, reg, REG_SWITCH_CNTRL);
378 /* Page << 8 | offset */
381 core_writel(priv, addr, reg);
383 /* Page << 8 | offset */
384 reg = 0x80 << 8 | regnum << 1;
388 ret = core_readl(priv, reg);
390 core_writel(priv, val, reg);
392 reg = reg_readl(priv, REG_SWITCH_CNTRL);
393 reg &= ~MDIO_MASTER_SEL;
394 reg_writel(priv, reg, REG_SWITCH_CNTRL);
399 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
401 struct bcm_sf2_priv *priv = bus->priv;
403 /* Intercept reads from Broadcom pseudo-PHY address, else, send
404 * them to our master MDIO bus controller
406 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
407 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
409 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
412 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
415 struct bcm_sf2_priv *priv = bus->priv;
417 /* Intercept writes to the Broadcom pseudo-PHY address, else,
418 * send them to our master MDIO bus controller
420 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
421 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
423 mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val);
428 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
430 struct bcm_sf2_priv *priv = dev_id;
432 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
434 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
439 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
441 struct bcm_sf2_priv *priv = dev_id;
443 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
445 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
447 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
448 priv->port_sts[7].link = 1;
449 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
450 priv->port_sts[7].link = 0;
455 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
457 unsigned int timeout = 1000;
460 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
461 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
462 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
465 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
466 if (!(reg & SOFTWARE_RESET))
469 usleep_range(1000, 2000);
470 } while (timeout-- > 0);
478 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
480 intrl2_0_mask_set(priv, 0xffffffff);
481 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
482 intrl2_1_mask_set(priv, 0xffffffff);
483 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
486 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
487 struct device_node *dn)
489 struct device_node *port;
491 unsigned int port_num;
493 priv->moca_port = -1;
495 for_each_available_child_of_node(dn, port) {
496 if (of_property_read_u32(port, "reg", &port_num))
499 /* Internal PHYs get assigned a specific 'phy-mode' property
500 * value: "internal" to help flag them before MDIO probing
501 * has completed, since they might be turned off at that
504 mode = of_get_phy_mode(port);
508 if (mode == PHY_INTERFACE_MODE_INTERNAL)
509 priv->int_phy_mask |= 1 << port_num;
511 if (mode == PHY_INTERFACE_MODE_MOCA)
512 priv->moca_port = port_num;
514 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
515 priv->brcm_tag_mask |= 1 << port_num;
519 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
521 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
522 struct device_node *dn;
526 /* Find our integrated MDIO bus node */
527 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
528 priv->master_mii_bus = of_mdio_find_bus(dn);
529 if (!priv->master_mii_bus)
530 return -EPROBE_DEFER;
532 get_device(&priv->master_mii_bus->dev);
533 priv->master_mii_dn = dn;
535 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
536 if (!priv->slave_mii_bus)
539 priv->slave_mii_bus->priv = priv;
540 priv->slave_mii_bus->name = "sf2 slave mii";
541 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
542 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
543 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
545 priv->slave_mii_bus->dev.of_node = dn;
547 /* Include the pseudo-PHY address to divert reads towards our
548 * workaround. This is only required for 7445D0, since 7445E0
549 * disconnects the internal switch pseudo-PHY such that we can use the
550 * regular SWITCH_MDIO master controller instead.
552 * Here we flag the pseudo PHY as needing special treatment and would
553 * otherwise make all other PHY read/writes go to the master MDIO bus
554 * controller that comes with this switch backed by the "mdio-unimac"
557 if (of_machine_is_compatible("brcm,bcm7445d0"))
558 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
560 priv->indir_phy_mask = 0;
562 ds->phys_mii_mask = priv->indir_phy_mask;
563 ds->slave_mii_bus = priv->slave_mii_bus;
564 priv->slave_mii_bus->parent = ds->dev->parent;
565 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
568 err = of_mdiobus_register(priv->slave_mii_bus, dn);
570 err = mdiobus_register(priv->slave_mii_bus);
578 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
580 mdiobus_unregister(priv->slave_mii_bus);
581 if (priv->master_mii_dn)
582 of_node_put(priv->master_mii_dn);
585 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
587 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
589 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
590 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
591 * the REG_PHY_REVISION register layout is.
594 return priv->hw_params.gphy_rev;
597 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
598 struct phy_device *phydev)
600 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
601 struct ethtool_eee *p = &priv->port_sts[port].eee;
602 u32 id_mode_dis = 0, port_mode;
603 const char *str = NULL;
606 if (priv->type == BCM7445_DEVICE_ID)
607 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
609 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
611 switch (phydev->interface) {
612 case PHY_INTERFACE_MODE_RGMII:
613 str = "RGMII (no delay)";
615 case PHY_INTERFACE_MODE_RGMII_TXID:
617 str = "RGMII (TX delay)";
618 port_mode = EXT_GPHY;
620 case PHY_INTERFACE_MODE_MII:
622 port_mode = EXT_EPHY;
624 case PHY_INTERFACE_MODE_REVMII:
626 port_mode = EXT_REVMII;
629 /* All other PHYs: internal and MoCA */
633 /* If the link is down, just disable the interface to conserve power */
635 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
636 reg &= ~RGMII_MODE_EN;
637 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
641 /* Clear id_mode_dis bit, and the existing port mode, but
642 * make sure we enable the RGMII block for data to pass
644 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
646 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
647 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
649 reg |= port_mode | RGMII_MODE_EN;
654 if (phydev->asym_pause)
659 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
661 pr_info("Port %d configured for %s\n", port, str);
664 /* Force link settings detected from the PHY */
666 switch (phydev->speed) {
668 reg |= SPDSTS_1000 << SPEED_SHIFT;
671 reg |= SPDSTS_100 << SPEED_SHIFT;
677 if (phydev->duplex == DUPLEX_FULL)
680 core_writel(priv, reg, offset);
682 if (!phydev->is_pseudo_fixed_link)
683 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
686 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
687 struct fixed_phy_status *status)
689 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
690 u32 duplex, pause, offset;
693 if (priv->type == BCM7445_DEVICE_ID)
694 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
696 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
698 duplex = core_readl(priv, CORE_DUPSTS);
699 pause = core_readl(priv, CORE_PAUSESTS);
703 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
704 * which means that we need to force the link at the port override
705 * level to get the data to flow. We do use what the interrupt handler
706 * did determine before.
708 * For the other ports, we just force the link status, since this is
709 * a fixed PHY device.
711 if (port == priv->moca_port) {
712 status->link = priv->port_sts[port].link;
713 /* For MoCA interfaces, also force a link down notification
714 * since some version of the user-space daemon (mocad) use
715 * cmd->autoneg to force the link, which messes up the PHY
716 * state machine and make it go in PHY_FORCING state instead.
719 netif_carrier_off(ds->ports[port].netdev);
723 status->duplex = !!(duplex & (1 << port));
726 reg = core_readl(priv, offset);
732 core_writel(priv, reg, offset);
734 if ((pause & (1 << port)) &&
735 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
736 status->asym_pause = 1;
740 if (pause & (1 << port))
744 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
746 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
749 bcm_sf2_intr_disable(priv);
751 /* Disable all ports physically present including the IMP
752 * port, the other ones have already been disabled during
755 for (port = 0; port < DSA_MAX_PORTS; port++) {
756 if ((1 << port) & ds->enabled_port_mask ||
757 dsa_is_cpu_port(ds, port))
758 bcm_sf2_port_disable(ds, port, NULL);
764 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
766 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
770 ret = bcm_sf2_sw_rst(priv);
772 pr_err("%s: failed to software reset switch\n", __func__);
776 if (priv->hw_params.num_gphy == 1)
777 bcm_sf2_gphy_enable_set(ds, true);
779 for (port = 0; port < DSA_MAX_PORTS; port++) {
780 if ((1 << port) & ds->enabled_port_mask)
781 bcm_sf2_port_setup(ds, port, NULL);
782 else if (dsa_is_cpu_port(ds, port))
783 bcm_sf2_imp_setup(ds, port);
789 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
790 struct ethtool_wolinfo *wol)
792 struct net_device *p = ds->dst[ds->index].cpu_dp->netdev;
793 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
794 struct ethtool_wolinfo pwol;
796 /* Get the parent device WoL settings */
797 p->ethtool_ops->get_wol(p, &pwol);
799 /* Advertise the parent device supported settings */
800 wol->supported = pwol.supported;
801 memset(&wol->sopass, 0, sizeof(wol->sopass));
803 if (pwol.wolopts & WAKE_MAGICSECURE)
804 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
806 if (priv->wol_ports_mask & (1 << port))
807 wol->wolopts = pwol.wolopts;
812 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
813 struct ethtool_wolinfo *wol)
815 struct net_device *p = ds->dst[ds->index].cpu_dp->netdev;
816 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
817 s8 cpu_port = ds->dst->cpu_dp->index;
818 struct ethtool_wolinfo pwol;
820 p->ethtool_ops->get_wol(p, &pwol);
821 if (wol->wolopts & ~pwol.supported)
825 priv->wol_ports_mask |= (1 << port);
827 priv->wol_ports_mask &= ~(1 << port);
829 /* If we have at least one port enabled, make sure the CPU port
830 * is also enabled. If the CPU port is the last one enabled, we disable
831 * it since this configuration does not make sense.
833 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
834 priv->wol_ports_mask |= (1 << cpu_port);
836 priv->wol_ports_mask &= ~(1 << cpu_port);
838 return p->ethtool_ops->set_wol(p, wol);
841 static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)
843 unsigned int timeout = 10;
847 reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);
848 if (!(reg & ARLA_VTBL_STDN))
851 usleep_range(1000, 2000);
857 static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)
859 core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);
861 return bcm_sf2_vlan_op_wait(priv);
864 static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)
866 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
869 /* Clear all VLANs */
870 bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);
872 for (port = 0; port < priv->hw_params.num_ports; port++) {
873 if (!((1 << port) & ds->enabled_port_mask))
876 core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));
880 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
882 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
885 /* Enable all valid ports and disable those unused */
886 for (port = 0; port < priv->hw_params.num_ports; port++) {
887 /* IMP port receives special treatment */
888 if ((1 << port) & ds->enabled_port_mask)
889 bcm_sf2_port_setup(ds, port, NULL);
890 else if (dsa_is_cpu_port(ds, port))
891 bcm_sf2_imp_setup(ds, port);
893 bcm_sf2_port_disable(ds, port, NULL);
896 bcm_sf2_sw_configure_vlan(ds);
901 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
902 * register basis so we need to translate that into an address that the
903 * bus-glue understands.
905 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
907 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
910 struct bcm_sf2_priv *priv = dev->priv;
912 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
917 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
920 struct bcm_sf2_priv *priv = dev->priv;
922 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
927 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
930 struct bcm_sf2_priv *priv = dev->priv;
932 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
937 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
940 struct bcm_sf2_priv *priv = dev->priv;
942 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
947 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
950 struct bcm_sf2_priv *priv = dev->priv;
952 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
957 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
960 struct bcm_sf2_priv *priv = dev->priv;
962 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
967 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
970 struct bcm_sf2_priv *priv = dev->priv;
972 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
977 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
980 struct bcm_sf2_priv *priv = dev->priv;
982 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
987 static struct b53_io_ops bcm_sf2_io_ops = {
988 .read8 = bcm_sf2_core_read8,
989 .read16 = bcm_sf2_core_read16,
990 .read32 = bcm_sf2_core_read32,
991 .read48 = bcm_sf2_core_read64,
992 .read64 = bcm_sf2_core_read64,
993 .write8 = bcm_sf2_core_write8,
994 .write16 = bcm_sf2_core_write16,
995 .write32 = bcm_sf2_core_write32,
996 .write48 = bcm_sf2_core_write64,
997 .write64 = bcm_sf2_core_write64,
1000 static const struct dsa_switch_ops bcm_sf2_ops = {
1001 .get_tag_protocol = bcm_sf2_sw_get_tag_protocol,
1002 .setup = bcm_sf2_sw_setup,
1003 .get_strings = b53_get_strings,
1004 .get_ethtool_stats = b53_get_ethtool_stats,
1005 .get_sset_count = b53_get_sset_count,
1006 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1007 .adjust_link = bcm_sf2_sw_adjust_link,
1008 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
1009 .suspend = bcm_sf2_sw_suspend,
1010 .resume = bcm_sf2_sw_resume,
1011 .get_wol = bcm_sf2_sw_get_wol,
1012 .set_wol = bcm_sf2_sw_set_wol,
1013 .port_enable = bcm_sf2_port_setup,
1014 .port_disable = bcm_sf2_port_disable,
1015 .get_eee = bcm_sf2_sw_get_eee,
1016 .set_eee = bcm_sf2_sw_set_eee,
1017 .port_bridge_join = b53_br_join,
1018 .port_bridge_leave = b53_br_leave,
1019 .port_stp_state_set = b53_br_set_stp_state,
1020 .port_fast_age = b53_br_fast_age,
1021 .port_vlan_filtering = b53_vlan_filtering,
1022 .port_vlan_prepare = b53_vlan_prepare,
1023 .port_vlan_add = b53_vlan_add,
1024 .port_vlan_del = b53_vlan_del,
1025 .port_vlan_dump = b53_vlan_dump,
1026 .port_fdb_prepare = b53_fdb_prepare,
1027 .port_fdb_dump = b53_fdb_dump,
1028 .port_fdb_add = b53_fdb_add,
1029 .port_fdb_del = b53_fdb_del,
1030 .get_rxnfc = bcm_sf2_get_rxnfc,
1031 .set_rxnfc = bcm_sf2_set_rxnfc,
1032 .port_mirror_add = b53_mirror_add,
1033 .port_mirror_del = b53_mirror_del,
1036 struct bcm_sf2_of_data {
1038 const u16 *reg_offsets;
1039 unsigned int core_reg_align;
1042 /* Register offsets for the SWITCH_REG_* block */
1043 static const u16 bcm_sf2_7445_reg_offsets[] = {
1044 [REG_SWITCH_CNTRL] = 0x00,
1045 [REG_SWITCH_STATUS] = 0x04,
1046 [REG_DIR_DATA_WRITE] = 0x08,
1047 [REG_DIR_DATA_READ] = 0x0C,
1048 [REG_SWITCH_REVISION] = 0x18,
1049 [REG_PHY_REVISION] = 0x1C,
1050 [REG_SPHY_CNTRL] = 0x2C,
1051 [REG_RGMII_0_CNTRL] = 0x34,
1052 [REG_RGMII_1_CNTRL] = 0x40,
1053 [REG_RGMII_2_CNTRL] = 0x4c,
1054 [REG_LED_0_CNTRL] = 0x90,
1055 [REG_LED_1_CNTRL] = 0x94,
1056 [REG_LED_2_CNTRL] = 0x98,
1059 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1060 .type = BCM7445_DEVICE_ID,
1061 .core_reg_align = 0,
1062 .reg_offsets = bcm_sf2_7445_reg_offsets,
1065 static const u16 bcm_sf2_7278_reg_offsets[] = {
1066 [REG_SWITCH_CNTRL] = 0x00,
1067 [REG_SWITCH_STATUS] = 0x04,
1068 [REG_DIR_DATA_WRITE] = 0x08,
1069 [REG_DIR_DATA_READ] = 0x0c,
1070 [REG_SWITCH_REVISION] = 0x10,
1071 [REG_PHY_REVISION] = 0x14,
1072 [REG_SPHY_CNTRL] = 0x24,
1073 [REG_RGMII_0_CNTRL] = 0xe0,
1074 [REG_RGMII_1_CNTRL] = 0xec,
1075 [REG_RGMII_2_CNTRL] = 0xf8,
1076 [REG_LED_0_CNTRL] = 0x40,
1077 [REG_LED_1_CNTRL] = 0x4c,
1078 [REG_LED_2_CNTRL] = 0x58,
1081 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1082 .type = BCM7278_DEVICE_ID,
1083 .core_reg_align = 1,
1084 .reg_offsets = bcm_sf2_7278_reg_offsets,
1087 static const struct of_device_id bcm_sf2_of_match[] = {
1088 { .compatible = "brcm,bcm7445-switch-v4.0",
1089 .data = &bcm_sf2_7445_data
1091 { .compatible = "brcm,bcm7278-switch-v4.0",
1092 .data = &bcm_sf2_7278_data
1096 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1098 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1100 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1101 struct device_node *dn = pdev->dev.of_node;
1102 const struct of_device_id *of_id = NULL;
1103 const struct bcm_sf2_of_data *data;
1104 struct b53_platform_data *pdata;
1105 struct dsa_switch_ops *ops;
1106 struct bcm_sf2_priv *priv;
1107 struct b53_device *dev;
1108 struct dsa_switch *ds;
1109 void __iomem **base;
1115 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1119 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1123 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1127 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1131 of_id = of_match_node(bcm_sf2_of_match, dn);
1132 if (!of_id || !of_id->data)
1137 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1138 priv->type = data->type;
1139 priv->reg_offsets = data->reg_offsets;
1140 priv->core_reg_align = data->core_reg_align;
1142 /* Auto-detection using standard registers will not work, so
1143 * provide an indication of what kind of device we are for
1144 * b53_common to work with
1146 pdata->chip_id = priv->type;
1151 ds->ops = &bcm_sf2_ops;
1153 dev_set_drvdata(&pdev->dev, priv);
1155 spin_lock_init(&priv->indir_lock);
1156 mutex_init(&priv->stats_mutex);
1157 mutex_init(&priv->cfp.lock);
1159 /* CFP rule #0 cannot be used for specific classifications, flag it as
1162 set_bit(0, priv->cfp.used);
1164 bcm_sf2_identify_ports(priv, dn->child);
1166 priv->irq0 = irq_of_parse_and_map(dn, 0);
1167 priv->irq1 = irq_of_parse_and_map(dn, 1);
1170 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1171 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1172 *base = devm_ioremap_resource(&pdev->dev, r);
1173 if (IS_ERR(*base)) {
1174 pr_err("unable to find register: %s\n", reg_names[i]);
1175 return PTR_ERR(*base);
1180 ret = bcm_sf2_sw_rst(priv);
1182 pr_err("unable to software reset switch: %d\n", ret);
1186 ret = bcm_sf2_mdio_register(ds);
1188 pr_err("failed to register MDIO bus\n");
1192 ret = bcm_sf2_cfp_rst(priv);
1194 pr_err("failed to reset CFP\n");
1198 /* Disable all interrupts and request them */
1199 bcm_sf2_intr_disable(priv);
1201 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1204 pr_err("failed to request switch_0 IRQ\n");
1208 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1211 pr_err("failed to request switch_1 IRQ\n");
1215 /* Reset the MIB counters */
1216 reg = core_readl(priv, CORE_GMNCFGCFG);
1218 core_writel(priv, reg, CORE_GMNCFGCFG);
1219 reg &= ~RST_MIB_CNT;
1220 core_writel(priv, reg, CORE_GMNCFGCFG);
1222 /* Get the maximum number of ports for this switch */
1223 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1224 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1225 priv->hw_params.num_ports = DSA_MAX_PORTS;
1227 /* Assume a single GPHY setup if we can't read that property */
1228 if (of_property_read_u32(dn, "brcm,num-gphy",
1229 &priv->hw_params.num_gphy))
1230 priv->hw_params.num_gphy = 1;
1232 rev = reg_readl(priv, REG_SWITCH_REVISION);
1233 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1234 SWITCH_TOP_REV_MASK;
1235 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1237 rev = reg_readl(priv, REG_PHY_REVISION);
1238 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1240 ret = b53_switch_register(dev);
1244 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1245 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1246 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1247 priv->core, priv->irq0, priv->irq1);
1252 bcm_sf2_mdio_unregister(priv);
1256 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1258 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1260 /* Disable all ports and interrupts */
1261 priv->wol_ports_mask = 0;
1262 bcm_sf2_sw_suspend(priv->dev->ds);
1263 dsa_unregister_switch(priv->dev->ds);
1264 bcm_sf2_mdio_unregister(priv);
1269 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1271 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1273 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1274 * successful MDIO bus scan to occur. If we did turn off the GPHY
1275 * before (e.g: port_disable), this will also power it back on.
1277 * Do not rely on kexec_in_progress, just power the PHY on.
1279 if (priv->hw_params.num_gphy == 1)
1280 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1283 #ifdef CONFIG_PM_SLEEP
1284 static int bcm_sf2_suspend(struct device *dev)
1286 struct platform_device *pdev = to_platform_device(dev);
1287 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1289 return dsa_switch_suspend(priv->dev->ds);
1292 static int bcm_sf2_resume(struct device *dev)
1294 struct platform_device *pdev = to_platform_device(dev);
1295 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1297 return dsa_switch_resume(priv->dev->ds);
1299 #endif /* CONFIG_PM_SLEEP */
1301 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1302 bcm_sf2_suspend, bcm_sf2_resume);
1305 static struct platform_driver bcm_sf2_driver = {
1306 .probe = bcm_sf2_sw_probe,
1307 .remove = bcm_sf2_sw_remove,
1308 .shutdown = bcm_sf2_sw_shutdown,
1311 .of_match_table = bcm_sf2_of_match,
1312 .pm = &bcm_sf2_pm_ops,
1315 module_platform_driver(bcm_sf2_driver);
1317 MODULE_AUTHOR("Broadcom Corporation");
1318 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1319 MODULE_LICENSE("GPL");
1320 MODULE_ALIAS("platform:brcm-sf2");