2 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/regmap.h>
18 #include <linux/mutex.h>
19 #include <linux/mii.h>
23 #define LAN9303_NUM_PORTS 3
25 /* 13.2 System Control and Status Registers
26 * Multiply register number by 4 to get address offset.
28 #define LAN9303_CHIP_REV 0x14
29 # define LAN9303_CHIP_ID 0x9303
30 #define LAN9303_IRQ_CFG 0x15
31 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8)
32 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4)
33 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
34 #define LAN9303_INT_STS 0x16
35 # define LAN9303_INT_STS_PHY_INT2 BIT(27)
36 # define LAN9303_INT_STS_PHY_INT1 BIT(26)
37 #define LAN9303_INT_EN 0x17
38 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
39 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
40 #define LAN9303_HW_CFG 0x1D
41 # define LAN9303_HW_CFG_READY BIT(27)
42 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
43 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25)
44 #define LAN9303_PMI_DATA 0x29
45 #define LAN9303_PMI_ACCESS 0x2A
46 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
47 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
48 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
49 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1)
50 #define LAN9303_MANUAL_FC_1 0x68
51 #define LAN9303_MANUAL_FC_2 0x69
52 #define LAN9303_MANUAL_FC_0 0x6a
53 #define LAN9303_SWITCH_CSR_DATA 0x6b
54 #define LAN9303_SWITCH_CSR_CMD 0x6c
55 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31)
56 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30)
57 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16))
58 #define LAN9303_VIRT_PHY_BASE 0x70
59 #define LAN9303_VIRT_SPECIAL_CTRL 0x77
61 /*13.4 Switch Fabric Control and Status Registers
62 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA.
64 #define LAN9303_SW_DEV_ID 0x0000
65 #define LAN9303_SW_RESET 0x0001
66 #define LAN9303_SW_RESET_RESET BIT(0)
67 #define LAN9303_SW_IMR 0x0004
68 #define LAN9303_SW_IPR 0x0005
69 #define LAN9303_MAC_VER_ID_0 0x0400
70 #define LAN9303_MAC_RX_CFG_0 0x0401
71 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1)
72 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
73 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
74 #define LAN9303_MAC_RX_64_CNT_0 0x0411
75 #define LAN9303_MAC_RX_127_CNT_0 0x0412
76 #define LAN9303_MAC_RX_255_CNT_0 0x413
77 #define LAN9303_MAC_RX_511_CNT_0 0x0414
78 #define LAN9303_MAC_RX_1023_CNT_0 0x0415
79 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416
80 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
81 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
82 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
83 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
84 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
85 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
86 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
87 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e
88 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
89 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
90 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
91 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
92 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
94 #define LAN9303_MAC_TX_CFG_0 0x0440
95 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2)
96 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1)
97 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
98 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
99 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
100 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
101 #define LAN9303_MAC_TX_64_CNT_0 0x0454
102 #define LAN9303_MAC_TX_127_CNT_0 0x0455
103 #define LAN9303_MAC_TX_255_CNT_0 0x0456
104 #define LAN9303_MAC_TX_511_CNT_0 0x0457
105 #define LAN9303_MAC_TX_1023_CNT_0 0x0458
106 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459
107 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
108 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
109 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
110 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
111 #define LAN9303_MAC_TX_LATECOL_0 0x045f
112 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
113 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
114 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
115 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
117 #define LAN9303_MAC_VER_ID_1 0x0800
118 #define LAN9303_MAC_RX_CFG_1 0x0801
119 #define LAN9303_MAC_TX_CFG_1 0x0840
120 #define LAN9303_MAC_VER_ID_2 0x0c00
121 #define LAN9303_MAC_RX_CFG_2 0x0c01
122 #define LAN9303_MAC_TX_CFG_2 0x0c40
123 #define LAN9303_SWE_ALR_CMD 0x1800
124 #define LAN9303_SWE_VLAN_CMD 0x180b
125 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5)
126 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4)
127 #define LAN9303_SWE_VLAN_WR_DATA 0x180c
128 #define LAN9303_SWE_VLAN_RD_DATA 0x180e
129 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17)
130 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16)
131 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15)
132 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14)
133 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13)
134 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
135 #define LAN9303_SWE_VLAN_CMD_STS 0x1810
136 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
137 #define LAN9303_SWE_PORT_STATE 0x1843
138 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
139 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
140 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4)
141 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
142 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3)
143 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2)
144 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
145 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1)
146 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
147 #define LAN9303_SWE_PORT_MIRROR 0x1846
148 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8)
149 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7)
150 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6)
151 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5)
152 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4)
153 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3)
154 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2)
155 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1)
156 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
157 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
158 #define LAN9303_BM_CFG 0x1c00
159 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
160 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16))
161 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
162 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
164 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
166 /* the built-in PHYs are of type LAN911X */
167 #define MII_LAN911X_SPECIAL_MODES 0x12
168 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
170 static const struct regmap_range lan9303_valid_regs[] = {
171 regmap_reg_range(0x14, 0x17), /* misc, interrupt */
172 regmap_reg_range(0x19, 0x19), /* endian test */
173 regmap_reg_range(0x1d, 0x1d), /* hardware config */
174 regmap_reg_range(0x23, 0x24), /* general purpose timer */
175 regmap_reg_range(0x27, 0x27), /* counter */
176 regmap_reg_range(0x29, 0x2a), /* PMI index regs */
177 regmap_reg_range(0x68, 0x6a), /* flow control */
178 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
179 regmap_reg_range(0x6d, 0x6f), /* misc */
180 regmap_reg_range(0x70, 0x77), /* virtual phy */
181 regmap_reg_range(0x78, 0x7a), /* GPIO */
182 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
183 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
186 static const struct regmap_range lan9303_reserved_ranges[] = {
187 regmap_reg_range(0x00, 0x13),
188 regmap_reg_range(0x18, 0x18),
189 regmap_reg_range(0x1a, 0x1c),
190 regmap_reg_range(0x1e, 0x22),
191 regmap_reg_range(0x25, 0x26),
192 regmap_reg_range(0x28, 0x28),
193 regmap_reg_range(0x2b, 0x67),
194 regmap_reg_range(0x7b, 0x7b),
195 regmap_reg_range(0x7f, 0x7f),
196 regmap_reg_range(0xb8, 0xff),
199 const struct regmap_access_table lan9303_register_set = {
200 .yes_ranges = lan9303_valid_regs,
201 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs),
202 .no_ranges = lan9303_reserved_ranges,
203 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges),
205 EXPORT_SYMBOL(lan9303_register_set);
207 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
211 /* we can lose arbitration for the I2C case, because the device
212 * tries to detect and read an external EEPROM after reset and acts as
213 * a master on the shared I2C bus itself. This conflicts with our
214 * attempts to access the device as a slave at the same moment.
216 for (i = 0; i < 5; i++) {
217 ret = regmap_read(regmap, offset, reg);
228 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
233 if (regnum > MII_EXPANSION)
236 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
243 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
245 if (regnum > MII_EXPANSION)
248 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
251 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip)
256 for (i = 0; i < 25; i++) {
257 ret = lan9303_read(chip->regmap, LAN9303_PMI_ACCESS, ®);
260 "Failed to read pmi access status: %d\n", ret);
263 if (!(reg & LAN9303_PMI_ACCESS_MII_BUSY))
271 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum)
276 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
277 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
279 mutex_lock(&chip->indirect_mutex);
281 ret = lan9303_indirect_phy_wait_for_completion(chip);
285 /* start the MII read cycle */
286 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
290 ret = lan9303_indirect_phy_wait_for_completion(chip);
294 /* read the result of this operation */
295 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
299 mutex_unlock(&chip->indirect_mutex);
304 mutex_unlock(&chip->indirect_mutex);
308 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr,
314 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
315 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
316 reg |= LAN9303_PMI_ACCESS_MII_WRITE;
318 mutex_lock(&chip->indirect_mutex);
320 ret = lan9303_indirect_phy_wait_for_completion(chip);
324 /* write the data first... */
325 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
329 /* ...then start the MII write cycle */
330 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
333 mutex_unlock(&chip->indirect_mutex);
337 const struct lan9303_phy_ops lan9303_indirect_phy_ops = {
338 .phy_read = lan9303_indirect_phy_read,
339 .phy_write = lan9303_indirect_phy_write,
341 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops);
343 static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
348 for (i = 0; i < 25; i++) {
349 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_CMD, ®);
352 "Failed to read csr command status: %d\n", ret);
355 if (!(reg & LAN9303_SWITCH_CSR_CMD_BUSY))
363 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
369 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
370 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
372 mutex_lock(&chip->indirect_mutex);
374 ret = lan9303_switch_wait_for_completion(chip);
378 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
380 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
385 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
387 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
391 mutex_unlock(&chip->indirect_mutex);
395 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
401 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
402 reg |= LAN9303_SWITCH_CSR_CMD_RW;
403 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
405 mutex_lock(&chip->indirect_mutex);
407 ret = lan9303_switch_wait_for_completion(chip);
412 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
414 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
419 ret = lan9303_switch_wait_for_completion(chip);
423 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
425 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
427 mutex_unlock(&chip->indirect_mutex);
431 static int lan9303_write_switch_port(struct lan9303 *chip, int port,
434 return lan9303_write_switch_reg(
435 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
438 static int lan9303_read_switch_port(struct lan9303 *chip, int port,
439 u16 regnum, u32 *val)
441 return lan9303_read_switch_reg(
442 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
445 static int lan9303_detect_phy_setup(struct lan9303 *chip)
449 /* depending on the 'phy_addr_sel_strap' setting, the three phys are
450 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the
451 * 'phy_addr_sel_strap' setting directly, so we need a test, which
452 * configuration is active:
453 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0
454 * and the IDs are 0-1-2, else it contains something different from
455 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.
456 * 0xffff is returned on MDIO read with no response.
458 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
460 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
464 if ((reg != 0) && (reg != 0xffff))
465 chip->phy_addr_sel_strap = 1;
467 chip->phy_addr_sel_strap = 0;
469 dev_dbg(chip->dev, "Phy setup '%s' detected\n",
470 chip->phy_addr_sel_strap ? "1-2-3" : "0-1-2");
475 static int lan9303_disable_processing_port(struct lan9303 *chip,
480 /* disable RX, but keep register reset default values else */
481 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
482 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
486 /* disable TX, but keep register reset default values else */
487 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
488 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
489 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
492 static int lan9303_enable_processing_port(struct lan9303 *chip,
497 /* enable RX and keep register reset default values else */
498 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
499 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
500 LAN9303_MAC_RX_CFG_X_RX_ENABLE);
504 /* enable TX and keep register reset default values else */
505 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
506 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
507 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
508 LAN9303_MAC_TX_CFG_X_TX_ENABLE);
511 /* We want a special working switch:
512 * - do not forward packets between port 1 and 2
513 * - forward everything from port 1 to port 0
514 * - forward everything from port 2 to port 0
515 * - forward special tagged packets from port 0 to port 1 *or* port 2
517 static int lan9303_separate_ports(struct lan9303 *chip)
521 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
522 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 |
523 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 |
524 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 |
525 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING |
526 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL);
530 /* enable defining the destination port via special VLAN tagging
533 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE,
538 /* tag incoming packets at port 1 and 2 on their way to port 0 to be
539 * able to discover their source port
541 ret = lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE,
542 LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0);
546 /* prevent port 1 and 2 from forwarding packets by their own */
547 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
548 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 |
549 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 |
550 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2);
553 static int lan9303_handle_reset(struct lan9303 *chip)
555 if (!chip->reset_gpio)
558 if (chip->reset_duration != 0)
559 msleep(chip->reset_duration);
561 /* release (deassert) reset and activate the device */
562 gpiod_set_value_cansleep(chip->reset_gpio, 0);
567 /* stop processing packets for all ports */
568 static int lan9303_disable_processing(struct lan9303 *chip)
572 for (p = 0; p < LAN9303_NUM_PORTS; p++) {
573 int ret = lan9303_disable_processing_port(chip, p);
582 static int lan9303_check_device(struct lan9303 *chip)
587 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®);
589 dev_err(chip->dev, "failed to read chip revision register: %d\n",
591 if (!chip->reset_gpio) {
593 "hint: maybe failed due to missing reset GPIO\n");
598 if ((reg >> 16) != LAN9303_CHIP_ID) {
599 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n",
604 /* The default state of the LAN9303 device is to forward packets between
605 * all ports (if not configured differently by an external EEPROM).
606 * The initial state of a DSA device must be forwarding packets only
607 * between the external and the internal ports and no forwarding
608 * between the external ports. In preparation we stop packet handling
609 * at all for now until the LAN9303 device is re-programmed accordingly.
611 ret = lan9303_disable_processing(chip);
613 dev_warn(chip->dev, "failed to disable switching %d\n", ret);
615 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff);
617 ret = lan9303_detect_phy_setup(chip);
620 "failed to discover phy bootstrap setup: %d\n", ret);
627 /* ---------------------------- DSA -----------------------------------*/
629 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds)
631 return DSA_TAG_PROTO_LAN9303;
634 static int lan9303_setup(struct dsa_switch *ds)
636 struct lan9303 *chip = ds->priv;
639 /* Make sure that port 0 is the cpu port */
640 if (!dsa_is_cpu_port(ds, 0)) {
641 dev_err(chip->dev, "port 0 is not the CPU port\n");
645 ret = lan9303_separate_ports(chip);
647 dev_err(chip->dev, "failed to separate ports %d\n", ret);
649 ret = lan9303_enable_processing_port(chip, 0);
651 dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
656 struct lan9303_mib_desc {
657 unsigned int offset; /* offset of first MAC */
661 static const struct lan9303_mib_desc lan9303_mib[] = {
662 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", },
663 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", },
664 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", },
665 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", },
666 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", },
667 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", },
668 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", },
669 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", },
670 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", },
671 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", },
672 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", },
673 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", },
674 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", },
675 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", },
676 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", },
677 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", },
678 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", },
679 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", },
680 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", },
681 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", },
682 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", },
683 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", },
684 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", },
685 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", },
686 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", },
687 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", },
688 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", },
689 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", },
690 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", },
691 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", },
692 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", },
693 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", },
694 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", },
695 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", },
696 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", },
697 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", },
698 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", },
701 static void lan9303_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
705 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
706 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
711 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
714 struct lan9303 *chip = ds->priv;
717 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
721 ret = lan9303_read_switch_port(
722 chip, port, lan9303_mib[u].offset, ®);
725 dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
726 port, lan9303_mib[u].offset);
731 static int lan9303_get_sset_count(struct dsa_switch *ds)
733 return ARRAY_SIZE(lan9303_mib);
736 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum)
738 struct lan9303 *chip = ds->priv;
739 int phy_base = chip->phy_addr_sel_strap;
742 return lan9303_virt_phy_reg_read(chip, regnum);
743 if (phy > phy_base + 2)
746 return chip->ops->phy_read(chip, phy, regnum);
749 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum,
752 struct lan9303 *chip = ds->priv;
753 int phy_base = chip->phy_addr_sel_strap;
756 return lan9303_virt_phy_reg_write(chip, regnum, val);
757 if (phy > phy_base + 2)
760 return chip->ops->phy_write(chip, phy, regnum, val);
763 static int lan9303_port_enable(struct dsa_switch *ds, int port,
764 struct phy_device *phy)
766 struct lan9303 *chip = ds->priv;
768 /* enable internal packet processing */
772 return lan9303_enable_processing_port(chip, port);
775 "Error: request to power up invalid port %d\n", port);
781 static void lan9303_port_disable(struct dsa_switch *ds, int port,
782 struct phy_device *phy)
784 struct lan9303 *chip = ds->priv;
786 /* disable internal packet processing */
790 lan9303_disable_processing_port(chip, port);
791 lan9303_phy_write(ds, chip->phy_addr_sel_strap + port,
792 MII_BMCR, BMCR_PDOWN);
796 "Error: request to power down invalid port %d\n", port);
800 static const struct dsa_switch_ops lan9303_switch_ops = {
801 .get_tag_protocol = lan9303_get_tag_protocol,
802 .setup = lan9303_setup,
803 .get_strings = lan9303_get_strings,
804 .phy_read = lan9303_phy_read,
805 .phy_write = lan9303_phy_write,
806 .get_ethtool_stats = lan9303_get_ethtool_stats,
807 .get_sset_count = lan9303_get_sset_count,
808 .port_enable = lan9303_port_enable,
809 .port_disable = lan9303_port_disable,
812 static int lan9303_register_switch(struct lan9303 *chip)
814 chip->ds = dsa_switch_alloc(chip->dev, LAN9303_NUM_PORTS);
818 chip->ds->priv = chip;
819 chip->ds->ops = &lan9303_switch_ops;
820 chip->ds->phys_mii_mask = chip->phy_addr_sel_strap ? 0xe : 0x7;
822 return dsa_register_switch(chip->ds);
825 static void lan9303_probe_reset_gpio(struct lan9303 *chip,
826 struct device_node *np)
828 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
831 if (!chip->reset_gpio) {
832 dev_dbg(chip->dev, "No reset GPIO defined\n");
836 chip->reset_duration = 200;
839 of_property_read_u32(np, "reset-duration",
840 &chip->reset_duration);
842 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
845 /* A sane reset duration should not be longer than 1s */
846 if (chip->reset_duration > 1000)
847 chip->reset_duration = 1000;
850 int lan9303_probe(struct lan9303 *chip, struct device_node *np)
854 mutex_init(&chip->indirect_mutex);
856 lan9303_probe_reset_gpio(chip, np);
858 ret = lan9303_handle_reset(chip);
862 ret = lan9303_check_device(chip);
866 ret = lan9303_register_switch(chip);
868 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
874 EXPORT_SYMBOL(lan9303_probe);
876 int lan9303_remove(struct lan9303 *chip)
880 rc = lan9303_disable_processing(chip);
882 dev_warn(chip->dev, "shutting down failed\n");
884 dsa_unregister_switch(chip->ds);
886 /* assert reset to the whole device to prevent it from doing anything */
887 gpiod_set_value_cansleep(chip->reset_gpio, 1);
888 gpiod_unexport(chip->reset_gpio);
892 EXPORT_SYMBOL(lan9303_remove);
894 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
895 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
896 MODULE_LICENSE("GPL v2");