1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip KSZ9477 switch driver main logic
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/iopoll.h>
11 #include <linux/platform_data/microchip-ksz.h>
12 #include <linux/phy.h>
13 #include <linux/if_bridge.h>
15 #include <net/switchdev.h>
18 #include "ksz9477_reg.h"
19 #include "ksz_common.h"
21 /* Used with variable features to indicate capabilities. */
22 #define GBIT_SUPPORT BIT(0)
23 #define NEW_XMII BIT(1)
24 #define IS_9893 BIT(2)
28 char string[ETH_GSTRING_LEN];
29 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
31 { 0x01, "rx_undersize" },
32 { 0x02, "rx_fragments" },
33 { 0x03, "rx_oversize" },
34 { 0x04, "rx_jabbers" },
35 { 0x05, "rx_symbol_err" },
36 { 0x06, "rx_crc_err" },
37 { 0x07, "rx_align_err" },
38 { 0x08, "rx_mac_ctrl" },
43 { 0x0D, "rx_64_or_less" },
44 { 0x0E, "rx_65_127" },
45 { 0x0F, "rx_128_255" },
46 { 0x10, "rx_256_511" },
47 { 0x11, "rx_512_1023" },
48 { 0x12, "rx_1024_1522" },
49 { 0x13, "rx_1523_2000" },
52 { 0x16, "tx_late_col" },
57 { 0x1B, "tx_deferred" },
58 { 0x1C, "tx_total_col" },
59 { 0x1D, "tx_exc_col" },
60 { 0x1E, "tx_single_col" },
61 { 0x1F, "tx_mult_col" },
64 { 0x82, "rx_discards" },
65 { 0x83, "tx_discards" },
68 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
72 ksz_read32(dev, addr, &data);
77 ksz_write32(dev, addr, data);
80 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
86 addr = PORT_CTRL_ADDR(port, offset);
87 ksz_read32(dev, addr, &data);
94 ksz_write32(dev, addr, data);
97 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton,
103 ksz_read8(dev, REG_SW_VLAN_CTRL, &data);
104 if (!(data & waiton))
107 } while (timeout-- > 0);
115 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
120 mutex_lock(&dev->vlan_mutex);
122 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
123 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
125 /* wait to be cleared */
126 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
128 dev_dbg(dev->dev, "Failed to read vlan table\n");
132 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
133 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
134 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
136 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
139 mutex_unlock(&dev->vlan_mutex);
144 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
149 mutex_lock(&dev->vlan_mutex);
151 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
152 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
153 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
155 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
156 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
158 /* wait to be cleared */
159 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
161 dev_dbg(dev->dev, "Failed to write vlan table\n");
165 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
167 /* update vlan cache table */
168 dev->vlan_cache[vid].table[0] = vlan_table[0];
169 dev->vlan_cache[vid].table[1] = vlan_table[1];
170 dev->vlan_cache[vid].table[2] = vlan_table[2];
173 mutex_unlock(&dev->vlan_mutex);
178 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
180 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
181 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
182 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
183 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
186 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
188 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
189 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
190 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
191 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
194 static int ksz9477_wait_alu_ready(struct ksz_device *dev, u32 waiton,
200 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data);
201 if (!(data & waiton))
204 } while (timeout-- > 0);
212 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev, u32 waiton,
218 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data);
219 if (!(data & waiton))
222 } while (timeout-- > 0);
230 static int ksz9477_reset_switch(struct ksz_device *dev)
237 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
239 /* turn off SPI DO Edge select */
240 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
241 data8 &= ~SPI_AUTO_EDGE_DETECTION;
242 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
244 /* default configuration */
245 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
246 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
247 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
248 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
250 /* disable interrupts */
251 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
252 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
253 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
255 /* set broadcast storm protection 10% rate */
256 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16);
257 data16 &= ~BROADCAST_STORM_RATE;
258 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
259 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16);
264 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
267 struct ksz_poll_ctx ctx = {
270 .offset = REG_PORT_MIB_CTRL_STAT__4,
272 struct ksz_port *p = &dev->ports[port];
276 /* retain the flush/freeze bit */
277 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
278 data |= MIB_COUNTER_READ;
279 data |= (addr << MIB_COUNTER_INDEX_S);
280 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
282 ret = readx_poll_timeout(ksz_pread32_poll, &ctx, data,
283 !(data & MIB_COUNTER_READ), 10, 1000);
285 /* failed to read MIB. get out of loop */
287 dev_dbg(dev->dev, "Failed to get MIB\n");
291 /* count resets upon read */
292 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
296 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
297 u64 *dropped, u64 *cnt)
299 addr = ksz9477_mib_names[addr].index;
300 ksz9477_r_mib_cnt(dev, port, addr, cnt);
303 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
305 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
306 struct ksz_port *p = &dev->ports[port];
308 /* enable/disable the port for flush/freeze function */
309 mutex_lock(&p->mib.cnt_mutex);
310 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
312 /* used by MIB counter reading code to know freeze is enabled */
314 mutex_unlock(&p->mib.cnt_mutex);
317 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
319 struct ksz_port_mib *mib = &dev->ports[port].mib;
321 /* flush all enabled port MIB counters */
322 mutex_lock(&mib->cnt_mutex);
323 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
324 MIB_COUNTER_FLUSH_FREEZE);
325 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
326 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
327 mutex_unlock(&mib->cnt_mutex);
330 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
333 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
336 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
337 struct ksz_device *dev = ds->priv;
339 if (dev->features & IS_9893)
340 proto = DSA_TAG_PROTO_KSZ9893;
344 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
346 struct ksz_device *dev = ds->priv;
349 /* No real PHY after this. Simulate the PHY.
350 * A fixed PHY can be setup in the device tree, but this function is
351 * still called for that port during initialization.
352 * For RGMII PHY there is no way to access it so the fixed PHY should
353 * be used. For SGMII PHY the supporting code will be added later.
355 if (addr >= dev->phy_port_cnt) {
356 struct ksz_port *p = &dev->ports[addr];
381 if (p->phydev.speed == SPEED_1000)
388 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
394 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
397 struct ksz_device *dev = ds->priv;
399 /* No real PHY after this. */
400 if (addr >= dev->phy_port_cnt)
403 /* No gigabit support. Do not write to this register. */
404 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
406 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
411 static void ksz9477_get_strings(struct dsa_switch *ds, int port,
412 u32 stringset, uint8_t *buf)
416 if (stringset != ETH_SS_STATS)
419 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
420 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string,
425 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
428 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
429 dev->ports[port].member = member;
432 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port,
435 struct ksz_device *dev = ds->priv;
436 struct ksz_port *p = &dev->ports[port];
439 int forward = dev->member;
441 ksz_pread8(dev, port, P_STP_CTRL, &data);
442 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
445 case BR_STATE_DISABLED:
446 data |= PORT_LEARN_DISABLE;
447 if (port != dev->cpu_port)
450 case BR_STATE_LISTENING:
451 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
452 if (port != dev->cpu_port &&
453 p->stp_state == BR_STATE_DISABLED)
454 member = dev->host_mask | p->vid_member;
456 case BR_STATE_LEARNING:
457 data |= PORT_RX_ENABLE;
459 case BR_STATE_FORWARDING:
460 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
462 /* This function is also used internally. */
463 if (port == dev->cpu_port)
466 member = dev->host_mask | p->vid_member;
467 mutex_lock(&dev->dev_mutex);
469 /* Port is a member of a bridge. */
470 if (dev->br_member & (1 << port)) {
471 dev->member |= (1 << port);
472 member = dev->member;
474 mutex_unlock(&dev->dev_mutex);
476 case BR_STATE_BLOCKING:
477 data |= PORT_LEARN_DISABLE;
478 if (port != dev->cpu_port &&
479 p->stp_state == BR_STATE_DISABLED)
480 member = dev->host_mask | p->vid_member;
483 dev_err(ds->dev, "invalid STP state: %d\n", state);
487 ksz_pwrite8(dev, port, P_STP_CTRL, data);
488 p->stp_state = state;
489 mutex_lock(&dev->dev_mutex);
490 if (data & PORT_RX_ENABLE)
491 dev->rx_ports |= (1 << port);
493 dev->rx_ports &= ~(1 << port);
494 if (data & PORT_TX_ENABLE)
495 dev->tx_ports |= (1 << port);
497 dev->tx_ports &= ~(1 << port);
499 /* Port membership may share register with STP state. */
500 if (member >= 0 && member != p->member)
501 ksz9477_cfg_port_member(dev, port, (u8)member);
503 /* Check if forwarding needs to be updated. */
504 if (state != BR_STATE_FORWARDING) {
505 if (dev->br_member & (1 << port))
506 dev->member &= ~(1 << port);
509 /* When topology has changed the function ksz_update_port_member
510 * should be called to modify port forwarding behavior.
512 if (forward != dev->member)
513 ksz_update_port_member(dev, port);
514 mutex_unlock(&dev->dev_mutex);
517 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
521 ksz_read8(dev, REG_SW_LUE_CTRL_2, &data);
522 data &= ~(SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S);
523 data |= (SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
524 ksz_write8(dev, REG_SW_LUE_CTRL_2, data);
525 if (port < dev->mib_port_cnt) {
526 /* flush individual port */
527 ksz_pread8(dev, port, P_STP_CTRL, &data);
528 if (!(data & PORT_LEARN_DISABLE))
529 ksz_pwrite8(dev, port, P_STP_CTRL,
530 data | PORT_LEARN_DISABLE);
531 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
532 ksz_pwrite8(dev, port, P_STP_CTRL, data);
535 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
539 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port,
542 struct ksz_device *dev = ds->priv;
545 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
546 PORT_VLAN_LOOKUP_VID_0, true);
547 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
549 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
550 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
551 PORT_VLAN_LOOKUP_VID_0, false);
557 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port,
558 const struct switchdev_obj_port_vlan *vlan)
560 struct ksz_device *dev = ds->priv;
563 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
565 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
566 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
567 dev_dbg(dev->dev, "Failed to get vlan table\n");
571 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M);
573 vlan_table[1] |= BIT(port);
575 vlan_table[1] &= ~BIT(port);
576 vlan_table[1] &= ~(BIT(dev->cpu_port));
578 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
580 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
581 dev_dbg(dev->dev, "Failed to set vlan table\n");
586 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
587 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid);
591 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port,
592 const struct switchdev_obj_port_vlan *vlan)
594 struct ksz_device *dev = ds->priv;
595 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
600 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
603 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
604 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
605 dev_dbg(dev->dev, "Failed to get vlan table\n");
609 vlan_table[2] &= ~BIT(port);
615 vlan_table[1] &= ~BIT(port);
617 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
618 dev_dbg(dev->dev, "Failed to set vlan table\n");
623 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
628 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port,
629 const unsigned char *addr, u16 vid)
631 struct ksz_device *dev = ds->priv;
636 mutex_lock(&dev->alu_mutex);
638 /* find any entry with mac & vid */
639 data = vid << ALU_FID_INDEX_S;
640 data |= ((addr[0] << 8) | addr[1]);
641 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
643 data = ((addr[2] << 24) | (addr[3] << 16));
644 data |= ((addr[4] << 8) | addr[5]);
645 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
647 /* start read operation */
648 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
650 /* wait to be finished */
651 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
653 dev_dbg(dev->dev, "Failed to read ALU\n");
658 ksz9477_read_table(dev, alu_table);
660 /* update ALU entry */
661 alu_table[0] = ALU_V_STATIC_VALID;
662 alu_table[1] |= BIT(port);
664 alu_table[1] |= ALU_V_USE_FID;
665 alu_table[2] = (vid << ALU_V_FID_S);
666 alu_table[2] |= ((addr[0] << 8) | addr[1]);
667 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
668 alu_table[3] |= ((addr[4] << 8) | addr[5]);
670 ksz9477_write_table(dev, alu_table);
672 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
674 /* wait to be finished */
675 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
677 dev_dbg(dev->dev, "Failed to write ALU\n");
680 mutex_unlock(&dev->alu_mutex);
685 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port,
686 const unsigned char *addr, u16 vid)
688 struct ksz_device *dev = ds->priv;
693 mutex_lock(&dev->alu_mutex);
695 /* read any entry with mac & vid */
696 data = vid << ALU_FID_INDEX_S;
697 data |= ((addr[0] << 8) | addr[1]);
698 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
700 data = ((addr[2] << 24) | (addr[3] << 16));
701 data |= ((addr[4] << 8) | addr[5]);
702 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
704 /* start read operation */
705 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
707 /* wait to be finished */
708 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
710 dev_dbg(dev->dev, "Failed to read ALU\n");
714 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
715 if (alu_table[0] & ALU_V_STATIC_VALID) {
716 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
717 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
718 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
720 /* clear forwarding port */
721 alu_table[2] &= ~BIT(port);
723 /* if there is no port to forward, clear table */
724 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
737 ksz9477_write_table(dev, alu_table);
739 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
741 /* wait to be finished */
742 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
744 dev_dbg(dev->dev, "Failed to write ALU\n");
747 mutex_unlock(&dev->alu_mutex);
752 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
754 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
755 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
756 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
757 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
758 ALU_V_PRIO_AGE_CNT_M;
759 alu->mstp = alu_table[0] & ALU_V_MSTP_M;
761 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
762 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
763 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
765 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
767 alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
768 alu->mac[1] = alu_table[2] & 0xFF;
769 alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
770 alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
771 alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
772 alu->mac[5] = alu_table[3] & 0xFF;
775 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port,
776 dsa_fdb_dump_cb_t *cb, void *data)
778 struct ksz_device *dev = ds->priv;
782 struct alu_struct alu;
785 mutex_lock(&dev->alu_mutex);
787 /* start ALU search */
788 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
793 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
794 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
797 } while (timeout-- > 0);
800 dev_dbg(dev->dev, "Failed to search ALU\n");
806 ksz9477_read_table(dev, alu_table);
808 ksz9477_convert_alu(&alu, alu_table);
810 if (alu.port_forward & BIT(port)) {
811 ret = cb(alu.mac, alu.fid, alu.is_static, data);
815 } while (ksz_data & ALU_START);
819 /* stop ALU search */
820 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
822 mutex_unlock(&dev->alu_mutex);
827 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port,
828 const struct switchdev_obj_port_mdb *mdb)
830 struct ksz_device *dev = ds->priv;
836 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
837 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
838 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
840 mutex_lock(&dev->alu_mutex);
842 for (index = 0; index < dev->num_statics; index++) {
843 /* find empty slot first */
844 data = (index << ALU_STAT_INDEX_S) |
845 ALU_STAT_READ | ALU_STAT_START;
846 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
848 /* wait to be finished */
849 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) {
850 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
854 /* read ALU static table */
855 ksz9477_read_table(dev, static_table);
857 if (static_table[0] & ALU_V_STATIC_VALID) {
858 /* check this has same vid & mac address */
859 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
860 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
861 static_table[3] == mac_lo) {
862 /* found matching one */
866 /* found empty one */
871 /* no available entry */
872 if (index == dev->num_statics)
876 static_table[0] = ALU_V_STATIC_VALID;
877 static_table[1] |= BIT(port);
879 static_table[1] |= ALU_V_USE_FID;
880 static_table[2] = (mdb->vid << ALU_V_FID_S);
881 static_table[2] |= mac_hi;
882 static_table[3] = mac_lo;
884 ksz9477_write_table(dev, static_table);
886 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
887 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
889 /* wait to be finished */
890 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0)
891 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
894 mutex_unlock(&dev->alu_mutex);
897 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port,
898 const struct switchdev_obj_port_mdb *mdb)
900 struct ksz_device *dev = ds->priv;
907 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
908 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
909 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
911 mutex_lock(&dev->alu_mutex);
913 for (index = 0; index < dev->num_statics; index++) {
914 /* find empty slot first */
915 data = (index << ALU_STAT_INDEX_S) |
916 ALU_STAT_READ | ALU_STAT_START;
917 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
919 /* wait to be finished */
920 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
922 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
926 /* read ALU static table */
927 ksz9477_read_table(dev, static_table);
929 if (static_table[0] & ALU_V_STATIC_VALID) {
930 /* check this has same vid & mac address */
932 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
933 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
934 static_table[3] == mac_lo) {
935 /* found matching one */
941 /* no available entry */
942 if (index == dev->num_statics)
946 static_table[1] &= ~BIT(port);
948 if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
956 ksz9477_write_table(dev, static_table);
958 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
959 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
961 /* wait to be finished */
962 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
964 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
967 mutex_unlock(&dev->alu_mutex);
972 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port,
973 struct dsa_mall_mirror_tc_entry *mirror,
976 struct ksz_device *dev = ds->priv;
979 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
981 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
983 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
985 /* configure mirror port */
986 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
987 PORT_MIRROR_SNIFFER, true);
989 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
994 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
995 struct dsa_mall_mirror_tc_entry *mirror)
997 struct ksz_device *dev = ds->priv;
1000 if (mirror->ingress)
1001 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1003 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1005 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1007 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
1008 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1009 PORT_MIRROR_SNIFFER, false);
1012 static void ksz9477_phy_setup(struct ksz_device *dev, int port,
1013 struct phy_device *phy)
1015 /* Only apply to port with PHY. */
1016 if (port >= dev->phy_port_cnt)
1019 /* The MAC actually cannot run in 1000 half-duplex mode. */
1020 phy_remove_link_mode(phy,
1021 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1023 /* PHY does not support gigabit. */
1024 if (!(dev->features & GBIT_SUPPORT))
1025 phy_remove_link_mode(phy,
1026 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1029 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
1033 if (dev->features & NEW_XMII)
1034 gbit = !(data & PORT_MII_NOT_1GBIT);
1036 gbit = !!(data & PORT_MII_1000MBIT_S1);
1040 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
1042 if (dev->features & NEW_XMII) {
1044 *data &= ~PORT_MII_NOT_1GBIT;
1046 *data |= PORT_MII_NOT_1GBIT;
1049 *data |= PORT_MII_1000MBIT_S1;
1051 *data &= ~PORT_MII_1000MBIT_S1;
1055 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
1059 if (dev->features & NEW_XMII) {
1060 switch (data & PORT_MII_SEL_M) {
1074 switch (data & PORT_MII_SEL_M) {
1075 case PORT_MII_SEL_S1:
1078 case PORT_RMII_SEL_S1:
1081 case PORT_GMII_SEL_S1:
1091 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
1095 if (dev->features & NEW_XMII) {
1098 xmii = PORT_MII_SEL;
1101 xmii = PORT_RMII_SEL;
1104 xmii = PORT_GMII_SEL;
1107 xmii = PORT_RGMII_SEL;
1113 xmii = PORT_MII_SEL_S1;
1116 xmii = PORT_RMII_SEL_S1;
1119 xmii = PORT_GMII_SEL_S1;
1122 xmii = PORT_RGMII_SEL_S1;
1126 *data &= ~PORT_MII_SEL_M;
1130 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
1132 phy_interface_t interface;
1137 if (port < dev->phy_port_cnt)
1138 return PHY_INTERFACE_MODE_NA;
1139 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1140 gbit = ksz9477_get_gbit(dev, data8);
1141 mode = ksz9477_get_xmii(dev, data8);
1144 interface = PHY_INTERFACE_MODE_GMII;
1149 interface = PHY_INTERFACE_MODE_MII;
1152 interface = PHY_INTERFACE_MODE_RMII;
1155 interface = PHY_INTERFACE_MODE_RGMII;
1156 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1157 interface = PHY_INTERFACE_MODE_RGMII_TXID;
1158 if (data8 & PORT_RGMII_ID_IG_ENABLE) {
1159 interface = PHY_INTERFACE_MODE_RGMII_RXID;
1160 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1161 interface = PHY_INTERFACE_MODE_RGMII_ID;
1168 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1173 struct ksz_port *p = &dev->ports[port];
1175 /* enable tag tail for host port */
1177 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
1180 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
1182 /* set back pressure */
1183 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
1185 /* enable broadcast storm limit */
1186 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1188 /* disable DiffServ priority */
1189 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
1191 /* replace priority */
1192 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1194 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1195 MTI_PVID_REPLACE, false);
1197 /* enable 802.1p priority */
1198 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1200 if (port < dev->phy_port_cnt) {
1201 /* do not force flow control */
1202 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1203 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1207 /* force flow control */
1208 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1209 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1212 /* configure MAC to 1G & RGMII mode */
1213 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1214 switch (dev->interface) {
1215 case PHY_INTERFACE_MODE_MII:
1216 ksz9477_set_xmii(dev, 0, &data8);
1217 ksz9477_set_gbit(dev, false, &data8);
1218 p->phydev.speed = SPEED_100;
1220 case PHY_INTERFACE_MODE_RMII:
1221 ksz9477_set_xmii(dev, 1, &data8);
1222 ksz9477_set_gbit(dev, false, &data8);
1223 p->phydev.speed = SPEED_100;
1225 case PHY_INTERFACE_MODE_GMII:
1226 ksz9477_set_xmii(dev, 2, &data8);
1227 ksz9477_set_gbit(dev, true, &data8);
1228 p->phydev.speed = SPEED_1000;
1231 ksz9477_set_xmii(dev, 3, &data8);
1232 ksz9477_set_gbit(dev, true, &data8);
1233 data8 &= ~PORT_RGMII_ID_IG_ENABLE;
1234 data8 &= ~PORT_RGMII_ID_EG_ENABLE;
1235 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1236 dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1237 data8 |= PORT_RGMII_ID_IG_ENABLE;
1238 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1239 dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1240 data8 |= PORT_RGMII_ID_EG_ENABLE;
1241 p->phydev.speed = SPEED_1000;
1244 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
1245 p->phydev.duplex = 1;
1247 mutex_lock(&dev->dev_mutex);
1249 member = dev->port_mask;
1250 dev->on_ports = dev->host_mask;
1251 dev->live_ports = dev->host_mask;
1253 member = dev->host_mask | p->vid_member;
1254 dev->on_ports |= (1 << port);
1256 /* Link was detected before port is enabled. */
1258 dev->live_ports |= (1 << port);
1260 mutex_unlock(&dev->dev_mutex);
1261 ksz9477_cfg_port_member(dev, port, member);
1263 /* clear pending interrupts */
1264 if (port < dev->phy_port_cnt)
1265 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1268 static void ksz9477_config_cpu_port(struct dsa_switch *ds)
1270 struct ksz_device *dev = ds->priv;
1274 ds->num_ports = dev->port_cnt;
1276 for (i = 0; i < dev->port_cnt; i++) {
1277 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
1278 phy_interface_t interface;
1281 dev->host_mask = (1 << dev->cpu_port);
1282 dev->port_mask |= dev->host_mask;
1284 /* Read from XMII register to determine host port
1285 * interface. If set specifically in device tree
1286 * note the difference to help debugging.
1288 interface = ksz9477_get_interface(dev, i);
1289 if (!dev->interface)
1290 dev->interface = interface;
1291 if (interface && interface != dev->interface)
1293 "use %s instead of %s\n",
1294 phy_modes(dev->interface),
1295 phy_modes(interface));
1297 /* enable cpu port */
1298 ksz9477_port_setup(dev, i, true);
1299 p = &dev->ports[dev->cpu_port];
1300 p->vid_member = dev->port_mask;
1305 dev->member = dev->host_mask;
1307 for (i = 0; i < dev->mib_port_cnt; i++) {
1308 if (i == dev->cpu_port)
1312 /* Initialize to non-zero so that ksz_cfg_port_member() will
1315 p->vid_member = (1 << i);
1316 p->member = dev->port_mask;
1317 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1319 if (i < dev->phy_port_cnt)
1321 if (dev->chip_id == 0x00947700 && i == 6) {
1324 /* SGMII PHY detection code is not implemented yet. */
1330 static int ksz9477_setup(struct dsa_switch *ds)
1332 struct ksz_device *dev = ds->priv;
1335 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1336 dev->num_vlans, GFP_KERNEL);
1337 if (!dev->vlan_cache)
1340 ret = ksz9477_reset_switch(dev);
1342 dev_err(ds->dev, "failed to reset switch\n");
1346 /* Required for port partitioning. */
1347 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1350 /* Do not work correctly with tail tagging. */
1351 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1353 /* accept packet up to 2000bytes */
1354 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
1356 ksz9477_config_cpu_port(ds);
1358 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
1360 /* queue based egress rate limit */
1361 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1363 /* enable global MIB counter freeze function */
1364 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1367 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
1369 ksz_init_mib_timer(dev);
1374 static const struct dsa_switch_ops ksz9477_switch_ops = {
1375 .get_tag_protocol = ksz9477_get_tag_protocol,
1376 .setup = ksz9477_setup,
1377 .phy_read = ksz9477_phy_read16,
1378 .phy_write = ksz9477_phy_write16,
1379 .adjust_link = ksz_adjust_link,
1380 .port_enable = ksz_enable_port,
1381 .port_disable = ksz_disable_port,
1382 .get_strings = ksz9477_get_strings,
1383 .get_ethtool_stats = ksz_get_ethtool_stats,
1384 .get_sset_count = ksz_sset_count,
1385 .port_bridge_join = ksz_port_bridge_join,
1386 .port_bridge_leave = ksz_port_bridge_leave,
1387 .port_stp_state_set = ksz9477_port_stp_state_set,
1388 .port_fast_age = ksz_port_fast_age,
1389 .port_vlan_filtering = ksz9477_port_vlan_filtering,
1390 .port_vlan_prepare = ksz_port_vlan_prepare,
1391 .port_vlan_add = ksz9477_port_vlan_add,
1392 .port_vlan_del = ksz9477_port_vlan_del,
1393 .port_fdb_dump = ksz9477_port_fdb_dump,
1394 .port_fdb_add = ksz9477_port_fdb_add,
1395 .port_fdb_del = ksz9477_port_fdb_del,
1396 .port_mdb_prepare = ksz_port_mdb_prepare,
1397 .port_mdb_add = ksz9477_port_mdb_add,
1398 .port_mdb_del = ksz9477_port_mdb_del,
1399 .port_mirror_add = ksz9477_port_mirror_add,
1400 .port_mirror_del = ksz9477_port_mirror_del,
1403 static u32 ksz9477_get_port_addr(int port, int offset)
1405 return PORT_CTRL_ADDR(port, offset);
1408 static int ksz9477_switch_detect(struct ksz_device *dev)
1416 /* turn off SPI DO Edge select */
1417 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1421 data8 &= ~SPI_AUTO_EDGE_DETECTION;
1422 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1427 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1430 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1434 /* Number of ports can be reduced depending on chip. */
1435 dev->mib_port_cnt = TOTAL_PORT_NUM;
1436 dev->phy_port_cnt = 5;
1438 /* Default capability is gigabit capable. */
1439 dev->features = GBIT_SUPPORT;
1441 id_hi = (u8)(id32 >> 16);
1442 id_lo = (u8)(id32 >> 8);
1443 if ((id_lo & 0xf) == 3) {
1444 /* Chip is from KSZ9893 design. */
1445 dev->features |= IS_9893;
1447 /* Chip does not support gigabit. */
1448 if (data8 & SW_QW_ABLE)
1449 dev->features &= ~GBIT_SUPPORT;
1450 dev->mib_port_cnt = 3;
1451 dev->phy_port_cnt = 2;
1453 /* Chip uses new XMII register definitions. */
1454 dev->features |= NEW_XMII;
1456 /* Chip does not support gigabit. */
1457 if (!(data8 & SW_GIGABIT_ABLE))
1458 dev->features &= ~GBIT_SUPPORT;
1461 /* Change chip id to known ones so it can be matched against them. */
1462 id32 = (id_hi << 16) | (id_lo << 8);
1464 dev->chip_id = id32;
1469 struct ksz_chip_data {
1471 const char *dev_name;
1479 static const struct ksz_chip_data ksz9477_switch_chips[] = {
1481 .chip_id = 0x00947700,
1482 .dev_name = "KSZ9477",
1486 .cpu_ports = 0x7F, /* can be configured as cpu port */
1487 .port_cnt = 7, /* total physical port count */
1490 .chip_id = 0x00989700,
1491 .dev_name = "KSZ9897",
1495 .cpu_ports = 0x7F, /* can be configured as cpu port */
1496 .port_cnt = 7, /* total physical port count */
1499 .chip_id = 0x00989300,
1500 .dev_name = "KSZ9893",
1504 .cpu_ports = 0x07, /* can be configured as cpu port */
1505 .port_cnt = 3, /* total port count */
1509 static int ksz9477_switch_init(struct ksz_device *dev)
1513 dev->ds->ops = &ksz9477_switch_ops;
1515 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) {
1516 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i];
1518 if (dev->chip_id == chip->chip_id) {
1519 dev->name = chip->dev_name;
1520 dev->num_vlans = chip->num_vlans;
1521 dev->num_alus = chip->num_alus;
1522 dev->num_statics = chip->num_statics;
1523 dev->port_cnt = chip->port_cnt;
1524 dev->cpu_ports = chip->cpu_ports;
1530 /* no switch found */
1534 dev->port_mask = (1 << dev->port_cnt) - 1;
1536 dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1537 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1539 i = dev->mib_port_cnt;
1540 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1544 for (i = 0; i < dev->mib_port_cnt; i++) {
1545 mutex_init(&dev->ports[i].mib.cnt_mutex);
1546 dev->ports[i].mib.counters =
1547 devm_kzalloc(dev->dev,
1549 (TOTAL_SWITCH_COUNTER_NUM + 1),
1551 if (!dev->ports[i].mib.counters)
1558 static void ksz9477_switch_exit(struct ksz_device *dev)
1560 ksz9477_reset_switch(dev);
1563 static const struct ksz_dev_ops ksz9477_dev_ops = {
1564 .get_port_addr = ksz9477_get_port_addr,
1565 .cfg_port_member = ksz9477_cfg_port_member,
1566 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
1567 .phy_setup = ksz9477_phy_setup,
1568 .port_setup = ksz9477_port_setup,
1569 .r_mib_cnt = ksz9477_r_mib_cnt,
1570 .r_mib_pkt = ksz9477_r_mib_pkt,
1571 .freeze_mib = ksz9477_freeze_mib,
1572 .port_init_cnt = ksz9477_port_init_cnt,
1573 .shutdown = ksz9477_reset_switch,
1574 .detect = ksz9477_switch_detect,
1575 .init = ksz9477_switch_init,
1576 .exit = ksz9477_switch_exit,
1579 int ksz9477_switch_register(struct ksz_device *dev)
1581 return ksz_switch_register(dev, &ksz9477_dev_ops);
1583 EXPORT_SYMBOL(ksz9477_switch_register);
1585 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1586 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1587 MODULE_LICENSE("GPL");