2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/platform_data/mv88e6xxx.h>
32 #include <linux/netdevice.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/phy.h>
35 #include <linux/phylink.h>
47 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
50 dev_err(chip->dev, "Switch registers lock not held!\n");
55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
56 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
58 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
59 * is the only device connected to the SMI master. In this mode it responds to
60 * all 32 possible SMI addresses, and thus maps directly the internal devices.
62 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
63 * multiple devices to share the SMI interface. In this mode it responds to only
64 * 2 registers, used to indirectly access the internal SMI devices.
67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
68 int addr, int reg, u16 *val)
73 return chip->smi_ops->read(chip, addr, reg, val);
76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
77 int addr, int reg, u16 val)
82 return chip->smi_ops->write(chip, addr, reg, val);
85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
86 int addr, int reg, u16 *val)
90 ret = mdiobus_read_nested(chip->bus, addr, reg);
99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
100 int addr, int reg, u16 val)
104 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
112 .read = mv88e6xxx_smi_single_chip_read,
113 .write = mv88e6xxx_smi_single_chip_write,
116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
121 for (i = 0; i < 16; i++) {
122 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
126 if ((ret & SMI_CMD_BUSY) == 0)
133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
134 int addr, int reg, u16 *val)
138 /* Wait for the bus to become free. */
139 ret = mv88e6xxx_smi_multi_chip_wait(chip);
143 /* Transmit the read command. */
144 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
145 SMI_CMD_OP_22_READ | (addr << 5) | reg);
149 /* Wait for the read command to complete. */
150 ret = mv88e6xxx_smi_multi_chip_wait(chip);
155 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
165 int addr, int reg, u16 val)
169 /* Wait for the bus to become free. */
170 ret = mv88e6xxx_smi_multi_chip_wait(chip);
174 /* Transmit the data to write. */
175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
179 /* Transmit the write command. */
180 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
181 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
185 /* Wait for the write command to complete. */
186 ret = mv88e6xxx_smi_multi_chip_wait(chip);
193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
194 .read = mv88e6xxx_smi_multi_chip_read,
195 .write = mv88e6xxx_smi_multi_chip_write,
198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
202 assert_reg_lock(chip);
204 err = mv88e6xxx_smi_read(chip, addr, reg, val);
208 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
218 assert_reg_lock(chip);
220 err = mv88e6xxx_smi_write(chip, addr, reg, val);
224 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
232 struct mv88e6xxx_mdio_bus *mdio_bus;
234 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
239 return mdio_bus->bus;
242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
244 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
245 unsigned int n = d->hwirq;
247 chip->g1_irq.masked |= (1 << n);
250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
252 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
253 unsigned int n = d->hwirq;
255 chip->g1_irq.masked &= ~(1 << n);
258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
260 unsigned int nhandled = 0;
261 unsigned int sub_irq;
267 mutex_lock(&chip->reg_lock);
268 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
269 mutex_unlock(&chip->reg_lock);
275 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
276 if (reg & (1 << n)) {
277 sub_irq = irq_find_mapping(chip->g1_irq.domain,
279 handle_nested_irq(sub_irq);
284 mutex_lock(&chip->reg_lock);
285 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
288 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
290 mutex_unlock(&chip->reg_lock);
293 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
294 } while (reg & ctl1);
297 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
300 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
302 struct mv88e6xxx_chip *chip = dev_id;
304 return mv88e6xxx_g1_irq_thread_work(chip);
307 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
309 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
311 mutex_lock(&chip->reg_lock);
314 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
316 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
317 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
321 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
326 reg |= (~chip->g1_irq.masked & mask);
328 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
333 mutex_unlock(&chip->reg_lock);
336 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
337 .name = "mv88e6xxx-g1",
338 .irq_mask = mv88e6xxx_g1_irq_mask,
339 .irq_unmask = mv88e6xxx_g1_irq_unmask,
340 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
341 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
344 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
346 irq_hw_number_t hwirq)
348 struct mv88e6xxx_chip *chip = d->host_data;
350 irq_set_chip_data(irq, d->host_data);
351 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
352 irq_set_noprobe(irq);
357 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
358 .map = mv88e6xxx_g1_irq_domain_map,
359 .xlate = irq_domain_xlate_twocell,
362 /* To be called with reg_lock held */
363 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
368 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
369 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
370 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
372 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
373 virq = irq_find_mapping(chip->g1_irq.domain, irq);
374 irq_dispose_mapping(virq);
377 irq_domain_remove(chip->g1_irq.domain);
380 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
383 * free_irq must be called without reg_lock taken because the irq
384 * handler takes this lock, too.
386 free_irq(chip->irq, chip);
388 mutex_lock(&chip->reg_lock);
389 mv88e6xxx_g1_irq_free_common(chip);
390 mutex_unlock(&chip->reg_lock);
393 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
398 chip->g1_irq.nirqs = chip->info->g1_irqs;
399 chip->g1_irq.domain = irq_domain_add_simple(
400 NULL, chip->g1_irq.nirqs, 0,
401 &mv88e6xxx_g1_irq_domain_ops, chip);
402 if (!chip->g1_irq.domain)
405 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
406 irq_create_mapping(chip->g1_irq.domain, irq);
408 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
409 chip->g1_irq.masked = ~0;
411 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
415 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
417 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
421 /* Reading the interrupt status clears (most of) them */
422 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
429 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
430 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
433 for (irq = 0; irq < 16; irq++) {
434 virq = irq_find_mapping(chip->g1_irq.domain, irq);
435 irq_dispose_mapping(virq);
438 irq_domain_remove(chip->g1_irq.domain);
443 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
445 static struct lock_class_key lock_key;
446 static struct lock_class_key request_key;
449 err = mv88e6xxx_g1_irq_setup_common(chip);
453 /* These lock classes tells lockdep that global 1 irqs are in
454 * a different category than their parent GPIO, so it won't
455 * report false recursion.
457 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
459 mutex_unlock(&chip->reg_lock);
460 err = request_threaded_irq(chip->irq, NULL,
461 mv88e6xxx_g1_irq_thread_fn,
462 IRQF_ONESHOT | IRQF_SHARED,
463 dev_name(chip->dev), chip);
464 mutex_lock(&chip->reg_lock);
466 mv88e6xxx_g1_irq_free_common(chip);
471 static void mv88e6xxx_irq_poll(struct kthread_work *work)
473 struct mv88e6xxx_chip *chip = container_of(work,
474 struct mv88e6xxx_chip,
476 mv88e6xxx_g1_irq_thread_work(chip);
478 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
479 msecs_to_jiffies(100));
482 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
486 err = mv88e6xxx_g1_irq_setup_common(chip);
490 kthread_init_delayed_work(&chip->irq_poll_work,
493 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
494 if (IS_ERR(chip->kworker))
495 return PTR_ERR(chip->kworker);
497 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
498 msecs_to_jiffies(100));
503 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
505 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
506 kthread_destroy_worker(chip->kworker);
508 mutex_lock(&chip->reg_lock);
509 mv88e6xxx_g1_irq_free_common(chip);
510 mutex_unlock(&chip->reg_lock);
513 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
517 for (i = 0; i < 16; i++) {
521 err = mv88e6xxx_read(chip, addr, reg, &val);
528 usleep_range(1000, 2000);
531 dev_err(chip->dev, "Timeout while waiting for switch\n");
535 /* Indirect write to single pointer-data register with an Update bit */
536 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
541 /* Wait until the previous operation is completed */
542 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
546 /* Set the Update bit to trigger a write operation */
547 val = BIT(15) | update;
549 return mv88e6xxx_write(chip, addr, reg, val);
552 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
553 int speed, int duplex, int pause,
554 phy_interface_t mode)
558 if (!chip->info->ops->port_set_link)
561 /* Port's MAC control must not be changed unless the link is down */
562 err = chip->info->ops->port_set_link(chip, port, 0);
566 if (chip->info->ops->port_set_speed) {
567 err = chip->info->ops->port_set_speed(chip, port, speed);
568 if (err && err != -EOPNOTSUPP)
572 if (chip->info->ops->port_set_pause) {
573 err = chip->info->ops->port_set_pause(chip, port, pause);
578 if (chip->info->ops->port_set_duplex) {
579 err = chip->info->ops->port_set_duplex(chip, port, duplex);
580 if (err && err != -EOPNOTSUPP)
584 if (chip->info->ops->port_set_rgmii_delay) {
585 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
586 if (err && err != -EOPNOTSUPP)
590 if (chip->info->ops->port_set_cmode) {
591 err = chip->info->ops->port_set_cmode(chip, port, mode);
592 if (err && err != -EOPNOTSUPP)
598 if (chip->info->ops->port_set_link(chip, port, link))
599 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
604 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
606 struct mv88e6xxx_chip *chip = ds->priv;
608 return port < chip->info->num_internal_phys;
611 /* We expect the switch to perform auto negotiation if there is a real
612 * phy. However, in the case of a fixed link phy, we force the port
613 * settings from the fixed link settings.
615 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
616 struct phy_device *phydev)
618 struct mv88e6xxx_chip *chip = ds->priv;
621 if (!phy_is_pseudo_fixed_link(phydev) &&
622 mv88e6xxx_phy_is_internal(ds, port))
625 mutex_lock(&chip->reg_lock);
626 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
627 phydev->duplex, phydev->pause,
629 mutex_unlock(&chip->reg_lock);
631 if (err && err != -EOPNOTSUPP)
632 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
635 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
637 struct phylink_link_state *state)
639 if (!phy_interface_mode_is_8023z(state->interface)) {
640 /* 10M and 100M are only supported in non-802.3z mode */
641 phylink_set(mask, 10baseT_Half);
642 phylink_set(mask, 10baseT_Full);
643 phylink_set(mask, 100baseT_Half);
644 phylink_set(mask, 100baseT_Full);
648 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
650 struct phylink_link_state *state)
652 /* FIXME: if the port is in 1000Base-X mode, then it only supports
653 * 1000M FD speeds. In this case, CMODE will indicate 5.
655 phylink_set(mask, 1000baseT_Full);
656 phylink_set(mask, 1000baseX_Full);
658 mv88e6065_phylink_validate(chip, port, mask, state);
661 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
663 struct phylink_link_state *state)
666 phylink_set(mask, 2500baseX_Full);
668 /* No ethtool bits for 200Mbps */
669 phylink_set(mask, 1000baseT_Full);
670 phylink_set(mask, 1000baseX_Full);
672 mv88e6065_phylink_validate(chip, port, mask, state);
675 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
677 struct phylink_link_state *state)
679 /* No ethtool bits for 200Mbps */
680 phylink_set(mask, 1000baseT_Full);
681 phylink_set(mask, 1000baseX_Full);
683 mv88e6065_phylink_validate(chip, port, mask, state);
686 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
688 struct phylink_link_state *state)
691 phylink_set(mask, 2500baseX_Full);
692 phylink_set(mask, 2500baseT_Full);
695 /* No ethtool bits for 200Mbps */
696 phylink_set(mask, 1000baseT_Full);
697 phylink_set(mask, 1000baseX_Full);
699 mv88e6065_phylink_validate(chip, port, mask, state);
702 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
704 struct phylink_link_state *state)
707 phylink_set(mask, 10000baseT_Full);
708 phylink_set(mask, 10000baseKR_Full);
711 mv88e6390_phylink_validate(chip, port, mask, state);
714 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
715 unsigned long *supported,
716 struct phylink_link_state *state)
718 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
719 struct mv88e6xxx_chip *chip = ds->priv;
721 /* Allow all the expected bits */
722 phylink_set(mask, Autoneg);
723 phylink_set(mask, Pause);
724 phylink_set_port_modes(mask);
726 if (chip->info->ops->phylink_validate)
727 chip->info->ops->phylink_validate(chip, port, mask, state);
729 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
730 bitmap_and(state->advertising, state->advertising, mask,
731 __ETHTOOL_LINK_MODE_MASK_NBITS);
733 /* We can only operate at 2500BaseX or 1000BaseX. If requested
734 * to advertise both, only report advertising at 2500BaseX.
736 phylink_helper_basex_speed(state);
739 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
740 struct phylink_link_state *state)
742 struct mv88e6xxx_chip *chip = ds->priv;
745 mutex_lock(&chip->reg_lock);
746 if (chip->info->ops->port_link_state)
747 err = chip->info->ops->port_link_state(chip, port, state);
750 mutex_unlock(&chip->reg_lock);
755 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
757 const struct phylink_link_state *state)
759 struct mv88e6xxx_chip *chip = ds->priv;
760 int speed, duplex, link, pause, err;
762 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
765 if (mode == MLO_AN_FIXED) {
766 link = LINK_FORCED_UP;
767 speed = state->speed;
768 duplex = state->duplex;
769 } else if (!mv88e6xxx_phy_is_internal(ds, port)) {
771 speed = state->speed;
772 duplex = state->duplex;
774 speed = SPEED_UNFORCED;
775 duplex = DUPLEX_UNFORCED;
776 link = LINK_UNFORCED;
778 pause = !!phylink_test(state->advertising, Pause);
780 mutex_lock(&chip->reg_lock);
781 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
783 mutex_unlock(&chip->reg_lock);
785 if (err && err != -EOPNOTSUPP)
786 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
789 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
791 struct mv88e6xxx_chip *chip = ds->priv;
794 mutex_lock(&chip->reg_lock);
795 err = chip->info->ops->port_set_link(chip, port, link);
796 mutex_unlock(&chip->reg_lock);
799 dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
802 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
804 phy_interface_t interface)
806 if (mode == MLO_AN_FIXED)
807 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
810 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
811 unsigned int mode, phy_interface_t interface,
812 struct phy_device *phydev)
814 if (mode == MLO_AN_FIXED)
815 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
818 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
820 if (!chip->info->ops->stats_snapshot)
823 return chip->info->ops->stats_snapshot(chip, port);
826 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
827 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
828 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
829 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
830 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
831 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
832 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
833 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
834 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
835 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
836 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
837 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
838 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
839 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
840 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
841 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
842 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
843 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
844 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
845 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
846 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
847 { "single", 4, 0x14, STATS_TYPE_BANK0, },
848 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
849 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
850 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
851 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
852 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
853 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
854 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
855 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
856 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
857 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
858 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
859 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
860 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
861 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
862 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
863 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
864 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
865 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
866 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
867 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
868 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
869 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
870 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
871 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
872 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
873 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
874 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
875 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
876 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
877 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
878 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
879 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
880 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
881 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
882 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
883 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
884 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
885 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
888 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
889 struct mv88e6xxx_hw_stat *s,
890 int port, u16 bank1_select,
900 case STATS_TYPE_PORT:
901 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
907 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
913 case STATS_TYPE_BANK1:
916 case STATS_TYPE_BANK0:
917 reg |= s->reg | histogram;
918 mv88e6xxx_g1_stats_read(chip, reg, &low);
920 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
925 value = (((u64)high) << 32) | low;
929 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
930 uint8_t *data, int types)
932 struct mv88e6xxx_hw_stat *stat;
935 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
936 stat = &mv88e6xxx_hw_stats[i];
937 if (stat->type & types) {
938 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
947 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
950 return mv88e6xxx_stats_get_strings(chip, data,
951 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
954 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
957 return mv88e6xxx_stats_get_strings(chip, data,
958 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
961 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
962 "atu_member_violation",
963 "atu_miss_violation",
964 "atu_full_violation",
965 "vtu_member_violation",
966 "vtu_miss_violation",
969 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
973 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
974 strlcpy(data + i * ETH_GSTRING_LEN,
975 mv88e6xxx_atu_vtu_stats_strings[i],
979 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
980 u32 stringset, uint8_t *data)
982 struct mv88e6xxx_chip *chip = ds->priv;
985 if (stringset != ETH_SS_STATS)
988 mutex_lock(&chip->reg_lock);
990 if (chip->info->ops->stats_get_strings)
991 count = chip->info->ops->stats_get_strings(chip, data);
993 if (chip->info->ops->serdes_get_strings) {
994 data += count * ETH_GSTRING_LEN;
995 count = chip->info->ops->serdes_get_strings(chip, port, data);
998 data += count * ETH_GSTRING_LEN;
999 mv88e6xxx_atu_vtu_get_strings(data);
1001 mutex_unlock(&chip->reg_lock);
1004 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1007 struct mv88e6xxx_hw_stat *stat;
1010 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1011 stat = &mv88e6xxx_hw_stats[i];
1012 if (stat->type & types)
1018 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1020 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1024 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1026 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1030 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1032 struct mv88e6xxx_chip *chip = ds->priv;
1033 int serdes_count = 0;
1036 if (sset != ETH_SS_STATS)
1039 mutex_lock(&chip->reg_lock);
1040 if (chip->info->ops->stats_get_sset_count)
1041 count = chip->info->ops->stats_get_sset_count(chip);
1045 if (chip->info->ops->serdes_get_sset_count)
1046 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1048 if (serdes_count < 0) {
1049 count = serdes_count;
1052 count += serdes_count;
1053 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1056 mutex_unlock(&chip->reg_lock);
1061 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1062 uint64_t *data, int types,
1063 u16 bank1_select, u16 histogram)
1065 struct mv88e6xxx_hw_stat *stat;
1068 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1069 stat = &mv88e6xxx_hw_stats[i];
1070 if (stat->type & types) {
1071 mutex_lock(&chip->reg_lock);
1072 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1075 mutex_unlock(&chip->reg_lock);
1083 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1086 return mv88e6xxx_stats_get_stats(chip, port, data,
1087 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1088 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1091 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1094 return mv88e6xxx_stats_get_stats(chip, port, data,
1095 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1096 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1097 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1100 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1103 return mv88e6xxx_stats_get_stats(chip, port, data,
1104 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1105 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1109 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1112 *data++ = chip->ports[port].atu_member_violation;
1113 *data++ = chip->ports[port].atu_miss_violation;
1114 *data++ = chip->ports[port].atu_full_violation;
1115 *data++ = chip->ports[port].vtu_member_violation;
1116 *data++ = chip->ports[port].vtu_miss_violation;
1119 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1124 if (chip->info->ops->stats_get_stats)
1125 count = chip->info->ops->stats_get_stats(chip, port, data);
1127 mutex_lock(&chip->reg_lock);
1128 if (chip->info->ops->serdes_get_stats) {
1130 count = chip->info->ops->serdes_get_stats(chip, port, data);
1133 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1134 mutex_unlock(&chip->reg_lock);
1137 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1140 struct mv88e6xxx_chip *chip = ds->priv;
1143 mutex_lock(&chip->reg_lock);
1145 ret = mv88e6xxx_stats_snapshot(chip, port);
1146 mutex_unlock(&chip->reg_lock);
1151 mv88e6xxx_get_stats(chip, port, data);
1155 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1157 return 32 * sizeof(u16);
1160 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1161 struct ethtool_regs *regs, void *_p)
1163 struct mv88e6xxx_chip *chip = ds->priv;
1169 regs->version = chip->info->prod_num;
1171 memset(p, 0xff, 32 * sizeof(u16));
1173 mutex_lock(&chip->reg_lock);
1175 for (i = 0; i < 32; i++) {
1177 err = mv88e6xxx_port_read(chip, port, i, ®);
1182 mutex_unlock(&chip->reg_lock);
1185 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1186 struct ethtool_eee *e)
1188 /* Nothing to do on the port's MAC */
1192 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1193 struct ethtool_eee *e)
1195 /* Nothing to do on the port's MAC */
1199 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1201 struct dsa_switch *ds = NULL;
1202 struct net_device *br;
1206 if (dev < DSA_MAX_SWITCHES)
1207 ds = chip->ds->dst->ds[dev];
1209 /* Prevent frames from unknown switch or port */
1210 if (!ds || port >= ds->num_ports)
1213 /* Frames from DSA links and CPU ports can egress any local port */
1214 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1215 return mv88e6xxx_port_mask(chip);
1217 br = ds->ports[port].bridge_dev;
1220 /* Frames from user ports can egress any local DSA links and CPU ports,
1221 * as well as any local member of their bridge group.
1223 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1224 if (dsa_is_cpu_port(chip->ds, i) ||
1225 dsa_is_dsa_port(chip->ds, i) ||
1226 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1232 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1234 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1236 /* prevent frames from going back out of the port they came in on */
1237 output_ports &= ~BIT(port);
1239 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1242 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1245 struct mv88e6xxx_chip *chip = ds->priv;
1248 mutex_lock(&chip->reg_lock);
1249 err = mv88e6xxx_port_set_state(chip, port, state);
1250 mutex_unlock(&chip->reg_lock);
1253 dev_err(ds->dev, "p%d: failed to update state\n", port);
1256 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1260 if (chip->info->ops->ieee_pri_map) {
1261 err = chip->info->ops->ieee_pri_map(chip);
1266 if (chip->info->ops->ip_pri_map) {
1267 err = chip->info->ops->ip_pri_map(chip);
1275 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1280 if (!chip->info->global2_addr)
1283 /* Initialize the routing port to the 32 possible target devices */
1284 for (target = 0; target < 32; target++) {
1286 if (target < DSA_MAX_SWITCHES)
1287 if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
1288 port = chip->ds->rtable[target];
1290 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1295 if (chip->info->ops->set_cascade_port) {
1296 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1297 err = chip->info->ops->set_cascade_port(chip, port);
1302 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1309 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1311 /* Clear all trunk masks and mapping */
1312 if (chip->info->global2_addr)
1313 return mv88e6xxx_g2_trunk_clear(chip);
1318 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1320 if (chip->info->ops->rmu_disable)
1321 return chip->info->ops->rmu_disable(chip);
1326 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1328 if (chip->info->ops->pot_clear)
1329 return chip->info->ops->pot_clear(chip);
1334 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1336 if (chip->info->ops->mgmt_rsvd2cpu)
1337 return chip->info->ops->mgmt_rsvd2cpu(chip);
1342 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1346 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1350 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1354 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1357 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1362 if (!chip->info->ops->irl_init_all)
1365 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1366 /* Disable ingress rate limiting by resetting all per port
1367 * ingress rate limit resources to their initial state.
1369 err = chip->info->ops->irl_init_all(chip, port);
1377 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1379 if (chip->info->ops->set_switch_mac) {
1382 eth_random_addr(addr);
1384 return chip->info->ops->set_switch_mac(chip, addr);
1390 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1394 if (!mv88e6xxx_has_pvt(chip))
1397 /* Skip the local source device, which uses in-chip port VLAN */
1398 if (dev != chip->ds->index)
1399 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1401 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1404 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1409 if (!mv88e6xxx_has_pvt(chip))
1412 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1413 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1415 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1419 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1420 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1421 err = mv88e6xxx_pvt_map(chip, dev, port);
1430 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1432 struct mv88e6xxx_chip *chip = ds->priv;
1435 mutex_lock(&chip->reg_lock);
1436 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1437 mutex_unlock(&chip->reg_lock);
1440 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1443 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1445 if (!chip->info->max_vid)
1448 return mv88e6xxx_g1_vtu_flush(chip);
1451 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1452 struct mv88e6xxx_vtu_entry *entry)
1454 if (!chip->info->ops->vtu_getnext)
1457 return chip->info->ops->vtu_getnext(chip, entry);
1460 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1461 struct mv88e6xxx_vtu_entry *entry)
1463 if (!chip->info->ops->vtu_loadpurge)
1466 return chip->info->ops->vtu_loadpurge(chip, entry);
1469 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1471 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1472 struct mv88e6xxx_vtu_entry vlan = {
1473 .vid = chip->info->max_vid,
1477 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1479 /* Set every FID bit used by the (un)bridged ports */
1480 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1481 err = mv88e6xxx_port_get_fid(chip, i, fid);
1485 set_bit(*fid, fid_bitmap);
1488 /* Set every FID bit used by the VLAN entries */
1490 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1497 set_bit(vlan.fid, fid_bitmap);
1498 } while (vlan.vid < chip->info->max_vid);
1500 /* The reset value 0x000 is used to indicate that multiple address
1501 * databases are not needed. Return the next positive available.
1503 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1504 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1507 /* Clear the database */
1508 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1511 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1512 struct mv88e6xxx_vtu_entry *entry, bool new)
1519 entry->vid = vid - 1;
1520 entry->valid = false;
1522 err = mv88e6xxx_vtu_getnext(chip, entry);
1526 if (entry->vid == vid && entry->valid)
1532 /* Initialize a fresh VLAN entry */
1533 memset(entry, 0, sizeof(*entry));
1534 entry->valid = true;
1537 /* Exclude all ports */
1538 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1540 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1542 return mv88e6xxx_atu_new(chip, &entry->fid);
1545 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1549 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1550 u16 vid_begin, u16 vid_end)
1552 struct mv88e6xxx_chip *chip = ds->priv;
1553 struct mv88e6xxx_vtu_entry vlan = {
1554 .vid = vid_begin - 1,
1558 /* DSA and CPU ports have to be members of multiple vlans */
1559 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1565 mutex_lock(&chip->reg_lock);
1568 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1575 if (vlan.vid > vid_end)
1578 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1579 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1582 if (!ds->ports[i].slave)
1585 if (vlan.member[i] ==
1586 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1589 if (dsa_to_port(ds, i)->bridge_dev ==
1590 ds->ports[port].bridge_dev)
1591 break; /* same bridge, check next VLAN */
1593 if (!dsa_to_port(ds, i)->bridge_dev)
1596 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1598 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1602 } while (vlan.vid < vid_end);
1605 mutex_unlock(&chip->reg_lock);
1610 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1611 bool vlan_filtering)
1613 struct mv88e6xxx_chip *chip = ds->priv;
1614 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1615 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1618 if (!chip->info->max_vid)
1621 mutex_lock(&chip->reg_lock);
1622 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1623 mutex_unlock(&chip->reg_lock);
1629 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1630 const struct switchdev_obj_port_vlan *vlan)
1632 struct mv88e6xxx_chip *chip = ds->priv;
1635 if (!chip->info->max_vid)
1638 /* If the requested port doesn't belong to the same bridge as the VLAN
1639 * members, do not support it (yet) and fallback to software VLAN.
1641 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1646 /* We don't need any dynamic resource from the kernel (yet),
1647 * so skip the prepare phase.
1652 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1653 const unsigned char *addr, u16 vid,
1656 struct mv88e6xxx_vtu_entry vlan;
1657 struct mv88e6xxx_atu_entry entry;
1660 /* Null VLAN ID corresponds to the port private database */
1662 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1664 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1668 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1669 ether_addr_copy(entry.mac, addr);
1670 eth_addr_dec(entry.mac);
1672 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1676 /* Initialize a fresh ATU entry if it isn't found */
1677 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1678 !ether_addr_equal(entry.mac, addr)) {
1679 memset(&entry, 0, sizeof(entry));
1680 ether_addr_copy(entry.mac, addr);
1683 /* Purge the ATU entry only if no port is using it anymore */
1684 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1685 entry.portvec &= ~BIT(port);
1687 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1689 entry.portvec |= BIT(port);
1690 entry.state = state;
1693 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1696 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1699 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1700 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1702 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1705 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1710 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1711 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1719 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1722 struct mv88e6xxx_vtu_entry vlan;
1725 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1729 vlan.member[port] = member;
1731 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1735 return mv88e6xxx_broadcast_setup(chip, vid);
1738 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1739 const struct switchdev_obj_port_vlan *vlan)
1741 struct mv88e6xxx_chip *chip = ds->priv;
1742 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1743 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1747 if (!chip->info->max_vid)
1750 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1751 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1753 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1755 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1757 mutex_lock(&chip->reg_lock);
1759 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1760 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1761 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1762 vid, untagged ? 'u' : 't');
1764 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1765 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1768 mutex_unlock(&chip->reg_lock);
1771 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1774 struct mv88e6xxx_vtu_entry vlan;
1777 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1781 /* Tell switchdev if this VLAN is handled in software */
1782 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1785 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1787 /* keep the VLAN unless all ports are excluded */
1789 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1790 if (vlan.member[i] !=
1791 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1797 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1801 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1804 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1805 const struct switchdev_obj_port_vlan *vlan)
1807 struct mv88e6xxx_chip *chip = ds->priv;
1811 if (!chip->info->max_vid)
1814 mutex_lock(&chip->reg_lock);
1816 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1820 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1821 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1826 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1833 mutex_unlock(&chip->reg_lock);
1838 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1839 const unsigned char *addr, u16 vid)
1841 struct mv88e6xxx_chip *chip = ds->priv;
1844 mutex_lock(&chip->reg_lock);
1845 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1846 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1847 mutex_unlock(&chip->reg_lock);
1852 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1853 const unsigned char *addr, u16 vid)
1855 struct mv88e6xxx_chip *chip = ds->priv;
1858 mutex_lock(&chip->reg_lock);
1859 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1860 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1861 mutex_unlock(&chip->reg_lock);
1866 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1867 u16 fid, u16 vid, int port,
1868 dsa_fdb_dump_cb_t *cb, void *data)
1870 struct mv88e6xxx_atu_entry addr;
1874 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1875 eth_broadcast_addr(addr.mac);
1878 mutex_lock(&chip->reg_lock);
1879 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1880 mutex_unlock(&chip->reg_lock);
1884 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1887 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1890 if (!is_unicast_ether_addr(addr.mac))
1893 is_static = (addr.state ==
1894 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1895 err = cb(addr.mac, vid, is_static, data);
1898 } while (!is_broadcast_ether_addr(addr.mac));
1903 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1904 dsa_fdb_dump_cb_t *cb, void *data)
1906 struct mv88e6xxx_vtu_entry vlan = {
1907 .vid = chip->info->max_vid,
1912 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1913 mutex_lock(&chip->reg_lock);
1914 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1915 mutex_unlock(&chip->reg_lock);
1920 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1924 /* Dump VLANs' Filtering Information Databases */
1926 mutex_lock(&chip->reg_lock);
1927 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1928 mutex_unlock(&chip->reg_lock);
1935 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1939 } while (vlan.vid < chip->info->max_vid);
1944 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1945 dsa_fdb_dump_cb_t *cb, void *data)
1947 struct mv88e6xxx_chip *chip = ds->priv;
1949 return mv88e6xxx_port_db_dump(chip, port, cb, data);
1952 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1953 struct net_device *br)
1955 struct dsa_switch *ds;
1960 /* Remap the Port VLAN of each local bridge group member */
1961 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1962 if (chip->ds->ports[port].bridge_dev == br) {
1963 err = mv88e6xxx_port_vlan_map(chip, port);
1969 if (!mv88e6xxx_has_pvt(chip))
1972 /* Remap the Port VLAN of each cross-chip bridge group member */
1973 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1974 ds = chip->ds->dst->ds[dev];
1978 for (port = 0; port < ds->num_ports; ++port) {
1979 if (ds->ports[port].bridge_dev == br) {
1980 err = mv88e6xxx_pvt_map(chip, dev, port);
1990 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1991 struct net_device *br)
1993 struct mv88e6xxx_chip *chip = ds->priv;
1996 mutex_lock(&chip->reg_lock);
1997 err = mv88e6xxx_bridge_map(chip, br);
1998 mutex_unlock(&chip->reg_lock);
2003 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2004 struct net_device *br)
2006 struct mv88e6xxx_chip *chip = ds->priv;
2008 mutex_lock(&chip->reg_lock);
2009 if (mv88e6xxx_bridge_map(chip, br) ||
2010 mv88e6xxx_port_vlan_map(chip, port))
2011 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2012 mutex_unlock(&chip->reg_lock);
2015 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
2016 int port, struct net_device *br)
2018 struct mv88e6xxx_chip *chip = ds->priv;
2021 if (!mv88e6xxx_has_pvt(chip))
2024 mutex_lock(&chip->reg_lock);
2025 err = mv88e6xxx_pvt_map(chip, dev, port);
2026 mutex_unlock(&chip->reg_lock);
2031 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
2032 int port, struct net_device *br)
2034 struct mv88e6xxx_chip *chip = ds->priv;
2036 if (!mv88e6xxx_has_pvt(chip))
2039 mutex_lock(&chip->reg_lock);
2040 if (mv88e6xxx_pvt_map(chip, dev, port))
2041 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2042 mutex_unlock(&chip->reg_lock);
2045 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2047 if (chip->info->ops->reset)
2048 return chip->info->ops->reset(chip);
2053 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2055 struct gpio_desc *gpiod = chip->reset;
2057 /* If there is a GPIO connected to the reset pin, toggle it */
2059 gpiod_set_value_cansleep(gpiod, 1);
2060 usleep_range(10000, 20000);
2061 gpiod_set_value_cansleep(gpiod, 0);
2062 usleep_range(10000, 20000);
2066 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2070 /* Set all ports to the Disabled state */
2071 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2072 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2077 /* Wait for transmit queues to drain,
2078 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2080 usleep_range(2000, 4000);
2085 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2089 err = mv88e6xxx_disable_ports(chip);
2093 mv88e6xxx_hardware_reset(chip);
2095 return mv88e6xxx_software_reset(chip);
2098 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2099 enum mv88e6xxx_frame_mode frame,
2100 enum mv88e6xxx_egress_mode egress, u16 etype)
2104 if (!chip->info->ops->port_set_frame_mode)
2107 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2111 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2115 if (chip->info->ops->port_set_ether_type)
2116 return chip->info->ops->port_set_ether_type(chip, port, etype);
2121 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2123 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2124 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2125 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2128 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2130 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2131 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2132 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2135 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2137 return mv88e6xxx_set_port_mode(chip, port,
2138 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2139 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2143 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2145 if (dsa_is_dsa_port(chip->ds, port))
2146 return mv88e6xxx_set_port_mode_dsa(chip, port);
2148 if (dsa_is_user_port(chip->ds, port))
2149 return mv88e6xxx_set_port_mode_normal(chip, port);
2151 /* Setup CPU port mode depending on its supported tag format */
2152 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2153 return mv88e6xxx_set_port_mode_dsa(chip, port);
2155 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2156 return mv88e6xxx_set_port_mode_edsa(chip, port);
2161 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2163 bool message = dsa_is_dsa_port(chip->ds, port);
2165 return mv88e6xxx_port_set_message_port(chip, port, message);
2168 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2170 struct dsa_switch *ds = chip->ds;
2173 /* Upstream ports flood frames with unknown unicast or multicast DA */
2174 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2175 if (chip->info->ops->port_set_egress_floods)
2176 return chip->info->ops->port_set_egress_floods(chip, port,
2182 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2185 if (chip->info->ops->serdes_power)
2186 return chip->info->ops->serdes_power(chip, port, on);
2191 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2193 struct dsa_switch *ds = chip->ds;
2197 upstream_port = dsa_upstream_port(ds, port);
2198 if (chip->info->ops->port_set_upstream_port) {
2199 err = chip->info->ops->port_set_upstream_port(chip, port,
2205 if (port == upstream_port) {
2206 if (chip->info->ops->set_cpu_port) {
2207 err = chip->info->ops->set_cpu_port(chip,
2213 if (chip->info->ops->set_egress_port) {
2214 err = chip->info->ops->set_egress_port(chip,
2224 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2226 struct dsa_switch *ds = chip->ds;
2230 chip->ports[port].chip = chip;
2231 chip->ports[port].port = port;
2233 /* MAC Forcing register: don't force link, speed, duplex or flow control
2234 * state to any particular values on physical ports, but force the CPU
2235 * port and all DSA ports to their maximum bandwidth and full duplex.
2237 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2238 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2239 SPEED_MAX, DUPLEX_FULL,
2241 PHY_INTERFACE_MODE_NA);
2243 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2244 SPEED_UNFORCED, DUPLEX_UNFORCED,
2246 PHY_INTERFACE_MODE_NA);
2250 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2251 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2252 * tunneling, determine priority by looking at 802.1p and IP
2253 * priority fields (IP prio has precedence), and set STP state
2256 * If this is the CPU link, use DSA or EDSA tagging depending
2257 * on which tagging mode was configured.
2259 * If this is a link to another switch, use DSA tagging mode.
2261 * If this is the upstream port for this switch, enable
2262 * forwarding of unknown unicasts and multicasts.
2264 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2265 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2266 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2267 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2271 err = mv88e6xxx_setup_port_mode(chip, port);
2275 err = mv88e6xxx_setup_egress_floods(chip, port);
2279 /* Enable the SERDES interface for DSA and CPU ports. Normal
2280 * ports SERDES are enabled when the port is enabled, thus
2281 * saving a bit of power.
2283 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
2284 err = mv88e6xxx_serdes_power(chip, port, true);
2289 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2290 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2291 * untagged frames on this port, do a destination address lookup on all
2292 * received packets as usual, disable ARP mirroring and don't send a
2293 * copy of all transmitted/received frames on this port to the CPU.
2295 err = mv88e6xxx_port_set_map_da(chip, port);
2299 err = mv88e6xxx_setup_upstream_port(chip, port);
2303 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2304 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2308 if (chip->info->ops->port_set_jumbo_size) {
2309 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2314 /* Port Association Vector: when learning source addresses
2315 * of packets, add the address to the address database using
2316 * a port bitmap that has only the bit for this port set and
2317 * the other bits clear.
2320 /* Disable learning for CPU port */
2321 if (dsa_is_cpu_port(ds, port))
2324 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2329 /* Egress rate control 2: disable egress rate control. */
2330 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2335 if (chip->info->ops->port_pause_limit) {
2336 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2341 if (chip->info->ops->port_disable_learn_limit) {
2342 err = chip->info->ops->port_disable_learn_limit(chip, port);
2347 if (chip->info->ops->port_disable_pri_override) {
2348 err = chip->info->ops->port_disable_pri_override(chip, port);
2353 if (chip->info->ops->port_tag_remap) {
2354 err = chip->info->ops->port_tag_remap(chip, port);
2359 if (chip->info->ops->port_egress_rate_limiting) {
2360 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2365 err = mv88e6xxx_setup_message_port(chip, port);
2369 /* Port based VLAN map: give each port the same default address
2370 * database, and allow bidirectional communication between the
2371 * CPU and DSA port(s), and the other ports.
2373 err = mv88e6xxx_port_set_fid(chip, port, 0);
2377 err = mv88e6xxx_port_vlan_map(chip, port);
2381 /* Default VLAN ID and priority: don't set a default VLAN
2382 * ID, and set the default packet priority to zero.
2384 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2387 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2388 struct phy_device *phydev)
2390 struct mv88e6xxx_chip *chip = ds->priv;
2393 mutex_lock(&chip->reg_lock);
2395 err = mv88e6xxx_serdes_power(chip, port, true);
2397 if (!err && chip->info->ops->serdes_irq_setup)
2398 err = chip->info->ops->serdes_irq_setup(chip, port);
2400 mutex_unlock(&chip->reg_lock);
2405 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2407 struct mv88e6xxx_chip *chip = ds->priv;
2409 mutex_lock(&chip->reg_lock);
2411 if (chip->info->ops->serdes_irq_free)
2412 chip->info->ops->serdes_irq_free(chip, port);
2414 if (mv88e6xxx_serdes_power(chip, port, false))
2415 dev_err(chip->dev, "failed to power off SERDES\n");
2417 mutex_unlock(&chip->reg_lock);
2420 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2421 unsigned int ageing_time)
2423 struct mv88e6xxx_chip *chip = ds->priv;
2426 mutex_lock(&chip->reg_lock);
2427 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2428 mutex_unlock(&chip->reg_lock);
2433 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2437 /* Initialize the statistics unit */
2438 if (chip->info->ops->stats_set_histogram) {
2439 err = chip->info->ops->stats_set_histogram(chip);
2444 return mv88e6xxx_g1_stats_clear(chip);
2447 /* The mv88e6390 has some hidden registers used for debug and
2448 * development. The errata also makes use of them.
2450 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2456 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2457 PORT_RESERVED_1A, val);
2461 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE |
2462 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2465 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2466 PORT_RESERVED_1A, ctrl);
2469 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2471 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2472 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2476 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2482 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ |
2483 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2486 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2487 PORT_RESERVED_1A, ctrl);
2491 err = mv88e6390_hidden_wait(chip);
2495 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2496 PORT_RESERVED_1A, val);
2499 /* Check if the errata has already been applied. */
2500 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2506 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2507 err = mv88e6390_hidden_read(chip, port, 0, &val);
2510 "Error reading hidden register: %d\n", err);
2520 /* The 6390 copper ports have an errata which require poking magic
2521 * values into undocumented hidden registers and then performing a
2524 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2529 if (mv88e6390_setup_errata_applied(chip))
2532 /* Set the ports into blocking mode */
2533 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2534 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2539 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2540 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
2545 return mv88e6xxx_software_reset(chip);
2548 static int mv88e6xxx_setup(struct dsa_switch *ds)
2550 struct mv88e6xxx_chip *chip = ds->priv;
2556 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2558 mutex_lock(&chip->reg_lock);
2560 if (chip->info->ops->setup_errata) {
2561 err = chip->info->ops->setup_errata(chip);
2566 /* Cache the cmode of each port. */
2567 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2568 if (chip->info->ops->port_get_cmode) {
2569 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2573 chip->ports[i].cmode = cmode;
2577 /* Setup Switch Port Registers */
2578 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2579 if (dsa_is_unused_port(ds, i))
2582 err = mv88e6xxx_setup_port(chip, i);
2587 err = mv88e6xxx_irl_setup(chip);
2591 err = mv88e6xxx_mac_setup(chip);
2595 err = mv88e6xxx_phy_setup(chip);
2599 err = mv88e6xxx_vtu_setup(chip);
2603 err = mv88e6xxx_pvt_setup(chip);
2607 err = mv88e6xxx_atu_setup(chip);
2611 err = mv88e6xxx_broadcast_setup(chip, 0);
2615 err = mv88e6xxx_pot_setup(chip);
2619 err = mv88e6xxx_rmu_setup(chip);
2623 err = mv88e6xxx_rsvd2cpu_setup(chip);
2627 err = mv88e6xxx_trunk_setup(chip);
2631 err = mv88e6xxx_devmap_setup(chip);
2635 err = mv88e6xxx_pri_setup(chip);
2639 /* Setup PTP Hardware Clock and timestamping */
2640 if (chip->info->ptp_support) {
2641 err = mv88e6xxx_ptp_setup(chip);
2645 err = mv88e6xxx_hwtstamp_setup(chip);
2650 err = mv88e6xxx_stats_setup(chip);
2655 mutex_unlock(&chip->reg_lock);
2660 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2662 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2663 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2667 if (!chip->info->ops->phy_read)
2670 mutex_lock(&chip->reg_lock);
2671 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2672 mutex_unlock(&chip->reg_lock);
2674 if (reg == MII_PHYSID2) {
2675 /* Some internal PHYs don't have a model number. */
2676 if (chip->info->family != MV88E6XXX_FAMILY_6165)
2677 /* Then there is the 6165 family. It gets is
2678 * PHYs correct. But it can also have two
2679 * SERDES interfaces in the PHY address
2680 * space. And these don't have a model
2681 * number. But they are not PHYs, so we don't
2682 * want to give them something a PHY driver
2685 * Use the mv88e6390 family model number
2686 * instead, for anything which really could be
2690 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2693 return err ? err : val;
2696 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2698 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2699 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2702 if (!chip->info->ops->phy_write)
2705 mutex_lock(&chip->reg_lock);
2706 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2707 mutex_unlock(&chip->reg_lock);
2712 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2713 struct device_node *np,
2717 struct mv88e6xxx_mdio_bus *mdio_bus;
2718 struct mii_bus *bus;
2722 mutex_lock(&chip->reg_lock);
2723 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2724 mutex_unlock(&chip->reg_lock);
2730 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2734 mdio_bus = bus->priv;
2735 mdio_bus->bus = bus;
2736 mdio_bus->chip = chip;
2737 INIT_LIST_HEAD(&mdio_bus->list);
2738 mdio_bus->external = external;
2741 bus->name = np->full_name;
2742 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2744 bus->name = "mv88e6xxx SMI";
2745 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2748 bus->read = mv88e6xxx_mdio_read;
2749 bus->write = mv88e6xxx_mdio_write;
2750 bus->parent = chip->dev;
2753 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2758 err = of_mdiobus_register(bus, np);
2760 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2761 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2766 list_add_tail(&mdio_bus->list, &chip->mdios);
2768 list_add(&mdio_bus->list, &chip->mdios);
2773 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2774 { .compatible = "marvell,mv88e6xxx-mdio-external",
2775 .data = (void *)true },
2779 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2782 struct mv88e6xxx_mdio_bus *mdio_bus;
2783 struct mii_bus *bus;
2785 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2786 bus = mdio_bus->bus;
2788 if (!mdio_bus->external)
2789 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2791 mdiobus_unregister(bus);
2795 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2796 struct device_node *np)
2798 const struct of_device_id *match;
2799 struct device_node *child;
2802 /* Always register one mdio bus for the internal/default mdio
2803 * bus. This maybe represented in the device tree, but is
2806 child = of_get_child_by_name(np, "mdio");
2807 err = mv88e6xxx_mdio_register(chip, child, false);
2811 /* Walk the device tree, and see if there are any other nodes
2812 * which say they are compatible with the external mdio
2815 for_each_available_child_of_node(np, child) {
2816 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2818 err = mv88e6xxx_mdio_register(chip, child, true);
2820 mv88e6xxx_mdios_unregister(chip);
2829 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2831 struct mv88e6xxx_chip *chip = ds->priv;
2833 return chip->eeprom_len;
2836 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2837 struct ethtool_eeprom *eeprom, u8 *data)
2839 struct mv88e6xxx_chip *chip = ds->priv;
2842 if (!chip->info->ops->get_eeprom)
2845 mutex_lock(&chip->reg_lock);
2846 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2847 mutex_unlock(&chip->reg_lock);
2852 eeprom->magic = 0xc3ec4951;
2857 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2858 struct ethtool_eeprom *eeprom, u8 *data)
2860 struct mv88e6xxx_chip *chip = ds->priv;
2863 if (!chip->info->ops->set_eeprom)
2866 if (eeprom->magic != 0xc3ec4951)
2869 mutex_lock(&chip->reg_lock);
2870 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2871 mutex_unlock(&chip->reg_lock);
2876 static const struct mv88e6xxx_ops mv88e6085_ops = {
2877 /* MV88E6XXX_FAMILY_6097 */
2878 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2879 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2880 .irl_init_all = mv88e6352_g2_irl_init_all,
2881 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2882 .phy_read = mv88e6185_phy_ppu_read,
2883 .phy_write = mv88e6185_phy_ppu_write,
2884 .port_set_link = mv88e6xxx_port_set_link,
2885 .port_set_duplex = mv88e6xxx_port_set_duplex,
2886 .port_set_speed = mv88e6185_port_set_speed,
2887 .port_tag_remap = mv88e6095_port_tag_remap,
2888 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2889 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2890 .port_set_ether_type = mv88e6351_port_set_ether_type,
2891 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2892 .port_pause_limit = mv88e6097_port_pause_limit,
2893 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2894 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2895 .port_link_state = mv88e6352_port_link_state,
2896 .port_get_cmode = mv88e6185_port_get_cmode,
2897 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2898 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2899 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2900 .stats_get_strings = mv88e6095_stats_get_strings,
2901 .stats_get_stats = mv88e6095_stats_get_stats,
2902 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2903 .set_egress_port = mv88e6095_g1_set_egress_port,
2904 .watchdog_ops = &mv88e6097_watchdog_ops,
2905 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2906 .pot_clear = mv88e6xxx_g2_pot_clear,
2907 .ppu_enable = mv88e6185_g1_ppu_enable,
2908 .ppu_disable = mv88e6185_g1_ppu_disable,
2909 .reset = mv88e6185_g1_reset,
2910 .rmu_disable = mv88e6085_g1_rmu_disable,
2911 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2912 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2913 .phylink_validate = mv88e6185_phylink_validate,
2916 static const struct mv88e6xxx_ops mv88e6095_ops = {
2917 /* MV88E6XXX_FAMILY_6095 */
2918 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2919 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2920 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2921 .phy_read = mv88e6185_phy_ppu_read,
2922 .phy_write = mv88e6185_phy_ppu_write,
2923 .port_set_link = mv88e6xxx_port_set_link,
2924 .port_set_duplex = mv88e6xxx_port_set_duplex,
2925 .port_set_speed = mv88e6185_port_set_speed,
2926 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2927 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2928 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2929 .port_link_state = mv88e6185_port_link_state,
2930 .port_get_cmode = mv88e6185_port_get_cmode,
2931 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2932 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2933 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2934 .stats_get_strings = mv88e6095_stats_get_strings,
2935 .stats_get_stats = mv88e6095_stats_get_stats,
2936 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2937 .ppu_enable = mv88e6185_g1_ppu_enable,
2938 .ppu_disable = mv88e6185_g1_ppu_disable,
2939 .reset = mv88e6185_g1_reset,
2940 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2941 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2942 .phylink_validate = mv88e6185_phylink_validate,
2945 static const struct mv88e6xxx_ops mv88e6097_ops = {
2946 /* MV88E6XXX_FAMILY_6097 */
2947 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2948 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2949 .irl_init_all = mv88e6352_g2_irl_init_all,
2950 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2951 .phy_read = mv88e6xxx_g2_smi_phy_read,
2952 .phy_write = mv88e6xxx_g2_smi_phy_write,
2953 .port_set_link = mv88e6xxx_port_set_link,
2954 .port_set_duplex = mv88e6xxx_port_set_duplex,
2955 .port_set_speed = mv88e6185_port_set_speed,
2956 .port_tag_remap = mv88e6095_port_tag_remap,
2957 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2958 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2959 .port_set_ether_type = mv88e6351_port_set_ether_type,
2960 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2961 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2962 .port_pause_limit = mv88e6097_port_pause_limit,
2963 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2964 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2965 .port_link_state = mv88e6352_port_link_state,
2966 .port_get_cmode = mv88e6185_port_get_cmode,
2967 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2968 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2969 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2970 .stats_get_strings = mv88e6095_stats_get_strings,
2971 .stats_get_stats = mv88e6095_stats_get_stats,
2972 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2973 .set_egress_port = mv88e6095_g1_set_egress_port,
2974 .watchdog_ops = &mv88e6097_watchdog_ops,
2975 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2976 .pot_clear = mv88e6xxx_g2_pot_clear,
2977 .reset = mv88e6352_g1_reset,
2978 .rmu_disable = mv88e6085_g1_rmu_disable,
2979 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2980 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2981 .phylink_validate = mv88e6185_phylink_validate,
2984 static const struct mv88e6xxx_ops mv88e6123_ops = {
2985 /* MV88E6XXX_FAMILY_6165 */
2986 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2987 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2988 .irl_init_all = mv88e6352_g2_irl_init_all,
2989 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2990 .phy_read = mv88e6xxx_g2_smi_phy_read,
2991 .phy_write = mv88e6xxx_g2_smi_phy_write,
2992 .port_set_link = mv88e6xxx_port_set_link,
2993 .port_set_duplex = mv88e6xxx_port_set_duplex,
2994 .port_set_speed = mv88e6185_port_set_speed,
2995 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2996 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2997 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2998 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2999 .port_link_state = mv88e6352_port_link_state,
3000 .port_get_cmode = mv88e6185_port_get_cmode,
3001 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3002 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3003 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3004 .stats_get_strings = mv88e6095_stats_get_strings,
3005 .stats_get_stats = mv88e6095_stats_get_stats,
3006 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3007 .set_egress_port = mv88e6095_g1_set_egress_port,
3008 .watchdog_ops = &mv88e6097_watchdog_ops,
3009 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3010 .pot_clear = mv88e6xxx_g2_pot_clear,
3011 .reset = mv88e6352_g1_reset,
3012 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3013 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3014 .phylink_validate = mv88e6185_phylink_validate,
3017 static const struct mv88e6xxx_ops mv88e6131_ops = {
3018 /* MV88E6XXX_FAMILY_6185 */
3019 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3020 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3021 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3022 .phy_read = mv88e6185_phy_ppu_read,
3023 .phy_write = mv88e6185_phy_ppu_write,
3024 .port_set_link = mv88e6xxx_port_set_link,
3025 .port_set_duplex = mv88e6xxx_port_set_duplex,
3026 .port_set_speed = mv88e6185_port_set_speed,
3027 .port_tag_remap = mv88e6095_port_tag_remap,
3028 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3029 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3030 .port_set_ether_type = mv88e6351_port_set_ether_type,
3031 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3032 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3033 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3034 .port_pause_limit = mv88e6097_port_pause_limit,
3035 .port_set_pause = mv88e6185_port_set_pause,
3036 .port_link_state = mv88e6352_port_link_state,
3037 .port_get_cmode = mv88e6185_port_get_cmode,
3038 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3039 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3040 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3041 .stats_get_strings = mv88e6095_stats_get_strings,
3042 .stats_get_stats = mv88e6095_stats_get_stats,
3043 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3044 .set_egress_port = mv88e6095_g1_set_egress_port,
3045 .watchdog_ops = &mv88e6097_watchdog_ops,
3046 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3047 .ppu_enable = mv88e6185_g1_ppu_enable,
3048 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3049 .ppu_disable = mv88e6185_g1_ppu_disable,
3050 .reset = mv88e6185_g1_reset,
3051 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3052 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3053 .phylink_validate = mv88e6185_phylink_validate,
3056 static const struct mv88e6xxx_ops mv88e6141_ops = {
3057 /* MV88E6XXX_FAMILY_6341 */
3058 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3059 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3060 .irl_init_all = mv88e6352_g2_irl_init_all,
3061 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3062 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3063 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3064 .phy_read = mv88e6xxx_g2_smi_phy_read,
3065 .phy_write = mv88e6xxx_g2_smi_phy_write,
3066 .port_set_link = mv88e6xxx_port_set_link,
3067 .port_set_duplex = mv88e6xxx_port_set_duplex,
3068 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3069 .port_set_speed = mv88e6341_port_set_speed,
3070 .port_tag_remap = mv88e6095_port_tag_remap,
3071 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3072 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3073 .port_set_ether_type = mv88e6351_port_set_ether_type,
3074 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3075 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3076 .port_pause_limit = mv88e6097_port_pause_limit,
3077 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3078 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3079 .port_link_state = mv88e6352_port_link_state,
3080 .port_get_cmode = mv88e6352_port_get_cmode,
3081 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3082 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3083 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3084 .stats_get_strings = mv88e6320_stats_get_strings,
3085 .stats_get_stats = mv88e6390_stats_get_stats,
3086 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3087 .set_egress_port = mv88e6390_g1_set_egress_port,
3088 .watchdog_ops = &mv88e6390_watchdog_ops,
3089 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3090 .pot_clear = mv88e6xxx_g2_pot_clear,
3091 .reset = mv88e6352_g1_reset,
3092 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3093 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3094 .serdes_power = mv88e6341_serdes_power,
3095 .gpio_ops = &mv88e6352_gpio_ops,
3096 .phylink_validate = mv88e6341_phylink_validate,
3099 static const struct mv88e6xxx_ops mv88e6161_ops = {
3100 /* MV88E6XXX_FAMILY_6165 */
3101 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3102 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3103 .irl_init_all = mv88e6352_g2_irl_init_all,
3104 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3105 .phy_read = mv88e6xxx_g2_smi_phy_read,
3106 .phy_write = mv88e6xxx_g2_smi_phy_write,
3107 .port_set_link = mv88e6xxx_port_set_link,
3108 .port_set_duplex = mv88e6xxx_port_set_duplex,
3109 .port_set_speed = mv88e6185_port_set_speed,
3110 .port_tag_remap = mv88e6095_port_tag_remap,
3111 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3112 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3113 .port_set_ether_type = mv88e6351_port_set_ether_type,
3114 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3115 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3116 .port_pause_limit = mv88e6097_port_pause_limit,
3117 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3118 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3119 .port_link_state = mv88e6352_port_link_state,
3120 .port_get_cmode = mv88e6185_port_get_cmode,
3121 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3122 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3123 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3124 .stats_get_strings = mv88e6095_stats_get_strings,
3125 .stats_get_stats = mv88e6095_stats_get_stats,
3126 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3127 .set_egress_port = mv88e6095_g1_set_egress_port,
3128 .watchdog_ops = &mv88e6097_watchdog_ops,
3129 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3130 .pot_clear = mv88e6xxx_g2_pot_clear,
3131 .reset = mv88e6352_g1_reset,
3132 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3133 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3134 .avb_ops = &mv88e6165_avb_ops,
3135 .ptp_ops = &mv88e6165_ptp_ops,
3136 .phylink_validate = mv88e6185_phylink_validate,
3139 static const struct mv88e6xxx_ops mv88e6165_ops = {
3140 /* MV88E6XXX_FAMILY_6165 */
3141 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3142 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3143 .irl_init_all = mv88e6352_g2_irl_init_all,
3144 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3145 .phy_read = mv88e6165_phy_read,
3146 .phy_write = mv88e6165_phy_write,
3147 .port_set_link = mv88e6xxx_port_set_link,
3148 .port_set_duplex = mv88e6xxx_port_set_duplex,
3149 .port_set_speed = mv88e6185_port_set_speed,
3150 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3151 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3152 .port_link_state = mv88e6352_port_link_state,
3153 .port_get_cmode = mv88e6185_port_get_cmode,
3154 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3155 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3156 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3157 .stats_get_strings = mv88e6095_stats_get_strings,
3158 .stats_get_stats = mv88e6095_stats_get_stats,
3159 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3160 .set_egress_port = mv88e6095_g1_set_egress_port,
3161 .watchdog_ops = &mv88e6097_watchdog_ops,
3162 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3163 .pot_clear = mv88e6xxx_g2_pot_clear,
3164 .reset = mv88e6352_g1_reset,
3165 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3166 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3167 .avb_ops = &mv88e6165_avb_ops,
3168 .ptp_ops = &mv88e6165_ptp_ops,
3169 .phylink_validate = mv88e6185_phylink_validate,
3172 static const struct mv88e6xxx_ops mv88e6171_ops = {
3173 /* MV88E6XXX_FAMILY_6351 */
3174 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3175 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3176 .irl_init_all = mv88e6352_g2_irl_init_all,
3177 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3178 .phy_read = mv88e6xxx_g2_smi_phy_read,
3179 .phy_write = mv88e6xxx_g2_smi_phy_write,
3180 .port_set_link = mv88e6xxx_port_set_link,
3181 .port_set_duplex = mv88e6xxx_port_set_duplex,
3182 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3183 .port_set_speed = mv88e6185_port_set_speed,
3184 .port_tag_remap = mv88e6095_port_tag_remap,
3185 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3186 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3187 .port_set_ether_type = mv88e6351_port_set_ether_type,
3188 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3189 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3190 .port_pause_limit = mv88e6097_port_pause_limit,
3191 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3192 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3193 .port_link_state = mv88e6352_port_link_state,
3194 .port_get_cmode = mv88e6352_port_get_cmode,
3195 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3196 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3197 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3198 .stats_get_strings = mv88e6095_stats_get_strings,
3199 .stats_get_stats = mv88e6095_stats_get_stats,
3200 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3201 .set_egress_port = mv88e6095_g1_set_egress_port,
3202 .watchdog_ops = &mv88e6097_watchdog_ops,
3203 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3204 .pot_clear = mv88e6xxx_g2_pot_clear,
3205 .reset = mv88e6352_g1_reset,
3206 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3207 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3208 .phylink_validate = mv88e6185_phylink_validate,
3211 static const struct mv88e6xxx_ops mv88e6172_ops = {
3212 /* MV88E6XXX_FAMILY_6352 */
3213 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3214 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3215 .irl_init_all = mv88e6352_g2_irl_init_all,
3216 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3217 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3218 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3219 .phy_read = mv88e6xxx_g2_smi_phy_read,
3220 .phy_write = mv88e6xxx_g2_smi_phy_write,
3221 .port_set_link = mv88e6xxx_port_set_link,
3222 .port_set_duplex = mv88e6xxx_port_set_duplex,
3223 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3224 .port_set_speed = mv88e6352_port_set_speed,
3225 .port_tag_remap = mv88e6095_port_tag_remap,
3226 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3227 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3228 .port_set_ether_type = mv88e6351_port_set_ether_type,
3229 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3230 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3231 .port_pause_limit = mv88e6097_port_pause_limit,
3232 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3233 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3234 .port_link_state = mv88e6352_port_link_state,
3235 .port_get_cmode = mv88e6352_port_get_cmode,
3236 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3237 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3238 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3239 .stats_get_strings = mv88e6095_stats_get_strings,
3240 .stats_get_stats = mv88e6095_stats_get_stats,
3241 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3242 .set_egress_port = mv88e6095_g1_set_egress_port,
3243 .watchdog_ops = &mv88e6097_watchdog_ops,
3244 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3245 .pot_clear = mv88e6xxx_g2_pot_clear,
3246 .reset = mv88e6352_g1_reset,
3247 .rmu_disable = mv88e6352_g1_rmu_disable,
3248 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3249 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3250 .serdes_power = mv88e6352_serdes_power,
3251 .gpio_ops = &mv88e6352_gpio_ops,
3252 .phylink_validate = mv88e6352_phylink_validate,
3255 static const struct mv88e6xxx_ops mv88e6175_ops = {
3256 /* MV88E6XXX_FAMILY_6351 */
3257 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3258 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3259 .irl_init_all = mv88e6352_g2_irl_init_all,
3260 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3261 .phy_read = mv88e6xxx_g2_smi_phy_read,
3262 .phy_write = mv88e6xxx_g2_smi_phy_write,
3263 .port_set_link = mv88e6xxx_port_set_link,
3264 .port_set_duplex = mv88e6xxx_port_set_duplex,
3265 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3266 .port_set_speed = mv88e6185_port_set_speed,
3267 .port_tag_remap = mv88e6095_port_tag_remap,
3268 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3269 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3270 .port_set_ether_type = mv88e6351_port_set_ether_type,
3271 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3272 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3273 .port_pause_limit = mv88e6097_port_pause_limit,
3274 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3275 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3276 .port_link_state = mv88e6352_port_link_state,
3277 .port_get_cmode = mv88e6352_port_get_cmode,
3278 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3279 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3280 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3281 .stats_get_strings = mv88e6095_stats_get_strings,
3282 .stats_get_stats = mv88e6095_stats_get_stats,
3283 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3284 .set_egress_port = mv88e6095_g1_set_egress_port,
3285 .watchdog_ops = &mv88e6097_watchdog_ops,
3286 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3287 .pot_clear = mv88e6xxx_g2_pot_clear,
3288 .reset = mv88e6352_g1_reset,
3289 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3290 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3291 .phylink_validate = mv88e6185_phylink_validate,
3294 static const struct mv88e6xxx_ops mv88e6176_ops = {
3295 /* MV88E6XXX_FAMILY_6352 */
3296 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3297 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3298 .irl_init_all = mv88e6352_g2_irl_init_all,
3299 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3300 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3301 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3302 .phy_read = mv88e6xxx_g2_smi_phy_read,
3303 .phy_write = mv88e6xxx_g2_smi_phy_write,
3304 .port_set_link = mv88e6xxx_port_set_link,
3305 .port_set_duplex = mv88e6xxx_port_set_duplex,
3306 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3307 .port_set_speed = mv88e6352_port_set_speed,
3308 .port_tag_remap = mv88e6095_port_tag_remap,
3309 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3310 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3311 .port_set_ether_type = mv88e6351_port_set_ether_type,
3312 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3313 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3314 .port_pause_limit = mv88e6097_port_pause_limit,
3315 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3316 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3317 .port_link_state = mv88e6352_port_link_state,
3318 .port_get_cmode = mv88e6352_port_get_cmode,
3319 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3320 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3321 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3322 .stats_get_strings = mv88e6095_stats_get_strings,
3323 .stats_get_stats = mv88e6095_stats_get_stats,
3324 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3325 .set_egress_port = mv88e6095_g1_set_egress_port,
3326 .watchdog_ops = &mv88e6097_watchdog_ops,
3327 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3328 .pot_clear = mv88e6xxx_g2_pot_clear,
3329 .reset = mv88e6352_g1_reset,
3330 .rmu_disable = mv88e6352_g1_rmu_disable,
3331 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3332 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3333 .serdes_power = mv88e6352_serdes_power,
3334 .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3335 .serdes_irq_free = mv88e6352_serdes_irq_free,
3336 .gpio_ops = &mv88e6352_gpio_ops,
3337 .phylink_validate = mv88e6352_phylink_validate,
3340 static const struct mv88e6xxx_ops mv88e6185_ops = {
3341 /* MV88E6XXX_FAMILY_6185 */
3342 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3343 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3344 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3345 .phy_read = mv88e6185_phy_ppu_read,
3346 .phy_write = mv88e6185_phy_ppu_write,
3347 .port_set_link = mv88e6xxx_port_set_link,
3348 .port_set_duplex = mv88e6xxx_port_set_duplex,
3349 .port_set_speed = mv88e6185_port_set_speed,
3350 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3351 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3352 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3353 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3354 .port_set_pause = mv88e6185_port_set_pause,
3355 .port_link_state = mv88e6185_port_link_state,
3356 .port_get_cmode = mv88e6185_port_get_cmode,
3357 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3358 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3359 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3360 .stats_get_strings = mv88e6095_stats_get_strings,
3361 .stats_get_stats = mv88e6095_stats_get_stats,
3362 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3363 .set_egress_port = mv88e6095_g1_set_egress_port,
3364 .watchdog_ops = &mv88e6097_watchdog_ops,
3365 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3366 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3367 .ppu_enable = mv88e6185_g1_ppu_enable,
3368 .ppu_disable = mv88e6185_g1_ppu_disable,
3369 .reset = mv88e6185_g1_reset,
3370 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3371 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3372 .phylink_validate = mv88e6185_phylink_validate,
3375 static const struct mv88e6xxx_ops mv88e6190_ops = {
3376 /* MV88E6XXX_FAMILY_6390 */
3377 .setup_errata = mv88e6390_setup_errata,
3378 .irl_init_all = mv88e6390_g2_irl_init_all,
3379 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3380 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3381 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3382 .phy_read = mv88e6xxx_g2_smi_phy_read,
3383 .phy_write = mv88e6xxx_g2_smi_phy_write,
3384 .port_set_link = mv88e6xxx_port_set_link,
3385 .port_set_duplex = mv88e6xxx_port_set_duplex,
3386 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3387 .port_set_speed = mv88e6390_port_set_speed,
3388 .port_tag_remap = mv88e6390_port_tag_remap,
3389 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3390 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3391 .port_set_ether_type = mv88e6351_port_set_ether_type,
3392 .port_pause_limit = mv88e6390_port_pause_limit,
3393 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3394 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3395 .port_link_state = mv88e6352_port_link_state,
3396 .port_get_cmode = mv88e6352_port_get_cmode,
3397 .port_set_cmode = mv88e6390_port_set_cmode,
3398 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3399 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3400 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3401 .stats_get_strings = mv88e6320_stats_get_strings,
3402 .stats_get_stats = mv88e6390_stats_get_stats,
3403 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3404 .set_egress_port = mv88e6390_g1_set_egress_port,
3405 .watchdog_ops = &mv88e6390_watchdog_ops,
3406 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3407 .pot_clear = mv88e6xxx_g2_pot_clear,
3408 .reset = mv88e6352_g1_reset,
3409 .rmu_disable = mv88e6390_g1_rmu_disable,
3410 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3411 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3412 .serdes_power = mv88e6390_serdes_power,
3413 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3414 .serdes_irq_free = mv88e6390_serdes_irq_free,
3415 .gpio_ops = &mv88e6352_gpio_ops,
3416 .phylink_validate = mv88e6390_phylink_validate,
3419 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3420 /* MV88E6XXX_FAMILY_6390 */
3421 .setup_errata = mv88e6390_setup_errata,
3422 .irl_init_all = mv88e6390_g2_irl_init_all,
3423 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3424 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3425 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3426 .phy_read = mv88e6xxx_g2_smi_phy_read,
3427 .phy_write = mv88e6xxx_g2_smi_phy_write,
3428 .port_set_link = mv88e6xxx_port_set_link,
3429 .port_set_duplex = mv88e6xxx_port_set_duplex,
3430 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3431 .port_set_speed = mv88e6390x_port_set_speed,
3432 .port_tag_remap = mv88e6390_port_tag_remap,
3433 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3434 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3435 .port_set_ether_type = mv88e6351_port_set_ether_type,
3436 .port_pause_limit = mv88e6390_port_pause_limit,
3437 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3438 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3439 .port_link_state = mv88e6352_port_link_state,
3440 .port_get_cmode = mv88e6352_port_get_cmode,
3441 .port_set_cmode = mv88e6390x_port_set_cmode,
3442 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3443 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3444 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3445 .stats_get_strings = mv88e6320_stats_get_strings,
3446 .stats_get_stats = mv88e6390_stats_get_stats,
3447 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3448 .set_egress_port = mv88e6390_g1_set_egress_port,
3449 .watchdog_ops = &mv88e6390_watchdog_ops,
3450 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3451 .pot_clear = mv88e6xxx_g2_pot_clear,
3452 .reset = mv88e6352_g1_reset,
3453 .rmu_disable = mv88e6390_g1_rmu_disable,
3454 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3455 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3456 .serdes_power = mv88e6390x_serdes_power,
3457 .serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3458 .serdes_irq_free = mv88e6390x_serdes_irq_free,
3459 .gpio_ops = &mv88e6352_gpio_ops,
3460 .phylink_validate = mv88e6390x_phylink_validate,
3463 static const struct mv88e6xxx_ops mv88e6191_ops = {
3464 /* MV88E6XXX_FAMILY_6390 */
3465 .setup_errata = mv88e6390_setup_errata,
3466 .irl_init_all = mv88e6390_g2_irl_init_all,
3467 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3468 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3469 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3470 .phy_read = mv88e6xxx_g2_smi_phy_read,
3471 .phy_write = mv88e6xxx_g2_smi_phy_write,
3472 .port_set_link = mv88e6xxx_port_set_link,
3473 .port_set_duplex = mv88e6xxx_port_set_duplex,
3474 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3475 .port_set_speed = mv88e6390_port_set_speed,
3476 .port_tag_remap = mv88e6390_port_tag_remap,
3477 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3478 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3479 .port_set_ether_type = mv88e6351_port_set_ether_type,
3480 .port_pause_limit = mv88e6390_port_pause_limit,
3481 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3482 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3483 .port_link_state = mv88e6352_port_link_state,
3484 .port_get_cmode = mv88e6352_port_get_cmode,
3485 .port_set_cmode = mv88e6390_port_set_cmode,
3486 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3487 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3488 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3489 .stats_get_strings = mv88e6320_stats_get_strings,
3490 .stats_get_stats = mv88e6390_stats_get_stats,
3491 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3492 .set_egress_port = mv88e6390_g1_set_egress_port,
3493 .watchdog_ops = &mv88e6390_watchdog_ops,
3494 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3495 .pot_clear = mv88e6xxx_g2_pot_clear,
3496 .reset = mv88e6352_g1_reset,
3497 .rmu_disable = mv88e6390_g1_rmu_disable,
3498 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3499 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3500 .serdes_power = mv88e6390_serdes_power,
3501 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3502 .serdes_irq_free = mv88e6390_serdes_irq_free,
3503 .avb_ops = &mv88e6390_avb_ops,
3504 .ptp_ops = &mv88e6352_ptp_ops,
3505 .phylink_validate = mv88e6390_phylink_validate,
3508 static const struct mv88e6xxx_ops mv88e6240_ops = {
3509 /* MV88E6XXX_FAMILY_6352 */
3510 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3511 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3512 .irl_init_all = mv88e6352_g2_irl_init_all,
3513 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3514 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3515 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3516 .phy_read = mv88e6xxx_g2_smi_phy_read,
3517 .phy_write = mv88e6xxx_g2_smi_phy_write,
3518 .port_set_link = mv88e6xxx_port_set_link,
3519 .port_set_duplex = mv88e6xxx_port_set_duplex,
3520 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3521 .port_set_speed = mv88e6352_port_set_speed,
3522 .port_tag_remap = mv88e6095_port_tag_remap,
3523 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3524 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3525 .port_set_ether_type = mv88e6351_port_set_ether_type,
3526 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3527 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3528 .port_pause_limit = mv88e6097_port_pause_limit,
3529 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3530 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3531 .port_link_state = mv88e6352_port_link_state,
3532 .port_get_cmode = mv88e6352_port_get_cmode,
3533 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3534 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3535 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3536 .stats_get_strings = mv88e6095_stats_get_strings,
3537 .stats_get_stats = mv88e6095_stats_get_stats,
3538 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3539 .set_egress_port = mv88e6095_g1_set_egress_port,
3540 .watchdog_ops = &mv88e6097_watchdog_ops,
3541 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3542 .pot_clear = mv88e6xxx_g2_pot_clear,
3543 .reset = mv88e6352_g1_reset,
3544 .rmu_disable = mv88e6352_g1_rmu_disable,
3545 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3546 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3547 .serdes_power = mv88e6352_serdes_power,
3548 .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3549 .serdes_irq_free = mv88e6352_serdes_irq_free,
3550 .gpio_ops = &mv88e6352_gpio_ops,
3551 .avb_ops = &mv88e6352_avb_ops,
3552 .ptp_ops = &mv88e6352_ptp_ops,
3553 .phylink_validate = mv88e6352_phylink_validate,
3556 static const struct mv88e6xxx_ops mv88e6290_ops = {
3557 /* MV88E6XXX_FAMILY_6390 */
3558 .setup_errata = mv88e6390_setup_errata,
3559 .irl_init_all = mv88e6390_g2_irl_init_all,
3560 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3561 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3562 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3563 .phy_read = mv88e6xxx_g2_smi_phy_read,
3564 .phy_write = mv88e6xxx_g2_smi_phy_write,
3565 .port_set_link = mv88e6xxx_port_set_link,
3566 .port_set_duplex = mv88e6xxx_port_set_duplex,
3567 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3568 .port_set_speed = mv88e6390_port_set_speed,
3569 .port_tag_remap = mv88e6390_port_tag_remap,
3570 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3571 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3572 .port_set_ether_type = mv88e6351_port_set_ether_type,
3573 .port_pause_limit = mv88e6390_port_pause_limit,
3574 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3575 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3576 .port_link_state = mv88e6352_port_link_state,
3577 .port_get_cmode = mv88e6352_port_get_cmode,
3578 .port_set_cmode = mv88e6390_port_set_cmode,
3579 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3580 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3581 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3582 .stats_get_strings = mv88e6320_stats_get_strings,
3583 .stats_get_stats = mv88e6390_stats_get_stats,
3584 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3585 .set_egress_port = mv88e6390_g1_set_egress_port,
3586 .watchdog_ops = &mv88e6390_watchdog_ops,
3587 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3588 .pot_clear = mv88e6xxx_g2_pot_clear,
3589 .reset = mv88e6352_g1_reset,
3590 .rmu_disable = mv88e6390_g1_rmu_disable,
3591 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3592 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3593 .serdes_power = mv88e6390_serdes_power,
3594 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3595 .serdes_irq_free = mv88e6390_serdes_irq_free,
3596 .gpio_ops = &mv88e6352_gpio_ops,
3597 .avb_ops = &mv88e6390_avb_ops,
3598 .ptp_ops = &mv88e6352_ptp_ops,
3599 .phylink_validate = mv88e6390_phylink_validate,
3602 static const struct mv88e6xxx_ops mv88e6320_ops = {
3603 /* MV88E6XXX_FAMILY_6320 */
3604 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3605 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3606 .irl_init_all = mv88e6352_g2_irl_init_all,
3607 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3608 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3609 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3610 .phy_read = mv88e6xxx_g2_smi_phy_read,
3611 .phy_write = mv88e6xxx_g2_smi_phy_write,
3612 .port_set_link = mv88e6xxx_port_set_link,
3613 .port_set_duplex = mv88e6xxx_port_set_duplex,
3614 .port_set_speed = mv88e6185_port_set_speed,
3615 .port_tag_remap = mv88e6095_port_tag_remap,
3616 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3617 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3618 .port_set_ether_type = mv88e6351_port_set_ether_type,
3619 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3620 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3621 .port_pause_limit = mv88e6097_port_pause_limit,
3622 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3623 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3624 .port_link_state = mv88e6352_port_link_state,
3625 .port_get_cmode = mv88e6352_port_get_cmode,
3626 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3627 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3628 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3629 .stats_get_strings = mv88e6320_stats_get_strings,
3630 .stats_get_stats = mv88e6320_stats_get_stats,
3631 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3632 .set_egress_port = mv88e6095_g1_set_egress_port,
3633 .watchdog_ops = &mv88e6390_watchdog_ops,
3634 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3635 .pot_clear = mv88e6xxx_g2_pot_clear,
3636 .reset = mv88e6352_g1_reset,
3637 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3638 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3639 .gpio_ops = &mv88e6352_gpio_ops,
3640 .avb_ops = &mv88e6352_avb_ops,
3641 .ptp_ops = &mv88e6352_ptp_ops,
3642 .phylink_validate = mv88e6185_phylink_validate,
3645 static const struct mv88e6xxx_ops mv88e6321_ops = {
3646 /* MV88E6XXX_FAMILY_6320 */
3647 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3648 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3649 .irl_init_all = mv88e6352_g2_irl_init_all,
3650 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3651 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3652 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3653 .phy_read = mv88e6xxx_g2_smi_phy_read,
3654 .phy_write = mv88e6xxx_g2_smi_phy_write,
3655 .port_set_link = mv88e6xxx_port_set_link,
3656 .port_set_duplex = mv88e6xxx_port_set_duplex,
3657 .port_set_speed = mv88e6185_port_set_speed,
3658 .port_tag_remap = mv88e6095_port_tag_remap,
3659 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3660 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3661 .port_set_ether_type = mv88e6351_port_set_ether_type,
3662 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3663 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3664 .port_pause_limit = mv88e6097_port_pause_limit,
3665 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3666 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3667 .port_link_state = mv88e6352_port_link_state,
3668 .port_get_cmode = mv88e6352_port_get_cmode,
3669 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3670 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3671 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3672 .stats_get_strings = mv88e6320_stats_get_strings,
3673 .stats_get_stats = mv88e6320_stats_get_stats,
3674 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3675 .set_egress_port = mv88e6095_g1_set_egress_port,
3676 .watchdog_ops = &mv88e6390_watchdog_ops,
3677 .reset = mv88e6352_g1_reset,
3678 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3679 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3680 .gpio_ops = &mv88e6352_gpio_ops,
3681 .avb_ops = &mv88e6352_avb_ops,
3682 .ptp_ops = &mv88e6352_ptp_ops,
3683 .phylink_validate = mv88e6185_phylink_validate,
3686 static const struct mv88e6xxx_ops mv88e6341_ops = {
3687 /* MV88E6XXX_FAMILY_6341 */
3688 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3689 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3690 .irl_init_all = mv88e6352_g2_irl_init_all,
3691 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3692 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3693 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3694 .phy_read = mv88e6xxx_g2_smi_phy_read,
3695 .phy_write = mv88e6xxx_g2_smi_phy_write,
3696 .port_set_link = mv88e6xxx_port_set_link,
3697 .port_set_duplex = mv88e6xxx_port_set_duplex,
3698 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3699 .port_set_speed = mv88e6341_port_set_speed,
3700 .port_tag_remap = mv88e6095_port_tag_remap,
3701 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3702 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3703 .port_set_ether_type = mv88e6351_port_set_ether_type,
3704 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3705 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3706 .port_pause_limit = mv88e6097_port_pause_limit,
3707 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3708 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3709 .port_link_state = mv88e6352_port_link_state,
3710 .port_get_cmode = mv88e6352_port_get_cmode,
3711 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3712 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3713 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3714 .stats_get_strings = mv88e6320_stats_get_strings,
3715 .stats_get_stats = mv88e6390_stats_get_stats,
3716 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3717 .set_egress_port = mv88e6390_g1_set_egress_port,
3718 .watchdog_ops = &mv88e6390_watchdog_ops,
3719 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3720 .pot_clear = mv88e6xxx_g2_pot_clear,
3721 .reset = mv88e6352_g1_reset,
3722 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3723 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3724 .serdes_power = mv88e6341_serdes_power,
3725 .gpio_ops = &mv88e6352_gpio_ops,
3726 .avb_ops = &mv88e6390_avb_ops,
3727 .ptp_ops = &mv88e6352_ptp_ops,
3728 .phylink_validate = mv88e6341_phylink_validate,
3731 static const struct mv88e6xxx_ops mv88e6350_ops = {
3732 /* MV88E6XXX_FAMILY_6351 */
3733 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3734 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3735 .irl_init_all = mv88e6352_g2_irl_init_all,
3736 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3737 .phy_read = mv88e6xxx_g2_smi_phy_read,
3738 .phy_write = mv88e6xxx_g2_smi_phy_write,
3739 .port_set_link = mv88e6xxx_port_set_link,
3740 .port_set_duplex = mv88e6xxx_port_set_duplex,
3741 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3742 .port_set_speed = mv88e6185_port_set_speed,
3743 .port_tag_remap = mv88e6095_port_tag_remap,
3744 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3745 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3746 .port_set_ether_type = mv88e6351_port_set_ether_type,
3747 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3748 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3749 .port_pause_limit = mv88e6097_port_pause_limit,
3750 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3751 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3752 .port_link_state = mv88e6352_port_link_state,
3753 .port_get_cmode = mv88e6352_port_get_cmode,
3754 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3755 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3756 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3757 .stats_get_strings = mv88e6095_stats_get_strings,
3758 .stats_get_stats = mv88e6095_stats_get_stats,
3759 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3760 .set_egress_port = mv88e6095_g1_set_egress_port,
3761 .watchdog_ops = &mv88e6097_watchdog_ops,
3762 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3763 .pot_clear = mv88e6xxx_g2_pot_clear,
3764 .reset = mv88e6352_g1_reset,
3765 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3766 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3767 .phylink_validate = mv88e6185_phylink_validate,
3770 static const struct mv88e6xxx_ops mv88e6351_ops = {
3771 /* MV88E6XXX_FAMILY_6351 */
3772 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3773 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3774 .irl_init_all = mv88e6352_g2_irl_init_all,
3775 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3776 .phy_read = mv88e6xxx_g2_smi_phy_read,
3777 .phy_write = mv88e6xxx_g2_smi_phy_write,
3778 .port_set_link = mv88e6xxx_port_set_link,
3779 .port_set_duplex = mv88e6xxx_port_set_duplex,
3780 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3781 .port_set_speed = mv88e6185_port_set_speed,
3782 .port_tag_remap = mv88e6095_port_tag_remap,
3783 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3784 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3785 .port_set_ether_type = mv88e6351_port_set_ether_type,
3786 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3787 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3788 .port_pause_limit = mv88e6097_port_pause_limit,
3789 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3790 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3791 .port_link_state = mv88e6352_port_link_state,
3792 .port_get_cmode = mv88e6352_port_get_cmode,
3793 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3794 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3795 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3796 .stats_get_strings = mv88e6095_stats_get_strings,
3797 .stats_get_stats = mv88e6095_stats_get_stats,
3798 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3799 .set_egress_port = mv88e6095_g1_set_egress_port,
3800 .watchdog_ops = &mv88e6097_watchdog_ops,
3801 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3802 .pot_clear = mv88e6xxx_g2_pot_clear,
3803 .reset = mv88e6352_g1_reset,
3804 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3805 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3806 .avb_ops = &mv88e6352_avb_ops,
3807 .ptp_ops = &mv88e6352_ptp_ops,
3808 .phylink_validate = mv88e6185_phylink_validate,
3811 static const struct mv88e6xxx_ops mv88e6352_ops = {
3812 /* MV88E6XXX_FAMILY_6352 */
3813 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3814 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3815 .irl_init_all = mv88e6352_g2_irl_init_all,
3816 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3817 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3818 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3819 .phy_read = mv88e6xxx_g2_smi_phy_read,
3820 .phy_write = mv88e6xxx_g2_smi_phy_write,
3821 .port_set_link = mv88e6xxx_port_set_link,
3822 .port_set_duplex = mv88e6xxx_port_set_duplex,
3823 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3824 .port_set_speed = mv88e6352_port_set_speed,
3825 .port_tag_remap = mv88e6095_port_tag_remap,
3826 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3827 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3828 .port_set_ether_type = mv88e6351_port_set_ether_type,
3829 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3830 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3831 .port_pause_limit = mv88e6097_port_pause_limit,
3832 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3833 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3834 .port_link_state = mv88e6352_port_link_state,
3835 .port_get_cmode = mv88e6352_port_get_cmode,
3836 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3837 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3838 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3839 .stats_get_strings = mv88e6095_stats_get_strings,
3840 .stats_get_stats = mv88e6095_stats_get_stats,
3841 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3842 .set_egress_port = mv88e6095_g1_set_egress_port,
3843 .watchdog_ops = &mv88e6097_watchdog_ops,
3844 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3845 .pot_clear = mv88e6xxx_g2_pot_clear,
3846 .reset = mv88e6352_g1_reset,
3847 .rmu_disable = mv88e6352_g1_rmu_disable,
3848 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3849 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3850 .serdes_power = mv88e6352_serdes_power,
3851 .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3852 .serdes_irq_free = mv88e6352_serdes_irq_free,
3853 .gpio_ops = &mv88e6352_gpio_ops,
3854 .avb_ops = &mv88e6352_avb_ops,
3855 .ptp_ops = &mv88e6352_ptp_ops,
3856 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3857 .serdes_get_strings = mv88e6352_serdes_get_strings,
3858 .serdes_get_stats = mv88e6352_serdes_get_stats,
3859 .phylink_validate = mv88e6352_phylink_validate,
3862 static const struct mv88e6xxx_ops mv88e6390_ops = {
3863 /* MV88E6XXX_FAMILY_6390 */
3864 .setup_errata = mv88e6390_setup_errata,
3865 .irl_init_all = mv88e6390_g2_irl_init_all,
3866 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3867 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3868 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3869 .phy_read = mv88e6xxx_g2_smi_phy_read,
3870 .phy_write = mv88e6xxx_g2_smi_phy_write,
3871 .port_set_link = mv88e6xxx_port_set_link,
3872 .port_set_duplex = mv88e6xxx_port_set_duplex,
3873 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3874 .port_set_speed = mv88e6390_port_set_speed,
3875 .port_tag_remap = mv88e6390_port_tag_remap,
3876 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3877 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3878 .port_set_ether_type = mv88e6351_port_set_ether_type,
3879 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3880 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3881 .port_pause_limit = mv88e6390_port_pause_limit,
3882 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3883 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3884 .port_link_state = mv88e6352_port_link_state,
3885 .port_get_cmode = mv88e6352_port_get_cmode,
3886 .port_set_cmode = mv88e6390_port_set_cmode,
3887 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3888 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3889 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3890 .stats_get_strings = mv88e6320_stats_get_strings,
3891 .stats_get_stats = mv88e6390_stats_get_stats,
3892 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3893 .set_egress_port = mv88e6390_g1_set_egress_port,
3894 .watchdog_ops = &mv88e6390_watchdog_ops,
3895 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3896 .pot_clear = mv88e6xxx_g2_pot_clear,
3897 .reset = mv88e6352_g1_reset,
3898 .rmu_disable = mv88e6390_g1_rmu_disable,
3899 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3900 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3901 .serdes_power = mv88e6390_serdes_power,
3902 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3903 .serdes_irq_free = mv88e6390_serdes_irq_free,
3904 .gpio_ops = &mv88e6352_gpio_ops,
3905 .avb_ops = &mv88e6390_avb_ops,
3906 .ptp_ops = &mv88e6352_ptp_ops,
3907 .phylink_validate = mv88e6390_phylink_validate,
3910 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3911 /* MV88E6XXX_FAMILY_6390 */
3912 .setup_errata = mv88e6390_setup_errata,
3913 .irl_init_all = mv88e6390_g2_irl_init_all,
3914 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3915 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3916 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3917 .phy_read = mv88e6xxx_g2_smi_phy_read,
3918 .phy_write = mv88e6xxx_g2_smi_phy_write,
3919 .port_set_link = mv88e6xxx_port_set_link,
3920 .port_set_duplex = mv88e6xxx_port_set_duplex,
3921 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3922 .port_set_speed = mv88e6390x_port_set_speed,
3923 .port_tag_remap = mv88e6390_port_tag_remap,
3924 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3925 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3926 .port_set_ether_type = mv88e6351_port_set_ether_type,
3927 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3928 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3929 .port_pause_limit = mv88e6390_port_pause_limit,
3930 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3931 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3932 .port_link_state = mv88e6352_port_link_state,
3933 .port_get_cmode = mv88e6352_port_get_cmode,
3934 .port_set_cmode = mv88e6390x_port_set_cmode,
3935 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3936 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3937 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3938 .stats_get_strings = mv88e6320_stats_get_strings,
3939 .stats_get_stats = mv88e6390_stats_get_stats,
3940 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3941 .set_egress_port = mv88e6390_g1_set_egress_port,
3942 .watchdog_ops = &mv88e6390_watchdog_ops,
3943 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3944 .pot_clear = mv88e6xxx_g2_pot_clear,
3945 .reset = mv88e6352_g1_reset,
3946 .rmu_disable = mv88e6390_g1_rmu_disable,
3947 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3948 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3949 .serdes_power = mv88e6390x_serdes_power,
3950 .serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3951 .serdes_irq_free = mv88e6390x_serdes_irq_free,
3952 .gpio_ops = &mv88e6352_gpio_ops,
3953 .avb_ops = &mv88e6390_avb_ops,
3954 .ptp_ops = &mv88e6352_ptp_ops,
3955 .phylink_validate = mv88e6390x_phylink_validate,
3958 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3960 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3961 .family = MV88E6XXX_FAMILY_6097,
3962 .name = "Marvell 88E6085",
3963 .num_databases = 4096,
3965 .num_internal_phys = 5,
3967 .port_base_addr = 0x10,
3968 .phy_base_addr = 0x0,
3969 .global1_addr = 0x1b,
3970 .global2_addr = 0x1c,
3971 .age_time_coeff = 15000,
3974 .atu_move_port_mask = 0xf,
3977 .tag_protocol = DSA_TAG_PROTO_DSA,
3978 .ops = &mv88e6085_ops,
3982 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3983 .family = MV88E6XXX_FAMILY_6095,
3984 .name = "Marvell 88E6095/88E6095F",
3985 .num_databases = 256,
3987 .num_internal_phys = 0,
3989 .port_base_addr = 0x10,
3990 .phy_base_addr = 0x0,
3991 .global1_addr = 0x1b,
3992 .global2_addr = 0x1c,
3993 .age_time_coeff = 15000,
3995 .atu_move_port_mask = 0xf,
3997 .tag_protocol = DSA_TAG_PROTO_DSA,
3998 .ops = &mv88e6095_ops,
4002 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4003 .family = MV88E6XXX_FAMILY_6097,
4004 .name = "Marvell 88E6097/88E6097F",
4005 .num_databases = 4096,
4007 .num_internal_phys = 8,
4009 .port_base_addr = 0x10,
4010 .phy_base_addr = 0x0,
4011 .global1_addr = 0x1b,
4012 .global2_addr = 0x1c,
4013 .age_time_coeff = 15000,
4016 .atu_move_port_mask = 0xf,
4019 .tag_protocol = DSA_TAG_PROTO_EDSA,
4020 .ops = &mv88e6097_ops,
4024 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4025 .family = MV88E6XXX_FAMILY_6165,
4026 .name = "Marvell 88E6123",
4027 .num_databases = 4096,
4029 .num_internal_phys = 5,
4031 .port_base_addr = 0x10,
4032 .phy_base_addr = 0x0,
4033 .global1_addr = 0x1b,
4034 .global2_addr = 0x1c,
4035 .age_time_coeff = 15000,
4038 .atu_move_port_mask = 0xf,
4041 .tag_protocol = DSA_TAG_PROTO_EDSA,
4042 .ops = &mv88e6123_ops,
4046 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4047 .family = MV88E6XXX_FAMILY_6185,
4048 .name = "Marvell 88E6131",
4049 .num_databases = 256,
4051 .num_internal_phys = 0,
4053 .port_base_addr = 0x10,
4054 .phy_base_addr = 0x0,
4055 .global1_addr = 0x1b,
4056 .global2_addr = 0x1c,
4057 .age_time_coeff = 15000,
4059 .atu_move_port_mask = 0xf,
4061 .tag_protocol = DSA_TAG_PROTO_DSA,
4062 .ops = &mv88e6131_ops,
4066 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4067 .family = MV88E6XXX_FAMILY_6341,
4068 .name = "Marvell 88E6141",
4069 .num_databases = 4096,
4071 .num_internal_phys = 5,
4074 .port_base_addr = 0x10,
4075 .phy_base_addr = 0x10,
4076 .global1_addr = 0x1b,
4077 .global2_addr = 0x1c,
4078 .age_time_coeff = 3750,
4079 .atu_move_port_mask = 0x1f,
4084 .tag_protocol = DSA_TAG_PROTO_EDSA,
4085 .ops = &mv88e6141_ops,
4089 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4090 .family = MV88E6XXX_FAMILY_6165,
4091 .name = "Marvell 88E6161",
4092 .num_databases = 4096,
4094 .num_internal_phys = 5,
4096 .port_base_addr = 0x10,
4097 .phy_base_addr = 0x0,
4098 .global1_addr = 0x1b,
4099 .global2_addr = 0x1c,
4100 .age_time_coeff = 15000,
4103 .atu_move_port_mask = 0xf,
4106 .tag_protocol = DSA_TAG_PROTO_EDSA,
4107 .ptp_support = true,
4108 .ops = &mv88e6161_ops,
4112 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4113 .family = MV88E6XXX_FAMILY_6165,
4114 .name = "Marvell 88E6165",
4115 .num_databases = 4096,
4117 .num_internal_phys = 0,
4119 .port_base_addr = 0x10,
4120 .phy_base_addr = 0x0,
4121 .global1_addr = 0x1b,
4122 .global2_addr = 0x1c,
4123 .age_time_coeff = 15000,
4126 .atu_move_port_mask = 0xf,
4129 .tag_protocol = DSA_TAG_PROTO_DSA,
4130 .ptp_support = true,
4131 .ops = &mv88e6165_ops,
4135 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4136 .family = MV88E6XXX_FAMILY_6351,
4137 .name = "Marvell 88E6171",
4138 .num_databases = 4096,
4140 .num_internal_phys = 5,
4142 .port_base_addr = 0x10,
4143 .phy_base_addr = 0x0,
4144 .global1_addr = 0x1b,
4145 .global2_addr = 0x1c,
4146 .age_time_coeff = 15000,
4149 .atu_move_port_mask = 0xf,
4152 .tag_protocol = DSA_TAG_PROTO_EDSA,
4153 .ops = &mv88e6171_ops,
4157 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4158 .family = MV88E6XXX_FAMILY_6352,
4159 .name = "Marvell 88E6172",
4160 .num_databases = 4096,
4162 .num_internal_phys = 5,
4165 .port_base_addr = 0x10,
4166 .phy_base_addr = 0x0,
4167 .global1_addr = 0x1b,
4168 .global2_addr = 0x1c,
4169 .age_time_coeff = 15000,
4172 .atu_move_port_mask = 0xf,
4175 .tag_protocol = DSA_TAG_PROTO_EDSA,
4176 .ops = &mv88e6172_ops,
4180 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4181 .family = MV88E6XXX_FAMILY_6351,
4182 .name = "Marvell 88E6175",
4183 .num_databases = 4096,
4185 .num_internal_phys = 5,
4187 .port_base_addr = 0x10,
4188 .phy_base_addr = 0x0,
4189 .global1_addr = 0x1b,
4190 .global2_addr = 0x1c,
4191 .age_time_coeff = 15000,
4194 .atu_move_port_mask = 0xf,
4197 .tag_protocol = DSA_TAG_PROTO_EDSA,
4198 .ops = &mv88e6175_ops,
4202 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4203 .family = MV88E6XXX_FAMILY_6352,
4204 .name = "Marvell 88E6176",
4205 .num_databases = 4096,
4207 .num_internal_phys = 5,
4210 .port_base_addr = 0x10,
4211 .phy_base_addr = 0x0,
4212 .global1_addr = 0x1b,
4213 .global2_addr = 0x1c,
4214 .age_time_coeff = 15000,
4217 .atu_move_port_mask = 0xf,
4220 .tag_protocol = DSA_TAG_PROTO_EDSA,
4221 .ops = &mv88e6176_ops,
4225 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4226 .family = MV88E6XXX_FAMILY_6185,
4227 .name = "Marvell 88E6185",
4228 .num_databases = 256,
4230 .num_internal_phys = 0,
4232 .port_base_addr = 0x10,
4233 .phy_base_addr = 0x0,
4234 .global1_addr = 0x1b,
4235 .global2_addr = 0x1c,
4236 .age_time_coeff = 15000,
4238 .atu_move_port_mask = 0xf,
4240 .tag_protocol = DSA_TAG_PROTO_EDSA,
4241 .ops = &mv88e6185_ops,
4245 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4246 .family = MV88E6XXX_FAMILY_6390,
4247 .name = "Marvell 88E6190",
4248 .num_databases = 4096,
4249 .num_ports = 11, /* 10 + Z80 */
4250 .num_internal_phys = 11,
4253 .port_base_addr = 0x0,
4254 .phy_base_addr = 0x0,
4255 .global1_addr = 0x1b,
4256 .global2_addr = 0x1c,
4257 .tag_protocol = DSA_TAG_PROTO_DSA,
4258 .age_time_coeff = 3750,
4263 .atu_move_port_mask = 0x1f,
4264 .ops = &mv88e6190_ops,
4268 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4269 .family = MV88E6XXX_FAMILY_6390,
4270 .name = "Marvell 88E6190X",
4271 .num_databases = 4096,
4272 .num_ports = 11, /* 10 + Z80 */
4273 .num_internal_phys = 11,
4276 .port_base_addr = 0x0,
4277 .phy_base_addr = 0x0,
4278 .global1_addr = 0x1b,
4279 .global2_addr = 0x1c,
4280 .age_time_coeff = 3750,
4283 .atu_move_port_mask = 0x1f,
4286 .tag_protocol = DSA_TAG_PROTO_DSA,
4287 .ops = &mv88e6190x_ops,
4291 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4292 .family = MV88E6XXX_FAMILY_6390,
4293 .name = "Marvell 88E6191",
4294 .num_databases = 4096,
4295 .num_ports = 11, /* 10 + Z80 */
4296 .num_internal_phys = 11,
4298 .port_base_addr = 0x0,
4299 .phy_base_addr = 0x0,
4300 .global1_addr = 0x1b,
4301 .global2_addr = 0x1c,
4302 .age_time_coeff = 3750,
4305 .atu_move_port_mask = 0x1f,
4308 .tag_protocol = DSA_TAG_PROTO_DSA,
4309 .ptp_support = true,
4310 .ops = &mv88e6191_ops,
4314 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4315 .family = MV88E6XXX_FAMILY_6352,
4316 .name = "Marvell 88E6240",
4317 .num_databases = 4096,
4319 .num_internal_phys = 5,
4322 .port_base_addr = 0x10,
4323 .phy_base_addr = 0x0,
4324 .global1_addr = 0x1b,
4325 .global2_addr = 0x1c,
4326 .age_time_coeff = 15000,
4329 .atu_move_port_mask = 0xf,
4332 .tag_protocol = DSA_TAG_PROTO_EDSA,
4333 .ptp_support = true,
4334 .ops = &mv88e6240_ops,
4338 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4339 .family = MV88E6XXX_FAMILY_6390,
4340 .name = "Marvell 88E6290",
4341 .num_databases = 4096,
4342 .num_ports = 11, /* 10 + Z80 */
4343 .num_internal_phys = 11,
4346 .port_base_addr = 0x0,
4347 .phy_base_addr = 0x0,
4348 .global1_addr = 0x1b,
4349 .global2_addr = 0x1c,
4350 .age_time_coeff = 3750,
4353 .atu_move_port_mask = 0x1f,
4356 .tag_protocol = DSA_TAG_PROTO_DSA,
4357 .ptp_support = true,
4358 .ops = &mv88e6290_ops,
4362 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4363 .family = MV88E6XXX_FAMILY_6320,
4364 .name = "Marvell 88E6320",
4365 .num_databases = 4096,
4367 .num_internal_phys = 5,
4370 .port_base_addr = 0x10,
4371 .phy_base_addr = 0x0,
4372 .global1_addr = 0x1b,
4373 .global2_addr = 0x1c,
4374 .age_time_coeff = 15000,
4377 .atu_move_port_mask = 0xf,
4380 .tag_protocol = DSA_TAG_PROTO_EDSA,
4381 .ptp_support = true,
4382 .ops = &mv88e6320_ops,
4386 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4387 .family = MV88E6XXX_FAMILY_6320,
4388 .name = "Marvell 88E6321",
4389 .num_databases = 4096,
4391 .num_internal_phys = 5,
4394 .port_base_addr = 0x10,
4395 .phy_base_addr = 0x0,
4396 .global1_addr = 0x1b,
4397 .global2_addr = 0x1c,
4398 .age_time_coeff = 15000,
4401 .atu_move_port_mask = 0xf,
4403 .tag_protocol = DSA_TAG_PROTO_EDSA,
4404 .ptp_support = true,
4405 .ops = &mv88e6321_ops,
4409 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
4410 .family = MV88E6XXX_FAMILY_6341,
4411 .name = "Marvell 88E6341",
4412 .num_databases = 4096,
4413 .num_internal_phys = 5,
4417 .port_base_addr = 0x10,
4418 .phy_base_addr = 0x10,
4419 .global1_addr = 0x1b,
4420 .global2_addr = 0x1c,
4421 .age_time_coeff = 3750,
4422 .atu_move_port_mask = 0x1f,
4427 .tag_protocol = DSA_TAG_PROTO_EDSA,
4428 .ptp_support = true,
4429 .ops = &mv88e6341_ops,
4433 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4434 .family = MV88E6XXX_FAMILY_6351,
4435 .name = "Marvell 88E6350",
4436 .num_databases = 4096,
4438 .num_internal_phys = 5,
4440 .port_base_addr = 0x10,
4441 .phy_base_addr = 0x0,
4442 .global1_addr = 0x1b,
4443 .global2_addr = 0x1c,
4444 .age_time_coeff = 15000,
4447 .atu_move_port_mask = 0xf,
4450 .tag_protocol = DSA_TAG_PROTO_EDSA,
4451 .ops = &mv88e6350_ops,
4455 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4456 .family = MV88E6XXX_FAMILY_6351,
4457 .name = "Marvell 88E6351",
4458 .num_databases = 4096,
4460 .num_internal_phys = 5,
4462 .port_base_addr = 0x10,
4463 .phy_base_addr = 0x0,
4464 .global1_addr = 0x1b,
4465 .global2_addr = 0x1c,
4466 .age_time_coeff = 15000,
4469 .atu_move_port_mask = 0xf,
4472 .tag_protocol = DSA_TAG_PROTO_EDSA,
4473 .ops = &mv88e6351_ops,
4477 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4478 .family = MV88E6XXX_FAMILY_6352,
4479 .name = "Marvell 88E6352",
4480 .num_databases = 4096,
4482 .num_internal_phys = 5,
4485 .port_base_addr = 0x10,
4486 .phy_base_addr = 0x0,
4487 .global1_addr = 0x1b,
4488 .global2_addr = 0x1c,
4489 .age_time_coeff = 15000,
4492 .atu_move_port_mask = 0xf,
4495 .tag_protocol = DSA_TAG_PROTO_EDSA,
4496 .ptp_support = true,
4497 .ops = &mv88e6352_ops,
4500 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4501 .family = MV88E6XXX_FAMILY_6390,
4502 .name = "Marvell 88E6390",
4503 .num_databases = 4096,
4504 .num_ports = 11, /* 10 + Z80 */
4505 .num_internal_phys = 11,
4508 .port_base_addr = 0x0,
4509 .phy_base_addr = 0x0,
4510 .global1_addr = 0x1b,
4511 .global2_addr = 0x1c,
4512 .age_time_coeff = 3750,
4515 .atu_move_port_mask = 0x1f,
4518 .tag_protocol = DSA_TAG_PROTO_DSA,
4519 .ptp_support = true,
4520 .ops = &mv88e6390_ops,
4523 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4524 .family = MV88E6XXX_FAMILY_6390,
4525 .name = "Marvell 88E6390X",
4526 .num_databases = 4096,
4527 .num_ports = 11, /* 10 + Z80 */
4528 .num_internal_phys = 11,
4531 .port_base_addr = 0x0,
4532 .phy_base_addr = 0x0,
4533 .global1_addr = 0x1b,
4534 .global2_addr = 0x1c,
4535 .age_time_coeff = 3750,
4538 .atu_move_port_mask = 0x1f,
4541 .tag_protocol = DSA_TAG_PROTO_DSA,
4542 .ptp_support = true,
4543 .ops = &mv88e6390x_ops,
4547 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4551 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4552 if (mv88e6xxx_table[i].prod_num == prod_num)
4553 return &mv88e6xxx_table[i];
4558 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4560 const struct mv88e6xxx_info *info;
4561 unsigned int prod_num, rev;
4565 mutex_lock(&chip->reg_lock);
4566 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4567 mutex_unlock(&chip->reg_lock);
4571 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
4572 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4574 info = mv88e6xxx_lookup_info(prod_num);
4578 /* Update the compatible info with the probed one */
4581 err = mv88e6xxx_g2_require(chip);
4585 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4586 chip->info->prod_num, chip->info->name, rev);
4591 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4593 struct mv88e6xxx_chip *chip;
4595 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4601 mutex_init(&chip->reg_lock);
4602 INIT_LIST_HEAD(&chip->mdios);
4607 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4608 struct mii_bus *bus, int sw_addr)
4611 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4612 else if (chip->info->multi_chip)
4613 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4618 chip->sw_addr = sw_addr;
4623 static void mv88e6xxx_ports_cmode_init(struct mv88e6xxx_chip *chip)
4627 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
4628 chip->ports[i].cmode = MV88E6XXX_PORT_STS_CMODE_INVALID;
4631 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4634 struct mv88e6xxx_chip *chip = ds->priv;
4636 return chip->info->tag_protocol;
4639 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4640 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4641 struct device *host_dev, int sw_addr,
4644 struct mv88e6xxx_chip *chip;
4645 struct mii_bus *bus;
4648 bus = dsa_host_dev_to_mii_bus(host_dev);
4652 chip = mv88e6xxx_alloc_chip(dsa_dev);
4656 /* Legacy SMI probing will only support chips similar to 88E6085 */
4657 chip->info = &mv88e6xxx_table[MV88E6085];
4659 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4663 err = mv88e6xxx_detect(chip);
4667 mv88e6xxx_ports_cmode_init(chip);
4669 mutex_lock(&chip->reg_lock);
4670 err = mv88e6xxx_switch_reset(chip);
4671 mutex_unlock(&chip->reg_lock);
4675 mv88e6xxx_phy_init(chip);
4677 err = mv88e6xxx_mdios_register(chip, NULL);
4683 return chip->info->name;
4685 devm_kfree(dsa_dev, chip);
4691 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4692 const struct switchdev_obj_port_mdb *mdb)
4694 /* We don't need any dynamic resource from the kernel (yet),
4695 * so skip the prepare phase.
4701 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4702 const struct switchdev_obj_port_mdb *mdb)
4704 struct mv88e6xxx_chip *chip = ds->priv;
4706 mutex_lock(&chip->reg_lock);
4707 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4708 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4709 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4711 mutex_unlock(&chip->reg_lock);
4714 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4715 const struct switchdev_obj_port_mdb *mdb)
4717 struct mv88e6xxx_chip *chip = ds->priv;
4720 mutex_lock(&chip->reg_lock);
4721 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4722 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4723 mutex_unlock(&chip->reg_lock);
4728 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
4729 bool unicast, bool multicast)
4731 struct mv88e6xxx_chip *chip = ds->priv;
4732 int err = -EOPNOTSUPP;
4734 mutex_lock(&chip->reg_lock);
4735 if (chip->info->ops->port_set_egress_floods)
4736 err = chip->info->ops->port_set_egress_floods(chip, port,
4739 mutex_unlock(&chip->reg_lock);
4744 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4745 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4746 .probe = mv88e6xxx_drv_probe,
4748 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4749 .setup = mv88e6xxx_setup,
4750 .adjust_link = mv88e6xxx_adjust_link,
4751 .phylink_validate = mv88e6xxx_validate,
4752 .phylink_mac_link_state = mv88e6xxx_link_state,
4753 .phylink_mac_config = mv88e6xxx_mac_config,
4754 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
4755 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
4756 .get_strings = mv88e6xxx_get_strings,
4757 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4758 .get_sset_count = mv88e6xxx_get_sset_count,
4759 .port_enable = mv88e6xxx_port_enable,
4760 .port_disable = mv88e6xxx_port_disable,
4761 .get_mac_eee = mv88e6xxx_get_mac_eee,
4762 .set_mac_eee = mv88e6xxx_set_mac_eee,
4763 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4764 .get_eeprom = mv88e6xxx_get_eeprom,
4765 .set_eeprom = mv88e6xxx_set_eeprom,
4766 .get_regs_len = mv88e6xxx_get_regs_len,
4767 .get_regs = mv88e6xxx_get_regs,
4768 .set_ageing_time = mv88e6xxx_set_ageing_time,
4769 .port_bridge_join = mv88e6xxx_port_bridge_join,
4770 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4771 .port_egress_floods = mv88e6xxx_port_egress_floods,
4772 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4773 .port_fast_age = mv88e6xxx_port_fast_age,
4774 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4775 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4776 .port_vlan_add = mv88e6xxx_port_vlan_add,
4777 .port_vlan_del = mv88e6xxx_port_vlan_del,
4778 .port_fdb_add = mv88e6xxx_port_fdb_add,
4779 .port_fdb_del = mv88e6xxx_port_fdb_del,
4780 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4781 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4782 .port_mdb_add = mv88e6xxx_port_mdb_add,
4783 .port_mdb_del = mv88e6xxx_port_mdb_del,
4784 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4785 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4786 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
4787 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
4788 .port_txtstamp = mv88e6xxx_port_txtstamp,
4789 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
4790 .get_ts_info = mv88e6xxx_get_ts_info,
4793 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4794 .ops = &mv88e6xxx_switch_ops,
4797 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4799 struct device *dev = chip->dev;
4800 struct dsa_switch *ds;
4802 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4808 ds->ops = &mv88e6xxx_switch_ops;
4809 ds->ageing_time_min = chip->info->age_time_coeff;
4810 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4812 dev_set_drvdata(dev, ds);
4814 return dsa_register_switch(ds);
4817 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4819 dsa_unregister_switch(chip->ds);
4822 static const void *pdata_device_get_match_data(struct device *dev)
4824 const struct of_device_id *matches = dev->driver->of_match_table;
4825 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
4827 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
4829 if (!strcmp(pdata->compatible, matches->compatible))
4830 return matches->data;
4835 /* There is no suspend to RAM support at DSA level yet, the switch configuration
4836 * would be lost after a power cycle so prevent it to be suspended.
4838 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
4843 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
4848 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
4850 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4852 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
4853 const struct mv88e6xxx_info *compat_info = NULL;
4854 struct device *dev = &mdiodev->dev;
4855 struct device_node *np = dev->of_node;
4856 struct mv88e6xxx_chip *chip;
4864 compat_info = of_device_get_match_data(dev);
4867 compat_info = pdata_device_get_match_data(dev);
4872 for (port = 0; port < DSA_MAX_PORTS; port++) {
4873 if (!(pdata->enabled_ports & (1 << port)))
4875 if (strcmp(pdata->cd.port_names[port], "cpu"))
4877 pdata->cd.netdev[port] = &pdata->netdev->dev;
4885 chip = mv88e6xxx_alloc_chip(dev);
4891 chip->info = compat_info;
4893 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4897 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4898 if (IS_ERR(chip->reset)) {
4899 err = PTR_ERR(chip->reset);
4903 err = mv88e6xxx_detect(chip);
4907 mv88e6xxx_ports_cmode_init(chip);
4908 mv88e6xxx_phy_init(chip);
4910 if (chip->info->ops->get_eeprom) {
4912 of_property_read_u32(np, "eeprom-length",
4915 chip->eeprom_len = pdata->eeprom_len;
4918 mutex_lock(&chip->reg_lock);
4919 err = mv88e6xxx_switch_reset(chip);
4920 mutex_unlock(&chip->reg_lock);
4924 chip->irq = of_irq_get(np, 0);
4925 if (chip->irq == -EPROBE_DEFER) {
4930 /* Has to be performed before the MDIO bus is created, because
4931 * the PHYs will link their interrupts to these interrupt
4934 mutex_lock(&chip->reg_lock);
4936 err = mv88e6xxx_g1_irq_setup(chip);
4938 err = mv88e6xxx_irq_poll_setup(chip);
4939 mutex_unlock(&chip->reg_lock);
4944 if (chip->info->g2_irqs > 0) {
4945 err = mv88e6xxx_g2_irq_setup(chip);
4950 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
4954 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
4956 goto out_g1_atu_prob_irq;
4958 err = mv88e6xxx_mdios_register(chip, np);
4960 goto out_g1_vtu_prob_irq;
4962 err = mv88e6xxx_register_switch(chip);
4969 mv88e6xxx_mdios_unregister(chip);
4970 out_g1_vtu_prob_irq:
4971 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4972 out_g1_atu_prob_irq:
4973 mv88e6xxx_g1_atu_prob_irq_free(chip);
4975 if (chip->info->g2_irqs > 0)
4976 mv88e6xxx_g2_irq_free(chip);
4979 mv88e6xxx_g1_irq_free(chip);
4981 mv88e6xxx_irq_poll_free(chip);
4984 dev_put(pdata->netdev);
4989 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4991 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4992 struct mv88e6xxx_chip *chip = ds->priv;
4994 if (chip->info->ptp_support) {
4995 mv88e6xxx_hwtstamp_free(chip);
4996 mv88e6xxx_ptp_free(chip);
4999 mv88e6xxx_phy_destroy(chip);
5000 mv88e6xxx_unregister_switch(chip);
5001 mv88e6xxx_mdios_unregister(chip);
5003 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5004 mv88e6xxx_g1_atu_prob_irq_free(chip);
5006 if (chip->info->g2_irqs > 0)
5007 mv88e6xxx_g2_irq_free(chip);
5010 mv88e6xxx_g1_irq_free(chip);
5012 mv88e6xxx_irq_poll_free(chip);
5015 static const struct of_device_id mv88e6xxx_of_match[] = {
5017 .compatible = "marvell,mv88e6085",
5018 .data = &mv88e6xxx_table[MV88E6085],
5021 .compatible = "marvell,mv88e6190",
5022 .data = &mv88e6xxx_table[MV88E6190],
5027 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5029 static struct mdio_driver mv88e6xxx_driver = {
5030 .probe = mv88e6xxx_probe,
5031 .remove = mv88e6xxx_remove,
5033 .name = "mv88e6085",
5034 .of_match_table = mv88e6xxx_of_match,
5035 .pm = &mv88e6xxx_pm_ops,
5039 static int __init mv88e6xxx_init(void)
5041 register_switch_driver(&mv88e6xxx_switch_drv);
5042 return mdio_driver_register(&mv88e6xxx_driver);
5044 module_init(mv88e6xxx_init);
5046 static void __exit mv88e6xxx_cleanup(void)
5048 mdio_driver_unregister(&mv88e6xxx_driver);
5049 unregister_switch_driver(&mv88e6xxx_switch_drv);
5051 module_exit(mv88e6xxx_cleanup);
5053 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5054 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5055 MODULE_LICENSE("GPL");