2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
43 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
64 int addr, int reg, u16 *val)
69 return chip->smi_ops->read(chip, addr, reg, val);
72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
73 int addr, int reg, u16 val)
78 return chip->smi_ops->write(chip, addr, reg, val);
81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
82 int addr, int reg, u16 *val)
86 ret = mdiobus_read_nested(chip->bus, addr, reg);
95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
96 int addr, int reg, u16 val)
100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
117 for (i = 0; i < 16; i++) {
118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
122 if ((ret & SMI_CMD_BUSY) == 0)
129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
130 int addr, int reg, u16 *val)
134 /* Wait for the bus to become free. */
135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
139 /* Transmit the read command. */
140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
145 /* Wait for the read command to complete. */
146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
161 int addr, int reg, u16 val)
165 /* Wait for the bus to become free. */
166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
170 /* Transmit the data to write. */
171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
175 /* Transmit the write command. */
176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
181 /* Wait for the write command to complete. */
182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
198 assert_reg_lock(chip);
200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
214 assert_reg_lock(chip);
216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
228 struct mv88e6xxx_mdio_bus *mdio_bus;
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
235 return mdio_bus->bus;
238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
243 chip->g1_irq.masked |= (1 << n);
246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
251 chip->g1_irq.masked &= ~(1 << n);
254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
263 mutex_lock(&chip->reg_lock);
264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
265 mutex_unlock(&chip->reg_lock);
270 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
271 if (reg & (1 << n)) {
272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
273 handle_nested_irq(sub_irq);
278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
285 mutex_lock(&chip->reg_lock);
288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
300 reg |= (~chip->g1_irq.masked & mask);
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
307 mutex_unlock(&chip->reg_lock);
310 static struct irq_chip mv88e6xxx_g1_irq_chip = {
311 .name = "mv88e6xxx-g1",
312 .irq_mask = mv88e6xxx_g1_irq_mask,
313 .irq_unmask = mv88e6xxx_g1_irq_unmask,
314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
320 irq_hw_number_t hwirq)
322 struct mv88e6xxx_chip *chip = d->host_data;
324 irq_set_chip_data(irq, d->host_data);
325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
326 irq_set_noprobe(irq);
331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
332 .map = mv88e6xxx_g1_irq_domain_map,
333 .xlate = irq_domain_xlate_twocell,
336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
342 mask |= GENMASK(chip->g1_irq.nirqs, 0);
343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
345 free_irq(chip->irq, chip);
347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
348 virq = irq_find_mapping(chip->g1_irq.domain, irq);
349 irq_dispose_mapping(virq);
352 irq_domain_remove(chip->g1_irq.domain);
355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
360 chip->g1_irq.nirqs = chip->info->g1_irqs;
361 chip->g1_irq.domain = irq_domain_add_simple(
362 NULL, chip->g1_irq.nirqs, 0,
363 &mv88e6xxx_g1_irq_domain_ops, chip);
364 if (!chip->g1_irq.domain)
367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
368 irq_create_mapping(chip->g1_irq.domain, irq);
370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
371 chip->g1_irq.masked = ~0;
373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
383 /* Reading the interrupt status clears (most of) them */
384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
388 err = request_threaded_irq(chip->irq, NULL,
389 mv88e6xxx_g1_irq_thread_fn,
390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
391 dev_name(chip->dev), chip);
398 mask |= GENMASK(chip->g1_irq.nirqs, 0);
399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
402 for (irq = 0; irq < 16; irq++) {
403 virq = irq_find_mapping(chip->g1_irq.domain, irq);
404 irq_dispose_mapping(virq);
407 irq_domain_remove(chip->g1_irq.domain);
412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
416 for (i = 0; i < 16; i++) {
420 err = mv88e6xxx_read(chip, addr, reg, &val);
427 usleep_range(1000, 2000);
430 dev_err(chip->dev, "Timeout while waiting for switch\n");
434 /* Indirect write to single pointer-data register with an Update bit */
435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
440 /* Wait until the previous operation is completed */
441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
445 /* Set the Update bit to trigger a write operation */
446 val = BIT(15) | update;
448 return mv88e6xxx_write(chip, addr, reg, val);
451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452 int link, int speed, int duplex,
453 phy_interface_t mode)
457 if (!chip->info->ops->port_set_link)
460 /* Port's MAC control must not be changed unless the link is down */
461 err = chip->info->ops->port_set_link(chip, port, 0);
465 if (chip->info->ops->port_set_speed) {
466 err = chip->info->ops->port_set_speed(chip, port, speed);
467 if (err && err != -EOPNOTSUPP)
471 if (chip->info->ops->port_set_duplex) {
472 err = chip->info->ops->port_set_duplex(chip, port, duplex);
473 if (err && err != -EOPNOTSUPP)
477 if (chip->info->ops->port_set_rgmii_delay) {
478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
479 if (err && err != -EOPNOTSUPP)
483 if (chip->info->ops->port_set_cmode) {
484 err = chip->info->ops->port_set_cmode(chip, port, mode);
485 if (err && err != -EOPNOTSUPP)
491 if (chip->info->ops->port_set_link(chip, port, link))
492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
497 /* We expect the switch to perform auto negotiation if there is a real
498 * phy. However, in the case of a fixed link phy, we force the port
499 * settings from the fixed link settings.
501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
502 struct phy_device *phydev)
504 struct mv88e6xxx_chip *chip = ds->priv;
507 if (!phy_is_pseudo_fixed_link(phydev))
510 mutex_lock(&chip->reg_lock);
511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
512 phydev->duplex, phydev->interface);
513 mutex_unlock(&chip->reg_lock);
515 if (err && err != -EOPNOTSUPP)
516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
521 if (!chip->info->ops->stats_snapshot)
524 return chip->info->ops->stats_snapshot(chip, port);
527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
548 { "single", 4, 0x14, STATS_TYPE_BANK0, },
549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
551 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
590 struct mv88e6xxx_hw_stat *s,
591 int port, u16 bank1_select,
601 case STATS_TYPE_PORT:
602 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
607 if (s->sizeof_stat == 4) {
608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
614 case STATS_TYPE_BANK1:
617 case STATS_TYPE_BANK0:
618 reg |= s->reg | histogram;
619 mv88e6xxx_g1_stats_read(chip, reg, &low);
620 if (s->sizeof_stat == 8)
621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
626 value = (((u64)high) << 16) | low;
630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
631 uint8_t *data, int types)
633 struct mv88e6xxx_hw_stat *stat;
636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
637 stat = &mv88e6xxx_hw_stats[i];
638 if (stat->type & types) {
639 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
649 mv88e6xxx_stats_get_strings(chip, data,
650 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
656 mv88e6xxx_stats_get_strings(chip, data,
657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
663 struct mv88e6xxx_chip *chip = ds->priv;
665 if (chip->info->ops->stats_get_strings)
666 chip->info->ops->stats_get_strings(chip, data);
669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
672 struct mv88e6xxx_hw_stat *stat;
675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
676 stat = &mv88e6xxx_hw_stats[i];
677 if (stat->type & types)
683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
697 struct mv88e6xxx_chip *chip = ds->priv;
699 if (chip->info->ops->stats_get_sset_count)
700 return chip->info->ops->stats_get_sset_count(chip);
705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
706 uint64_t *data, int types,
707 u16 bank1_select, u16 histogram)
709 struct mv88e6xxx_hw_stat *stat;
712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
713 stat = &mv88e6xxx_hw_stats[i];
714 if (stat->type & types) {
715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
726 return mv88e6xxx_stats_get_stats(chip, port, data,
727 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
734 return mv88e6xxx_stats_get_stats(chip, port, data,
735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
743 return mv88e6xxx_stats_get_stats(chip, port, data,
744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
752 if (chip->info->ops->stats_get_stats)
753 chip->info->ops->stats_get_stats(chip, port, data);
756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
759 struct mv88e6xxx_chip *chip = ds->priv;
762 mutex_lock(&chip->reg_lock);
764 ret = mv88e6xxx_stats_snapshot(chip, port);
766 mutex_unlock(&chip->reg_lock);
770 mv88e6xxx_get_stats(chip, port, data);
772 mutex_unlock(&chip->reg_lock);
775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
777 if (chip->info->ops->stats_set_histogram)
778 return chip->info->ops->stats_set_histogram(chip);
783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
785 return 32 * sizeof(u16);
788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
789 struct ethtool_regs *regs, void *_p)
791 struct mv88e6xxx_chip *chip = ds->priv;
799 memset(p, 0xff, 32 * sizeof(u16));
801 mutex_lock(&chip->reg_lock);
803 for (i = 0; i < 32; i++) {
805 err = mv88e6xxx_port_read(chip, port, i, ®);
810 mutex_unlock(&chip->reg_lock);
813 static int mv88e6xxx_energy_detect_read(struct mv88e6xxx_chip *chip, int port,
814 struct ethtool_eee *eee)
818 if (!chip->info->ops->phy_energy_detect_read)
821 /* assign eee->eee_enabled and eee->tx_lpi_enabled */
822 err = chip->info->ops->phy_energy_detect_read(chip, port, eee);
826 /* assign eee->eee_active */
827 return mv88e6xxx_port_status_eee(chip, port, eee);
830 static int mv88e6xxx_energy_detect_write(struct mv88e6xxx_chip *chip, int port,
831 struct ethtool_eee *eee)
833 if (!chip->info->ops->phy_energy_detect_write)
836 return chip->info->ops->phy_energy_detect_write(chip, port, eee);
839 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
840 struct ethtool_eee *e)
842 struct mv88e6xxx_chip *chip = ds->priv;
845 mutex_lock(&chip->reg_lock);
846 err = mv88e6xxx_energy_detect_read(chip, port, e);
847 mutex_unlock(&chip->reg_lock);
852 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
853 struct phy_device *phydev, struct ethtool_eee *e)
855 struct mv88e6xxx_chip *chip = ds->priv;
858 mutex_lock(&chip->reg_lock);
859 err = mv88e6xxx_energy_detect_write(chip, port, e);
860 mutex_unlock(&chip->reg_lock);
865 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
867 struct dsa_switch *ds = NULL;
868 struct net_device *br;
872 if (dev < DSA_MAX_SWITCHES)
873 ds = chip->ds->dst->ds[dev];
875 /* Prevent frames from unknown switch or port */
876 if (!ds || port >= ds->num_ports)
879 /* Frames from DSA links and CPU ports can egress any local port */
880 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
881 return mv88e6xxx_port_mask(chip);
883 br = ds->ports[port].bridge_dev;
886 /* Frames from user ports can egress any local DSA links and CPU ports,
887 * as well as any local member of their bridge group.
889 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
890 if (dsa_is_cpu_port(chip->ds, i) ||
891 dsa_is_dsa_port(chip->ds, i) ||
892 (br && chip->ds->ports[i].bridge_dev == br))
898 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
900 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
902 /* prevent frames from going back out of the port they came in on */
903 output_ports &= ~BIT(port);
905 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
908 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
911 struct mv88e6xxx_chip *chip = ds->priv;
914 mutex_lock(&chip->reg_lock);
915 err = mv88e6xxx_port_set_state(chip, port, state);
916 mutex_unlock(&chip->reg_lock);
919 dev_err(ds->dev, "p%d: failed to update state\n", port);
922 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
924 if (chip->info->ops->pot_clear)
925 return chip->info->ops->pot_clear(chip);
930 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
932 if (chip->info->ops->mgmt_rsvd2cpu)
933 return chip->info->ops->mgmt_rsvd2cpu(chip);
938 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
942 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
946 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
950 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
953 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
958 if (!chip->info->ops->irl_init_all)
961 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
962 /* Disable ingress rate limiting by resetting all per port
963 * ingress rate limit resources to their initial state.
965 err = chip->info->ops->irl_init_all(chip, port);
973 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
977 if (!mv88e6xxx_has_pvt(chip))
980 /* Skip the local source device, which uses in-chip port VLAN */
981 if (dev != chip->ds->index)
982 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
984 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
987 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
992 if (!mv88e6xxx_has_pvt(chip))
995 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
996 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
998 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1002 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1003 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1004 err = mv88e6xxx_pvt_map(chip, dev, port);
1013 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1015 struct mv88e6xxx_chip *chip = ds->priv;
1018 mutex_lock(&chip->reg_lock);
1019 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1020 mutex_unlock(&chip->reg_lock);
1023 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1026 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1028 if (!chip->info->max_vid)
1031 return mv88e6xxx_g1_vtu_flush(chip);
1034 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1035 struct mv88e6xxx_vtu_entry *entry)
1037 if (!chip->info->ops->vtu_getnext)
1040 return chip->info->ops->vtu_getnext(chip, entry);
1043 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1044 struct mv88e6xxx_vtu_entry *entry)
1046 if (!chip->info->ops->vtu_loadpurge)
1049 return chip->info->ops->vtu_loadpurge(chip, entry);
1052 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1053 struct switchdev_obj_port_vlan *vlan,
1054 switchdev_obj_dump_cb_t *cb)
1056 struct mv88e6xxx_chip *chip = ds->priv;
1057 struct mv88e6xxx_vtu_entry next = {
1058 .vid = chip->info->max_vid,
1063 if (!chip->info->max_vid)
1066 mutex_lock(&chip->reg_lock);
1068 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1073 err = mv88e6xxx_vtu_getnext(chip, &next);
1080 if (next.member[port] ==
1081 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1084 /* reinit and dump this VLAN obj */
1085 vlan->vid_begin = next.vid;
1086 vlan->vid_end = next.vid;
1089 if (next.member[port] ==
1090 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED)
1091 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1093 if (next.vid == pvid)
1094 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1096 err = cb(&vlan->obj);
1099 } while (next.vid < chip->info->max_vid);
1102 mutex_unlock(&chip->reg_lock);
1107 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1109 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1110 struct mv88e6xxx_vtu_entry vlan = {
1111 .vid = chip->info->max_vid,
1115 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1117 /* Set every FID bit used by the (un)bridged ports */
1118 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1119 err = mv88e6xxx_port_get_fid(chip, i, fid);
1123 set_bit(*fid, fid_bitmap);
1126 /* Set every FID bit used by the VLAN entries */
1128 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1135 set_bit(vlan.fid, fid_bitmap);
1136 } while (vlan.vid < chip->info->max_vid);
1138 /* The reset value 0x000 is used to indicate that multiple address
1139 * databases are not needed. Return the next positive available.
1141 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1142 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1145 /* Clear the database */
1146 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1149 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1150 struct mv88e6xxx_vtu_entry *entry, bool new)
1157 entry->vid = vid - 1;
1158 entry->valid = false;
1160 err = mv88e6xxx_vtu_getnext(chip, entry);
1164 if (entry->vid == vid && entry->valid)
1170 /* Initialize a fresh VLAN entry */
1171 memset(entry, 0, sizeof(*entry));
1172 entry->valid = true;
1175 /* Exclude all ports */
1176 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1178 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1180 return mv88e6xxx_atu_new(chip, &entry->fid);
1183 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1187 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1188 u16 vid_begin, u16 vid_end)
1190 struct mv88e6xxx_chip *chip = ds->priv;
1191 struct mv88e6xxx_vtu_entry vlan = {
1192 .vid = vid_begin - 1,
1199 mutex_lock(&chip->reg_lock);
1202 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1209 if (vlan.vid > vid_end)
1212 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1213 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1216 if (!ds->ports[port].netdev)
1219 if (vlan.member[i] ==
1220 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1223 if (ds->ports[i].bridge_dev ==
1224 ds->ports[port].bridge_dev)
1225 break; /* same bridge, check next VLAN */
1227 if (!ds->ports[i].bridge_dev)
1230 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
1232 netdev_name(ds->ports[i].bridge_dev));
1236 } while (vlan.vid < vid_end);
1239 mutex_unlock(&chip->reg_lock);
1244 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1245 bool vlan_filtering)
1247 struct mv88e6xxx_chip *chip = ds->priv;
1248 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1249 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1252 if (!chip->info->max_vid)
1255 mutex_lock(&chip->reg_lock);
1256 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1257 mutex_unlock(&chip->reg_lock);
1263 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1264 const struct switchdev_obj_port_vlan *vlan,
1265 struct switchdev_trans *trans)
1267 struct mv88e6xxx_chip *chip = ds->priv;
1270 if (!chip->info->max_vid)
1273 /* If the requested port doesn't belong to the same bridge as the VLAN
1274 * members, do not support it (yet) and fallback to software VLAN.
1276 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1281 /* We don't need any dynamic resource from the kernel (yet),
1282 * so skip the prepare phase.
1287 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1290 struct mv88e6xxx_vtu_entry vlan;
1293 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1297 vlan.member[port] = member;
1299 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
1302 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1303 const struct switchdev_obj_port_vlan *vlan,
1304 struct switchdev_trans *trans)
1306 struct mv88e6xxx_chip *chip = ds->priv;
1307 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1308 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1312 if (!chip->info->max_vid)
1315 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1316 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1318 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1320 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1322 mutex_lock(&chip->reg_lock);
1324 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1325 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1326 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1327 vid, untagged ? 'u' : 't');
1329 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1330 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1333 mutex_unlock(&chip->reg_lock);
1336 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1339 struct mv88e6xxx_vtu_entry vlan;
1342 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1346 /* Tell switchdev if this VLAN is handled in software */
1347 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1350 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1352 /* keep the VLAN unless all ports are excluded */
1354 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1355 if (vlan.member[i] !=
1356 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1362 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1366 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1369 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1370 const struct switchdev_obj_port_vlan *vlan)
1372 struct mv88e6xxx_chip *chip = ds->priv;
1376 if (!chip->info->max_vid)
1379 mutex_lock(&chip->reg_lock);
1381 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1385 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1386 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1391 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1398 mutex_unlock(&chip->reg_lock);
1403 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1404 const unsigned char *addr, u16 vid,
1407 struct mv88e6xxx_vtu_entry vlan;
1408 struct mv88e6xxx_atu_entry entry;
1411 /* Null VLAN ID corresponds to the port private database */
1413 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1415 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1419 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1420 ether_addr_copy(entry.mac, addr);
1421 eth_addr_dec(entry.mac);
1423 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1427 /* Initialize a fresh ATU entry if it isn't found */
1428 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1429 !ether_addr_equal(entry.mac, addr)) {
1430 memset(&entry, 0, sizeof(entry));
1431 ether_addr_copy(entry.mac, addr);
1434 /* Purge the ATU entry only if no port is using it anymore */
1435 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1436 entry.portvec &= ~BIT(port);
1438 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1440 entry.portvec |= BIT(port);
1441 entry.state = state;
1444 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1447 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1448 const struct switchdev_obj_port_fdb *fdb,
1449 struct switchdev_trans *trans)
1451 /* We don't need any dynamic resource from the kernel (yet),
1452 * so skip the prepare phase.
1457 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1458 const struct switchdev_obj_port_fdb *fdb,
1459 struct switchdev_trans *trans)
1461 struct mv88e6xxx_chip *chip = ds->priv;
1463 mutex_lock(&chip->reg_lock);
1464 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1465 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC))
1466 dev_err(ds->dev, "p%d: failed to load unicast MAC address\n",
1468 mutex_unlock(&chip->reg_lock);
1471 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1472 const struct switchdev_obj_port_fdb *fdb)
1474 struct mv88e6xxx_chip *chip = ds->priv;
1477 mutex_lock(&chip->reg_lock);
1478 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1479 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1480 mutex_unlock(&chip->reg_lock);
1485 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1486 u16 fid, u16 vid, int port,
1487 struct switchdev_obj *obj,
1488 switchdev_obj_dump_cb_t *cb)
1490 struct mv88e6xxx_atu_entry addr;
1493 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1494 eth_broadcast_addr(addr.mac);
1497 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1501 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1504 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1507 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1508 struct switchdev_obj_port_fdb *fdb;
1510 if (!is_unicast_ether_addr(addr.mac))
1513 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
1515 ether_addr_copy(fdb->addr, addr.mac);
1516 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1517 fdb->ndm_state = NUD_NOARP;
1519 fdb->ndm_state = NUD_REACHABLE;
1520 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
1521 struct switchdev_obj_port_mdb *mdb;
1523 if (!is_multicast_ether_addr(addr.mac))
1526 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
1528 ether_addr_copy(mdb->addr, addr.mac);
1536 } while (!is_broadcast_ether_addr(addr.mac));
1541 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1542 struct switchdev_obj *obj,
1543 switchdev_obj_dump_cb_t *cb)
1545 struct mv88e6xxx_vtu_entry vlan = {
1546 .vid = chip->info->max_vid,
1551 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1552 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1556 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
1560 /* Dump VLANs' Filtering Information Databases */
1562 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1569 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1573 } while (vlan.vid < chip->info->max_vid);
1578 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1579 struct switchdev_obj_port_fdb *fdb,
1580 switchdev_obj_dump_cb_t *cb)
1582 struct mv88e6xxx_chip *chip = ds->priv;
1585 mutex_lock(&chip->reg_lock);
1586 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
1587 mutex_unlock(&chip->reg_lock);
1592 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1593 struct net_device *br)
1595 struct dsa_switch *ds;
1600 /* Remap the Port VLAN of each local bridge group member */
1601 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1602 if (chip->ds->ports[port].bridge_dev == br) {
1603 err = mv88e6xxx_port_vlan_map(chip, port);
1609 if (!mv88e6xxx_has_pvt(chip))
1612 /* Remap the Port VLAN of each cross-chip bridge group member */
1613 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1614 ds = chip->ds->dst->ds[dev];
1618 for (port = 0; port < ds->num_ports; ++port) {
1619 if (ds->ports[port].bridge_dev == br) {
1620 err = mv88e6xxx_pvt_map(chip, dev, port);
1630 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1631 struct net_device *br)
1633 struct mv88e6xxx_chip *chip = ds->priv;
1636 mutex_lock(&chip->reg_lock);
1637 err = mv88e6xxx_bridge_map(chip, br);
1638 mutex_unlock(&chip->reg_lock);
1643 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1644 struct net_device *br)
1646 struct mv88e6xxx_chip *chip = ds->priv;
1648 mutex_lock(&chip->reg_lock);
1649 if (mv88e6xxx_bridge_map(chip, br) ||
1650 mv88e6xxx_port_vlan_map(chip, port))
1651 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1652 mutex_unlock(&chip->reg_lock);
1655 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1656 int port, struct net_device *br)
1658 struct mv88e6xxx_chip *chip = ds->priv;
1661 if (!mv88e6xxx_has_pvt(chip))
1664 mutex_lock(&chip->reg_lock);
1665 err = mv88e6xxx_pvt_map(chip, dev, port);
1666 mutex_unlock(&chip->reg_lock);
1671 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1672 int port, struct net_device *br)
1674 struct mv88e6xxx_chip *chip = ds->priv;
1676 if (!mv88e6xxx_has_pvt(chip))
1679 mutex_lock(&chip->reg_lock);
1680 if (mv88e6xxx_pvt_map(chip, dev, port))
1681 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1682 mutex_unlock(&chip->reg_lock);
1685 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1687 if (chip->info->ops->reset)
1688 return chip->info->ops->reset(chip);
1693 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1695 struct gpio_desc *gpiod = chip->reset;
1697 /* If there is a GPIO connected to the reset pin, toggle it */
1699 gpiod_set_value_cansleep(gpiod, 1);
1700 usleep_range(10000, 20000);
1701 gpiod_set_value_cansleep(gpiod, 0);
1702 usleep_range(10000, 20000);
1706 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1710 /* Set all ports to the Disabled state */
1711 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1712 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1717 /* Wait for transmit queues to drain,
1718 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1720 usleep_range(2000, 4000);
1725 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1729 err = mv88e6xxx_disable_ports(chip);
1733 mv88e6xxx_hardware_reset(chip);
1735 return mv88e6xxx_software_reset(chip);
1738 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1739 enum mv88e6xxx_frame_mode frame,
1740 enum mv88e6xxx_egress_mode egress, u16 etype)
1744 if (!chip->info->ops->port_set_frame_mode)
1747 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1751 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1755 if (chip->info->ops->port_set_ether_type)
1756 return chip->info->ops->port_set_ether_type(chip, port, etype);
1761 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1763 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1764 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1765 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1768 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1770 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1771 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1772 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1775 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1777 return mv88e6xxx_set_port_mode(chip, port,
1778 MV88E6XXX_FRAME_MODE_ETHERTYPE,
1779 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1783 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1785 if (dsa_is_dsa_port(chip->ds, port))
1786 return mv88e6xxx_set_port_mode_dsa(chip, port);
1788 if (dsa_is_normal_port(chip->ds, port))
1789 return mv88e6xxx_set_port_mode_normal(chip, port);
1791 /* Setup CPU port mode depending on its supported tag format */
1792 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1793 return mv88e6xxx_set_port_mode_dsa(chip, port);
1795 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1796 return mv88e6xxx_set_port_mode_edsa(chip, port);
1801 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1803 bool message = dsa_is_dsa_port(chip->ds, port);
1805 return mv88e6xxx_port_set_message_port(chip, port, message);
1808 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1810 bool flood = port == dsa_upstream_port(chip->ds);
1812 /* Upstream ports flood frames with unknown unicast or multicast DA */
1813 if (chip->info->ops->port_set_egress_floods)
1814 return chip->info->ops->port_set_egress_floods(chip, port,
1820 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1823 if (chip->info->ops->serdes_power)
1824 return chip->info->ops->serdes_power(chip, port, on);
1829 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1831 struct dsa_switch *ds = chip->ds;
1835 /* MAC Forcing register: don't force link, speed, duplex or flow control
1836 * state to any particular values on physical ports, but force the CPU
1837 * port and all DSA ports to their maximum bandwidth and full duplex.
1839 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1840 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1841 SPEED_MAX, DUPLEX_FULL,
1842 PHY_INTERFACE_MODE_NA);
1844 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1845 SPEED_UNFORCED, DUPLEX_UNFORCED,
1846 PHY_INTERFACE_MODE_NA);
1850 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1851 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1852 * tunneling, determine priority by looking at 802.1p and IP
1853 * priority fields (IP prio has precedence), and set STP state
1856 * If this is the CPU link, use DSA or EDSA tagging depending
1857 * on which tagging mode was configured.
1859 * If this is a link to another switch, use DSA tagging mode.
1861 * If this is the upstream port for this switch, enable
1862 * forwarding of unknown unicasts and multicasts.
1864 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1865 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1866 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1867 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1871 err = mv88e6xxx_setup_port_mode(chip, port);
1875 err = mv88e6xxx_setup_egress_floods(chip, port);
1879 /* Enable the SERDES interface for DSA and CPU ports. Normal
1880 * ports SERDES are enabled when the port is enabled, thus
1881 * saving a bit of power.
1883 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1884 err = mv88e6xxx_serdes_power(chip, port, true);
1889 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1890 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1891 * untagged frames on this port, do a destination address lookup on all
1892 * received packets as usual, disable ARP mirroring and don't send a
1893 * copy of all transmitted/received frames on this port to the CPU.
1895 err = mv88e6xxx_port_set_map_da(chip, port);
1900 if (chip->info->ops->port_set_upstream_port) {
1901 err = chip->info->ops->port_set_upstream_port(
1902 chip, port, dsa_upstream_port(ds));
1907 err = mv88e6xxx_port_set_8021q_mode(chip, port,
1908 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1912 if (chip->info->ops->port_set_jumbo_size) {
1913 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1918 /* Port Association Vector: when learning source addresses
1919 * of packets, add the address to the address database using
1920 * a port bitmap that has only the bit for this port set and
1921 * the other bits clear.
1924 /* Disable learning for CPU port */
1925 if (dsa_is_cpu_port(ds, port))
1928 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1933 /* Egress rate control 2: disable egress rate control. */
1934 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1939 if (chip->info->ops->port_pause_limit) {
1940 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1945 if (chip->info->ops->port_disable_learn_limit) {
1946 err = chip->info->ops->port_disable_learn_limit(chip, port);
1951 if (chip->info->ops->port_disable_pri_override) {
1952 err = chip->info->ops->port_disable_pri_override(chip, port);
1957 if (chip->info->ops->port_tag_remap) {
1958 err = chip->info->ops->port_tag_remap(chip, port);
1963 if (chip->info->ops->port_egress_rate_limiting) {
1964 err = chip->info->ops->port_egress_rate_limiting(chip, port);
1969 err = mv88e6xxx_setup_message_port(chip, port);
1973 /* Port based VLAN map: give each port the same default address
1974 * database, and allow bidirectional communication between the
1975 * CPU and DSA port(s), and the other ports.
1977 err = mv88e6xxx_port_set_fid(chip, port, 0);
1981 err = mv88e6xxx_port_vlan_map(chip, port);
1985 /* Default VLAN ID and priority: don't set a default VLAN
1986 * ID, and set the default packet priority to zero.
1988 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
1991 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1992 struct phy_device *phydev)
1994 struct mv88e6xxx_chip *chip = ds->priv;
1997 mutex_lock(&chip->reg_lock);
1998 err = mv88e6xxx_serdes_power(chip, port, true);
1999 mutex_unlock(&chip->reg_lock);
2004 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2005 struct phy_device *phydev)
2007 struct mv88e6xxx_chip *chip = ds->priv;
2009 mutex_lock(&chip->reg_lock);
2010 if (mv88e6xxx_serdes_power(chip, port, false))
2011 dev_err(chip->dev, "failed to power off SERDES\n");
2012 mutex_unlock(&chip->reg_lock);
2015 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2016 unsigned int ageing_time)
2018 struct mv88e6xxx_chip *chip = ds->priv;
2021 mutex_lock(&chip->reg_lock);
2022 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2023 mutex_unlock(&chip->reg_lock);
2028 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2030 struct dsa_switch *ds = chip->ds;
2031 u32 upstream_port = dsa_upstream_port(ds);
2034 if (chip->info->ops->set_cpu_port) {
2035 err = chip->info->ops->set_cpu_port(chip, upstream_port);
2040 if (chip->info->ops->set_egress_port) {
2041 err = chip->info->ops->set_egress_port(chip, upstream_port);
2046 /* Disable remote management, and set the switch's DSA device number. */
2047 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
2048 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
2049 (ds->index & 0x1f));
2053 /* Configure the IP ToS mapping registers. */
2054 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
2057 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
2060 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
2063 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
2066 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
2069 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
2072 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
2075 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
2079 /* Configure the IEEE 802.1p priority mapping register. */
2080 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
2084 /* Initialize the statistics unit */
2085 err = mv88e6xxx_stats_set_histogram(chip);
2089 /* Clear the statistics counters for all ports */
2090 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
2091 MV88E6XXX_G1_STATS_OP_BUSY |
2092 MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
2096 /* Wait for the flush to complete. */
2097 err = mv88e6xxx_g1_stats_wait(chip);
2104 static int mv88e6xxx_setup(struct dsa_switch *ds)
2106 struct mv88e6xxx_chip *chip = ds->priv;
2111 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2113 mutex_lock(&chip->reg_lock);
2115 /* Setup Switch Port Registers */
2116 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2117 err = mv88e6xxx_setup_port(chip, i);
2122 /* Setup Switch Global 1 Registers */
2123 err = mv88e6xxx_g1_setup(chip);
2127 /* Setup Switch Global 2 Registers */
2128 if (chip->info->global2_addr) {
2129 err = mv88e6xxx_g2_setup(chip);
2134 err = mv88e6xxx_irl_setup(chip);
2138 err = mv88e6xxx_phy_setup(chip);
2142 err = mv88e6xxx_vtu_setup(chip);
2146 err = mv88e6xxx_pvt_setup(chip);
2150 err = mv88e6xxx_atu_setup(chip);
2154 err = mv88e6xxx_pot_setup(chip);
2158 err = mv88e6xxx_rsvd2cpu_setup(chip);
2163 mutex_unlock(&chip->reg_lock);
2168 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2170 struct mv88e6xxx_chip *chip = ds->priv;
2173 if (!chip->info->ops->set_switch_mac)
2176 mutex_lock(&chip->reg_lock);
2177 err = chip->info->ops->set_switch_mac(chip, addr);
2178 mutex_unlock(&chip->reg_lock);
2183 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2185 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2186 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2190 if (!chip->info->ops->phy_read)
2193 mutex_lock(&chip->reg_lock);
2194 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2195 mutex_unlock(&chip->reg_lock);
2197 if (reg == MII_PHYSID2) {
2198 /* Some internal PHYS don't have a model number. Use
2199 * the mv88e6390 family model number instead.
2202 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2205 return err ? err : val;
2208 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2210 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2211 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2214 if (!chip->info->ops->phy_write)
2217 mutex_lock(&chip->reg_lock);
2218 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2219 mutex_unlock(&chip->reg_lock);
2224 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2225 struct device_node *np,
2229 struct mv88e6xxx_mdio_bus *mdio_bus;
2230 struct mii_bus *bus;
2233 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2237 mdio_bus = bus->priv;
2238 mdio_bus->bus = bus;
2239 mdio_bus->chip = chip;
2240 INIT_LIST_HEAD(&mdio_bus->list);
2241 mdio_bus->external = external;
2244 bus->name = np->full_name;
2245 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2247 bus->name = "mv88e6xxx SMI";
2248 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2251 bus->read = mv88e6xxx_mdio_read;
2252 bus->write = mv88e6xxx_mdio_write;
2253 bus->parent = chip->dev;
2256 err = of_mdiobus_register(bus, np);
2258 err = mdiobus_register(bus);
2260 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2265 list_add_tail(&mdio_bus->list, &chip->mdios);
2267 list_add(&mdio_bus->list, &chip->mdios);
2272 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2273 { .compatible = "marvell,mv88e6xxx-mdio-external",
2274 .data = (void *)true },
2278 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2279 struct device_node *np)
2281 const struct of_device_id *match;
2282 struct device_node *child;
2285 /* Always register one mdio bus for the internal/default mdio
2286 * bus. This maybe represented in the device tree, but is
2289 child = of_get_child_by_name(np, "mdio");
2290 err = mv88e6xxx_mdio_register(chip, child, false);
2294 /* Walk the device tree, and see if there are any other nodes
2295 * which say they are compatible with the external mdio
2298 for_each_available_child_of_node(np, child) {
2299 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2301 err = mv88e6xxx_mdio_register(chip, child, true);
2310 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2313 struct mv88e6xxx_mdio_bus *mdio_bus;
2314 struct mii_bus *bus;
2316 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2317 bus = mdio_bus->bus;
2319 mdiobus_unregister(bus);
2323 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2325 struct mv88e6xxx_chip *chip = ds->priv;
2327 return chip->eeprom_len;
2330 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2331 struct ethtool_eeprom *eeprom, u8 *data)
2333 struct mv88e6xxx_chip *chip = ds->priv;
2336 if (!chip->info->ops->get_eeprom)
2339 mutex_lock(&chip->reg_lock);
2340 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2341 mutex_unlock(&chip->reg_lock);
2346 eeprom->magic = 0xc3ec4951;
2351 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2352 struct ethtool_eeprom *eeprom, u8 *data)
2354 struct mv88e6xxx_chip *chip = ds->priv;
2357 if (!chip->info->ops->set_eeprom)
2360 if (eeprom->magic != 0xc3ec4951)
2363 mutex_lock(&chip->reg_lock);
2364 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2365 mutex_unlock(&chip->reg_lock);
2370 static const struct mv88e6xxx_ops mv88e6085_ops = {
2371 /* MV88E6XXX_FAMILY_6097 */
2372 .irl_init_all = mv88e6352_g2_irl_init_all,
2373 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2374 .phy_read = mv88e6185_phy_ppu_read,
2375 .phy_write = mv88e6185_phy_ppu_write,
2376 .port_set_link = mv88e6xxx_port_set_link,
2377 .port_set_duplex = mv88e6xxx_port_set_duplex,
2378 .port_set_speed = mv88e6185_port_set_speed,
2379 .port_tag_remap = mv88e6095_port_tag_remap,
2380 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2381 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2382 .port_set_ether_type = mv88e6351_port_set_ether_type,
2383 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2384 .port_pause_limit = mv88e6097_port_pause_limit,
2385 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2386 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2387 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2388 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2389 .stats_get_strings = mv88e6095_stats_get_strings,
2390 .stats_get_stats = mv88e6095_stats_get_stats,
2391 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2392 .set_egress_port = mv88e6095_g1_set_egress_port,
2393 .watchdog_ops = &mv88e6097_watchdog_ops,
2394 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2395 .pot_clear = mv88e6xxx_g2_pot_clear,
2396 .ppu_enable = mv88e6185_g1_ppu_enable,
2397 .ppu_disable = mv88e6185_g1_ppu_disable,
2398 .reset = mv88e6185_g1_reset,
2399 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2400 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2403 static const struct mv88e6xxx_ops mv88e6095_ops = {
2404 /* MV88E6XXX_FAMILY_6095 */
2405 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2406 .phy_read = mv88e6185_phy_ppu_read,
2407 .phy_write = mv88e6185_phy_ppu_write,
2408 .port_set_link = mv88e6xxx_port_set_link,
2409 .port_set_duplex = mv88e6xxx_port_set_duplex,
2410 .port_set_speed = mv88e6185_port_set_speed,
2411 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2412 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2413 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2414 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2415 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2416 .stats_get_strings = mv88e6095_stats_get_strings,
2417 .stats_get_stats = mv88e6095_stats_get_stats,
2418 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2419 .ppu_enable = mv88e6185_g1_ppu_enable,
2420 .ppu_disable = mv88e6185_g1_ppu_disable,
2421 .reset = mv88e6185_g1_reset,
2422 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2423 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2426 static const struct mv88e6xxx_ops mv88e6097_ops = {
2427 /* MV88E6XXX_FAMILY_6097 */
2428 .irl_init_all = mv88e6352_g2_irl_init_all,
2429 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2430 .phy_read = mv88e6xxx_g2_smi_phy_read,
2431 .phy_write = mv88e6xxx_g2_smi_phy_write,
2432 .port_set_link = mv88e6xxx_port_set_link,
2433 .port_set_duplex = mv88e6xxx_port_set_duplex,
2434 .port_set_speed = mv88e6185_port_set_speed,
2435 .port_tag_remap = mv88e6095_port_tag_remap,
2436 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2437 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2438 .port_set_ether_type = mv88e6351_port_set_ether_type,
2439 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2440 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2441 .port_pause_limit = mv88e6097_port_pause_limit,
2442 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2443 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2444 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2445 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2446 .stats_get_strings = mv88e6095_stats_get_strings,
2447 .stats_get_stats = mv88e6095_stats_get_stats,
2448 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2449 .set_egress_port = mv88e6095_g1_set_egress_port,
2450 .watchdog_ops = &mv88e6097_watchdog_ops,
2451 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2452 .pot_clear = mv88e6xxx_g2_pot_clear,
2453 .reset = mv88e6352_g1_reset,
2454 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2455 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2458 static const struct mv88e6xxx_ops mv88e6123_ops = {
2459 /* MV88E6XXX_FAMILY_6165 */
2460 .irl_init_all = mv88e6352_g2_irl_init_all,
2461 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2462 .phy_read = mv88e6xxx_g2_smi_phy_read,
2463 .phy_write = mv88e6xxx_g2_smi_phy_write,
2464 .port_set_link = mv88e6xxx_port_set_link,
2465 .port_set_duplex = mv88e6xxx_port_set_duplex,
2466 .port_set_speed = mv88e6185_port_set_speed,
2467 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2468 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2469 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2470 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2471 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2472 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2473 .stats_get_strings = mv88e6095_stats_get_strings,
2474 .stats_get_stats = mv88e6095_stats_get_stats,
2475 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2476 .set_egress_port = mv88e6095_g1_set_egress_port,
2477 .watchdog_ops = &mv88e6097_watchdog_ops,
2478 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2479 .pot_clear = mv88e6xxx_g2_pot_clear,
2480 .reset = mv88e6352_g1_reset,
2481 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2482 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2485 static const struct mv88e6xxx_ops mv88e6131_ops = {
2486 /* MV88E6XXX_FAMILY_6185 */
2487 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2488 .phy_read = mv88e6185_phy_ppu_read,
2489 .phy_write = mv88e6185_phy_ppu_write,
2490 .port_set_link = mv88e6xxx_port_set_link,
2491 .port_set_duplex = mv88e6xxx_port_set_duplex,
2492 .port_set_speed = mv88e6185_port_set_speed,
2493 .port_tag_remap = mv88e6095_port_tag_remap,
2494 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2495 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2496 .port_set_ether_type = mv88e6351_port_set_ether_type,
2497 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2498 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2499 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2500 .port_pause_limit = mv88e6097_port_pause_limit,
2501 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2502 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2503 .stats_get_strings = mv88e6095_stats_get_strings,
2504 .stats_get_stats = mv88e6095_stats_get_stats,
2505 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2506 .set_egress_port = mv88e6095_g1_set_egress_port,
2507 .watchdog_ops = &mv88e6097_watchdog_ops,
2508 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2509 .ppu_enable = mv88e6185_g1_ppu_enable,
2510 .ppu_disable = mv88e6185_g1_ppu_disable,
2511 .reset = mv88e6185_g1_reset,
2512 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2513 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2516 static const struct mv88e6xxx_ops mv88e6141_ops = {
2517 /* MV88E6XXX_FAMILY_6341 */
2518 .irl_init_all = mv88e6352_g2_irl_init_all,
2519 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2520 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2521 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2522 .phy_read = mv88e6xxx_g2_smi_phy_read,
2523 .phy_write = mv88e6xxx_g2_smi_phy_write,
2524 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2525 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2526 .port_set_link = mv88e6xxx_port_set_link,
2527 .port_set_duplex = mv88e6xxx_port_set_duplex,
2528 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2529 .port_set_speed = mv88e6390_port_set_speed,
2530 .port_tag_remap = mv88e6095_port_tag_remap,
2531 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2532 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2533 .port_set_ether_type = mv88e6351_port_set_ether_type,
2534 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2535 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2536 .port_pause_limit = mv88e6097_port_pause_limit,
2537 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2538 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2539 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2540 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2541 .stats_get_strings = mv88e6320_stats_get_strings,
2542 .stats_get_stats = mv88e6390_stats_get_stats,
2543 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2544 .set_egress_port = mv88e6390_g1_set_egress_port,
2545 .watchdog_ops = &mv88e6390_watchdog_ops,
2546 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2547 .pot_clear = mv88e6xxx_g2_pot_clear,
2548 .reset = mv88e6352_g1_reset,
2549 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2550 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2553 static const struct mv88e6xxx_ops mv88e6161_ops = {
2554 /* MV88E6XXX_FAMILY_6165 */
2555 .irl_init_all = mv88e6352_g2_irl_init_all,
2556 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2557 .phy_read = mv88e6xxx_g2_smi_phy_read,
2558 .phy_write = mv88e6xxx_g2_smi_phy_write,
2559 .port_set_link = mv88e6xxx_port_set_link,
2560 .port_set_duplex = mv88e6xxx_port_set_duplex,
2561 .port_set_speed = mv88e6185_port_set_speed,
2562 .port_tag_remap = mv88e6095_port_tag_remap,
2563 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2564 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2565 .port_set_ether_type = mv88e6351_port_set_ether_type,
2566 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2567 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2568 .port_pause_limit = mv88e6097_port_pause_limit,
2569 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2570 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2571 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2572 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2573 .stats_get_strings = mv88e6095_stats_get_strings,
2574 .stats_get_stats = mv88e6095_stats_get_stats,
2575 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2576 .set_egress_port = mv88e6095_g1_set_egress_port,
2577 .watchdog_ops = &mv88e6097_watchdog_ops,
2578 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2579 .pot_clear = mv88e6xxx_g2_pot_clear,
2580 .reset = mv88e6352_g1_reset,
2581 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2582 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2585 static const struct mv88e6xxx_ops mv88e6165_ops = {
2586 /* MV88E6XXX_FAMILY_6165 */
2587 .irl_init_all = mv88e6352_g2_irl_init_all,
2588 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2589 .phy_read = mv88e6165_phy_read,
2590 .phy_write = mv88e6165_phy_write,
2591 .port_set_link = mv88e6xxx_port_set_link,
2592 .port_set_duplex = mv88e6xxx_port_set_duplex,
2593 .port_set_speed = mv88e6185_port_set_speed,
2594 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2595 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2596 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2597 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2598 .stats_get_strings = mv88e6095_stats_get_strings,
2599 .stats_get_stats = mv88e6095_stats_get_stats,
2600 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2601 .set_egress_port = mv88e6095_g1_set_egress_port,
2602 .watchdog_ops = &mv88e6097_watchdog_ops,
2603 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2604 .pot_clear = mv88e6xxx_g2_pot_clear,
2605 .reset = mv88e6352_g1_reset,
2606 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2607 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2610 static const struct mv88e6xxx_ops mv88e6171_ops = {
2611 /* MV88E6XXX_FAMILY_6351 */
2612 .irl_init_all = mv88e6352_g2_irl_init_all,
2613 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2614 .phy_read = mv88e6xxx_g2_smi_phy_read,
2615 .phy_write = mv88e6xxx_g2_smi_phy_write,
2616 .port_set_link = mv88e6xxx_port_set_link,
2617 .port_set_duplex = mv88e6xxx_port_set_duplex,
2618 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2619 .port_set_speed = mv88e6185_port_set_speed,
2620 .port_tag_remap = mv88e6095_port_tag_remap,
2621 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2622 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2623 .port_set_ether_type = mv88e6351_port_set_ether_type,
2624 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2625 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2626 .port_pause_limit = mv88e6097_port_pause_limit,
2627 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2628 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2629 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2630 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2631 .stats_get_strings = mv88e6095_stats_get_strings,
2632 .stats_get_stats = mv88e6095_stats_get_stats,
2633 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2634 .set_egress_port = mv88e6095_g1_set_egress_port,
2635 .watchdog_ops = &mv88e6097_watchdog_ops,
2636 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2637 .pot_clear = mv88e6xxx_g2_pot_clear,
2638 .reset = mv88e6352_g1_reset,
2639 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2640 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2643 static const struct mv88e6xxx_ops mv88e6172_ops = {
2644 /* MV88E6XXX_FAMILY_6352 */
2645 .irl_init_all = mv88e6352_g2_irl_init_all,
2646 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2647 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2648 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2649 .phy_read = mv88e6xxx_g2_smi_phy_read,
2650 .phy_write = mv88e6xxx_g2_smi_phy_write,
2651 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2652 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2653 .port_set_link = mv88e6xxx_port_set_link,
2654 .port_set_duplex = mv88e6xxx_port_set_duplex,
2655 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2656 .port_set_speed = mv88e6352_port_set_speed,
2657 .port_tag_remap = mv88e6095_port_tag_remap,
2658 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2659 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2660 .port_set_ether_type = mv88e6351_port_set_ether_type,
2661 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2662 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2663 .port_pause_limit = mv88e6097_port_pause_limit,
2664 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2665 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2666 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2667 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2668 .stats_get_strings = mv88e6095_stats_get_strings,
2669 .stats_get_stats = mv88e6095_stats_get_stats,
2670 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2671 .set_egress_port = mv88e6095_g1_set_egress_port,
2672 .watchdog_ops = &mv88e6097_watchdog_ops,
2673 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2674 .pot_clear = mv88e6xxx_g2_pot_clear,
2675 .reset = mv88e6352_g1_reset,
2676 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2677 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2678 .serdes_power = mv88e6352_serdes_power,
2681 static const struct mv88e6xxx_ops mv88e6175_ops = {
2682 /* MV88E6XXX_FAMILY_6351 */
2683 .irl_init_all = mv88e6352_g2_irl_init_all,
2684 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2685 .phy_read = mv88e6xxx_g2_smi_phy_read,
2686 .phy_write = mv88e6xxx_g2_smi_phy_write,
2687 .port_set_link = mv88e6xxx_port_set_link,
2688 .port_set_duplex = mv88e6xxx_port_set_duplex,
2689 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2690 .port_set_speed = mv88e6185_port_set_speed,
2691 .port_tag_remap = mv88e6095_port_tag_remap,
2692 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2693 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2694 .port_set_ether_type = mv88e6351_port_set_ether_type,
2695 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2696 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2697 .port_pause_limit = mv88e6097_port_pause_limit,
2698 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2699 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2700 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2701 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2702 .stats_get_strings = mv88e6095_stats_get_strings,
2703 .stats_get_stats = mv88e6095_stats_get_stats,
2704 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2705 .set_egress_port = mv88e6095_g1_set_egress_port,
2706 .watchdog_ops = &mv88e6097_watchdog_ops,
2707 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2708 .pot_clear = mv88e6xxx_g2_pot_clear,
2709 .reset = mv88e6352_g1_reset,
2710 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2711 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2714 static const struct mv88e6xxx_ops mv88e6176_ops = {
2715 /* MV88E6XXX_FAMILY_6352 */
2716 .irl_init_all = mv88e6352_g2_irl_init_all,
2717 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2718 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2719 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2720 .phy_read = mv88e6xxx_g2_smi_phy_read,
2721 .phy_write = mv88e6xxx_g2_smi_phy_write,
2722 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2723 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2724 .port_set_link = mv88e6xxx_port_set_link,
2725 .port_set_duplex = mv88e6xxx_port_set_duplex,
2726 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2727 .port_set_speed = mv88e6352_port_set_speed,
2728 .port_tag_remap = mv88e6095_port_tag_remap,
2729 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2730 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2731 .port_set_ether_type = mv88e6351_port_set_ether_type,
2732 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2733 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2734 .port_pause_limit = mv88e6097_port_pause_limit,
2735 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2736 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2737 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2738 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2739 .stats_get_strings = mv88e6095_stats_get_strings,
2740 .stats_get_stats = mv88e6095_stats_get_stats,
2741 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2742 .set_egress_port = mv88e6095_g1_set_egress_port,
2743 .watchdog_ops = &mv88e6097_watchdog_ops,
2744 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2745 .pot_clear = mv88e6xxx_g2_pot_clear,
2746 .reset = mv88e6352_g1_reset,
2747 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2748 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2749 .serdes_power = mv88e6352_serdes_power,
2752 static const struct mv88e6xxx_ops mv88e6185_ops = {
2753 /* MV88E6XXX_FAMILY_6185 */
2754 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2755 .phy_read = mv88e6185_phy_ppu_read,
2756 .phy_write = mv88e6185_phy_ppu_write,
2757 .port_set_link = mv88e6xxx_port_set_link,
2758 .port_set_duplex = mv88e6xxx_port_set_duplex,
2759 .port_set_speed = mv88e6185_port_set_speed,
2760 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2761 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2762 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2763 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2764 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2765 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2766 .stats_get_strings = mv88e6095_stats_get_strings,
2767 .stats_get_stats = mv88e6095_stats_get_stats,
2768 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2769 .set_egress_port = mv88e6095_g1_set_egress_port,
2770 .watchdog_ops = &mv88e6097_watchdog_ops,
2771 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2772 .ppu_enable = mv88e6185_g1_ppu_enable,
2773 .ppu_disable = mv88e6185_g1_ppu_disable,
2774 .reset = mv88e6185_g1_reset,
2775 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2776 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2779 static const struct mv88e6xxx_ops mv88e6190_ops = {
2780 /* MV88E6XXX_FAMILY_6390 */
2781 .irl_init_all = mv88e6390_g2_irl_init_all,
2782 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2783 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2784 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2785 .phy_read = mv88e6xxx_g2_smi_phy_read,
2786 .phy_write = mv88e6xxx_g2_smi_phy_write,
2787 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2788 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
2789 .port_set_link = mv88e6xxx_port_set_link,
2790 .port_set_duplex = mv88e6xxx_port_set_duplex,
2791 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2792 .port_set_speed = mv88e6390_port_set_speed,
2793 .port_tag_remap = mv88e6390_port_tag_remap,
2794 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2795 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2796 .port_set_ether_type = mv88e6351_port_set_ether_type,
2797 .port_pause_limit = mv88e6390_port_pause_limit,
2798 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2799 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2800 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2801 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2802 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2803 .stats_get_strings = mv88e6320_stats_get_strings,
2804 .stats_get_stats = mv88e6390_stats_get_stats,
2805 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2806 .set_egress_port = mv88e6390_g1_set_egress_port,
2807 .watchdog_ops = &mv88e6390_watchdog_ops,
2808 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2809 .pot_clear = mv88e6xxx_g2_pot_clear,
2810 .reset = mv88e6352_g1_reset,
2811 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2812 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2813 .serdes_power = mv88e6390_serdes_power,
2816 static const struct mv88e6xxx_ops mv88e6190x_ops = {
2817 /* MV88E6XXX_FAMILY_6390 */
2818 .irl_init_all = mv88e6390_g2_irl_init_all,
2819 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2820 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2821 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2822 .phy_read = mv88e6xxx_g2_smi_phy_read,
2823 .phy_write = mv88e6xxx_g2_smi_phy_write,
2824 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2825 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
2826 .port_set_link = mv88e6xxx_port_set_link,
2827 .port_set_duplex = mv88e6xxx_port_set_duplex,
2828 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2829 .port_set_speed = mv88e6390x_port_set_speed,
2830 .port_tag_remap = mv88e6390_port_tag_remap,
2831 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2832 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2833 .port_set_ether_type = mv88e6351_port_set_ether_type,
2834 .port_pause_limit = mv88e6390_port_pause_limit,
2835 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2836 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2837 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2838 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2839 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2840 .stats_get_strings = mv88e6320_stats_get_strings,
2841 .stats_get_stats = mv88e6390_stats_get_stats,
2842 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2843 .set_egress_port = mv88e6390_g1_set_egress_port,
2844 .watchdog_ops = &mv88e6390_watchdog_ops,
2845 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2846 .pot_clear = mv88e6xxx_g2_pot_clear,
2847 .reset = mv88e6352_g1_reset,
2848 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2849 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2850 .serdes_power = mv88e6390_serdes_power,
2853 static const struct mv88e6xxx_ops mv88e6191_ops = {
2854 /* MV88E6XXX_FAMILY_6390 */
2855 .irl_init_all = mv88e6390_g2_irl_init_all,
2856 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2857 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2858 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2859 .phy_read = mv88e6xxx_g2_smi_phy_read,
2860 .phy_write = mv88e6xxx_g2_smi_phy_write,
2861 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2862 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
2863 .port_set_link = mv88e6xxx_port_set_link,
2864 .port_set_duplex = mv88e6xxx_port_set_duplex,
2865 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2866 .port_set_speed = mv88e6390_port_set_speed,
2867 .port_tag_remap = mv88e6390_port_tag_remap,
2868 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2869 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2870 .port_set_ether_type = mv88e6351_port_set_ether_type,
2871 .port_pause_limit = mv88e6390_port_pause_limit,
2872 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2873 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2874 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2875 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2876 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2877 .stats_get_strings = mv88e6320_stats_get_strings,
2878 .stats_get_stats = mv88e6390_stats_get_stats,
2879 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2880 .set_egress_port = mv88e6390_g1_set_egress_port,
2881 .watchdog_ops = &mv88e6390_watchdog_ops,
2882 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2883 .pot_clear = mv88e6xxx_g2_pot_clear,
2884 .reset = mv88e6352_g1_reset,
2885 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2886 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2887 .serdes_power = mv88e6390_serdes_power,
2890 static const struct mv88e6xxx_ops mv88e6240_ops = {
2891 /* MV88E6XXX_FAMILY_6352 */
2892 .irl_init_all = mv88e6352_g2_irl_init_all,
2893 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2894 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2895 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2896 .phy_read = mv88e6xxx_g2_smi_phy_read,
2897 .phy_write = mv88e6xxx_g2_smi_phy_write,
2898 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2899 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2900 .port_set_link = mv88e6xxx_port_set_link,
2901 .port_set_duplex = mv88e6xxx_port_set_duplex,
2902 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2903 .port_set_speed = mv88e6352_port_set_speed,
2904 .port_tag_remap = mv88e6095_port_tag_remap,
2905 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2906 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2907 .port_set_ether_type = mv88e6351_port_set_ether_type,
2908 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2909 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2910 .port_pause_limit = mv88e6097_port_pause_limit,
2911 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2912 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2913 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2914 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2915 .stats_get_strings = mv88e6095_stats_get_strings,
2916 .stats_get_stats = mv88e6095_stats_get_stats,
2917 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2918 .set_egress_port = mv88e6095_g1_set_egress_port,
2919 .watchdog_ops = &mv88e6097_watchdog_ops,
2920 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2921 .pot_clear = mv88e6xxx_g2_pot_clear,
2922 .reset = mv88e6352_g1_reset,
2923 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2924 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2925 .serdes_power = mv88e6352_serdes_power,
2928 static const struct mv88e6xxx_ops mv88e6290_ops = {
2929 /* MV88E6XXX_FAMILY_6390 */
2930 .irl_init_all = mv88e6390_g2_irl_init_all,
2931 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2932 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2933 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2934 .phy_read = mv88e6xxx_g2_smi_phy_read,
2935 .phy_write = mv88e6xxx_g2_smi_phy_write,
2936 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2937 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
2938 .port_set_link = mv88e6xxx_port_set_link,
2939 .port_set_duplex = mv88e6xxx_port_set_duplex,
2940 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2941 .port_set_speed = mv88e6390_port_set_speed,
2942 .port_tag_remap = mv88e6390_port_tag_remap,
2943 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2944 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2945 .port_set_ether_type = mv88e6351_port_set_ether_type,
2946 .port_pause_limit = mv88e6390_port_pause_limit,
2947 .port_set_cmode = mv88e6390x_port_set_cmode,
2948 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2949 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2950 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2951 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2952 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2953 .stats_get_strings = mv88e6320_stats_get_strings,
2954 .stats_get_stats = mv88e6390_stats_get_stats,
2955 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2956 .set_egress_port = mv88e6390_g1_set_egress_port,
2957 .watchdog_ops = &mv88e6390_watchdog_ops,
2958 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2959 .pot_clear = mv88e6xxx_g2_pot_clear,
2960 .reset = mv88e6352_g1_reset,
2961 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2962 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2963 .serdes_power = mv88e6390_serdes_power,
2966 static const struct mv88e6xxx_ops mv88e6320_ops = {
2967 /* MV88E6XXX_FAMILY_6320 */
2968 .irl_init_all = mv88e6352_g2_irl_init_all,
2969 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2970 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2971 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2972 .phy_read = mv88e6xxx_g2_smi_phy_read,
2973 .phy_write = mv88e6xxx_g2_smi_phy_write,
2974 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2975 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2976 .port_set_link = mv88e6xxx_port_set_link,
2977 .port_set_duplex = mv88e6xxx_port_set_duplex,
2978 .port_set_speed = mv88e6185_port_set_speed,
2979 .port_tag_remap = mv88e6095_port_tag_remap,
2980 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2981 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2982 .port_set_ether_type = mv88e6351_port_set_ether_type,
2983 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2984 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2985 .port_pause_limit = mv88e6097_port_pause_limit,
2986 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2987 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2988 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2989 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2990 .stats_get_strings = mv88e6320_stats_get_strings,
2991 .stats_get_stats = mv88e6320_stats_get_stats,
2992 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2993 .set_egress_port = mv88e6095_g1_set_egress_port,
2994 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2995 .pot_clear = mv88e6xxx_g2_pot_clear,
2996 .reset = mv88e6352_g1_reset,
2997 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2998 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3001 static const struct mv88e6xxx_ops mv88e6321_ops = {
3002 /* MV88E6XXX_FAMILY_6320 */
3003 .irl_init_all = mv88e6352_g2_irl_init_all,
3004 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3005 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3006 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3007 .phy_read = mv88e6xxx_g2_smi_phy_read,
3008 .phy_write = mv88e6xxx_g2_smi_phy_write,
3009 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
3010 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
3011 .port_set_link = mv88e6xxx_port_set_link,
3012 .port_set_duplex = mv88e6xxx_port_set_duplex,
3013 .port_set_speed = mv88e6185_port_set_speed,
3014 .port_tag_remap = mv88e6095_port_tag_remap,
3015 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3016 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3017 .port_set_ether_type = mv88e6351_port_set_ether_type,
3018 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3019 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3020 .port_pause_limit = mv88e6097_port_pause_limit,
3021 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3022 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3023 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3024 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3025 .stats_get_strings = mv88e6320_stats_get_strings,
3026 .stats_get_stats = mv88e6320_stats_get_stats,
3027 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3028 .set_egress_port = mv88e6095_g1_set_egress_port,
3029 .reset = mv88e6352_g1_reset,
3030 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3031 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3034 static const struct mv88e6xxx_ops mv88e6341_ops = {
3035 /* MV88E6XXX_FAMILY_6341 */
3036 .irl_init_all = mv88e6352_g2_irl_init_all,
3037 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3038 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3039 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3040 .phy_read = mv88e6xxx_g2_smi_phy_read,
3041 .phy_write = mv88e6xxx_g2_smi_phy_write,
3042 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
3043 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
3044 .port_set_link = mv88e6xxx_port_set_link,
3045 .port_set_duplex = mv88e6xxx_port_set_duplex,
3046 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3047 .port_set_speed = mv88e6390_port_set_speed,
3048 .port_tag_remap = mv88e6095_port_tag_remap,
3049 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3050 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3051 .port_set_ether_type = mv88e6351_port_set_ether_type,
3052 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3053 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3054 .port_pause_limit = mv88e6097_port_pause_limit,
3055 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3056 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3057 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3058 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3059 .stats_get_strings = mv88e6320_stats_get_strings,
3060 .stats_get_stats = mv88e6390_stats_get_stats,
3061 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3062 .set_egress_port = mv88e6390_g1_set_egress_port,
3063 .watchdog_ops = &mv88e6390_watchdog_ops,
3064 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3065 .pot_clear = mv88e6xxx_g2_pot_clear,
3066 .reset = mv88e6352_g1_reset,
3067 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3068 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3071 static const struct mv88e6xxx_ops mv88e6350_ops = {
3072 /* MV88E6XXX_FAMILY_6351 */
3073 .irl_init_all = mv88e6352_g2_irl_init_all,
3074 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3075 .phy_read = mv88e6xxx_g2_smi_phy_read,
3076 .phy_write = mv88e6xxx_g2_smi_phy_write,
3077 .port_set_link = mv88e6xxx_port_set_link,
3078 .port_set_duplex = mv88e6xxx_port_set_duplex,
3079 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3080 .port_set_speed = mv88e6185_port_set_speed,
3081 .port_tag_remap = mv88e6095_port_tag_remap,
3082 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3083 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3084 .port_set_ether_type = mv88e6351_port_set_ether_type,
3085 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3086 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3087 .port_pause_limit = mv88e6097_port_pause_limit,
3088 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3089 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3090 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3091 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3092 .stats_get_strings = mv88e6095_stats_get_strings,
3093 .stats_get_stats = mv88e6095_stats_get_stats,
3094 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3095 .set_egress_port = mv88e6095_g1_set_egress_port,
3096 .watchdog_ops = &mv88e6097_watchdog_ops,
3097 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3098 .pot_clear = mv88e6xxx_g2_pot_clear,
3099 .reset = mv88e6352_g1_reset,
3100 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3101 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3104 static const struct mv88e6xxx_ops mv88e6351_ops = {
3105 /* MV88E6XXX_FAMILY_6351 */
3106 .irl_init_all = mv88e6352_g2_irl_init_all,
3107 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3108 .phy_read = mv88e6xxx_g2_smi_phy_read,
3109 .phy_write = mv88e6xxx_g2_smi_phy_write,
3110 .port_set_link = mv88e6xxx_port_set_link,
3111 .port_set_duplex = mv88e6xxx_port_set_duplex,
3112 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3113 .port_set_speed = mv88e6185_port_set_speed,
3114 .port_tag_remap = mv88e6095_port_tag_remap,
3115 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3116 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3117 .port_set_ether_type = mv88e6351_port_set_ether_type,
3118 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3119 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3120 .port_pause_limit = mv88e6097_port_pause_limit,
3121 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3122 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3123 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3124 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3125 .stats_get_strings = mv88e6095_stats_get_strings,
3126 .stats_get_stats = mv88e6095_stats_get_stats,
3127 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3128 .set_egress_port = mv88e6095_g1_set_egress_port,
3129 .watchdog_ops = &mv88e6097_watchdog_ops,
3130 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3131 .pot_clear = mv88e6xxx_g2_pot_clear,
3132 .reset = mv88e6352_g1_reset,
3133 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3134 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3137 static const struct mv88e6xxx_ops mv88e6352_ops = {
3138 /* MV88E6XXX_FAMILY_6352 */
3139 .irl_init_all = mv88e6352_g2_irl_init_all,
3140 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3141 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3142 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3143 .phy_read = mv88e6xxx_g2_smi_phy_read,
3144 .phy_write = mv88e6xxx_g2_smi_phy_write,
3145 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
3146 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
3147 .port_set_link = mv88e6xxx_port_set_link,
3148 .port_set_duplex = mv88e6xxx_port_set_duplex,
3149 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3150 .port_set_speed = mv88e6352_port_set_speed,
3151 .port_tag_remap = mv88e6095_port_tag_remap,
3152 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3153 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3154 .port_set_ether_type = mv88e6351_port_set_ether_type,
3155 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3156 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3157 .port_pause_limit = mv88e6097_port_pause_limit,
3158 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3159 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3160 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3161 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3162 .stats_get_strings = mv88e6095_stats_get_strings,
3163 .stats_get_stats = mv88e6095_stats_get_stats,
3164 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3165 .set_egress_port = mv88e6095_g1_set_egress_port,
3166 .watchdog_ops = &mv88e6097_watchdog_ops,
3167 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3168 .pot_clear = mv88e6xxx_g2_pot_clear,
3169 .reset = mv88e6352_g1_reset,
3170 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3171 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3172 .serdes_power = mv88e6352_serdes_power,
3175 static const struct mv88e6xxx_ops mv88e6390_ops = {
3176 /* MV88E6XXX_FAMILY_6390 */
3177 .irl_init_all = mv88e6390_g2_irl_init_all,
3178 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3179 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3180 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3181 .phy_read = mv88e6xxx_g2_smi_phy_read,
3182 .phy_write = mv88e6xxx_g2_smi_phy_write,
3183 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
3184 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
3185 .port_set_link = mv88e6xxx_port_set_link,
3186 .port_set_duplex = mv88e6xxx_port_set_duplex,
3187 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3188 .port_set_speed = mv88e6390_port_set_speed,
3189 .port_tag_remap = mv88e6390_port_tag_remap,
3190 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3191 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3192 .port_set_ether_type = mv88e6351_port_set_ether_type,
3193 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3194 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3195 .port_pause_limit = mv88e6390_port_pause_limit,
3196 .port_set_cmode = mv88e6390x_port_set_cmode,
3197 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3198 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3199 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3200 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3201 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3202 .stats_get_strings = mv88e6320_stats_get_strings,
3203 .stats_get_stats = mv88e6390_stats_get_stats,
3204 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3205 .set_egress_port = mv88e6390_g1_set_egress_port,
3206 .watchdog_ops = &mv88e6390_watchdog_ops,
3207 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3208 .pot_clear = mv88e6xxx_g2_pot_clear,
3209 .reset = mv88e6352_g1_reset,
3210 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3211 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3212 .serdes_power = mv88e6390_serdes_power,
3215 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3216 /* MV88E6XXX_FAMILY_6390 */
3217 .irl_init_all = mv88e6390_g2_irl_init_all,
3218 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3219 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3220 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3221 .phy_read = mv88e6xxx_g2_smi_phy_read,
3222 .phy_write = mv88e6xxx_g2_smi_phy_write,
3223 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
3224 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
3225 .port_set_link = mv88e6xxx_port_set_link,
3226 .port_set_duplex = mv88e6xxx_port_set_duplex,
3227 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3228 .port_set_speed = mv88e6390x_port_set_speed,
3229 .port_tag_remap = mv88e6390_port_tag_remap,
3230 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3231 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3232 .port_set_ether_type = mv88e6351_port_set_ether_type,
3233 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3234 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3235 .port_pause_limit = mv88e6390_port_pause_limit,
3236 .port_set_cmode = mv88e6390x_port_set_cmode,
3237 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3238 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3239 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3240 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3241 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3242 .stats_get_strings = mv88e6320_stats_get_strings,
3243 .stats_get_stats = mv88e6390_stats_get_stats,
3244 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3245 .set_egress_port = mv88e6390_g1_set_egress_port,
3246 .watchdog_ops = &mv88e6390_watchdog_ops,
3247 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3248 .pot_clear = mv88e6xxx_g2_pot_clear,
3249 .reset = mv88e6352_g1_reset,
3250 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3251 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3252 .serdes_power = mv88e6390_serdes_power,
3255 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3257 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3258 .family = MV88E6XXX_FAMILY_6097,
3259 .name = "Marvell 88E6085",
3260 .num_databases = 4096,
3263 .port_base_addr = 0x10,
3264 .global1_addr = 0x1b,
3265 .global2_addr = 0x1c,
3266 .age_time_coeff = 15000,
3269 .atu_move_port_mask = 0xf,
3272 .tag_protocol = DSA_TAG_PROTO_DSA,
3273 .ops = &mv88e6085_ops,
3277 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3278 .family = MV88E6XXX_FAMILY_6095,
3279 .name = "Marvell 88E6095/88E6095F",
3280 .num_databases = 256,
3283 .port_base_addr = 0x10,
3284 .global1_addr = 0x1b,
3285 .global2_addr = 0x1c,
3286 .age_time_coeff = 15000,
3288 .atu_move_port_mask = 0xf,
3290 .tag_protocol = DSA_TAG_PROTO_DSA,
3291 .ops = &mv88e6095_ops,
3295 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3296 .family = MV88E6XXX_FAMILY_6097,
3297 .name = "Marvell 88E6097/88E6097F",
3298 .num_databases = 4096,
3301 .port_base_addr = 0x10,
3302 .global1_addr = 0x1b,
3303 .global2_addr = 0x1c,
3304 .age_time_coeff = 15000,
3307 .atu_move_port_mask = 0xf,
3310 .tag_protocol = DSA_TAG_PROTO_EDSA,
3311 .ops = &mv88e6097_ops,
3315 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3316 .family = MV88E6XXX_FAMILY_6165,
3317 .name = "Marvell 88E6123",
3318 .num_databases = 4096,
3321 .port_base_addr = 0x10,
3322 .global1_addr = 0x1b,
3323 .global2_addr = 0x1c,
3324 .age_time_coeff = 15000,
3327 .atu_move_port_mask = 0xf,
3330 .tag_protocol = DSA_TAG_PROTO_EDSA,
3331 .ops = &mv88e6123_ops,
3335 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3336 .family = MV88E6XXX_FAMILY_6185,
3337 .name = "Marvell 88E6131",
3338 .num_databases = 256,
3341 .port_base_addr = 0x10,
3342 .global1_addr = 0x1b,
3343 .global2_addr = 0x1c,
3344 .age_time_coeff = 15000,
3346 .atu_move_port_mask = 0xf,
3348 .tag_protocol = DSA_TAG_PROTO_DSA,
3349 .ops = &mv88e6131_ops,
3353 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3354 .family = MV88E6XXX_FAMILY_6341,
3355 .name = "Marvell 88E6341",
3356 .num_databases = 4096,
3359 .port_base_addr = 0x10,
3360 .global1_addr = 0x1b,
3361 .global2_addr = 0x1c,
3362 .age_time_coeff = 3750,
3363 .atu_move_port_mask = 0x1f,
3367 .tag_protocol = DSA_TAG_PROTO_EDSA,
3368 .ops = &mv88e6141_ops,
3372 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3373 .family = MV88E6XXX_FAMILY_6165,
3374 .name = "Marvell 88E6161",
3375 .num_databases = 4096,
3378 .port_base_addr = 0x10,
3379 .global1_addr = 0x1b,
3380 .global2_addr = 0x1c,
3381 .age_time_coeff = 15000,
3384 .atu_move_port_mask = 0xf,
3387 .tag_protocol = DSA_TAG_PROTO_EDSA,
3388 .ops = &mv88e6161_ops,
3392 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3393 .family = MV88E6XXX_FAMILY_6165,
3394 .name = "Marvell 88E6165",
3395 .num_databases = 4096,
3398 .port_base_addr = 0x10,
3399 .global1_addr = 0x1b,
3400 .global2_addr = 0x1c,
3401 .age_time_coeff = 15000,
3404 .atu_move_port_mask = 0xf,
3407 .tag_protocol = DSA_TAG_PROTO_DSA,
3408 .ops = &mv88e6165_ops,
3412 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3413 .family = MV88E6XXX_FAMILY_6351,
3414 .name = "Marvell 88E6171",
3415 .num_databases = 4096,
3418 .port_base_addr = 0x10,
3419 .global1_addr = 0x1b,
3420 .global2_addr = 0x1c,
3421 .age_time_coeff = 15000,
3424 .atu_move_port_mask = 0xf,
3427 .tag_protocol = DSA_TAG_PROTO_EDSA,
3428 .ops = &mv88e6171_ops,
3432 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3433 .family = MV88E6XXX_FAMILY_6352,
3434 .name = "Marvell 88E6172",
3435 .num_databases = 4096,
3438 .port_base_addr = 0x10,
3439 .global1_addr = 0x1b,
3440 .global2_addr = 0x1c,
3441 .age_time_coeff = 15000,
3444 .atu_move_port_mask = 0xf,
3447 .tag_protocol = DSA_TAG_PROTO_EDSA,
3448 .ops = &mv88e6172_ops,
3452 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3453 .family = MV88E6XXX_FAMILY_6351,
3454 .name = "Marvell 88E6175",
3455 .num_databases = 4096,
3458 .port_base_addr = 0x10,
3459 .global1_addr = 0x1b,
3460 .global2_addr = 0x1c,
3461 .age_time_coeff = 15000,
3464 .atu_move_port_mask = 0xf,
3467 .tag_protocol = DSA_TAG_PROTO_EDSA,
3468 .ops = &mv88e6175_ops,
3472 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3473 .family = MV88E6XXX_FAMILY_6352,
3474 .name = "Marvell 88E6176",
3475 .num_databases = 4096,
3478 .port_base_addr = 0x10,
3479 .global1_addr = 0x1b,
3480 .global2_addr = 0x1c,
3481 .age_time_coeff = 15000,
3484 .atu_move_port_mask = 0xf,
3487 .tag_protocol = DSA_TAG_PROTO_EDSA,
3488 .ops = &mv88e6176_ops,
3492 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3493 .family = MV88E6XXX_FAMILY_6185,
3494 .name = "Marvell 88E6185",
3495 .num_databases = 256,
3498 .port_base_addr = 0x10,
3499 .global1_addr = 0x1b,
3500 .global2_addr = 0x1c,
3501 .age_time_coeff = 15000,
3503 .atu_move_port_mask = 0xf,
3505 .tag_protocol = DSA_TAG_PROTO_EDSA,
3506 .ops = &mv88e6185_ops,
3510 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3511 .family = MV88E6XXX_FAMILY_6390,
3512 .name = "Marvell 88E6190",
3513 .num_databases = 4096,
3514 .num_ports = 11, /* 10 + Z80 */
3516 .port_base_addr = 0x0,
3517 .global1_addr = 0x1b,
3518 .global2_addr = 0x1c,
3519 .tag_protocol = DSA_TAG_PROTO_DSA,
3520 .age_time_coeff = 3750,
3525 .atu_move_port_mask = 0x1f,
3526 .ops = &mv88e6190_ops,
3530 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3531 .family = MV88E6XXX_FAMILY_6390,
3532 .name = "Marvell 88E6190X",
3533 .num_databases = 4096,
3534 .num_ports = 11, /* 10 + Z80 */
3536 .port_base_addr = 0x0,
3537 .global1_addr = 0x1b,
3538 .global2_addr = 0x1c,
3539 .age_time_coeff = 3750,
3542 .atu_move_port_mask = 0x1f,
3545 .tag_protocol = DSA_TAG_PROTO_DSA,
3546 .ops = &mv88e6190x_ops,
3550 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3551 .family = MV88E6XXX_FAMILY_6390,
3552 .name = "Marvell 88E6191",
3553 .num_databases = 4096,
3554 .num_ports = 11, /* 10 + Z80 */
3556 .port_base_addr = 0x0,
3557 .global1_addr = 0x1b,
3558 .global2_addr = 0x1c,
3559 .age_time_coeff = 3750,
3562 .atu_move_port_mask = 0x1f,
3565 .tag_protocol = DSA_TAG_PROTO_DSA,
3566 .ops = &mv88e6191_ops,
3570 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3571 .family = MV88E6XXX_FAMILY_6352,
3572 .name = "Marvell 88E6240",
3573 .num_databases = 4096,
3576 .port_base_addr = 0x10,
3577 .global1_addr = 0x1b,
3578 .global2_addr = 0x1c,
3579 .age_time_coeff = 15000,
3582 .atu_move_port_mask = 0xf,
3585 .tag_protocol = DSA_TAG_PROTO_EDSA,
3586 .ops = &mv88e6240_ops,
3590 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3591 .family = MV88E6XXX_FAMILY_6390,
3592 .name = "Marvell 88E6290",
3593 .num_databases = 4096,
3594 .num_ports = 11, /* 10 + Z80 */
3596 .port_base_addr = 0x0,
3597 .global1_addr = 0x1b,
3598 .global2_addr = 0x1c,
3599 .age_time_coeff = 3750,
3602 .atu_move_port_mask = 0x1f,
3605 .tag_protocol = DSA_TAG_PROTO_DSA,
3606 .ops = &mv88e6290_ops,
3610 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3611 .family = MV88E6XXX_FAMILY_6320,
3612 .name = "Marvell 88E6320",
3613 .num_databases = 4096,
3616 .port_base_addr = 0x10,
3617 .global1_addr = 0x1b,
3618 .global2_addr = 0x1c,
3619 .age_time_coeff = 15000,
3621 .atu_move_port_mask = 0xf,
3624 .tag_protocol = DSA_TAG_PROTO_EDSA,
3625 .ops = &mv88e6320_ops,
3629 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3630 .family = MV88E6XXX_FAMILY_6320,
3631 .name = "Marvell 88E6321",
3632 .num_databases = 4096,
3635 .port_base_addr = 0x10,
3636 .global1_addr = 0x1b,
3637 .global2_addr = 0x1c,
3638 .age_time_coeff = 15000,
3640 .atu_move_port_mask = 0xf,
3642 .tag_protocol = DSA_TAG_PROTO_EDSA,
3643 .ops = &mv88e6321_ops,
3647 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3648 .family = MV88E6XXX_FAMILY_6341,
3649 .name = "Marvell 88E6341",
3650 .num_databases = 4096,
3653 .port_base_addr = 0x10,
3654 .global1_addr = 0x1b,
3655 .global2_addr = 0x1c,
3656 .age_time_coeff = 3750,
3657 .atu_move_port_mask = 0x1f,
3661 .tag_protocol = DSA_TAG_PROTO_EDSA,
3662 .ops = &mv88e6341_ops,
3666 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3667 .family = MV88E6XXX_FAMILY_6351,
3668 .name = "Marvell 88E6350",
3669 .num_databases = 4096,
3672 .port_base_addr = 0x10,
3673 .global1_addr = 0x1b,
3674 .global2_addr = 0x1c,
3675 .age_time_coeff = 15000,
3678 .atu_move_port_mask = 0xf,
3681 .tag_protocol = DSA_TAG_PROTO_EDSA,
3682 .ops = &mv88e6350_ops,
3686 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3687 .family = MV88E6XXX_FAMILY_6351,
3688 .name = "Marvell 88E6351",
3689 .num_databases = 4096,
3692 .port_base_addr = 0x10,
3693 .global1_addr = 0x1b,
3694 .global2_addr = 0x1c,
3695 .age_time_coeff = 15000,
3698 .atu_move_port_mask = 0xf,
3701 .tag_protocol = DSA_TAG_PROTO_EDSA,
3702 .ops = &mv88e6351_ops,
3706 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3707 .family = MV88E6XXX_FAMILY_6352,
3708 .name = "Marvell 88E6352",
3709 .num_databases = 4096,
3712 .port_base_addr = 0x10,
3713 .global1_addr = 0x1b,
3714 .global2_addr = 0x1c,
3715 .age_time_coeff = 15000,
3718 .atu_move_port_mask = 0xf,
3721 .tag_protocol = DSA_TAG_PROTO_EDSA,
3722 .ops = &mv88e6352_ops,
3725 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3726 .family = MV88E6XXX_FAMILY_6390,
3727 .name = "Marvell 88E6390",
3728 .num_databases = 4096,
3729 .num_ports = 11, /* 10 + Z80 */
3731 .port_base_addr = 0x0,
3732 .global1_addr = 0x1b,
3733 .global2_addr = 0x1c,
3734 .age_time_coeff = 3750,
3737 .atu_move_port_mask = 0x1f,
3740 .tag_protocol = DSA_TAG_PROTO_DSA,
3741 .ops = &mv88e6390_ops,
3744 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3745 .family = MV88E6XXX_FAMILY_6390,
3746 .name = "Marvell 88E6390X",
3747 .num_databases = 4096,
3748 .num_ports = 11, /* 10 + Z80 */
3750 .port_base_addr = 0x0,
3751 .global1_addr = 0x1b,
3752 .global2_addr = 0x1c,
3753 .age_time_coeff = 3750,
3756 .atu_move_port_mask = 0x1f,
3759 .tag_protocol = DSA_TAG_PROTO_DSA,
3760 .ops = &mv88e6390x_ops,
3764 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3768 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3769 if (mv88e6xxx_table[i].prod_num == prod_num)
3770 return &mv88e6xxx_table[i];
3775 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3777 const struct mv88e6xxx_info *info;
3778 unsigned int prod_num, rev;
3782 mutex_lock(&chip->reg_lock);
3783 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3784 mutex_unlock(&chip->reg_lock);
3788 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3789 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3791 info = mv88e6xxx_lookup_info(prod_num);
3795 /* Update the compatible info with the probed one */
3798 err = mv88e6xxx_g2_require(chip);
3802 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3803 chip->info->prod_num, chip->info->name, rev);
3808 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3810 struct mv88e6xxx_chip *chip;
3812 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3818 mutex_init(&chip->reg_lock);
3819 INIT_LIST_HEAD(&chip->mdios);
3824 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3825 struct mii_bus *bus, int sw_addr)
3828 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3829 else if (chip->info->multi_chip)
3830 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3835 chip->sw_addr = sw_addr;
3840 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3842 struct mv88e6xxx_chip *chip = ds->priv;
3844 return chip->info->tag_protocol;
3847 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3848 struct device *host_dev, int sw_addr,
3851 struct mv88e6xxx_chip *chip;
3852 struct mii_bus *bus;
3855 bus = dsa_host_dev_to_mii_bus(host_dev);
3859 chip = mv88e6xxx_alloc_chip(dsa_dev);
3863 /* Legacy SMI probing will only support chips similar to 88E6085 */
3864 chip->info = &mv88e6xxx_table[MV88E6085];
3866 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3870 err = mv88e6xxx_detect(chip);
3874 mutex_lock(&chip->reg_lock);
3875 err = mv88e6xxx_switch_reset(chip);
3876 mutex_unlock(&chip->reg_lock);
3880 mv88e6xxx_phy_init(chip);
3882 err = mv88e6xxx_mdios_register(chip, NULL);
3888 return chip->info->name;
3890 devm_kfree(dsa_dev, chip);
3895 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3896 const struct switchdev_obj_port_mdb *mdb,
3897 struct switchdev_trans *trans)
3899 /* We don't need any dynamic resource from the kernel (yet),
3900 * so skip the prepare phase.
3906 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3907 const struct switchdev_obj_port_mdb *mdb,
3908 struct switchdev_trans *trans)
3910 struct mv88e6xxx_chip *chip = ds->priv;
3912 mutex_lock(&chip->reg_lock);
3913 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3914 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
3915 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3917 mutex_unlock(&chip->reg_lock);
3920 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3921 const struct switchdev_obj_port_mdb *mdb)
3923 struct mv88e6xxx_chip *chip = ds->priv;
3926 mutex_lock(&chip->reg_lock);
3927 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3928 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
3929 mutex_unlock(&chip->reg_lock);
3934 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3935 struct switchdev_obj_port_mdb *mdb,
3936 switchdev_obj_dump_cb_t *cb)
3938 struct mv88e6xxx_chip *chip = ds->priv;
3941 mutex_lock(&chip->reg_lock);
3942 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3943 mutex_unlock(&chip->reg_lock);
3948 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
3949 .probe = mv88e6xxx_drv_probe,
3950 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
3951 .setup = mv88e6xxx_setup,
3952 .set_addr = mv88e6xxx_set_addr,
3953 .adjust_link = mv88e6xxx_adjust_link,
3954 .get_strings = mv88e6xxx_get_strings,
3955 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3956 .get_sset_count = mv88e6xxx_get_sset_count,
3957 .port_enable = mv88e6xxx_port_enable,
3958 .port_disable = mv88e6xxx_port_disable,
3959 .set_eee = mv88e6xxx_set_eee,
3960 .get_eee = mv88e6xxx_get_eee,
3961 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3962 .get_eeprom = mv88e6xxx_get_eeprom,
3963 .set_eeprom = mv88e6xxx_set_eeprom,
3964 .get_regs_len = mv88e6xxx_get_regs_len,
3965 .get_regs = mv88e6xxx_get_regs,
3966 .set_ageing_time = mv88e6xxx_set_ageing_time,
3967 .port_bridge_join = mv88e6xxx_port_bridge_join,
3968 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3969 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3970 .port_fast_age = mv88e6xxx_port_fast_age,
3971 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3972 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3973 .port_vlan_add = mv88e6xxx_port_vlan_add,
3974 .port_vlan_del = mv88e6xxx_port_vlan_del,
3975 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3976 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3977 .port_fdb_add = mv88e6xxx_port_fdb_add,
3978 .port_fdb_del = mv88e6xxx_port_fdb_del,
3979 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3980 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3981 .port_mdb_add = mv88e6xxx_port_mdb_add,
3982 .port_mdb_del = mv88e6xxx_port_mdb_del,
3983 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
3984 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3985 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
3988 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3989 .ops = &mv88e6xxx_switch_ops,
3992 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
3994 struct device *dev = chip->dev;
3995 struct dsa_switch *ds;
3997 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4002 ds->ops = &mv88e6xxx_switch_ops;
4003 ds->ageing_time_min = chip->info->age_time_coeff;
4004 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4006 dev_set_drvdata(dev, ds);
4008 return dsa_register_switch(ds);
4011 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4013 dsa_unregister_switch(chip->ds);
4016 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4018 struct device *dev = &mdiodev->dev;
4019 struct device_node *np = dev->of_node;
4020 const struct mv88e6xxx_info *compat_info;
4021 struct mv88e6xxx_chip *chip;
4025 compat_info = of_device_get_match_data(dev);
4029 chip = mv88e6xxx_alloc_chip(dev);
4033 chip->info = compat_info;
4035 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4039 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4040 if (IS_ERR(chip->reset))
4041 return PTR_ERR(chip->reset);
4043 err = mv88e6xxx_detect(chip);
4047 mv88e6xxx_phy_init(chip);
4049 if (chip->info->ops->get_eeprom &&
4050 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4051 chip->eeprom_len = eeprom_len;
4053 mutex_lock(&chip->reg_lock);
4054 err = mv88e6xxx_switch_reset(chip);
4055 mutex_unlock(&chip->reg_lock);
4059 chip->irq = of_irq_get(np, 0);
4060 if (chip->irq == -EPROBE_DEFER) {
4065 if (chip->irq > 0) {
4066 /* Has to be performed before the MDIO bus is created,
4067 * because the PHYs will link there interrupts to these
4068 * interrupt controllers
4070 mutex_lock(&chip->reg_lock);
4071 err = mv88e6xxx_g1_irq_setup(chip);
4072 mutex_unlock(&chip->reg_lock);
4077 if (chip->info->g2_irqs > 0) {
4078 err = mv88e6xxx_g2_irq_setup(chip);
4084 err = mv88e6xxx_mdios_register(chip, np);
4088 err = mv88e6xxx_register_switch(chip);
4095 mv88e6xxx_mdios_unregister(chip);
4097 if (chip->info->g2_irqs > 0 && chip->irq > 0)
4098 mv88e6xxx_g2_irq_free(chip);
4100 if (chip->irq > 0) {
4101 mutex_lock(&chip->reg_lock);
4102 mv88e6xxx_g1_irq_free(chip);
4103 mutex_unlock(&chip->reg_lock);
4109 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4111 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4112 struct mv88e6xxx_chip *chip = ds->priv;
4114 mv88e6xxx_phy_destroy(chip);
4115 mv88e6xxx_unregister_switch(chip);
4116 mv88e6xxx_mdios_unregister(chip);
4118 if (chip->irq > 0) {
4119 if (chip->info->g2_irqs > 0)
4120 mv88e6xxx_g2_irq_free(chip);
4121 mv88e6xxx_g1_irq_free(chip);
4125 static const struct of_device_id mv88e6xxx_of_match[] = {
4127 .compatible = "marvell,mv88e6085",
4128 .data = &mv88e6xxx_table[MV88E6085],
4131 .compatible = "marvell,mv88e6190",
4132 .data = &mv88e6xxx_table[MV88E6190],
4137 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4139 static struct mdio_driver mv88e6xxx_driver = {
4140 .probe = mv88e6xxx_probe,
4141 .remove = mv88e6xxx_remove,
4143 .name = "mv88e6085",
4144 .of_match_table = mv88e6xxx_of_match,
4148 static int __init mv88e6xxx_init(void)
4150 register_switch_driver(&mv88e6xxx_switch_drv);
4151 return mdio_driver_register(&mv88e6xxx_driver);
4153 module_init(mv88e6xxx_init);
4155 static void __exit mv88e6xxx_cleanup(void)
4157 mdio_driver_unregister(&mv88e6xxx_driver);
4158 unregister_switch_driver(&mv88e6xxx_switch_drv);
4160 module_exit(mv88e6xxx_cleanup);
4162 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4163 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4164 MODULE_LICENSE("GPL");