1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88e6xxx Ethernet switch single-chip support
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/if_bridge.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/jiffies.h>
21 #include <linux/list.h>
22 #include <linux/mdio.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/platform_data/mv88e6xxx.h>
28 #include <linux/netdevice.h>
29 #include <linux/gpio/consumer.h>
30 #include <linux/phy.h>
31 #include <linux/phylink.h>
44 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
47 dev_err(chip->dev, "Switch registers lock not held!\n");
52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
56 assert_reg_lock(chip);
58 err = mv88e6xxx_smi_read(chip, addr, reg, val);
62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
72 assert_reg_lock(chip);
74 err = mv88e6xxx_smi_write(chip, addr, reg, val);
78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
84 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
86 struct mv88e6xxx_mdio_bus *mdio_bus;
88 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
96 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
98 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
99 unsigned int n = d->hwirq;
101 chip->g1_irq.masked |= (1 << n);
104 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
106 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
107 unsigned int n = d->hwirq;
109 chip->g1_irq.masked &= ~(1 << n);
112 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
114 unsigned int nhandled = 0;
115 unsigned int sub_irq;
121 mv88e6xxx_reg_lock(chip);
122 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
123 mv88e6xxx_reg_unlock(chip);
129 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
130 if (reg & (1 << n)) {
131 sub_irq = irq_find_mapping(chip->g1_irq.domain,
133 handle_nested_irq(sub_irq);
138 mv88e6xxx_reg_lock(chip);
139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
142 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
144 mv88e6xxx_reg_unlock(chip);
147 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
148 } while (reg & ctl1);
151 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
154 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
156 struct mv88e6xxx_chip *chip = dev_id;
158 return mv88e6xxx_g1_irq_thread_work(chip);
161 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
163 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
165 mv88e6xxx_reg_lock(chip);
168 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
170 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
171 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
175 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
180 reg |= (~chip->g1_irq.masked & mask);
182 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
187 mv88e6xxx_reg_unlock(chip);
190 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
191 .name = "mv88e6xxx-g1",
192 .irq_mask = mv88e6xxx_g1_irq_mask,
193 .irq_unmask = mv88e6xxx_g1_irq_unmask,
194 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
195 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
198 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
200 irq_hw_number_t hwirq)
202 struct mv88e6xxx_chip *chip = d->host_data;
204 irq_set_chip_data(irq, d->host_data);
205 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
206 irq_set_noprobe(irq);
211 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
212 .map = mv88e6xxx_g1_irq_domain_map,
213 .xlate = irq_domain_xlate_twocell,
216 /* To be called with reg_lock held */
217 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
222 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
223 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
224 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
226 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
227 virq = irq_find_mapping(chip->g1_irq.domain, irq);
228 irq_dispose_mapping(virq);
231 irq_domain_remove(chip->g1_irq.domain);
234 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
237 * free_irq must be called without reg_lock taken because the irq
238 * handler takes this lock, too.
240 free_irq(chip->irq, chip);
242 mv88e6xxx_reg_lock(chip);
243 mv88e6xxx_g1_irq_free_common(chip);
244 mv88e6xxx_reg_unlock(chip);
247 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
252 chip->g1_irq.nirqs = chip->info->g1_irqs;
253 chip->g1_irq.domain = irq_domain_add_simple(
254 NULL, chip->g1_irq.nirqs, 0,
255 &mv88e6xxx_g1_irq_domain_ops, chip);
256 if (!chip->g1_irq.domain)
259 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
260 irq_create_mapping(chip->g1_irq.domain, irq);
262 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
263 chip->g1_irq.masked = ~0;
265 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
271 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
275 /* Reading the interrupt status clears (most of) them */
276 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
283 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
284 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
287 for (irq = 0; irq < 16; irq++) {
288 virq = irq_find_mapping(chip->g1_irq.domain, irq);
289 irq_dispose_mapping(virq);
292 irq_domain_remove(chip->g1_irq.domain);
297 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
299 static struct lock_class_key lock_key;
300 static struct lock_class_key request_key;
303 err = mv88e6xxx_g1_irq_setup_common(chip);
307 /* These lock classes tells lockdep that global 1 irqs are in
308 * a different category than their parent GPIO, so it won't
309 * report false recursion.
311 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
313 mv88e6xxx_reg_unlock(chip);
314 err = request_threaded_irq(chip->irq, NULL,
315 mv88e6xxx_g1_irq_thread_fn,
316 IRQF_ONESHOT | IRQF_SHARED,
317 dev_name(chip->dev), chip);
318 mv88e6xxx_reg_lock(chip);
320 mv88e6xxx_g1_irq_free_common(chip);
325 static void mv88e6xxx_irq_poll(struct kthread_work *work)
327 struct mv88e6xxx_chip *chip = container_of(work,
328 struct mv88e6xxx_chip,
330 mv88e6xxx_g1_irq_thread_work(chip);
332 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
333 msecs_to_jiffies(100));
336 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
340 err = mv88e6xxx_g1_irq_setup_common(chip);
344 kthread_init_delayed_work(&chip->irq_poll_work,
347 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
348 if (IS_ERR(chip->kworker))
349 return PTR_ERR(chip->kworker);
351 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
352 msecs_to_jiffies(100));
357 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
359 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
360 kthread_destroy_worker(chip->kworker);
362 mv88e6xxx_reg_lock(chip);
363 mv88e6xxx_g1_irq_free_common(chip);
364 mv88e6xxx_reg_unlock(chip);
367 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
371 for (i = 0; i < 16; i++) {
375 err = mv88e6xxx_read(chip, addr, reg, &val);
382 usleep_range(1000, 2000);
385 dev_err(chip->dev, "Timeout while waiting for switch\n");
389 /* Indirect write to single pointer-data register with an Update bit */
390 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
395 /* Wait until the previous operation is completed */
396 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
400 /* Set the Update bit to trigger a write operation */
401 val = BIT(15) | update;
403 return mv88e6xxx_write(chip, addr, reg, val);
406 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
407 int speed, int duplex, int pause,
408 phy_interface_t mode)
410 struct phylink_link_state state;
413 if (!chip->info->ops->port_set_link)
416 if (!chip->info->ops->port_link_state)
419 err = chip->info->ops->port_link_state(chip, port, &state);
423 /* Has anything actually changed? We don't expect the
424 * interface mode to change without one of the other
425 * parameters also changing
427 if (state.link == link &&
428 state.speed == speed &&
429 state.duplex == duplex)
432 /* Port's MAC control must not be changed unless the link is down */
433 err = chip->info->ops->port_set_link(chip, port, 0);
437 if (chip->info->ops->port_set_speed) {
438 err = chip->info->ops->port_set_speed(chip, port, speed);
439 if (err && err != -EOPNOTSUPP)
443 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
444 mode = chip->info->ops->port_max_speed_mode(port);
446 if (chip->info->ops->port_set_pause) {
447 err = chip->info->ops->port_set_pause(chip, port, pause);
452 if (chip->info->ops->port_set_duplex) {
453 err = chip->info->ops->port_set_duplex(chip, port, duplex);
454 if (err && err != -EOPNOTSUPP)
458 if (chip->info->ops->port_set_rgmii_delay) {
459 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
460 if (err && err != -EOPNOTSUPP)
464 if (chip->info->ops->port_set_cmode) {
465 err = chip->info->ops->port_set_cmode(chip, port, mode);
466 if (err && err != -EOPNOTSUPP)
472 if (chip->info->ops->port_set_link(chip, port, link))
473 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
478 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
480 struct mv88e6xxx_chip *chip = ds->priv;
482 return port < chip->info->num_internal_phys;
485 /* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
489 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
490 struct phy_device *phydev)
492 struct mv88e6xxx_chip *chip = ds->priv;
495 if (!phy_is_pseudo_fixed_link(phydev) &&
496 mv88e6xxx_phy_is_internal(ds, port))
499 mv88e6xxx_reg_lock(chip);
500 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
501 phydev->duplex, phydev->pause,
503 mv88e6xxx_reg_unlock(chip);
505 if (err && err != -EOPNOTSUPP)
506 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
509 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
511 struct phylink_link_state *state)
513 if (!phy_interface_mode_is_8023z(state->interface)) {
514 /* 10M and 100M are only supported in non-802.3z mode */
515 phylink_set(mask, 10baseT_Half);
516 phylink_set(mask, 10baseT_Full);
517 phylink_set(mask, 100baseT_Half);
518 phylink_set(mask, 100baseT_Full);
522 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
524 struct phylink_link_state *state)
526 /* FIXME: if the port is in 1000Base-X mode, then it only supports
527 * 1000M FD speeds. In this case, CMODE will indicate 5.
529 phylink_set(mask, 1000baseT_Full);
530 phylink_set(mask, 1000baseX_Full);
532 mv88e6065_phylink_validate(chip, port, mask, state);
535 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
537 struct phylink_link_state *state)
540 phylink_set(mask, 2500baseX_Full);
542 /* No ethtool bits for 200Mbps */
543 phylink_set(mask, 1000baseT_Full);
544 phylink_set(mask, 1000baseX_Full);
546 mv88e6065_phylink_validate(chip, port, mask, state);
549 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
551 struct phylink_link_state *state)
553 /* No ethtool bits for 200Mbps */
554 phylink_set(mask, 1000baseT_Full);
555 phylink_set(mask, 1000baseX_Full);
557 mv88e6065_phylink_validate(chip, port, mask, state);
560 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
562 struct phylink_link_state *state)
565 phylink_set(mask, 2500baseX_Full);
566 phylink_set(mask, 2500baseT_Full);
569 /* No ethtool bits for 200Mbps */
570 phylink_set(mask, 1000baseT_Full);
571 phylink_set(mask, 1000baseX_Full);
573 mv88e6065_phylink_validate(chip, port, mask, state);
576 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
578 struct phylink_link_state *state)
581 phylink_set(mask, 10000baseT_Full);
582 phylink_set(mask, 10000baseKR_Full);
585 mv88e6390_phylink_validate(chip, port, mask, state);
588 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
589 unsigned long *supported,
590 struct phylink_link_state *state)
592 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
593 struct mv88e6xxx_chip *chip = ds->priv;
595 /* Allow all the expected bits */
596 phylink_set(mask, Autoneg);
597 phylink_set(mask, Pause);
598 phylink_set_port_modes(mask);
600 if (chip->info->ops->phylink_validate)
601 chip->info->ops->phylink_validate(chip, port, mask, state);
603 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
604 bitmap_and(state->advertising, state->advertising, mask,
605 __ETHTOOL_LINK_MODE_MASK_NBITS);
607 /* We can only operate at 2500BaseX or 1000BaseX. If requested
608 * to advertise both, only report advertising at 2500BaseX.
610 phylink_helper_basex_speed(state);
613 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
614 struct phylink_link_state *state)
616 struct mv88e6xxx_chip *chip = ds->priv;
619 mv88e6xxx_reg_lock(chip);
620 if (chip->info->ops->port_link_state)
621 err = chip->info->ops->port_link_state(chip, port, state);
624 mv88e6xxx_reg_unlock(chip);
629 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
631 const struct phylink_link_state *state)
633 struct mv88e6xxx_chip *chip = ds->priv;
634 int speed, duplex, link, pause, err;
636 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
639 if (mode == MLO_AN_FIXED) {
640 link = LINK_FORCED_UP;
641 speed = state->speed;
642 duplex = state->duplex;
643 } else if (!mv88e6xxx_phy_is_internal(ds, port)) {
645 speed = state->speed;
646 duplex = state->duplex;
648 speed = SPEED_UNFORCED;
649 duplex = DUPLEX_UNFORCED;
650 link = LINK_UNFORCED;
652 pause = !!phylink_test(state->advertising, Pause);
654 mv88e6xxx_reg_lock(chip);
655 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
657 mv88e6xxx_reg_unlock(chip);
659 if (err && err != -EOPNOTSUPP)
660 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
663 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
665 struct mv88e6xxx_chip *chip = ds->priv;
668 mv88e6xxx_reg_lock(chip);
669 err = chip->info->ops->port_set_link(chip, port, link);
670 mv88e6xxx_reg_unlock(chip);
673 dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
676 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
678 phy_interface_t interface)
680 if (mode == MLO_AN_FIXED)
681 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
684 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
685 unsigned int mode, phy_interface_t interface,
686 struct phy_device *phydev)
688 if (mode == MLO_AN_FIXED)
689 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
692 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
694 if (!chip->info->ops->stats_snapshot)
697 return chip->info->ops->stats_snapshot(chip, port);
700 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
701 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
702 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
703 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
704 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
705 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
706 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
707 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
708 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
709 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
710 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
711 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
712 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
713 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
714 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
715 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
716 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
717 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
718 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
719 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
720 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
721 { "single", 4, 0x14, STATS_TYPE_BANK0, },
722 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
723 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
724 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
725 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
726 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
727 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
728 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
729 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
730 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
731 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
732 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
733 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
734 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
735 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
736 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
737 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
738 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
739 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
740 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
741 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
742 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
743 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
744 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
745 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
746 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
747 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
748 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
749 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
750 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
751 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
752 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
753 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
754 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
755 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
756 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
757 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
758 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
759 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
762 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
763 struct mv88e6xxx_hw_stat *s,
764 int port, u16 bank1_select,
774 case STATS_TYPE_PORT:
775 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
781 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
784 low |= ((u32)reg) << 16;
787 case STATS_TYPE_BANK1:
790 case STATS_TYPE_BANK0:
791 reg |= s->reg | histogram;
792 mv88e6xxx_g1_stats_read(chip, reg, &low);
794 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
799 value = (((u64)high) << 32) | low;
803 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
804 uint8_t *data, int types)
806 struct mv88e6xxx_hw_stat *stat;
809 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
810 stat = &mv88e6xxx_hw_stats[i];
811 if (stat->type & types) {
812 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
821 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
824 return mv88e6xxx_stats_get_strings(chip, data,
825 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
828 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
831 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
834 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
837 return mv88e6xxx_stats_get_strings(chip, data,
838 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
841 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
842 "atu_member_violation",
843 "atu_miss_violation",
844 "atu_full_violation",
845 "vtu_member_violation",
846 "vtu_miss_violation",
849 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
853 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
854 strlcpy(data + i * ETH_GSTRING_LEN,
855 mv88e6xxx_atu_vtu_stats_strings[i],
859 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
860 u32 stringset, uint8_t *data)
862 struct mv88e6xxx_chip *chip = ds->priv;
865 if (stringset != ETH_SS_STATS)
868 mv88e6xxx_reg_lock(chip);
870 if (chip->info->ops->stats_get_strings)
871 count = chip->info->ops->stats_get_strings(chip, data);
873 if (chip->info->ops->serdes_get_strings) {
874 data += count * ETH_GSTRING_LEN;
875 count = chip->info->ops->serdes_get_strings(chip, port, data);
878 data += count * ETH_GSTRING_LEN;
879 mv88e6xxx_atu_vtu_get_strings(data);
881 mv88e6xxx_reg_unlock(chip);
884 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
887 struct mv88e6xxx_hw_stat *stat;
890 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
891 stat = &mv88e6xxx_hw_stats[i];
892 if (stat->type & types)
898 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
900 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
904 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
906 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
909 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
911 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
915 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
917 struct mv88e6xxx_chip *chip = ds->priv;
918 int serdes_count = 0;
921 if (sset != ETH_SS_STATS)
924 mv88e6xxx_reg_lock(chip);
925 if (chip->info->ops->stats_get_sset_count)
926 count = chip->info->ops->stats_get_sset_count(chip);
930 if (chip->info->ops->serdes_get_sset_count)
931 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
933 if (serdes_count < 0) {
934 count = serdes_count;
937 count += serdes_count;
938 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
941 mv88e6xxx_reg_unlock(chip);
946 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
947 uint64_t *data, int types,
948 u16 bank1_select, u16 histogram)
950 struct mv88e6xxx_hw_stat *stat;
953 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
954 stat = &mv88e6xxx_hw_stats[i];
955 if (stat->type & types) {
956 mv88e6xxx_reg_lock(chip);
957 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
960 mv88e6xxx_reg_unlock(chip);
968 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
971 return mv88e6xxx_stats_get_stats(chip, port, data,
972 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
973 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
976 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
979 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
980 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
983 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
986 return mv88e6xxx_stats_get_stats(chip, port, data,
987 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
988 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
989 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
992 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
995 return mv88e6xxx_stats_get_stats(chip, port, data,
996 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
997 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1001 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1004 *data++ = chip->ports[port].atu_member_violation;
1005 *data++ = chip->ports[port].atu_miss_violation;
1006 *data++ = chip->ports[port].atu_full_violation;
1007 *data++ = chip->ports[port].vtu_member_violation;
1008 *data++ = chip->ports[port].vtu_miss_violation;
1011 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1016 if (chip->info->ops->stats_get_stats)
1017 count = chip->info->ops->stats_get_stats(chip, port, data);
1019 mv88e6xxx_reg_lock(chip);
1020 if (chip->info->ops->serdes_get_stats) {
1022 count = chip->info->ops->serdes_get_stats(chip, port, data);
1025 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1026 mv88e6xxx_reg_unlock(chip);
1029 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1032 struct mv88e6xxx_chip *chip = ds->priv;
1035 mv88e6xxx_reg_lock(chip);
1037 ret = mv88e6xxx_stats_snapshot(chip, port);
1038 mv88e6xxx_reg_unlock(chip);
1043 mv88e6xxx_get_stats(chip, port, data);
1047 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1049 return 32 * sizeof(u16);
1052 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1053 struct ethtool_regs *regs, void *_p)
1055 struct mv88e6xxx_chip *chip = ds->priv;
1061 regs->version = chip->info->prod_num;
1063 memset(p, 0xff, 32 * sizeof(u16));
1065 mv88e6xxx_reg_lock(chip);
1067 for (i = 0; i < 32; i++) {
1069 err = mv88e6xxx_port_read(chip, port, i, ®);
1074 mv88e6xxx_reg_unlock(chip);
1077 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1078 struct ethtool_eee *e)
1080 /* Nothing to do on the port's MAC */
1084 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1085 struct ethtool_eee *e)
1087 /* Nothing to do on the port's MAC */
1091 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1093 struct dsa_switch *ds = NULL;
1094 struct net_device *br;
1098 if (dev < DSA_MAX_SWITCHES)
1099 ds = chip->ds->dst->ds[dev];
1101 /* Prevent frames from unknown switch or port */
1102 if (!ds || port >= ds->num_ports)
1105 /* Frames from DSA links and CPU ports can egress any local port */
1106 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1107 return mv88e6xxx_port_mask(chip);
1109 br = ds->ports[port].bridge_dev;
1112 /* Frames from user ports can egress any local DSA links and CPU ports,
1113 * as well as any local member of their bridge group.
1115 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1116 if (dsa_is_cpu_port(chip->ds, i) ||
1117 dsa_is_dsa_port(chip->ds, i) ||
1118 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1124 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1126 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1128 /* prevent frames from going back out of the port they came in on */
1129 output_ports &= ~BIT(port);
1131 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1134 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1137 struct mv88e6xxx_chip *chip = ds->priv;
1140 mv88e6xxx_reg_lock(chip);
1141 err = mv88e6xxx_port_set_state(chip, port, state);
1142 mv88e6xxx_reg_unlock(chip);
1145 dev_err(ds->dev, "p%d: failed to update state\n", port);
1148 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1152 if (chip->info->ops->ieee_pri_map) {
1153 err = chip->info->ops->ieee_pri_map(chip);
1158 if (chip->info->ops->ip_pri_map) {
1159 err = chip->info->ops->ip_pri_map(chip);
1167 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1172 if (!chip->info->global2_addr)
1175 /* Initialize the routing port to the 32 possible target devices */
1176 for (target = 0; target < 32; target++) {
1178 if (target < DSA_MAX_SWITCHES)
1179 if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
1180 port = chip->ds->rtable[target];
1182 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1187 if (chip->info->ops->set_cascade_port) {
1188 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1189 err = chip->info->ops->set_cascade_port(chip, port);
1194 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1201 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1203 /* Clear all trunk masks and mapping */
1204 if (chip->info->global2_addr)
1205 return mv88e6xxx_g2_trunk_clear(chip);
1210 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1212 if (chip->info->ops->rmu_disable)
1213 return chip->info->ops->rmu_disable(chip);
1218 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1220 if (chip->info->ops->pot_clear)
1221 return chip->info->ops->pot_clear(chip);
1226 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1228 if (chip->info->ops->mgmt_rsvd2cpu)
1229 return chip->info->ops->mgmt_rsvd2cpu(chip);
1234 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1238 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1242 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1246 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1249 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1254 if (!chip->info->ops->irl_init_all)
1257 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1258 /* Disable ingress rate limiting by resetting all per port
1259 * ingress rate limit resources to their initial state.
1261 err = chip->info->ops->irl_init_all(chip, port);
1269 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1271 if (chip->info->ops->set_switch_mac) {
1274 eth_random_addr(addr);
1276 return chip->info->ops->set_switch_mac(chip, addr);
1282 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1286 if (!mv88e6xxx_has_pvt(chip))
1289 /* Skip the local source device, which uses in-chip port VLAN */
1290 if (dev != chip->ds->index)
1291 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1293 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1296 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1301 if (!mv88e6xxx_has_pvt(chip))
1304 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1305 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1307 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1311 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1312 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1313 err = mv88e6xxx_pvt_map(chip, dev, port);
1322 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1324 struct mv88e6xxx_chip *chip = ds->priv;
1327 mv88e6xxx_reg_lock(chip);
1328 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1329 mv88e6xxx_reg_unlock(chip);
1332 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1335 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1337 if (!chip->info->max_vid)
1340 return mv88e6xxx_g1_vtu_flush(chip);
1343 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1344 struct mv88e6xxx_vtu_entry *entry)
1346 if (!chip->info->ops->vtu_getnext)
1349 return chip->info->ops->vtu_getnext(chip, entry);
1352 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1353 struct mv88e6xxx_vtu_entry *entry)
1355 if (!chip->info->ops->vtu_loadpurge)
1358 return chip->info->ops->vtu_loadpurge(chip, entry);
1361 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1363 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1364 struct mv88e6xxx_vtu_entry vlan = {
1365 .vid = chip->info->max_vid,
1369 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1371 /* Set every FID bit used by the (un)bridged ports */
1372 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1373 err = mv88e6xxx_port_get_fid(chip, i, fid);
1377 set_bit(*fid, fid_bitmap);
1380 /* Set every FID bit used by the VLAN entries */
1382 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1389 set_bit(vlan.fid, fid_bitmap);
1390 } while (vlan.vid < chip->info->max_vid);
1392 /* The reset value 0x000 is used to indicate that multiple address
1393 * databases are not needed. Return the next positive available.
1395 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1396 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1399 /* Clear the database */
1400 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1403 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1404 struct mv88e6xxx_vtu_entry *entry, bool new)
1411 entry->vid = vid - 1;
1412 entry->valid = false;
1414 err = mv88e6xxx_vtu_getnext(chip, entry);
1418 if (entry->vid == vid && entry->valid)
1424 /* Initialize a fresh VLAN entry */
1425 memset(entry, 0, sizeof(*entry));
1426 entry->valid = true;
1429 /* Exclude all ports */
1430 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1432 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1434 return mv88e6xxx_atu_new(chip, &entry->fid);
1437 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1441 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1442 u16 vid_begin, u16 vid_end)
1444 struct mv88e6xxx_chip *chip = ds->priv;
1445 struct mv88e6xxx_vtu_entry vlan = {
1446 .vid = vid_begin - 1,
1450 /* DSA and CPU ports have to be members of multiple vlans */
1451 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1457 mv88e6xxx_reg_lock(chip);
1460 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1467 if (vlan.vid > vid_end)
1470 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1471 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1474 if (!ds->ports[i].slave)
1477 if (vlan.member[i] ==
1478 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1481 if (dsa_to_port(ds, i)->bridge_dev ==
1482 ds->ports[port].bridge_dev)
1483 break; /* same bridge, check next VLAN */
1485 if (!dsa_to_port(ds, i)->bridge_dev)
1488 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1490 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1494 } while (vlan.vid < vid_end);
1497 mv88e6xxx_reg_unlock(chip);
1502 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1503 bool vlan_filtering)
1505 struct mv88e6xxx_chip *chip = ds->priv;
1506 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1507 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1510 if (!chip->info->max_vid)
1513 mv88e6xxx_reg_lock(chip);
1514 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1515 mv88e6xxx_reg_unlock(chip);
1521 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1522 const struct switchdev_obj_port_vlan *vlan)
1524 struct mv88e6xxx_chip *chip = ds->priv;
1527 if (!chip->info->max_vid)
1530 /* If the requested port doesn't belong to the same bridge as the VLAN
1531 * members, do not support it (yet) and fallback to software VLAN.
1533 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1538 /* We don't need any dynamic resource from the kernel (yet),
1539 * so skip the prepare phase.
1544 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1545 const unsigned char *addr, u16 vid,
1548 struct mv88e6xxx_vtu_entry vlan;
1549 struct mv88e6xxx_atu_entry entry;
1552 /* Null VLAN ID corresponds to the port private database */
1554 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1556 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1560 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1561 ether_addr_copy(entry.mac, addr);
1562 eth_addr_dec(entry.mac);
1564 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1568 /* Initialize a fresh ATU entry if it isn't found */
1569 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1570 !ether_addr_equal(entry.mac, addr)) {
1571 memset(&entry, 0, sizeof(entry));
1572 ether_addr_copy(entry.mac, addr);
1575 /* Purge the ATU entry only if no port is using it anymore */
1576 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1577 entry.portvec &= ~BIT(port);
1579 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1581 entry.portvec |= BIT(port);
1582 entry.state = state;
1585 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1588 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1591 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1592 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1594 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1597 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1602 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1603 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1611 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1614 struct mv88e6xxx_vtu_entry vlan;
1617 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1621 vlan.member[port] = member;
1623 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1627 return mv88e6xxx_broadcast_setup(chip, vid);
1630 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1631 const struct switchdev_obj_port_vlan *vlan)
1633 struct mv88e6xxx_chip *chip = ds->priv;
1634 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1635 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1639 if (!chip->info->max_vid)
1642 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1643 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1645 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1647 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1649 mv88e6xxx_reg_lock(chip);
1651 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1652 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1653 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1654 vid, untagged ? 'u' : 't');
1656 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1657 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1660 mv88e6xxx_reg_unlock(chip);
1663 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1666 struct mv88e6xxx_vtu_entry vlan;
1669 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1673 /* Tell switchdev if this VLAN is handled in software */
1674 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1677 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1679 /* keep the VLAN unless all ports are excluded */
1681 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1682 if (vlan.member[i] !=
1683 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1689 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1693 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1696 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1697 const struct switchdev_obj_port_vlan *vlan)
1699 struct mv88e6xxx_chip *chip = ds->priv;
1703 if (!chip->info->max_vid)
1706 mv88e6xxx_reg_lock(chip);
1708 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1712 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1713 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1718 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1725 mv88e6xxx_reg_unlock(chip);
1730 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1731 const unsigned char *addr, u16 vid)
1733 struct mv88e6xxx_chip *chip = ds->priv;
1736 mv88e6xxx_reg_lock(chip);
1737 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1738 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1739 mv88e6xxx_reg_unlock(chip);
1744 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1745 const unsigned char *addr, u16 vid)
1747 struct mv88e6xxx_chip *chip = ds->priv;
1750 mv88e6xxx_reg_lock(chip);
1751 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1752 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1753 mv88e6xxx_reg_unlock(chip);
1758 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1759 u16 fid, u16 vid, int port,
1760 dsa_fdb_dump_cb_t *cb, void *data)
1762 struct mv88e6xxx_atu_entry addr;
1766 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1767 eth_broadcast_addr(addr.mac);
1770 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1774 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1777 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1780 if (!is_unicast_ether_addr(addr.mac))
1783 is_static = (addr.state ==
1784 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1785 err = cb(addr.mac, vid, is_static, data);
1788 } while (!is_broadcast_ether_addr(addr.mac));
1793 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1794 dsa_fdb_dump_cb_t *cb, void *data)
1796 struct mv88e6xxx_vtu_entry vlan = {
1797 .vid = chip->info->max_vid,
1802 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1803 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1807 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1811 /* Dump VLANs' Filtering Information Databases */
1813 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1820 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1824 } while (vlan.vid < chip->info->max_vid);
1829 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1830 dsa_fdb_dump_cb_t *cb, void *data)
1832 struct mv88e6xxx_chip *chip = ds->priv;
1835 mv88e6xxx_reg_lock(chip);
1836 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
1837 mv88e6xxx_reg_unlock(chip);
1842 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1843 struct net_device *br)
1845 struct dsa_switch *ds;
1850 /* Remap the Port VLAN of each local bridge group member */
1851 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1852 if (chip->ds->ports[port].bridge_dev == br) {
1853 err = mv88e6xxx_port_vlan_map(chip, port);
1859 if (!mv88e6xxx_has_pvt(chip))
1862 /* Remap the Port VLAN of each cross-chip bridge group member */
1863 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1864 ds = chip->ds->dst->ds[dev];
1868 for (port = 0; port < ds->num_ports; ++port) {
1869 if (ds->ports[port].bridge_dev == br) {
1870 err = mv88e6xxx_pvt_map(chip, dev, port);
1880 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1881 struct net_device *br)
1883 struct mv88e6xxx_chip *chip = ds->priv;
1886 mv88e6xxx_reg_lock(chip);
1887 err = mv88e6xxx_bridge_map(chip, br);
1888 mv88e6xxx_reg_unlock(chip);
1893 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1894 struct net_device *br)
1896 struct mv88e6xxx_chip *chip = ds->priv;
1898 mv88e6xxx_reg_lock(chip);
1899 if (mv88e6xxx_bridge_map(chip, br) ||
1900 mv88e6xxx_port_vlan_map(chip, port))
1901 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1902 mv88e6xxx_reg_unlock(chip);
1905 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1906 int port, struct net_device *br)
1908 struct mv88e6xxx_chip *chip = ds->priv;
1911 if (!mv88e6xxx_has_pvt(chip))
1914 mv88e6xxx_reg_lock(chip);
1915 err = mv88e6xxx_pvt_map(chip, dev, port);
1916 mv88e6xxx_reg_unlock(chip);
1921 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1922 int port, struct net_device *br)
1924 struct mv88e6xxx_chip *chip = ds->priv;
1926 if (!mv88e6xxx_has_pvt(chip))
1929 mv88e6xxx_reg_lock(chip);
1930 if (mv88e6xxx_pvt_map(chip, dev, port))
1931 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1932 mv88e6xxx_reg_unlock(chip);
1935 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1937 if (chip->info->ops->reset)
1938 return chip->info->ops->reset(chip);
1943 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1945 struct gpio_desc *gpiod = chip->reset;
1947 /* If there is a GPIO connected to the reset pin, toggle it */
1949 gpiod_set_value_cansleep(gpiod, 1);
1950 usleep_range(10000, 20000);
1951 gpiod_set_value_cansleep(gpiod, 0);
1952 usleep_range(10000, 20000);
1956 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1960 /* Set all ports to the Disabled state */
1961 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1962 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1967 /* Wait for transmit queues to drain,
1968 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1970 usleep_range(2000, 4000);
1975 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1979 err = mv88e6xxx_disable_ports(chip);
1983 mv88e6xxx_hardware_reset(chip);
1985 return mv88e6xxx_software_reset(chip);
1988 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1989 enum mv88e6xxx_frame_mode frame,
1990 enum mv88e6xxx_egress_mode egress, u16 etype)
1994 if (!chip->info->ops->port_set_frame_mode)
1997 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2001 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2005 if (chip->info->ops->port_set_ether_type)
2006 return chip->info->ops->port_set_ether_type(chip, port, etype);
2011 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2013 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2014 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2015 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2018 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2020 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2021 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2022 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2025 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2027 return mv88e6xxx_set_port_mode(chip, port,
2028 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2029 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2033 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2035 if (dsa_is_dsa_port(chip->ds, port))
2036 return mv88e6xxx_set_port_mode_dsa(chip, port);
2038 if (dsa_is_user_port(chip->ds, port))
2039 return mv88e6xxx_set_port_mode_normal(chip, port);
2041 /* Setup CPU port mode depending on its supported tag format */
2042 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2043 return mv88e6xxx_set_port_mode_dsa(chip, port);
2045 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2046 return mv88e6xxx_set_port_mode_edsa(chip, port);
2051 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2053 bool message = dsa_is_dsa_port(chip->ds, port);
2055 return mv88e6xxx_port_set_message_port(chip, port, message);
2058 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2060 struct dsa_switch *ds = chip->ds;
2063 /* Upstream ports flood frames with unknown unicast or multicast DA */
2064 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2065 if (chip->info->ops->port_set_egress_floods)
2066 return chip->info->ops->port_set_egress_floods(chip, port,
2072 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2075 if (chip->info->ops->serdes_power)
2076 return chip->info->ops->serdes_power(chip, port, on);
2081 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2083 struct dsa_switch *ds = chip->ds;
2087 upstream_port = dsa_upstream_port(ds, port);
2088 if (chip->info->ops->port_set_upstream_port) {
2089 err = chip->info->ops->port_set_upstream_port(chip, port,
2095 if (port == upstream_port) {
2096 if (chip->info->ops->set_cpu_port) {
2097 err = chip->info->ops->set_cpu_port(chip,
2103 if (chip->info->ops->set_egress_port) {
2104 err = chip->info->ops->set_egress_port(chip,
2114 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2116 struct dsa_switch *ds = chip->ds;
2120 chip->ports[port].chip = chip;
2121 chip->ports[port].port = port;
2123 /* MAC Forcing register: don't force link, speed, duplex or flow control
2124 * state to any particular values on physical ports, but force the CPU
2125 * port and all DSA ports to their maximum bandwidth and full duplex.
2127 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2128 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2129 SPEED_MAX, DUPLEX_FULL,
2131 PHY_INTERFACE_MODE_NA);
2133 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2134 SPEED_UNFORCED, DUPLEX_UNFORCED,
2136 PHY_INTERFACE_MODE_NA);
2140 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2141 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2142 * tunneling, determine priority by looking at 802.1p and IP
2143 * priority fields (IP prio has precedence), and set STP state
2146 * If this is the CPU link, use DSA or EDSA tagging depending
2147 * on which tagging mode was configured.
2149 * If this is a link to another switch, use DSA tagging mode.
2151 * If this is the upstream port for this switch, enable
2152 * forwarding of unknown unicasts and multicasts.
2154 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2155 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2156 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2157 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2161 err = mv88e6xxx_setup_port_mode(chip, port);
2165 err = mv88e6xxx_setup_egress_floods(chip, port);
2169 /* Enable the SERDES interface for DSA and CPU ports. Normal
2170 * ports SERDES are enabled when the port is enabled, thus
2171 * saving a bit of power.
2173 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
2174 err = mv88e6xxx_serdes_power(chip, port, true);
2179 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2180 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2181 * untagged frames on this port, do a destination address lookup on all
2182 * received packets as usual, disable ARP mirroring and don't send a
2183 * copy of all transmitted/received frames on this port to the CPU.
2185 err = mv88e6xxx_port_set_map_da(chip, port);
2189 err = mv88e6xxx_setup_upstream_port(chip, port);
2193 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2194 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2198 if (chip->info->ops->port_set_jumbo_size) {
2199 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2204 /* Port Association Vector: when learning source addresses
2205 * of packets, add the address to the address database using
2206 * a port bitmap that has only the bit for this port set and
2207 * the other bits clear.
2210 /* Disable learning for CPU port */
2211 if (dsa_is_cpu_port(ds, port))
2214 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2219 /* Egress rate control 2: disable egress rate control. */
2220 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2225 if (chip->info->ops->port_pause_limit) {
2226 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2231 if (chip->info->ops->port_disable_learn_limit) {
2232 err = chip->info->ops->port_disable_learn_limit(chip, port);
2237 if (chip->info->ops->port_disable_pri_override) {
2238 err = chip->info->ops->port_disable_pri_override(chip, port);
2243 if (chip->info->ops->port_tag_remap) {
2244 err = chip->info->ops->port_tag_remap(chip, port);
2249 if (chip->info->ops->port_egress_rate_limiting) {
2250 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2255 err = mv88e6xxx_setup_message_port(chip, port);
2259 /* Port based VLAN map: give each port the same default address
2260 * database, and allow bidirectional communication between the
2261 * CPU and DSA port(s), and the other ports.
2263 err = mv88e6xxx_port_set_fid(chip, port, 0);
2267 err = mv88e6xxx_port_vlan_map(chip, port);
2271 /* Default VLAN ID and priority: don't set a default VLAN
2272 * ID, and set the default packet priority to zero.
2274 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2277 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2278 struct phy_device *phydev)
2280 struct mv88e6xxx_chip *chip = ds->priv;
2283 mv88e6xxx_reg_lock(chip);
2285 err = mv88e6xxx_serdes_power(chip, port, true);
2287 if (!err && chip->info->ops->serdes_irq_setup)
2288 err = chip->info->ops->serdes_irq_setup(chip, port);
2290 mv88e6xxx_reg_unlock(chip);
2295 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2297 struct mv88e6xxx_chip *chip = ds->priv;
2299 mv88e6xxx_reg_lock(chip);
2301 if (mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED))
2302 dev_err(chip->dev, "failed to disable port\n");
2304 if (chip->info->ops->serdes_irq_free)
2305 chip->info->ops->serdes_irq_free(chip, port);
2307 if (mv88e6xxx_serdes_power(chip, port, false))
2308 dev_err(chip->dev, "failed to power off SERDES\n");
2310 mv88e6xxx_reg_unlock(chip);
2313 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2314 unsigned int ageing_time)
2316 struct mv88e6xxx_chip *chip = ds->priv;
2319 mv88e6xxx_reg_lock(chip);
2320 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2321 mv88e6xxx_reg_unlock(chip);
2326 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2330 /* Initialize the statistics unit */
2331 if (chip->info->ops->stats_set_histogram) {
2332 err = chip->info->ops->stats_set_histogram(chip);
2337 return mv88e6xxx_g1_stats_clear(chip);
2340 /* The mv88e6390 has some hidden registers used for debug and
2341 * development. The errata also makes use of them.
2343 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2349 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2350 PORT_RESERVED_1A, val);
2354 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE |
2355 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2358 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2359 PORT_RESERVED_1A, ctrl);
2362 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2364 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2365 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2369 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2375 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ |
2376 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2379 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2380 PORT_RESERVED_1A, ctrl);
2384 err = mv88e6390_hidden_wait(chip);
2388 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2389 PORT_RESERVED_1A, val);
2392 /* Check if the errata has already been applied. */
2393 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2399 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2400 err = mv88e6390_hidden_read(chip, port, 0, &val);
2403 "Error reading hidden register: %d\n", err);
2413 /* The 6390 copper ports have an errata which require poking magic
2414 * values into undocumented hidden registers and then performing a
2417 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2422 if (mv88e6390_setup_errata_applied(chip))
2425 /* Set the ports into blocking mode */
2426 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2427 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2432 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2433 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
2438 return mv88e6xxx_software_reset(chip);
2441 static int mv88e6xxx_setup(struct dsa_switch *ds)
2443 struct mv88e6xxx_chip *chip = ds->priv;
2449 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2451 mv88e6xxx_reg_lock(chip);
2453 if (chip->info->ops->setup_errata) {
2454 err = chip->info->ops->setup_errata(chip);
2459 /* Cache the cmode of each port. */
2460 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2461 if (chip->info->ops->port_get_cmode) {
2462 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2466 chip->ports[i].cmode = cmode;
2470 /* Setup Switch Port Registers */
2471 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2472 if (dsa_is_unused_port(ds, i)) {
2473 err = mv88e6xxx_port_set_state(chip, i,
2478 err = mv88e6xxx_serdes_power(chip, i, false);
2485 err = mv88e6xxx_setup_port(chip, i);
2490 err = mv88e6xxx_irl_setup(chip);
2494 err = mv88e6xxx_mac_setup(chip);
2498 err = mv88e6xxx_phy_setup(chip);
2502 err = mv88e6xxx_vtu_setup(chip);
2506 err = mv88e6xxx_pvt_setup(chip);
2510 err = mv88e6xxx_atu_setup(chip);
2514 err = mv88e6xxx_broadcast_setup(chip, 0);
2518 err = mv88e6xxx_pot_setup(chip);
2522 err = mv88e6xxx_rmu_setup(chip);
2526 err = mv88e6xxx_rsvd2cpu_setup(chip);
2530 err = mv88e6xxx_trunk_setup(chip);
2534 err = mv88e6xxx_devmap_setup(chip);
2538 err = mv88e6xxx_pri_setup(chip);
2542 /* Setup PTP Hardware Clock and timestamping */
2543 if (chip->info->ptp_support) {
2544 err = mv88e6xxx_ptp_setup(chip);
2548 err = mv88e6xxx_hwtstamp_setup(chip);
2553 err = mv88e6xxx_stats_setup(chip);
2558 mv88e6xxx_reg_unlock(chip);
2563 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2565 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2566 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2570 if (!chip->info->ops->phy_read)
2573 mv88e6xxx_reg_lock(chip);
2574 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2575 mv88e6xxx_reg_unlock(chip);
2577 if (reg == MII_PHYSID2) {
2578 /* Some internal PHYs don't have a model number. */
2579 if (chip->info->family != MV88E6XXX_FAMILY_6165)
2580 /* Then there is the 6165 family. It gets is
2581 * PHYs correct. But it can also have two
2582 * SERDES interfaces in the PHY address
2583 * space. And these don't have a model
2584 * number. But they are not PHYs, so we don't
2585 * want to give them something a PHY driver
2588 * Use the mv88e6390 family model number
2589 * instead, for anything which really could be
2593 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2596 return err ? err : val;
2599 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2601 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2602 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2605 if (!chip->info->ops->phy_write)
2608 mv88e6xxx_reg_lock(chip);
2609 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2610 mv88e6xxx_reg_unlock(chip);
2615 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2616 struct device_node *np,
2620 struct mv88e6xxx_mdio_bus *mdio_bus;
2621 struct mii_bus *bus;
2625 mv88e6xxx_reg_lock(chip);
2626 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2627 mv88e6xxx_reg_unlock(chip);
2633 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2637 mdio_bus = bus->priv;
2638 mdio_bus->bus = bus;
2639 mdio_bus->chip = chip;
2640 INIT_LIST_HEAD(&mdio_bus->list);
2641 mdio_bus->external = external;
2644 bus->name = np->full_name;
2645 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2647 bus->name = "mv88e6xxx SMI";
2648 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2651 bus->read = mv88e6xxx_mdio_read;
2652 bus->write = mv88e6xxx_mdio_write;
2653 bus->parent = chip->dev;
2656 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2661 err = of_mdiobus_register(bus, np);
2663 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2664 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2669 list_add_tail(&mdio_bus->list, &chip->mdios);
2671 list_add(&mdio_bus->list, &chip->mdios);
2676 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2677 { .compatible = "marvell,mv88e6xxx-mdio-external",
2678 .data = (void *)true },
2682 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2685 struct mv88e6xxx_mdio_bus *mdio_bus;
2686 struct mii_bus *bus;
2688 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2689 bus = mdio_bus->bus;
2691 if (!mdio_bus->external)
2692 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2694 mdiobus_unregister(bus);
2698 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2699 struct device_node *np)
2701 const struct of_device_id *match;
2702 struct device_node *child;
2705 /* Always register one mdio bus for the internal/default mdio
2706 * bus. This maybe represented in the device tree, but is
2709 child = of_get_child_by_name(np, "mdio");
2710 err = mv88e6xxx_mdio_register(chip, child, false);
2714 /* Walk the device tree, and see if there are any other nodes
2715 * which say they are compatible with the external mdio
2718 for_each_available_child_of_node(np, child) {
2719 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2721 err = mv88e6xxx_mdio_register(chip, child, true);
2723 mv88e6xxx_mdios_unregister(chip);
2732 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2734 struct mv88e6xxx_chip *chip = ds->priv;
2736 return chip->eeprom_len;
2739 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2740 struct ethtool_eeprom *eeprom, u8 *data)
2742 struct mv88e6xxx_chip *chip = ds->priv;
2745 if (!chip->info->ops->get_eeprom)
2748 mv88e6xxx_reg_lock(chip);
2749 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2750 mv88e6xxx_reg_unlock(chip);
2755 eeprom->magic = 0xc3ec4951;
2760 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2761 struct ethtool_eeprom *eeprom, u8 *data)
2763 struct mv88e6xxx_chip *chip = ds->priv;
2766 if (!chip->info->ops->set_eeprom)
2769 if (eeprom->magic != 0xc3ec4951)
2772 mv88e6xxx_reg_lock(chip);
2773 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2774 mv88e6xxx_reg_unlock(chip);
2779 static const struct mv88e6xxx_ops mv88e6085_ops = {
2780 /* MV88E6XXX_FAMILY_6097 */
2781 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2782 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2783 .irl_init_all = mv88e6352_g2_irl_init_all,
2784 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2785 .phy_read = mv88e6185_phy_ppu_read,
2786 .phy_write = mv88e6185_phy_ppu_write,
2787 .port_set_link = mv88e6xxx_port_set_link,
2788 .port_set_duplex = mv88e6xxx_port_set_duplex,
2789 .port_set_speed = mv88e6185_port_set_speed,
2790 .port_tag_remap = mv88e6095_port_tag_remap,
2791 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2792 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2793 .port_set_ether_type = mv88e6351_port_set_ether_type,
2794 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2795 .port_pause_limit = mv88e6097_port_pause_limit,
2796 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2797 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2798 .port_link_state = mv88e6352_port_link_state,
2799 .port_get_cmode = mv88e6185_port_get_cmode,
2800 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2801 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2802 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2803 .stats_get_strings = mv88e6095_stats_get_strings,
2804 .stats_get_stats = mv88e6095_stats_get_stats,
2805 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2806 .set_egress_port = mv88e6095_g1_set_egress_port,
2807 .watchdog_ops = &mv88e6097_watchdog_ops,
2808 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2809 .pot_clear = mv88e6xxx_g2_pot_clear,
2810 .ppu_enable = mv88e6185_g1_ppu_enable,
2811 .ppu_disable = mv88e6185_g1_ppu_disable,
2812 .reset = mv88e6185_g1_reset,
2813 .rmu_disable = mv88e6085_g1_rmu_disable,
2814 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2815 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2816 .phylink_validate = mv88e6185_phylink_validate,
2819 static const struct mv88e6xxx_ops mv88e6095_ops = {
2820 /* MV88E6XXX_FAMILY_6095 */
2821 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2822 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2823 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2824 .phy_read = mv88e6185_phy_ppu_read,
2825 .phy_write = mv88e6185_phy_ppu_write,
2826 .port_set_link = mv88e6xxx_port_set_link,
2827 .port_set_duplex = mv88e6xxx_port_set_duplex,
2828 .port_set_speed = mv88e6185_port_set_speed,
2829 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2830 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2831 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2832 .port_link_state = mv88e6185_port_link_state,
2833 .port_get_cmode = mv88e6185_port_get_cmode,
2834 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2835 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2836 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2837 .stats_get_strings = mv88e6095_stats_get_strings,
2838 .stats_get_stats = mv88e6095_stats_get_stats,
2839 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2840 .ppu_enable = mv88e6185_g1_ppu_enable,
2841 .ppu_disable = mv88e6185_g1_ppu_disable,
2842 .reset = mv88e6185_g1_reset,
2843 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2844 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2845 .phylink_validate = mv88e6185_phylink_validate,
2848 static const struct mv88e6xxx_ops mv88e6097_ops = {
2849 /* MV88E6XXX_FAMILY_6097 */
2850 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2851 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2852 .irl_init_all = mv88e6352_g2_irl_init_all,
2853 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2854 .phy_read = mv88e6xxx_g2_smi_phy_read,
2855 .phy_write = mv88e6xxx_g2_smi_phy_write,
2856 .port_set_link = mv88e6xxx_port_set_link,
2857 .port_set_duplex = mv88e6xxx_port_set_duplex,
2858 .port_set_speed = mv88e6185_port_set_speed,
2859 .port_tag_remap = mv88e6095_port_tag_remap,
2860 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2861 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2862 .port_set_ether_type = mv88e6351_port_set_ether_type,
2863 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2864 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2865 .port_pause_limit = mv88e6097_port_pause_limit,
2866 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2867 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2868 .port_link_state = mv88e6352_port_link_state,
2869 .port_get_cmode = mv88e6185_port_get_cmode,
2870 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2871 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2872 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2873 .stats_get_strings = mv88e6095_stats_get_strings,
2874 .stats_get_stats = mv88e6095_stats_get_stats,
2875 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2876 .set_egress_port = mv88e6095_g1_set_egress_port,
2877 .watchdog_ops = &mv88e6097_watchdog_ops,
2878 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2879 .pot_clear = mv88e6xxx_g2_pot_clear,
2880 .reset = mv88e6352_g1_reset,
2881 .rmu_disable = mv88e6085_g1_rmu_disable,
2882 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2883 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2884 .phylink_validate = mv88e6185_phylink_validate,
2887 static const struct mv88e6xxx_ops mv88e6123_ops = {
2888 /* MV88E6XXX_FAMILY_6165 */
2889 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2890 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2891 .irl_init_all = mv88e6352_g2_irl_init_all,
2892 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2893 .phy_read = mv88e6xxx_g2_smi_phy_read,
2894 .phy_write = mv88e6xxx_g2_smi_phy_write,
2895 .port_set_link = mv88e6xxx_port_set_link,
2896 .port_set_duplex = mv88e6xxx_port_set_duplex,
2897 .port_set_speed = mv88e6185_port_set_speed,
2898 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2899 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2900 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2901 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2902 .port_link_state = mv88e6352_port_link_state,
2903 .port_get_cmode = mv88e6185_port_get_cmode,
2904 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2905 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2906 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2907 .stats_get_strings = mv88e6095_stats_get_strings,
2908 .stats_get_stats = mv88e6095_stats_get_stats,
2909 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2910 .set_egress_port = mv88e6095_g1_set_egress_port,
2911 .watchdog_ops = &mv88e6097_watchdog_ops,
2912 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2913 .pot_clear = mv88e6xxx_g2_pot_clear,
2914 .reset = mv88e6352_g1_reset,
2915 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2916 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2917 .phylink_validate = mv88e6185_phylink_validate,
2920 static const struct mv88e6xxx_ops mv88e6131_ops = {
2921 /* MV88E6XXX_FAMILY_6185 */
2922 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2923 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2924 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2925 .phy_read = mv88e6185_phy_ppu_read,
2926 .phy_write = mv88e6185_phy_ppu_write,
2927 .port_set_link = mv88e6xxx_port_set_link,
2928 .port_set_duplex = mv88e6xxx_port_set_duplex,
2929 .port_set_speed = mv88e6185_port_set_speed,
2930 .port_tag_remap = mv88e6095_port_tag_remap,
2931 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2932 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2933 .port_set_ether_type = mv88e6351_port_set_ether_type,
2934 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2935 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2936 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2937 .port_pause_limit = mv88e6097_port_pause_limit,
2938 .port_set_pause = mv88e6185_port_set_pause,
2939 .port_link_state = mv88e6352_port_link_state,
2940 .port_get_cmode = mv88e6185_port_get_cmode,
2941 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2942 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2943 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2944 .stats_get_strings = mv88e6095_stats_get_strings,
2945 .stats_get_stats = mv88e6095_stats_get_stats,
2946 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2947 .set_egress_port = mv88e6095_g1_set_egress_port,
2948 .watchdog_ops = &mv88e6097_watchdog_ops,
2949 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2950 .ppu_enable = mv88e6185_g1_ppu_enable,
2951 .set_cascade_port = mv88e6185_g1_set_cascade_port,
2952 .ppu_disable = mv88e6185_g1_ppu_disable,
2953 .reset = mv88e6185_g1_reset,
2954 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2955 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2956 .phylink_validate = mv88e6185_phylink_validate,
2959 static const struct mv88e6xxx_ops mv88e6141_ops = {
2960 /* MV88E6XXX_FAMILY_6341 */
2961 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2962 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2963 .irl_init_all = mv88e6352_g2_irl_init_all,
2964 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2965 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2966 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2967 .phy_read = mv88e6xxx_g2_smi_phy_read,
2968 .phy_write = mv88e6xxx_g2_smi_phy_write,
2969 .port_set_link = mv88e6xxx_port_set_link,
2970 .port_set_duplex = mv88e6xxx_port_set_duplex,
2971 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2972 .port_set_speed = mv88e6341_port_set_speed,
2973 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
2974 .port_tag_remap = mv88e6095_port_tag_remap,
2975 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2976 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2977 .port_set_ether_type = mv88e6351_port_set_ether_type,
2978 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2979 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2980 .port_pause_limit = mv88e6097_port_pause_limit,
2981 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2982 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2983 .port_link_state = mv88e6352_port_link_state,
2984 .port_get_cmode = mv88e6352_port_get_cmode,
2985 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2986 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2987 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2988 .stats_get_strings = mv88e6320_stats_get_strings,
2989 .stats_get_stats = mv88e6390_stats_get_stats,
2990 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2991 .set_egress_port = mv88e6390_g1_set_egress_port,
2992 .watchdog_ops = &mv88e6390_watchdog_ops,
2993 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2994 .pot_clear = mv88e6xxx_g2_pot_clear,
2995 .reset = mv88e6352_g1_reset,
2996 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2997 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2998 .serdes_power = mv88e6341_serdes_power,
2999 .gpio_ops = &mv88e6352_gpio_ops,
3000 .phylink_validate = mv88e6341_phylink_validate,
3003 static const struct mv88e6xxx_ops mv88e6161_ops = {
3004 /* MV88E6XXX_FAMILY_6165 */
3005 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3006 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3007 .irl_init_all = mv88e6352_g2_irl_init_all,
3008 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3009 .phy_read = mv88e6xxx_g2_smi_phy_read,
3010 .phy_write = mv88e6xxx_g2_smi_phy_write,
3011 .port_set_link = mv88e6xxx_port_set_link,
3012 .port_set_duplex = mv88e6xxx_port_set_duplex,
3013 .port_set_speed = mv88e6185_port_set_speed,
3014 .port_tag_remap = mv88e6095_port_tag_remap,
3015 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3016 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3017 .port_set_ether_type = mv88e6351_port_set_ether_type,
3018 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3019 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3020 .port_pause_limit = mv88e6097_port_pause_limit,
3021 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3022 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3023 .port_link_state = mv88e6352_port_link_state,
3024 .port_get_cmode = mv88e6185_port_get_cmode,
3025 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3026 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3027 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3028 .stats_get_strings = mv88e6095_stats_get_strings,
3029 .stats_get_stats = mv88e6095_stats_get_stats,
3030 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3031 .set_egress_port = mv88e6095_g1_set_egress_port,
3032 .watchdog_ops = &mv88e6097_watchdog_ops,
3033 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3034 .pot_clear = mv88e6xxx_g2_pot_clear,
3035 .reset = mv88e6352_g1_reset,
3036 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3037 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3038 .avb_ops = &mv88e6165_avb_ops,
3039 .ptp_ops = &mv88e6165_ptp_ops,
3040 .phylink_validate = mv88e6185_phylink_validate,
3043 static const struct mv88e6xxx_ops mv88e6165_ops = {
3044 /* MV88E6XXX_FAMILY_6165 */
3045 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3046 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3047 .irl_init_all = mv88e6352_g2_irl_init_all,
3048 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3049 .phy_read = mv88e6165_phy_read,
3050 .phy_write = mv88e6165_phy_write,
3051 .port_set_link = mv88e6xxx_port_set_link,
3052 .port_set_duplex = mv88e6xxx_port_set_duplex,
3053 .port_set_speed = mv88e6185_port_set_speed,
3054 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3055 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3056 .port_link_state = mv88e6352_port_link_state,
3057 .port_get_cmode = mv88e6185_port_get_cmode,
3058 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3059 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3060 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3061 .stats_get_strings = mv88e6095_stats_get_strings,
3062 .stats_get_stats = mv88e6095_stats_get_stats,
3063 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3064 .set_egress_port = mv88e6095_g1_set_egress_port,
3065 .watchdog_ops = &mv88e6097_watchdog_ops,
3066 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3067 .pot_clear = mv88e6xxx_g2_pot_clear,
3068 .reset = mv88e6352_g1_reset,
3069 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3070 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3071 .avb_ops = &mv88e6165_avb_ops,
3072 .ptp_ops = &mv88e6165_ptp_ops,
3073 .phylink_validate = mv88e6185_phylink_validate,
3076 static const struct mv88e6xxx_ops mv88e6171_ops = {
3077 /* MV88E6XXX_FAMILY_6351 */
3078 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3079 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3080 .irl_init_all = mv88e6352_g2_irl_init_all,
3081 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3082 .phy_read = mv88e6xxx_g2_smi_phy_read,
3083 .phy_write = mv88e6xxx_g2_smi_phy_write,
3084 .port_set_link = mv88e6xxx_port_set_link,
3085 .port_set_duplex = mv88e6xxx_port_set_duplex,
3086 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3087 .port_set_speed = mv88e6185_port_set_speed,
3088 .port_tag_remap = mv88e6095_port_tag_remap,
3089 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3090 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3091 .port_set_ether_type = mv88e6351_port_set_ether_type,
3092 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3093 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3094 .port_pause_limit = mv88e6097_port_pause_limit,
3095 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3096 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3097 .port_link_state = mv88e6352_port_link_state,
3098 .port_get_cmode = mv88e6352_port_get_cmode,
3099 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3100 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3101 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3102 .stats_get_strings = mv88e6095_stats_get_strings,
3103 .stats_get_stats = mv88e6095_stats_get_stats,
3104 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3105 .set_egress_port = mv88e6095_g1_set_egress_port,
3106 .watchdog_ops = &mv88e6097_watchdog_ops,
3107 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3108 .pot_clear = mv88e6xxx_g2_pot_clear,
3109 .reset = mv88e6352_g1_reset,
3110 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3111 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3112 .phylink_validate = mv88e6185_phylink_validate,
3115 static const struct mv88e6xxx_ops mv88e6172_ops = {
3116 /* MV88E6XXX_FAMILY_6352 */
3117 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3118 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3119 .irl_init_all = mv88e6352_g2_irl_init_all,
3120 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3121 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3122 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3123 .phy_read = mv88e6xxx_g2_smi_phy_read,
3124 .phy_write = mv88e6xxx_g2_smi_phy_write,
3125 .port_set_link = mv88e6xxx_port_set_link,
3126 .port_set_duplex = mv88e6xxx_port_set_duplex,
3127 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3128 .port_set_speed = mv88e6352_port_set_speed,
3129 .port_tag_remap = mv88e6095_port_tag_remap,
3130 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3131 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3132 .port_set_ether_type = mv88e6351_port_set_ether_type,
3133 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3134 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3135 .port_pause_limit = mv88e6097_port_pause_limit,
3136 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3137 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3138 .port_link_state = mv88e6352_port_link_state,
3139 .port_get_cmode = mv88e6352_port_get_cmode,
3140 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3141 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3142 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3143 .stats_get_strings = mv88e6095_stats_get_strings,
3144 .stats_get_stats = mv88e6095_stats_get_stats,
3145 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3146 .set_egress_port = mv88e6095_g1_set_egress_port,
3147 .watchdog_ops = &mv88e6097_watchdog_ops,
3148 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3149 .pot_clear = mv88e6xxx_g2_pot_clear,
3150 .reset = mv88e6352_g1_reset,
3151 .rmu_disable = mv88e6352_g1_rmu_disable,
3152 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3153 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3154 .serdes_power = mv88e6352_serdes_power,
3155 .gpio_ops = &mv88e6352_gpio_ops,
3156 .phylink_validate = mv88e6352_phylink_validate,
3159 static const struct mv88e6xxx_ops mv88e6175_ops = {
3160 /* MV88E6XXX_FAMILY_6351 */
3161 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3162 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3163 .irl_init_all = mv88e6352_g2_irl_init_all,
3164 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3165 .phy_read = mv88e6xxx_g2_smi_phy_read,
3166 .phy_write = mv88e6xxx_g2_smi_phy_write,
3167 .port_set_link = mv88e6xxx_port_set_link,
3168 .port_set_duplex = mv88e6xxx_port_set_duplex,
3169 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3170 .port_set_speed = mv88e6185_port_set_speed,
3171 .port_tag_remap = mv88e6095_port_tag_remap,
3172 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3173 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3174 .port_set_ether_type = mv88e6351_port_set_ether_type,
3175 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3176 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3177 .port_pause_limit = mv88e6097_port_pause_limit,
3178 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3179 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3180 .port_link_state = mv88e6352_port_link_state,
3181 .port_get_cmode = mv88e6352_port_get_cmode,
3182 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3183 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3184 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3185 .stats_get_strings = mv88e6095_stats_get_strings,
3186 .stats_get_stats = mv88e6095_stats_get_stats,
3187 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3188 .set_egress_port = mv88e6095_g1_set_egress_port,
3189 .watchdog_ops = &mv88e6097_watchdog_ops,
3190 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3191 .pot_clear = mv88e6xxx_g2_pot_clear,
3192 .reset = mv88e6352_g1_reset,
3193 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3194 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3195 .phylink_validate = mv88e6185_phylink_validate,
3198 static const struct mv88e6xxx_ops mv88e6176_ops = {
3199 /* MV88E6XXX_FAMILY_6352 */
3200 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3201 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3202 .irl_init_all = mv88e6352_g2_irl_init_all,
3203 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3204 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3205 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3206 .phy_read = mv88e6xxx_g2_smi_phy_read,
3207 .phy_write = mv88e6xxx_g2_smi_phy_write,
3208 .port_set_link = mv88e6xxx_port_set_link,
3209 .port_set_duplex = mv88e6xxx_port_set_duplex,
3210 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3211 .port_set_speed = mv88e6352_port_set_speed,
3212 .port_tag_remap = mv88e6095_port_tag_remap,
3213 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3214 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3215 .port_set_ether_type = mv88e6351_port_set_ether_type,
3216 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3217 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3218 .port_pause_limit = mv88e6097_port_pause_limit,
3219 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3220 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3221 .port_link_state = mv88e6352_port_link_state,
3222 .port_get_cmode = mv88e6352_port_get_cmode,
3223 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3224 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3225 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3226 .stats_get_strings = mv88e6095_stats_get_strings,
3227 .stats_get_stats = mv88e6095_stats_get_stats,
3228 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3229 .set_egress_port = mv88e6095_g1_set_egress_port,
3230 .watchdog_ops = &mv88e6097_watchdog_ops,
3231 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3232 .pot_clear = mv88e6xxx_g2_pot_clear,
3233 .reset = mv88e6352_g1_reset,
3234 .rmu_disable = mv88e6352_g1_rmu_disable,
3235 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3236 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3237 .serdes_power = mv88e6352_serdes_power,
3238 .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3239 .serdes_irq_free = mv88e6352_serdes_irq_free,
3240 .gpio_ops = &mv88e6352_gpio_ops,
3241 .phylink_validate = mv88e6352_phylink_validate,
3244 static const struct mv88e6xxx_ops mv88e6185_ops = {
3245 /* MV88E6XXX_FAMILY_6185 */
3246 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3247 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3248 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3249 .phy_read = mv88e6185_phy_ppu_read,
3250 .phy_write = mv88e6185_phy_ppu_write,
3251 .port_set_link = mv88e6xxx_port_set_link,
3252 .port_set_duplex = mv88e6xxx_port_set_duplex,
3253 .port_set_speed = mv88e6185_port_set_speed,
3254 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3255 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3256 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3257 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3258 .port_set_pause = mv88e6185_port_set_pause,
3259 .port_link_state = mv88e6185_port_link_state,
3260 .port_get_cmode = mv88e6185_port_get_cmode,
3261 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3262 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3263 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3264 .stats_get_strings = mv88e6095_stats_get_strings,
3265 .stats_get_stats = mv88e6095_stats_get_stats,
3266 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3267 .set_egress_port = mv88e6095_g1_set_egress_port,
3268 .watchdog_ops = &mv88e6097_watchdog_ops,
3269 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3270 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3271 .ppu_enable = mv88e6185_g1_ppu_enable,
3272 .ppu_disable = mv88e6185_g1_ppu_disable,
3273 .reset = mv88e6185_g1_reset,
3274 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3275 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3276 .phylink_validate = mv88e6185_phylink_validate,
3279 static const struct mv88e6xxx_ops mv88e6190_ops = {
3280 /* MV88E6XXX_FAMILY_6390 */
3281 .setup_errata = mv88e6390_setup_errata,
3282 .irl_init_all = mv88e6390_g2_irl_init_all,
3283 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3284 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3285 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3286 .phy_read = mv88e6xxx_g2_smi_phy_read,
3287 .phy_write = mv88e6xxx_g2_smi_phy_write,
3288 .port_set_link = mv88e6xxx_port_set_link,
3289 .port_set_duplex = mv88e6xxx_port_set_duplex,
3290 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3291 .port_set_speed = mv88e6390_port_set_speed,
3292 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3293 .port_tag_remap = mv88e6390_port_tag_remap,
3294 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3295 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3296 .port_set_ether_type = mv88e6351_port_set_ether_type,
3297 .port_pause_limit = mv88e6390_port_pause_limit,
3298 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3299 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3300 .port_link_state = mv88e6352_port_link_state,
3301 .port_get_cmode = mv88e6352_port_get_cmode,
3302 .port_set_cmode = mv88e6390_port_set_cmode,
3303 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3304 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3305 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3306 .stats_get_strings = mv88e6320_stats_get_strings,
3307 .stats_get_stats = mv88e6390_stats_get_stats,
3308 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3309 .set_egress_port = mv88e6390_g1_set_egress_port,
3310 .watchdog_ops = &mv88e6390_watchdog_ops,
3311 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3312 .pot_clear = mv88e6xxx_g2_pot_clear,
3313 .reset = mv88e6352_g1_reset,
3314 .rmu_disable = mv88e6390_g1_rmu_disable,
3315 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3316 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3317 .serdes_power = mv88e6390_serdes_power,
3318 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3319 .serdes_irq_free = mv88e6390_serdes_irq_free,
3320 .gpio_ops = &mv88e6352_gpio_ops,
3321 .phylink_validate = mv88e6390_phylink_validate,
3324 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3325 /* MV88E6XXX_FAMILY_6390 */
3326 .setup_errata = mv88e6390_setup_errata,
3327 .irl_init_all = mv88e6390_g2_irl_init_all,
3328 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3329 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3330 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3331 .phy_read = mv88e6xxx_g2_smi_phy_read,
3332 .phy_write = mv88e6xxx_g2_smi_phy_write,
3333 .port_set_link = mv88e6xxx_port_set_link,
3334 .port_set_duplex = mv88e6xxx_port_set_duplex,
3335 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3336 .port_set_speed = mv88e6390x_port_set_speed,
3337 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3338 .port_tag_remap = mv88e6390_port_tag_remap,
3339 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3340 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3341 .port_set_ether_type = mv88e6351_port_set_ether_type,
3342 .port_pause_limit = mv88e6390_port_pause_limit,
3343 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3344 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3345 .port_link_state = mv88e6352_port_link_state,
3346 .port_get_cmode = mv88e6352_port_get_cmode,
3347 .port_set_cmode = mv88e6390x_port_set_cmode,
3348 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3349 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3350 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3351 .stats_get_strings = mv88e6320_stats_get_strings,
3352 .stats_get_stats = mv88e6390_stats_get_stats,
3353 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3354 .set_egress_port = mv88e6390_g1_set_egress_port,
3355 .watchdog_ops = &mv88e6390_watchdog_ops,
3356 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3357 .pot_clear = mv88e6xxx_g2_pot_clear,
3358 .reset = mv88e6352_g1_reset,
3359 .rmu_disable = mv88e6390_g1_rmu_disable,
3360 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3361 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3362 .serdes_power = mv88e6390x_serdes_power,
3363 .serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3364 .serdes_irq_free = mv88e6390x_serdes_irq_free,
3365 .gpio_ops = &mv88e6352_gpio_ops,
3366 .phylink_validate = mv88e6390x_phylink_validate,
3369 static const struct mv88e6xxx_ops mv88e6191_ops = {
3370 /* MV88E6XXX_FAMILY_6390 */
3371 .setup_errata = mv88e6390_setup_errata,
3372 .irl_init_all = mv88e6390_g2_irl_init_all,
3373 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3374 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3375 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3376 .phy_read = mv88e6xxx_g2_smi_phy_read,
3377 .phy_write = mv88e6xxx_g2_smi_phy_write,
3378 .port_set_link = mv88e6xxx_port_set_link,
3379 .port_set_duplex = mv88e6xxx_port_set_duplex,
3380 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3381 .port_set_speed = mv88e6390_port_set_speed,
3382 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3383 .port_tag_remap = mv88e6390_port_tag_remap,
3384 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3385 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3386 .port_set_ether_type = mv88e6351_port_set_ether_type,
3387 .port_pause_limit = mv88e6390_port_pause_limit,
3388 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3389 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3390 .port_link_state = mv88e6352_port_link_state,
3391 .port_get_cmode = mv88e6352_port_get_cmode,
3392 .port_set_cmode = mv88e6390_port_set_cmode,
3393 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3394 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3395 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3396 .stats_get_strings = mv88e6320_stats_get_strings,
3397 .stats_get_stats = mv88e6390_stats_get_stats,
3398 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3399 .set_egress_port = mv88e6390_g1_set_egress_port,
3400 .watchdog_ops = &mv88e6390_watchdog_ops,
3401 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3402 .pot_clear = mv88e6xxx_g2_pot_clear,
3403 .reset = mv88e6352_g1_reset,
3404 .rmu_disable = mv88e6390_g1_rmu_disable,
3405 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3406 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3407 .serdes_power = mv88e6390_serdes_power,
3408 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3409 .serdes_irq_free = mv88e6390_serdes_irq_free,
3410 .avb_ops = &mv88e6390_avb_ops,
3411 .ptp_ops = &mv88e6352_ptp_ops,
3412 .phylink_validate = mv88e6390_phylink_validate,
3415 static const struct mv88e6xxx_ops mv88e6240_ops = {
3416 /* MV88E6XXX_FAMILY_6352 */
3417 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3418 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3419 .irl_init_all = mv88e6352_g2_irl_init_all,
3420 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3421 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3422 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3423 .phy_read = mv88e6xxx_g2_smi_phy_read,
3424 .phy_write = mv88e6xxx_g2_smi_phy_write,
3425 .port_set_link = mv88e6xxx_port_set_link,
3426 .port_set_duplex = mv88e6xxx_port_set_duplex,
3427 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3428 .port_set_speed = mv88e6352_port_set_speed,
3429 .port_tag_remap = mv88e6095_port_tag_remap,
3430 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3431 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3432 .port_set_ether_type = mv88e6351_port_set_ether_type,
3433 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3434 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3435 .port_pause_limit = mv88e6097_port_pause_limit,
3436 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3437 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3438 .port_link_state = mv88e6352_port_link_state,
3439 .port_get_cmode = mv88e6352_port_get_cmode,
3440 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3441 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3442 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3443 .stats_get_strings = mv88e6095_stats_get_strings,
3444 .stats_get_stats = mv88e6095_stats_get_stats,
3445 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3446 .set_egress_port = mv88e6095_g1_set_egress_port,
3447 .watchdog_ops = &mv88e6097_watchdog_ops,
3448 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3449 .pot_clear = mv88e6xxx_g2_pot_clear,
3450 .reset = mv88e6352_g1_reset,
3451 .rmu_disable = mv88e6352_g1_rmu_disable,
3452 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3453 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3454 .serdes_power = mv88e6352_serdes_power,
3455 .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3456 .serdes_irq_free = mv88e6352_serdes_irq_free,
3457 .gpio_ops = &mv88e6352_gpio_ops,
3458 .avb_ops = &mv88e6352_avb_ops,
3459 .ptp_ops = &mv88e6352_ptp_ops,
3460 .phylink_validate = mv88e6352_phylink_validate,
3463 static const struct mv88e6xxx_ops mv88e6250_ops = {
3464 /* MV88E6XXX_FAMILY_6250 */
3465 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
3466 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3467 .irl_init_all = mv88e6352_g2_irl_init_all,
3468 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3469 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3470 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3471 .phy_read = mv88e6xxx_g2_smi_phy_read,
3472 .phy_write = mv88e6xxx_g2_smi_phy_write,
3473 .port_set_link = mv88e6xxx_port_set_link,
3474 .port_set_duplex = mv88e6xxx_port_set_duplex,
3475 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3476 .port_set_speed = mv88e6250_port_set_speed,
3477 .port_tag_remap = mv88e6095_port_tag_remap,
3478 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3479 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3480 .port_set_ether_type = mv88e6351_port_set_ether_type,
3481 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3482 .port_pause_limit = mv88e6097_port_pause_limit,
3483 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3484 .port_link_state = mv88e6250_port_link_state,
3485 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3486 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3487 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
3488 .stats_get_strings = mv88e6250_stats_get_strings,
3489 .stats_get_stats = mv88e6250_stats_get_stats,
3490 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3491 .set_egress_port = mv88e6095_g1_set_egress_port,
3492 .watchdog_ops = &mv88e6250_watchdog_ops,
3493 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3494 .pot_clear = mv88e6xxx_g2_pot_clear,
3495 .reset = mv88e6250_g1_reset,
3496 .vtu_getnext = mv88e6250_g1_vtu_getnext,
3497 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
3498 .phylink_validate = mv88e6065_phylink_validate,
3501 static const struct mv88e6xxx_ops mv88e6290_ops = {
3502 /* MV88E6XXX_FAMILY_6390 */
3503 .setup_errata = mv88e6390_setup_errata,
3504 .irl_init_all = mv88e6390_g2_irl_init_all,
3505 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3506 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3507 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3508 .phy_read = mv88e6xxx_g2_smi_phy_read,
3509 .phy_write = mv88e6xxx_g2_smi_phy_write,
3510 .port_set_link = mv88e6xxx_port_set_link,
3511 .port_set_duplex = mv88e6xxx_port_set_duplex,
3512 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3513 .port_set_speed = mv88e6390_port_set_speed,
3514 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3515 .port_tag_remap = mv88e6390_port_tag_remap,
3516 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3517 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3518 .port_set_ether_type = mv88e6351_port_set_ether_type,
3519 .port_pause_limit = mv88e6390_port_pause_limit,
3520 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3521 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3522 .port_link_state = mv88e6352_port_link_state,
3523 .port_get_cmode = mv88e6352_port_get_cmode,
3524 .port_set_cmode = mv88e6390_port_set_cmode,
3525 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3526 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3527 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3528 .stats_get_strings = mv88e6320_stats_get_strings,
3529 .stats_get_stats = mv88e6390_stats_get_stats,
3530 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3531 .set_egress_port = mv88e6390_g1_set_egress_port,
3532 .watchdog_ops = &mv88e6390_watchdog_ops,
3533 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3534 .pot_clear = mv88e6xxx_g2_pot_clear,
3535 .reset = mv88e6352_g1_reset,
3536 .rmu_disable = mv88e6390_g1_rmu_disable,
3537 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3538 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3539 .serdes_power = mv88e6390_serdes_power,
3540 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3541 .serdes_irq_free = mv88e6390_serdes_irq_free,
3542 .gpio_ops = &mv88e6352_gpio_ops,
3543 .avb_ops = &mv88e6390_avb_ops,
3544 .ptp_ops = &mv88e6352_ptp_ops,
3545 .phylink_validate = mv88e6390_phylink_validate,
3548 static const struct mv88e6xxx_ops mv88e6320_ops = {
3549 /* MV88E6XXX_FAMILY_6320 */
3550 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3551 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3552 .irl_init_all = mv88e6352_g2_irl_init_all,
3553 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3554 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3555 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3556 .phy_read = mv88e6xxx_g2_smi_phy_read,
3557 .phy_write = mv88e6xxx_g2_smi_phy_write,
3558 .port_set_link = mv88e6xxx_port_set_link,
3559 .port_set_duplex = mv88e6xxx_port_set_duplex,
3560 .port_set_speed = mv88e6185_port_set_speed,
3561 .port_tag_remap = mv88e6095_port_tag_remap,
3562 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3563 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3564 .port_set_ether_type = mv88e6351_port_set_ether_type,
3565 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3566 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3567 .port_pause_limit = mv88e6097_port_pause_limit,
3568 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3569 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3570 .port_link_state = mv88e6352_port_link_state,
3571 .port_get_cmode = mv88e6352_port_get_cmode,
3572 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3573 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3574 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3575 .stats_get_strings = mv88e6320_stats_get_strings,
3576 .stats_get_stats = mv88e6320_stats_get_stats,
3577 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3578 .set_egress_port = mv88e6095_g1_set_egress_port,
3579 .watchdog_ops = &mv88e6390_watchdog_ops,
3580 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3581 .pot_clear = mv88e6xxx_g2_pot_clear,
3582 .reset = mv88e6352_g1_reset,
3583 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3584 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3585 .gpio_ops = &mv88e6352_gpio_ops,
3586 .avb_ops = &mv88e6352_avb_ops,
3587 .ptp_ops = &mv88e6352_ptp_ops,
3588 .phylink_validate = mv88e6185_phylink_validate,
3591 static const struct mv88e6xxx_ops mv88e6321_ops = {
3592 /* MV88E6XXX_FAMILY_6320 */
3593 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3594 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3595 .irl_init_all = mv88e6352_g2_irl_init_all,
3596 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3597 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3598 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3599 .phy_read = mv88e6xxx_g2_smi_phy_read,
3600 .phy_write = mv88e6xxx_g2_smi_phy_write,
3601 .port_set_link = mv88e6xxx_port_set_link,
3602 .port_set_duplex = mv88e6xxx_port_set_duplex,
3603 .port_set_speed = mv88e6185_port_set_speed,
3604 .port_tag_remap = mv88e6095_port_tag_remap,
3605 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3606 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3607 .port_set_ether_type = mv88e6351_port_set_ether_type,
3608 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3609 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3610 .port_pause_limit = mv88e6097_port_pause_limit,
3611 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3612 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3613 .port_link_state = mv88e6352_port_link_state,
3614 .port_get_cmode = mv88e6352_port_get_cmode,
3615 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3616 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3617 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3618 .stats_get_strings = mv88e6320_stats_get_strings,
3619 .stats_get_stats = mv88e6320_stats_get_stats,
3620 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3621 .set_egress_port = mv88e6095_g1_set_egress_port,
3622 .watchdog_ops = &mv88e6390_watchdog_ops,
3623 .reset = mv88e6352_g1_reset,
3624 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3625 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3626 .gpio_ops = &mv88e6352_gpio_ops,
3627 .avb_ops = &mv88e6352_avb_ops,
3628 .ptp_ops = &mv88e6352_ptp_ops,
3629 .phylink_validate = mv88e6185_phylink_validate,
3632 static const struct mv88e6xxx_ops mv88e6341_ops = {
3633 /* MV88E6XXX_FAMILY_6341 */
3634 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3635 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3636 .irl_init_all = mv88e6352_g2_irl_init_all,
3637 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3638 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3639 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3640 .phy_read = mv88e6xxx_g2_smi_phy_read,
3641 .phy_write = mv88e6xxx_g2_smi_phy_write,
3642 .port_set_link = mv88e6xxx_port_set_link,
3643 .port_set_duplex = mv88e6xxx_port_set_duplex,
3644 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3645 .port_set_speed = mv88e6341_port_set_speed,
3646 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3647 .port_tag_remap = mv88e6095_port_tag_remap,
3648 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3649 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3650 .port_set_ether_type = mv88e6351_port_set_ether_type,
3651 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3652 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3653 .port_pause_limit = mv88e6097_port_pause_limit,
3654 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3655 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3656 .port_link_state = mv88e6352_port_link_state,
3657 .port_get_cmode = mv88e6352_port_get_cmode,
3658 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3659 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3660 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3661 .stats_get_strings = mv88e6320_stats_get_strings,
3662 .stats_get_stats = mv88e6390_stats_get_stats,
3663 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3664 .set_egress_port = mv88e6390_g1_set_egress_port,
3665 .watchdog_ops = &mv88e6390_watchdog_ops,
3666 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3667 .pot_clear = mv88e6xxx_g2_pot_clear,
3668 .reset = mv88e6352_g1_reset,
3669 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3670 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3671 .serdes_power = mv88e6341_serdes_power,
3672 .gpio_ops = &mv88e6352_gpio_ops,
3673 .avb_ops = &mv88e6390_avb_ops,
3674 .ptp_ops = &mv88e6352_ptp_ops,
3675 .phylink_validate = mv88e6341_phylink_validate,
3678 static const struct mv88e6xxx_ops mv88e6350_ops = {
3679 /* MV88E6XXX_FAMILY_6351 */
3680 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3681 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3682 .irl_init_all = mv88e6352_g2_irl_init_all,
3683 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3684 .phy_read = mv88e6xxx_g2_smi_phy_read,
3685 .phy_write = mv88e6xxx_g2_smi_phy_write,
3686 .port_set_link = mv88e6xxx_port_set_link,
3687 .port_set_duplex = mv88e6xxx_port_set_duplex,
3688 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3689 .port_set_speed = mv88e6185_port_set_speed,
3690 .port_tag_remap = mv88e6095_port_tag_remap,
3691 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3692 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3693 .port_set_ether_type = mv88e6351_port_set_ether_type,
3694 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3695 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3696 .port_pause_limit = mv88e6097_port_pause_limit,
3697 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3698 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3699 .port_link_state = mv88e6352_port_link_state,
3700 .port_get_cmode = mv88e6352_port_get_cmode,
3701 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3702 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3703 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3704 .stats_get_strings = mv88e6095_stats_get_strings,
3705 .stats_get_stats = mv88e6095_stats_get_stats,
3706 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3707 .set_egress_port = mv88e6095_g1_set_egress_port,
3708 .watchdog_ops = &mv88e6097_watchdog_ops,
3709 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3710 .pot_clear = mv88e6xxx_g2_pot_clear,
3711 .reset = mv88e6352_g1_reset,
3712 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3713 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3714 .phylink_validate = mv88e6185_phylink_validate,
3717 static const struct mv88e6xxx_ops mv88e6351_ops = {
3718 /* MV88E6XXX_FAMILY_6351 */
3719 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3720 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3721 .irl_init_all = mv88e6352_g2_irl_init_all,
3722 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3723 .phy_read = mv88e6xxx_g2_smi_phy_read,
3724 .phy_write = mv88e6xxx_g2_smi_phy_write,
3725 .port_set_link = mv88e6xxx_port_set_link,
3726 .port_set_duplex = mv88e6xxx_port_set_duplex,
3727 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3728 .port_set_speed = mv88e6185_port_set_speed,
3729 .port_tag_remap = mv88e6095_port_tag_remap,
3730 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3731 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3732 .port_set_ether_type = mv88e6351_port_set_ether_type,
3733 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3734 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3735 .port_pause_limit = mv88e6097_port_pause_limit,
3736 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3737 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3738 .port_link_state = mv88e6352_port_link_state,
3739 .port_get_cmode = mv88e6352_port_get_cmode,
3740 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3741 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3742 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3743 .stats_get_strings = mv88e6095_stats_get_strings,
3744 .stats_get_stats = mv88e6095_stats_get_stats,
3745 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3746 .set_egress_port = mv88e6095_g1_set_egress_port,
3747 .watchdog_ops = &mv88e6097_watchdog_ops,
3748 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3749 .pot_clear = mv88e6xxx_g2_pot_clear,
3750 .reset = mv88e6352_g1_reset,
3751 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3752 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3753 .avb_ops = &mv88e6352_avb_ops,
3754 .ptp_ops = &mv88e6352_ptp_ops,
3755 .phylink_validate = mv88e6185_phylink_validate,
3758 static const struct mv88e6xxx_ops mv88e6352_ops = {
3759 /* MV88E6XXX_FAMILY_6352 */
3760 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3761 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3762 .irl_init_all = mv88e6352_g2_irl_init_all,
3763 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3764 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3765 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3766 .phy_read = mv88e6xxx_g2_smi_phy_read,
3767 .phy_write = mv88e6xxx_g2_smi_phy_write,
3768 .port_set_link = mv88e6xxx_port_set_link,
3769 .port_set_duplex = mv88e6xxx_port_set_duplex,
3770 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3771 .port_set_speed = mv88e6352_port_set_speed,
3772 .port_tag_remap = mv88e6095_port_tag_remap,
3773 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3774 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3775 .port_set_ether_type = mv88e6351_port_set_ether_type,
3776 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3777 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3778 .port_pause_limit = mv88e6097_port_pause_limit,
3779 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3780 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3781 .port_link_state = mv88e6352_port_link_state,
3782 .port_get_cmode = mv88e6352_port_get_cmode,
3783 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3784 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3785 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3786 .stats_get_strings = mv88e6095_stats_get_strings,
3787 .stats_get_stats = mv88e6095_stats_get_stats,
3788 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3789 .set_egress_port = mv88e6095_g1_set_egress_port,
3790 .watchdog_ops = &mv88e6097_watchdog_ops,
3791 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3792 .pot_clear = mv88e6xxx_g2_pot_clear,
3793 .reset = mv88e6352_g1_reset,
3794 .rmu_disable = mv88e6352_g1_rmu_disable,
3795 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3796 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3797 .serdes_power = mv88e6352_serdes_power,
3798 .serdes_irq_setup = mv88e6352_serdes_irq_setup,
3799 .serdes_irq_free = mv88e6352_serdes_irq_free,
3800 .gpio_ops = &mv88e6352_gpio_ops,
3801 .avb_ops = &mv88e6352_avb_ops,
3802 .ptp_ops = &mv88e6352_ptp_ops,
3803 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3804 .serdes_get_strings = mv88e6352_serdes_get_strings,
3805 .serdes_get_stats = mv88e6352_serdes_get_stats,
3806 .phylink_validate = mv88e6352_phylink_validate,
3809 static const struct mv88e6xxx_ops mv88e6390_ops = {
3810 /* MV88E6XXX_FAMILY_6390 */
3811 .setup_errata = mv88e6390_setup_errata,
3812 .irl_init_all = mv88e6390_g2_irl_init_all,
3813 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3814 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3815 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3816 .phy_read = mv88e6xxx_g2_smi_phy_read,
3817 .phy_write = mv88e6xxx_g2_smi_phy_write,
3818 .port_set_link = mv88e6xxx_port_set_link,
3819 .port_set_duplex = mv88e6xxx_port_set_duplex,
3820 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3821 .port_set_speed = mv88e6390_port_set_speed,
3822 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3823 .port_tag_remap = mv88e6390_port_tag_remap,
3824 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3825 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3826 .port_set_ether_type = mv88e6351_port_set_ether_type,
3827 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3828 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3829 .port_pause_limit = mv88e6390_port_pause_limit,
3830 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3831 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3832 .port_link_state = mv88e6352_port_link_state,
3833 .port_get_cmode = mv88e6352_port_get_cmode,
3834 .port_set_cmode = mv88e6390_port_set_cmode,
3835 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3836 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3837 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3838 .stats_get_strings = mv88e6320_stats_get_strings,
3839 .stats_get_stats = mv88e6390_stats_get_stats,
3840 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3841 .set_egress_port = mv88e6390_g1_set_egress_port,
3842 .watchdog_ops = &mv88e6390_watchdog_ops,
3843 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3844 .pot_clear = mv88e6xxx_g2_pot_clear,
3845 .reset = mv88e6352_g1_reset,
3846 .rmu_disable = mv88e6390_g1_rmu_disable,
3847 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3848 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3849 .serdes_power = mv88e6390_serdes_power,
3850 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3851 .serdes_irq_free = mv88e6390_serdes_irq_free,
3852 .gpio_ops = &mv88e6352_gpio_ops,
3853 .avb_ops = &mv88e6390_avb_ops,
3854 .ptp_ops = &mv88e6352_ptp_ops,
3855 .phylink_validate = mv88e6390_phylink_validate,
3858 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3859 /* MV88E6XXX_FAMILY_6390 */
3860 .setup_errata = mv88e6390_setup_errata,
3861 .irl_init_all = mv88e6390_g2_irl_init_all,
3862 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3863 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3864 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3865 .phy_read = mv88e6xxx_g2_smi_phy_read,
3866 .phy_write = mv88e6xxx_g2_smi_phy_write,
3867 .port_set_link = mv88e6xxx_port_set_link,
3868 .port_set_duplex = mv88e6xxx_port_set_duplex,
3869 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3870 .port_set_speed = mv88e6390x_port_set_speed,
3871 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3872 .port_tag_remap = mv88e6390_port_tag_remap,
3873 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3874 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3875 .port_set_ether_type = mv88e6351_port_set_ether_type,
3876 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3877 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3878 .port_pause_limit = mv88e6390_port_pause_limit,
3879 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3880 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3881 .port_link_state = mv88e6352_port_link_state,
3882 .port_get_cmode = mv88e6352_port_get_cmode,
3883 .port_set_cmode = mv88e6390x_port_set_cmode,
3884 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3885 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3886 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3887 .stats_get_strings = mv88e6320_stats_get_strings,
3888 .stats_get_stats = mv88e6390_stats_get_stats,
3889 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3890 .set_egress_port = mv88e6390_g1_set_egress_port,
3891 .watchdog_ops = &mv88e6390_watchdog_ops,
3892 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3893 .pot_clear = mv88e6xxx_g2_pot_clear,
3894 .reset = mv88e6352_g1_reset,
3895 .rmu_disable = mv88e6390_g1_rmu_disable,
3896 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3897 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3898 .serdes_power = mv88e6390x_serdes_power,
3899 .serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3900 .serdes_irq_free = mv88e6390x_serdes_irq_free,
3901 .gpio_ops = &mv88e6352_gpio_ops,
3902 .avb_ops = &mv88e6390_avb_ops,
3903 .ptp_ops = &mv88e6352_ptp_ops,
3904 .phylink_validate = mv88e6390x_phylink_validate,
3907 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3909 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3910 .family = MV88E6XXX_FAMILY_6097,
3911 .name = "Marvell 88E6085",
3912 .num_databases = 4096,
3914 .num_internal_phys = 5,
3916 .port_base_addr = 0x10,
3917 .phy_base_addr = 0x0,
3918 .global1_addr = 0x1b,
3919 .global2_addr = 0x1c,
3920 .age_time_coeff = 15000,
3923 .atu_move_port_mask = 0xf,
3926 .tag_protocol = DSA_TAG_PROTO_DSA,
3927 .ops = &mv88e6085_ops,
3931 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3932 .family = MV88E6XXX_FAMILY_6095,
3933 .name = "Marvell 88E6095/88E6095F",
3934 .num_databases = 256,
3936 .num_internal_phys = 0,
3938 .port_base_addr = 0x10,
3939 .phy_base_addr = 0x0,
3940 .global1_addr = 0x1b,
3941 .global2_addr = 0x1c,
3942 .age_time_coeff = 15000,
3944 .atu_move_port_mask = 0xf,
3946 .tag_protocol = DSA_TAG_PROTO_DSA,
3947 .ops = &mv88e6095_ops,
3951 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3952 .family = MV88E6XXX_FAMILY_6097,
3953 .name = "Marvell 88E6097/88E6097F",
3954 .num_databases = 4096,
3956 .num_internal_phys = 8,
3958 .port_base_addr = 0x10,
3959 .phy_base_addr = 0x0,
3960 .global1_addr = 0x1b,
3961 .global2_addr = 0x1c,
3962 .age_time_coeff = 15000,
3965 .atu_move_port_mask = 0xf,
3968 .tag_protocol = DSA_TAG_PROTO_EDSA,
3969 .ops = &mv88e6097_ops,
3973 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3974 .family = MV88E6XXX_FAMILY_6165,
3975 .name = "Marvell 88E6123",
3976 .num_databases = 4096,
3978 .num_internal_phys = 5,
3980 .port_base_addr = 0x10,
3981 .phy_base_addr = 0x0,
3982 .global1_addr = 0x1b,
3983 .global2_addr = 0x1c,
3984 .age_time_coeff = 15000,
3987 .atu_move_port_mask = 0xf,
3990 .tag_protocol = DSA_TAG_PROTO_EDSA,
3991 .ops = &mv88e6123_ops,
3995 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3996 .family = MV88E6XXX_FAMILY_6185,
3997 .name = "Marvell 88E6131",
3998 .num_databases = 256,
4000 .num_internal_phys = 0,
4002 .port_base_addr = 0x10,
4003 .phy_base_addr = 0x0,
4004 .global1_addr = 0x1b,
4005 .global2_addr = 0x1c,
4006 .age_time_coeff = 15000,
4008 .atu_move_port_mask = 0xf,
4010 .tag_protocol = DSA_TAG_PROTO_DSA,
4011 .ops = &mv88e6131_ops,
4015 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4016 .family = MV88E6XXX_FAMILY_6341,
4017 .name = "Marvell 88E6141",
4018 .num_databases = 4096,
4020 .num_internal_phys = 5,
4023 .port_base_addr = 0x10,
4024 .phy_base_addr = 0x10,
4025 .global1_addr = 0x1b,
4026 .global2_addr = 0x1c,
4027 .age_time_coeff = 3750,
4028 .atu_move_port_mask = 0x1f,
4033 .tag_protocol = DSA_TAG_PROTO_EDSA,
4034 .ops = &mv88e6141_ops,
4038 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4039 .family = MV88E6XXX_FAMILY_6165,
4040 .name = "Marvell 88E6161",
4041 .num_databases = 4096,
4043 .num_internal_phys = 5,
4045 .port_base_addr = 0x10,
4046 .phy_base_addr = 0x0,
4047 .global1_addr = 0x1b,
4048 .global2_addr = 0x1c,
4049 .age_time_coeff = 15000,
4052 .atu_move_port_mask = 0xf,
4055 .tag_protocol = DSA_TAG_PROTO_EDSA,
4056 .ptp_support = true,
4057 .ops = &mv88e6161_ops,
4061 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4062 .family = MV88E6XXX_FAMILY_6165,
4063 .name = "Marvell 88E6165",
4064 .num_databases = 4096,
4066 .num_internal_phys = 0,
4068 .port_base_addr = 0x10,
4069 .phy_base_addr = 0x0,
4070 .global1_addr = 0x1b,
4071 .global2_addr = 0x1c,
4072 .age_time_coeff = 15000,
4075 .atu_move_port_mask = 0xf,
4078 .tag_protocol = DSA_TAG_PROTO_DSA,
4079 .ptp_support = true,
4080 .ops = &mv88e6165_ops,
4084 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4085 .family = MV88E6XXX_FAMILY_6351,
4086 .name = "Marvell 88E6171",
4087 .num_databases = 4096,
4089 .num_internal_phys = 5,
4091 .port_base_addr = 0x10,
4092 .phy_base_addr = 0x0,
4093 .global1_addr = 0x1b,
4094 .global2_addr = 0x1c,
4095 .age_time_coeff = 15000,
4098 .atu_move_port_mask = 0xf,
4101 .tag_protocol = DSA_TAG_PROTO_EDSA,
4102 .ops = &mv88e6171_ops,
4106 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4107 .family = MV88E6XXX_FAMILY_6352,
4108 .name = "Marvell 88E6172",
4109 .num_databases = 4096,
4111 .num_internal_phys = 5,
4114 .port_base_addr = 0x10,
4115 .phy_base_addr = 0x0,
4116 .global1_addr = 0x1b,
4117 .global2_addr = 0x1c,
4118 .age_time_coeff = 15000,
4121 .atu_move_port_mask = 0xf,
4124 .tag_protocol = DSA_TAG_PROTO_EDSA,
4125 .ops = &mv88e6172_ops,
4129 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4130 .family = MV88E6XXX_FAMILY_6351,
4131 .name = "Marvell 88E6175",
4132 .num_databases = 4096,
4134 .num_internal_phys = 5,
4136 .port_base_addr = 0x10,
4137 .phy_base_addr = 0x0,
4138 .global1_addr = 0x1b,
4139 .global2_addr = 0x1c,
4140 .age_time_coeff = 15000,
4143 .atu_move_port_mask = 0xf,
4146 .tag_protocol = DSA_TAG_PROTO_EDSA,
4147 .ops = &mv88e6175_ops,
4151 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4152 .family = MV88E6XXX_FAMILY_6352,
4153 .name = "Marvell 88E6176",
4154 .num_databases = 4096,
4156 .num_internal_phys = 5,
4159 .port_base_addr = 0x10,
4160 .phy_base_addr = 0x0,
4161 .global1_addr = 0x1b,
4162 .global2_addr = 0x1c,
4163 .age_time_coeff = 15000,
4166 .atu_move_port_mask = 0xf,
4169 .tag_protocol = DSA_TAG_PROTO_EDSA,
4170 .ops = &mv88e6176_ops,
4174 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4175 .family = MV88E6XXX_FAMILY_6185,
4176 .name = "Marvell 88E6185",
4177 .num_databases = 256,
4179 .num_internal_phys = 0,
4181 .port_base_addr = 0x10,
4182 .phy_base_addr = 0x0,
4183 .global1_addr = 0x1b,
4184 .global2_addr = 0x1c,
4185 .age_time_coeff = 15000,
4187 .atu_move_port_mask = 0xf,
4189 .tag_protocol = DSA_TAG_PROTO_EDSA,
4190 .ops = &mv88e6185_ops,
4194 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4195 .family = MV88E6XXX_FAMILY_6390,
4196 .name = "Marvell 88E6190",
4197 .num_databases = 4096,
4198 .num_ports = 11, /* 10 + Z80 */
4199 .num_internal_phys = 9,
4202 .port_base_addr = 0x0,
4203 .phy_base_addr = 0x0,
4204 .global1_addr = 0x1b,
4205 .global2_addr = 0x1c,
4206 .tag_protocol = DSA_TAG_PROTO_DSA,
4207 .age_time_coeff = 3750,
4212 .atu_move_port_mask = 0x1f,
4213 .ops = &mv88e6190_ops,
4217 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4218 .family = MV88E6XXX_FAMILY_6390,
4219 .name = "Marvell 88E6190X",
4220 .num_databases = 4096,
4221 .num_ports = 11, /* 10 + Z80 */
4222 .num_internal_phys = 9,
4225 .port_base_addr = 0x0,
4226 .phy_base_addr = 0x0,
4227 .global1_addr = 0x1b,
4228 .global2_addr = 0x1c,
4229 .age_time_coeff = 3750,
4232 .atu_move_port_mask = 0x1f,
4235 .tag_protocol = DSA_TAG_PROTO_DSA,
4236 .ops = &mv88e6190x_ops,
4240 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4241 .family = MV88E6XXX_FAMILY_6390,
4242 .name = "Marvell 88E6191",
4243 .num_databases = 4096,
4244 .num_ports = 11, /* 10 + Z80 */
4245 .num_internal_phys = 9,
4247 .port_base_addr = 0x0,
4248 .phy_base_addr = 0x0,
4249 .global1_addr = 0x1b,
4250 .global2_addr = 0x1c,
4251 .age_time_coeff = 3750,
4254 .atu_move_port_mask = 0x1f,
4257 .tag_protocol = DSA_TAG_PROTO_DSA,
4258 .ptp_support = true,
4259 .ops = &mv88e6191_ops,
4263 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4264 .family = MV88E6XXX_FAMILY_6352,
4265 .name = "Marvell 88E6240",
4266 .num_databases = 4096,
4268 .num_internal_phys = 5,
4271 .port_base_addr = 0x10,
4272 .phy_base_addr = 0x0,
4273 .global1_addr = 0x1b,
4274 .global2_addr = 0x1c,
4275 .age_time_coeff = 15000,
4278 .atu_move_port_mask = 0xf,
4281 .tag_protocol = DSA_TAG_PROTO_EDSA,
4282 .ptp_support = true,
4283 .ops = &mv88e6240_ops,
4287 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4288 .family = MV88E6XXX_FAMILY_6250,
4289 .name = "Marvell 88E6250",
4290 .num_databases = 64,
4292 .num_internal_phys = 5,
4294 .port_base_addr = 0x08,
4295 .phy_base_addr = 0x00,
4296 .global1_addr = 0x0f,
4297 .global2_addr = 0x07,
4298 .age_time_coeff = 15000,
4301 .atu_move_port_mask = 0xf,
4303 .tag_protocol = DSA_TAG_PROTO_DSA,
4304 .ops = &mv88e6250_ops,
4308 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4309 .family = MV88E6XXX_FAMILY_6390,
4310 .name = "Marvell 88E6290",
4311 .num_databases = 4096,
4312 .num_ports = 11, /* 10 + Z80 */
4313 .num_internal_phys = 9,
4316 .port_base_addr = 0x0,
4317 .phy_base_addr = 0x0,
4318 .global1_addr = 0x1b,
4319 .global2_addr = 0x1c,
4320 .age_time_coeff = 3750,
4323 .atu_move_port_mask = 0x1f,
4326 .tag_protocol = DSA_TAG_PROTO_DSA,
4327 .ptp_support = true,
4328 .ops = &mv88e6290_ops,
4332 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4333 .family = MV88E6XXX_FAMILY_6320,
4334 .name = "Marvell 88E6320",
4335 .num_databases = 4096,
4337 .num_internal_phys = 5,
4340 .port_base_addr = 0x10,
4341 .phy_base_addr = 0x0,
4342 .global1_addr = 0x1b,
4343 .global2_addr = 0x1c,
4344 .age_time_coeff = 15000,
4347 .atu_move_port_mask = 0xf,
4350 .tag_protocol = DSA_TAG_PROTO_EDSA,
4351 .ptp_support = true,
4352 .ops = &mv88e6320_ops,
4356 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4357 .family = MV88E6XXX_FAMILY_6320,
4358 .name = "Marvell 88E6321",
4359 .num_databases = 4096,
4361 .num_internal_phys = 5,
4364 .port_base_addr = 0x10,
4365 .phy_base_addr = 0x0,
4366 .global1_addr = 0x1b,
4367 .global2_addr = 0x1c,
4368 .age_time_coeff = 15000,
4371 .atu_move_port_mask = 0xf,
4373 .tag_protocol = DSA_TAG_PROTO_EDSA,
4374 .ptp_support = true,
4375 .ops = &mv88e6321_ops,
4379 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
4380 .family = MV88E6XXX_FAMILY_6341,
4381 .name = "Marvell 88E6341",
4382 .num_databases = 4096,
4383 .num_internal_phys = 5,
4387 .port_base_addr = 0x10,
4388 .phy_base_addr = 0x10,
4389 .global1_addr = 0x1b,
4390 .global2_addr = 0x1c,
4391 .age_time_coeff = 3750,
4392 .atu_move_port_mask = 0x1f,
4397 .tag_protocol = DSA_TAG_PROTO_EDSA,
4398 .ptp_support = true,
4399 .ops = &mv88e6341_ops,
4403 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4404 .family = MV88E6XXX_FAMILY_6351,
4405 .name = "Marvell 88E6350",
4406 .num_databases = 4096,
4408 .num_internal_phys = 5,
4410 .port_base_addr = 0x10,
4411 .phy_base_addr = 0x0,
4412 .global1_addr = 0x1b,
4413 .global2_addr = 0x1c,
4414 .age_time_coeff = 15000,
4417 .atu_move_port_mask = 0xf,
4420 .tag_protocol = DSA_TAG_PROTO_EDSA,
4421 .ops = &mv88e6350_ops,
4425 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4426 .family = MV88E6XXX_FAMILY_6351,
4427 .name = "Marvell 88E6351",
4428 .num_databases = 4096,
4430 .num_internal_phys = 5,
4432 .port_base_addr = 0x10,
4433 .phy_base_addr = 0x0,
4434 .global1_addr = 0x1b,
4435 .global2_addr = 0x1c,
4436 .age_time_coeff = 15000,
4439 .atu_move_port_mask = 0xf,
4442 .tag_protocol = DSA_TAG_PROTO_EDSA,
4443 .ops = &mv88e6351_ops,
4447 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4448 .family = MV88E6XXX_FAMILY_6352,
4449 .name = "Marvell 88E6352",
4450 .num_databases = 4096,
4452 .num_internal_phys = 5,
4455 .port_base_addr = 0x10,
4456 .phy_base_addr = 0x0,
4457 .global1_addr = 0x1b,
4458 .global2_addr = 0x1c,
4459 .age_time_coeff = 15000,
4462 .atu_move_port_mask = 0xf,
4465 .tag_protocol = DSA_TAG_PROTO_EDSA,
4466 .ptp_support = true,
4467 .ops = &mv88e6352_ops,
4470 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4471 .family = MV88E6XXX_FAMILY_6390,
4472 .name = "Marvell 88E6390",
4473 .num_databases = 4096,
4474 .num_ports = 11, /* 10 + Z80 */
4475 .num_internal_phys = 9,
4478 .port_base_addr = 0x0,
4479 .phy_base_addr = 0x0,
4480 .global1_addr = 0x1b,
4481 .global2_addr = 0x1c,
4482 .age_time_coeff = 3750,
4485 .atu_move_port_mask = 0x1f,
4488 .tag_protocol = DSA_TAG_PROTO_DSA,
4489 .ptp_support = true,
4490 .ops = &mv88e6390_ops,
4493 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4494 .family = MV88E6XXX_FAMILY_6390,
4495 .name = "Marvell 88E6390X",
4496 .num_databases = 4096,
4497 .num_ports = 11, /* 10 + Z80 */
4498 .num_internal_phys = 9,
4501 .port_base_addr = 0x0,
4502 .phy_base_addr = 0x0,
4503 .global1_addr = 0x1b,
4504 .global2_addr = 0x1c,
4505 .age_time_coeff = 3750,
4508 .atu_move_port_mask = 0x1f,
4511 .tag_protocol = DSA_TAG_PROTO_DSA,
4512 .ptp_support = true,
4513 .ops = &mv88e6390x_ops,
4517 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4521 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4522 if (mv88e6xxx_table[i].prod_num == prod_num)
4523 return &mv88e6xxx_table[i];
4528 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4530 const struct mv88e6xxx_info *info;
4531 unsigned int prod_num, rev;
4535 mv88e6xxx_reg_lock(chip);
4536 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4537 mv88e6xxx_reg_unlock(chip);
4541 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
4542 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4544 info = mv88e6xxx_lookup_info(prod_num);
4548 /* Update the compatible info with the probed one */
4551 err = mv88e6xxx_g2_require(chip);
4555 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4556 chip->info->prod_num, chip->info->name, rev);
4561 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4563 struct mv88e6xxx_chip *chip;
4565 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4571 mutex_init(&chip->reg_lock);
4572 INIT_LIST_HEAD(&chip->mdios);
4577 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4580 struct mv88e6xxx_chip *chip = ds->priv;
4582 return chip->info->tag_protocol;
4585 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4586 const struct switchdev_obj_port_mdb *mdb)
4588 /* We don't need any dynamic resource from the kernel (yet),
4589 * so skip the prepare phase.
4595 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4596 const struct switchdev_obj_port_mdb *mdb)
4598 struct mv88e6xxx_chip *chip = ds->priv;
4600 mv88e6xxx_reg_lock(chip);
4601 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4602 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4603 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4605 mv88e6xxx_reg_unlock(chip);
4608 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4609 const struct switchdev_obj_port_mdb *mdb)
4611 struct mv88e6xxx_chip *chip = ds->priv;
4614 mv88e6xxx_reg_lock(chip);
4615 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4616 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4617 mv88e6xxx_reg_unlock(chip);
4622 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
4623 bool unicast, bool multicast)
4625 struct mv88e6xxx_chip *chip = ds->priv;
4626 int err = -EOPNOTSUPP;
4628 mv88e6xxx_reg_lock(chip);
4629 if (chip->info->ops->port_set_egress_floods)
4630 err = chip->info->ops->port_set_egress_floods(chip, port,
4633 mv88e6xxx_reg_unlock(chip);
4638 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4639 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4640 .setup = mv88e6xxx_setup,
4641 .adjust_link = mv88e6xxx_adjust_link,
4642 .phylink_validate = mv88e6xxx_validate,
4643 .phylink_mac_link_state = mv88e6xxx_link_state,
4644 .phylink_mac_config = mv88e6xxx_mac_config,
4645 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
4646 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
4647 .get_strings = mv88e6xxx_get_strings,
4648 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4649 .get_sset_count = mv88e6xxx_get_sset_count,
4650 .port_enable = mv88e6xxx_port_enable,
4651 .port_disable = mv88e6xxx_port_disable,
4652 .get_mac_eee = mv88e6xxx_get_mac_eee,
4653 .set_mac_eee = mv88e6xxx_set_mac_eee,
4654 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4655 .get_eeprom = mv88e6xxx_get_eeprom,
4656 .set_eeprom = mv88e6xxx_set_eeprom,
4657 .get_regs_len = mv88e6xxx_get_regs_len,
4658 .get_regs = mv88e6xxx_get_regs,
4659 .set_ageing_time = mv88e6xxx_set_ageing_time,
4660 .port_bridge_join = mv88e6xxx_port_bridge_join,
4661 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4662 .port_egress_floods = mv88e6xxx_port_egress_floods,
4663 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4664 .port_fast_age = mv88e6xxx_port_fast_age,
4665 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4666 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4667 .port_vlan_add = mv88e6xxx_port_vlan_add,
4668 .port_vlan_del = mv88e6xxx_port_vlan_del,
4669 .port_fdb_add = mv88e6xxx_port_fdb_add,
4670 .port_fdb_del = mv88e6xxx_port_fdb_del,
4671 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4672 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4673 .port_mdb_add = mv88e6xxx_port_mdb_add,
4674 .port_mdb_del = mv88e6xxx_port_mdb_del,
4675 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4676 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4677 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
4678 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
4679 .port_txtstamp = mv88e6xxx_port_txtstamp,
4680 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
4681 .get_ts_info = mv88e6xxx_get_ts_info,
4684 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4686 struct device *dev = chip->dev;
4687 struct dsa_switch *ds;
4689 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4695 ds->ops = &mv88e6xxx_switch_ops;
4696 ds->ageing_time_min = chip->info->age_time_coeff;
4697 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4699 dev_set_drvdata(dev, ds);
4701 return dsa_register_switch(ds);
4704 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4706 dsa_unregister_switch(chip->ds);
4709 static const void *pdata_device_get_match_data(struct device *dev)
4711 const struct of_device_id *matches = dev->driver->of_match_table;
4712 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
4714 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
4716 if (!strcmp(pdata->compatible, matches->compatible))
4717 return matches->data;
4722 /* There is no suspend to RAM support at DSA level yet, the switch configuration
4723 * would be lost after a power cycle so prevent it to be suspended.
4725 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
4730 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
4735 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
4737 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4739 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
4740 const struct mv88e6xxx_info *compat_info = NULL;
4741 struct device *dev = &mdiodev->dev;
4742 struct device_node *np = dev->of_node;
4743 struct mv88e6xxx_chip *chip;
4751 compat_info = of_device_get_match_data(dev);
4754 compat_info = pdata_device_get_match_data(dev);
4759 for (port = 0; port < DSA_MAX_PORTS; port++) {
4760 if (!(pdata->enabled_ports & (1 << port)))
4762 if (strcmp(pdata->cd.port_names[port], "cpu"))
4764 pdata->cd.netdev[port] = &pdata->netdev->dev;
4772 chip = mv88e6xxx_alloc_chip(dev);
4778 chip->info = compat_info;
4780 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4784 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4785 if (IS_ERR(chip->reset)) {
4786 err = PTR_ERR(chip->reset);
4790 usleep_range(1000, 2000);
4792 err = mv88e6xxx_detect(chip);
4796 mv88e6xxx_phy_init(chip);
4798 if (chip->info->ops->get_eeprom) {
4800 of_property_read_u32(np, "eeprom-length",
4803 chip->eeprom_len = pdata->eeprom_len;
4806 mv88e6xxx_reg_lock(chip);
4807 err = mv88e6xxx_switch_reset(chip);
4808 mv88e6xxx_reg_unlock(chip);
4813 chip->irq = of_irq_get(np, 0);
4814 if (chip->irq == -EPROBE_DEFER) {
4821 chip->irq = pdata->irq;
4823 /* Has to be performed before the MDIO bus is created, because
4824 * the PHYs will link their interrupts to these interrupt
4827 mv88e6xxx_reg_lock(chip);
4829 err = mv88e6xxx_g1_irq_setup(chip);
4831 err = mv88e6xxx_irq_poll_setup(chip);
4832 mv88e6xxx_reg_unlock(chip);
4837 if (chip->info->g2_irqs > 0) {
4838 err = mv88e6xxx_g2_irq_setup(chip);
4843 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
4847 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
4849 goto out_g1_atu_prob_irq;
4851 err = mv88e6xxx_mdios_register(chip, np);
4853 goto out_g1_vtu_prob_irq;
4855 err = mv88e6xxx_register_switch(chip);
4862 mv88e6xxx_mdios_unregister(chip);
4863 out_g1_vtu_prob_irq:
4864 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4865 out_g1_atu_prob_irq:
4866 mv88e6xxx_g1_atu_prob_irq_free(chip);
4868 if (chip->info->g2_irqs > 0)
4869 mv88e6xxx_g2_irq_free(chip);
4872 mv88e6xxx_g1_irq_free(chip);
4874 mv88e6xxx_irq_poll_free(chip);
4877 dev_put(pdata->netdev);
4882 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4884 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4885 struct mv88e6xxx_chip *chip = ds->priv;
4887 if (chip->info->ptp_support) {
4888 mv88e6xxx_hwtstamp_free(chip);
4889 mv88e6xxx_ptp_free(chip);
4892 mv88e6xxx_phy_destroy(chip);
4893 mv88e6xxx_unregister_switch(chip);
4894 mv88e6xxx_mdios_unregister(chip);
4896 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4897 mv88e6xxx_g1_atu_prob_irq_free(chip);
4899 if (chip->info->g2_irqs > 0)
4900 mv88e6xxx_g2_irq_free(chip);
4903 mv88e6xxx_g1_irq_free(chip);
4905 mv88e6xxx_irq_poll_free(chip);
4908 static const struct of_device_id mv88e6xxx_of_match[] = {
4910 .compatible = "marvell,mv88e6085",
4911 .data = &mv88e6xxx_table[MV88E6085],
4914 .compatible = "marvell,mv88e6190",
4915 .data = &mv88e6xxx_table[MV88E6190],
4918 .compatible = "marvell,mv88e6250",
4919 .data = &mv88e6xxx_table[MV88E6250],
4924 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4926 static struct mdio_driver mv88e6xxx_driver = {
4927 .probe = mv88e6xxx_probe,
4928 .remove = mv88e6xxx_remove,
4930 .name = "mv88e6085",
4931 .of_match_table = mv88e6xxx_of_match,
4932 .pm = &mv88e6xxx_pm_ops,
4936 mdio_module_driver(mv88e6xxx_driver);
4938 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4939 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4940 MODULE_LICENSE("GPL");