2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
43 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
64 int addr, int reg, u16 *val)
69 return chip->smi_ops->read(chip, addr, reg, val);
72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
73 int addr, int reg, u16 val)
78 return chip->smi_ops->write(chip, addr, reg, val);
81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
82 int addr, int reg, u16 *val)
86 ret = mdiobus_read_nested(chip->bus, addr, reg);
95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
96 int addr, int reg, u16 val)
100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
117 for (i = 0; i < 16; i++) {
118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
122 if ((ret & SMI_CMD_BUSY) == 0)
129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
130 int addr, int reg, u16 *val)
134 /* Wait for the bus to become free. */
135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
139 /* Transmit the read command. */
140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
145 /* Wait for the read command to complete. */
146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
161 int addr, int reg, u16 val)
165 /* Wait for the bus to become free. */
166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
170 /* Transmit the data to write. */
171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
175 /* Transmit the write command. */
176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
181 /* Wait for the write command to complete. */
182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
198 assert_reg_lock(chip);
200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
214 assert_reg_lock(chip);
216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
228 struct mv88e6xxx_mdio_bus *mdio_bus;
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
235 return mdio_bus->bus;
238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
243 chip->g1_irq.masked |= (1 << n);
246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
251 chip->g1_irq.masked &= ~(1 << n);
254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
263 mutex_lock(&chip->reg_lock);
264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
265 mutex_unlock(&chip->reg_lock);
270 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
271 if (reg & (1 << n)) {
272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
273 handle_nested_irq(sub_irq);
278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
285 mutex_lock(&chip->reg_lock);
288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
300 reg |= (~chip->g1_irq.masked & mask);
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
307 mutex_unlock(&chip->reg_lock);
310 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
311 .name = "mv88e6xxx-g1",
312 .irq_mask = mv88e6xxx_g1_irq_mask,
313 .irq_unmask = mv88e6xxx_g1_irq_unmask,
314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
320 irq_hw_number_t hwirq)
322 struct mv88e6xxx_chip *chip = d->host_data;
324 irq_set_chip_data(irq, d->host_data);
325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
326 irq_set_noprobe(irq);
331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
332 .map = mv88e6xxx_g1_irq_domain_map,
333 .xlate = irq_domain_xlate_twocell,
336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
342 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
345 free_irq(chip->irq, chip);
347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
348 virq = irq_find_mapping(chip->g1_irq.domain, irq);
349 irq_dispose_mapping(virq);
352 irq_domain_remove(chip->g1_irq.domain);
355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
360 chip->g1_irq.nirqs = chip->info->g1_irqs;
361 chip->g1_irq.domain = irq_domain_add_simple(
362 NULL, chip->g1_irq.nirqs, 0,
363 &mv88e6xxx_g1_irq_domain_ops, chip);
364 if (!chip->g1_irq.domain)
367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
368 irq_create_mapping(chip->g1_irq.domain, irq);
370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
371 chip->g1_irq.masked = ~0;
373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
383 /* Reading the interrupt status clears (most of) them */
384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
388 err = request_threaded_irq(chip->irq, NULL,
389 mv88e6xxx_g1_irq_thread_fn,
390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
391 dev_name(chip->dev), chip);
398 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
402 for (irq = 0; irq < 16; irq++) {
403 virq = irq_find_mapping(chip->g1_irq.domain, irq);
404 irq_dispose_mapping(virq);
407 irq_domain_remove(chip->g1_irq.domain);
412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
416 for (i = 0; i < 16; i++) {
420 err = mv88e6xxx_read(chip, addr, reg, &val);
427 usleep_range(1000, 2000);
430 dev_err(chip->dev, "Timeout while waiting for switch\n");
434 /* Indirect write to single pointer-data register with an Update bit */
435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
440 /* Wait until the previous operation is completed */
441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
445 /* Set the Update bit to trigger a write operation */
446 val = BIT(15) | update;
448 return mv88e6xxx_write(chip, addr, reg, val);
451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452 int link, int speed, int duplex,
453 phy_interface_t mode)
457 if (!chip->info->ops->port_set_link)
460 /* Port's MAC control must not be changed unless the link is down */
461 err = chip->info->ops->port_set_link(chip, port, 0);
465 if (chip->info->ops->port_set_speed) {
466 err = chip->info->ops->port_set_speed(chip, port, speed);
467 if (err && err != -EOPNOTSUPP)
471 if (chip->info->ops->port_set_duplex) {
472 err = chip->info->ops->port_set_duplex(chip, port, duplex);
473 if (err && err != -EOPNOTSUPP)
477 if (chip->info->ops->port_set_rgmii_delay) {
478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
479 if (err && err != -EOPNOTSUPP)
483 if (chip->info->ops->port_set_cmode) {
484 err = chip->info->ops->port_set_cmode(chip, port, mode);
485 if (err && err != -EOPNOTSUPP)
491 if (chip->info->ops->port_set_link(chip, port, link))
492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
497 /* We expect the switch to perform auto negotiation if there is a real
498 * phy. However, in the case of a fixed link phy, we force the port
499 * settings from the fixed link settings.
501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
502 struct phy_device *phydev)
504 struct mv88e6xxx_chip *chip = ds->priv;
507 if (!phy_is_pseudo_fixed_link(phydev))
510 mutex_lock(&chip->reg_lock);
511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
512 phydev->duplex, phydev->interface);
513 mutex_unlock(&chip->reg_lock);
515 if (err && err != -EOPNOTSUPP)
516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
521 if (!chip->info->ops->stats_snapshot)
524 return chip->info->ops->stats_snapshot(chip, port);
527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
548 { "single", 4, 0x14, STATS_TYPE_BANK0, },
549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
551 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
590 struct mv88e6xxx_hw_stat *s,
591 int port, u16 bank1_select,
601 case STATS_TYPE_PORT:
602 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
607 if (s->sizeof_stat == 4) {
608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
614 case STATS_TYPE_BANK1:
617 case STATS_TYPE_BANK0:
618 reg |= s->reg | histogram;
619 mv88e6xxx_g1_stats_read(chip, reg, &low);
620 if (s->sizeof_stat == 8)
621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
626 value = (((u64)high) << 16) | low;
630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
631 uint8_t *data, int types)
633 struct mv88e6xxx_hw_stat *stat;
636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
637 stat = &mv88e6xxx_hw_stats[i];
638 if (stat->type & types) {
639 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
649 mv88e6xxx_stats_get_strings(chip, data,
650 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
656 mv88e6xxx_stats_get_strings(chip, data,
657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
663 struct mv88e6xxx_chip *chip = ds->priv;
665 if (chip->info->ops->stats_get_strings)
666 chip->info->ops->stats_get_strings(chip, data);
669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
672 struct mv88e6xxx_hw_stat *stat;
675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
676 stat = &mv88e6xxx_hw_stats[i];
677 if (stat->type & types)
683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
697 struct mv88e6xxx_chip *chip = ds->priv;
699 if (chip->info->ops->stats_get_sset_count)
700 return chip->info->ops->stats_get_sset_count(chip);
705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
706 uint64_t *data, int types,
707 u16 bank1_select, u16 histogram)
709 struct mv88e6xxx_hw_stat *stat;
712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
713 stat = &mv88e6xxx_hw_stats[i];
714 if (stat->type & types) {
715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
726 return mv88e6xxx_stats_get_stats(chip, port, data,
727 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
734 return mv88e6xxx_stats_get_stats(chip, port, data,
735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
743 return mv88e6xxx_stats_get_stats(chip, port, data,
744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
752 if (chip->info->ops->stats_get_stats)
753 chip->info->ops->stats_get_stats(chip, port, data);
756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
759 struct mv88e6xxx_chip *chip = ds->priv;
762 mutex_lock(&chip->reg_lock);
764 ret = mv88e6xxx_stats_snapshot(chip, port);
766 mutex_unlock(&chip->reg_lock);
770 mv88e6xxx_get_stats(chip, port, data);
772 mutex_unlock(&chip->reg_lock);
775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
777 if (chip->info->ops->stats_set_histogram)
778 return chip->info->ops->stats_set_histogram(chip);
783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
785 return 32 * sizeof(u16);
788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
789 struct ethtool_regs *regs, void *_p)
791 struct mv88e6xxx_chip *chip = ds->priv;
799 memset(p, 0xff, 32 * sizeof(u16));
801 mutex_lock(&chip->reg_lock);
803 for (i = 0; i < 32; i++) {
805 err = mv88e6xxx_port_read(chip, port, i, ®);
810 mutex_unlock(&chip->reg_lock);
813 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
814 struct ethtool_eee *e)
816 /* Nothing to do on the port's MAC */
820 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
821 struct ethtool_eee *e)
823 /* Nothing to do on the port's MAC */
827 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
829 struct dsa_switch *ds = NULL;
830 struct net_device *br;
834 if (dev < DSA_MAX_SWITCHES)
835 ds = chip->ds->dst->ds[dev];
837 /* Prevent frames from unknown switch or port */
838 if (!ds || port >= ds->num_ports)
841 /* Frames from DSA links and CPU ports can egress any local port */
842 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
843 return mv88e6xxx_port_mask(chip);
845 br = ds->ports[port].bridge_dev;
848 /* Frames from user ports can egress any local DSA links and CPU ports,
849 * as well as any local member of their bridge group.
851 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
852 if (dsa_is_cpu_port(chip->ds, i) ||
853 dsa_is_dsa_port(chip->ds, i) ||
854 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
860 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
862 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
864 /* prevent frames from going back out of the port they came in on */
865 output_ports &= ~BIT(port);
867 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
870 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
873 struct mv88e6xxx_chip *chip = ds->priv;
876 mutex_lock(&chip->reg_lock);
877 err = mv88e6xxx_port_set_state(chip, port, state);
878 mutex_unlock(&chip->reg_lock);
881 dev_err(ds->dev, "p%d: failed to update state\n", port);
884 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
886 if (chip->info->ops->pot_clear)
887 return chip->info->ops->pot_clear(chip);
892 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
894 if (chip->info->ops->mgmt_rsvd2cpu)
895 return chip->info->ops->mgmt_rsvd2cpu(chip);
900 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
904 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
908 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
912 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
915 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
920 if (!chip->info->ops->irl_init_all)
923 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
924 /* Disable ingress rate limiting by resetting all per port
925 * ingress rate limit resources to their initial state.
927 err = chip->info->ops->irl_init_all(chip, port);
935 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
937 if (chip->info->ops->set_switch_mac) {
940 eth_random_addr(addr);
942 return chip->info->ops->set_switch_mac(chip, addr);
948 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
952 if (!mv88e6xxx_has_pvt(chip))
955 /* Skip the local source device, which uses in-chip port VLAN */
956 if (dev != chip->ds->index)
957 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
959 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
962 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
967 if (!mv88e6xxx_has_pvt(chip))
970 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
971 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
973 err = mv88e6xxx_g2_misc_4_bit_port(chip);
977 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
978 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
979 err = mv88e6xxx_pvt_map(chip, dev, port);
988 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
990 struct mv88e6xxx_chip *chip = ds->priv;
993 mutex_lock(&chip->reg_lock);
994 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
995 mutex_unlock(&chip->reg_lock);
998 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1001 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1003 if (!chip->info->max_vid)
1006 return mv88e6xxx_g1_vtu_flush(chip);
1009 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1010 struct mv88e6xxx_vtu_entry *entry)
1012 if (!chip->info->ops->vtu_getnext)
1015 return chip->info->ops->vtu_getnext(chip, entry);
1018 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1019 struct mv88e6xxx_vtu_entry *entry)
1021 if (!chip->info->ops->vtu_loadpurge)
1024 return chip->info->ops->vtu_loadpurge(chip, entry);
1027 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1029 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1030 struct mv88e6xxx_vtu_entry vlan = {
1031 .vid = chip->info->max_vid,
1035 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1037 /* Set every FID bit used by the (un)bridged ports */
1038 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1039 err = mv88e6xxx_port_get_fid(chip, i, fid);
1043 set_bit(*fid, fid_bitmap);
1046 /* Set every FID bit used by the VLAN entries */
1048 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1055 set_bit(vlan.fid, fid_bitmap);
1056 } while (vlan.vid < chip->info->max_vid);
1058 /* The reset value 0x000 is used to indicate that multiple address
1059 * databases are not needed. Return the next positive available.
1061 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1062 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1065 /* Clear the database */
1066 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1069 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1070 struct mv88e6xxx_vtu_entry *entry, bool new)
1077 entry->vid = vid - 1;
1078 entry->valid = false;
1080 err = mv88e6xxx_vtu_getnext(chip, entry);
1084 if (entry->vid == vid && entry->valid)
1090 /* Initialize a fresh VLAN entry */
1091 memset(entry, 0, sizeof(*entry));
1092 entry->valid = true;
1095 /* Exclude all ports */
1096 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1098 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1100 return mv88e6xxx_atu_new(chip, &entry->fid);
1103 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1107 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1108 u16 vid_begin, u16 vid_end)
1110 struct mv88e6xxx_chip *chip = ds->priv;
1111 struct mv88e6xxx_vtu_entry vlan = {
1112 .vid = vid_begin - 1,
1116 /* DSA and CPU ports have to be members of multiple vlans */
1117 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1123 mutex_lock(&chip->reg_lock);
1126 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1133 if (vlan.vid > vid_end)
1136 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1137 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1140 if (!ds->ports[i].slave)
1143 if (vlan.member[i] ==
1144 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1147 if (dsa_to_port(ds, i)->bridge_dev ==
1148 ds->ports[port].bridge_dev)
1149 break; /* same bridge, check next VLAN */
1151 if (!dsa_to_port(ds, i)->bridge_dev)
1154 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1156 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1160 } while (vlan.vid < vid_end);
1163 mutex_unlock(&chip->reg_lock);
1168 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1169 bool vlan_filtering)
1171 struct mv88e6xxx_chip *chip = ds->priv;
1172 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1173 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1176 if (!chip->info->max_vid)
1179 mutex_lock(&chip->reg_lock);
1180 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1181 mutex_unlock(&chip->reg_lock);
1187 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1188 const struct switchdev_obj_port_vlan *vlan)
1190 struct mv88e6xxx_chip *chip = ds->priv;
1193 if (!chip->info->max_vid)
1196 /* If the requested port doesn't belong to the same bridge as the VLAN
1197 * members, do not support it (yet) and fallback to software VLAN.
1199 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1204 /* We don't need any dynamic resource from the kernel (yet),
1205 * so skip the prepare phase.
1210 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1211 const unsigned char *addr, u16 vid,
1214 struct mv88e6xxx_vtu_entry vlan;
1215 struct mv88e6xxx_atu_entry entry;
1218 /* Null VLAN ID corresponds to the port private database */
1220 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1222 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1226 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1227 ether_addr_copy(entry.mac, addr);
1228 eth_addr_dec(entry.mac);
1230 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1234 /* Initialize a fresh ATU entry if it isn't found */
1235 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1236 !ether_addr_equal(entry.mac, addr)) {
1237 memset(&entry, 0, sizeof(entry));
1238 ether_addr_copy(entry.mac, addr);
1241 /* Purge the ATU entry only if no port is using it anymore */
1242 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1243 entry.portvec &= ~BIT(port);
1245 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1247 entry.portvec |= BIT(port);
1248 entry.state = state;
1251 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1254 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1257 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1258 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1260 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1263 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1268 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1269 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1277 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1280 struct mv88e6xxx_vtu_entry vlan;
1283 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1287 vlan.member[port] = member;
1289 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1293 return mv88e6xxx_broadcast_setup(chip, vid);
1296 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1297 const struct switchdev_obj_port_vlan *vlan)
1299 struct mv88e6xxx_chip *chip = ds->priv;
1300 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1301 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1305 if (!chip->info->max_vid)
1308 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1309 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1311 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1313 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1315 mutex_lock(&chip->reg_lock);
1317 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1318 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1319 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1320 vid, untagged ? 'u' : 't');
1322 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1323 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1326 mutex_unlock(&chip->reg_lock);
1329 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1332 struct mv88e6xxx_vtu_entry vlan;
1335 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1339 /* Tell switchdev if this VLAN is handled in software */
1340 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1343 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1345 /* keep the VLAN unless all ports are excluded */
1347 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1348 if (vlan.member[i] !=
1349 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1355 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1359 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1362 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1363 const struct switchdev_obj_port_vlan *vlan)
1365 struct mv88e6xxx_chip *chip = ds->priv;
1369 if (!chip->info->max_vid)
1372 mutex_lock(&chip->reg_lock);
1374 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1378 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1379 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1384 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1391 mutex_unlock(&chip->reg_lock);
1396 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1397 const unsigned char *addr, u16 vid)
1399 struct mv88e6xxx_chip *chip = ds->priv;
1402 mutex_lock(&chip->reg_lock);
1403 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1404 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1405 mutex_unlock(&chip->reg_lock);
1410 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1411 const unsigned char *addr, u16 vid)
1413 struct mv88e6xxx_chip *chip = ds->priv;
1416 mutex_lock(&chip->reg_lock);
1417 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1418 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1419 mutex_unlock(&chip->reg_lock);
1424 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1425 u16 fid, u16 vid, int port,
1426 dsa_fdb_dump_cb_t *cb, void *data)
1428 struct mv88e6xxx_atu_entry addr;
1432 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1433 eth_broadcast_addr(addr.mac);
1436 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1440 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1443 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1446 if (!is_unicast_ether_addr(addr.mac))
1449 is_static = (addr.state ==
1450 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1451 err = cb(addr.mac, vid, is_static, data);
1454 } while (!is_broadcast_ether_addr(addr.mac));
1459 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1460 dsa_fdb_dump_cb_t *cb, void *data)
1462 struct mv88e6xxx_vtu_entry vlan = {
1463 .vid = chip->info->max_vid,
1468 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1469 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1473 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1477 /* Dump VLANs' Filtering Information Databases */
1479 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1486 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1490 } while (vlan.vid < chip->info->max_vid);
1495 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1496 dsa_fdb_dump_cb_t *cb, void *data)
1498 struct mv88e6xxx_chip *chip = ds->priv;
1501 mutex_lock(&chip->reg_lock);
1502 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
1503 mutex_unlock(&chip->reg_lock);
1508 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1509 struct net_device *br)
1511 struct dsa_switch *ds;
1516 /* Remap the Port VLAN of each local bridge group member */
1517 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1518 if (chip->ds->ports[port].bridge_dev == br) {
1519 err = mv88e6xxx_port_vlan_map(chip, port);
1525 if (!mv88e6xxx_has_pvt(chip))
1528 /* Remap the Port VLAN of each cross-chip bridge group member */
1529 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1530 ds = chip->ds->dst->ds[dev];
1534 for (port = 0; port < ds->num_ports; ++port) {
1535 if (ds->ports[port].bridge_dev == br) {
1536 err = mv88e6xxx_pvt_map(chip, dev, port);
1546 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1547 struct net_device *br)
1549 struct mv88e6xxx_chip *chip = ds->priv;
1552 mutex_lock(&chip->reg_lock);
1553 err = mv88e6xxx_bridge_map(chip, br);
1554 mutex_unlock(&chip->reg_lock);
1559 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1560 struct net_device *br)
1562 struct mv88e6xxx_chip *chip = ds->priv;
1564 mutex_lock(&chip->reg_lock);
1565 if (mv88e6xxx_bridge_map(chip, br) ||
1566 mv88e6xxx_port_vlan_map(chip, port))
1567 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1568 mutex_unlock(&chip->reg_lock);
1571 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1572 int port, struct net_device *br)
1574 struct mv88e6xxx_chip *chip = ds->priv;
1577 if (!mv88e6xxx_has_pvt(chip))
1580 mutex_lock(&chip->reg_lock);
1581 err = mv88e6xxx_pvt_map(chip, dev, port);
1582 mutex_unlock(&chip->reg_lock);
1587 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1588 int port, struct net_device *br)
1590 struct mv88e6xxx_chip *chip = ds->priv;
1592 if (!mv88e6xxx_has_pvt(chip))
1595 mutex_lock(&chip->reg_lock);
1596 if (mv88e6xxx_pvt_map(chip, dev, port))
1597 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1598 mutex_unlock(&chip->reg_lock);
1601 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1603 if (chip->info->ops->reset)
1604 return chip->info->ops->reset(chip);
1609 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1611 struct gpio_desc *gpiod = chip->reset;
1613 /* If there is a GPIO connected to the reset pin, toggle it */
1615 gpiod_set_value_cansleep(gpiod, 1);
1616 usleep_range(10000, 20000);
1617 gpiod_set_value_cansleep(gpiod, 0);
1618 usleep_range(10000, 20000);
1622 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1626 /* Set all ports to the Disabled state */
1627 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1628 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1633 /* Wait for transmit queues to drain,
1634 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1636 usleep_range(2000, 4000);
1641 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1645 err = mv88e6xxx_disable_ports(chip);
1649 mv88e6xxx_hardware_reset(chip);
1651 return mv88e6xxx_software_reset(chip);
1654 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1655 enum mv88e6xxx_frame_mode frame,
1656 enum mv88e6xxx_egress_mode egress, u16 etype)
1660 if (!chip->info->ops->port_set_frame_mode)
1663 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1667 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1671 if (chip->info->ops->port_set_ether_type)
1672 return chip->info->ops->port_set_ether_type(chip, port, etype);
1677 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1679 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1680 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1681 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1684 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1686 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1687 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1688 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1691 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1693 return mv88e6xxx_set_port_mode(chip, port,
1694 MV88E6XXX_FRAME_MODE_ETHERTYPE,
1695 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1699 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1701 if (dsa_is_dsa_port(chip->ds, port))
1702 return mv88e6xxx_set_port_mode_dsa(chip, port);
1704 if (dsa_is_user_port(chip->ds, port))
1705 return mv88e6xxx_set_port_mode_normal(chip, port);
1707 /* Setup CPU port mode depending on its supported tag format */
1708 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1709 return mv88e6xxx_set_port_mode_dsa(chip, port);
1711 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1712 return mv88e6xxx_set_port_mode_edsa(chip, port);
1717 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1719 bool message = dsa_is_dsa_port(chip->ds, port);
1721 return mv88e6xxx_port_set_message_port(chip, port, message);
1724 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1726 struct dsa_switch *ds = chip->ds;
1729 /* Upstream ports flood frames with unknown unicast or multicast DA */
1730 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
1731 if (chip->info->ops->port_set_egress_floods)
1732 return chip->info->ops->port_set_egress_floods(chip, port,
1738 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1741 if (chip->info->ops->serdes_power)
1742 return chip->info->ops->serdes_power(chip, port, on);
1747 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
1749 struct dsa_switch *ds = chip->ds;
1753 upstream_port = dsa_upstream_port(ds, port);
1754 if (chip->info->ops->port_set_upstream_port) {
1755 err = chip->info->ops->port_set_upstream_port(chip, port,
1761 if (port == upstream_port) {
1762 if (chip->info->ops->set_cpu_port) {
1763 err = chip->info->ops->set_cpu_port(chip,
1769 if (chip->info->ops->set_egress_port) {
1770 err = chip->info->ops->set_egress_port(chip,
1780 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1782 struct dsa_switch *ds = chip->ds;
1786 /* MAC Forcing register: don't force link, speed, duplex or flow control
1787 * state to any particular values on physical ports, but force the CPU
1788 * port and all DSA ports to their maximum bandwidth and full duplex.
1790 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1791 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1792 SPEED_MAX, DUPLEX_FULL,
1793 PHY_INTERFACE_MODE_NA);
1795 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1796 SPEED_UNFORCED, DUPLEX_UNFORCED,
1797 PHY_INTERFACE_MODE_NA);
1801 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1802 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1803 * tunneling, determine priority by looking at 802.1p and IP
1804 * priority fields (IP prio has precedence), and set STP state
1807 * If this is the CPU link, use DSA or EDSA tagging depending
1808 * on which tagging mode was configured.
1810 * If this is a link to another switch, use DSA tagging mode.
1812 * If this is the upstream port for this switch, enable
1813 * forwarding of unknown unicasts and multicasts.
1815 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1816 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1817 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1818 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1822 err = mv88e6xxx_setup_port_mode(chip, port);
1826 err = mv88e6xxx_setup_egress_floods(chip, port);
1830 /* Enable the SERDES interface for DSA and CPU ports. Normal
1831 * ports SERDES are enabled when the port is enabled, thus
1832 * saving a bit of power.
1834 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1835 err = mv88e6xxx_serdes_power(chip, port, true);
1840 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1841 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1842 * untagged frames on this port, do a destination address lookup on all
1843 * received packets as usual, disable ARP mirroring and don't send a
1844 * copy of all transmitted/received frames on this port to the CPU.
1846 err = mv88e6xxx_port_set_map_da(chip, port);
1850 err = mv88e6xxx_setup_upstream_port(chip, port);
1854 err = mv88e6xxx_port_set_8021q_mode(chip, port,
1855 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1859 if (chip->info->ops->port_set_jumbo_size) {
1860 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1865 /* Port Association Vector: when learning source addresses
1866 * of packets, add the address to the address database using
1867 * a port bitmap that has only the bit for this port set and
1868 * the other bits clear.
1871 /* Disable learning for CPU port */
1872 if (dsa_is_cpu_port(ds, port))
1875 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1880 /* Egress rate control 2: disable egress rate control. */
1881 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1886 if (chip->info->ops->port_pause_limit) {
1887 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1892 if (chip->info->ops->port_disable_learn_limit) {
1893 err = chip->info->ops->port_disable_learn_limit(chip, port);
1898 if (chip->info->ops->port_disable_pri_override) {
1899 err = chip->info->ops->port_disable_pri_override(chip, port);
1904 if (chip->info->ops->port_tag_remap) {
1905 err = chip->info->ops->port_tag_remap(chip, port);
1910 if (chip->info->ops->port_egress_rate_limiting) {
1911 err = chip->info->ops->port_egress_rate_limiting(chip, port);
1916 err = mv88e6xxx_setup_message_port(chip, port);
1920 /* Port based VLAN map: give each port the same default address
1921 * database, and allow bidirectional communication between the
1922 * CPU and DSA port(s), and the other ports.
1924 err = mv88e6xxx_port_set_fid(chip, port, 0);
1928 err = mv88e6xxx_port_vlan_map(chip, port);
1932 /* Default VLAN ID and priority: don't set a default VLAN
1933 * ID, and set the default packet priority to zero.
1935 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
1938 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1939 struct phy_device *phydev)
1941 struct mv88e6xxx_chip *chip = ds->priv;
1944 mutex_lock(&chip->reg_lock);
1945 err = mv88e6xxx_serdes_power(chip, port, true);
1946 mutex_unlock(&chip->reg_lock);
1951 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
1952 struct phy_device *phydev)
1954 struct mv88e6xxx_chip *chip = ds->priv;
1956 mutex_lock(&chip->reg_lock);
1957 if (mv88e6xxx_serdes_power(chip, port, false))
1958 dev_err(chip->dev, "failed to power off SERDES\n");
1959 mutex_unlock(&chip->reg_lock);
1962 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
1963 unsigned int ageing_time)
1965 struct mv88e6xxx_chip *chip = ds->priv;
1968 mutex_lock(&chip->reg_lock);
1969 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
1970 mutex_unlock(&chip->reg_lock);
1975 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
1977 struct dsa_switch *ds = chip->ds;
1980 /* Disable remote management, and set the switch's DSA device number. */
1981 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
1982 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
1983 (ds->index & 0x1f));
1987 /* Configure the IP ToS mapping registers. */
1988 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
1991 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
1994 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
1997 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
2000 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
2003 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
2006 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
2009 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
2013 /* Configure the IEEE 802.1p priority mapping register. */
2014 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
2018 /* Initialize the statistics unit */
2019 err = mv88e6xxx_stats_set_histogram(chip);
2023 return mv88e6xxx_g1_stats_clear(chip);
2026 static int mv88e6xxx_setup(struct dsa_switch *ds)
2028 struct mv88e6xxx_chip *chip = ds->priv;
2033 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2035 mutex_lock(&chip->reg_lock);
2037 /* Setup Switch Port Registers */
2038 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2039 if (dsa_is_unused_port(ds, i))
2042 err = mv88e6xxx_setup_port(chip, i);
2047 /* Setup Switch Global 1 Registers */
2048 err = mv88e6xxx_g1_setup(chip);
2052 /* Setup Switch Global 2 Registers */
2053 if (chip->info->global2_addr) {
2054 err = mv88e6xxx_g2_setup(chip);
2059 err = mv88e6xxx_irl_setup(chip);
2063 err = mv88e6xxx_mac_setup(chip);
2067 err = mv88e6xxx_phy_setup(chip);
2071 err = mv88e6xxx_vtu_setup(chip);
2075 err = mv88e6xxx_pvt_setup(chip);
2079 err = mv88e6xxx_atu_setup(chip);
2083 err = mv88e6xxx_broadcast_setup(chip, 0);
2087 err = mv88e6xxx_pot_setup(chip);
2091 err = mv88e6xxx_rsvd2cpu_setup(chip);
2096 mutex_unlock(&chip->reg_lock);
2101 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2103 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2104 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2108 if (!chip->info->ops->phy_read)
2111 mutex_lock(&chip->reg_lock);
2112 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2113 mutex_unlock(&chip->reg_lock);
2115 if (reg == MII_PHYSID2) {
2116 /* Some internal PHYS don't have a model number. Use
2117 * the mv88e6390 family model number instead.
2120 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2123 return err ? err : val;
2126 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2128 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2129 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2132 if (!chip->info->ops->phy_write)
2135 mutex_lock(&chip->reg_lock);
2136 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2137 mutex_unlock(&chip->reg_lock);
2142 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2143 struct device_node *np,
2147 struct mv88e6xxx_mdio_bus *mdio_bus;
2148 struct mii_bus *bus;
2151 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2155 mdio_bus = bus->priv;
2156 mdio_bus->bus = bus;
2157 mdio_bus->chip = chip;
2158 INIT_LIST_HEAD(&mdio_bus->list);
2159 mdio_bus->external = external;
2162 bus->name = np->full_name;
2163 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2165 bus->name = "mv88e6xxx SMI";
2166 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2169 bus->read = mv88e6xxx_mdio_read;
2170 bus->write = mv88e6xxx_mdio_write;
2171 bus->parent = chip->dev;
2174 err = of_mdiobus_register(bus, np);
2176 err = mdiobus_register(bus);
2178 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2183 list_add_tail(&mdio_bus->list, &chip->mdios);
2185 list_add(&mdio_bus->list, &chip->mdios);
2190 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2191 { .compatible = "marvell,mv88e6xxx-mdio-external",
2192 .data = (void *)true },
2196 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2199 struct mv88e6xxx_mdio_bus *mdio_bus;
2200 struct mii_bus *bus;
2202 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2203 bus = mdio_bus->bus;
2205 mdiobus_unregister(bus);
2209 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2210 struct device_node *np)
2212 const struct of_device_id *match;
2213 struct device_node *child;
2216 /* Always register one mdio bus for the internal/default mdio
2217 * bus. This maybe represented in the device tree, but is
2220 child = of_get_child_by_name(np, "mdio");
2221 err = mv88e6xxx_mdio_register(chip, child, false);
2225 /* Walk the device tree, and see if there are any other nodes
2226 * which say they are compatible with the external mdio
2229 for_each_available_child_of_node(np, child) {
2230 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2232 err = mv88e6xxx_mdio_register(chip, child, true);
2234 mv88e6xxx_mdios_unregister(chip);
2243 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2245 struct mv88e6xxx_chip *chip = ds->priv;
2247 return chip->eeprom_len;
2250 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2251 struct ethtool_eeprom *eeprom, u8 *data)
2253 struct mv88e6xxx_chip *chip = ds->priv;
2256 if (!chip->info->ops->get_eeprom)
2259 mutex_lock(&chip->reg_lock);
2260 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2261 mutex_unlock(&chip->reg_lock);
2266 eeprom->magic = 0xc3ec4951;
2271 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2272 struct ethtool_eeprom *eeprom, u8 *data)
2274 struct mv88e6xxx_chip *chip = ds->priv;
2277 if (!chip->info->ops->set_eeprom)
2280 if (eeprom->magic != 0xc3ec4951)
2283 mutex_lock(&chip->reg_lock);
2284 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2285 mutex_unlock(&chip->reg_lock);
2290 static const struct mv88e6xxx_ops mv88e6085_ops = {
2291 /* MV88E6XXX_FAMILY_6097 */
2292 .irl_init_all = mv88e6352_g2_irl_init_all,
2293 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2294 .phy_read = mv88e6185_phy_ppu_read,
2295 .phy_write = mv88e6185_phy_ppu_write,
2296 .port_set_link = mv88e6xxx_port_set_link,
2297 .port_set_duplex = mv88e6xxx_port_set_duplex,
2298 .port_set_speed = mv88e6185_port_set_speed,
2299 .port_tag_remap = mv88e6095_port_tag_remap,
2300 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2301 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2302 .port_set_ether_type = mv88e6351_port_set_ether_type,
2303 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2304 .port_pause_limit = mv88e6097_port_pause_limit,
2305 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2306 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2307 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2308 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2309 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2310 .stats_get_strings = mv88e6095_stats_get_strings,
2311 .stats_get_stats = mv88e6095_stats_get_stats,
2312 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2313 .set_egress_port = mv88e6095_g1_set_egress_port,
2314 .watchdog_ops = &mv88e6097_watchdog_ops,
2315 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2316 .pot_clear = mv88e6xxx_g2_pot_clear,
2317 .ppu_enable = mv88e6185_g1_ppu_enable,
2318 .ppu_disable = mv88e6185_g1_ppu_disable,
2319 .reset = mv88e6185_g1_reset,
2320 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2321 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2324 static const struct mv88e6xxx_ops mv88e6095_ops = {
2325 /* MV88E6XXX_FAMILY_6095 */
2326 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2327 .phy_read = mv88e6185_phy_ppu_read,
2328 .phy_write = mv88e6185_phy_ppu_write,
2329 .port_set_link = mv88e6xxx_port_set_link,
2330 .port_set_duplex = mv88e6xxx_port_set_duplex,
2331 .port_set_speed = mv88e6185_port_set_speed,
2332 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2333 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2334 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2335 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2336 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2337 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2338 .stats_get_strings = mv88e6095_stats_get_strings,
2339 .stats_get_stats = mv88e6095_stats_get_stats,
2340 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2341 .ppu_enable = mv88e6185_g1_ppu_enable,
2342 .ppu_disable = mv88e6185_g1_ppu_disable,
2343 .reset = mv88e6185_g1_reset,
2344 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2345 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2348 static const struct mv88e6xxx_ops mv88e6097_ops = {
2349 /* MV88E6XXX_FAMILY_6097 */
2350 .irl_init_all = mv88e6352_g2_irl_init_all,
2351 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2352 .phy_read = mv88e6xxx_g2_smi_phy_read,
2353 .phy_write = mv88e6xxx_g2_smi_phy_write,
2354 .port_set_link = mv88e6xxx_port_set_link,
2355 .port_set_duplex = mv88e6xxx_port_set_duplex,
2356 .port_set_speed = mv88e6185_port_set_speed,
2357 .port_tag_remap = mv88e6095_port_tag_remap,
2358 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2359 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2360 .port_set_ether_type = mv88e6351_port_set_ether_type,
2361 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2362 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2363 .port_pause_limit = mv88e6097_port_pause_limit,
2364 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2365 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2366 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2367 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2368 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2369 .stats_get_strings = mv88e6095_stats_get_strings,
2370 .stats_get_stats = mv88e6095_stats_get_stats,
2371 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2372 .set_egress_port = mv88e6095_g1_set_egress_port,
2373 .watchdog_ops = &mv88e6097_watchdog_ops,
2374 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2375 .pot_clear = mv88e6xxx_g2_pot_clear,
2376 .reset = mv88e6352_g1_reset,
2377 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2378 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2381 static const struct mv88e6xxx_ops mv88e6123_ops = {
2382 /* MV88E6XXX_FAMILY_6165 */
2383 .irl_init_all = mv88e6352_g2_irl_init_all,
2384 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2385 .phy_read = mv88e6xxx_g2_smi_phy_read,
2386 .phy_write = mv88e6xxx_g2_smi_phy_write,
2387 .port_set_link = mv88e6xxx_port_set_link,
2388 .port_set_duplex = mv88e6xxx_port_set_duplex,
2389 .port_set_speed = mv88e6185_port_set_speed,
2390 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2391 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2392 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2393 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2394 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2395 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2396 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2397 .stats_get_strings = mv88e6095_stats_get_strings,
2398 .stats_get_stats = mv88e6095_stats_get_stats,
2399 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2400 .set_egress_port = mv88e6095_g1_set_egress_port,
2401 .watchdog_ops = &mv88e6097_watchdog_ops,
2402 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2403 .pot_clear = mv88e6xxx_g2_pot_clear,
2404 .reset = mv88e6352_g1_reset,
2405 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2406 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2409 static const struct mv88e6xxx_ops mv88e6131_ops = {
2410 /* MV88E6XXX_FAMILY_6185 */
2411 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2412 .phy_read = mv88e6185_phy_ppu_read,
2413 .phy_write = mv88e6185_phy_ppu_write,
2414 .port_set_link = mv88e6xxx_port_set_link,
2415 .port_set_duplex = mv88e6xxx_port_set_duplex,
2416 .port_set_speed = mv88e6185_port_set_speed,
2417 .port_tag_remap = mv88e6095_port_tag_remap,
2418 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2419 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2420 .port_set_ether_type = mv88e6351_port_set_ether_type,
2421 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2422 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2423 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2424 .port_pause_limit = mv88e6097_port_pause_limit,
2425 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2426 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2427 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2428 .stats_get_strings = mv88e6095_stats_get_strings,
2429 .stats_get_stats = mv88e6095_stats_get_stats,
2430 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2431 .set_egress_port = mv88e6095_g1_set_egress_port,
2432 .watchdog_ops = &mv88e6097_watchdog_ops,
2433 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2434 .ppu_enable = mv88e6185_g1_ppu_enable,
2435 .ppu_disable = mv88e6185_g1_ppu_disable,
2436 .reset = mv88e6185_g1_reset,
2437 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2438 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2441 static const struct mv88e6xxx_ops mv88e6141_ops = {
2442 /* MV88E6XXX_FAMILY_6341 */
2443 .irl_init_all = mv88e6352_g2_irl_init_all,
2444 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2445 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2446 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2447 .phy_read = mv88e6xxx_g2_smi_phy_read,
2448 .phy_write = mv88e6xxx_g2_smi_phy_write,
2449 .port_set_link = mv88e6xxx_port_set_link,
2450 .port_set_duplex = mv88e6xxx_port_set_duplex,
2451 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2452 .port_set_speed = mv88e6390_port_set_speed,
2453 .port_tag_remap = mv88e6095_port_tag_remap,
2454 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2455 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2456 .port_set_ether_type = mv88e6351_port_set_ether_type,
2457 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2458 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2459 .port_pause_limit = mv88e6097_port_pause_limit,
2460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2462 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2463 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2464 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2465 .stats_get_strings = mv88e6320_stats_get_strings,
2466 .stats_get_stats = mv88e6390_stats_get_stats,
2467 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2468 .set_egress_port = mv88e6390_g1_set_egress_port,
2469 .watchdog_ops = &mv88e6390_watchdog_ops,
2470 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2471 .pot_clear = mv88e6xxx_g2_pot_clear,
2472 .reset = mv88e6352_g1_reset,
2473 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2474 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2477 static const struct mv88e6xxx_ops mv88e6161_ops = {
2478 /* MV88E6XXX_FAMILY_6165 */
2479 .irl_init_all = mv88e6352_g2_irl_init_all,
2480 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2481 .phy_read = mv88e6xxx_g2_smi_phy_read,
2482 .phy_write = mv88e6xxx_g2_smi_phy_write,
2483 .port_set_link = mv88e6xxx_port_set_link,
2484 .port_set_duplex = mv88e6xxx_port_set_duplex,
2485 .port_set_speed = mv88e6185_port_set_speed,
2486 .port_tag_remap = mv88e6095_port_tag_remap,
2487 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2488 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2489 .port_set_ether_type = mv88e6351_port_set_ether_type,
2490 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2491 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2492 .port_pause_limit = mv88e6097_port_pause_limit,
2493 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2494 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2495 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2496 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2497 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2498 .stats_get_strings = mv88e6095_stats_get_strings,
2499 .stats_get_stats = mv88e6095_stats_get_stats,
2500 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2501 .set_egress_port = mv88e6095_g1_set_egress_port,
2502 .watchdog_ops = &mv88e6097_watchdog_ops,
2503 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2504 .pot_clear = mv88e6xxx_g2_pot_clear,
2505 .reset = mv88e6352_g1_reset,
2506 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2507 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2510 static const struct mv88e6xxx_ops mv88e6165_ops = {
2511 /* MV88E6XXX_FAMILY_6165 */
2512 .irl_init_all = mv88e6352_g2_irl_init_all,
2513 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2514 .phy_read = mv88e6165_phy_read,
2515 .phy_write = mv88e6165_phy_write,
2516 .port_set_link = mv88e6xxx_port_set_link,
2517 .port_set_duplex = mv88e6xxx_port_set_duplex,
2518 .port_set_speed = mv88e6185_port_set_speed,
2519 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2520 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2521 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2522 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2523 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2524 .stats_get_strings = mv88e6095_stats_get_strings,
2525 .stats_get_stats = mv88e6095_stats_get_stats,
2526 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2527 .set_egress_port = mv88e6095_g1_set_egress_port,
2528 .watchdog_ops = &mv88e6097_watchdog_ops,
2529 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2530 .pot_clear = mv88e6xxx_g2_pot_clear,
2531 .reset = mv88e6352_g1_reset,
2532 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2533 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2536 static const struct mv88e6xxx_ops mv88e6171_ops = {
2537 /* MV88E6XXX_FAMILY_6351 */
2538 .irl_init_all = mv88e6352_g2_irl_init_all,
2539 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2540 .phy_read = mv88e6xxx_g2_smi_phy_read,
2541 .phy_write = mv88e6xxx_g2_smi_phy_write,
2542 .port_set_link = mv88e6xxx_port_set_link,
2543 .port_set_duplex = mv88e6xxx_port_set_duplex,
2544 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2545 .port_set_speed = mv88e6185_port_set_speed,
2546 .port_tag_remap = mv88e6095_port_tag_remap,
2547 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2548 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2549 .port_set_ether_type = mv88e6351_port_set_ether_type,
2550 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2551 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2552 .port_pause_limit = mv88e6097_port_pause_limit,
2553 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2554 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2555 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2556 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2557 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2558 .stats_get_strings = mv88e6095_stats_get_strings,
2559 .stats_get_stats = mv88e6095_stats_get_stats,
2560 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2561 .set_egress_port = mv88e6095_g1_set_egress_port,
2562 .watchdog_ops = &mv88e6097_watchdog_ops,
2563 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2564 .pot_clear = mv88e6xxx_g2_pot_clear,
2565 .reset = mv88e6352_g1_reset,
2566 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2567 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2570 static const struct mv88e6xxx_ops mv88e6172_ops = {
2571 /* MV88E6XXX_FAMILY_6352 */
2572 .irl_init_all = mv88e6352_g2_irl_init_all,
2573 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2574 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2575 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2576 .phy_read = mv88e6xxx_g2_smi_phy_read,
2577 .phy_write = mv88e6xxx_g2_smi_phy_write,
2578 .port_set_link = mv88e6xxx_port_set_link,
2579 .port_set_duplex = mv88e6xxx_port_set_duplex,
2580 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2581 .port_set_speed = mv88e6352_port_set_speed,
2582 .port_tag_remap = mv88e6095_port_tag_remap,
2583 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2584 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2585 .port_set_ether_type = mv88e6351_port_set_ether_type,
2586 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2587 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2588 .port_pause_limit = mv88e6097_port_pause_limit,
2589 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2590 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2591 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2592 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2593 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2594 .stats_get_strings = mv88e6095_stats_get_strings,
2595 .stats_get_stats = mv88e6095_stats_get_stats,
2596 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2597 .set_egress_port = mv88e6095_g1_set_egress_port,
2598 .watchdog_ops = &mv88e6097_watchdog_ops,
2599 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2600 .pot_clear = mv88e6xxx_g2_pot_clear,
2601 .reset = mv88e6352_g1_reset,
2602 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2603 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2604 .serdes_power = mv88e6352_serdes_power,
2607 static const struct mv88e6xxx_ops mv88e6175_ops = {
2608 /* MV88E6XXX_FAMILY_6351 */
2609 .irl_init_all = mv88e6352_g2_irl_init_all,
2610 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2611 .phy_read = mv88e6xxx_g2_smi_phy_read,
2612 .phy_write = mv88e6xxx_g2_smi_phy_write,
2613 .port_set_link = mv88e6xxx_port_set_link,
2614 .port_set_duplex = mv88e6xxx_port_set_duplex,
2615 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2616 .port_set_speed = mv88e6185_port_set_speed,
2617 .port_tag_remap = mv88e6095_port_tag_remap,
2618 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2619 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2620 .port_set_ether_type = mv88e6351_port_set_ether_type,
2621 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2622 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2623 .port_pause_limit = mv88e6097_port_pause_limit,
2624 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2625 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2626 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2627 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2628 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2629 .stats_get_strings = mv88e6095_stats_get_strings,
2630 .stats_get_stats = mv88e6095_stats_get_stats,
2631 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2632 .set_egress_port = mv88e6095_g1_set_egress_port,
2633 .watchdog_ops = &mv88e6097_watchdog_ops,
2634 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2635 .pot_clear = mv88e6xxx_g2_pot_clear,
2636 .reset = mv88e6352_g1_reset,
2637 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2638 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2641 static const struct mv88e6xxx_ops mv88e6176_ops = {
2642 /* MV88E6XXX_FAMILY_6352 */
2643 .irl_init_all = mv88e6352_g2_irl_init_all,
2644 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2645 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2646 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2647 .phy_read = mv88e6xxx_g2_smi_phy_read,
2648 .phy_write = mv88e6xxx_g2_smi_phy_write,
2649 .port_set_link = mv88e6xxx_port_set_link,
2650 .port_set_duplex = mv88e6xxx_port_set_duplex,
2651 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2652 .port_set_speed = mv88e6352_port_set_speed,
2653 .port_tag_remap = mv88e6095_port_tag_remap,
2654 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2655 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2656 .port_set_ether_type = mv88e6351_port_set_ether_type,
2657 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2658 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2659 .port_pause_limit = mv88e6097_port_pause_limit,
2660 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2661 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2662 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2663 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2664 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2665 .stats_get_strings = mv88e6095_stats_get_strings,
2666 .stats_get_stats = mv88e6095_stats_get_stats,
2667 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2668 .set_egress_port = mv88e6095_g1_set_egress_port,
2669 .watchdog_ops = &mv88e6097_watchdog_ops,
2670 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2671 .pot_clear = mv88e6xxx_g2_pot_clear,
2672 .reset = mv88e6352_g1_reset,
2673 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2674 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2675 .serdes_power = mv88e6352_serdes_power,
2678 static const struct mv88e6xxx_ops mv88e6185_ops = {
2679 /* MV88E6XXX_FAMILY_6185 */
2680 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2681 .phy_read = mv88e6185_phy_ppu_read,
2682 .phy_write = mv88e6185_phy_ppu_write,
2683 .port_set_link = mv88e6xxx_port_set_link,
2684 .port_set_duplex = mv88e6xxx_port_set_duplex,
2685 .port_set_speed = mv88e6185_port_set_speed,
2686 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2687 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2688 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2689 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2690 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2691 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2692 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2693 .stats_get_strings = mv88e6095_stats_get_strings,
2694 .stats_get_stats = mv88e6095_stats_get_stats,
2695 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2696 .set_egress_port = mv88e6095_g1_set_egress_port,
2697 .watchdog_ops = &mv88e6097_watchdog_ops,
2698 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2699 .ppu_enable = mv88e6185_g1_ppu_enable,
2700 .ppu_disable = mv88e6185_g1_ppu_disable,
2701 .reset = mv88e6185_g1_reset,
2702 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2703 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2706 static const struct mv88e6xxx_ops mv88e6190_ops = {
2707 /* MV88E6XXX_FAMILY_6390 */
2708 .irl_init_all = mv88e6390_g2_irl_init_all,
2709 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2710 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2711 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2712 .phy_read = mv88e6xxx_g2_smi_phy_read,
2713 .phy_write = mv88e6xxx_g2_smi_phy_write,
2714 .port_set_link = mv88e6xxx_port_set_link,
2715 .port_set_duplex = mv88e6xxx_port_set_duplex,
2716 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2717 .port_set_speed = mv88e6390_port_set_speed,
2718 .port_tag_remap = mv88e6390_port_tag_remap,
2719 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2720 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2721 .port_set_ether_type = mv88e6351_port_set_ether_type,
2722 .port_pause_limit = mv88e6390_port_pause_limit,
2723 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2724 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2725 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2726 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2727 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2728 .stats_get_strings = mv88e6320_stats_get_strings,
2729 .stats_get_stats = mv88e6390_stats_get_stats,
2730 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2731 .set_egress_port = mv88e6390_g1_set_egress_port,
2732 .watchdog_ops = &mv88e6390_watchdog_ops,
2733 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2734 .pot_clear = mv88e6xxx_g2_pot_clear,
2735 .reset = mv88e6352_g1_reset,
2736 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2737 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2738 .serdes_power = mv88e6390_serdes_power,
2741 static const struct mv88e6xxx_ops mv88e6190x_ops = {
2742 /* MV88E6XXX_FAMILY_6390 */
2743 .irl_init_all = mv88e6390_g2_irl_init_all,
2744 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2745 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2746 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2747 .phy_read = mv88e6xxx_g2_smi_phy_read,
2748 .phy_write = mv88e6xxx_g2_smi_phy_write,
2749 .port_set_link = mv88e6xxx_port_set_link,
2750 .port_set_duplex = mv88e6xxx_port_set_duplex,
2751 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2752 .port_set_speed = mv88e6390x_port_set_speed,
2753 .port_tag_remap = mv88e6390_port_tag_remap,
2754 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2755 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2756 .port_set_ether_type = mv88e6351_port_set_ether_type,
2757 .port_pause_limit = mv88e6390_port_pause_limit,
2758 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2759 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2760 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2761 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2762 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2763 .stats_get_strings = mv88e6320_stats_get_strings,
2764 .stats_get_stats = mv88e6390_stats_get_stats,
2765 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2766 .set_egress_port = mv88e6390_g1_set_egress_port,
2767 .watchdog_ops = &mv88e6390_watchdog_ops,
2768 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2769 .pot_clear = mv88e6xxx_g2_pot_clear,
2770 .reset = mv88e6352_g1_reset,
2771 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2772 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2773 .serdes_power = mv88e6390_serdes_power,
2776 static const struct mv88e6xxx_ops mv88e6191_ops = {
2777 /* MV88E6XXX_FAMILY_6390 */
2778 .irl_init_all = mv88e6390_g2_irl_init_all,
2779 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2780 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2781 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2782 .phy_read = mv88e6xxx_g2_smi_phy_read,
2783 .phy_write = mv88e6xxx_g2_smi_phy_write,
2784 .port_set_link = mv88e6xxx_port_set_link,
2785 .port_set_duplex = mv88e6xxx_port_set_duplex,
2786 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2787 .port_set_speed = mv88e6390_port_set_speed,
2788 .port_tag_remap = mv88e6390_port_tag_remap,
2789 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2790 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2791 .port_set_ether_type = mv88e6351_port_set_ether_type,
2792 .port_pause_limit = mv88e6390_port_pause_limit,
2793 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2794 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2795 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2796 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2797 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2798 .stats_get_strings = mv88e6320_stats_get_strings,
2799 .stats_get_stats = mv88e6390_stats_get_stats,
2800 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2801 .set_egress_port = mv88e6390_g1_set_egress_port,
2802 .watchdog_ops = &mv88e6390_watchdog_ops,
2803 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2804 .pot_clear = mv88e6xxx_g2_pot_clear,
2805 .reset = mv88e6352_g1_reset,
2806 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2807 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2808 .serdes_power = mv88e6390_serdes_power,
2811 static const struct mv88e6xxx_ops mv88e6240_ops = {
2812 /* MV88E6XXX_FAMILY_6352 */
2813 .irl_init_all = mv88e6352_g2_irl_init_all,
2814 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2815 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2816 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2817 .phy_read = mv88e6xxx_g2_smi_phy_read,
2818 .phy_write = mv88e6xxx_g2_smi_phy_write,
2819 .port_set_link = mv88e6xxx_port_set_link,
2820 .port_set_duplex = mv88e6xxx_port_set_duplex,
2821 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2822 .port_set_speed = mv88e6352_port_set_speed,
2823 .port_tag_remap = mv88e6095_port_tag_remap,
2824 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2825 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2826 .port_set_ether_type = mv88e6351_port_set_ether_type,
2827 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2828 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2829 .port_pause_limit = mv88e6097_port_pause_limit,
2830 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2831 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2832 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2833 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2834 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2835 .stats_get_strings = mv88e6095_stats_get_strings,
2836 .stats_get_stats = mv88e6095_stats_get_stats,
2837 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2838 .set_egress_port = mv88e6095_g1_set_egress_port,
2839 .watchdog_ops = &mv88e6097_watchdog_ops,
2840 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2841 .pot_clear = mv88e6xxx_g2_pot_clear,
2842 .reset = mv88e6352_g1_reset,
2843 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2844 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2845 .serdes_power = mv88e6352_serdes_power,
2848 static const struct mv88e6xxx_ops mv88e6290_ops = {
2849 /* MV88E6XXX_FAMILY_6390 */
2850 .irl_init_all = mv88e6390_g2_irl_init_all,
2851 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2852 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2853 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2854 .phy_read = mv88e6xxx_g2_smi_phy_read,
2855 .phy_write = mv88e6xxx_g2_smi_phy_write,
2856 .port_set_link = mv88e6xxx_port_set_link,
2857 .port_set_duplex = mv88e6xxx_port_set_duplex,
2858 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2859 .port_set_speed = mv88e6390_port_set_speed,
2860 .port_tag_remap = mv88e6390_port_tag_remap,
2861 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2862 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2863 .port_set_ether_type = mv88e6351_port_set_ether_type,
2864 .port_pause_limit = mv88e6390_port_pause_limit,
2865 .port_set_cmode = mv88e6390x_port_set_cmode,
2866 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2867 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2868 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2869 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2870 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2871 .stats_get_strings = mv88e6320_stats_get_strings,
2872 .stats_get_stats = mv88e6390_stats_get_stats,
2873 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2874 .set_egress_port = mv88e6390_g1_set_egress_port,
2875 .watchdog_ops = &mv88e6390_watchdog_ops,
2876 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2877 .pot_clear = mv88e6xxx_g2_pot_clear,
2878 .reset = mv88e6352_g1_reset,
2879 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2880 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2881 .serdes_power = mv88e6390_serdes_power,
2884 static const struct mv88e6xxx_ops mv88e6320_ops = {
2885 /* MV88E6XXX_FAMILY_6320 */
2886 .irl_init_all = mv88e6352_g2_irl_init_all,
2887 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2888 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2889 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2890 .phy_read = mv88e6xxx_g2_smi_phy_read,
2891 .phy_write = mv88e6xxx_g2_smi_phy_write,
2892 .port_set_link = mv88e6xxx_port_set_link,
2893 .port_set_duplex = mv88e6xxx_port_set_duplex,
2894 .port_set_speed = mv88e6185_port_set_speed,
2895 .port_tag_remap = mv88e6095_port_tag_remap,
2896 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2897 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2898 .port_set_ether_type = mv88e6351_port_set_ether_type,
2899 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2900 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2901 .port_pause_limit = mv88e6097_port_pause_limit,
2902 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2903 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2904 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2905 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2906 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2907 .stats_get_strings = mv88e6320_stats_get_strings,
2908 .stats_get_stats = mv88e6320_stats_get_stats,
2909 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2910 .set_egress_port = mv88e6095_g1_set_egress_port,
2911 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2912 .pot_clear = mv88e6xxx_g2_pot_clear,
2913 .reset = mv88e6352_g1_reset,
2914 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2915 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2918 static const struct mv88e6xxx_ops mv88e6321_ops = {
2919 /* MV88E6XXX_FAMILY_6320 */
2920 .irl_init_all = mv88e6352_g2_irl_init_all,
2921 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2922 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2923 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2924 .phy_read = mv88e6xxx_g2_smi_phy_read,
2925 .phy_write = mv88e6xxx_g2_smi_phy_write,
2926 .port_set_link = mv88e6xxx_port_set_link,
2927 .port_set_duplex = mv88e6xxx_port_set_duplex,
2928 .port_set_speed = mv88e6185_port_set_speed,
2929 .port_tag_remap = mv88e6095_port_tag_remap,
2930 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2931 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2932 .port_set_ether_type = mv88e6351_port_set_ether_type,
2933 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2934 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2935 .port_pause_limit = mv88e6097_port_pause_limit,
2936 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2937 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2938 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2939 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2940 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2941 .stats_get_strings = mv88e6320_stats_get_strings,
2942 .stats_get_stats = mv88e6320_stats_get_stats,
2943 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2944 .set_egress_port = mv88e6095_g1_set_egress_port,
2945 .reset = mv88e6352_g1_reset,
2946 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2947 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2950 static const struct mv88e6xxx_ops mv88e6341_ops = {
2951 /* MV88E6XXX_FAMILY_6341 */
2952 .irl_init_all = mv88e6352_g2_irl_init_all,
2953 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2954 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2955 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2956 .phy_read = mv88e6xxx_g2_smi_phy_read,
2957 .phy_write = mv88e6xxx_g2_smi_phy_write,
2958 .port_set_link = mv88e6xxx_port_set_link,
2959 .port_set_duplex = mv88e6xxx_port_set_duplex,
2960 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2961 .port_set_speed = mv88e6390_port_set_speed,
2962 .port_tag_remap = mv88e6095_port_tag_remap,
2963 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2964 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2965 .port_set_ether_type = mv88e6351_port_set_ether_type,
2966 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2967 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2968 .port_pause_limit = mv88e6097_port_pause_limit,
2969 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2970 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2971 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2972 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2973 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2974 .stats_get_strings = mv88e6320_stats_get_strings,
2975 .stats_get_stats = mv88e6390_stats_get_stats,
2976 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2977 .set_egress_port = mv88e6390_g1_set_egress_port,
2978 .watchdog_ops = &mv88e6390_watchdog_ops,
2979 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2980 .pot_clear = mv88e6xxx_g2_pot_clear,
2981 .reset = mv88e6352_g1_reset,
2982 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2983 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2986 static const struct mv88e6xxx_ops mv88e6350_ops = {
2987 /* MV88E6XXX_FAMILY_6351 */
2988 .irl_init_all = mv88e6352_g2_irl_init_all,
2989 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2990 .phy_read = mv88e6xxx_g2_smi_phy_read,
2991 .phy_write = mv88e6xxx_g2_smi_phy_write,
2992 .port_set_link = mv88e6xxx_port_set_link,
2993 .port_set_duplex = mv88e6xxx_port_set_duplex,
2994 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2995 .port_set_speed = mv88e6185_port_set_speed,
2996 .port_tag_remap = mv88e6095_port_tag_remap,
2997 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2998 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2999 .port_set_ether_type = mv88e6351_port_set_ether_type,
3000 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3001 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3002 .port_pause_limit = mv88e6097_port_pause_limit,
3003 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3004 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3005 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3006 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3007 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3008 .stats_get_strings = mv88e6095_stats_get_strings,
3009 .stats_get_stats = mv88e6095_stats_get_stats,
3010 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3011 .set_egress_port = mv88e6095_g1_set_egress_port,
3012 .watchdog_ops = &mv88e6097_watchdog_ops,
3013 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3014 .pot_clear = mv88e6xxx_g2_pot_clear,
3015 .reset = mv88e6352_g1_reset,
3016 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3017 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3020 static const struct mv88e6xxx_ops mv88e6351_ops = {
3021 /* MV88E6XXX_FAMILY_6351 */
3022 .irl_init_all = mv88e6352_g2_irl_init_all,
3023 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3024 .phy_read = mv88e6xxx_g2_smi_phy_read,
3025 .phy_write = mv88e6xxx_g2_smi_phy_write,
3026 .port_set_link = mv88e6xxx_port_set_link,
3027 .port_set_duplex = mv88e6xxx_port_set_duplex,
3028 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3029 .port_set_speed = mv88e6185_port_set_speed,
3030 .port_tag_remap = mv88e6095_port_tag_remap,
3031 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3032 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3033 .port_set_ether_type = mv88e6351_port_set_ether_type,
3034 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3035 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3036 .port_pause_limit = mv88e6097_port_pause_limit,
3037 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3038 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3039 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3040 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3041 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3042 .stats_get_strings = mv88e6095_stats_get_strings,
3043 .stats_get_stats = mv88e6095_stats_get_stats,
3044 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3045 .set_egress_port = mv88e6095_g1_set_egress_port,
3046 .watchdog_ops = &mv88e6097_watchdog_ops,
3047 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3048 .pot_clear = mv88e6xxx_g2_pot_clear,
3049 .reset = mv88e6352_g1_reset,
3050 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3051 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3054 static const struct mv88e6xxx_ops mv88e6352_ops = {
3055 /* MV88E6XXX_FAMILY_6352 */
3056 .irl_init_all = mv88e6352_g2_irl_init_all,
3057 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3058 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3059 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3060 .phy_read = mv88e6xxx_g2_smi_phy_read,
3061 .phy_write = mv88e6xxx_g2_smi_phy_write,
3062 .port_set_link = mv88e6xxx_port_set_link,
3063 .port_set_duplex = mv88e6xxx_port_set_duplex,
3064 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3065 .port_set_speed = mv88e6352_port_set_speed,
3066 .port_tag_remap = mv88e6095_port_tag_remap,
3067 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3068 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3069 .port_set_ether_type = mv88e6351_port_set_ether_type,
3070 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3071 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3072 .port_pause_limit = mv88e6097_port_pause_limit,
3073 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3074 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3075 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3076 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3077 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3078 .stats_get_strings = mv88e6095_stats_get_strings,
3079 .stats_get_stats = mv88e6095_stats_get_stats,
3080 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3081 .set_egress_port = mv88e6095_g1_set_egress_port,
3082 .watchdog_ops = &mv88e6097_watchdog_ops,
3083 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3084 .pot_clear = mv88e6xxx_g2_pot_clear,
3085 .reset = mv88e6352_g1_reset,
3086 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3087 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3088 .serdes_power = mv88e6352_serdes_power,
3091 static const struct mv88e6xxx_ops mv88e6390_ops = {
3092 /* MV88E6XXX_FAMILY_6390 */
3093 .irl_init_all = mv88e6390_g2_irl_init_all,
3094 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3095 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3096 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3097 .phy_read = mv88e6xxx_g2_smi_phy_read,
3098 .phy_write = mv88e6xxx_g2_smi_phy_write,
3099 .port_set_link = mv88e6xxx_port_set_link,
3100 .port_set_duplex = mv88e6xxx_port_set_duplex,
3101 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3102 .port_set_speed = mv88e6390_port_set_speed,
3103 .port_tag_remap = mv88e6390_port_tag_remap,
3104 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3105 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3106 .port_set_ether_type = mv88e6351_port_set_ether_type,
3107 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3108 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3109 .port_pause_limit = mv88e6390_port_pause_limit,
3110 .port_set_cmode = mv88e6390x_port_set_cmode,
3111 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3112 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3113 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3114 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3115 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3116 .stats_get_strings = mv88e6320_stats_get_strings,
3117 .stats_get_stats = mv88e6390_stats_get_stats,
3118 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3119 .set_egress_port = mv88e6390_g1_set_egress_port,
3120 .watchdog_ops = &mv88e6390_watchdog_ops,
3121 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3122 .pot_clear = mv88e6xxx_g2_pot_clear,
3123 .reset = mv88e6352_g1_reset,
3124 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3125 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3126 .serdes_power = mv88e6390_serdes_power,
3129 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3130 /* MV88E6XXX_FAMILY_6390 */
3131 .irl_init_all = mv88e6390_g2_irl_init_all,
3132 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3133 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3134 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3135 .phy_read = mv88e6xxx_g2_smi_phy_read,
3136 .phy_write = mv88e6xxx_g2_smi_phy_write,
3137 .port_set_link = mv88e6xxx_port_set_link,
3138 .port_set_duplex = mv88e6xxx_port_set_duplex,
3139 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3140 .port_set_speed = mv88e6390x_port_set_speed,
3141 .port_tag_remap = mv88e6390_port_tag_remap,
3142 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3143 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3144 .port_set_ether_type = mv88e6351_port_set_ether_type,
3145 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3146 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3147 .port_pause_limit = mv88e6390_port_pause_limit,
3148 .port_set_cmode = mv88e6390x_port_set_cmode,
3149 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3150 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3151 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3152 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3153 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3154 .stats_get_strings = mv88e6320_stats_get_strings,
3155 .stats_get_stats = mv88e6390_stats_get_stats,
3156 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3157 .set_egress_port = mv88e6390_g1_set_egress_port,
3158 .watchdog_ops = &mv88e6390_watchdog_ops,
3159 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3160 .pot_clear = mv88e6xxx_g2_pot_clear,
3161 .reset = mv88e6352_g1_reset,
3162 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3163 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3164 .serdes_power = mv88e6390_serdes_power,
3167 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3169 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3170 .family = MV88E6XXX_FAMILY_6097,
3171 .name = "Marvell 88E6085",
3172 .num_databases = 4096,
3175 .port_base_addr = 0x10,
3176 .global1_addr = 0x1b,
3177 .global2_addr = 0x1c,
3178 .age_time_coeff = 15000,
3181 .atu_move_port_mask = 0xf,
3184 .tag_protocol = DSA_TAG_PROTO_DSA,
3185 .ops = &mv88e6085_ops,
3189 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3190 .family = MV88E6XXX_FAMILY_6095,
3191 .name = "Marvell 88E6095/88E6095F",
3192 .num_databases = 256,
3195 .port_base_addr = 0x10,
3196 .global1_addr = 0x1b,
3197 .global2_addr = 0x1c,
3198 .age_time_coeff = 15000,
3200 .atu_move_port_mask = 0xf,
3202 .tag_protocol = DSA_TAG_PROTO_DSA,
3203 .ops = &mv88e6095_ops,
3207 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3208 .family = MV88E6XXX_FAMILY_6097,
3209 .name = "Marvell 88E6097/88E6097F",
3210 .num_databases = 4096,
3213 .port_base_addr = 0x10,
3214 .global1_addr = 0x1b,
3215 .global2_addr = 0x1c,
3216 .age_time_coeff = 15000,
3219 .atu_move_port_mask = 0xf,
3222 .tag_protocol = DSA_TAG_PROTO_EDSA,
3223 .ops = &mv88e6097_ops,
3227 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3228 .family = MV88E6XXX_FAMILY_6165,
3229 .name = "Marvell 88E6123",
3230 .num_databases = 4096,
3233 .port_base_addr = 0x10,
3234 .global1_addr = 0x1b,
3235 .global2_addr = 0x1c,
3236 .age_time_coeff = 15000,
3239 .atu_move_port_mask = 0xf,
3242 .tag_protocol = DSA_TAG_PROTO_EDSA,
3243 .ops = &mv88e6123_ops,
3247 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3248 .family = MV88E6XXX_FAMILY_6185,
3249 .name = "Marvell 88E6131",
3250 .num_databases = 256,
3253 .port_base_addr = 0x10,
3254 .global1_addr = 0x1b,
3255 .global2_addr = 0x1c,
3256 .age_time_coeff = 15000,
3258 .atu_move_port_mask = 0xf,
3260 .tag_protocol = DSA_TAG_PROTO_DSA,
3261 .ops = &mv88e6131_ops,
3265 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3266 .family = MV88E6XXX_FAMILY_6341,
3267 .name = "Marvell 88E6341",
3268 .num_databases = 4096,
3271 .port_base_addr = 0x10,
3272 .global1_addr = 0x1b,
3273 .global2_addr = 0x1c,
3274 .age_time_coeff = 3750,
3275 .atu_move_port_mask = 0x1f,
3279 .tag_protocol = DSA_TAG_PROTO_EDSA,
3280 .ops = &mv88e6141_ops,
3284 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3285 .family = MV88E6XXX_FAMILY_6165,
3286 .name = "Marvell 88E6161",
3287 .num_databases = 4096,
3290 .port_base_addr = 0x10,
3291 .global1_addr = 0x1b,
3292 .global2_addr = 0x1c,
3293 .age_time_coeff = 15000,
3296 .atu_move_port_mask = 0xf,
3299 .tag_protocol = DSA_TAG_PROTO_EDSA,
3300 .ops = &mv88e6161_ops,
3304 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3305 .family = MV88E6XXX_FAMILY_6165,
3306 .name = "Marvell 88E6165",
3307 .num_databases = 4096,
3310 .port_base_addr = 0x10,
3311 .global1_addr = 0x1b,
3312 .global2_addr = 0x1c,
3313 .age_time_coeff = 15000,
3316 .atu_move_port_mask = 0xf,
3319 .tag_protocol = DSA_TAG_PROTO_DSA,
3320 .ops = &mv88e6165_ops,
3324 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3325 .family = MV88E6XXX_FAMILY_6351,
3326 .name = "Marvell 88E6171",
3327 .num_databases = 4096,
3330 .port_base_addr = 0x10,
3331 .global1_addr = 0x1b,
3332 .global2_addr = 0x1c,
3333 .age_time_coeff = 15000,
3336 .atu_move_port_mask = 0xf,
3339 .tag_protocol = DSA_TAG_PROTO_EDSA,
3340 .ops = &mv88e6171_ops,
3344 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3345 .family = MV88E6XXX_FAMILY_6352,
3346 .name = "Marvell 88E6172",
3347 .num_databases = 4096,
3350 .port_base_addr = 0x10,
3351 .global1_addr = 0x1b,
3352 .global2_addr = 0x1c,
3353 .age_time_coeff = 15000,
3356 .atu_move_port_mask = 0xf,
3359 .tag_protocol = DSA_TAG_PROTO_EDSA,
3360 .ops = &mv88e6172_ops,
3364 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3365 .family = MV88E6XXX_FAMILY_6351,
3366 .name = "Marvell 88E6175",
3367 .num_databases = 4096,
3370 .port_base_addr = 0x10,
3371 .global1_addr = 0x1b,
3372 .global2_addr = 0x1c,
3373 .age_time_coeff = 15000,
3376 .atu_move_port_mask = 0xf,
3379 .tag_protocol = DSA_TAG_PROTO_EDSA,
3380 .ops = &mv88e6175_ops,
3384 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3385 .family = MV88E6XXX_FAMILY_6352,
3386 .name = "Marvell 88E6176",
3387 .num_databases = 4096,
3390 .port_base_addr = 0x10,
3391 .global1_addr = 0x1b,
3392 .global2_addr = 0x1c,
3393 .age_time_coeff = 15000,
3396 .atu_move_port_mask = 0xf,
3399 .tag_protocol = DSA_TAG_PROTO_EDSA,
3400 .ops = &mv88e6176_ops,
3404 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3405 .family = MV88E6XXX_FAMILY_6185,
3406 .name = "Marvell 88E6185",
3407 .num_databases = 256,
3410 .port_base_addr = 0x10,
3411 .global1_addr = 0x1b,
3412 .global2_addr = 0x1c,
3413 .age_time_coeff = 15000,
3415 .atu_move_port_mask = 0xf,
3417 .tag_protocol = DSA_TAG_PROTO_EDSA,
3418 .ops = &mv88e6185_ops,
3422 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3423 .family = MV88E6XXX_FAMILY_6390,
3424 .name = "Marvell 88E6190",
3425 .num_databases = 4096,
3426 .num_ports = 11, /* 10 + Z80 */
3428 .port_base_addr = 0x0,
3429 .global1_addr = 0x1b,
3430 .global2_addr = 0x1c,
3431 .tag_protocol = DSA_TAG_PROTO_DSA,
3432 .age_time_coeff = 3750,
3437 .atu_move_port_mask = 0x1f,
3438 .ops = &mv88e6190_ops,
3442 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3443 .family = MV88E6XXX_FAMILY_6390,
3444 .name = "Marvell 88E6190X",
3445 .num_databases = 4096,
3446 .num_ports = 11, /* 10 + Z80 */
3448 .port_base_addr = 0x0,
3449 .global1_addr = 0x1b,
3450 .global2_addr = 0x1c,
3451 .age_time_coeff = 3750,
3454 .atu_move_port_mask = 0x1f,
3457 .tag_protocol = DSA_TAG_PROTO_DSA,
3458 .ops = &mv88e6190x_ops,
3462 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3463 .family = MV88E6XXX_FAMILY_6390,
3464 .name = "Marvell 88E6191",
3465 .num_databases = 4096,
3466 .num_ports = 11, /* 10 + Z80 */
3468 .port_base_addr = 0x0,
3469 .global1_addr = 0x1b,
3470 .global2_addr = 0x1c,
3471 .age_time_coeff = 3750,
3474 .atu_move_port_mask = 0x1f,
3477 .tag_protocol = DSA_TAG_PROTO_DSA,
3478 .ops = &mv88e6191_ops,
3482 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3483 .family = MV88E6XXX_FAMILY_6352,
3484 .name = "Marvell 88E6240",
3485 .num_databases = 4096,
3488 .port_base_addr = 0x10,
3489 .global1_addr = 0x1b,
3490 .global2_addr = 0x1c,
3491 .age_time_coeff = 15000,
3494 .atu_move_port_mask = 0xf,
3497 .tag_protocol = DSA_TAG_PROTO_EDSA,
3498 .ops = &mv88e6240_ops,
3502 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3503 .family = MV88E6XXX_FAMILY_6390,
3504 .name = "Marvell 88E6290",
3505 .num_databases = 4096,
3506 .num_ports = 11, /* 10 + Z80 */
3508 .port_base_addr = 0x0,
3509 .global1_addr = 0x1b,
3510 .global2_addr = 0x1c,
3511 .age_time_coeff = 3750,
3514 .atu_move_port_mask = 0x1f,
3517 .tag_protocol = DSA_TAG_PROTO_DSA,
3518 .ops = &mv88e6290_ops,
3522 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3523 .family = MV88E6XXX_FAMILY_6320,
3524 .name = "Marvell 88E6320",
3525 .num_databases = 4096,
3528 .port_base_addr = 0x10,
3529 .global1_addr = 0x1b,
3530 .global2_addr = 0x1c,
3531 .age_time_coeff = 15000,
3533 .atu_move_port_mask = 0xf,
3536 .tag_protocol = DSA_TAG_PROTO_EDSA,
3537 .ops = &mv88e6320_ops,
3541 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3542 .family = MV88E6XXX_FAMILY_6320,
3543 .name = "Marvell 88E6321",
3544 .num_databases = 4096,
3547 .port_base_addr = 0x10,
3548 .global1_addr = 0x1b,
3549 .global2_addr = 0x1c,
3550 .age_time_coeff = 15000,
3552 .atu_move_port_mask = 0xf,
3554 .tag_protocol = DSA_TAG_PROTO_EDSA,
3555 .ops = &mv88e6321_ops,
3559 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3560 .family = MV88E6XXX_FAMILY_6341,
3561 .name = "Marvell 88E6341",
3562 .num_databases = 4096,
3565 .port_base_addr = 0x10,
3566 .global1_addr = 0x1b,
3567 .global2_addr = 0x1c,
3568 .age_time_coeff = 3750,
3569 .atu_move_port_mask = 0x1f,
3573 .tag_protocol = DSA_TAG_PROTO_EDSA,
3574 .ops = &mv88e6341_ops,
3578 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3579 .family = MV88E6XXX_FAMILY_6351,
3580 .name = "Marvell 88E6350",
3581 .num_databases = 4096,
3584 .port_base_addr = 0x10,
3585 .global1_addr = 0x1b,
3586 .global2_addr = 0x1c,
3587 .age_time_coeff = 15000,
3590 .atu_move_port_mask = 0xf,
3593 .tag_protocol = DSA_TAG_PROTO_EDSA,
3594 .ops = &mv88e6350_ops,
3598 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3599 .family = MV88E6XXX_FAMILY_6351,
3600 .name = "Marvell 88E6351",
3601 .num_databases = 4096,
3604 .port_base_addr = 0x10,
3605 .global1_addr = 0x1b,
3606 .global2_addr = 0x1c,
3607 .age_time_coeff = 15000,
3610 .atu_move_port_mask = 0xf,
3613 .tag_protocol = DSA_TAG_PROTO_EDSA,
3614 .ops = &mv88e6351_ops,
3618 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3619 .family = MV88E6XXX_FAMILY_6352,
3620 .name = "Marvell 88E6352",
3621 .num_databases = 4096,
3624 .port_base_addr = 0x10,
3625 .global1_addr = 0x1b,
3626 .global2_addr = 0x1c,
3627 .age_time_coeff = 15000,
3630 .atu_move_port_mask = 0xf,
3633 .tag_protocol = DSA_TAG_PROTO_EDSA,
3634 .ops = &mv88e6352_ops,
3637 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3638 .family = MV88E6XXX_FAMILY_6390,
3639 .name = "Marvell 88E6390",
3640 .num_databases = 4096,
3641 .num_ports = 11, /* 10 + Z80 */
3643 .port_base_addr = 0x0,
3644 .global1_addr = 0x1b,
3645 .global2_addr = 0x1c,
3646 .age_time_coeff = 3750,
3649 .atu_move_port_mask = 0x1f,
3652 .tag_protocol = DSA_TAG_PROTO_DSA,
3653 .ops = &mv88e6390_ops,
3656 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3657 .family = MV88E6XXX_FAMILY_6390,
3658 .name = "Marvell 88E6390X",
3659 .num_databases = 4096,
3660 .num_ports = 11, /* 10 + Z80 */
3662 .port_base_addr = 0x0,
3663 .global1_addr = 0x1b,
3664 .global2_addr = 0x1c,
3665 .age_time_coeff = 3750,
3668 .atu_move_port_mask = 0x1f,
3671 .tag_protocol = DSA_TAG_PROTO_DSA,
3672 .ops = &mv88e6390x_ops,
3676 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3680 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3681 if (mv88e6xxx_table[i].prod_num == prod_num)
3682 return &mv88e6xxx_table[i];
3687 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3689 const struct mv88e6xxx_info *info;
3690 unsigned int prod_num, rev;
3694 mutex_lock(&chip->reg_lock);
3695 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3696 mutex_unlock(&chip->reg_lock);
3700 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3701 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3703 info = mv88e6xxx_lookup_info(prod_num);
3707 /* Update the compatible info with the probed one */
3710 err = mv88e6xxx_g2_require(chip);
3714 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3715 chip->info->prod_num, chip->info->name, rev);
3720 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3722 struct mv88e6xxx_chip *chip;
3724 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3730 mutex_init(&chip->reg_lock);
3731 INIT_LIST_HEAD(&chip->mdios);
3736 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3737 struct mii_bus *bus, int sw_addr)
3740 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3741 else if (chip->info->multi_chip)
3742 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3747 chip->sw_addr = sw_addr;
3752 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
3755 struct mv88e6xxx_chip *chip = ds->priv;
3757 return chip->info->tag_protocol;
3760 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3761 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3762 struct device *host_dev, int sw_addr,
3765 struct mv88e6xxx_chip *chip;
3766 struct mii_bus *bus;
3769 bus = dsa_host_dev_to_mii_bus(host_dev);
3773 chip = mv88e6xxx_alloc_chip(dsa_dev);
3777 /* Legacy SMI probing will only support chips similar to 88E6085 */
3778 chip->info = &mv88e6xxx_table[MV88E6085];
3780 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3784 err = mv88e6xxx_detect(chip);
3788 mutex_lock(&chip->reg_lock);
3789 err = mv88e6xxx_switch_reset(chip);
3790 mutex_unlock(&chip->reg_lock);
3794 mv88e6xxx_phy_init(chip);
3796 err = mv88e6xxx_mdios_register(chip, NULL);
3802 return chip->info->name;
3804 devm_kfree(dsa_dev, chip);
3810 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3811 const struct switchdev_obj_port_mdb *mdb)
3813 /* We don't need any dynamic resource from the kernel (yet),
3814 * so skip the prepare phase.
3820 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3821 const struct switchdev_obj_port_mdb *mdb)
3823 struct mv88e6xxx_chip *chip = ds->priv;
3825 mutex_lock(&chip->reg_lock);
3826 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3827 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
3828 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3830 mutex_unlock(&chip->reg_lock);
3833 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3834 const struct switchdev_obj_port_mdb *mdb)
3836 struct mv88e6xxx_chip *chip = ds->priv;
3839 mutex_lock(&chip->reg_lock);
3840 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3841 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
3842 mutex_unlock(&chip->reg_lock);
3847 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
3848 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3849 .probe = mv88e6xxx_drv_probe,
3851 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
3852 .setup = mv88e6xxx_setup,
3853 .adjust_link = mv88e6xxx_adjust_link,
3854 .get_strings = mv88e6xxx_get_strings,
3855 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3856 .get_sset_count = mv88e6xxx_get_sset_count,
3857 .port_enable = mv88e6xxx_port_enable,
3858 .port_disable = mv88e6xxx_port_disable,
3859 .get_mac_eee = mv88e6xxx_get_mac_eee,
3860 .set_mac_eee = mv88e6xxx_set_mac_eee,
3861 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3862 .get_eeprom = mv88e6xxx_get_eeprom,
3863 .set_eeprom = mv88e6xxx_set_eeprom,
3864 .get_regs_len = mv88e6xxx_get_regs_len,
3865 .get_regs = mv88e6xxx_get_regs,
3866 .set_ageing_time = mv88e6xxx_set_ageing_time,
3867 .port_bridge_join = mv88e6xxx_port_bridge_join,
3868 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3869 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3870 .port_fast_age = mv88e6xxx_port_fast_age,
3871 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3872 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3873 .port_vlan_add = mv88e6xxx_port_vlan_add,
3874 .port_vlan_del = mv88e6xxx_port_vlan_del,
3875 .port_fdb_add = mv88e6xxx_port_fdb_add,
3876 .port_fdb_del = mv88e6xxx_port_fdb_del,
3877 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3878 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3879 .port_mdb_add = mv88e6xxx_port_mdb_add,
3880 .port_mdb_del = mv88e6xxx_port_mdb_del,
3881 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3882 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
3885 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3886 .ops = &mv88e6xxx_switch_ops,
3889 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
3891 struct device *dev = chip->dev;
3892 struct dsa_switch *ds;
3894 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
3899 ds->ops = &mv88e6xxx_switch_ops;
3900 ds->ageing_time_min = chip->info->age_time_coeff;
3901 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
3903 dev_set_drvdata(dev, ds);
3905 return dsa_register_switch(ds);
3908 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3910 dsa_unregister_switch(chip->ds);
3913 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3915 struct device *dev = &mdiodev->dev;
3916 struct device_node *np = dev->of_node;
3917 const struct mv88e6xxx_info *compat_info;
3918 struct mv88e6xxx_chip *chip;
3922 compat_info = of_device_get_match_data(dev);
3926 chip = mv88e6xxx_alloc_chip(dev);
3930 chip->info = compat_info;
3932 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3936 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
3937 if (IS_ERR(chip->reset))
3938 return PTR_ERR(chip->reset);
3940 err = mv88e6xxx_detect(chip);
3944 mv88e6xxx_phy_init(chip);
3946 if (chip->info->ops->get_eeprom &&
3947 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3948 chip->eeprom_len = eeprom_len;
3950 mutex_lock(&chip->reg_lock);
3951 err = mv88e6xxx_switch_reset(chip);
3952 mutex_unlock(&chip->reg_lock);
3956 chip->irq = of_irq_get(np, 0);
3957 if (chip->irq == -EPROBE_DEFER) {
3962 if (chip->irq > 0) {
3963 /* Has to be performed before the MDIO bus is created,
3964 * because the PHYs will link there interrupts to these
3965 * interrupt controllers
3967 mutex_lock(&chip->reg_lock);
3968 err = mv88e6xxx_g1_irq_setup(chip);
3969 mutex_unlock(&chip->reg_lock);
3974 if (chip->info->g2_irqs > 0) {
3975 err = mv88e6xxx_g2_irq_setup(chip);
3980 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
3985 err = mv88e6xxx_mdios_register(chip, np);
3987 goto out_g1_atu_prob_irq;
3989 err = mv88e6xxx_register_switch(chip);
3996 mv88e6xxx_mdios_unregister(chip);
3997 out_g1_atu_prob_irq:
3998 mv88e6xxx_g1_atu_prob_irq_free(chip);
4000 if (chip->info->g2_irqs > 0 && chip->irq > 0)
4001 mv88e6xxx_g2_irq_free(chip);
4003 if (chip->irq > 0) {
4004 mutex_lock(&chip->reg_lock);
4005 mv88e6xxx_g1_irq_free(chip);
4006 mutex_unlock(&chip->reg_lock);
4012 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4014 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4015 struct mv88e6xxx_chip *chip = ds->priv;
4017 mv88e6xxx_phy_destroy(chip);
4018 mv88e6xxx_unregister_switch(chip);
4019 mv88e6xxx_mdios_unregister(chip);
4021 if (chip->irq > 0) {
4022 mv88e6xxx_g1_atu_prob_irq_free(chip);
4023 if (chip->info->g2_irqs > 0)
4024 mv88e6xxx_g2_irq_free(chip);
4025 mutex_lock(&chip->reg_lock);
4026 mv88e6xxx_g1_irq_free(chip);
4027 mutex_unlock(&chip->reg_lock);
4031 static const struct of_device_id mv88e6xxx_of_match[] = {
4033 .compatible = "marvell,mv88e6085",
4034 .data = &mv88e6xxx_table[MV88E6085],
4037 .compatible = "marvell,mv88e6190",
4038 .data = &mv88e6xxx_table[MV88E6190],
4043 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4045 static struct mdio_driver mv88e6xxx_driver = {
4046 .probe = mv88e6xxx_probe,
4047 .remove = mv88e6xxx_remove,
4049 .name = "mv88e6085",
4050 .of_match_table = mv88e6xxx_of_match,
4054 static int __init mv88e6xxx_init(void)
4056 register_switch_driver(&mv88e6xxx_switch_drv);
4057 return mdio_driver_register(&mv88e6xxx_driver);
4059 module_init(mv88e6xxx_init);
4061 static void __exit mv88e6xxx_cleanup(void)
4063 mdio_driver_unregister(&mv88e6xxx_driver);
4064 unregister_switch_driver(&mv88e6xxx_switch_drv);
4066 module_exit(mv88e6xxx_cleanup);
4068 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4069 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4070 MODULE_LICENSE("GPL");