2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
43 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
64 int addr, int reg, u16 *val)
69 return chip->smi_ops->read(chip, addr, reg, val);
72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
73 int addr, int reg, u16 val)
78 return chip->smi_ops->write(chip, addr, reg, val);
81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
82 int addr, int reg, u16 *val)
86 ret = mdiobus_read_nested(chip->bus, addr, reg);
95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
96 int addr, int reg, u16 val)
100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
117 for (i = 0; i < 16; i++) {
118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
122 if ((ret & SMI_CMD_BUSY) == 0)
129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
130 int addr, int reg, u16 *val)
134 /* Wait for the bus to become free. */
135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
139 /* Transmit the read command. */
140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
145 /* Wait for the read command to complete. */
146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
161 int addr, int reg, u16 val)
165 /* Wait for the bus to become free. */
166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
170 /* Transmit the data to write. */
171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
175 /* Transmit the write command. */
176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
181 /* Wait for the write command to complete. */
182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
198 assert_reg_lock(chip);
200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
214 assert_reg_lock(chip);
216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
228 struct mv88e6xxx_mdio_bus *mdio_bus;
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
235 return mdio_bus->bus;
238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
243 chip->g1_irq.masked |= (1 << n);
246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
251 chip->g1_irq.masked &= ~(1 << n);
254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
263 mutex_lock(&chip->reg_lock);
264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
265 mutex_unlock(&chip->reg_lock);
270 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
271 if (reg & (1 << n)) {
272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
273 handle_nested_irq(sub_irq);
278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
285 mutex_lock(&chip->reg_lock);
288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
300 reg |= (~chip->g1_irq.masked & mask);
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
307 mutex_unlock(&chip->reg_lock);
310 static struct irq_chip mv88e6xxx_g1_irq_chip = {
311 .name = "mv88e6xxx-g1",
312 .irq_mask = mv88e6xxx_g1_irq_mask,
313 .irq_unmask = mv88e6xxx_g1_irq_unmask,
314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
320 irq_hw_number_t hwirq)
322 struct mv88e6xxx_chip *chip = d->host_data;
324 irq_set_chip_data(irq, d->host_data);
325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
326 irq_set_noprobe(irq);
331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
332 .map = mv88e6xxx_g1_irq_domain_map,
333 .xlate = irq_domain_xlate_twocell,
336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
342 mask |= GENMASK(chip->g1_irq.nirqs, 0);
343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
345 free_irq(chip->irq, chip);
347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
348 virq = irq_find_mapping(chip->g1_irq.domain, irq);
349 irq_dispose_mapping(virq);
352 irq_domain_remove(chip->g1_irq.domain);
355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
360 chip->g1_irq.nirqs = chip->info->g1_irqs;
361 chip->g1_irq.domain = irq_domain_add_simple(
362 NULL, chip->g1_irq.nirqs, 0,
363 &mv88e6xxx_g1_irq_domain_ops, chip);
364 if (!chip->g1_irq.domain)
367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
368 irq_create_mapping(chip->g1_irq.domain, irq);
370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
371 chip->g1_irq.masked = ~0;
373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
383 /* Reading the interrupt status clears (most of) them */
384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
388 err = request_threaded_irq(chip->irq, NULL,
389 mv88e6xxx_g1_irq_thread_fn,
390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
391 dev_name(chip->dev), chip);
398 mask |= GENMASK(chip->g1_irq.nirqs, 0);
399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
402 for (irq = 0; irq < 16; irq++) {
403 virq = irq_find_mapping(chip->g1_irq.domain, irq);
404 irq_dispose_mapping(virq);
407 irq_domain_remove(chip->g1_irq.domain);
412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
416 for (i = 0; i < 16; i++) {
420 err = mv88e6xxx_read(chip, addr, reg, &val);
427 usleep_range(1000, 2000);
430 dev_err(chip->dev, "Timeout while waiting for switch\n");
434 /* Indirect write to single pointer-data register with an Update bit */
435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
440 /* Wait until the previous operation is completed */
441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
445 /* Set the Update bit to trigger a write operation */
446 val = BIT(15) | update;
448 return mv88e6xxx_write(chip, addr, reg, val);
451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452 int link, int speed, int duplex,
453 phy_interface_t mode)
457 if (!chip->info->ops->port_set_link)
460 /* Port's MAC control must not be changed unless the link is down */
461 err = chip->info->ops->port_set_link(chip, port, 0);
465 if (chip->info->ops->port_set_speed) {
466 err = chip->info->ops->port_set_speed(chip, port, speed);
467 if (err && err != -EOPNOTSUPP)
471 if (chip->info->ops->port_set_duplex) {
472 err = chip->info->ops->port_set_duplex(chip, port, duplex);
473 if (err && err != -EOPNOTSUPP)
477 if (chip->info->ops->port_set_rgmii_delay) {
478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
479 if (err && err != -EOPNOTSUPP)
483 if (chip->info->ops->port_set_cmode) {
484 err = chip->info->ops->port_set_cmode(chip, port, mode);
485 if (err && err != -EOPNOTSUPP)
491 if (chip->info->ops->port_set_link(chip, port, link))
492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
497 /* We expect the switch to perform auto negotiation if there is a real
498 * phy. However, in the case of a fixed link phy, we force the port
499 * settings from the fixed link settings.
501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
502 struct phy_device *phydev)
504 struct mv88e6xxx_chip *chip = ds->priv;
507 if (!phy_is_pseudo_fixed_link(phydev))
510 mutex_lock(&chip->reg_lock);
511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
512 phydev->duplex, phydev->interface);
513 mutex_unlock(&chip->reg_lock);
515 if (err && err != -EOPNOTSUPP)
516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
521 if (!chip->info->ops->stats_snapshot)
524 return chip->info->ops->stats_snapshot(chip, port);
527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
548 { "single", 4, 0x14, STATS_TYPE_BANK0, },
549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
551 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
590 struct mv88e6xxx_hw_stat *s,
591 int port, u16 bank1_select,
601 case STATS_TYPE_PORT:
602 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
607 if (s->sizeof_stat == 4) {
608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
614 case STATS_TYPE_BANK1:
617 case STATS_TYPE_BANK0:
618 reg |= s->reg | histogram;
619 mv88e6xxx_g1_stats_read(chip, reg, &low);
620 if (s->sizeof_stat == 8)
621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
626 value = (((u64)high) << 16) | low;
630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
631 uint8_t *data, int types)
633 struct mv88e6xxx_hw_stat *stat;
636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
637 stat = &mv88e6xxx_hw_stats[i];
638 if (stat->type & types) {
639 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
649 mv88e6xxx_stats_get_strings(chip, data,
650 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
656 mv88e6xxx_stats_get_strings(chip, data,
657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
663 struct mv88e6xxx_chip *chip = ds->priv;
665 if (chip->info->ops->stats_get_strings)
666 chip->info->ops->stats_get_strings(chip, data);
669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
672 struct mv88e6xxx_hw_stat *stat;
675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
676 stat = &mv88e6xxx_hw_stats[i];
677 if (stat->type & types)
683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
697 struct mv88e6xxx_chip *chip = ds->priv;
699 if (chip->info->ops->stats_get_sset_count)
700 return chip->info->ops->stats_get_sset_count(chip);
705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
706 uint64_t *data, int types,
707 u16 bank1_select, u16 histogram)
709 struct mv88e6xxx_hw_stat *stat;
712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
713 stat = &mv88e6xxx_hw_stats[i];
714 if (stat->type & types) {
715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
726 return mv88e6xxx_stats_get_stats(chip, port, data,
727 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
734 return mv88e6xxx_stats_get_stats(chip, port, data,
735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
743 return mv88e6xxx_stats_get_stats(chip, port, data,
744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
752 if (chip->info->ops->stats_get_stats)
753 chip->info->ops->stats_get_stats(chip, port, data);
756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
759 struct mv88e6xxx_chip *chip = ds->priv;
762 mutex_lock(&chip->reg_lock);
764 ret = mv88e6xxx_stats_snapshot(chip, port);
766 mutex_unlock(&chip->reg_lock);
770 mv88e6xxx_get_stats(chip, port, data);
772 mutex_unlock(&chip->reg_lock);
775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
777 if (chip->info->ops->stats_set_histogram)
778 return chip->info->ops->stats_set_histogram(chip);
783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
785 return 32 * sizeof(u16);
788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
789 struct ethtool_regs *regs, void *_p)
791 struct mv88e6xxx_chip *chip = ds->priv;
799 memset(p, 0xff, 32 * sizeof(u16));
801 mutex_lock(&chip->reg_lock);
803 for (i = 0; i < 32; i++) {
805 err = mv88e6xxx_port_read(chip, port, i, ®);
810 mutex_unlock(&chip->reg_lock);
813 static int mv88e6xxx_energy_detect_read(struct mv88e6xxx_chip *chip, int port,
814 struct ethtool_eee *eee)
818 if (!chip->info->ops->phy_energy_detect_read)
821 /* assign eee->eee_enabled and eee->tx_lpi_enabled */
822 err = chip->info->ops->phy_energy_detect_read(chip, port, eee);
826 /* assign eee->eee_active */
827 return mv88e6xxx_port_status_eee(chip, port, eee);
830 static int mv88e6xxx_energy_detect_write(struct mv88e6xxx_chip *chip, int port,
831 struct ethtool_eee *eee)
833 if (!chip->info->ops->phy_energy_detect_write)
836 return chip->info->ops->phy_energy_detect_write(chip, port, eee);
839 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
840 struct ethtool_eee *e)
842 struct mv88e6xxx_chip *chip = ds->priv;
845 mutex_lock(&chip->reg_lock);
846 err = mv88e6xxx_energy_detect_read(chip, port, e);
847 mutex_unlock(&chip->reg_lock);
852 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
853 struct phy_device *phydev, struct ethtool_eee *e)
855 struct mv88e6xxx_chip *chip = ds->priv;
858 if (e->eee_enabled) {
859 err = phy_init_eee(phydev, 0);
864 mutex_lock(&chip->reg_lock);
865 err = mv88e6xxx_energy_detect_write(chip, port, e);
866 mutex_unlock(&chip->reg_lock);
871 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
873 struct dsa_switch *ds = NULL;
874 struct net_device *br;
878 if (dev < DSA_MAX_SWITCHES)
879 ds = chip->ds->dst->ds[dev];
881 /* Prevent frames from unknown switch or port */
882 if (!ds || port >= ds->num_ports)
885 /* Frames from DSA links and CPU ports can egress any local port */
886 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
887 return mv88e6xxx_port_mask(chip);
889 br = ds->ports[port].bridge_dev;
892 /* Frames from user ports can egress any local DSA links and CPU ports,
893 * as well as any local member of their bridge group.
895 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
896 if (dsa_is_cpu_port(chip->ds, i) ||
897 dsa_is_dsa_port(chip->ds, i) ||
898 (br && chip->ds->ports[i].bridge_dev == br))
904 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
906 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
908 /* prevent frames from going back out of the port they came in on */
909 output_ports &= ~BIT(port);
911 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
914 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
917 struct mv88e6xxx_chip *chip = ds->priv;
920 mutex_lock(&chip->reg_lock);
921 err = mv88e6xxx_port_set_state(chip, port, state);
922 mutex_unlock(&chip->reg_lock);
925 dev_err(ds->dev, "p%d: failed to update state\n", port);
928 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
930 if (chip->info->ops->pot_clear)
931 return chip->info->ops->pot_clear(chip);
936 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
938 if (chip->info->ops->mgmt_rsvd2cpu)
939 return chip->info->ops->mgmt_rsvd2cpu(chip);
944 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
948 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
952 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
956 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
959 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
964 if (!chip->info->ops->irl_init_all)
967 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
968 /* Disable ingress rate limiting by resetting all per port
969 * ingress rate limit resources to their initial state.
971 err = chip->info->ops->irl_init_all(chip, port);
979 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
983 if (!mv88e6xxx_has_pvt(chip))
986 /* Skip the local source device, which uses in-chip port VLAN */
987 if (dev != chip->ds->index)
988 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
990 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
993 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
998 if (!mv88e6xxx_has_pvt(chip))
1001 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1002 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1004 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1008 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1009 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1010 err = mv88e6xxx_pvt_map(chip, dev, port);
1019 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1021 struct mv88e6xxx_chip *chip = ds->priv;
1024 mutex_lock(&chip->reg_lock);
1025 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1026 mutex_unlock(&chip->reg_lock);
1029 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1032 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1034 if (!chip->info->max_vid)
1037 return mv88e6xxx_g1_vtu_flush(chip);
1040 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1041 struct mv88e6xxx_vtu_entry *entry)
1043 if (!chip->info->ops->vtu_getnext)
1046 return chip->info->ops->vtu_getnext(chip, entry);
1049 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1050 struct mv88e6xxx_vtu_entry *entry)
1052 if (!chip->info->ops->vtu_loadpurge)
1055 return chip->info->ops->vtu_loadpurge(chip, entry);
1058 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1059 struct switchdev_obj_port_vlan *vlan,
1060 switchdev_obj_dump_cb_t *cb)
1062 struct mv88e6xxx_chip *chip = ds->priv;
1063 struct mv88e6xxx_vtu_entry next = {
1064 .vid = chip->info->max_vid,
1069 if (!chip->info->max_vid)
1072 mutex_lock(&chip->reg_lock);
1074 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1079 err = mv88e6xxx_vtu_getnext(chip, &next);
1086 if (next.member[port] ==
1087 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1090 /* reinit and dump this VLAN obj */
1091 vlan->vid_begin = next.vid;
1092 vlan->vid_end = next.vid;
1095 if (next.member[port] ==
1096 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED)
1097 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1099 if (next.vid == pvid)
1100 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1102 err = cb(&vlan->obj);
1105 } while (next.vid < chip->info->max_vid);
1108 mutex_unlock(&chip->reg_lock);
1113 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1115 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1116 struct mv88e6xxx_vtu_entry vlan = {
1117 .vid = chip->info->max_vid,
1121 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1123 /* Set every FID bit used by the (un)bridged ports */
1124 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1125 err = mv88e6xxx_port_get_fid(chip, i, fid);
1129 set_bit(*fid, fid_bitmap);
1132 /* Set every FID bit used by the VLAN entries */
1134 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1141 set_bit(vlan.fid, fid_bitmap);
1142 } while (vlan.vid < chip->info->max_vid);
1144 /* The reset value 0x000 is used to indicate that multiple address
1145 * databases are not needed. Return the next positive available.
1147 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1148 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1151 /* Clear the database */
1152 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1155 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1156 struct mv88e6xxx_vtu_entry *entry, bool new)
1163 entry->vid = vid - 1;
1164 entry->valid = false;
1166 err = mv88e6xxx_vtu_getnext(chip, entry);
1170 if (entry->vid == vid && entry->valid)
1176 /* Initialize a fresh VLAN entry */
1177 memset(entry, 0, sizeof(*entry));
1178 entry->valid = true;
1181 /* Exclude all ports */
1182 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1184 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1186 return mv88e6xxx_atu_new(chip, &entry->fid);
1189 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1193 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1194 u16 vid_begin, u16 vid_end)
1196 struct mv88e6xxx_chip *chip = ds->priv;
1197 struct mv88e6xxx_vtu_entry vlan = {
1198 .vid = vid_begin - 1,
1205 mutex_lock(&chip->reg_lock);
1208 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1215 if (vlan.vid > vid_end)
1218 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1219 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1222 if (!ds->ports[port].netdev)
1225 if (vlan.member[i] ==
1226 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1229 if (ds->ports[i].bridge_dev ==
1230 ds->ports[port].bridge_dev)
1231 break; /* same bridge, check next VLAN */
1233 if (!ds->ports[i].bridge_dev)
1236 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
1238 netdev_name(ds->ports[i].bridge_dev));
1242 } while (vlan.vid < vid_end);
1245 mutex_unlock(&chip->reg_lock);
1250 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1251 bool vlan_filtering)
1253 struct mv88e6xxx_chip *chip = ds->priv;
1254 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1255 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1258 if (!chip->info->max_vid)
1261 mutex_lock(&chip->reg_lock);
1262 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1263 mutex_unlock(&chip->reg_lock);
1269 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1270 const struct switchdev_obj_port_vlan *vlan,
1271 struct switchdev_trans *trans)
1273 struct mv88e6xxx_chip *chip = ds->priv;
1276 if (!chip->info->max_vid)
1279 /* If the requested port doesn't belong to the same bridge as the VLAN
1280 * members, do not support it (yet) and fallback to software VLAN.
1282 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1287 /* We don't need any dynamic resource from the kernel (yet),
1288 * so skip the prepare phase.
1293 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1296 struct mv88e6xxx_vtu_entry vlan;
1299 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1303 vlan.member[port] = member;
1305 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
1308 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1309 const struct switchdev_obj_port_vlan *vlan,
1310 struct switchdev_trans *trans)
1312 struct mv88e6xxx_chip *chip = ds->priv;
1313 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1314 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1318 if (!chip->info->max_vid)
1321 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1322 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1324 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1326 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1328 mutex_lock(&chip->reg_lock);
1330 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1331 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1332 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1333 vid, untagged ? 'u' : 't');
1335 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1336 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1339 mutex_unlock(&chip->reg_lock);
1342 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1345 struct mv88e6xxx_vtu_entry vlan;
1348 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1352 /* Tell switchdev if this VLAN is handled in software */
1353 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1356 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1358 /* keep the VLAN unless all ports are excluded */
1360 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1361 if (vlan.member[i] !=
1362 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1368 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1372 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1375 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1376 const struct switchdev_obj_port_vlan *vlan)
1378 struct mv88e6xxx_chip *chip = ds->priv;
1382 if (!chip->info->max_vid)
1385 mutex_lock(&chip->reg_lock);
1387 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1391 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1392 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1397 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1404 mutex_unlock(&chip->reg_lock);
1409 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1410 const unsigned char *addr, u16 vid,
1413 struct mv88e6xxx_vtu_entry vlan;
1414 struct mv88e6xxx_atu_entry entry;
1417 /* Null VLAN ID corresponds to the port private database */
1419 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1421 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1425 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1426 ether_addr_copy(entry.mac, addr);
1427 eth_addr_dec(entry.mac);
1429 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1433 /* Initialize a fresh ATU entry if it isn't found */
1434 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1435 !ether_addr_equal(entry.mac, addr)) {
1436 memset(&entry, 0, sizeof(entry));
1437 ether_addr_copy(entry.mac, addr);
1440 /* Purge the ATU entry only if no port is using it anymore */
1441 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1442 entry.portvec &= ~BIT(port);
1444 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1446 entry.portvec |= BIT(port);
1447 entry.state = state;
1450 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1453 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1454 const struct switchdev_obj_port_fdb *fdb,
1455 struct switchdev_trans *trans)
1457 /* We don't need any dynamic resource from the kernel (yet),
1458 * so skip the prepare phase.
1463 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1464 const struct switchdev_obj_port_fdb *fdb,
1465 struct switchdev_trans *trans)
1467 struct mv88e6xxx_chip *chip = ds->priv;
1469 mutex_lock(&chip->reg_lock);
1470 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1471 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC))
1472 dev_err(ds->dev, "p%d: failed to load unicast MAC address\n",
1474 mutex_unlock(&chip->reg_lock);
1477 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1478 const struct switchdev_obj_port_fdb *fdb)
1480 struct mv88e6xxx_chip *chip = ds->priv;
1483 mutex_lock(&chip->reg_lock);
1484 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1485 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1486 mutex_unlock(&chip->reg_lock);
1491 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1492 u16 fid, u16 vid, int port,
1493 struct switchdev_obj *obj,
1494 switchdev_obj_dump_cb_t *cb)
1496 struct mv88e6xxx_atu_entry addr;
1499 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1500 eth_broadcast_addr(addr.mac);
1503 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1507 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1510 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1513 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1514 struct switchdev_obj_port_fdb *fdb;
1516 if (!is_unicast_ether_addr(addr.mac))
1519 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
1521 ether_addr_copy(fdb->addr, addr.mac);
1522 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1523 fdb->ndm_state = NUD_NOARP;
1525 fdb->ndm_state = NUD_REACHABLE;
1526 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
1527 struct switchdev_obj_port_mdb *mdb;
1529 if (!is_multicast_ether_addr(addr.mac))
1532 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
1534 ether_addr_copy(mdb->addr, addr.mac);
1542 } while (!is_broadcast_ether_addr(addr.mac));
1547 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1548 struct switchdev_obj *obj,
1549 switchdev_obj_dump_cb_t *cb)
1551 struct mv88e6xxx_vtu_entry vlan = {
1552 .vid = chip->info->max_vid,
1557 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1558 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1562 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
1566 /* Dump VLANs' Filtering Information Databases */
1568 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1575 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1579 } while (vlan.vid < chip->info->max_vid);
1584 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1585 struct switchdev_obj_port_fdb *fdb,
1586 switchdev_obj_dump_cb_t *cb)
1588 struct mv88e6xxx_chip *chip = ds->priv;
1591 mutex_lock(&chip->reg_lock);
1592 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
1593 mutex_unlock(&chip->reg_lock);
1598 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1599 struct net_device *br)
1601 struct dsa_switch *ds;
1606 /* Remap the Port VLAN of each local bridge group member */
1607 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1608 if (chip->ds->ports[port].bridge_dev == br) {
1609 err = mv88e6xxx_port_vlan_map(chip, port);
1615 if (!mv88e6xxx_has_pvt(chip))
1618 /* Remap the Port VLAN of each cross-chip bridge group member */
1619 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1620 ds = chip->ds->dst->ds[dev];
1624 for (port = 0; port < ds->num_ports; ++port) {
1625 if (ds->ports[port].bridge_dev == br) {
1626 err = mv88e6xxx_pvt_map(chip, dev, port);
1636 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1637 struct net_device *br)
1639 struct mv88e6xxx_chip *chip = ds->priv;
1642 mutex_lock(&chip->reg_lock);
1643 err = mv88e6xxx_bridge_map(chip, br);
1644 mutex_unlock(&chip->reg_lock);
1649 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1650 struct net_device *br)
1652 struct mv88e6xxx_chip *chip = ds->priv;
1654 mutex_lock(&chip->reg_lock);
1655 if (mv88e6xxx_bridge_map(chip, br) ||
1656 mv88e6xxx_port_vlan_map(chip, port))
1657 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1658 mutex_unlock(&chip->reg_lock);
1661 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1662 int port, struct net_device *br)
1664 struct mv88e6xxx_chip *chip = ds->priv;
1667 if (!mv88e6xxx_has_pvt(chip))
1670 mutex_lock(&chip->reg_lock);
1671 err = mv88e6xxx_pvt_map(chip, dev, port);
1672 mutex_unlock(&chip->reg_lock);
1677 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1678 int port, struct net_device *br)
1680 struct mv88e6xxx_chip *chip = ds->priv;
1682 if (!mv88e6xxx_has_pvt(chip))
1685 mutex_lock(&chip->reg_lock);
1686 if (mv88e6xxx_pvt_map(chip, dev, port))
1687 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1688 mutex_unlock(&chip->reg_lock);
1691 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1693 if (chip->info->ops->reset)
1694 return chip->info->ops->reset(chip);
1699 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1701 struct gpio_desc *gpiod = chip->reset;
1703 /* If there is a GPIO connected to the reset pin, toggle it */
1705 gpiod_set_value_cansleep(gpiod, 1);
1706 usleep_range(10000, 20000);
1707 gpiod_set_value_cansleep(gpiod, 0);
1708 usleep_range(10000, 20000);
1712 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1716 /* Set all ports to the Disabled state */
1717 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1718 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1723 /* Wait for transmit queues to drain,
1724 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1726 usleep_range(2000, 4000);
1731 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1735 err = mv88e6xxx_disable_ports(chip);
1739 mv88e6xxx_hardware_reset(chip);
1741 return mv88e6xxx_software_reset(chip);
1744 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1745 enum mv88e6xxx_frame_mode frame,
1746 enum mv88e6xxx_egress_mode egress, u16 etype)
1750 if (!chip->info->ops->port_set_frame_mode)
1753 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1757 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1761 if (chip->info->ops->port_set_ether_type)
1762 return chip->info->ops->port_set_ether_type(chip, port, etype);
1767 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1769 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1770 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1771 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1774 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1776 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1777 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1778 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1781 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1783 return mv88e6xxx_set_port_mode(chip, port,
1784 MV88E6XXX_FRAME_MODE_ETHERTYPE,
1785 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1789 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1791 if (dsa_is_dsa_port(chip->ds, port))
1792 return mv88e6xxx_set_port_mode_dsa(chip, port);
1794 if (dsa_is_normal_port(chip->ds, port))
1795 return mv88e6xxx_set_port_mode_normal(chip, port);
1797 /* Setup CPU port mode depending on its supported tag format */
1798 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1799 return mv88e6xxx_set_port_mode_dsa(chip, port);
1801 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1802 return mv88e6xxx_set_port_mode_edsa(chip, port);
1807 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1809 bool message = dsa_is_dsa_port(chip->ds, port);
1811 return mv88e6xxx_port_set_message_port(chip, port, message);
1814 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1816 bool flood = port == dsa_upstream_port(chip->ds);
1818 /* Upstream ports flood frames with unknown unicast or multicast DA */
1819 if (chip->info->ops->port_set_egress_floods)
1820 return chip->info->ops->port_set_egress_floods(chip, port,
1826 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1829 if (chip->info->ops->serdes_power)
1830 return chip->info->ops->serdes_power(chip, port, on);
1835 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1837 struct dsa_switch *ds = chip->ds;
1841 /* MAC Forcing register: don't force link, speed, duplex or flow control
1842 * state to any particular values on physical ports, but force the CPU
1843 * port and all DSA ports to their maximum bandwidth and full duplex.
1845 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1846 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1847 SPEED_MAX, DUPLEX_FULL,
1848 PHY_INTERFACE_MODE_NA);
1850 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1851 SPEED_UNFORCED, DUPLEX_UNFORCED,
1852 PHY_INTERFACE_MODE_NA);
1856 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1857 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1858 * tunneling, determine priority by looking at 802.1p and IP
1859 * priority fields (IP prio has precedence), and set STP state
1862 * If this is the CPU link, use DSA or EDSA tagging depending
1863 * on which tagging mode was configured.
1865 * If this is a link to another switch, use DSA tagging mode.
1867 * If this is the upstream port for this switch, enable
1868 * forwarding of unknown unicasts and multicasts.
1870 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1871 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1872 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1873 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1877 err = mv88e6xxx_setup_port_mode(chip, port);
1881 err = mv88e6xxx_setup_egress_floods(chip, port);
1885 /* Enable the SERDES interface for DSA and CPU ports. Normal
1886 * ports SERDES are enabled when the port is enabled, thus
1887 * saving a bit of power.
1889 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1890 err = mv88e6xxx_serdes_power(chip, port, true);
1895 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1896 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1897 * untagged frames on this port, do a destination address lookup on all
1898 * received packets as usual, disable ARP mirroring and don't send a
1899 * copy of all transmitted/received frames on this port to the CPU.
1901 err = mv88e6xxx_port_set_map_da(chip, port);
1906 if (chip->info->ops->port_set_upstream_port) {
1907 err = chip->info->ops->port_set_upstream_port(
1908 chip, port, dsa_upstream_port(ds));
1913 err = mv88e6xxx_port_set_8021q_mode(chip, port,
1914 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1918 if (chip->info->ops->port_set_jumbo_size) {
1919 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1924 /* Port Association Vector: when learning source addresses
1925 * of packets, add the address to the address database using
1926 * a port bitmap that has only the bit for this port set and
1927 * the other bits clear.
1930 /* Disable learning for CPU port */
1931 if (dsa_is_cpu_port(ds, port))
1934 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1939 /* Egress rate control 2: disable egress rate control. */
1940 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1945 if (chip->info->ops->port_pause_limit) {
1946 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1951 if (chip->info->ops->port_disable_learn_limit) {
1952 err = chip->info->ops->port_disable_learn_limit(chip, port);
1957 if (chip->info->ops->port_disable_pri_override) {
1958 err = chip->info->ops->port_disable_pri_override(chip, port);
1963 if (chip->info->ops->port_tag_remap) {
1964 err = chip->info->ops->port_tag_remap(chip, port);
1969 if (chip->info->ops->port_egress_rate_limiting) {
1970 err = chip->info->ops->port_egress_rate_limiting(chip, port);
1975 err = mv88e6xxx_setup_message_port(chip, port);
1979 /* Port based VLAN map: give each port the same default address
1980 * database, and allow bidirectional communication between the
1981 * CPU and DSA port(s), and the other ports.
1983 err = mv88e6xxx_port_set_fid(chip, port, 0);
1987 err = mv88e6xxx_port_vlan_map(chip, port);
1991 /* Default VLAN ID and priority: don't set a default VLAN
1992 * ID, and set the default packet priority to zero.
1994 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
1997 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1998 struct phy_device *phydev)
2000 struct mv88e6xxx_chip *chip = ds->priv;
2003 mutex_lock(&chip->reg_lock);
2004 err = mv88e6xxx_serdes_power(chip, port, true);
2005 mutex_unlock(&chip->reg_lock);
2010 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2011 struct phy_device *phydev)
2013 struct mv88e6xxx_chip *chip = ds->priv;
2015 mutex_lock(&chip->reg_lock);
2016 if (mv88e6xxx_serdes_power(chip, port, false))
2017 dev_err(chip->dev, "failed to power off SERDES\n");
2018 mutex_unlock(&chip->reg_lock);
2021 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2022 unsigned int ageing_time)
2024 struct mv88e6xxx_chip *chip = ds->priv;
2027 mutex_lock(&chip->reg_lock);
2028 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2029 mutex_unlock(&chip->reg_lock);
2034 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2036 struct dsa_switch *ds = chip->ds;
2037 u32 upstream_port = dsa_upstream_port(ds);
2040 if (chip->info->ops->set_cpu_port) {
2041 err = chip->info->ops->set_cpu_port(chip, upstream_port);
2046 if (chip->info->ops->set_egress_port) {
2047 err = chip->info->ops->set_egress_port(chip, upstream_port);
2052 /* Disable remote management, and set the switch's DSA device number. */
2053 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
2054 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
2055 (ds->index & 0x1f));
2059 /* Configure the IP ToS mapping registers. */
2060 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
2063 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
2066 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
2069 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
2072 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
2075 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
2078 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
2081 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
2085 /* Configure the IEEE 802.1p priority mapping register. */
2086 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
2090 /* Initialize the statistics unit */
2091 err = mv88e6xxx_stats_set_histogram(chip);
2095 /* Clear the statistics counters for all ports */
2096 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
2097 MV88E6XXX_G1_STATS_OP_BUSY |
2098 MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
2102 /* Wait for the flush to complete. */
2103 err = mv88e6xxx_g1_stats_wait(chip);
2110 static int mv88e6xxx_setup(struct dsa_switch *ds)
2112 struct mv88e6xxx_chip *chip = ds->priv;
2117 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2119 mutex_lock(&chip->reg_lock);
2121 /* Setup Switch Port Registers */
2122 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2123 err = mv88e6xxx_setup_port(chip, i);
2128 /* Setup Switch Global 1 Registers */
2129 err = mv88e6xxx_g1_setup(chip);
2133 /* Setup Switch Global 2 Registers */
2134 if (chip->info->global2_addr) {
2135 err = mv88e6xxx_g2_setup(chip);
2140 err = mv88e6xxx_irl_setup(chip);
2144 err = mv88e6xxx_phy_setup(chip);
2148 err = mv88e6xxx_vtu_setup(chip);
2152 err = mv88e6xxx_pvt_setup(chip);
2156 err = mv88e6xxx_atu_setup(chip);
2160 err = mv88e6xxx_pot_setup(chip);
2164 err = mv88e6xxx_rsvd2cpu_setup(chip);
2169 mutex_unlock(&chip->reg_lock);
2174 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2176 struct mv88e6xxx_chip *chip = ds->priv;
2179 if (!chip->info->ops->set_switch_mac)
2182 mutex_lock(&chip->reg_lock);
2183 err = chip->info->ops->set_switch_mac(chip, addr);
2184 mutex_unlock(&chip->reg_lock);
2189 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2191 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2192 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2196 if (!chip->info->ops->phy_read)
2199 mutex_lock(&chip->reg_lock);
2200 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2201 mutex_unlock(&chip->reg_lock);
2203 if (reg == MII_PHYSID2) {
2204 /* Some internal PHYS don't have a model number. Use
2205 * the mv88e6390 family model number instead.
2208 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2211 return err ? err : val;
2214 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2216 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2217 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2220 if (!chip->info->ops->phy_write)
2223 mutex_lock(&chip->reg_lock);
2224 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2225 mutex_unlock(&chip->reg_lock);
2230 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2231 struct device_node *np,
2235 struct mv88e6xxx_mdio_bus *mdio_bus;
2236 struct mii_bus *bus;
2239 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2243 mdio_bus = bus->priv;
2244 mdio_bus->bus = bus;
2245 mdio_bus->chip = chip;
2246 INIT_LIST_HEAD(&mdio_bus->list);
2247 mdio_bus->external = external;
2250 bus->name = np->full_name;
2251 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2253 bus->name = "mv88e6xxx SMI";
2254 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2257 bus->read = mv88e6xxx_mdio_read;
2258 bus->write = mv88e6xxx_mdio_write;
2259 bus->parent = chip->dev;
2262 err = of_mdiobus_register(bus, np);
2264 err = mdiobus_register(bus);
2266 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2271 list_add_tail(&mdio_bus->list, &chip->mdios);
2273 list_add(&mdio_bus->list, &chip->mdios);
2278 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2279 { .compatible = "marvell,mv88e6xxx-mdio-external",
2280 .data = (void *)true },
2284 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2285 struct device_node *np)
2287 const struct of_device_id *match;
2288 struct device_node *child;
2291 /* Always register one mdio bus for the internal/default mdio
2292 * bus. This maybe represented in the device tree, but is
2295 child = of_get_child_by_name(np, "mdio");
2296 err = mv88e6xxx_mdio_register(chip, child, false);
2300 /* Walk the device tree, and see if there are any other nodes
2301 * which say they are compatible with the external mdio
2304 for_each_available_child_of_node(np, child) {
2305 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2307 err = mv88e6xxx_mdio_register(chip, child, true);
2316 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2319 struct mv88e6xxx_mdio_bus *mdio_bus;
2320 struct mii_bus *bus;
2322 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2323 bus = mdio_bus->bus;
2325 mdiobus_unregister(bus);
2329 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2331 struct mv88e6xxx_chip *chip = ds->priv;
2333 return chip->eeprom_len;
2336 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2337 struct ethtool_eeprom *eeprom, u8 *data)
2339 struct mv88e6xxx_chip *chip = ds->priv;
2342 if (!chip->info->ops->get_eeprom)
2345 mutex_lock(&chip->reg_lock);
2346 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2347 mutex_unlock(&chip->reg_lock);
2352 eeprom->magic = 0xc3ec4951;
2357 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2358 struct ethtool_eeprom *eeprom, u8 *data)
2360 struct mv88e6xxx_chip *chip = ds->priv;
2363 if (!chip->info->ops->set_eeprom)
2366 if (eeprom->magic != 0xc3ec4951)
2369 mutex_lock(&chip->reg_lock);
2370 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2371 mutex_unlock(&chip->reg_lock);
2376 static const struct mv88e6xxx_ops mv88e6085_ops = {
2377 /* MV88E6XXX_FAMILY_6097 */
2378 .irl_init_all = mv88e6352_g2_irl_init_all,
2379 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2380 .phy_read = mv88e6185_phy_ppu_read,
2381 .phy_write = mv88e6185_phy_ppu_write,
2382 .port_set_link = mv88e6xxx_port_set_link,
2383 .port_set_duplex = mv88e6xxx_port_set_duplex,
2384 .port_set_speed = mv88e6185_port_set_speed,
2385 .port_tag_remap = mv88e6095_port_tag_remap,
2386 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2387 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2388 .port_set_ether_type = mv88e6351_port_set_ether_type,
2389 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2390 .port_pause_limit = mv88e6097_port_pause_limit,
2391 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2392 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2393 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2394 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2395 .stats_get_strings = mv88e6095_stats_get_strings,
2396 .stats_get_stats = mv88e6095_stats_get_stats,
2397 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2398 .set_egress_port = mv88e6095_g1_set_egress_port,
2399 .watchdog_ops = &mv88e6097_watchdog_ops,
2400 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2401 .pot_clear = mv88e6xxx_g2_pot_clear,
2402 .ppu_enable = mv88e6185_g1_ppu_enable,
2403 .ppu_disable = mv88e6185_g1_ppu_disable,
2404 .reset = mv88e6185_g1_reset,
2405 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2406 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2409 static const struct mv88e6xxx_ops mv88e6095_ops = {
2410 /* MV88E6XXX_FAMILY_6095 */
2411 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2412 .phy_read = mv88e6185_phy_ppu_read,
2413 .phy_write = mv88e6185_phy_ppu_write,
2414 .port_set_link = mv88e6xxx_port_set_link,
2415 .port_set_duplex = mv88e6xxx_port_set_duplex,
2416 .port_set_speed = mv88e6185_port_set_speed,
2417 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2418 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2419 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2420 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2421 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2422 .stats_get_strings = mv88e6095_stats_get_strings,
2423 .stats_get_stats = mv88e6095_stats_get_stats,
2424 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2425 .ppu_enable = mv88e6185_g1_ppu_enable,
2426 .ppu_disable = mv88e6185_g1_ppu_disable,
2427 .reset = mv88e6185_g1_reset,
2428 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2429 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2432 static const struct mv88e6xxx_ops mv88e6097_ops = {
2433 /* MV88E6XXX_FAMILY_6097 */
2434 .irl_init_all = mv88e6352_g2_irl_init_all,
2435 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2436 .phy_read = mv88e6xxx_g2_smi_phy_read,
2437 .phy_write = mv88e6xxx_g2_smi_phy_write,
2438 .port_set_link = mv88e6xxx_port_set_link,
2439 .port_set_duplex = mv88e6xxx_port_set_duplex,
2440 .port_set_speed = mv88e6185_port_set_speed,
2441 .port_tag_remap = mv88e6095_port_tag_remap,
2442 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2443 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2444 .port_set_ether_type = mv88e6351_port_set_ether_type,
2445 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2446 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2447 .port_pause_limit = mv88e6097_port_pause_limit,
2448 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2449 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2450 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2451 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2452 .stats_get_strings = mv88e6095_stats_get_strings,
2453 .stats_get_stats = mv88e6095_stats_get_stats,
2454 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2455 .set_egress_port = mv88e6095_g1_set_egress_port,
2456 .watchdog_ops = &mv88e6097_watchdog_ops,
2457 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2458 .pot_clear = mv88e6xxx_g2_pot_clear,
2459 .reset = mv88e6352_g1_reset,
2460 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2461 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2464 static const struct mv88e6xxx_ops mv88e6123_ops = {
2465 /* MV88E6XXX_FAMILY_6165 */
2466 .irl_init_all = mv88e6352_g2_irl_init_all,
2467 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2468 .phy_read = mv88e6xxx_g2_smi_phy_read,
2469 .phy_write = mv88e6xxx_g2_smi_phy_write,
2470 .port_set_link = mv88e6xxx_port_set_link,
2471 .port_set_duplex = mv88e6xxx_port_set_duplex,
2472 .port_set_speed = mv88e6185_port_set_speed,
2473 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2474 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2475 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2476 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2477 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2478 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2479 .stats_get_strings = mv88e6095_stats_get_strings,
2480 .stats_get_stats = mv88e6095_stats_get_stats,
2481 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2482 .set_egress_port = mv88e6095_g1_set_egress_port,
2483 .watchdog_ops = &mv88e6097_watchdog_ops,
2484 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2485 .pot_clear = mv88e6xxx_g2_pot_clear,
2486 .reset = mv88e6352_g1_reset,
2487 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2488 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2491 static const struct mv88e6xxx_ops mv88e6131_ops = {
2492 /* MV88E6XXX_FAMILY_6185 */
2493 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2494 .phy_read = mv88e6185_phy_ppu_read,
2495 .phy_write = mv88e6185_phy_ppu_write,
2496 .port_set_link = mv88e6xxx_port_set_link,
2497 .port_set_duplex = mv88e6xxx_port_set_duplex,
2498 .port_set_speed = mv88e6185_port_set_speed,
2499 .port_tag_remap = mv88e6095_port_tag_remap,
2500 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2501 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2502 .port_set_ether_type = mv88e6351_port_set_ether_type,
2503 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2504 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2505 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2506 .port_pause_limit = mv88e6097_port_pause_limit,
2507 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2508 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2509 .stats_get_strings = mv88e6095_stats_get_strings,
2510 .stats_get_stats = mv88e6095_stats_get_stats,
2511 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2512 .set_egress_port = mv88e6095_g1_set_egress_port,
2513 .watchdog_ops = &mv88e6097_watchdog_ops,
2514 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2515 .ppu_enable = mv88e6185_g1_ppu_enable,
2516 .ppu_disable = mv88e6185_g1_ppu_disable,
2517 .reset = mv88e6185_g1_reset,
2518 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2519 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2522 static const struct mv88e6xxx_ops mv88e6141_ops = {
2523 /* MV88E6XXX_FAMILY_6341 */
2524 .irl_init_all = mv88e6352_g2_irl_init_all,
2525 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2526 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2527 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2528 .phy_read = mv88e6xxx_g2_smi_phy_read,
2529 .phy_write = mv88e6xxx_g2_smi_phy_write,
2530 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2531 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2532 .port_set_link = mv88e6xxx_port_set_link,
2533 .port_set_duplex = mv88e6xxx_port_set_duplex,
2534 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2535 .port_set_speed = mv88e6390_port_set_speed,
2536 .port_tag_remap = mv88e6095_port_tag_remap,
2537 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2538 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2539 .port_set_ether_type = mv88e6351_port_set_ether_type,
2540 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2541 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2542 .port_pause_limit = mv88e6097_port_pause_limit,
2543 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2544 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2545 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2546 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2547 .stats_get_strings = mv88e6320_stats_get_strings,
2548 .stats_get_stats = mv88e6390_stats_get_stats,
2549 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2550 .set_egress_port = mv88e6390_g1_set_egress_port,
2551 .watchdog_ops = &mv88e6390_watchdog_ops,
2552 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2553 .pot_clear = mv88e6xxx_g2_pot_clear,
2554 .reset = mv88e6352_g1_reset,
2555 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2556 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2559 static const struct mv88e6xxx_ops mv88e6161_ops = {
2560 /* MV88E6XXX_FAMILY_6165 */
2561 .irl_init_all = mv88e6352_g2_irl_init_all,
2562 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2563 .phy_read = mv88e6xxx_g2_smi_phy_read,
2564 .phy_write = mv88e6xxx_g2_smi_phy_write,
2565 .port_set_link = mv88e6xxx_port_set_link,
2566 .port_set_duplex = mv88e6xxx_port_set_duplex,
2567 .port_set_speed = mv88e6185_port_set_speed,
2568 .port_tag_remap = mv88e6095_port_tag_remap,
2569 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2570 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2571 .port_set_ether_type = mv88e6351_port_set_ether_type,
2572 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2573 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2574 .port_pause_limit = mv88e6097_port_pause_limit,
2575 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2576 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2577 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2578 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2579 .stats_get_strings = mv88e6095_stats_get_strings,
2580 .stats_get_stats = mv88e6095_stats_get_stats,
2581 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2582 .set_egress_port = mv88e6095_g1_set_egress_port,
2583 .watchdog_ops = &mv88e6097_watchdog_ops,
2584 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2585 .pot_clear = mv88e6xxx_g2_pot_clear,
2586 .reset = mv88e6352_g1_reset,
2587 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2588 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2591 static const struct mv88e6xxx_ops mv88e6165_ops = {
2592 /* MV88E6XXX_FAMILY_6165 */
2593 .irl_init_all = mv88e6352_g2_irl_init_all,
2594 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2595 .phy_read = mv88e6165_phy_read,
2596 .phy_write = mv88e6165_phy_write,
2597 .port_set_link = mv88e6xxx_port_set_link,
2598 .port_set_duplex = mv88e6xxx_port_set_duplex,
2599 .port_set_speed = mv88e6185_port_set_speed,
2600 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2601 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2602 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2603 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2604 .stats_get_strings = mv88e6095_stats_get_strings,
2605 .stats_get_stats = mv88e6095_stats_get_stats,
2606 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2607 .set_egress_port = mv88e6095_g1_set_egress_port,
2608 .watchdog_ops = &mv88e6097_watchdog_ops,
2609 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2610 .pot_clear = mv88e6xxx_g2_pot_clear,
2611 .reset = mv88e6352_g1_reset,
2612 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2613 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2616 static const struct mv88e6xxx_ops mv88e6171_ops = {
2617 /* MV88E6XXX_FAMILY_6351 */
2618 .irl_init_all = mv88e6352_g2_irl_init_all,
2619 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2620 .phy_read = mv88e6xxx_g2_smi_phy_read,
2621 .phy_write = mv88e6xxx_g2_smi_phy_write,
2622 .port_set_link = mv88e6xxx_port_set_link,
2623 .port_set_duplex = mv88e6xxx_port_set_duplex,
2624 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2625 .port_set_speed = mv88e6185_port_set_speed,
2626 .port_tag_remap = mv88e6095_port_tag_remap,
2627 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2628 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2629 .port_set_ether_type = mv88e6351_port_set_ether_type,
2630 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2631 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2632 .port_pause_limit = mv88e6097_port_pause_limit,
2633 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2634 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2635 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2636 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2637 .stats_get_strings = mv88e6095_stats_get_strings,
2638 .stats_get_stats = mv88e6095_stats_get_stats,
2639 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2640 .set_egress_port = mv88e6095_g1_set_egress_port,
2641 .watchdog_ops = &mv88e6097_watchdog_ops,
2642 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2643 .pot_clear = mv88e6xxx_g2_pot_clear,
2644 .reset = mv88e6352_g1_reset,
2645 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2646 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2649 static const struct mv88e6xxx_ops mv88e6172_ops = {
2650 /* MV88E6XXX_FAMILY_6352 */
2651 .irl_init_all = mv88e6352_g2_irl_init_all,
2652 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2653 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2654 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2655 .phy_read = mv88e6xxx_g2_smi_phy_read,
2656 .phy_write = mv88e6xxx_g2_smi_phy_write,
2657 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2658 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2659 .port_set_link = mv88e6xxx_port_set_link,
2660 .port_set_duplex = mv88e6xxx_port_set_duplex,
2661 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2662 .port_set_speed = mv88e6352_port_set_speed,
2663 .port_tag_remap = mv88e6095_port_tag_remap,
2664 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2665 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2666 .port_set_ether_type = mv88e6351_port_set_ether_type,
2667 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2668 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2669 .port_pause_limit = mv88e6097_port_pause_limit,
2670 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2671 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2672 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2673 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2674 .stats_get_strings = mv88e6095_stats_get_strings,
2675 .stats_get_stats = mv88e6095_stats_get_stats,
2676 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2677 .set_egress_port = mv88e6095_g1_set_egress_port,
2678 .watchdog_ops = &mv88e6097_watchdog_ops,
2679 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2680 .pot_clear = mv88e6xxx_g2_pot_clear,
2681 .reset = mv88e6352_g1_reset,
2682 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2683 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2684 .serdes_power = mv88e6352_serdes_power,
2687 static const struct mv88e6xxx_ops mv88e6175_ops = {
2688 /* MV88E6XXX_FAMILY_6351 */
2689 .irl_init_all = mv88e6352_g2_irl_init_all,
2690 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2691 .phy_read = mv88e6xxx_g2_smi_phy_read,
2692 .phy_write = mv88e6xxx_g2_smi_phy_write,
2693 .port_set_link = mv88e6xxx_port_set_link,
2694 .port_set_duplex = mv88e6xxx_port_set_duplex,
2695 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2696 .port_set_speed = mv88e6185_port_set_speed,
2697 .port_tag_remap = mv88e6095_port_tag_remap,
2698 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2699 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2700 .port_set_ether_type = mv88e6351_port_set_ether_type,
2701 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2702 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2703 .port_pause_limit = mv88e6097_port_pause_limit,
2704 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2705 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2706 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2707 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2708 .stats_get_strings = mv88e6095_stats_get_strings,
2709 .stats_get_stats = mv88e6095_stats_get_stats,
2710 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2711 .set_egress_port = mv88e6095_g1_set_egress_port,
2712 .watchdog_ops = &mv88e6097_watchdog_ops,
2713 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2714 .pot_clear = mv88e6xxx_g2_pot_clear,
2715 .reset = mv88e6352_g1_reset,
2716 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2717 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2720 static const struct mv88e6xxx_ops mv88e6176_ops = {
2721 /* MV88E6XXX_FAMILY_6352 */
2722 .irl_init_all = mv88e6352_g2_irl_init_all,
2723 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2724 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2725 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2726 .phy_read = mv88e6xxx_g2_smi_phy_read,
2727 .phy_write = mv88e6xxx_g2_smi_phy_write,
2728 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2729 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2730 .port_set_link = mv88e6xxx_port_set_link,
2731 .port_set_duplex = mv88e6xxx_port_set_duplex,
2732 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2733 .port_set_speed = mv88e6352_port_set_speed,
2734 .port_tag_remap = mv88e6095_port_tag_remap,
2735 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2736 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2737 .port_set_ether_type = mv88e6351_port_set_ether_type,
2738 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2739 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2740 .port_pause_limit = mv88e6097_port_pause_limit,
2741 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2742 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2743 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2744 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2745 .stats_get_strings = mv88e6095_stats_get_strings,
2746 .stats_get_stats = mv88e6095_stats_get_stats,
2747 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2748 .set_egress_port = mv88e6095_g1_set_egress_port,
2749 .watchdog_ops = &mv88e6097_watchdog_ops,
2750 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2751 .pot_clear = mv88e6xxx_g2_pot_clear,
2752 .reset = mv88e6352_g1_reset,
2753 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2754 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2755 .serdes_power = mv88e6352_serdes_power,
2758 static const struct mv88e6xxx_ops mv88e6185_ops = {
2759 /* MV88E6XXX_FAMILY_6185 */
2760 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2761 .phy_read = mv88e6185_phy_ppu_read,
2762 .phy_write = mv88e6185_phy_ppu_write,
2763 .port_set_link = mv88e6xxx_port_set_link,
2764 .port_set_duplex = mv88e6xxx_port_set_duplex,
2765 .port_set_speed = mv88e6185_port_set_speed,
2766 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2767 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2768 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2769 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2770 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2771 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2772 .stats_get_strings = mv88e6095_stats_get_strings,
2773 .stats_get_stats = mv88e6095_stats_get_stats,
2774 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2775 .set_egress_port = mv88e6095_g1_set_egress_port,
2776 .watchdog_ops = &mv88e6097_watchdog_ops,
2777 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2778 .ppu_enable = mv88e6185_g1_ppu_enable,
2779 .ppu_disable = mv88e6185_g1_ppu_disable,
2780 .reset = mv88e6185_g1_reset,
2781 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2782 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2785 static const struct mv88e6xxx_ops mv88e6190_ops = {
2786 /* MV88E6XXX_FAMILY_6390 */
2787 .irl_init_all = mv88e6390_g2_irl_init_all,
2788 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2789 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2790 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2791 .phy_read = mv88e6xxx_g2_smi_phy_read,
2792 .phy_write = mv88e6xxx_g2_smi_phy_write,
2793 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2794 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
2795 .port_set_link = mv88e6xxx_port_set_link,
2796 .port_set_duplex = mv88e6xxx_port_set_duplex,
2797 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2798 .port_set_speed = mv88e6390_port_set_speed,
2799 .port_tag_remap = mv88e6390_port_tag_remap,
2800 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2801 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2802 .port_set_ether_type = mv88e6351_port_set_ether_type,
2803 .port_pause_limit = mv88e6390_port_pause_limit,
2804 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2805 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2806 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2807 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2808 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2809 .stats_get_strings = mv88e6320_stats_get_strings,
2810 .stats_get_stats = mv88e6390_stats_get_stats,
2811 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2812 .set_egress_port = mv88e6390_g1_set_egress_port,
2813 .watchdog_ops = &mv88e6390_watchdog_ops,
2814 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2815 .pot_clear = mv88e6xxx_g2_pot_clear,
2816 .reset = mv88e6352_g1_reset,
2817 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2818 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2819 .serdes_power = mv88e6390_serdes_power,
2822 static const struct mv88e6xxx_ops mv88e6190x_ops = {
2823 /* MV88E6XXX_FAMILY_6390 */
2824 .irl_init_all = mv88e6390_g2_irl_init_all,
2825 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2826 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2827 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2828 .phy_read = mv88e6xxx_g2_smi_phy_read,
2829 .phy_write = mv88e6xxx_g2_smi_phy_write,
2830 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2831 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
2832 .port_set_link = mv88e6xxx_port_set_link,
2833 .port_set_duplex = mv88e6xxx_port_set_duplex,
2834 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2835 .port_set_speed = mv88e6390x_port_set_speed,
2836 .port_tag_remap = mv88e6390_port_tag_remap,
2837 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2838 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2839 .port_set_ether_type = mv88e6351_port_set_ether_type,
2840 .port_pause_limit = mv88e6390_port_pause_limit,
2841 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2842 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2843 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2844 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2845 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2846 .stats_get_strings = mv88e6320_stats_get_strings,
2847 .stats_get_stats = mv88e6390_stats_get_stats,
2848 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2849 .set_egress_port = mv88e6390_g1_set_egress_port,
2850 .watchdog_ops = &mv88e6390_watchdog_ops,
2851 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2852 .pot_clear = mv88e6xxx_g2_pot_clear,
2853 .reset = mv88e6352_g1_reset,
2854 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2855 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2856 .serdes_power = mv88e6390_serdes_power,
2859 static const struct mv88e6xxx_ops mv88e6191_ops = {
2860 /* MV88E6XXX_FAMILY_6390 */
2861 .irl_init_all = mv88e6390_g2_irl_init_all,
2862 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2863 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2864 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2865 .phy_read = mv88e6xxx_g2_smi_phy_read,
2866 .phy_write = mv88e6xxx_g2_smi_phy_write,
2867 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2868 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
2869 .port_set_link = mv88e6xxx_port_set_link,
2870 .port_set_duplex = mv88e6xxx_port_set_duplex,
2871 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2872 .port_set_speed = mv88e6390_port_set_speed,
2873 .port_tag_remap = mv88e6390_port_tag_remap,
2874 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2875 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2876 .port_set_ether_type = mv88e6351_port_set_ether_type,
2877 .port_pause_limit = mv88e6390_port_pause_limit,
2878 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2879 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2880 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2881 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2882 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2883 .stats_get_strings = mv88e6320_stats_get_strings,
2884 .stats_get_stats = mv88e6390_stats_get_stats,
2885 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2886 .set_egress_port = mv88e6390_g1_set_egress_port,
2887 .watchdog_ops = &mv88e6390_watchdog_ops,
2888 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2889 .pot_clear = mv88e6xxx_g2_pot_clear,
2890 .reset = mv88e6352_g1_reset,
2891 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2892 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2893 .serdes_power = mv88e6390_serdes_power,
2896 static const struct mv88e6xxx_ops mv88e6240_ops = {
2897 /* MV88E6XXX_FAMILY_6352 */
2898 .irl_init_all = mv88e6352_g2_irl_init_all,
2899 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2900 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2901 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2902 .phy_read = mv88e6xxx_g2_smi_phy_read,
2903 .phy_write = mv88e6xxx_g2_smi_phy_write,
2904 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2905 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2906 .port_set_link = mv88e6xxx_port_set_link,
2907 .port_set_duplex = mv88e6xxx_port_set_duplex,
2908 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2909 .port_set_speed = mv88e6352_port_set_speed,
2910 .port_tag_remap = mv88e6095_port_tag_remap,
2911 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2912 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2913 .port_set_ether_type = mv88e6351_port_set_ether_type,
2914 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2915 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2916 .port_pause_limit = mv88e6097_port_pause_limit,
2917 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2918 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2919 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2920 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2921 .stats_get_strings = mv88e6095_stats_get_strings,
2922 .stats_get_stats = mv88e6095_stats_get_stats,
2923 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2924 .set_egress_port = mv88e6095_g1_set_egress_port,
2925 .watchdog_ops = &mv88e6097_watchdog_ops,
2926 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2927 .pot_clear = mv88e6xxx_g2_pot_clear,
2928 .reset = mv88e6352_g1_reset,
2929 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2930 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2931 .serdes_power = mv88e6352_serdes_power,
2934 static const struct mv88e6xxx_ops mv88e6290_ops = {
2935 /* MV88E6XXX_FAMILY_6390 */
2936 .irl_init_all = mv88e6390_g2_irl_init_all,
2937 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2938 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2939 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2940 .phy_read = mv88e6xxx_g2_smi_phy_read,
2941 .phy_write = mv88e6xxx_g2_smi_phy_write,
2942 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2943 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
2944 .port_set_link = mv88e6xxx_port_set_link,
2945 .port_set_duplex = mv88e6xxx_port_set_duplex,
2946 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2947 .port_set_speed = mv88e6390_port_set_speed,
2948 .port_tag_remap = mv88e6390_port_tag_remap,
2949 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2950 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2951 .port_set_ether_type = mv88e6351_port_set_ether_type,
2952 .port_pause_limit = mv88e6390_port_pause_limit,
2953 .port_set_cmode = mv88e6390x_port_set_cmode,
2954 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2955 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2956 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2957 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2958 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2959 .stats_get_strings = mv88e6320_stats_get_strings,
2960 .stats_get_stats = mv88e6390_stats_get_stats,
2961 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2962 .set_egress_port = mv88e6390_g1_set_egress_port,
2963 .watchdog_ops = &mv88e6390_watchdog_ops,
2964 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2965 .pot_clear = mv88e6xxx_g2_pot_clear,
2966 .reset = mv88e6352_g1_reset,
2967 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2968 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2969 .serdes_power = mv88e6390_serdes_power,
2972 static const struct mv88e6xxx_ops mv88e6320_ops = {
2973 /* MV88E6XXX_FAMILY_6320 */
2974 .irl_init_all = mv88e6352_g2_irl_init_all,
2975 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2976 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2977 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2978 .phy_read = mv88e6xxx_g2_smi_phy_read,
2979 .phy_write = mv88e6xxx_g2_smi_phy_write,
2980 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2981 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
2982 .port_set_link = mv88e6xxx_port_set_link,
2983 .port_set_duplex = mv88e6xxx_port_set_duplex,
2984 .port_set_speed = mv88e6185_port_set_speed,
2985 .port_tag_remap = mv88e6095_port_tag_remap,
2986 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2987 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2988 .port_set_ether_type = mv88e6351_port_set_ether_type,
2989 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2990 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2991 .port_pause_limit = mv88e6097_port_pause_limit,
2992 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2993 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2994 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2995 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2996 .stats_get_strings = mv88e6320_stats_get_strings,
2997 .stats_get_stats = mv88e6320_stats_get_stats,
2998 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2999 .set_egress_port = mv88e6095_g1_set_egress_port,
3000 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3001 .pot_clear = mv88e6xxx_g2_pot_clear,
3002 .reset = mv88e6352_g1_reset,
3003 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3004 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3007 static const struct mv88e6xxx_ops mv88e6321_ops = {
3008 /* MV88E6XXX_FAMILY_6320 */
3009 .irl_init_all = mv88e6352_g2_irl_init_all,
3010 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3011 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3012 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3013 .phy_read = mv88e6xxx_g2_smi_phy_read,
3014 .phy_write = mv88e6xxx_g2_smi_phy_write,
3015 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
3016 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
3017 .port_set_link = mv88e6xxx_port_set_link,
3018 .port_set_duplex = mv88e6xxx_port_set_duplex,
3019 .port_set_speed = mv88e6185_port_set_speed,
3020 .port_tag_remap = mv88e6095_port_tag_remap,
3021 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3022 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3023 .port_set_ether_type = mv88e6351_port_set_ether_type,
3024 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3025 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3026 .port_pause_limit = mv88e6097_port_pause_limit,
3027 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3028 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3029 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3030 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3031 .stats_get_strings = mv88e6320_stats_get_strings,
3032 .stats_get_stats = mv88e6320_stats_get_stats,
3033 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3034 .set_egress_port = mv88e6095_g1_set_egress_port,
3035 .reset = mv88e6352_g1_reset,
3036 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3037 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3040 static const struct mv88e6xxx_ops mv88e6341_ops = {
3041 /* MV88E6XXX_FAMILY_6341 */
3042 .irl_init_all = mv88e6352_g2_irl_init_all,
3043 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3044 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3045 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3046 .phy_read = mv88e6xxx_g2_smi_phy_read,
3047 .phy_write = mv88e6xxx_g2_smi_phy_write,
3048 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
3049 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
3050 .port_set_link = mv88e6xxx_port_set_link,
3051 .port_set_duplex = mv88e6xxx_port_set_duplex,
3052 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3053 .port_set_speed = mv88e6390_port_set_speed,
3054 .port_tag_remap = mv88e6095_port_tag_remap,
3055 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3056 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3057 .port_set_ether_type = mv88e6351_port_set_ether_type,
3058 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3059 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3060 .port_pause_limit = mv88e6097_port_pause_limit,
3061 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3062 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3063 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3064 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3065 .stats_get_strings = mv88e6320_stats_get_strings,
3066 .stats_get_stats = mv88e6390_stats_get_stats,
3067 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3068 .set_egress_port = mv88e6390_g1_set_egress_port,
3069 .watchdog_ops = &mv88e6390_watchdog_ops,
3070 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3071 .pot_clear = mv88e6xxx_g2_pot_clear,
3072 .reset = mv88e6352_g1_reset,
3073 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3074 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3077 static const struct mv88e6xxx_ops mv88e6350_ops = {
3078 /* MV88E6XXX_FAMILY_6351 */
3079 .irl_init_all = mv88e6352_g2_irl_init_all,
3080 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3081 .phy_read = mv88e6xxx_g2_smi_phy_read,
3082 .phy_write = mv88e6xxx_g2_smi_phy_write,
3083 .port_set_link = mv88e6xxx_port_set_link,
3084 .port_set_duplex = mv88e6xxx_port_set_duplex,
3085 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3086 .port_set_speed = mv88e6185_port_set_speed,
3087 .port_tag_remap = mv88e6095_port_tag_remap,
3088 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3089 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3090 .port_set_ether_type = mv88e6351_port_set_ether_type,
3091 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3092 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3093 .port_pause_limit = mv88e6097_port_pause_limit,
3094 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3095 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3096 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3097 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3098 .stats_get_strings = mv88e6095_stats_get_strings,
3099 .stats_get_stats = mv88e6095_stats_get_stats,
3100 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3101 .set_egress_port = mv88e6095_g1_set_egress_port,
3102 .watchdog_ops = &mv88e6097_watchdog_ops,
3103 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3104 .pot_clear = mv88e6xxx_g2_pot_clear,
3105 .reset = mv88e6352_g1_reset,
3106 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3107 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3110 static const struct mv88e6xxx_ops mv88e6351_ops = {
3111 /* MV88E6XXX_FAMILY_6351 */
3112 .irl_init_all = mv88e6352_g2_irl_init_all,
3113 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3114 .phy_read = mv88e6xxx_g2_smi_phy_read,
3115 .phy_write = mv88e6xxx_g2_smi_phy_write,
3116 .port_set_link = mv88e6xxx_port_set_link,
3117 .port_set_duplex = mv88e6xxx_port_set_duplex,
3118 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3119 .port_set_speed = mv88e6185_port_set_speed,
3120 .port_tag_remap = mv88e6095_port_tag_remap,
3121 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3122 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3123 .port_set_ether_type = mv88e6351_port_set_ether_type,
3124 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3125 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3126 .port_pause_limit = mv88e6097_port_pause_limit,
3127 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3128 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3129 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3130 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3131 .stats_get_strings = mv88e6095_stats_get_strings,
3132 .stats_get_stats = mv88e6095_stats_get_stats,
3133 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3134 .set_egress_port = mv88e6095_g1_set_egress_port,
3135 .watchdog_ops = &mv88e6097_watchdog_ops,
3136 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3137 .pot_clear = mv88e6xxx_g2_pot_clear,
3138 .reset = mv88e6352_g1_reset,
3139 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3140 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3143 static const struct mv88e6xxx_ops mv88e6352_ops = {
3144 /* MV88E6XXX_FAMILY_6352 */
3145 .irl_init_all = mv88e6352_g2_irl_init_all,
3146 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3147 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3148 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3149 .phy_read = mv88e6xxx_g2_smi_phy_read,
3150 .phy_write = mv88e6xxx_g2_smi_phy_write,
3151 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
3152 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
3153 .port_set_link = mv88e6xxx_port_set_link,
3154 .port_set_duplex = mv88e6xxx_port_set_duplex,
3155 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3156 .port_set_speed = mv88e6352_port_set_speed,
3157 .port_tag_remap = mv88e6095_port_tag_remap,
3158 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3159 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3160 .port_set_ether_type = mv88e6351_port_set_ether_type,
3161 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3162 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3163 .port_pause_limit = mv88e6097_port_pause_limit,
3164 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3165 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3166 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3167 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3168 .stats_get_strings = mv88e6095_stats_get_strings,
3169 .stats_get_stats = mv88e6095_stats_get_stats,
3170 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3171 .set_egress_port = mv88e6095_g1_set_egress_port,
3172 .watchdog_ops = &mv88e6097_watchdog_ops,
3173 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3174 .pot_clear = mv88e6xxx_g2_pot_clear,
3175 .reset = mv88e6352_g1_reset,
3176 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3177 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3178 .serdes_power = mv88e6352_serdes_power,
3181 static const struct mv88e6xxx_ops mv88e6390_ops = {
3182 /* MV88E6XXX_FAMILY_6390 */
3183 .irl_init_all = mv88e6390_g2_irl_init_all,
3184 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3185 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3186 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3187 .phy_read = mv88e6xxx_g2_smi_phy_read,
3188 .phy_write = mv88e6xxx_g2_smi_phy_write,
3189 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
3190 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
3191 .port_set_link = mv88e6xxx_port_set_link,
3192 .port_set_duplex = mv88e6xxx_port_set_duplex,
3193 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3194 .port_set_speed = mv88e6390_port_set_speed,
3195 .port_tag_remap = mv88e6390_port_tag_remap,
3196 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3197 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3198 .port_set_ether_type = mv88e6351_port_set_ether_type,
3199 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3200 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3201 .port_pause_limit = mv88e6390_port_pause_limit,
3202 .port_set_cmode = mv88e6390x_port_set_cmode,
3203 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3204 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3205 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3206 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3207 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3208 .stats_get_strings = mv88e6320_stats_get_strings,
3209 .stats_get_stats = mv88e6390_stats_get_stats,
3210 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3211 .set_egress_port = mv88e6390_g1_set_egress_port,
3212 .watchdog_ops = &mv88e6390_watchdog_ops,
3213 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3214 .pot_clear = mv88e6xxx_g2_pot_clear,
3215 .reset = mv88e6352_g1_reset,
3216 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3217 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3218 .serdes_power = mv88e6390_serdes_power,
3221 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3222 /* MV88E6XXX_FAMILY_6390 */
3223 .irl_init_all = mv88e6390_g2_irl_init_all,
3224 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3225 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3226 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3227 .phy_read = mv88e6xxx_g2_smi_phy_read,
3228 .phy_write = mv88e6xxx_g2_smi_phy_write,
3229 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
3230 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
3231 .port_set_link = mv88e6xxx_port_set_link,
3232 .port_set_duplex = mv88e6xxx_port_set_duplex,
3233 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3234 .port_set_speed = mv88e6390x_port_set_speed,
3235 .port_tag_remap = mv88e6390_port_tag_remap,
3236 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3237 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3238 .port_set_ether_type = mv88e6351_port_set_ether_type,
3239 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3240 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3241 .port_pause_limit = mv88e6390_port_pause_limit,
3242 .port_set_cmode = mv88e6390x_port_set_cmode,
3243 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3244 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3245 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3246 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3247 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3248 .stats_get_strings = mv88e6320_stats_get_strings,
3249 .stats_get_stats = mv88e6390_stats_get_stats,
3250 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3251 .set_egress_port = mv88e6390_g1_set_egress_port,
3252 .watchdog_ops = &mv88e6390_watchdog_ops,
3253 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3254 .pot_clear = mv88e6xxx_g2_pot_clear,
3255 .reset = mv88e6352_g1_reset,
3256 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3257 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3258 .serdes_power = mv88e6390_serdes_power,
3261 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3263 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3264 .family = MV88E6XXX_FAMILY_6097,
3265 .name = "Marvell 88E6085",
3266 .num_databases = 4096,
3269 .port_base_addr = 0x10,
3270 .global1_addr = 0x1b,
3271 .global2_addr = 0x1c,
3272 .age_time_coeff = 15000,
3275 .atu_move_port_mask = 0xf,
3278 .tag_protocol = DSA_TAG_PROTO_DSA,
3279 .ops = &mv88e6085_ops,
3283 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3284 .family = MV88E6XXX_FAMILY_6095,
3285 .name = "Marvell 88E6095/88E6095F",
3286 .num_databases = 256,
3289 .port_base_addr = 0x10,
3290 .global1_addr = 0x1b,
3291 .global2_addr = 0x1c,
3292 .age_time_coeff = 15000,
3294 .atu_move_port_mask = 0xf,
3296 .tag_protocol = DSA_TAG_PROTO_DSA,
3297 .ops = &mv88e6095_ops,
3301 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3302 .family = MV88E6XXX_FAMILY_6097,
3303 .name = "Marvell 88E6097/88E6097F",
3304 .num_databases = 4096,
3307 .port_base_addr = 0x10,
3308 .global1_addr = 0x1b,
3309 .global2_addr = 0x1c,
3310 .age_time_coeff = 15000,
3313 .atu_move_port_mask = 0xf,
3316 .tag_protocol = DSA_TAG_PROTO_EDSA,
3317 .ops = &mv88e6097_ops,
3321 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3322 .family = MV88E6XXX_FAMILY_6165,
3323 .name = "Marvell 88E6123",
3324 .num_databases = 4096,
3327 .port_base_addr = 0x10,
3328 .global1_addr = 0x1b,
3329 .global2_addr = 0x1c,
3330 .age_time_coeff = 15000,
3333 .atu_move_port_mask = 0xf,
3336 .tag_protocol = DSA_TAG_PROTO_EDSA,
3337 .ops = &mv88e6123_ops,
3341 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3342 .family = MV88E6XXX_FAMILY_6185,
3343 .name = "Marvell 88E6131",
3344 .num_databases = 256,
3347 .port_base_addr = 0x10,
3348 .global1_addr = 0x1b,
3349 .global2_addr = 0x1c,
3350 .age_time_coeff = 15000,
3352 .atu_move_port_mask = 0xf,
3354 .tag_protocol = DSA_TAG_PROTO_DSA,
3355 .ops = &mv88e6131_ops,
3359 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3360 .family = MV88E6XXX_FAMILY_6341,
3361 .name = "Marvell 88E6341",
3362 .num_databases = 4096,
3365 .port_base_addr = 0x10,
3366 .global1_addr = 0x1b,
3367 .global2_addr = 0x1c,
3368 .age_time_coeff = 3750,
3369 .atu_move_port_mask = 0x1f,
3373 .tag_protocol = DSA_TAG_PROTO_EDSA,
3374 .ops = &mv88e6141_ops,
3378 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3379 .family = MV88E6XXX_FAMILY_6165,
3380 .name = "Marvell 88E6161",
3381 .num_databases = 4096,
3384 .port_base_addr = 0x10,
3385 .global1_addr = 0x1b,
3386 .global2_addr = 0x1c,
3387 .age_time_coeff = 15000,
3390 .atu_move_port_mask = 0xf,
3393 .tag_protocol = DSA_TAG_PROTO_EDSA,
3394 .ops = &mv88e6161_ops,
3398 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3399 .family = MV88E6XXX_FAMILY_6165,
3400 .name = "Marvell 88E6165",
3401 .num_databases = 4096,
3404 .port_base_addr = 0x10,
3405 .global1_addr = 0x1b,
3406 .global2_addr = 0x1c,
3407 .age_time_coeff = 15000,
3410 .atu_move_port_mask = 0xf,
3413 .tag_protocol = DSA_TAG_PROTO_DSA,
3414 .ops = &mv88e6165_ops,
3418 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3419 .family = MV88E6XXX_FAMILY_6351,
3420 .name = "Marvell 88E6171",
3421 .num_databases = 4096,
3424 .port_base_addr = 0x10,
3425 .global1_addr = 0x1b,
3426 .global2_addr = 0x1c,
3427 .age_time_coeff = 15000,
3430 .atu_move_port_mask = 0xf,
3433 .tag_protocol = DSA_TAG_PROTO_EDSA,
3434 .ops = &mv88e6171_ops,
3438 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3439 .family = MV88E6XXX_FAMILY_6352,
3440 .name = "Marvell 88E6172",
3441 .num_databases = 4096,
3444 .port_base_addr = 0x10,
3445 .global1_addr = 0x1b,
3446 .global2_addr = 0x1c,
3447 .age_time_coeff = 15000,
3450 .atu_move_port_mask = 0xf,
3453 .tag_protocol = DSA_TAG_PROTO_EDSA,
3454 .ops = &mv88e6172_ops,
3458 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3459 .family = MV88E6XXX_FAMILY_6351,
3460 .name = "Marvell 88E6175",
3461 .num_databases = 4096,
3464 .port_base_addr = 0x10,
3465 .global1_addr = 0x1b,
3466 .global2_addr = 0x1c,
3467 .age_time_coeff = 15000,
3470 .atu_move_port_mask = 0xf,
3473 .tag_protocol = DSA_TAG_PROTO_EDSA,
3474 .ops = &mv88e6175_ops,
3478 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3479 .family = MV88E6XXX_FAMILY_6352,
3480 .name = "Marvell 88E6176",
3481 .num_databases = 4096,
3484 .port_base_addr = 0x10,
3485 .global1_addr = 0x1b,
3486 .global2_addr = 0x1c,
3487 .age_time_coeff = 15000,
3490 .atu_move_port_mask = 0xf,
3493 .tag_protocol = DSA_TAG_PROTO_EDSA,
3494 .ops = &mv88e6176_ops,
3498 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3499 .family = MV88E6XXX_FAMILY_6185,
3500 .name = "Marvell 88E6185",
3501 .num_databases = 256,
3504 .port_base_addr = 0x10,
3505 .global1_addr = 0x1b,
3506 .global2_addr = 0x1c,
3507 .age_time_coeff = 15000,
3509 .atu_move_port_mask = 0xf,
3511 .tag_protocol = DSA_TAG_PROTO_EDSA,
3512 .ops = &mv88e6185_ops,
3516 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3517 .family = MV88E6XXX_FAMILY_6390,
3518 .name = "Marvell 88E6190",
3519 .num_databases = 4096,
3520 .num_ports = 11, /* 10 + Z80 */
3522 .port_base_addr = 0x0,
3523 .global1_addr = 0x1b,
3524 .global2_addr = 0x1c,
3525 .tag_protocol = DSA_TAG_PROTO_DSA,
3526 .age_time_coeff = 3750,
3531 .atu_move_port_mask = 0x1f,
3532 .ops = &mv88e6190_ops,
3536 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3537 .family = MV88E6XXX_FAMILY_6390,
3538 .name = "Marvell 88E6190X",
3539 .num_databases = 4096,
3540 .num_ports = 11, /* 10 + Z80 */
3542 .port_base_addr = 0x0,
3543 .global1_addr = 0x1b,
3544 .global2_addr = 0x1c,
3545 .age_time_coeff = 3750,
3548 .atu_move_port_mask = 0x1f,
3551 .tag_protocol = DSA_TAG_PROTO_DSA,
3552 .ops = &mv88e6190x_ops,
3556 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3557 .family = MV88E6XXX_FAMILY_6390,
3558 .name = "Marvell 88E6191",
3559 .num_databases = 4096,
3560 .num_ports = 11, /* 10 + Z80 */
3562 .port_base_addr = 0x0,
3563 .global1_addr = 0x1b,
3564 .global2_addr = 0x1c,
3565 .age_time_coeff = 3750,
3568 .atu_move_port_mask = 0x1f,
3571 .tag_protocol = DSA_TAG_PROTO_DSA,
3572 .ops = &mv88e6191_ops,
3576 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3577 .family = MV88E6XXX_FAMILY_6352,
3578 .name = "Marvell 88E6240",
3579 .num_databases = 4096,
3582 .port_base_addr = 0x10,
3583 .global1_addr = 0x1b,
3584 .global2_addr = 0x1c,
3585 .age_time_coeff = 15000,
3588 .atu_move_port_mask = 0xf,
3591 .tag_protocol = DSA_TAG_PROTO_EDSA,
3592 .ops = &mv88e6240_ops,
3596 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3597 .family = MV88E6XXX_FAMILY_6390,
3598 .name = "Marvell 88E6290",
3599 .num_databases = 4096,
3600 .num_ports = 11, /* 10 + Z80 */
3602 .port_base_addr = 0x0,
3603 .global1_addr = 0x1b,
3604 .global2_addr = 0x1c,
3605 .age_time_coeff = 3750,
3608 .atu_move_port_mask = 0x1f,
3611 .tag_protocol = DSA_TAG_PROTO_DSA,
3612 .ops = &mv88e6290_ops,
3616 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3617 .family = MV88E6XXX_FAMILY_6320,
3618 .name = "Marvell 88E6320",
3619 .num_databases = 4096,
3622 .port_base_addr = 0x10,
3623 .global1_addr = 0x1b,
3624 .global2_addr = 0x1c,
3625 .age_time_coeff = 15000,
3627 .atu_move_port_mask = 0xf,
3630 .tag_protocol = DSA_TAG_PROTO_EDSA,
3631 .ops = &mv88e6320_ops,
3635 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3636 .family = MV88E6XXX_FAMILY_6320,
3637 .name = "Marvell 88E6321",
3638 .num_databases = 4096,
3641 .port_base_addr = 0x10,
3642 .global1_addr = 0x1b,
3643 .global2_addr = 0x1c,
3644 .age_time_coeff = 15000,
3646 .atu_move_port_mask = 0xf,
3648 .tag_protocol = DSA_TAG_PROTO_EDSA,
3649 .ops = &mv88e6321_ops,
3653 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3654 .family = MV88E6XXX_FAMILY_6341,
3655 .name = "Marvell 88E6341",
3656 .num_databases = 4096,
3659 .port_base_addr = 0x10,
3660 .global1_addr = 0x1b,
3661 .global2_addr = 0x1c,
3662 .age_time_coeff = 3750,
3663 .atu_move_port_mask = 0x1f,
3667 .tag_protocol = DSA_TAG_PROTO_EDSA,
3668 .ops = &mv88e6341_ops,
3672 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3673 .family = MV88E6XXX_FAMILY_6351,
3674 .name = "Marvell 88E6350",
3675 .num_databases = 4096,
3678 .port_base_addr = 0x10,
3679 .global1_addr = 0x1b,
3680 .global2_addr = 0x1c,
3681 .age_time_coeff = 15000,
3684 .atu_move_port_mask = 0xf,
3687 .tag_protocol = DSA_TAG_PROTO_EDSA,
3688 .ops = &mv88e6350_ops,
3692 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3693 .family = MV88E6XXX_FAMILY_6351,
3694 .name = "Marvell 88E6351",
3695 .num_databases = 4096,
3698 .port_base_addr = 0x10,
3699 .global1_addr = 0x1b,
3700 .global2_addr = 0x1c,
3701 .age_time_coeff = 15000,
3704 .atu_move_port_mask = 0xf,
3707 .tag_protocol = DSA_TAG_PROTO_EDSA,
3708 .ops = &mv88e6351_ops,
3712 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3713 .family = MV88E6XXX_FAMILY_6352,
3714 .name = "Marvell 88E6352",
3715 .num_databases = 4096,
3718 .port_base_addr = 0x10,
3719 .global1_addr = 0x1b,
3720 .global2_addr = 0x1c,
3721 .age_time_coeff = 15000,
3724 .atu_move_port_mask = 0xf,
3727 .tag_protocol = DSA_TAG_PROTO_EDSA,
3728 .ops = &mv88e6352_ops,
3731 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3732 .family = MV88E6XXX_FAMILY_6390,
3733 .name = "Marvell 88E6390",
3734 .num_databases = 4096,
3735 .num_ports = 11, /* 10 + Z80 */
3737 .port_base_addr = 0x0,
3738 .global1_addr = 0x1b,
3739 .global2_addr = 0x1c,
3740 .age_time_coeff = 3750,
3743 .atu_move_port_mask = 0x1f,
3746 .tag_protocol = DSA_TAG_PROTO_DSA,
3747 .ops = &mv88e6390_ops,
3750 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3751 .family = MV88E6XXX_FAMILY_6390,
3752 .name = "Marvell 88E6390X",
3753 .num_databases = 4096,
3754 .num_ports = 11, /* 10 + Z80 */
3756 .port_base_addr = 0x0,
3757 .global1_addr = 0x1b,
3758 .global2_addr = 0x1c,
3759 .age_time_coeff = 3750,
3762 .atu_move_port_mask = 0x1f,
3765 .tag_protocol = DSA_TAG_PROTO_DSA,
3766 .ops = &mv88e6390x_ops,
3770 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3774 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3775 if (mv88e6xxx_table[i].prod_num == prod_num)
3776 return &mv88e6xxx_table[i];
3781 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3783 const struct mv88e6xxx_info *info;
3784 unsigned int prod_num, rev;
3788 mutex_lock(&chip->reg_lock);
3789 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3790 mutex_unlock(&chip->reg_lock);
3794 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3795 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3797 info = mv88e6xxx_lookup_info(prod_num);
3801 /* Update the compatible info with the probed one */
3804 err = mv88e6xxx_g2_require(chip);
3808 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3809 chip->info->prod_num, chip->info->name, rev);
3814 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3816 struct mv88e6xxx_chip *chip;
3818 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3824 mutex_init(&chip->reg_lock);
3825 INIT_LIST_HEAD(&chip->mdios);
3830 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3831 struct mii_bus *bus, int sw_addr)
3834 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3835 else if (chip->info->multi_chip)
3836 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3841 chip->sw_addr = sw_addr;
3846 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3848 struct mv88e6xxx_chip *chip = ds->priv;
3850 return chip->info->tag_protocol;
3853 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3854 struct device *host_dev, int sw_addr,
3857 struct mv88e6xxx_chip *chip;
3858 struct mii_bus *bus;
3861 bus = dsa_host_dev_to_mii_bus(host_dev);
3865 chip = mv88e6xxx_alloc_chip(dsa_dev);
3869 /* Legacy SMI probing will only support chips similar to 88E6085 */
3870 chip->info = &mv88e6xxx_table[MV88E6085];
3872 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3876 err = mv88e6xxx_detect(chip);
3880 mutex_lock(&chip->reg_lock);
3881 err = mv88e6xxx_switch_reset(chip);
3882 mutex_unlock(&chip->reg_lock);
3886 mv88e6xxx_phy_init(chip);
3888 err = mv88e6xxx_mdios_register(chip, NULL);
3894 return chip->info->name;
3896 devm_kfree(dsa_dev, chip);
3901 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3902 const struct switchdev_obj_port_mdb *mdb,
3903 struct switchdev_trans *trans)
3905 /* We don't need any dynamic resource from the kernel (yet),
3906 * so skip the prepare phase.
3912 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3913 const struct switchdev_obj_port_mdb *mdb,
3914 struct switchdev_trans *trans)
3916 struct mv88e6xxx_chip *chip = ds->priv;
3918 mutex_lock(&chip->reg_lock);
3919 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3920 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
3921 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3923 mutex_unlock(&chip->reg_lock);
3926 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3927 const struct switchdev_obj_port_mdb *mdb)
3929 struct mv88e6xxx_chip *chip = ds->priv;
3932 mutex_lock(&chip->reg_lock);
3933 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3934 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
3935 mutex_unlock(&chip->reg_lock);
3940 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3941 struct switchdev_obj_port_mdb *mdb,
3942 switchdev_obj_dump_cb_t *cb)
3944 struct mv88e6xxx_chip *chip = ds->priv;
3947 mutex_lock(&chip->reg_lock);
3948 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3949 mutex_unlock(&chip->reg_lock);
3954 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
3955 .probe = mv88e6xxx_drv_probe,
3956 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
3957 .setup = mv88e6xxx_setup,
3958 .set_addr = mv88e6xxx_set_addr,
3959 .adjust_link = mv88e6xxx_adjust_link,
3960 .get_strings = mv88e6xxx_get_strings,
3961 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3962 .get_sset_count = mv88e6xxx_get_sset_count,
3963 .port_enable = mv88e6xxx_port_enable,
3964 .port_disable = mv88e6xxx_port_disable,
3965 .set_eee = mv88e6xxx_set_eee,
3966 .get_eee = mv88e6xxx_get_eee,
3967 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3968 .get_eeprom = mv88e6xxx_get_eeprom,
3969 .set_eeprom = mv88e6xxx_set_eeprom,
3970 .get_regs_len = mv88e6xxx_get_regs_len,
3971 .get_regs = mv88e6xxx_get_regs,
3972 .set_ageing_time = mv88e6xxx_set_ageing_time,
3973 .port_bridge_join = mv88e6xxx_port_bridge_join,
3974 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3975 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3976 .port_fast_age = mv88e6xxx_port_fast_age,
3977 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3978 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3979 .port_vlan_add = mv88e6xxx_port_vlan_add,
3980 .port_vlan_del = mv88e6xxx_port_vlan_del,
3981 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3982 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3983 .port_fdb_add = mv88e6xxx_port_fdb_add,
3984 .port_fdb_del = mv88e6xxx_port_fdb_del,
3985 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3986 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3987 .port_mdb_add = mv88e6xxx_port_mdb_add,
3988 .port_mdb_del = mv88e6xxx_port_mdb_del,
3989 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
3990 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3991 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
3994 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3995 .ops = &mv88e6xxx_switch_ops,
3998 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4000 struct device *dev = chip->dev;
4001 struct dsa_switch *ds;
4003 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4008 ds->ops = &mv88e6xxx_switch_ops;
4009 ds->ageing_time_min = chip->info->age_time_coeff;
4010 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4012 dev_set_drvdata(dev, ds);
4014 return dsa_register_switch(ds);
4017 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4019 dsa_unregister_switch(chip->ds);
4022 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4024 struct device *dev = &mdiodev->dev;
4025 struct device_node *np = dev->of_node;
4026 const struct mv88e6xxx_info *compat_info;
4027 struct mv88e6xxx_chip *chip;
4031 compat_info = of_device_get_match_data(dev);
4035 chip = mv88e6xxx_alloc_chip(dev);
4039 chip->info = compat_info;
4041 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4045 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4046 if (IS_ERR(chip->reset))
4047 return PTR_ERR(chip->reset);
4049 err = mv88e6xxx_detect(chip);
4053 mv88e6xxx_phy_init(chip);
4055 if (chip->info->ops->get_eeprom &&
4056 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4057 chip->eeprom_len = eeprom_len;
4059 mutex_lock(&chip->reg_lock);
4060 err = mv88e6xxx_switch_reset(chip);
4061 mutex_unlock(&chip->reg_lock);
4065 chip->irq = of_irq_get(np, 0);
4066 if (chip->irq == -EPROBE_DEFER) {
4071 if (chip->irq > 0) {
4072 /* Has to be performed before the MDIO bus is created,
4073 * because the PHYs will link there interrupts to these
4074 * interrupt controllers
4076 mutex_lock(&chip->reg_lock);
4077 err = mv88e6xxx_g1_irq_setup(chip);
4078 mutex_unlock(&chip->reg_lock);
4083 if (chip->info->g2_irqs > 0) {
4084 err = mv88e6xxx_g2_irq_setup(chip);
4090 err = mv88e6xxx_mdios_register(chip, np);
4094 err = mv88e6xxx_register_switch(chip);
4101 mv88e6xxx_mdios_unregister(chip);
4103 if (chip->info->g2_irqs > 0 && chip->irq > 0)
4104 mv88e6xxx_g2_irq_free(chip);
4106 if (chip->irq > 0) {
4107 mutex_lock(&chip->reg_lock);
4108 mv88e6xxx_g1_irq_free(chip);
4109 mutex_unlock(&chip->reg_lock);
4115 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4117 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4118 struct mv88e6xxx_chip *chip = ds->priv;
4120 mv88e6xxx_phy_destroy(chip);
4121 mv88e6xxx_unregister_switch(chip);
4122 mv88e6xxx_mdios_unregister(chip);
4124 if (chip->irq > 0) {
4125 if (chip->info->g2_irqs > 0)
4126 mv88e6xxx_g2_irq_free(chip);
4127 mv88e6xxx_g1_irq_free(chip);
4131 static const struct of_device_id mv88e6xxx_of_match[] = {
4133 .compatible = "marvell,mv88e6085",
4134 .data = &mv88e6xxx_table[MV88E6085],
4137 .compatible = "marvell,mv88e6190",
4138 .data = &mv88e6xxx_table[MV88E6190],
4143 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4145 static struct mdio_driver mv88e6xxx_driver = {
4146 .probe = mv88e6xxx_probe,
4147 .remove = mv88e6xxx_remove,
4149 .name = "mv88e6085",
4150 .of_match_table = mv88e6xxx_of_match,
4154 static int __init mv88e6xxx_init(void)
4156 register_switch_driver(&mv88e6xxx_switch_drv);
4157 return mdio_driver_register(&mv88e6xxx_driver);
4159 module_init(mv88e6xxx_init);
4161 static void __exit mv88e6xxx_cleanup(void)
4163 mdio_driver_unregister(&mv88e6xxx_driver);
4164 unregister_switch_driver(&mv88e6xxx_switch_drv);
4166 module_exit(mv88e6xxx_cleanup);
4168 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4169 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4170 MODULE_LICENSE("GPL");