2 * Marvell 88E6xxx Ethernet switch single-chip definition
4 * Copyright (c) 2008 Marvell Semiconductor
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #ifndef _MV88E6XXX_CHIP_H
13 #define _MV88E6XXX_CHIP_H
15 #include <linux/if_vlan.h>
16 #include <linux/irq.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/phy.h>
22 #define UINT64_MAX (u64)(~((u64)0))
26 #define SMI_CMD_BUSY BIT(15)
27 #define SMI_CMD_CLAUSE_22 BIT(12)
28 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
29 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
30 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
31 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
32 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
33 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
36 #define MV88E6XXX_N_FID 4096
38 /* PVT limits for 4-bit port and 5-bit switch */
39 #define MV88E6XXX_MAX_PVT_SWITCHES 32
40 #define MV88E6XXX_MAX_PVT_PORTS 16
42 enum mv88e6xxx_egress_mode {
43 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
44 MV88E6XXX_EGRESS_MODE_UNTAGGED,
45 MV88E6XXX_EGRESS_MODE_TAGGED,
46 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
49 enum mv88e6xxx_frame_mode {
50 MV88E6XXX_FRAME_MODE_NORMAL,
51 MV88E6XXX_FRAME_MODE_DSA,
52 MV88E6XXX_FRAME_MODE_PROVIDER,
53 MV88E6XXX_FRAME_MODE_ETHERTYPE,
56 /* List of supported models */
57 enum mv88e6xxx_model {
86 enum mv88e6xxx_family {
87 MV88E6XXX_FAMILY_NONE,
88 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
89 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
90 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
91 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
92 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
93 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
94 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
95 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
96 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
97 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
101 /* Energy Efficient Ethernet.
105 /* Multi-chip Addressing Mode.
106 * Some chips respond to only 2 registers of its own SMI device address
107 * when it is non-zero, and use indirect access to internal registers.
109 MV88E6XXX_CAP_SMI_CMD, /* (0x00) SMI Command */
110 MV88E6XXX_CAP_SMI_DATA, /* (0x01) SMI Data */
113 /* Bitmask of capabilities */
114 #define MV88E6XXX_FLAG_EEE BIT_ULL(MV88E6XXX_CAP_EEE)
116 #define MV88E6XXX_FLAG_SMI_CMD BIT_ULL(MV88E6XXX_CAP_SMI_CMD)
117 #define MV88E6XXX_FLAG_SMI_DATA BIT_ULL(MV88E6XXX_CAP_SMI_DATA)
119 /* Multi-chip Addressing Mode */
120 #define MV88E6XXX_FLAGS_MULTI_CHIP \
121 (MV88E6XXX_FLAG_SMI_CMD | \
122 MV88E6XXX_FLAG_SMI_DATA)
124 #define MV88E6XXX_FLAGS_FAMILY_6095 \
125 (MV88E6XXX_FLAGS_MULTI_CHIP)
127 #define MV88E6XXX_FLAGS_FAMILY_6097 \
128 (MV88E6XXX_FLAGS_MULTI_CHIP)
130 #define MV88E6XXX_FLAGS_FAMILY_6165 \
131 (MV88E6XXX_FLAGS_MULTI_CHIP)
133 #define MV88E6XXX_FLAGS_FAMILY_6185 \
134 (MV88E6XXX_FLAGS_MULTI_CHIP)
136 #define MV88E6XXX_FLAGS_FAMILY_6320 \
137 (MV88E6XXX_FLAG_EEE | \
138 MV88E6XXX_FLAGS_MULTI_CHIP)
140 #define MV88E6XXX_FLAGS_FAMILY_6341 \
141 (MV88E6XXX_FLAG_EEE | \
142 MV88E6XXX_FLAGS_MULTI_CHIP)
144 #define MV88E6XXX_FLAGS_FAMILY_6351 \
145 (MV88E6XXX_FLAGS_MULTI_CHIP)
147 #define MV88E6XXX_FLAGS_FAMILY_6352 \
148 (MV88E6XXX_FLAG_EEE | \
149 MV88E6XXX_FLAGS_MULTI_CHIP)
151 #define MV88E6XXX_FLAGS_FAMILY_6390 \
152 (MV88E6XXX_FLAG_EEE | \
153 MV88E6XXX_FLAGS_MULTI_CHIP)
155 struct mv88e6xxx_ops;
157 struct mv88e6xxx_info {
158 enum mv88e6xxx_family family;
161 unsigned int num_databases;
162 unsigned int num_ports;
163 unsigned int max_vid;
164 unsigned int port_base_addr;
165 unsigned int global1_addr;
166 unsigned int global2_addr;
167 unsigned int age_time_coeff;
168 unsigned int g1_irqs;
169 unsigned int g2_irqs;
171 enum dsa_tag_protocol tag_protocol;
172 unsigned long long flags;
174 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
175 * operation. 0 means that the ATU Move operation is not supported.
177 u8 atu_move_port_mask;
178 const struct mv88e6xxx_ops *ops;
181 struct mv88e6xxx_atu_entry {
188 struct mv88e6xxx_vtu_entry {
193 u8 member[DSA_MAX_PORTS];
194 u8 state[DSA_MAX_PORTS];
197 struct mv88e6xxx_bus_ops;
198 struct mv88e6xxx_irq_ops;
200 struct mv88e6xxx_irq {
202 struct irq_chip chip;
203 struct irq_domain *domain;
207 struct mv88e6xxx_chip {
208 const struct mv88e6xxx_info *info;
210 /* The dsa_switch this private structure is related to */
211 struct dsa_switch *ds;
213 /* The device this structure is associated to */
216 /* This mutex protects the access to the switch registers */
217 struct mutex reg_lock;
219 /* The MII bus and the address on the bus that is used to
220 * communication with the switch
222 const struct mv88e6xxx_bus_ops *smi_ops;
226 /* Handles automatic disabling and re-enabling of the PHY
229 const struct mv88e6xxx_bus_ops *phy_ops;
230 struct mutex ppu_mutex;
232 struct work_struct ppu_work;
233 struct timer_list ppu_timer;
235 /* This mutex serialises access to the statistics unit.
236 * Hold this mutex over snapshot + dump sequences.
238 struct mutex stats_mutex;
240 /* A switch may have a GPIO line tied to its reset pin. Parse
241 * this from the device tree, and use it before performing
244 struct gpio_desc *reset;
246 /* set to size of eeprom if supported by the switch */
249 /* List of mdio busses */
250 struct list_head mdios;
252 /* There can be two interrupt controllers, which are chained
253 * off a GPIO as interrupt source
255 struct mv88e6xxx_irq g1_irq;
256 struct mv88e6xxx_irq g2_irq;
262 struct mv88e6xxx_bus_ops {
263 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
264 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
267 struct mv88e6xxx_mdio_bus {
269 struct mv88e6xxx_chip *chip;
270 struct list_head list;
274 struct mv88e6xxx_ops {
275 /* Ingress Rate Limit unit (IRL) operations */
276 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
278 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
279 struct ethtool_eeprom *eeprom, u8 *data);
280 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
281 struct ethtool_eeprom *eeprom, u8 *data);
283 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
285 int (*phy_read)(struct mv88e6xxx_chip *chip,
287 int addr, int reg, u16 *val);
288 int (*phy_write)(struct mv88e6xxx_chip *chip,
290 int addr, int reg, u16 val);
292 /* Priority Override Table operations */
293 int (*pot_clear)(struct mv88e6xxx_chip *chip);
295 /* PHY Polling Unit (PPU) operations */
296 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
297 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
299 /* Switch Software Reset */
300 int (*reset)(struct mv88e6xxx_chip *chip);
302 /* RGMII Receive/Transmit Timing Control
303 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
305 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
306 phy_interface_t mode);
308 #define LINK_FORCED_DOWN 0
309 #define LINK_FORCED_UP 1
310 #define LINK_UNFORCED -2
312 /* Port's MAC link state
313 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
314 * or LINK_UNFORCED for normal link detection.
316 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
318 #define DUPLEX_UNFORCED -2
320 /* Port's MAC duplex mode
322 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
323 * or DUPLEX_UNFORCED for normal duplex detection.
325 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
327 #define SPEED_MAX INT_MAX
328 #define SPEED_UNFORCED -2
330 /* Port's MAC speed (in Mbps)
332 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
333 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
335 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
337 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
339 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
340 enum mv88e6xxx_frame_mode mode);
341 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
342 bool unicast, bool multicast);
343 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
345 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
348 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
349 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
351 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
352 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
354 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
355 * Some chips allow this to be configured on specific ports.
357 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
358 phy_interface_t mode);
360 /* Some devices have a per port register indicating what is
361 * the upstream port this port should forward to.
363 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
366 /* Snapshot the statistics for a port. The statistics can then
367 * be read back a leisure but still with a consistent view.
369 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
371 /* Set the histogram mode for statistics, when the control registers
372 * are separated out of the STATS_OP register.
374 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
376 /* Return the number of strings describing statistics */
377 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
378 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
379 void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
381 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
382 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
383 const struct mv88e6xxx_irq_ops *watchdog_ops;
385 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
387 /* Power on/off a SERDES interface */
388 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);
390 /* VLAN Translation Unit operations */
391 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
392 struct mv88e6xxx_vtu_entry *entry);
393 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
394 struct mv88e6xxx_vtu_entry *entry);
397 struct mv88e6xxx_irq_ops {
398 /* Action to be performed when the interrupt happens */
399 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
400 /* Setup the hardware to generate the interrupt */
401 int (*irq_setup)(struct mv88e6xxx_chip *chip);
402 /* Reset the hardware to stop generating the interrupt */
403 void (*irq_free)(struct mv88e6xxx_chip *chip);
406 #define STATS_TYPE_PORT BIT(0)
407 #define STATS_TYPE_BANK0 BIT(1)
408 #define STATS_TYPE_BANK1 BIT(2)
410 struct mv88e6xxx_hw_stat {
411 char string[ETH_GSTRING_LEN];
417 static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip,
420 return (chip->info->flags & flags) == flags;
423 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
425 return chip->info->pvt;
428 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
430 return chip->info->num_databases;
433 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
435 return chip->info->num_ports;
438 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
440 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
443 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
444 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
445 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
447 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
448 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
450 #endif /* _MV88E6XXX_CHIP_H */