2 * Marvell 88E6xxx Ethernet switch single-chip definition
4 * Copyright (c) 2008 Marvell Semiconductor
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #ifndef _MV88E6XXX_CHIP_H
13 #define _MV88E6XXX_CHIP_H
15 #include <linux/if_vlan.h>
16 #include <linux/irq.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/phy.h>
22 #define UINT64_MAX (u64)(~((u64)0))
26 #define SMI_CMD_BUSY BIT(15)
27 #define SMI_CMD_CLAUSE_22 BIT(12)
28 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
29 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
30 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
31 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
32 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
33 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
36 #define MV88E6XXX_N_FID 4096
38 /* PVT limits for 4-bit port and 5-bit switch */
39 #define MV88E6XXX_MAX_PVT_SWITCHES 32
40 #define MV88E6XXX_MAX_PVT_PORTS 16
42 enum mv88e6xxx_egress_mode {
43 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
44 MV88E6XXX_EGRESS_MODE_UNTAGGED,
45 MV88E6XXX_EGRESS_MODE_TAGGED,
46 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
49 enum mv88e6xxx_frame_mode {
50 MV88E6XXX_FRAME_MODE_NORMAL,
51 MV88E6XXX_FRAME_MODE_DSA,
52 MV88E6XXX_FRAME_MODE_PROVIDER,
53 MV88E6XXX_FRAME_MODE_ETHERTYPE,
56 /* List of supported models */
57 enum mv88e6xxx_model {
86 enum mv88e6xxx_family {
87 MV88E6XXX_FAMILY_NONE,
88 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
89 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
90 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
91 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
92 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
93 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
94 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
95 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
96 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
97 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
101 /* Energy Efficient Ethernet.
105 /* Multi-chip Addressing Mode.
106 * Some chips respond to only 2 registers of its own SMI device address
107 * when it is non-zero, and use indirect access to internal registers.
109 MV88E6XXX_CAP_SMI_CMD, /* (0x00) SMI Command */
110 MV88E6XXX_CAP_SMI_DATA, /* (0x01) SMI Data */
112 /* Switch Global 2 Registers.
113 * The device contains a second set of global 16-bit registers.
115 MV88E6XXX_CAP_GLOBAL2,
118 /* Bitmask of capabilities */
119 #define MV88E6XXX_FLAG_EEE BIT_ULL(MV88E6XXX_CAP_EEE)
121 #define MV88E6XXX_FLAG_SMI_CMD BIT_ULL(MV88E6XXX_CAP_SMI_CMD)
122 #define MV88E6XXX_FLAG_SMI_DATA BIT_ULL(MV88E6XXX_CAP_SMI_DATA)
124 #define MV88E6XXX_FLAG_GLOBAL2 BIT_ULL(MV88E6XXX_CAP_GLOBAL2)
126 /* Multi-chip Addressing Mode */
127 #define MV88E6XXX_FLAGS_MULTI_CHIP \
128 (MV88E6XXX_FLAG_SMI_CMD | \
129 MV88E6XXX_FLAG_SMI_DATA)
131 #define MV88E6XXX_FLAGS_FAMILY_6095 \
132 (MV88E6XXX_FLAG_GLOBAL2 | \
133 MV88E6XXX_FLAGS_MULTI_CHIP)
135 #define MV88E6XXX_FLAGS_FAMILY_6097 \
136 (MV88E6XXX_FLAG_GLOBAL2 | \
137 MV88E6XXX_FLAGS_MULTI_CHIP)
139 #define MV88E6XXX_FLAGS_FAMILY_6165 \
140 (MV88E6XXX_FLAG_GLOBAL2 | \
141 MV88E6XXX_FLAGS_MULTI_CHIP)
143 #define MV88E6XXX_FLAGS_FAMILY_6185 \
144 (MV88E6XXX_FLAG_GLOBAL2 | \
145 MV88E6XXX_FLAGS_MULTI_CHIP)
147 #define MV88E6XXX_FLAGS_FAMILY_6320 \
148 (MV88E6XXX_FLAG_EEE | \
149 MV88E6XXX_FLAG_GLOBAL2 | \
150 MV88E6XXX_FLAGS_MULTI_CHIP)
152 #define MV88E6XXX_FLAGS_FAMILY_6341 \
153 (MV88E6XXX_FLAG_EEE | \
154 MV88E6XXX_FLAG_GLOBAL2 | \
155 MV88E6XXX_FLAGS_MULTI_CHIP)
157 #define MV88E6XXX_FLAGS_FAMILY_6351 \
158 (MV88E6XXX_FLAG_GLOBAL2 | \
159 MV88E6XXX_FLAGS_MULTI_CHIP)
161 #define MV88E6XXX_FLAGS_FAMILY_6352 \
162 (MV88E6XXX_FLAG_EEE | \
163 MV88E6XXX_FLAG_GLOBAL2 | \
164 MV88E6XXX_FLAGS_MULTI_CHIP)
166 #define MV88E6XXX_FLAGS_FAMILY_6390 \
167 (MV88E6XXX_FLAG_EEE | \
168 MV88E6XXX_FLAG_GLOBAL2 | \
169 MV88E6XXX_FLAGS_MULTI_CHIP)
171 struct mv88e6xxx_ops;
173 struct mv88e6xxx_info {
174 enum mv88e6xxx_family family;
177 unsigned int num_databases;
178 unsigned int num_ports;
179 unsigned int max_vid;
180 unsigned int port_base_addr;
181 unsigned int global1_addr;
182 unsigned int age_time_coeff;
183 unsigned int g1_irqs;
184 unsigned int g2_irqs;
186 enum dsa_tag_protocol tag_protocol;
187 unsigned long long flags;
189 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
190 * operation. 0 means that the ATU Move operation is not supported.
192 u8 atu_move_port_mask;
193 const struct mv88e6xxx_ops *ops;
196 struct mv88e6xxx_atu_entry {
203 struct mv88e6xxx_vtu_entry {
208 u8 member[DSA_MAX_PORTS];
209 u8 state[DSA_MAX_PORTS];
212 struct mv88e6xxx_bus_ops;
213 struct mv88e6xxx_irq_ops;
215 struct mv88e6xxx_irq {
217 struct irq_chip chip;
218 struct irq_domain *domain;
222 struct mv88e6xxx_chip {
223 const struct mv88e6xxx_info *info;
225 /* The dsa_switch this private structure is related to */
226 struct dsa_switch *ds;
228 /* The device this structure is associated to */
231 /* This mutex protects the access to the switch registers */
232 struct mutex reg_lock;
234 /* The MII bus and the address on the bus that is used to
235 * communication with the switch
237 const struct mv88e6xxx_bus_ops *smi_ops;
241 /* Handles automatic disabling and re-enabling of the PHY
244 const struct mv88e6xxx_bus_ops *phy_ops;
245 struct mutex ppu_mutex;
247 struct work_struct ppu_work;
248 struct timer_list ppu_timer;
250 /* This mutex serialises access to the statistics unit.
251 * Hold this mutex over snapshot + dump sequences.
253 struct mutex stats_mutex;
255 /* A switch may have a GPIO line tied to its reset pin. Parse
256 * this from the device tree, and use it before performing
259 struct gpio_desc *reset;
261 /* set to size of eeprom if supported by the switch */
264 /* List of mdio busses */
265 struct list_head mdios;
267 /* There can be two interrupt controllers, which are chained
268 * off a GPIO as interrupt source
270 struct mv88e6xxx_irq g1_irq;
271 struct mv88e6xxx_irq g2_irq;
277 struct mv88e6xxx_bus_ops {
278 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
279 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
282 struct mv88e6xxx_mdio_bus {
284 struct mv88e6xxx_chip *chip;
285 struct list_head list;
289 struct mv88e6xxx_ops {
290 /* Ingress Rate Limit unit (IRL) operations */
291 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
293 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
294 struct ethtool_eeprom *eeprom, u8 *data);
295 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
296 struct ethtool_eeprom *eeprom, u8 *data);
298 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
300 int (*phy_read)(struct mv88e6xxx_chip *chip,
302 int addr, int reg, u16 *val);
303 int (*phy_write)(struct mv88e6xxx_chip *chip,
305 int addr, int reg, u16 val);
307 /* Priority Override Table operations */
308 int (*pot_clear)(struct mv88e6xxx_chip *chip);
310 /* PHY Polling Unit (PPU) operations */
311 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
312 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
314 /* Switch Software Reset */
315 int (*reset)(struct mv88e6xxx_chip *chip);
317 /* RGMII Receive/Transmit Timing Control
318 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
320 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
321 phy_interface_t mode);
323 #define LINK_FORCED_DOWN 0
324 #define LINK_FORCED_UP 1
325 #define LINK_UNFORCED -2
327 /* Port's MAC link state
328 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
329 * or LINK_UNFORCED for normal link detection.
331 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
333 #define DUPLEX_UNFORCED -2
335 /* Port's MAC duplex mode
337 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
338 * or DUPLEX_UNFORCED for normal duplex detection.
340 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
342 #define SPEED_MAX INT_MAX
343 #define SPEED_UNFORCED -2
345 /* Port's MAC speed (in Mbps)
347 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
348 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
350 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
352 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
354 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
355 enum mv88e6xxx_frame_mode mode);
356 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
357 bool unicast, bool multicast);
358 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
360 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
363 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
364 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
366 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
367 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
369 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
370 * Some chips allow this to be configured on specific ports.
372 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
373 phy_interface_t mode);
375 /* Some devices have a per port register indicating what is
376 * the upstream port this port should forward to.
378 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
381 /* Snapshot the statistics for a port. The statistics can then
382 * be read back a leisure but still with a consistent view.
384 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
386 /* Set the histogram mode for statistics, when the control registers
387 * are separated out of the STATS_OP register.
389 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
391 /* Return the number of strings describing statistics */
392 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
393 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
394 void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
396 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
397 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
398 const struct mv88e6xxx_irq_ops *watchdog_ops;
400 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
402 /* Power on/off a SERDES interface */
403 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);
405 /* VLAN Translation Unit operations */
406 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
407 struct mv88e6xxx_vtu_entry *entry);
408 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
409 struct mv88e6xxx_vtu_entry *entry);
412 struct mv88e6xxx_irq_ops {
413 /* Action to be performed when the interrupt happens */
414 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
415 /* Setup the hardware to generate the interrupt */
416 int (*irq_setup)(struct mv88e6xxx_chip *chip);
417 /* Reset the hardware to stop generating the interrupt */
418 void (*irq_free)(struct mv88e6xxx_chip *chip);
421 #define STATS_TYPE_PORT BIT(0)
422 #define STATS_TYPE_BANK0 BIT(1)
423 #define STATS_TYPE_BANK1 BIT(2)
425 struct mv88e6xxx_hw_stat {
426 char string[ETH_GSTRING_LEN];
432 static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip,
435 return (chip->info->flags & flags) == flags;
438 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
440 return chip->info->pvt;
443 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
445 return chip->info->num_databases;
448 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
450 return chip->info->num_ports;
453 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
455 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
458 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
459 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
460 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
462 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
463 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
465 #endif /* _MV88E6XXX_CHIP_H */