2 * Marvell 88E6xxx Switch Port Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/bitfield.h>
16 #include <linux/if_bridge.h>
17 #include <linux/phy.h>
18 #include <linux/phylink.h>
24 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
27 int addr = chip->info->port_base_addr + port;
29 return mv88e6xxx_read(chip, addr, reg, val);
32 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
35 int addr = chip->info->port_base_addr + port;
37 return mv88e6xxx_write(chip, addr, reg, val);
40 /* Offset 0x00: MAC (or PCS or Physical) Status Register
42 * For most devices, this is read only. However the 6185 has the MyPause
45 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
51 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
56 reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
58 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
60 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
63 /* Offset 0x01: MAC (or PCS or Physical) Control Register
65 * Link, Duplex and Flow Control have one force bit, one value bit.
67 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
68 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
69 * Newer chips need a ForcedSpd bit 13 set to consider the value.
72 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
78 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
82 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
83 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
86 case PHY_INTERFACE_MODE_RGMII_RXID:
87 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
89 case PHY_INTERFACE_MODE_RGMII_TXID:
90 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
92 case PHY_INTERFACE_MODE_RGMII_ID:
93 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
94 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
96 case PHY_INTERFACE_MODE_RGMII:
102 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
106 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
107 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
108 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
113 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
114 phy_interface_t mode)
119 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
122 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
123 phy_interface_t mode)
128 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
131 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
136 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
140 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
141 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
144 case LINK_FORCED_DOWN:
145 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
148 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
149 MV88E6XXX_PORT_MAC_CTL_LINK_UP;
152 /* normal link detection */
158 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
162 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
163 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
164 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
169 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
174 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
178 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
179 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
183 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
186 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
187 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
189 case DUPLEX_UNFORCED:
190 /* normal duplex detection */
196 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
200 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
201 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
202 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
207 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
208 int speed, bool alt_bit, bool force_bit)
215 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
218 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
222 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
223 MV88E6390_PORT_MAC_CTL_ALTSPEED;
225 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
228 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
232 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
233 MV88E6390_PORT_MAC_CTL_ALTSPEED;
235 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
238 /* all bits set, fall through... */
240 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
246 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
250 reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK;
252 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
254 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
255 if (speed != SPEED_UNFORCED)
256 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
260 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
265 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
267 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
272 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
273 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
275 if (speed == SPEED_MAX)
281 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
282 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
285 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
286 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
288 if (speed == SPEED_MAX)
291 if (speed == 200 || speed > 1000)
294 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
297 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */
298 int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
300 if (speed == SPEED_MAX)
301 speed = port < 5 ? 1000 : 2500;
306 if (speed == 200 && port != 0)
309 if (speed == 2500 && port < 5)
312 return mv88e6xxx_port_set_speed(chip, port, speed, !port, true);
315 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
316 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
318 if (speed == SPEED_MAX)
324 if (speed == 200 && port < 5)
327 return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
330 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
331 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
333 if (speed == SPEED_MAX)
334 speed = port < 9 ? 1000 : 2500;
339 if (speed == 200 && port != 0)
342 if (speed == 2500 && port < 9)
345 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
348 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
349 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
351 if (speed == SPEED_MAX)
352 speed = port < 9 ? 1000 : 10000;
354 if (speed == 200 && port != 0)
357 if (speed >= 2500 && port < 9)
360 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
363 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
364 phy_interface_t mode)
371 if (port != 9 && port != 10)
374 /* Default to a slow mode, so freeing up SERDES interfaces for
375 * other ports which might use them for SFPs.
377 if (mode == PHY_INTERFACE_MODE_NA)
378 mode = PHY_INTERFACE_MODE_1000BASEX;
381 case PHY_INTERFACE_MODE_1000BASEX:
382 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASE_X;
384 case PHY_INTERFACE_MODE_SGMII:
385 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
387 case PHY_INTERFACE_MODE_2500BASEX:
388 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
390 case PHY_INTERFACE_MODE_XGMII:
391 case PHY_INTERFACE_MODE_XAUI:
392 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
394 case PHY_INTERFACE_MODE_RXAUI:
395 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
401 /* cmode doesn't change, nothing to do for us */
402 if (cmode == chip->ports[port].cmode)
405 lane = mv88e6390x_serdes_get_lane(chip, port);
409 if (chip->ports[port].serdes_irq) {
410 err = mv88e6390_serdes_irq_disable(chip, port, lane);
415 err = mv88e6390x_serdes_power(chip, port, false);
420 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
424 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
427 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
431 err = mv88e6390x_serdes_power(chip, port, true);
435 if (chip->ports[port].serdes_irq) {
436 err = mv88e6390_serdes_irq_enable(chip, port, lane);
442 chip->ports[port].cmode = cmode;
447 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
448 phy_interface_t mode)
451 case PHY_INTERFACE_MODE_NA:
453 case PHY_INTERFACE_MODE_XGMII:
454 case PHY_INTERFACE_MODE_XAUI:
455 case PHY_INTERFACE_MODE_RXAUI:
461 return mv88e6390x_port_set_cmode(chip, port, mode);
464 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
469 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
473 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
478 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
483 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
487 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
492 int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
493 struct phylink_link_state *state)
498 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
502 switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) {
503 case MV88E6XXX_PORT_STS_SPEED_10:
504 state->speed = SPEED_10;
506 case MV88E6XXX_PORT_STS_SPEED_100:
507 state->speed = SPEED_100;
509 case MV88E6XXX_PORT_STS_SPEED_1000:
510 state->speed = SPEED_1000;
512 case MV88E6XXX_PORT_STS_SPEED_10000:
513 if ((reg & MV88E6XXX_PORT_STS_CMODE_MASK) ==
514 MV88E6XXX_PORT_STS_CMODE_2500BASEX)
515 state->speed = SPEED_2500;
517 state->speed = SPEED_10000;
521 state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ?
522 DUPLEX_FULL : DUPLEX_HALF;
523 state->link = !!(reg & MV88E6XXX_PORT_STS_LINK);
524 state->an_enabled = 1;
525 state->an_complete = state->link;
530 int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
531 struct phylink_link_state *state)
533 if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
534 u8 cmode = chip->ports[port].cmode;
536 /* When a port is in "Cross-chip serdes" mode, it uses
537 * 1000Base-X full duplex mode, but there is no automatic
538 * link detection. Use the sync OK status for link (as it
539 * would do for 1000Base-X mode.)
541 if (cmode == MV88E6185_PORT_STS_CMODE_SERDES) {
545 err = mv88e6xxx_port_read(chip, port,
546 MV88E6XXX_PORT_MAC_CTL, &mac);
550 state->link = !!(mac & MV88E6185_PORT_MAC_CTL_SYNC_OK);
551 state->an_enabled = 1;
553 !!(mac & MV88E6185_PORT_MAC_CTL_AN_DONE);
555 state->link ? DUPLEX_FULL : DUPLEX_UNKNOWN;
557 state->link ? SPEED_1000 : SPEED_UNKNOWN;
563 return mv88e6352_port_link_state(chip, port, state);
566 /* Offset 0x02: Jamming Control
568 * Do not limit the period of time that this port can be paused for by
569 * the remote end or the period of time that this port can pause the
572 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
575 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
579 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
584 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
585 MV88E6390_PORT_FLOW_CTL_UPDATE |
586 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
590 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
591 MV88E6390_PORT_FLOW_CTL_UPDATE |
592 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
595 /* Offset 0x04: Port Control Register */
597 static const char * const mv88e6xxx_port_state_names[] = {
598 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
599 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
600 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
601 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
604 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
609 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
613 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
616 case BR_STATE_DISABLED:
617 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
619 case BR_STATE_BLOCKING:
620 case BR_STATE_LISTENING:
621 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
623 case BR_STATE_LEARNING:
624 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
626 case BR_STATE_FORWARDING:
627 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
635 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
639 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
640 mv88e6xxx_port_state_names[state]);
645 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
646 enum mv88e6xxx_egress_mode mode)
651 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
655 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
658 case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
659 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
661 case MV88E6XXX_EGRESS_MODE_UNTAGGED:
662 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
664 case MV88E6XXX_EGRESS_MODE_TAGGED:
665 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
667 case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
668 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
674 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
677 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
678 enum mv88e6xxx_frame_mode mode)
683 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
687 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
690 case MV88E6XXX_FRAME_MODE_NORMAL:
691 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
693 case MV88E6XXX_FRAME_MODE_DSA:
694 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
700 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
703 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
704 enum mv88e6xxx_frame_mode mode)
709 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
713 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
716 case MV88E6XXX_FRAME_MODE_NORMAL:
717 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
719 case MV88E6XXX_FRAME_MODE_DSA:
720 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
722 case MV88E6XXX_FRAME_MODE_PROVIDER:
723 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
725 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
726 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
732 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
735 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
736 int port, bool unicast)
741 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
746 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
748 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
750 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
753 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
754 bool unicast, bool multicast)
759 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
763 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK;
765 if (unicast && multicast)
766 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA;
768 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
770 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
772 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA;
774 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
777 /* Offset 0x05: Port Control 1 */
779 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
785 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
790 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
792 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
794 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
797 /* Offset 0x06: Port Based VLAN Map */
799 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
801 const u16 mask = mv88e6xxx_port_mask(chip);
805 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
812 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
816 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
821 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
823 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
827 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
828 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
832 *fid = (reg & 0xf000) >> 12;
834 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
836 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
841 *fid |= (reg & upper_mask) << 4;
847 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
849 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
853 if (fid >= mv88e6xxx_num_databases(chip))
856 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
857 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
862 reg |= (fid & 0x000f) << 12;
864 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
868 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
870 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
876 reg |= (fid >> 4) & upper_mask;
878 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
884 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
889 /* Offset 0x07: Default Port VLAN ID & Priority */
891 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
896 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
901 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
906 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
911 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
916 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
917 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
919 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
924 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
929 /* Offset 0x08: Port Control 2 Register */
931 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
932 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
933 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
934 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
935 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
938 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
939 int port, bool multicast)
944 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
949 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
951 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
953 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
956 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
957 bool unicast, bool multicast)
961 err = mv88e6185_port_set_forward_unknown(chip, port, unicast);
965 return mv88e6185_port_set_default_forward(chip, port, multicast);
968 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
974 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
978 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
979 reg |= upstream_port;
981 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
984 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
990 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
994 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
995 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
997 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1001 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1002 mv88e6xxx_port_8021q_mode_names[mode]);
1007 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
1012 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1016 reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1018 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1021 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1027 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1031 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1034 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1035 else if (size <= 2048)
1036 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1037 else if (size <= 10240)
1038 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1042 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1045 /* Offset 0x09: Port Rate Control */
1047 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1049 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1053 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1055 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1059 /* Offset 0x0C: Port ATU Control */
1061 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1063 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1066 /* Offset 0x0D: (Priority) Override Register */
1068 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1070 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1073 /* Offset 0x0f: Port Ether type */
1075 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1078 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1081 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1082 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1085 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1089 /* Use a direct priority mapping for all IEEE tagged frames */
1090 err = mv88e6xxx_port_write(chip, port,
1091 MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
1096 return mv88e6xxx_port_write(chip, port,
1097 MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
1101 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1102 int port, u16 table, u8 ptr, u16 data)
1106 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1107 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
1108 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
1110 return mv88e6xxx_port_write(chip, port,
1111 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1114 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1119 for (i = 0; i <= 7; i++) {
1120 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
1121 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1126 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
1127 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1131 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
1132 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1136 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
1137 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);