drivers/net/dsa/qca8k.c

   1 /*
   2  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   3  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   4  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   5  * Copyright (c) 2016 John Crispin <john@phrozen.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 and
   9  * only version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/phy.h>
  19 #include <linux/netdevice.h>
  20 #include <net/dsa.h>
  21 #include <linux/of_net.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/if_bridge.h>
  24 #include <linux/mdio.h>
  25 #include <linux/etherdevice.h>
  26
  27 #include "qca8k.h"
  28
  29 #define MIB_DESC(_s, _o, _n)    \
  30         {                       \
  31                 .size = (_s),   \
  32                 .offset = (_o), \
  33                 .name = (_n),   \
  34         }
  35
  36 static const struct qca8k_mib_desc ar8327_mib[] = {
  37         MIB_DESC(1, 0x00, "RxBroad"),
  38         MIB_DESC(1, 0x04, "RxPause"),
  39         MIB_DESC(1, 0x08, "RxMulti"),
  40         MIB_DESC(1, 0x0c, "RxFcsErr"),
  41         MIB_DESC(1, 0x10, "RxAlignErr"),
  42         MIB_DESC(1, 0x14, "RxRunt"),
  43         MIB_DESC(1, 0x18, "RxFragment"),
  44         MIB_DESC(1, 0x1c, "Rx64Byte"),
  45         MIB_DESC(1, 0x20, "Rx128Byte"),
  46         MIB_DESC(1, 0x24, "Rx256Byte"),
  47         MIB_DESC(1, 0x28, "Rx512Byte"),
  48         MIB_DESC(1, 0x2c, "Rx1024Byte"),
  49         MIB_DESC(1, 0x30, "Rx1518Byte"),
  50         MIB_DESC(1, 0x34, "RxMaxByte"),
  51         MIB_DESC(1, 0x38, "RxTooLong"),
  52         MIB_DESC(2, 0x3c, "RxGoodByte"),
  53         MIB_DESC(2, 0x44, "RxBadByte"),
  54         MIB_DESC(1, 0x4c, "RxOverFlow"),
  55         MIB_DESC(1, 0x50, "Filtered"),
  56         MIB_DESC(1, 0x54, "TxBroad"),
  57         MIB_DESC(1, 0x58, "TxPause"),
  58         MIB_DESC(1, 0x5c, "TxMulti"),
  59         MIB_DESC(1, 0x60, "TxUnderRun"),
  60         MIB_DESC(1, 0x64, "Tx64Byte"),
  61         MIB_DESC(1, 0x68, "Tx128Byte"),
  62         MIB_DESC(1, 0x6c, "Tx256Byte"),
  63         MIB_DESC(1, 0x70, "Tx512Byte"),
  64         MIB_DESC(1, 0x74, "Tx1024Byte"),
  65         MIB_DESC(1, 0x78, "Tx1518Byte"),
  66         MIB_DESC(1, 0x7c, "TxMaxByte"),
  67         MIB_DESC(1, 0x80, "TxOverSize"),
  68         MIB_DESC(2, 0x84, "TxByte"),
  69         MIB_DESC(1, 0x8c, "TxCollision"),
  70         MIB_DESC(1, 0x90, "TxAbortCol"),
  71         MIB_DESC(1, 0x94, "TxMultiCol"),
  72         MIB_DESC(1, 0x98, "TxSingleCol"),
  73         MIB_DESC(1, 0x9c, "TxExcDefer"),
  74         MIB_DESC(1, 0xa0, "TxDefer"),
  75         MIB_DESC(1, 0xa4, "TxLateCol"),
  76 };
  77
  78 /* The 32bit switch registers are accessed indirectly. To achieve this we need
  79  * to set the page of the register. Track the last page that was set to reduce
  80  * mdio writes
  81  */
  82 static u16 qca8k_current_page = 0xffff;
  83
  84 static void
  85 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  86 {
  87         regaddr >>= 1;
  88         *r1 = regaddr & 0x1e;
  89
  90         regaddr >>= 5;
  91         *r2 = regaddr & 0x7;
  92
  93         regaddr >>= 3;
  94         *page = regaddr & 0x3ff;
  95 }
  96
  97 static u32
  98 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
  99 {
 100         u32 val;
 101         int ret;
 102
 103         ret = bus->read(bus, phy_id, regnum);
 104         if (ret >= 0) {
 105                 val = ret;
 106                 ret = bus->read(bus, phy_id, regnum + 1);
 107                 val |= ret << 16;
 108         }
 109
 110         if (ret < 0) {
 111                 dev_err_ratelimited(&bus->dev,
 112                                     "failed to read qca8k 32bit register\n");
 113                 return ret;
 114         }
 115
 116         return val;
 117 }
 118
 119 static void
 120 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 121 {
 122         u16 lo, hi;
 123         int ret;
 124
 125         lo = val & 0xffff;
 126         hi = (u16)(val >> 16);
 127
 128         ret = bus->write(bus, phy_id, regnum, lo);
 129         if (ret >= 0)
 130                 ret = bus->write(bus, phy_id, regnum + 1, hi);
 131         if (ret < 0)
 132                 dev_err_ratelimited(&bus->dev,
 133                                     "failed to write qca8k 32bit register\n");
 134 }
 135
 136 static void
 137 qca8k_set_page(struct mii_bus *bus, u16 page)
 138 {
 139         if (page == qca8k_current_page)
 140                 return;
 141
 142         if (bus->write(bus, 0x18, 0, page) < 0)
 143                 dev_err_ratelimited(&bus->dev,
 144                                     "failed to set qca8k page\n");
 145         qca8k_current_page = page;
 146 }
 147
 148 static u32
 149 qca8k_read(struct qca8k_priv *priv, u32 reg)
 150 {
 151         u16 r1, r2, page;
 152         u32 val;
 153
 154         qca8k_split_addr(reg, &r1, &r2, &page);
 155
 156         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 157
 158         qca8k_set_page(priv->bus, page);
 159         val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
 160
 161         mutex_unlock(&priv->bus->mdio_lock);
 162
 163         return val;
 164 }
 165
 166 static void
 167 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
 168 {
 169         u16 r1, r2, page;
 170
 171         qca8k_split_addr(reg, &r1, &r2, &page);
 172
 173         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 174
 175         qca8k_set_page(priv->bus, page);
 176         qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
 177
 178         mutex_unlock(&priv->bus->mdio_lock);
 179 }
 180
 181 static u32
 182 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
 183 {
 184         u16 r1, r2, page;
 185         u32 ret;
 186
 187         qca8k_split_addr(reg, &r1, &r2, &page);
 188
 189         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 190
 191         qca8k_set_page(priv->bus, page);
 192         ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
 193         ret &= ~mask;
 194         ret |= val;
 195         qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
 196
 197         mutex_unlock(&priv->bus->mdio_lock);
 198
 199         return ret;
 200 }
 201
 202 static void
 203 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
 204 {
 205         qca8k_rmw(priv, reg, 0, val);
 206 }
 207
 208 static void
 209 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
 210 {
 211         qca8k_rmw(priv, reg, val, 0);
 212 }
 213
 214 static int
 215 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 216 {
 217         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 218
 219         *val = qca8k_read(priv, reg);
 220
 221         return 0;
 222 }
 223
 224 static int
 225 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
 226 {
 227         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 228
 229         qca8k_write(priv, reg, val);
 230
 231         return 0;
 232 }
 233
 234 static const struct regmap_range qca8k_readable_ranges[] = {
 235         regmap_reg_range(0x0000, 0x00e4), /* Global control */
 236         regmap_reg_range(0x0100, 0x0168), /* EEE control */
 237         regmap_reg_range(0x0200, 0x0270), /* Parser control */
 238         regmap_reg_range(0x0400, 0x0454), /* ACL */
 239         regmap_reg_range(0x0600, 0x0718), /* Lookup */
 240         regmap_reg_range(0x0800, 0x0b70), /* QM */
 241         regmap_reg_range(0x0c00, 0x0c80), /* PKT */
 242         regmap_reg_range(0x0e00, 0x0e98), /* L3 */
 243         regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
 244         regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
 245         regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
 246         regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
 247         regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
 248         regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
 249         regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
 250
 251 };
 252
 253 static struct regmap_access_table qca8k_readable_table = {
 254         .yes_ranges = qca8k_readable_ranges,
 255         .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
 256 };
 257
 258 static struct regmap_config qca8k_regmap_config = {
 259         .reg_bits = 16,
 260         .val_bits = 32,
 261         .reg_stride = 4,
 262         .max_register = 0x16ac, /* end MIB - Port6 range */
 263         .reg_read = qca8k_regmap_read,
 264         .reg_write = qca8k_regmap_write,
 265         .rd_table = &qca8k_readable_table,
 266 };
 267
 268 static int
 269 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
 270 {
 271         unsigned long timeout;
 272
 273         timeout = jiffies + msecs_to_jiffies(20);
 274
 275         /* loop until the busy flag has cleared */
 276         do {
 277                 u32 val = qca8k_read(priv, reg);
 278                 int busy = val & mask;
 279
 280                 if (!busy)
 281                         break;
 282                 cond_resched();
 283         } while (!time_after_eq(jiffies, timeout));
 284
 285         return time_after_eq(jiffies, timeout);
 286 }
 287
 288 static void
 289 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
 290 {
 291         u32 reg[4];
 292         int i;
 293
 294         /* load the ARL table into an array */
 295         for (i = 0; i < 4; i++)
 296                 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
 297
 298         /* vid - 83:72 */
 299         fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
 300         /* aging - 67:64 */
 301         fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
 302         /* portmask - 54:48 */
 303         fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
 304         /* mac - 47:0 */
 305         fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
 306         fdb->mac[1] = reg[1] & 0xff;
 307         fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
 308         fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
 309         fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
 310         fdb->mac[5] = reg[0] & 0xff;
 311 }
 312
 313 static void
 314 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
 315                 u8 aging)
 316 {
 317         u32 reg[3] = { 0 };
 318         int i;
 319
 320         /* vid - 83:72 */
 321         reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
 322         /* aging - 67:64 */
 323         reg[2] |= aging & QCA8K_ATU_STATUS_M;
 324         /* portmask - 54:48 */
 325         reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
 326         /* mac - 47:0 */
 327         reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
 328         reg[1] |= mac[1];
 329         reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
 330         reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
 331         reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
 332         reg[0] |= mac[5];
 333
 334         /* load the array into the ARL table */
 335         for (i = 0; i < 3; i++)
 336                 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
 337 }
 338
 339 static int
 340 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
 341 {
 342         u32 reg;
 343
 344         /* Set the command and FDB index */
 345         reg = QCA8K_ATU_FUNC_BUSY;
 346         reg |= cmd;
 347         if (port >= 0) {
 348                 reg |= QCA8K_ATU_FUNC_PORT_EN;
 349                 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
 350         }
 351
 352         /* Write the function register triggering the table access */
 353         qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
 354
 355         /* wait for completion */
 356         if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
 357                 return -1;
 358
 359         /* Check for table full violation when adding an entry */
 360         if (cmd == QCA8K_FDB_LOAD) {
 361                 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
 362                 if (reg & QCA8K_ATU_FUNC_FULL)
 363                         return -1;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int
 370 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
 371 {
 372         int ret;
 373
 374         qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
 375         ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
 376         if (ret >= 0)
 377                 qca8k_fdb_read(priv, fdb);
 378
 379         return ret;
 380 }
 381
 382 static int
 383 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
 384               u16 vid, u8 aging)
 385 {
 386         int ret;
 387
 388         mutex_lock(&priv->reg_mutex);
 389         qca8k_fdb_write(priv, vid, port_mask, mac, aging);
 390         ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
 391         mutex_unlock(&priv->reg_mutex);
 392
 393         return ret;
 394 }
 395
 396 static int
 397 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
 398 {
 399         int ret;
 400
 401         mutex_lock(&priv->reg_mutex);
 402         qca8k_fdb_write(priv, vid, port_mask, mac, 0);
 403         ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
 404         mutex_unlock(&priv->reg_mutex);
 405
 406         return ret;
 407 }
 408
 409 static void
 410 qca8k_fdb_flush(struct qca8k_priv *priv)
 411 {
 412         mutex_lock(&priv->reg_mutex);
 413         qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
 414         mutex_unlock(&priv->reg_mutex);
 415 }
 416
 417 static void
 418 qca8k_mib_init(struct qca8k_priv *priv)
 419 {
 420         mutex_lock(&priv->reg_mutex);
 421         qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
 422         qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
 423         qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
 424         qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
 425         mutex_unlock(&priv->reg_mutex);
 426 }
 427
 428 static int
 429 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 430 {
 431         u32 reg;
 432
 433         switch (port) {
 434         case 0:
 435                 reg = QCA8K_REG_PORT0_PAD_CTRL;
 436                 break;
 437         case 6:
 438                 reg = QCA8K_REG_PORT6_PAD_CTRL;
 439                 break;
 440         default:
 441                 pr_err("Can't set PAD_CTRL on port %d\n", port);
 442                 return -EINVAL;
 443         }
 444
 445         /* Configure a port to be directly connected to an external
 446          * PHY or MAC.
 447          */
 448         switch (mode) {
 449         case PHY_INTERFACE_MODE_RGMII:
 450                 qca8k_write(priv, reg,
 451                             QCA8K_PORT_PAD_RGMII_EN |
 452                             QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
 453                             QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
 454
 455                 /* According to the datasheet, RGMII delay is enabled through
 456                  * PORT5_PAD_CTRL for all ports, rather than individual port
 457                  * registers
 458                  */
 459                 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
 460                             QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
 461                 break;
 462         case PHY_INTERFACE_MODE_SGMII:
 463                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
 464                 break;
 465         default:
 466                 pr_err("xMII mode %d not supported\n", mode);
 467                 return -EINVAL;
 468         }
 469
 470         return 0;
 471 }
 472
 473 static void
 474 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
 475 {
 476         u32 mask = QCA8K_PORT_STATUS_TXMAC;
 477
 478         /* Port 0 and 6 have no internal PHY */
 479         if ((port > 0) && (port < 6))
 480                 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
 481
 482         if (enable)
 483                 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
 484         else
 485                 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
 486 }
 487
 488 static int
 489 qca8k_setup(struct dsa_switch *ds)
 490 {
 491         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 492         int ret, i, phy_mode = -1;
 493
 494         /* Make sure that port 0 is the cpu port */
 495         if (!dsa_is_cpu_port(ds, 0)) {
 496                 pr_err("port 0 is not the CPU port\n");
 497                 return -EINVAL;
 498         }
 499
 500         mutex_init(&priv->reg_mutex);
 501
 502         /* Start by setting up the register mapping */
 503         priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
 504                                         &qca8k_regmap_config);
 505         if (IS_ERR(priv->regmap))
 506                 pr_warn("regmap initialization failed");
 507
 508         /* Initialize CPU port pad mode (xMII type, delays...) */
 509         phy_mode = of_get_phy_mode(ds->dst->cpu_dp->dn);
 510         if (phy_mode < 0) {
 511                 pr_err("Can't find phy-mode for master device\n");
 512                 return phy_mode;
 513         }
 514         ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
 515         if (ret < 0)
 516                 return ret;
 517
 518         /* Enable CPU Port */
 519         qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
 520                       QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
 521         qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
 522         priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
 523
 524         /* Enable MIB counters */
 525         qca8k_mib_init(priv);
 526
 527         /* Enable QCA header mode on the cpu port */
 528         qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
 529                     QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
 530                     QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
 531
 532         /* Disable forwarding by default on all ports */
 533         for (i = 0; i < QCA8K_NUM_PORTS; i++)
 534                 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 535                           QCA8K_PORT_LOOKUP_MEMBER, 0);
 536
 537         /* Disable MAC by default on all user ports */
 538         for (i = 1; i < QCA8K_NUM_PORTS; i++)
 539                 if (ds->enabled_port_mask & BIT(i))
 540                         qca8k_port_set_status(priv, i, 0);
 541
 542         /* Forward all unknown frames to CPU port for Linux processing */
 543         qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
 544                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
 545                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
 546                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
 547                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
 548
 549         /* Setup connection between CPU port & user ports */
 550         for (i = 0; i < DSA_MAX_PORTS; i++) {
 551                 /* CPU port gets connected to all user ports of the switch */
 552                 if (dsa_is_cpu_port(ds, i)) {
 553                         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
 554                                   QCA8K_PORT_LOOKUP_MEMBER,
 555                                   ds->enabled_port_mask);
 556                 }
 557
 558                 /* Invividual user ports get connected to CPU port only */
 559                 if (ds->enabled_port_mask & BIT(i)) {
 560                         int shift = 16 * (i % 2);
 561
 562                         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 563                                   QCA8K_PORT_LOOKUP_MEMBER,
 564                                   BIT(QCA8K_CPU_PORT));
 565
 566                         /* Enable ARP Auto-learning by default */
 567                         qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 568                                       QCA8K_PORT_LOOKUP_LEARN);
 569
 570                         /* For port based vlans to work we need to set the
 571                          * default egress vid
 572                          */
 573                         qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
 574                                   0xffff << shift, 1 << shift);
 575                         qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
 576                                     QCA8K_PORT_VLAN_CVID(1) |
 577                                     QCA8K_PORT_VLAN_SVID(1));
 578                 }
 579         }
 580
 581         /* Flush the FDB table */
 582         qca8k_fdb_flush(priv);
 583
 584         return 0;
 585 }
 586
 587 static int
 588 qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum)
 589 {
 590         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 591
 592         return mdiobus_read(priv->bus, phy, regnum);
 593 }
 594
 595 static int
 596 qca8k_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val)
 597 {
 598         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 599
 600         return mdiobus_write(priv->bus, phy, regnum, val);
 601 }
 602
 603 static void
 604 qca8k_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 605 {
 606         int i;
 607
 608         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
 609                 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
 610                         ETH_GSTRING_LEN);
 611 }
 612
 613 static void
 614 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
 615                         uint64_t *data)
 616 {
 617         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 618         const struct qca8k_mib_desc *mib;
 619         u32 reg, i;
 620         u64 hi;
 621
 622         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
 623                 mib = &ar8327_mib[i];
 624                 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
 625
 626                 data[i] = qca8k_read(priv, reg);
 627                 if (mib->size == 2) {
 628                         hi = qca8k_read(priv, reg + 4);
 629                         data[i] |= hi << 32;
 630                 }
 631         }
 632 }
 633
 634 static int
 635 qca8k_get_sset_count(struct dsa_switch *ds)
 636 {
 637         return ARRAY_SIZE(ar8327_mib);
 638 }
 639
 640 static void
 641 qca8k_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
 642 {
 643         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 644         u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
 645         u32 reg;
 646
 647         mutex_lock(&priv->reg_mutex);
 648         reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
 649         if (enable)
 650                 reg |= lpi_en;
 651         else
 652                 reg &= ~lpi_en;
 653         qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
 654         mutex_unlock(&priv->reg_mutex);
 655 }
 656
 657 static int
 658 qca8k_eee_init(struct dsa_switch *ds, int port,
 659                struct phy_device *phy)
 660 {
 661         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 662         struct ethtool_eee *p = &priv->port_sts[port].eee;
 663         int ret;
 664
 665         p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
 666
 667         ret = phy_init_eee(phy, 0);
 668         if (ret)
 669                 return ret;
 670
 671         qca8k_eee_enable_set(ds, port, true);
 672
 673         return 0;
 674 }
 675
 676 static int
 677 qca8k_set_eee(struct dsa_switch *ds, int port,
 678               struct phy_device *phydev,
 679               struct ethtool_eee *e)
 680 {
 681         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 682         struct ethtool_eee *p = &priv->port_sts[port].eee;
 683         int ret = 0;
 684
 685         p->eee_enabled = e->eee_enabled;
 686
 687         if (e->eee_enabled) {
 688                 p->eee_enabled = qca8k_eee_init(ds, port, phydev);
 689                 if (!p->eee_enabled)
 690                         ret = -EOPNOTSUPP;
 691         }
 692         qca8k_eee_enable_set(ds, port, p->eee_enabled);
 693
 694         return ret;
 695 }
 696
 697 static int
 698 qca8k_get_eee(struct dsa_switch *ds, int port,
 699               struct ethtool_eee *e)
 700 {
 701         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 702         struct ethtool_eee *p = &priv->port_sts[port].eee;
 703         struct net_device *netdev = ds->ports[port].netdev;
 704         int ret;
 705
 706         ret = phy_ethtool_get_eee(netdev->phydev, p);
 707         if (!ret)
 708                 e->eee_active =
 709                         !!(p->supported & p->advertised & p->lp_advertised);
 710         else
 711                 e->eee_active = 0;
 712
 713         e->eee_enabled = p->eee_enabled;
 714
 715         return ret;
 716 }
 717
 718 static void
 719 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
 720 {
 721         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 722         u32 stp_state;
 723
 724         switch (state) {
 725         case BR_STATE_DISABLED:
 726                 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
 727                 break;
 728         case BR_STATE_BLOCKING:
 729                 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
 730                 break;
 731         case BR_STATE_LISTENING:
 732                 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
 733                 break;
 734         case BR_STATE_LEARNING:
 735                 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
 736                 break;
 737         case BR_STATE_FORWARDING:
 738         default:
 739                 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
 740                 break;
 741         }
 742
 743         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
 744                   QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
 745 }
 746
 747 static int
 748 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
 749 {
 750         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 751         int port_mask = BIT(QCA8K_CPU_PORT);
 752         int i;
 753
 754         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
 755                 if (ds->ports[i].bridge_dev != br)
 756                         continue;
 757                 /* Add this port to the portvlan mask of the other ports
 758                  * in the bridge
 759                  */
 760                 qca8k_reg_set(priv,
 761                               QCA8K_PORT_LOOKUP_CTRL(i),
 762                               BIT(port));
 763                 if (i != port)
 764                         port_mask |= BIT(i);
 765         }
 766         /* Add all other ports to this ports portvlan mask */
 767         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
 768                   QCA8K_PORT_LOOKUP_MEMBER, port_mask);
 769
 770         return 0;
 771 }
 772
 773 static void
 774 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
 775 {
 776         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 777         int i;
 778
 779         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
 780                 if (ds->ports[i].bridge_dev != br)
 781                         continue;
 782                 /* Remove this port to the portvlan mask of the other ports
 783                  * in the bridge
 784                  */
 785                 qca8k_reg_clear(priv,
 786                                 QCA8K_PORT_LOOKUP_CTRL(i),
 787                                 BIT(port));
 788         }
 789
 790         /* Set the cpu port to be the only one in the portvlan mask of
 791          * this port
 792          */
 793         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
 794                   QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
 795 }
 796
 797 static int
 798 qca8k_port_enable(struct dsa_switch *ds, int port,
 799                   struct phy_device *phy)
 800 {
 801         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 802
 803         qca8k_port_set_status(priv, port, 1);
 804         priv->port_sts[port].enabled = 1;
 805
 806         return 0;
 807 }
 808
 809 static void
 810 qca8k_port_disable(struct dsa_switch *ds, int port,
 811                    struct phy_device *phy)
 812 {
 813         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 814
 815         qca8k_port_set_status(priv, port, 0);
 816         priv->port_sts[port].enabled = 0;
 817 }
 818
 819 static int
 820 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
 821                       u16 port_mask, u16 vid)
 822 {
 823         /* Set the vid to the port vlan id if no vid is set */
 824         if (!vid)
 825                 vid = 1;
 826
 827         return qca8k_fdb_add(priv, addr, port_mask, vid,
 828                              QCA8K_ATU_STATUS_STATIC);
 829 }
 830
 831 static int
 832 qca8k_port_fdb_prepare(struct dsa_switch *ds, int port,
 833                        const struct switchdev_obj_port_fdb *fdb,
 834                        struct switchdev_trans *trans)
 835 {
 836         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 837
 838         /* The FDB table for static and auto learned entries is the same. We
 839          * need to reserve an entry with no port_mask set to make sure that
 840          * when port_fdb_add is called an entry is still available. Otherwise
 841          * the last free entry might have been used up by auto learning
 842          */
 843         return qca8k_port_fdb_insert(priv, fdb->addr, 0, fdb->vid);
 844 }
 845
 846 static void
 847 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
 848                    const struct switchdev_obj_port_fdb *fdb,
 849                    struct switchdev_trans *trans)
 850 {
 851         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 852         u16 port_mask = BIT(port);
 853
 854         /* Update the FDB entry adding the port_mask */
 855         qca8k_port_fdb_insert(priv, fdb->addr, port_mask, fdb->vid);
 856 }
 857
 858 static int
 859 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
 860                    const struct switchdev_obj_port_fdb *fdb)
 861 {
 862         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 863         u16 port_mask = BIT(port);
 864         u16 vid = fdb->vid;
 865
 866         if (!vid)
 867                 vid = 1;
 868
 869         return qca8k_fdb_del(priv, fdb->addr, port_mask, vid);
 870 }
 871
 872 static int
 873 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
 874                     struct switchdev_obj_port_fdb *fdb,
 875                     switchdev_obj_dump_cb_t *cb)
 876 {
 877         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 878         struct qca8k_fdb _fdb = { 0 };
 879         int cnt = QCA8K_NUM_FDB_RECORDS;
 880         int ret = 0;
 881
 882         mutex_lock(&priv->reg_mutex);
 883         while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
 884                 if (!_fdb.aging)
 885                         break;
 886
 887                 ether_addr_copy(fdb->addr, _fdb.mac);
 888                 fdb->vid = _fdb.vid;
 889                 if (_fdb.aging == QCA8K_ATU_STATUS_STATIC)
 890                         fdb->ndm_state = NUD_NOARP;
 891                 else
 892                         fdb->ndm_state = NUD_REACHABLE;
 893
 894                 ret = cb(&fdb->obj);
 895                 if (ret)
 896                         break;
 897         }
 898         mutex_unlock(&priv->reg_mutex);
 899
 900         return 0;
 901 }
 902
 903 static enum dsa_tag_protocol
 904 qca8k_get_tag_protocol(struct dsa_switch *ds)
 905 {
 906         return DSA_TAG_PROTO_QCA;
 907 }
 908
 909 static const struct dsa_switch_ops qca8k_switch_ops = {
 910         .get_tag_protocol       = qca8k_get_tag_protocol,
 911         .setup                  = qca8k_setup,
 912         .get_strings            = qca8k_get_strings,
 913         .phy_read               = qca8k_phy_read,
 914         .phy_write              = qca8k_phy_write,
 915         .get_ethtool_stats      = qca8k_get_ethtool_stats,
 916         .get_sset_count         = qca8k_get_sset_count,
 917         .get_eee                = qca8k_get_eee,
 918         .set_eee                = qca8k_set_eee,
 919         .port_enable            = qca8k_port_enable,
 920         .port_disable           = qca8k_port_disable,
 921         .port_stp_state_set     = qca8k_port_stp_state_set,
 922         .port_bridge_join       = qca8k_port_bridge_join,
 923         .port_bridge_leave      = qca8k_port_bridge_leave,
 924         .port_fdb_prepare       = qca8k_port_fdb_prepare,
 925         .port_fdb_add           = qca8k_port_fdb_add,
 926         .port_fdb_del           = qca8k_port_fdb_del,
 927         .port_fdb_dump          = qca8k_port_fdb_dump,
 928 };
 929
 930 static int
 931 qca8k_sw_probe(struct mdio_device *mdiodev)
 932 {
 933         struct qca8k_priv *priv;
 934         u32 id;
 935
 936         /* allocate the private data struct so that we can probe the switches
 937          * ID register
 938          */
 939         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
 940         if (!priv)
 941                 return -ENOMEM;
 942
 943         priv->bus = mdiodev->bus;
 944
 945         /* read the switches ID register */
 946         id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
 947         id >>= QCA8K_MASK_CTRL_ID_S;
 948         id &= QCA8K_MASK_CTRL_ID_M;
 949         if (id != QCA8K_ID_QCA8337)
 950                 return -ENODEV;
 951
 952         priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
 953         if (!priv->ds)
 954                 return -ENOMEM;
 955
 956         priv->ds->priv = priv;
 957         priv->ds->ops = &qca8k_switch_ops;
 958         mutex_init(&priv->reg_mutex);
 959         dev_set_drvdata(&mdiodev->dev, priv);
 960
 961         return dsa_register_switch(priv->ds);
 962 }
 963
 964 static void
 965 qca8k_sw_remove(struct mdio_device *mdiodev)
 966 {
 967         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
 968         int i;
 969
 970         for (i = 0; i < QCA8K_NUM_PORTS; i++)
 971                 qca8k_port_set_status(priv, i, 0);
 972
 973         dsa_unregister_switch(priv->ds);
 974 }
 975
 976 #ifdef CONFIG_PM_SLEEP
 977 static void
 978 qca8k_set_pm(struct qca8k_priv *priv, int enable)
 979 {
 980         int i;
 981
 982         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 983                 if (!priv->port_sts[i].enabled)
 984                         continue;
 985
 986                 qca8k_port_set_status(priv, i, enable);
 987         }
 988 }
 989
 990 static int qca8k_suspend(struct device *dev)
 991 {
 992         struct platform_device *pdev = to_platform_device(dev);
 993         struct qca8k_priv *priv = platform_get_drvdata(pdev);
 994
 995         qca8k_set_pm(priv, 0);
 996
 997         return dsa_switch_suspend(priv->ds);
 998 }
 999
1000 static int qca8k_resume(struct device *dev)
1001 {
1002         struct platform_device *pdev = to_platform_device(dev);
1003         struct qca8k_priv *priv = platform_get_drvdata(pdev);
1004
1005         qca8k_set_pm(priv, 1);
1006
1007         return dsa_switch_resume(priv->ds);
1008 }
1009 #endif /* CONFIG_PM_SLEEP */
1010
1011 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
1012                          qca8k_suspend, qca8k_resume);
1013
1014 static const struct of_device_id qca8k_of_match[] = {
1015         { .compatible = "qca,qca8337" },
1016         { /* sentinel */ },
1017 };
1018
1019 static struct mdio_driver qca8kmdio_driver = {
1020         .probe  = qca8k_sw_probe,
1021         .remove = qca8k_sw_remove,
1022         .mdiodrv.driver = {
1023                 .name = "qca8k",
1024                 .of_match_table = qca8k_of_match,
1025                 .pm = &qca8k_pm_ops,
1026         },
1027 };
1028
1029 mdio_module_driver(qca8kmdio_driver);
1030
1031 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1032 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1033 MODULE_LICENSE("GPL v2");
1034 MODULE_ALIAS("platform:qca8k");