1 /* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
31 #include <linux/atomic.h>
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/if_vlan.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/of_device.h>
42 #include <linux/of_mdio.h>
43 #include <linux/of_net.h>
44 #include <linux/of_platform.h>
45 #include <linux/phy.h>
46 #include <linux/platform_device.h>
47 #include <linux/skbuff.h>
48 #include <asm/cacheflush.h>
50 #include "altera_utils.h"
51 #include "altera_tse.h"
52 #include "altera_sgdma.h"
53 #include "altera_msgdma.h"
55 static atomic_t instance_count = ATOMIC_INIT(~0);
56 /* Module parameters */
57 static int debug = -1;
58 module_param(debug, int, S_IRUGO | S_IWUSR);
59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
62 NETIF_MSG_LINK | NETIF_MSG_IFUP |
65 #define RX_DESCRIPTORS 64
66 static int dma_rx_num = RX_DESCRIPTORS;
67 module_param(dma_rx_num, int, S_IRUGO | S_IWUSR);
68 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
70 #define TX_DESCRIPTORS 64
71 static int dma_tx_num = TX_DESCRIPTORS;
72 module_param(dma_tx_num, int, S_IRUGO | S_IWUSR);
73 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
78 /* Make sure DMA buffer size is larger than the max frame size
79 * plus some alignment offset and a VLAN header. If the max frame size is
80 * 1518, a VLAN header would be additional 4 bytes and additional
81 * headroom for alignment is 2 bytes, 2048 is just fine.
83 #define ALTERA_RXDMABUFFER_SIZE 2048
85 /* Allow network stack to resume queueing packets after we've
86 * finished transmitting at least 1/4 of the packets in the queue.
88 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
90 #define TXQUEUESTOP_THRESHHOLD 2
92 static const struct of_device_id altera_tse_ids[];
94 static inline u32 tse_tx_avail(struct altera_tse_private *priv)
96 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
99 /* MDIO specific functions
101 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
103 struct net_device *ndev = bus->priv;
104 struct altera_tse_private *priv = netdev_priv(ndev);
106 /* set MDIO address */
107 csrwr32((mii_id & 0x1f), priv->mac_dev,
108 tse_csroffs(mdio_phy1_addr));
111 return csrrd32(priv->mac_dev,
112 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
115 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
118 struct net_device *ndev = bus->priv;
119 struct altera_tse_private *priv = netdev_priv(ndev);
121 /* set MDIO address */
122 csrwr32((mii_id & 0x1f), priv->mac_dev,
123 tse_csroffs(mdio_phy1_addr));
126 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
130 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
132 struct altera_tse_private *priv = netdev_priv(dev);
135 struct device_node *mdio_node = NULL;
136 struct mii_bus *mdio = NULL;
137 struct device_node *child_node = NULL;
139 for_each_child_of_node(priv->device->of_node, child_node) {
140 if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
141 mdio_node = child_node;
147 netdev_dbg(dev, "FOUND MDIO subnode\n");
149 netdev_dbg(dev, "NO MDIO subnode\n");
153 mdio = mdiobus_alloc();
155 netdev_err(dev, "Error allocating MDIO bus\n");
159 mdio->name = ALTERA_TSE_RESOURCE_NAME;
160 mdio->read = &altera_tse_mdio_read;
161 mdio->write = &altera_tse_mdio_write;
162 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
164 mdio->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
165 if (mdio->irq == NULL) {
169 for (i = 0; i < PHY_MAX_ADDR; i++)
170 mdio->irq[i] = PHY_POLL;
173 mdio->parent = priv->device;
175 ret = of_mdiobus_register(mdio, mdio_node);
177 netdev_err(dev, "Cannot register MDIO bus %s\n",
179 goto out_free_mdio_irq;
182 if (netif_msg_drv(priv))
183 netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
195 static void altera_tse_mdio_destroy(struct net_device *dev)
197 struct altera_tse_private *priv = netdev_priv(dev);
199 if (priv->mdio == NULL)
202 if (netif_msg_drv(priv))
203 netdev_info(dev, "MDIO bus %s: removed\n",
206 mdiobus_unregister(priv->mdio);
207 kfree(priv->mdio->irq);
208 mdiobus_free(priv->mdio);
212 static int tse_init_rx_buffer(struct altera_tse_private *priv,
213 struct tse_buffer *rxbuffer, int len)
215 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
219 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
223 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
224 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
225 dev_kfree_skb_any(rxbuffer->skb);
228 rxbuffer->dma_addr &= (dma_addr_t)~3;
233 static void tse_free_rx_buffer(struct altera_tse_private *priv,
234 struct tse_buffer *rxbuffer)
236 struct sk_buff *skb = rxbuffer->skb;
237 dma_addr_t dma_addr = rxbuffer->dma_addr;
241 dma_unmap_single(priv->device, dma_addr,
244 dev_kfree_skb_any(skb);
245 rxbuffer->skb = NULL;
246 rxbuffer->dma_addr = 0;
250 /* Unmap and free Tx buffer resources
252 static void tse_free_tx_buffer(struct altera_tse_private *priv,
253 struct tse_buffer *buffer)
255 if (buffer->dma_addr) {
256 if (buffer->mapped_as_page)
257 dma_unmap_page(priv->device, buffer->dma_addr,
258 buffer->len, DMA_TO_DEVICE);
260 dma_unmap_single(priv->device, buffer->dma_addr,
261 buffer->len, DMA_TO_DEVICE);
262 buffer->dma_addr = 0;
265 dev_kfree_skb_any(buffer->skb);
270 static int alloc_init_skbufs(struct altera_tse_private *priv)
272 unsigned int rx_descs = priv->rx_ring_size;
273 unsigned int tx_descs = priv->tx_ring_size;
277 /* Create Rx ring buffer */
278 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
283 /* Create Tx ring buffer */
284 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
293 for (i = 0; i < rx_descs; i++) {
294 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
295 priv->rx_dma_buf_sz);
297 goto err_init_rx_buffers;
306 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
307 kfree(priv->tx_ring);
309 kfree(priv->rx_ring);
314 static void free_skbufs(struct net_device *dev)
316 struct altera_tse_private *priv = netdev_priv(dev);
317 unsigned int rx_descs = priv->rx_ring_size;
318 unsigned int tx_descs = priv->tx_ring_size;
321 /* Release the DMA TX/RX socket buffers */
322 for (i = 0; i < rx_descs; i++)
323 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
324 for (i = 0; i < tx_descs; i++)
325 tse_free_tx_buffer(priv, &priv->tx_ring[i]);
328 kfree(priv->tx_ring);
331 /* Reallocate the skb for the reception process
333 static inline void tse_rx_refill(struct altera_tse_private *priv)
335 unsigned int rxsize = priv->rx_ring_size;
339 for (; priv->rx_cons - priv->rx_prod > 0;
341 entry = priv->rx_prod % rxsize;
342 if (likely(priv->rx_ring[entry].skb == NULL)) {
343 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
344 priv->rx_dma_buf_sz);
345 if (unlikely(ret != 0))
347 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
352 /* Pull out the VLAN tag and fix up the packet
354 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
356 struct ethhdr *eth_hdr;
358 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
359 !__vlan_get_tag(skb, &vid)) {
360 eth_hdr = (struct ethhdr *)skb->data;
361 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
362 skb_pull(skb, VLAN_HLEN);
363 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
367 /* Receive a packet: retrieve and pass over to upper levels
369 static int tse_rx(struct altera_tse_private *priv, int limit)
371 unsigned int count = 0;
372 unsigned int next_entry;
374 unsigned int entry = priv->rx_cons % priv->rx_ring_size;
379 /* Check for count < limit first as get_rx_status is changing
380 * the response-fifo so we must process the next packet
381 * after calling get_rx_status if a response is pending.
382 * (reading the last byte of the response pops the value from the fifo.)
384 while ((count < limit) &&
385 ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) {
386 pktstatus = rxstatus >> 16;
387 pktlength = rxstatus & 0xffff;
389 if ((pktstatus & 0xFF) || (pktlength == 0))
390 netdev_err(priv->dev,
391 "RCV pktstatus %08X pktlength %08X\n",
392 pktstatus, pktlength);
395 next_entry = (++priv->rx_cons) % priv->rx_ring_size;
397 skb = priv->rx_ring[entry].skb;
398 if (unlikely(!skb)) {
399 netdev_err(priv->dev,
400 "%s: Inconsistent Rx descriptor chain\n",
402 priv->dev->stats.rx_dropped++;
405 priv->rx_ring[entry].skb = NULL;
407 skb_put(skb, pktlength);
409 /* make cache consistent with receive packet buffer */
410 dma_sync_single_for_cpu(priv->device,
411 priv->rx_ring[entry].dma_addr,
412 priv->rx_ring[entry].len,
415 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
416 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
418 if (netif_msg_pktdata(priv)) {
419 netdev_info(priv->dev, "frame received %d bytes\n",
421 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
422 16, 1, skb->data, pktlength, true);
425 tse_rx_vlan(priv->dev, skb);
427 skb->protocol = eth_type_trans(skb, priv->dev);
428 skb_checksum_none_assert(skb);
430 napi_gro_receive(&priv->napi, skb);
432 priv->dev->stats.rx_packets++;
433 priv->dev->stats.rx_bytes += pktlength;
443 /* Reclaim resources after transmission completes
445 static int tse_tx_complete(struct altera_tse_private *priv)
447 unsigned int txsize = priv->tx_ring_size;
450 struct tse_buffer *tx_buff;
453 spin_lock(&priv->tx_lock);
455 ready = priv->dmaops->tx_completions(priv);
457 /* Free sent buffers */
458 while (ready && (priv->tx_cons != priv->tx_prod)) {
459 entry = priv->tx_cons % txsize;
460 tx_buff = &priv->tx_ring[entry];
462 if (netif_msg_tx_done(priv))
463 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
464 __func__, priv->tx_prod, priv->tx_cons);
466 if (likely(tx_buff->skb))
467 priv->dev->stats.tx_packets++;
469 tse_free_tx_buffer(priv, tx_buff);
476 if (unlikely(netif_queue_stopped(priv->dev) &&
477 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
478 netif_tx_lock(priv->dev);
479 if (netif_queue_stopped(priv->dev) &&
480 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
481 if (netif_msg_tx_done(priv))
482 netdev_dbg(priv->dev, "%s: restart transmit\n",
484 netif_wake_queue(priv->dev);
486 netif_tx_unlock(priv->dev);
489 spin_unlock(&priv->tx_lock);
493 /* NAPI polling function
495 static int tse_poll(struct napi_struct *napi, int budget)
497 struct altera_tse_private *priv =
498 container_of(napi, struct altera_tse_private, napi);
500 unsigned long int flags;
502 tse_tx_complete(priv);
504 rxcomplete = tse_rx(priv, budget);
506 if (rxcomplete < budget) {
508 napi_gro_flush(napi, false);
509 __napi_complete(napi);
511 netdev_dbg(priv->dev,
512 "NAPI Complete, did %d packets with budget %d\n",
515 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
516 priv->dmaops->enable_rxirq(priv);
517 priv->dmaops->enable_txirq(priv);
518 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
523 /* DMA TX & RX FIFO interrupt routing
525 static irqreturn_t altera_isr(int irq, void *dev_id)
527 struct net_device *dev = dev_id;
528 struct altera_tse_private *priv;
530 if (unlikely(!dev)) {
531 pr_err("%s: invalid dev pointer\n", __func__);
534 priv = netdev_priv(dev);
536 spin_lock(&priv->rxdma_irq_lock);
538 priv->dmaops->clear_rxirq(priv);
539 priv->dmaops->clear_txirq(priv);
540 spin_unlock(&priv->rxdma_irq_lock);
542 if (likely(napi_schedule_prep(&priv->napi))) {
543 spin_lock(&priv->rxdma_irq_lock);
544 priv->dmaops->disable_rxirq(priv);
545 priv->dmaops->disable_txirq(priv);
546 spin_unlock(&priv->rxdma_irq_lock);
547 __napi_schedule(&priv->napi);
554 /* Transmit a packet (called by the kernel). Dispatches
555 * either the SGDMA method for transmitting or the
556 * MSGDMA method, assumes no scatter/gather support,
557 * implying an assumption that there's only one
558 * physically contiguous fragment starting at
559 * skb->data, for length of skb_headlen(skb).
561 static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
563 struct altera_tse_private *priv = netdev_priv(dev);
564 unsigned int txsize = priv->tx_ring_size;
566 struct tse_buffer *buffer = NULL;
567 int nfrags = skb_shinfo(skb)->nr_frags;
568 unsigned int nopaged_len = skb_headlen(skb);
569 enum netdev_tx ret = NETDEV_TX_OK;
572 spin_lock_bh(&priv->tx_lock);
574 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
575 if (!netif_queue_stopped(dev)) {
576 netif_stop_queue(dev);
577 /* This is a hard error, log it. */
578 netdev_err(priv->dev,
579 "%s: Tx list full when queue awake\n",
582 ret = NETDEV_TX_BUSY;
586 /* Map the first skb fragment */
587 entry = priv->tx_prod % txsize;
588 buffer = &priv->tx_ring[entry];
590 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
592 if (dma_mapping_error(priv->device, dma_addr)) {
593 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
599 buffer->dma_addr = dma_addr;
600 buffer->len = nopaged_len;
602 /* Push data out of the cache hierarchy into main memory */
603 dma_sync_single_for_device(priv->device, buffer->dma_addr,
604 buffer->len, DMA_TO_DEVICE);
606 priv->dmaops->tx_buffer(priv, buffer);
608 skb_tx_timestamp(skb);
611 dev->stats.tx_bytes += skb->len;
613 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
614 if (netif_msg_hw(priv))
615 netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
617 netif_stop_queue(dev);
621 spin_unlock_bh(&priv->tx_lock);
626 /* Called every time the controller might need to be made
627 * aware of new link state. The PHY code conveys this
628 * information through variables in the phydev structure, and this
629 * function converts those variables into the appropriate
630 * register values, and can bring down the device if needed.
632 static void altera_tse_adjust_link(struct net_device *dev)
634 struct altera_tse_private *priv = netdev_priv(dev);
635 struct phy_device *phydev = priv->phydev;
638 /* only change config if there is a link */
639 spin_lock(&priv->mac_cfg_lock);
641 /* Read old config */
642 u32 cfg_reg = ioread32(&priv->mac_dev->command_config);
645 if (phydev->duplex != priv->oldduplex) {
647 if (!(phydev->duplex))
648 cfg_reg |= MAC_CMDCFG_HD_ENA;
650 cfg_reg &= ~MAC_CMDCFG_HD_ENA;
652 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n",
653 dev->name, phydev->duplex);
655 priv->oldduplex = phydev->duplex;
659 if (phydev->speed != priv->oldspeed) {
661 switch (phydev->speed) {
663 cfg_reg |= MAC_CMDCFG_ETH_SPEED;
664 cfg_reg &= ~MAC_CMDCFG_ENA_10;
667 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
668 cfg_reg &= ~MAC_CMDCFG_ENA_10;
671 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
672 cfg_reg |= MAC_CMDCFG_ENA_10;
675 if (netif_msg_link(priv))
676 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n",
680 priv->oldspeed = phydev->speed;
682 iowrite32(cfg_reg, &priv->mac_dev->command_config);
684 if (!priv->oldlink) {
688 } else if (priv->oldlink) {
692 priv->oldduplex = -1;
695 if (new_state && netif_msg_link(priv))
696 phy_print_status(phydev);
698 spin_unlock(&priv->mac_cfg_lock);
700 static struct phy_device *connect_local_phy(struct net_device *dev)
702 struct altera_tse_private *priv = netdev_priv(dev);
703 struct phy_device *phydev = NULL;
704 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
706 if (priv->phy_addr != POLL_PHY) {
707 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
708 priv->mdio->id, priv->phy_addr);
710 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt);
712 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link,
715 netdev_err(dev, "Could not attach to PHY\n");
719 phydev = phy_find_first(priv->mdio);
720 if (phydev == NULL) {
721 netdev_err(dev, "No PHY found\n");
725 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link,
728 netdev_err(dev, "Could not attach to PHY\n");
735 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev)
737 struct altera_tse_private *priv = netdev_priv(dev);
738 struct device_node *np = priv->device->of_node;
741 priv->phy_iface = of_get_phy_mode(np);
743 /* Avoid get phy addr and create mdio if no phy is present */
744 if (!priv->phy_iface)
747 /* try to get PHY address from device tree, use PHY autodetection if
748 * no valid address is given
751 if (of_property_read_u32(priv->device->of_node, "phy-addr",
753 priv->phy_addr = POLL_PHY;
756 if (!((priv->phy_addr == POLL_PHY) ||
757 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
758 netdev_err(dev, "invalid phy-addr specified %d\n",
763 /* Create/attach to MDIO bus */
764 ret = altera_tse_mdio_create(dev,
765 atomic_add_return(1, &instance_count));
773 /* Initialize driver's PHY state, and attach to the PHY
775 static int init_phy(struct net_device *dev)
777 struct altera_tse_private *priv = netdev_priv(dev);
778 struct phy_device *phydev;
779 struct device_node *phynode;
781 /* Avoid init phy in case of no phy present */
782 if (!priv->phy_iface)
787 priv->oldduplex = -1;
789 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0);
792 netdev_dbg(dev, "no phy-handle found\n");
795 "No phy-handle nor local mdio specified\n");
798 phydev = connect_local_phy(dev);
800 netdev_dbg(dev, "phy-handle found\n");
801 phydev = of_phy_connect(dev, phynode,
802 &altera_tse_adjust_link, 0, priv->phy_iface);
806 netdev_err(dev, "Could not find the PHY\n");
810 /* Stop Advertising 1000BASE Capability if interface is not GMII
811 * Note: Checkpatch throws CHECKs for the camel case defines below,
814 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) ||
815 (priv->phy_iface == PHY_INTERFACE_MODE_RMII))
816 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
817 SUPPORTED_1000baseT_Full);
819 /* Broken HW is sometimes missing the pull-up resistor on the
820 * MDIO line, which results in reads to non-existent devices returning
821 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
823 * Note: phydev->phy_id is the result of reading the UID PHY registers.
825 if (phydev->phy_id == 0) {
826 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id);
827 phy_disconnect(phydev);
831 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n",
832 phydev->addr, phydev->phy_id, phydev->link);
834 priv->phydev = phydev;
838 static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
843 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
844 lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
846 /* Set primary MAC address */
847 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
848 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
851 /* MAC software reset.
852 * When reset is triggered, the MAC function completes the current
853 * transmission or reception, and subsequently disables the transmit and
854 * receive logic, flushes the receive FIFO buffer, and resets the statistics
857 static int reset_mac(struct altera_tse_private *priv)
862 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
863 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
864 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
865 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
868 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
869 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
870 MAC_CMDCFG_SW_RESET))
875 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
876 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
877 dat &= ~MAC_CMDCFG_SW_RESET;
878 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
884 /* Initialize MAC core registers
886 static int init_mac(struct altera_tse_private *priv)
888 unsigned int cmd = 0;
892 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
893 priv->mac_dev, tse_csroffs(rx_section_empty));
895 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
896 tse_csroffs(rx_section_full));
898 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
899 tse_csroffs(rx_almost_empty));
901 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
902 tse_csroffs(rx_almost_full));
905 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
906 priv->mac_dev, tse_csroffs(tx_section_empty));
908 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
909 tse_csroffs(tx_section_full));
911 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
912 tse_csroffs(tx_almost_empty));
914 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
915 tse_csroffs(tx_almost_full));
917 /* MAC Address Configuration */
918 tse_update_mac_addr(priv, priv->dev->dev_addr);
920 /* MAC Function Configuration */
921 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
922 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
924 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
925 tse_csroffs(tx_ipg_length));
927 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
930 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
931 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
933 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
934 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
935 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
937 /* Set the MAC options */
938 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
939 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
940 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
941 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
944 cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
945 cmd &= ~MAC_CMDCFG_TX_ENA;
946 cmd &= ~MAC_CMDCFG_RX_ENA;
948 /* Default speed and duplex setting, full/100 */
949 cmd &= ~MAC_CMDCFG_HD_ENA;
950 cmd &= ~MAC_CMDCFG_ETH_SPEED;
951 cmd &= ~MAC_CMDCFG_ENA_10;
953 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
955 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
956 tse_csroffs(pause_quanta));
958 if (netif_msg_hw(priv))
959 dev_dbg(priv->device,
960 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
965 /* Start/stop MAC transmission logic
967 static void tse_set_mac(struct altera_tse_private *priv, bool enable)
969 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
972 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
974 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
976 csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
981 static int tse_change_mtu(struct net_device *dev, int new_mtu)
983 struct altera_tse_private *priv = netdev_priv(dev);
984 unsigned int max_mtu = priv->max_mtu;
985 unsigned int min_mtu = ETH_ZLEN + ETH_FCS_LEN;
987 if (netif_running(dev)) {
988 netdev_err(dev, "must be stopped to change its MTU\n");
992 if ((new_mtu < min_mtu) || (new_mtu > max_mtu)) {
993 netdev_err(dev, "invalid MTU, max MTU is: %u\n", max_mtu);
998 netdev_update_features(dev);
1003 static void altera_tse_set_mcfilter(struct net_device *dev)
1005 struct altera_tse_private *priv = netdev_priv(dev);
1007 struct netdev_hw_addr *ha;
1009 /* clear the hash filter */
1010 for (i = 0; i < 64; i++)
1011 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1013 netdev_for_each_mc_addr(ha, dev) {
1014 unsigned int hash = 0;
1017 for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
1018 unsigned char xor_bit = 0;
1019 unsigned char octet = ha->addr[mac_octet];
1020 unsigned int bitshift;
1022 for (bitshift = 0; bitshift < 8; bitshift++)
1023 xor_bit ^= ((octet >> bitshift) & 0x01);
1025 hash = (hash << 1) | xor_bit;
1027 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
1032 static void altera_tse_set_mcfilterall(struct net_device *dev)
1034 struct altera_tse_private *priv = netdev_priv(dev);
1037 /* set the hash filter */
1038 for (i = 0; i < 64; i++)
1039 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1042 /* Set or clear the multicast filter for this adaptor
1044 static void tse_set_rx_mode_hashfilter(struct net_device *dev)
1046 struct altera_tse_private *priv = netdev_priv(dev);
1048 spin_lock(&priv->mac_cfg_lock);
1050 if (dev->flags & IFF_PROMISC)
1051 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1052 MAC_CMDCFG_PROMIS_EN);
1054 if (dev->flags & IFF_ALLMULTI)
1055 altera_tse_set_mcfilterall(dev);
1057 altera_tse_set_mcfilter(dev);
1059 spin_unlock(&priv->mac_cfg_lock);
1062 /* Set or clear the multicast filter for this adaptor
1064 static void tse_set_rx_mode(struct net_device *dev)
1066 struct altera_tse_private *priv = netdev_priv(dev);
1068 spin_lock(&priv->mac_cfg_lock);
1070 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
1071 !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
1072 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1073 MAC_CMDCFG_PROMIS_EN);
1075 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
1076 MAC_CMDCFG_PROMIS_EN);
1078 spin_unlock(&priv->mac_cfg_lock);
1081 /* Open and initialize the interface
1083 static int tse_open(struct net_device *dev)
1085 struct altera_tse_private *priv = netdev_priv(dev);
1088 unsigned long int flags;
1090 /* Reset and configure TSE MAC and probe associated PHY */
1091 ret = priv->dmaops->init_dma(priv);
1093 netdev_err(dev, "Cannot initialize DMA\n");
1097 if (netif_msg_ifup(priv))
1098 netdev_warn(dev, "device MAC address %pM\n",
1101 if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
1102 netdev_warn(dev, "TSE revision %x\n", priv->revision);
1104 spin_lock(&priv->mac_cfg_lock);
1105 ret = reset_mac(priv);
1106 /* Note that reset_mac will fail if the clocks are gated by the PHY
1107 * due to the PHY being put into isolation or power down mode.
1108 * This is not an error if reset fails due to no clock.
1111 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1113 ret = init_mac(priv);
1114 spin_unlock(&priv->mac_cfg_lock);
1116 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
1117 goto alloc_skbuf_error;
1120 priv->dmaops->reset_dma(priv);
1122 /* Create and initialize the TX/RX descriptors chains. */
1123 priv->rx_ring_size = dma_rx_num;
1124 priv->tx_ring_size = dma_tx_num;
1125 ret = alloc_init_skbufs(priv);
1127 netdev_err(dev, "DMA descriptors initialization failed\n");
1128 goto alloc_skbuf_error;
1132 /* Register RX interrupt */
1133 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
1136 netdev_err(dev, "Unable to register RX interrupt %d\n",
1141 /* Register TX interrupt */
1142 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
1145 netdev_err(dev, "Unable to register TX interrupt %d\n",
1147 goto tx_request_irq_error;
1150 /* Enable DMA interrupts */
1151 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1152 priv->dmaops->enable_rxirq(priv);
1153 priv->dmaops->enable_txirq(priv);
1155 /* Setup RX descriptor chain */
1156 for (i = 0; i < priv->rx_ring_size; i++)
1157 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
1159 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1162 phy_start(priv->phydev);
1164 napi_enable(&priv->napi);
1165 netif_start_queue(dev);
1167 priv->dmaops->start_rxdma(priv);
1169 /* Start MAC Rx/Tx */
1170 spin_lock(&priv->mac_cfg_lock);
1171 tse_set_mac(priv, true);
1172 spin_unlock(&priv->mac_cfg_lock);
1176 tx_request_irq_error:
1177 free_irq(priv->rx_irq, dev);
1185 /* Stop TSE MAC interface and put the device in an inactive state
1187 static int tse_shutdown(struct net_device *dev)
1189 struct altera_tse_private *priv = netdev_priv(dev);
1191 unsigned long int flags;
1195 phy_stop(priv->phydev);
1197 netif_stop_queue(dev);
1198 napi_disable(&priv->napi);
1200 /* Disable DMA interrupts */
1201 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1202 priv->dmaops->disable_rxirq(priv);
1203 priv->dmaops->disable_txirq(priv);
1204 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1206 /* Free the IRQ lines */
1207 free_irq(priv->rx_irq, dev);
1208 free_irq(priv->tx_irq, dev);
1210 /* disable and reset the MAC, empties fifo */
1211 spin_lock(&priv->mac_cfg_lock);
1212 spin_lock(&priv->tx_lock);
1214 ret = reset_mac(priv);
1215 /* Note that reset_mac will fail if the clocks are gated by the PHY
1216 * due to the PHY being put into isolation or power down mode.
1217 * This is not an error if reset fails due to no clock.
1220 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1221 priv->dmaops->reset_dma(priv);
1224 spin_unlock(&priv->tx_lock);
1225 spin_unlock(&priv->mac_cfg_lock);
1227 priv->dmaops->uninit_dma(priv);
1232 static struct net_device_ops altera_tse_netdev_ops = {
1233 .ndo_open = tse_open,
1234 .ndo_stop = tse_shutdown,
1235 .ndo_start_xmit = tse_start_xmit,
1236 .ndo_set_mac_address = eth_mac_addr,
1237 .ndo_set_rx_mode = tse_set_rx_mode,
1238 .ndo_change_mtu = tse_change_mtu,
1239 .ndo_validate_addr = eth_validate_addr,
1242 static int request_and_map(struct platform_device *pdev, const char *name,
1243 struct resource **res, void __iomem **ptr)
1245 struct resource *region;
1246 struct device *device = &pdev->dev;
1248 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1250 dev_err(device, "resource %s not defined\n", name);
1254 region = devm_request_mem_region(device, (*res)->start,
1255 resource_size(*res), dev_name(device));
1256 if (region == NULL) {
1257 dev_err(device, "unable to request %s\n", name);
1261 *ptr = devm_ioremap_nocache(device, region->start,
1262 resource_size(region));
1264 dev_err(device, "ioremap_nocache of %s failed!", name);
1271 /* Probe Altera TSE MAC device
1273 static int altera_tse_probe(struct platform_device *pdev)
1275 struct net_device *ndev;
1277 struct resource *control_port;
1278 struct resource *dma_res;
1279 struct altera_tse_private *priv;
1280 const unsigned char *macaddr;
1281 void __iomem *descmap;
1282 const struct of_device_id *of_id = NULL;
1284 ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1286 dev_err(&pdev->dev, "Could not allocate network device\n");
1290 SET_NETDEV_DEV(ndev, &pdev->dev);
1292 priv = netdev_priv(ndev);
1293 priv->device = &pdev->dev;
1295 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1297 of_id = of_match_device(altera_tse_ids, &pdev->dev);
1300 priv->dmaops = (struct altera_dmaops *)of_id->data;
1304 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1305 /* Get the mapped address to the SGDMA descriptor memory */
1306 ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1308 goto err_free_netdev;
1310 /* Start of that memory is for transmit descriptors */
1311 priv->tx_dma_desc = descmap;
1313 /* First half is for tx descriptors, other half for tx */
1314 priv->txdescmem = resource_size(dma_res)/2;
1316 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1318 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1320 priv->rxdescmem = resource_size(dma_res)/2;
1321 priv->rxdescmem_busaddr = dma_res->start;
1322 priv->rxdescmem_busaddr += priv->txdescmem;
1324 if (upper_32_bits(priv->rxdescmem_busaddr)) {
1325 dev_dbg(priv->device,
1326 "SGDMA bus addresses greater than 32-bits\n");
1327 goto err_free_netdev;
1329 if (upper_32_bits(priv->txdescmem_busaddr)) {
1330 dev_dbg(priv->device,
1331 "SGDMA bus addresses greater than 32-bits\n");
1332 goto err_free_netdev;
1334 } else if (priv->dmaops &&
1335 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1336 ret = request_and_map(pdev, "rx_resp", &dma_res,
1337 &priv->rx_dma_resp);
1339 goto err_free_netdev;
1341 ret = request_and_map(pdev, "tx_desc", &dma_res,
1342 &priv->tx_dma_desc);
1344 goto err_free_netdev;
1346 priv->txdescmem = resource_size(dma_res);
1347 priv->txdescmem_busaddr = dma_res->start;
1349 ret = request_and_map(pdev, "rx_desc", &dma_res,
1350 &priv->rx_dma_desc);
1352 goto err_free_netdev;
1354 priv->rxdescmem = resource_size(dma_res);
1355 priv->rxdescmem_busaddr = dma_res->start;
1358 goto err_free_netdev;
1361 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask)))
1362 dma_set_coherent_mask(priv->device,
1363 DMA_BIT_MASK(priv->dmaops->dmamask));
1364 else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32)))
1365 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1367 goto err_free_netdev;
1369 /* MAC address space */
1370 ret = request_and_map(pdev, "control_port", &control_port,
1371 (void __iomem **)&priv->mac_dev);
1373 goto err_free_netdev;
1375 /* xSGDMA Rx Dispatcher address space */
1376 ret = request_and_map(pdev, "rx_csr", &dma_res,
1379 goto err_free_netdev;
1382 /* xSGDMA Tx Dispatcher address space */
1383 ret = request_and_map(pdev, "tx_csr", &dma_res,
1386 goto err_free_netdev;
1390 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1391 if (priv->rx_irq == -ENXIO) {
1392 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1394 goto err_free_netdev;
1398 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1399 if (priv->tx_irq == -ENXIO) {
1400 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1402 goto err_free_netdev;
1405 /* get FIFO depths from device tree */
1406 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1407 &priv->rx_fifo_depth)) {
1408 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1410 goto err_free_netdev;
1413 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1414 &priv->tx_fifo_depth)) {
1415 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1417 goto err_free_netdev;
1420 /* get hash filter settings for this instance */
1422 of_property_read_bool(pdev->dev.of_node,
1423 "altr,has-hash-multicast-filter");
1425 /* Set hash filter to not set for now until the
1426 * multicast filter receive issue is debugged
1428 priv->hash_filter = 0;
1430 /* get supplemental address settings for this instance */
1431 priv->added_unicast =
1432 of_property_read_bool(pdev->dev.of_node,
1433 "altr,has-supplementary-unicast");
1435 /* Max MTU is 1500, ETH_DATA_LEN */
1436 priv->max_mtu = ETH_DATA_LEN;
1438 /* Get the max mtu from the device tree. Note that the
1439 * "max-frame-size" parameter is actually max mtu. Definition
1440 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1442 of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1445 /* The DMA buffer size already accounts for an alignment bias
1446 * to avoid unaligned access exceptions for the NIOS processor,
1448 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1450 /* get default MAC address from device tree */
1451 macaddr = of_get_mac_address(pdev->dev.of_node);
1453 ether_addr_copy(ndev->dev_addr, macaddr);
1455 eth_hw_addr_random(ndev);
1457 /* get phy addr and create mdio */
1458 ret = altera_tse_phy_get_addr_mdio_create(ndev);
1461 goto err_free_netdev;
1463 /* initialize netdev */
1464 ndev->mem_start = control_port->start;
1465 ndev->mem_end = control_port->end;
1466 ndev->netdev_ops = &altera_tse_netdev_ops;
1467 altera_tse_set_ethtool_ops(ndev);
1469 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1471 if (priv->hash_filter)
1472 altera_tse_netdev_ops.ndo_set_rx_mode =
1473 tse_set_rx_mode_hashfilter;
1475 /* Scatter/gather IO is not supported,
1476 * so it is turned off
1478 ndev->hw_features &= ~NETIF_F_SG;
1479 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1481 /* VLAN offloading of tagging, stripping and filtering is not
1482 * supported by hardware, but driver will accommodate the
1483 * extra 4-byte VLAN tag for processing by upper layers
1485 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1487 /* setup NAPI interface */
1488 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT);
1490 spin_lock_init(&priv->mac_cfg_lock);
1491 spin_lock_init(&priv->tx_lock);
1492 spin_lock_init(&priv->rxdma_irq_lock);
1494 ret = register_netdev(ndev);
1496 dev_err(&pdev->dev, "failed to register TSE net device\n");
1497 goto err_register_netdev;
1500 platform_set_drvdata(pdev, ndev);
1502 priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1504 if (netif_msg_probe(priv))
1505 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1506 (priv->revision >> 8) & 0xff,
1507 priv->revision & 0xff,
1508 (unsigned long) control_port->start, priv->rx_irq,
1511 ret = init_phy(ndev);
1513 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret);
1519 unregister_netdev(ndev);
1520 err_register_netdev:
1521 netif_napi_del(&priv->napi);
1522 altera_tse_mdio_destroy(ndev);
1528 /* Remove Altera TSE MAC device
1530 static int altera_tse_remove(struct platform_device *pdev)
1532 struct net_device *ndev = platform_get_drvdata(pdev);
1533 struct altera_tse_private *priv = netdev_priv(ndev);
1536 phy_disconnect(priv->phydev);
1538 platform_set_drvdata(pdev, NULL);
1539 altera_tse_mdio_destroy(ndev);
1540 unregister_netdev(ndev);
1546 static const struct altera_dmaops altera_dtype_sgdma = {
1547 .altera_dtype = ALTERA_DTYPE_SGDMA,
1549 .reset_dma = sgdma_reset,
1550 .enable_txirq = sgdma_enable_txirq,
1551 .enable_rxirq = sgdma_enable_rxirq,
1552 .disable_txirq = sgdma_disable_txirq,
1553 .disable_rxirq = sgdma_disable_rxirq,
1554 .clear_txirq = sgdma_clear_txirq,
1555 .clear_rxirq = sgdma_clear_rxirq,
1556 .tx_buffer = sgdma_tx_buffer,
1557 .tx_completions = sgdma_tx_completions,
1558 .add_rx_desc = sgdma_add_rx_desc,
1559 .get_rx_status = sgdma_rx_status,
1560 .init_dma = sgdma_initialize,
1561 .uninit_dma = sgdma_uninitialize,
1562 .start_rxdma = sgdma_start_rxdma,
1565 static const struct altera_dmaops altera_dtype_msgdma = {
1566 .altera_dtype = ALTERA_DTYPE_MSGDMA,
1568 .reset_dma = msgdma_reset,
1569 .enable_txirq = msgdma_enable_txirq,
1570 .enable_rxirq = msgdma_enable_rxirq,
1571 .disable_txirq = msgdma_disable_txirq,
1572 .disable_rxirq = msgdma_disable_rxirq,
1573 .clear_txirq = msgdma_clear_txirq,
1574 .clear_rxirq = msgdma_clear_rxirq,
1575 .tx_buffer = msgdma_tx_buffer,
1576 .tx_completions = msgdma_tx_completions,
1577 .add_rx_desc = msgdma_add_rx_desc,
1578 .get_rx_status = msgdma_rx_status,
1579 .init_dma = msgdma_initialize,
1580 .uninit_dma = msgdma_uninitialize,
1581 .start_rxdma = msgdma_start_rxdma,
1584 static const struct of_device_id altera_tse_ids[] = {
1585 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1586 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1587 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1590 MODULE_DEVICE_TABLE(of, altera_tse_ids);
1592 static struct platform_driver altera_tse_driver = {
1593 .probe = altera_tse_probe,
1594 .remove = altera_tse_remove,
1598 .name = ALTERA_TSE_RESOURCE_NAME,
1599 .of_match_table = altera_tse_ids,
1603 module_platform_driver(altera_tse_driver);
1605 MODULE_AUTHOR("Altera Corporation");
1606 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1607 MODULE_LICENSE("GPL v2");