drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * aQuantia Corporation Network Driver
   4  * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved
   5  */
   6
   7 /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
   8  * Atlantic hardware abstraction layer.
   9  */
  10
  11 #include "../aq_hw.h"
  12 #include "../aq_hw_utils.h"
  13 #include "../aq_pci_func.h"
  14 #include "../aq_ring.h"
  15 #include "../aq_vec.h"
  16 #include "../aq_nic.h"
  17 #include "hw_atl_utils.h"
  18 #include "hw_atl_llh.h"
  19
  20 #define HW_ATL_FW2X_MPI_LED_ADDR         0x31c
  21 #define HW_ATL_FW2X_MPI_RPC_ADDR         0x334
  22
  23 #define HW_ATL_FW2X_MPI_MBOX_ADDR        0x360
  24 #define HW_ATL_FW2X_MPI_EFUSE_ADDR       0x364
  25 #define HW_ATL_FW2X_MPI_CONTROL_ADDR     0x368
  26 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR    0x36C
  27 #define HW_ATL_FW2X_MPI_STATE_ADDR       0x370
  28 #define HW_ATL_FW2X_MPI_STATE2_ADDR      0x374
  29
  30 #define HW_ATL_FW3X_EXT_CONTROL_ADDR     0x378
  31 #define HW_ATL_FW3X_EXT_STATE_ADDR       0x37c
  32
  33 #define HW_ATL_FW2X_CAP_PAUSE            BIT(CAPS_HI_PAUSE)
  34 #define HW_ATL_FW2X_CAP_ASYM_PAUSE       BIT(CAPS_HI_ASYMMETRIC_PAUSE)
  35 #define HW_ATL_FW2X_CAP_SLEEP_PROXY      BIT(CAPS_HI_SLEEP_PROXY)
  36 #define HW_ATL_FW2X_CAP_WOL              BIT(CAPS_HI_WOL)
  37
  38 #define HW_ATL_FW2X_CTRL_WAKE_ON_LINK     BIT(CTRL_WAKE_ON_LINK)
  39 #define HW_ATL_FW2X_CTRL_SLEEP_PROXY      BIT(CTRL_SLEEP_PROXY)
  40 #define HW_ATL_FW2X_CTRL_WOL              BIT(CTRL_WOL)
  41 #define HW_ATL_FW2X_CTRL_LINK_DROP        BIT(CTRL_LINK_DROP)
  42 #define HW_ATL_FW2X_CTRL_PAUSE            BIT(CTRL_PAUSE)
  43 #define HW_ATL_FW2X_CTRL_TEMPERATURE      BIT(CTRL_TEMPERATURE)
  44 #define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE)
  45 #define HW_ATL_FW2X_CTRL_INT_LOOPBACK     BIT(CTRL_INT_LOOPBACK)
  46 #define HW_ATL_FW2X_CTRL_EXT_LOOPBACK     BIT(CTRL_EXT_LOOPBACK)
  47 #define HW_ATL_FW2X_CTRL_DOWNSHIFT        BIT(CTRL_DOWNSHIFT)
  48 #define HW_ATL_FW2X_CTRL_FORCE_RECONNECT  BIT(CTRL_FORCE_RECONNECT)
  49
  50 #define HW_ATL_FW2X_CAP_EEE_1G_MASK      BIT(CAPS_HI_1000BASET_FD_EEE)
  51 #define HW_ATL_FW2X_CAP_EEE_2G5_MASK     BIT(CAPS_HI_2P5GBASET_FD_EEE)
  52 #define HW_ATL_FW2X_CAP_EEE_5G_MASK      BIT(CAPS_HI_5GBASET_FD_EEE)
  53 #define HW_ATL_FW2X_CAP_EEE_10G_MASK     BIT(CAPS_HI_10GBASET_FD_EEE)
  54
  55 #define HAL_ATLANTIC_WOL_FILTERS_COUNT   8
  56 #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL  0x0E
  57
  58 #define HW_ATL_FW_VER_LED                0x03010026U
  59 #define HW_ATL_FW_VER_MEDIA_CONTROL      0x0301005aU
  60
  61 struct __packed fw2x_msg_wol_pattern {
  62         u8 mask[16];
  63         u32 crc;
  64 };
  65
  66 struct __packed fw2x_msg_wol {
  67         u32 msg_id;
  68         u8 hw_addr[ETH_ALEN];
  69         u8 magic_packet_enabled;
  70         u8 filter_count;
  71         struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
  72         u8 link_up_enabled;
  73         u8 link_down_enabled;
  74         u16 reserved;
  75         u32 link_up_timeout;
  76         u32 link_down_timeout;
  77 };
  78
  79 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
  80 static int aq_fw2x_set_state(struct aq_hw_s *self,
  81                              enum hal_atl_utils_fw_state_e state);
  82
  83 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self);
  84 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self);
  85 static int aq_fw2x_settings_get(struct aq_hw_s *self, u32 *addr);
  86 static u32 aq_fw2x_state2_get(struct aq_hw_s *self);
  87
  88 static int aq_fw2x_init(struct aq_hw_s *self)
  89 {
  90         int err = 0;
  91
  92         /* check 10 times by 1ms */
  93         err = readx_poll_timeout_atomic(aq_fw2x_mbox_get,
  94                                         self, self->mbox_addr,
  95                                         self->mbox_addr != 0U,
  96                                         1000U, 10000U);
  97
  98         err = readx_poll_timeout_atomic(aq_fw2x_rpc_get,
  99                                         self, self->rpc_addr,
 100                                         self->rpc_addr != 0U,
 101                                         1000U, 100000U);
 102
 103         err = aq_fw2x_settings_get(self, &self->settings_addr);
 104
 105         return err;
 106 }
 107
 108 static int aq_fw2x_deinit(struct aq_hw_s *self)
 109 {
 110         int err = aq_fw2x_set_link_speed(self, 0);
 111
 112         if (!err)
 113                 err = aq_fw2x_set_state(self, MPI_DEINIT);
 114
 115         return err;
 116 }
 117
 118 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
 119 {
 120         enum hw_atl_fw2x_rate rate = 0;
 121
 122         if (speed & AQ_NIC_RATE_10G)
 123                 rate |= FW2X_RATE_10G;
 124
 125         if (speed & AQ_NIC_RATE_5G)
 126                 rate |= FW2X_RATE_5G;
 127
 128         if (speed & AQ_NIC_RATE_5GSR)
 129                 rate |= FW2X_RATE_5G;
 130
 131         if (speed & AQ_NIC_RATE_2GS)
 132                 rate |= FW2X_RATE_2G5;
 133
 134         if (speed & AQ_NIC_RATE_1G)
 135                 rate |= FW2X_RATE_1G;
 136
 137         if (speed & AQ_NIC_RATE_100M)
 138                 rate |= FW2X_RATE_100M;
 139
 140         return rate;
 141 }
 142
 143 static u32 fw2x_to_eee_mask(u32 speed)
 144 {
 145         u32 rate = 0;
 146
 147         if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
 148                 rate |= AQ_NIC_RATE_EEE_10G;
 149         if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
 150                 rate |= AQ_NIC_RATE_EEE_5G;
 151         if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
 152                 rate |= AQ_NIC_RATE_EEE_2GS;
 153         if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
 154                 rate |= AQ_NIC_RATE_EEE_1G;
 155
 156         return rate;
 157 }
 158
 159 static u32 eee_mask_to_fw2x(u32 speed)
 160 {
 161         u32 rate = 0;
 162
 163         if (speed & AQ_NIC_RATE_EEE_10G)
 164                 rate |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
 165         if (speed & AQ_NIC_RATE_EEE_5G)
 166                 rate |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
 167         if (speed & AQ_NIC_RATE_EEE_2GS)
 168                 rate |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
 169         if (speed & AQ_NIC_RATE_EEE_1G)
 170                 rate |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
 171
 172         return rate;
 173 }
 174
 175 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
 176 {
 177         u32 val = link_speed_mask_2fw2x_ratemask(speed);
 178
 179         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
 180
 181         return 0;
 182 }
 183
 184 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
 185 {
 186         if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
 187                 *mpi_state |= BIT(CAPS_HI_PAUSE);
 188         else
 189                 *mpi_state &= ~BIT(CAPS_HI_PAUSE);
 190
 191         if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
 192                 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
 193         else
 194                 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
 195 }
 196
 197 static void aq_fw2x_upd_eee_rate_bits(struct aq_hw_s *self, u32 *mpi_opts,
 198                                       u32 eee_speeds)
 199 {
 200         *mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
 201                        HW_ATL_FW2X_CAP_EEE_2G5_MASK |
 202                        HW_ATL_FW2X_CAP_EEE_5G_MASK |
 203                        HW_ATL_FW2X_CAP_EEE_10G_MASK);
 204
 205         *mpi_opts |= eee_mask_to_fw2x(eee_speeds);
 206 }
 207
 208 static int aq_fw2x_set_state(struct aq_hw_s *self,
 209                              enum hal_atl_utils_fw_state_e state)
 210 {
 211         u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 212         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 213
 214         switch (state) {
 215         case MPI_INIT:
 216                 mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
 217                 aq_fw2x_upd_eee_rate_bits(self, &mpi_state, cfg->eee_speeds);
 218                 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
 219                 break;
 220         case MPI_DEINIT:
 221                 mpi_state |= BIT(CAPS_HI_LINK_DROP);
 222                 break;
 223         case MPI_RESET:
 224         case MPI_POWER:
 225                 /* No actions */
 226                 break;
 227         }
 228         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
 229         return 0;
 230 }
 231
 232 static int aq_fw2x_update_link_status(struct aq_hw_s *self)
 233 {
 234         u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
 235         u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
 236                                  FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
 237         struct aq_hw_link_status_s *link_status = &self->aq_link_status;
 238
 239         if (speed) {
 240                 if (speed & FW2X_RATE_10G)
 241                         link_status->mbps = 10000;
 242                 else if (speed & FW2X_RATE_5G)
 243                         link_status->mbps = 5000;
 244                 else if (speed & FW2X_RATE_2G5)
 245                         link_status->mbps = 2500;
 246                 else if (speed & FW2X_RATE_1G)
 247                         link_status->mbps = 1000;
 248                 else if (speed & FW2X_RATE_100M)
 249                         link_status->mbps = 100;
 250                 else
 251                         link_status->mbps = 10000;
 252         } else {
 253                 link_status->mbps = 0;
 254         }
 255
 256         return 0;
 257 }
 258
 259 static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
 260 {
 261         int err = 0;
 262         u32 h = 0U;
 263         u32 l = 0U;
 264         u32 mac_addr[2] = { 0 };
 265         u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
 266
 267         if (efuse_addr != 0) {
 268                 err = hw_atl_utils_fw_downld_dwords(self,
 269                                                     efuse_addr + (40U * 4U),
 270                                                     mac_addr,
 271                                                     ARRAY_SIZE(mac_addr));
 272                 if (err)
 273                         return err;
 274                 mac_addr[0] = __swab32(mac_addr[0]);
 275                 mac_addr[1] = __swab32(mac_addr[1]);
 276         }
 277
 278         ether_addr_copy(mac, (u8 *)mac_addr);
 279
 280         if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
 281                 unsigned int rnd = 0;
 282
 283                 get_random_bytes(&rnd, sizeof(unsigned int));
 284
 285                 l = 0xE3000000U | (0xFFFFU & rnd) | (0x00 << 16);
 286                 h = 0x8001300EU;
 287
 288                 mac[5] = (u8)(0xFFU & l);
 289                 l >>= 8;
 290                 mac[4] = (u8)(0xFFU & l);
 291                 l >>= 8;
 292                 mac[3] = (u8)(0xFFU & l);
 293                 l >>= 8;
 294                 mac[2] = (u8)(0xFFU & l);
 295                 mac[1] = (u8)(0xFFU & h);
 296                 h >>= 8;
 297                 mac[0] = (u8)(0xFFU & h);
 298         }
 299         return err;
 300 }
 301
 302 static int aq_fw2x_update_stats(struct aq_hw_s *self)
 303 {
 304         int err = 0;
 305         u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 306         u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
 307         u32 stats_val;
 308
 309         /* Toggle statistics bit for FW to update */
 310         mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
 311         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 312
 313         /* Wait FW to report back */
 314         err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
 315                                         self, stats_val,
 316                                         orig_stats_val != (stats_val &
 317                                         BIT(CAPS_HI_STATISTICS)),
 318                                         1U, 10000U);
 319         if (err)
 320                 return err;
 321
 322         return hw_atl_utils_update_stats(self);
 323 }
 324
 325 static int aq_fw2x_get_phy_temp(struct aq_hw_s *self, int *temp)
 326 {
 327         u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 328         u32 temp_val = mpi_opts & HW_ATL_FW2X_CTRL_TEMPERATURE;
 329         u32 phy_temp_offset;
 330         u32 temp_res;
 331         int err = 0;
 332         u32 val;
 333
 334         phy_temp_offset = self->mbox_addr +
 335                           offsetof(struct hw_atl_utils_mbox, info) +
 336                           offsetof(struct hw_aq_info, phy_temperature);
 337         /* Toggle statistics bit for FW to 0x36C.18 (CTRL_TEMPERATURE) */
 338         mpi_opts = mpi_opts ^ HW_ATL_FW2X_CTRL_TEMPERATURE;
 339         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 340         /* Wait FW to report back */
 341         err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
 342                                         temp_val !=
 343                                         (val & HW_ATL_FW2X_CTRL_TEMPERATURE),
 344                                         1U, 10000U);
 345         err = hw_atl_utils_fw_downld_dwords(self, phy_temp_offset,
 346                                             &temp_res, 1);
 347
 348         if (err)
 349                 return err;
 350
 351         /* Convert PHY temperature from 1/256 degree Celsius
 352          * to 1/1000 degree Celsius.
 353          */
 354         *temp = (temp_res & 0xFFFF) * 1000 / 256;
 355
 356         return 0;
 357 }
 358
 359 static int aq_fw2x_set_wol(struct aq_hw_s *self, u8 *mac)
 360 {
 361         struct hw_atl_utils_fw_rpc *rpc = NULL;
 362         struct offload_info *info = NULL;
 363         u32 wol_bits = 0;
 364         u32 rpc_size;
 365         int err = 0;
 366         u32 val;
 367
 368         if (self->aq_nic_cfg->wol & WAKE_PHY) {
 369                 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR,
 370                                 HW_ATL_FW2X_CTRL_LINK_DROP);
 371                 readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
 372                                           (val &
 373                                            HW_ATL_FW2X_CTRL_LINK_DROP) != 0,
 374                                           1000, 100000);
 375                 wol_bits |= HW_ATL_FW2X_CTRL_WAKE_ON_LINK;
 376         }
 377
 378         if (self->aq_nic_cfg->wol & WAKE_MAGIC) {
 379                 wol_bits |= HW_ATL_FW2X_CTRL_SLEEP_PROXY |
 380                             HW_ATL_FW2X_CTRL_WOL;
 381
 382                 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
 383                 if (err < 0)
 384                         goto err_exit;
 385
 386                 rpc_size = sizeof(*info) +
 387                            offsetof(struct hw_atl_utils_fw_rpc, fw2x_offloads);
 388                 memset(rpc, 0, rpc_size);
 389                 info = &rpc->fw2x_offloads;
 390                 memcpy(info->mac_addr, mac, ETH_ALEN);
 391                 info->len = sizeof(*info);
 392
 393                 err = hw_atl_utils_fw_rpc_call(self, rpc_size);
 394                 if (err < 0)
 395                         goto err_exit;
 396         }
 397
 398         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, wol_bits);
 399
 400 err_exit:
 401         return err;
 402 }
 403
 404 static int aq_fw2x_set_power(struct aq_hw_s *self, unsigned int power_state,
 405                              u8 *mac)
 406 {
 407         int err = 0;
 408
 409         if (self->aq_nic_cfg->wol)
 410                 err = aq_fw2x_set_wol(self, mac);
 411
 412         return err;
 413 }
 414
 415 static int aq_fw2x_send_fw_request(struct aq_hw_s *self,
 416                                    const struct hw_fw_request_iface *fw_req,
 417                                    size_t size)
 418 {
 419         u32 ctrl2, orig_ctrl2;
 420         u32 dword_cnt;
 421         int err = 0;
 422         u32 val;
 423
 424         /* Write data to drvIface Mailbox */
 425         dword_cnt = size / sizeof(u32);
 426         if (size % sizeof(u32))
 427                 dword_cnt++;
 428         err = hw_atl_write_fwcfg_dwords(self, (void *)fw_req, dword_cnt);
 429         if (err < 0)
 430                 goto err_exit;
 431
 432         /* Toggle statistics bit for FW to update */
 433         ctrl2 = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 434         orig_ctrl2 = ctrl2 & BIT(CAPS_HI_FW_REQUEST);
 435         ctrl2 = ctrl2 ^ BIT(CAPS_HI_FW_REQUEST);
 436         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, ctrl2);
 437
 438         /* Wait FW to report back */
 439         err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
 440                                         orig_ctrl2 != (val &
 441                                                        BIT(CAPS_HI_FW_REQUEST)),
 442                                         1U, 10000U);
 443
 444 err_exit:
 445         return err;
 446 }
 447
 448 static void aq_fw3x_enable_ptp(struct aq_hw_s *self, int enable)
 449 {
 450         u32 ptp_opts = aq_hw_read_reg(self, HW_ATL_FW3X_EXT_STATE_ADDR);
 451         u32 all_ptp_features = BIT(CAPS_EX_PHY_PTP_EN) |
 452                                                    BIT(CAPS_EX_PTP_GPIO_EN);
 453
 454         if (enable)
 455                 ptp_opts |= all_ptp_features;
 456         else
 457                 ptp_opts &= ~all_ptp_features;
 458
 459         aq_hw_write_reg(self, HW_ATL_FW3X_EXT_CONTROL_ADDR, ptp_opts);
 460 }
 461
 462 static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode)
 463 {
 464         if (self->fw_ver_actual < HW_ATL_FW_VER_LED)
 465                 return -EOPNOTSUPP;
 466
 467         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode);
 468
 469         return 0;
 470 }
 471
 472 static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
 473 {
 474         u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 475
 476         aq_fw2x_upd_eee_rate_bits(self, &mpi_opts, speed);
 477
 478         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 479
 480         return 0;
 481 }
 482
 483 static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
 484                                 u32 *supported_rates)
 485 {
 486         u32 mpi_state;
 487         u32 caps_hi;
 488         int err = 0;
 489         u32 addr = self->mbox_addr + offsetof(struct hw_atl_utils_mbox, info) +
 490                    offsetof(struct hw_aq_info, caps_hi);
 491
 492         err = hw_atl_utils_fw_downld_dwords(self, addr, &caps_hi,
 493                                             sizeof(caps_hi) / sizeof(u32));
 494
 495         if (err)
 496                 return err;
 497
 498         *supported_rates = fw2x_to_eee_mask(caps_hi);
 499
 500         mpi_state = aq_fw2x_state2_get(self);
 501         *rate = fw2x_to_eee_mask(mpi_state);
 502
 503         return err;
 504 }
 505
 506 static int aq_fw2x_renegotiate(struct aq_hw_s *self)
 507 {
 508         u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 509
 510         mpi_opts |= BIT(CTRL_FORCE_RECONNECT);
 511
 512         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 513
 514         return 0;
 515 }
 516
 517 static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
 518 {
 519         u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 520
 521         aq_fw2x_set_mpi_flow_control(self, &mpi_state);
 522
 523         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
 524
 525         return 0;
 526 }
 527
 528 static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode)
 529 {
 530         u32 mpi_state = aq_fw2x_state2_get(self);
 531
 532         if (mpi_state & HW_ATL_FW2X_CAP_PAUSE)
 533                 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)
 534                         *fcmode = AQ_NIC_FC_RX;
 535                 else
 536                         *fcmode = AQ_NIC_FC_RX | AQ_NIC_FC_TX;
 537         else
 538                 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)
 539                         *fcmode = AQ_NIC_FC_TX;
 540                 else
 541                         *fcmode = 0;
 542
 543         return 0;
 544 }
 545
 546 static int aq_fw2x_set_phyloopback(struct aq_hw_s *self, u32 mode, bool enable)
 547 {
 548         u32 mpi_opts;
 549
 550         switch (mode) {
 551         case AQ_HW_LOOPBACK_PHYINT_SYS:
 552                 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 553                 if (enable)
 554                         mpi_opts |= HW_ATL_FW2X_CTRL_INT_LOOPBACK;
 555                 else
 556                         mpi_opts &= ~HW_ATL_FW2X_CTRL_INT_LOOPBACK;
 557                 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 558                 break;
 559         case AQ_HW_LOOPBACK_PHYEXT_SYS:
 560                 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 561                 if (enable)
 562                         mpi_opts |= HW_ATL_FW2X_CTRL_EXT_LOOPBACK;
 563                 else
 564                         mpi_opts &= ~HW_ATL_FW2X_CTRL_EXT_LOOPBACK;
 565                 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 566                 break;
 567         default:
 568                 return -EINVAL;
 569         }
 570         return 0;
 571 }
 572
 573 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self)
 574 {
 575         return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);
 576 }
 577
 578 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self)
 579 {
 580         return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR);
 581 }
 582
 583 static int aq_fw2x_settings_get(struct aq_hw_s *self, u32 *addr)
 584 {
 585         int err = 0;
 586         u32 offset;
 587
 588         offset = self->mbox_addr + offsetof(struct hw_atl_utils_mbox,
 589                                             info.setting_address);
 590
 591         err = hw_atl_utils_fw_downld_dwords(self, offset, addr, 1);
 592
 593         return err;
 594 }
 595
 596 static u32 aq_fw2x_state2_get(struct aq_hw_s *self)
 597 {
 598         return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
 599 }
 600
 601 const struct aq_fw_ops aq_fw_2x_ops = {
 602         .init               = aq_fw2x_init,
 603         .deinit             = aq_fw2x_deinit,
 604         .reset              = NULL,
 605         .renegotiate        = aq_fw2x_renegotiate,
 606         .get_mac_permanent  = aq_fw2x_get_mac_permanent,
 607         .set_link_speed     = aq_fw2x_set_link_speed,
 608         .set_state          = aq_fw2x_set_state,
 609         .update_link_status = aq_fw2x_update_link_status,
 610         .update_stats       = aq_fw2x_update_stats,
 611         .get_phy_temp       = aq_fw2x_get_phy_temp,
 612         .set_power          = aq_fw2x_set_power,
 613         .set_eee_rate       = aq_fw2x_set_eee_rate,
 614         .get_eee_rate       = aq_fw2x_get_eee_rate,
 615         .set_flow_control   = aq_fw2x_set_flow_control,
 616         .get_flow_control   = aq_fw2x_get_flow_control,
 617         .send_fw_request    = aq_fw2x_send_fw_request,
 618         .enable_ptp         = aq_fw3x_enable_ptp,
 619         .led_control        = aq_fw2x_led_control,
 620         .set_phyloopback    = aq_fw2x_set_phyloopback,
 621 };