drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * aQuantia Corporation Network Driver
   4  * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved
   5  */
   6
   7 /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
   8  * Atlantic hardware abstraction layer.
   9  */
  10
  11 #include "../aq_hw.h"
  12 #include "../aq_hw_utils.h"
  13 #include "../aq_pci_func.h"
  14 #include "../aq_ring.h"
  15 #include "../aq_vec.h"
  16 #include "../aq_nic.h"
  17 #include "hw_atl_utils.h"
  18 #include "hw_atl_llh.h"
  19
  20 #define HW_ATL_FW2X_MPI_RPC_ADDR         0x334
  21
  22 #define HW_ATL_FW2X_MPI_MBOX_ADDR        0x360
  23 #define HW_ATL_FW2X_MPI_EFUSE_ADDR       0x364
  24 #define HW_ATL_FW2X_MPI_CONTROL_ADDR     0x368
  25 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR    0x36C
  26 #define HW_ATL_FW2X_MPI_STATE_ADDR       0x370
  27 #define HW_ATL_FW2X_MPI_STATE2_ADDR      0x374
  28
  29 #define HW_ATL_FW3X_EXT_CONTROL_ADDR     0x378
  30 #define HW_ATL_FW3X_EXT_STATE_ADDR       0x37c
  31
  32 #define HW_ATL_FW2X_CAP_PAUSE            BIT(CAPS_HI_PAUSE)
  33 #define HW_ATL_FW2X_CAP_ASYM_PAUSE       BIT(CAPS_HI_ASYMMETRIC_PAUSE)
  34 #define HW_ATL_FW2X_CAP_SLEEP_PROXY      BIT(CAPS_HI_SLEEP_PROXY)
  35 #define HW_ATL_FW2X_CAP_WOL              BIT(CAPS_HI_WOL)
  36
  37 #define HW_ATL_FW2X_CTRL_SLEEP_PROXY      BIT(CTRL_SLEEP_PROXY)
  38 #define HW_ATL_FW2X_CTRL_WOL              BIT(CTRL_WOL)
  39 #define HW_ATL_FW2X_CTRL_LINK_DROP        BIT(CTRL_LINK_DROP)
  40 #define HW_ATL_FW2X_CTRL_PAUSE            BIT(CTRL_PAUSE)
  41 #define HW_ATL_FW2X_CTRL_TEMPERATURE      BIT(CTRL_TEMPERATURE)
  42 #define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE)
  43 #define HW_ATL_FW2X_CTRL_FORCE_RECONNECT  BIT(CTRL_FORCE_RECONNECT)
  44
  45 #define HW_ATL_FW2X_CAP_EEE_1G_MASK      BIT(CAPS_HI_1000BASET_FD_EEE)
  46 #define HW_ATL_FW2X_CAP_EEE_2G5_MASK     BIT(CAPS_HI_2P5GBASET_FD_EEE)
  47 #define HW_ATL_FW2X_CAP_EEE_5G_MASK      BIT(CAPS_HI_5GBASET_FD_EEE)
  48 #define HW_ATL_FW2X_CAP_EEE_10G_MASK     BIT(CAPS_HI_10GBASET_FD_EEE)
  49
  50 #define HAL_ATLANTIC_WOL_FILTERS_COUNT   8
  51 #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL  0x0E
  52
  53 struct __packed fw2x_msg_wol_pattern {
  54         u8 mask[16];
  55         u32 crc;
  56 };
  57
  58 struct __packed fw2x_msg_wol {
  59         u32 msg_id;
  60         u8 hw_addr[ETH_ALEN];
  61         u8 magic_packet_enabled;
  62         u8 filter_count;
  63         struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
  64         u8 link_up_enabled;
  65         u8 link_down_enabled;
  66         u16 reserved;
  67         u32 link_up_timeout;
  68         u32 link_down_timeout;
  69 };
  70
  71 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
  72 static int aq_fw2x_set_state(struct aq_hw_s *self,
  73                              enum hal_atl_utils_fw_state_e state);
  74
  75 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self);
  76 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self);
  77 static u32 aq_fw2x_state2_get(struct aq_hw_s *self);
  78
  79 static int aq_fw2x_init(struct aq_hw_s *self)
  80 {
  81         int err = 0;
  82
  83         /* check 10 times by 1ms */
  84         err = readx_poll_timeout_atomic(aq_fw2x_mbox_get,
  85                                         self, self->mbox_addr,
  86                                         self->mbox_addr != 0U,
  87                                         1000U, 10000U);
  88
  89         err = readx_poll_timeout_atomic(aq_fw2x_rpc_get,
  90                                         self, self->rpc_addr,
  91                                         self->rpc_addr != 0U,
  92                                         1000U, 100000U);
  93
  94         return err;
  95 }
  96
  97 static int aq_fw2x_deinit(struct aq_hw_s *self)
  98 {
  99         int err = aq_fw2x_set_link_speed(self, 0);
 100
 101         if (!err)
 102                 err = aq_fw2x_set_state(self, MPI_DEINIT);
 103
 104         return err;
 105 }
 106
 107 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
 108 {
 109         enum hw_atl_fw2x_rate rate = 0;
 110
 111         if (speed & AQ_NIC_RATE_10G)
 112                 rate |= FW2X_RATE_10G;
 113
 114         if (speed & AQ_NIC_RATE_5G)
 115                 rate |= FW2X_RATE_5G;
 116
 117         if (speed & AQ_NIC_RATE_5GSR)
 118                 rate |= FW2X_RATE_5G;
 119
 120         if (speed & AQ_NIC_RATE_2GS)
 121                 rate |= FW2X_RATE_2G5;
 122
 123         if (speed & AQ_NIC_RATE_1G)
 124                 rate |= FW2X_RATE_1G;
 125
 126         if (speed & AQ_NIC_RATE_100M)
 127                 rate |= FW2X_RATE_100M;
 128
 129         return rate;
 130 }
 131
 132 static u32 fw2x_to_eee_mask(u32 speed)
 133 {
 134         u32 rate = 0;
 135
 136         if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
 137                 rate |= AQ_NIC_RATE_EEE_10G;
 138         if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
 139                 rate |= AQ_NIC_RATE_EEE_5G;
 140         if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
 141                 rate |= AQ_NIC_RATE_EEE_2GS;
 142         if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
 143                 rate |= AQ_NIC_RATE_EEE_1G;
 144
 145         return rate;
 146 }
 147
 148 static u32 eee_mask_to_fw2x(u32 speed)
 149 {
 150         u32 rate = 0;
 151
 152         if (speed & AQ_NIC_RATE_EEE_10G)
 153                 rate |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
 154         if (speed & AQ_NIC_RATE_EEE_5G)
 155                 rate |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
 156         if (speed & AQ_NIC_RATE_EEE_2GS)
 157                 rate |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
 158         if (speed & AQ_NIC_RATE_EEE_1G)
 159                 rate |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
 160
 161         return rate;
 162 }
 163
 164 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
 165 {
 166         u32 val = link_speed_mask_2fw2x_ratemask(speed);
 167
 168         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
 169
 170         return 0;
 171 }
 172
 173 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
 174 {
 175         if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
 176                 *mpi_state |= BIT(CAPS_HI_PAUSE);
 177         else
 178                 *mpi_state &= ~BIT(CAPS_HI_PAUSE);
 179
 180         if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
 181                 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
 182         else
 183                 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
 184 }
 185
 186 static void aq_fw2x_upd_eee_rate_bits(struct aq_hw_s *self, u32 *mpi_opts,
 187                                       u32 eee_speeds)
 188 {
 189         *mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
 190                        HW_ATL_FW2X_CAP_EEE_2G5_MASK |
 191                        HW_ATL_FW2X_CAP_EEE_5G_MASK |
 192                        HW_ATL_FW2X_CAP_EEE_10G_MASK);
 193
 194         *mpi_opts |= eee_mask_to_fw2x(eee_speeds);
 195 }
 196
 197 static int aq_fw2x_set_state(struct aq_hw_s *self,
 198                              enum hal_atl_utils_fw_state_e state)
 199 {
 200         u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 201         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 202
 203         switch (state) {
 204         case MPI_INIT:
 205                 mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
 206                 aq_fw2x_upd_eee_rate_bits(self, &mpi_state, cfg->eee_speeds);
 207                 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
 208                 break;
 209         case MPI_DEINIT:
 210                 mpi_state |= BIT(CAPS_HI_LINK_DROP);
 211                 break;
 212         case MPI_RESET:
 213         case MPI_POWER:
 214                 /* No actions */
 215                 break;
 216         }
 217         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
 218         return 0;
 219 }
 220
 221 static int aq_fw2x_update_link_status(struct aq_hw_s *self)
 222 {
 223         u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
 224         u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
 225                                  FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
 226         struct aq_hw_link_status_s *link_status = &self->aq_link_status;
 227
 228         if (speed) {
 229                 if (speed & FW2X_RATE_10G)
 230                         link_status->mbps = 10000;
 231                 else if (speed & FW2X_RATE_5G)
 232                         link_status->mbps = 5000;
 233                 else if (speed & FW2X_RATE_2G5)
 234                         link_status->mbps = 2500;
 235                 else if (speed & FW2X_RATE_1G)
 236                         link_status->mbps = 1000;
 237                 else if (speed & FW2X_RATE_100M)
 238                         link_status->mbps = 100;
 239                 else
 240                         link_status->mbps = 10000;
 241         } else {
 242                 link_status->mbps = 0;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
 249 {
 250         int err = 0;
 251         u32 h = 0U;
 252         u32 l = 0U;
 253         u32 mac_addr[2] = { 0 };
 254         u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
 255
 256         if (efuse_addr != 0) {
 257                 err = hw_atl_utils_fw_downld_dwords(self,
 258                                                     efuse_addr + (40U * 4U),
 259                                                     mac_addr,
 260                                                     ARRAY_SIZE(mac_addr));
 261                 if (err)
 262                         return err;
 263                 mac_addr[0] = __swab32(mac_addr[0]);
 264                 mac_addr[1] = __swab32(mac_addr[1]);
 265         }
 266
 267         ether_addr_copy(mac, (u8 *)mac_addr);
 268
 269         if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
 270                 unsigned int rnd = 0;
 271
 272                 get_random_bytes(&rnd, sizeof(unsigned int));
 273
 274                 l = 0xE3000000U | (0xFFFFU & rnd) | (0x00 << 16);
 275                 h = 0x8001300EU;
 276
 277                 mac[5] = (u8)(0xFFU & l);
 278                 l >>= 8;
 279                 mac[4] = (u8)(0xFFU & l);
 280                 l >>= 8;
 281                 mac[3] = (u8)(0xFFU & l);
 282                 l >>= 8;
 283                 mac[2] = (u8)(0xFFU & l);
 284                 mac[1] = (u8)(0xFFU & h);
 285                 h >>= 8;
 286                 mac[0] = (u8)(0xFFU & h);
 287         }
 288         return err;
 289 }
 290
 291 static int aq_fw2x_update_stats(struct aq_hw_s *self)
 292 {
 293         int err = 0;
 294         u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 295         u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
 296         u32 stats_val;
 297
 298         /* Toggle statistics bit for FW to update */
 299         mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
 300         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 301
 302         /* Wait FW to report back */
 303         err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
 304                                         self, stats_val,
 305                                         orig_stats_val != (stats_val &
 306                                         BIT(CAPS_HI_STATISTICS)),
 307                                         1U, 10000U);
 308         if (err)
 309                 return err;
 310
 311         return hw_atl_utils_update_stats(self);
 312 }
 313
 314 static int aq_fw2x_get_phy_temp(struct aq_hw_s *self, int *temp)
 315 {
 316         u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 317         u32 temp_val = mpi_opts & HW_ATL_FW2X_CTRL_TEMPERATURE;
 318         u32 phy_temp_offset;
 319         u32 temp_res;
 320         int err = 0;
 321         u32 val;
 322
 323         phy_temp_offset = self->mbox_addr +
 324                           offsetof(struct hw_atl_utils_mbox, info) +
 325                           offsetof(struct hw_aq_info, phy_temperature);
 326         /* Toggle statistics bit for FW to 0x36C.18 (CTRL_TEMPERATURE) */
 327         mpi_opts = mpi_opts ^ HW_ATL_FW2X_CTRL_TEMPERATURE;
 328         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 329         /* Wait FW to report back */
 330         err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
 331                                         temp_val !=
 332                                         (val & HW_ATL_FW2X_CTRL_TEMPERATURE),
 333                                         1U, 10000U);
 334         err = hw_atl_utils_fw_downld_dwords(self, phy_temp_offset,
 335                                             &temp_res, 1);
 336
 337         if (err)
 338                 return err;
 339
 340         /* Convert PHY temperature from 1/256 degree Celsius
 341          * to 1/1000 degree Celsius.
 342          */
 343         *temp = (temp_res & 0xFFFF) * 1000 / 256;
 344
 345         return 0;
 346 }
 347
 348 static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
 349 {
 350         struct hw_atl_utils_fw_rpc *rpc = NULL;
 351         struct offload_info *cfg = NULL;
 352         unsigned int rpc_size = 0U;
 353         u32 mpi_opts;
 354         int err = 0;
 355         u32 val;
 356
 357         rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg);
 358
 359         err = hw_atl_utils_fw_rpc_wait(self, &rpc);
 360         if (err < 0)
 361                 goto err_exit;
 362
 363         memset(rpc, 0, rpc_size);
 364         cfg = (struct offload_info *)(&rpc->msg_id + 1);
 365
 366         memcpy(cfg->mac_addr, mac, ETH_ALEN);
 367         cfg->len = sizeof(*cfg);
 368
 369         /* Clear bit 0x36C.23 and 0x36C.22 */
 370         mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 371         mpi_opts &= ~HW_ATL_FW2X_CTRL_SLEEP_PROXY;
 372         mpi_opts &= ~HW_ATL_FW2X_CTRL_LINK_DROP;
 373
 374         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 375
 376         err = hw_atl_utils_fw_rpc_call(self, rpc_size);
 377         if (err < 0)
 378                 goto err_exit;
 379
 380         /* Set bit 0x36C.23 */
 381         mpi_opts |= HW_ATL_FW2X_CTRL_SLEEP_PROXY;
 382         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 383
 384         err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
 385                                         self, val,
 386                                         val & HW_ATL_FW2X_CTRL_SLEEP_PROXY,
 387                                         1U, 100000U);
 388
 389 err_exit:
 390         return err;
 391 }
 392
 393 static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
 394 {
 395         struct hw_atl_utils_fw_rpc *rpc = NULL;
 396         struct fw2x_msg_wol *msg = NULL;
 397         u32 mpi_opts;
 398         int err = 0;
 399         u32 val;
 400
 401         err = hw_atl_utils_fw_rpc_wait(self, &rpc);
 402         if (err < 0)
 403                 goto err_exit;
 404
 405         msg = (struct fw2x_msg_wol *)rpc;
 406
 407         memset(msg, 0, sizeof(*msg));
 408
 409         msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL;
 410         msg->magic_packet_enabled = true;
 411         memcpy(msg->hw_addr, mac, ETH_ALEN);
 412
 413         mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 414         mpi_opts &= ~(HW_ATL_FW2X_CTRL_SLEEP_PROXY | HW_ATL_FW2X_CTRL_WOL);
 415
 416         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 417
 418         err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg));
 419         if (err < 0)
 420                 goto err_exit;
 421
 422         /* Set bit 0x36C.24 */
 423         mpi_opts |= HW_ATL_FW2X_CTRL_WOL;
 424         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 425
 426         err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
 427                                         self, val, val & HW_ATL_FW2X_CTRL_WOL,
 428                                         1U, 10000U);
 429
 430 err_exit:
 431         return err;
 432 }
 433
 434 static int aq_fw2x_set_power(struct aq_hw_s *self, unsigned int power_state,
 435                              u8 *mac)
 436 {
 437         int err = 0;
 438
 439         if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) {
 440                 err = aq_fw2x_set_sleep_proxy(self, mac);
 441                 if (err < 0)
 442                         goto err_exit;
 443                 err = aq_fw2x_set_wol_params(self, mac);
 444         }
 445
 446 err_exit:
 447         return err;
 448 }
 449
 450 static int aq_fw2x_send_fw_request(struct aq_hw_s *self,
 451                                    const struct hw_fw_request_iface *fw_req,
 452                                    size_t size)
 453 {
 454         u32 ctrl2, orig_ctrl2;
 455         u32 dword_cnt;
 456         int err = 0;
 457         u32 val;
 458
 459         /* Write data to drvIface Mailbox */
 460         dword_cnt = size / sizeof(u32);
 461         if (size % sizeof(u32))
 462                 dword_cnt++;
 463         err = hw_atl_utils_fw_upload_dwords(self, aq_fw2x_rpc_get(self),
 464                                             (void *)fw_req, dword_cnt);
 465         if (err < 0)
 466                 goto err_exit;
 467
 468         /* Toggle statistics bit for FW to update */
 469         ctrl2 = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 470         orig_ctrl2 = ctrl2 & BIT(CAPS_HI_FW_REQUEST);
 471         ctrl2 = ctrl2 ^ BIT(CAPS_HI_FW_REQUEST);
 472         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, ctrl2);
 473
 474         /* Wait FW to report back */
 475         err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
 476                                         orig_ctrl2 != (val &
 477                                                        BIT(CAPS_HI_FW_REQUEST)),
 478                                         1U, 10000U);
 479
 480 err_exit:
 481         return err;
 482 }
 483
 484 static void aq_fw3x_enable_ptp(struct aq_hw_s *self, int enable)
 485 {
 486         u32 ptp_opts = aq_hw_read_reg(self, HW_ATL_FW3X_EXT_STATE_ADDR);
 487         u32 all_ptp_features = BIT(CAPS_EX_PHY_PTP_EN) |
 488                                                    BIT(CAPS_EX_PTP_GPIO_EN);
 489
 490         if (enable)
 491                 ptp_opts |= all_ptp_features;
 492         else
 493                 ptp_opts &= ~all_ptp_features;
 494
 495         aq_hw_write_reg(self, HW_ATL_FW3X_EXT_CONTROL_ADDR, ptp_opts);
 496 }
 497
 498 static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
 499 {
 500         u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 501
 502         aq_fw2x_upd_eee_rate_bits(self, &mpi_opts, speed);
 503
 504         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 505
 506         return 0;
 507 }
 508
 509 static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
 510                                 u32 *supported_rates)
 511 {
 512         u32 mpi_state;
 513         u32 caps_hi;
 514         int err = 0;
 515         u32 addr = self->mbox_addr + offsetof(struct hw_atl_utils_mbox, info) +
 516                    offsetof(struct hw_aq_info, caps_hi);
 517
 518         err = hw_atl_utils_fw_downld_dwords(self, addr, &caps_hi,
 519                                             sizeof(caps_hi) / sizeof(u32));
 520
 521         if (err)
 522                 return err;
 523
 524         *supported_rates = fw2x_to_eee_mask(caps_hi);
 525
 526         mpi_state = aq_fw2x_state2_get(self);
 527         *rate = fw2x_to_eee_mask(mpi_state);
 528
 529         return err;
 530 }
 531
 532 static int aq_fw2x_renegotiate(struct aq_hw_s *self)
 533 {
 534         u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 535
 536         mpi_opts |= BIT(CTRL_FORCE_RECONNECT);
 537
 538         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 539
 540         return 0;
 541 }
 542
 543 static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
 544 {
 545         u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
 546
 547         aq_fw2x_set_mpi_flow_control(self, &mpi_state);
 548
 549         aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
 550
 551         return 0;
 552 }
 553
 554 static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode)
 555 {
 556         u32 mpi_state = aq_fw2x_state2_get(self);
 557
 558         if (mpi_state & HW_ATL_FW2X_CAP_PAUSE)
 559                 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)
 560                         *fcmode = AQ_NIC_FC_RX;
 561                 else
 562                         *fcmode = AQ_NIC_FC_RX | AQ_NIC_FC_TX;
 563         else
 564                 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)
 565                         *fcmode = AQ_NIC_FC_TX;
 566                 else
 567                         *fcmode = 0;
 568
 569         return 0;
 570 }
 571
 572 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self)
 573 {
 574         return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);
 575 }
 576
 577 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self)
 578 {
 579         return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR);
 580 }
 581
 582 static u32 aq_fw2x_state2_get(struct aq_hw_s *self)
 583 {
 584         return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
 585 }
 586
 587 const struct aq_fw_ops aq_fw_2x_ops = {
 588         .init               = aq_fw2x_init,
 589         .deinit             = aq_fw2x_deinit,
 590         .reset              = NULL,
 591         .renegotiate        = aq_fw2x_renegotiate,
 592         .get_mac_permanent  = aq_fw2x_get_mac_permanent,
 593         .set_link_speed     = aq_fw2x_set_link_speed,
 594         .set_state          = aq_fw2x_set_state,
 595         .update_link_status = aq_fw2x_update_link_status,
 596         .update_stats       = aq_fw2x_update_stats,
 597         .get_phy_temp       = aq_fw2x_get_phy_temp,
 598         .set_power          = aq_fw2x_set_power,
 599         .set_eee_rate       = aq_fw2x_set_eee_rate,
 600         .get_eee_rate       = aq_fw2x_get_eee_rate,
 601         .set_flow_control   = aq_fw2x_set_flow_control,
 602         .get_flow_control   = aq_fw2x_get_flow_control,
 603         .send_fw_request    = aq_fw2x_send_fw_request,
 604         .enable_ptp         = aq_fw3x_enable_ptp,
 605 };