1 /* bnx2x_cmn.h: QLogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/irq.h>
29 #include "bnx2x_sriov.h"
31 /* This is used as a replacement for an MCP if it's not present */
32 extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
33 extern int bnx2x_num_queues;
35 /************************ Macros ********************************/
36 #define BNX2X_PCI_FREE(x, y, size) \
39 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
45 #define BNX2X_FREE(x) \
53 #define BNX2X_PCI_ALLOC(y, size) \
55 void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
58 "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \
59 (unsigned long long)(*y), x); \
62 #define BNX2X_PCI_FALLOC(y, size) \
64 void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
66 memset(x, 0xff, size); \
68 "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n", \
69 (unsigned long long)(*y), x); \
74 /*********************** Interfaces ****************************
75 * Functions that need to be implemented by each driver version
80 * bnx2x_send_unload_req - request unload mode from the MCP.
83 * @unload_mode: requested function's unload mode
85 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
87 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
90 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
93 * @keep_link: true iff link should be kept up
95 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link);
98 * bnx2x_config_rss_pf - configure RSS parameters in a PF.
101 * @rss_obj: RSS object to use
102 * @ind_table: indirection table to configure
103 * @config_hash: re-configure RSS hash keys configuration
104 * @enable: enabled or disabled configuration
106 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
107 bool config_hash, bool enable);
110 * bnx2x__init_func_obj - init function object
114 * Initializes the Function Object with the appropriate
115 * parameters which include a function slow path driver
118 void bnx2x__init_func_obj(struct bnx2x *bp);
121 * bnx2x_setup_queue - setup eth queue.
124 * @fp: pointer to the fastpath structure
128 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
132 * bnx2x_setup_leading - bring up a leading eth queue.
136 int bnx2x_setup_leading(struct bnx2x *bp);
139 * bnx2x_fw_command - send the MCP a request
143 * @param: request's parameter
145 * block until there is a reply
147 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
150 * bnx2x_initial_phy_init - initialize link parameters structure variables.
153 * @load_mode: current mode
155 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
158 * bnx2x_link_set - configure hw according to link parameters structure.
162 void bnx2x_link_set(struct bnx2x *bp);
165 * bnx2x_force_link_reset - Forces link reset, and put the PHY
170 void bnx2x_force_link_reset(struct bnx2x *bp);
173 * bnx2x_link_test - query link status.
178 * Returns 0 if link is UP.
180 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
183 * bnx2x_drv_pulse - write driver pulse to shmem
187 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
190 void bnx2x_drv_pulse(struct bnx2x *bp);
193 * bnx2x_igu_ack_sb - update IGU with current SB value
197 * @segment: SB segment
200 * @update: is HW update required
202 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
203 u16 index, u8 op, u8 update);
205 /* Disable transactions from chip to host */
206 void bnx2x_pf_disable(struct bnx2x *bp);
207 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
210 * bnx2x__link_status_update - handles link status change.
214 void bnx2x__link_status_update(struct bnx2x *bp);
217 * bnx2x_link_report - report link status to upper layer.
221 void bnx2x_link_report(struct bnx2x *bp);
223 /* None-atomic version of bnx2x_link_report() */
224 void __bnx2x_link_report(struct bnx2x *bp);
227 * bnx2x_get_mf_speed - calculate MF speed.
231 * Takes into account current linespeed and MF configuration.
233 u16 bnx2x_get_mf_speed(struct bnx2x *bp);
236 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
239 * @dev_instance: private instance
241 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
244 * bnx2x_interrupt - non MSI-X interrupt handler
247 * @dev_instance: private instance
249 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
252 * bnx2x_cnic_notify - send command to cnic driver
257 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
260 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
264 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
267 * bnx2x_setup_cnic_info - provides cnic with updated info
271 void bnx2x_setup_cnic_info(struct bnx2x *bp);
274 * bnx2x_int_enable - enable HW interrupts.
278 void bnx2x_int_enable(struct bnx2x *bp);
281 * bnx2x_int_disable_sync - disable interrupts.
284 * @disable_hw: true, disable HW interrupts.
286 * This function ensures that there are no
287 * ISRs or SP DPCs (sp_task) are running after it returns.
289 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
292 * bnx2x_nic_init_cnic - init driver internals for cnic.
295 * @load_code: COMMON, PORT or FUNCTION
302 void bnx2x_nic_init_cnic(struct bnx2x *bp);
305 * bnx2x_preirq_nic_init - init driver internals.
314 void bnx2x_pre_irq_nic_init(struct bnx2x *bp);
317 * bnx2x_postirq_nic_init - init driver internals.
320 * @load_code: COMMON, PORT or FUNCTION
327 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code);
329 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic.
333 int bnx2x_alloc_mem_cnic(struct bnx2x *bp);
335 * bnx2x_alloc_mem - allocate driver's memory.
339 int bnx2x_alloc_mem(struct bnx2x *bp);
342 * bnx2x_free_mem_cnic - release driver's memory for cnic.
346 void bnx2x_free_mem_cnic(struct bnx2x *bp);
348 * bnx2x_free_mem - release driver's memory.
352 void bnx2x_free_mem(struct bnx2x *bp);
355 * bnx2x_set_num_queues - set number of queues according to mode.
359 void bnx2x_set_num_queues(struct bnx2x *bp);
362 * bnx2x_chip_cleanup - cleanup chip internals.
365 * @unload_mode: COMMON, PORT, FUNCTION
366 * @keep_link: true iff link should be kept up.
368 * - Cleanup MAC configuration.
372 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link);
375 * bnx2x_acquire_hw_lock - acquire HW lock.
378 * @resource: resource bit which was locked
380 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
383 * bnx2x_release_hw_lock - release HW lock.
386 * @resource: resource bit which was locked
388 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
391 * bnx2x_release_leader_lock - release recovery leader lock
395 int bnx2x_release_leader_lock(struct bnx2x *bp);
398 * bnx2x_set_eth_mac - configure eth MAC address in the HW
403 * Configures according to the value in netdev->dev_addr.
405 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
408 * bnx2x_set_rx_mode - set MAC filtering configurations.
412 * called with netif_tx_lock from dev_mcast.c
413 * If bp->state is OPEN, should be called with
414 * netif_addr_lock_bh()
416 void bnx2x_set_rx_mode_inner(struct bnx2x *bp);
418 /* Parity errors related */
419 void bnx2x_set_pf_load(struct bnx2x *bp);
420 bool bnx2x_clear_pf_load(struct bnx2x *bp);
421 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
422 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
423 void bnx2x_set_reset_in_progress(struct bnx2x *bp);
424 void bnx2x_set_reset_global(struct bnx2x *bp);
425 void bnx2x_disable_close_the_gate(struct bnx2x *bp);
426 int bnx2x_init_hw_func_cnic(struct bnx2x *bp);
429 * bnx2x_sp_event - handle ramrods completion.
431 * @fp: fastpath handle for the event
432 * @rr_cqe: eth_rx_cqe
434 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
437 * bnx2x_ilt_set_info - prepare ILT configurations.
441 void bnx2x_ilt_set_info(struct bnx2x *bp);
444 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC
449 void bnx2x_ilt_set_info_cnic(struct bnx2x *bp);
452 * bnx2x_dcbx_init - initialize dcbx protocol.
456 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem);
459 * bnx2x_set_power_state - set power state to the requested value.
462 * @state: required state D0 or D3hot
464 * Currently only D0 and D3hot are supported.
466 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
469 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
474 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
476 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
478 /* dev_close main block */
479 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link);
481 /* dev_open main block */
482 int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
484 /* hard_xmit callback */
485 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
487 /* setup_tc callback */
488 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
489 int __bnx2x_setup_tc(struct net_device *dev, enum tc_setup_type type,
492 int bnx2x_get_vf_config(struct net_device *dev, int vf,
493 struct ifla_vf_info *ivi);
494 int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac);
495 int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos,
497 int bnx2x_set_vf_spoofchk(struct net_device *dev, int idx, bool val);
499 /* select_queue callback */
500 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
501 struct net_device *sb_dev,
502 select_queue_fallback_t fallback);
504 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
505 struct bnx2x_fastpath *fp,
506 u16 bd_prod, u16 rx_comp_prod,
509 struct ustorm_eth_rx_producers rx_prods = {0};
512 /* Update producers */
513 rx_prods.bd_prod = bd_prod;
514 rx_prods.cqe_prod = rx_comp_prod;
515 rx_prods.sge_prod = rx_sge_prod;
517 /* Make sure that the BD and SGE data is updated before updating the
518 * producers since FW might read the BD/SGE right after the producer
520 * This is only applicable for weak-ordered memory model archs such
521 * as IA-64. The following barrier is also mandatory since FW will
522 * assumes BDs must have buffers.
526 for (i = 0; i < sizeof(rx_prods)/4; i++)
527 REG_WR_RELAXED(bp, fp->ustorm_rx_prods_offset + i * 4,
528 ((u32 *)&rx_prods)[i]);
532 DP(NETIF_MSG_RX_STATUS,
533 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
534 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
538 int bnx2x_reload_if_running(struct net_device *dev);
540 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
542 /* NAPI poll Tx part */
543 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
545 /* suspend/resume callbacks */
546 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
547 int bnx2x_resume(struct pci_dev *pdev);
549 /* Release IRQ vectors */
550 void bnx2x_free_irq(struct bnx2x *bp);
552 void bnx2x_free_fp_mem(struct bnx2x *bp);
553 void bnx2x_init_rx_rings(struct bnx2x *bp);
554 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp);
555 void bnx2x_free_skbs(struct bnx2x *bp);
556 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
557 void bnx2x_netif_start(struct bnx2x *bp);
558 int bnx2x_load_cnic(struct bnx2x *bp);
561 * bnx2x_enable_msix - set msix configuration.
565 * fills msix_table, requests vectors, updates num_queues
566 * according to number of available vectors.
568 int bnx2x_enable_msix(struct bnx2x *bp);
571 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
575 int bnx2x_enable_msi(struct bnx2x *bp);
578 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
582 int bnx2x_alloc_mem_bp(struct bnx2x *bp);
585 * bnx2x_free_mem_bp - release memories outsize main driver structure
589 void bnx2x_free_mem_bp(struct bnx2x *bp);
592 * bnx2x_change_mtu - change mtu netdev callback
595 * @new_mtu: requested mtu
598 int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
600 #ifdef NETDEV_FCOE_WWNN
602 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
605 * @wwn: output buffer
606 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
609 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
612 netdev_features_t bnx2x_fix_features(struct net_device *dev,
613 netdev_features_t features);
614 int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
617 * bnx2x_tx_timeout - tx timeout netdev callback
621 void bnx2x_tx_timeout(struct net_device *dev);
623 /** bnx2x_get_c2s_mapping - read inner-to-outer vlan configuration
624 * c2s_map should have BNX2X_MAX_PRIORITY entries.
626 * @c2s_map: should have BNX2X_MAX_PRIORITY entries for mapping
627 * @c2s_default: entry for non-tagged configuration
629 void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default);
631 /*********************** Inlines **********************************/
632 /*********************** Fast path ********************************/
633 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
635 barrier(); /* status block is written to by the chip */
636 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
639 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
640 u8 segment, u16 index, u8 op,
641 u8 update, u32 igu_addr)
643 struct igu_regular cmd_data = {0};
645 cmd_data.sb_id_and_flags =
646 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
647 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
648 (update << IGU_REGULAR_BUPDATE_SHIFT) |
649 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
651 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
652 cmd_data.sb_id_and_flags, igu_addr);
653 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
655 /* Make sure that ACK is written */
660 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
661 u8 storm, u16 index, u8 op, u8 update)
663 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
664 COMMAND_REG_INT_ACK);
665 struct igu_ack_register igu_ack;
667 igu_ack.status_block_index = index;
668 igu_ack.sb_id_and_flags =
669 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
670 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
671 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
672 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
674 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
676 /* Make sure that ACK is written */
681 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
682 u16 index, u8 op, u8 update)
684 if (bp->common.int_block == INT_BLOCK_HC)
685 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
689 if (CHIP_INT_MODE_IS_BC(bp))
691 else if (igu_sb_id != bp->igu_dsb_id)
692 segment = IGU_SEG_ACCESS_DEF;
693 else if (storm == ATTENTION_ID)
694 segment = IGU_SEG_ACCESS_ATTN;
696 segment = IGU_SEG_ACCESS_DEF;
697 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
701 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
703 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
704 COMMAND_REG_SIMD_MASK);
705 u32 result = REG_RD(bp, hc_addr);
711 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
713 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
714 u32 result = REG_RD(bp, igu_addr);
716 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
723 static inline u16 bnx2x_ack_int(struct bnx2x *bp)
726 if (bp->common.int_block == INT_BLOCK_HC)
727 return bnx2x_hc_ack_int(bp);
729 return bnx2x_igu_ack_int(bp);
732 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
734 /* Tell compiler that consumer and producer can change */
736 return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
739 static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
740 struct bnx2x_fp_txdata *txdata)
746 prod = txdata->tx_bd_prod;
747 cons = txdata->tx_bd_cons;
749 used = SUB_S16(prod, cons);
751 #ifdef BNX2X_STOP_ON_ERROR
753 WARN_ON(used > txdata->tx_ring_size);
754 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL);
757 return (s16)(txdata->tx_ring_size) - used;
760 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
764 /* Tell compiler that status block fields can change */
766 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
767 return hw_cons != txdata->tx_pkt_cons;
770 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
773 for_each_cos_in_tx_queue(fp, cos)
774 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
779 #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0)
780 #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF)
781 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
784 union eth_rx_cqe *cqe;
785 struct eth_fast_path_rx_cqe *cqe_fp;
787 cons = RCQ_BD(fp->rx_comp_cons);
788 cqe = &fp->rx_comp_ring[cons];
789 cqe_fp = &cqe->fast_path_cqe;
790 return BNX2X_IS_CQE_COMPLETED(cqe_fp);
794 * bnx2x_tx_disable - disables tx from stack point of view
798 static inline void bnx2x_tx_disable(struct bnx2x *bp)
800 netif_tx_disable(bp->dev);
801 netif_carrier_off(bp->dev);
804 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
805 struct bnx2x_fastpath *fp, u16 index)
807 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
808 struct page *page = sw_buf->page;
809 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
811 /* Skip "next page" elements */
815 /* Since many fragments can share the same page, make sure to
816 * only unmap and free the page once.
818 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
819 SGE_PAGE_SIZE, DMA_FROM_DEVICE);
828 static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp)
832 for_each_rx_queue_cnic(bp, i) {
833 napi_hash_del(&bnx2x_fp(bp, i, napi));
834 netif_napi_del(&bnx2x_fp(bp, i, napi));
838 static inline void bnx2x_del_all_napi(struct bnx2x *bp)
842 for_each_eth_queue(bp, i) {
843 napi_hash_del(&bnx2x_fp(bp, i, napi));
844 netif_napi_del(&bnx2x_fp(bp, i, napi));
848 int bnx2x_set_int_mode(struct bnx2x *bp);
850 static inline void bnx2x_disable_msi(struct bnx2x *bp)
852 if (bp->flags & USING_MSIX_FLAG) {
853 pci_disable_msix(bp->pdev);
854 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
855 } else if (bp->flags & USING_MSI_FLAG) {
856 pci_disable_msi(bp->pdev);
857 bp->flags &= ~USING_MSI_FLAG;
861 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
865 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
866 int idx = RX_SGE_CNT * i - 1;
868 for (j = 0; j < 2; j++) {
869 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
875 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
877 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
878 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
880 /* Clear the two last indices in the page to 1:
881 these are the indices that correspond to the "next" element,
882 hence will never be indicated and should be removed from
884 bnx2x_clear_sge_mask_next_elems(fp);
887 /* note that we are not allocating a new buffer,
888 * we are just moving one from cons to prod
889 * we are not creating a new mapping,
890 * so there is no need to check for dma_mapping_error().
892 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
895 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
896 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
897 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
898 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
900 dma_unmap_addr_set(prod_rx_buf, mapping,
901 dma_unmap_addr(cons_rx_buf, mapping));
902 prod_rx_buf->data = cons_rx_buf->data;
906 /************************* Init ******************************************/
908 /* returns func by VN for current port */
909 static inline int func_by_vn(struct bnx2x *bp, int vn)
911 return 2 * vn + BP_PORT(bp);
914 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
916 return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true);
920 * bnx2x_func_start - init function
924 * Must be called before sending CLIENT_SETUP for the first client.
926 static inline int bnx2x_func_start(struct bnx2x *bp)
928 struct bnx2x_func_state_params func_params = {NULL};
929 struct bnx2x_func_start_params *start_params =
930 &func_params.params.start;
933 /* Prepare parameters for function state transitions */
934 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
936 func_params.f_obj = &bp->func_obj;
937 func_params.cmd = BNX2X_F_CMD_START;
939 /* Function parameters */
940 start_params->mf_mode = bp->mf_mode;
941 start_params->sd_vlan_tag = bp->mf_ov;
943 /* Configure Ethertype for BD mode */
945 DP(NETIF_MSG_IFUP, "Configuring ethertype 0x88a8 for BD\n");
946 start_params->sd_vlan_eth_type = ETH_P_8021AD;
947 REG_WR(bp, PRS_REG_VLAN_TYPE_0, ETH_P_8021AD);
948 REG_WR(bp, PBF_REG_VLAN_TYPE_0, ETH_P_8021AD);
949 REG_WR(bp, NIG_REG_LLH_E1HOV_TYPE_1, ETH_P_8021AD);
951 bnx2x_get_c2s_mapping(bp, start_params->c2s_pri,
952 &start_params->c2s_pri_default);
953 start_params->c2s_pri_valid = 1;
956 "Inner-to-Outer priority: %02x %02x %02x %02x %02x %02x %02x %02x [Default %02x]\n",
957 start_params->c2s_pri[0], start_params->c2s_pri[1],
958 start_params->c2s_pri[2], start_params->c2s_pri[3],
959 start_params->c2s_pri[4], start_params->c2s_pri[5],
960 start_params->c2s_pri[6], start_params->c2s_pri[7],
961 start_params->c2s_pri_default);
964 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
965 start_params->network_cos_mode = STATIC_COS;
966 else /* CHIP_IS_E1X */
967 start_params->network_cos_mode = FW_WRR;
968 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
969 port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].dst_port;
970 start_params->vxlan_dst_port = port;
972 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
973 port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].dst_port;
974 start_params->geneve_dst_port = port;
977 start_params->inner_rss = 1;
979 if (IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
980 start_params->class_fail_ethtype = ETH_P_FIP;
981 start_params->class_fail = 1;
982 start_params->no_added_tags = 1;
985 return bnx2x_func_state_change(bp, &func_params);
989 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
991 * @fw_hi: pointer to upper part
992 * @fw_mid: pointer to middle part
993 * @fw_lo: pointer to lower part
994 * @mac: pointer to MAC address
996 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
997 __le16 *fw_lo, u8 *mac)
999 ((u8 *)fw_hi)[0] = mac[1];
1000 ((u8 *)fw_hi)[1] = mac[0];
1001 ((u8 *)fw_mid)[0] = mac[3];
1002 ((u8 *)fw_mid)[1] = mac[2];
1003 ((u8 *)fw_lo)[0] = mac[5];
1004 ((u8 *)fw_lo)[1] = mac[4];
1007 static inline void bnx2x_free_rx_mem_pool(struct bnx2x *bp,
1008 struct bnx2x_alloc_pool *pool)
1013 put_page(pool->page);
1018 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1019 struct bnx2x_fastpath *fp, int last)
1023 if (fp->mode == TPA_MODE_DISABLED)
1026 for (i = 0; i < last; i++)
1027 bnx2x_free_rx_sge(bp, fp, i);
1029 bnx2x_free_rx_mem_pool(bp, &fp->page_pool);
1032 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
1036 for (i = 1; i <= NUM_RX_RINGS; i++) {
1037 struct eth_rx_bd *rx_bd;
1039 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
1041 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
1042 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1044 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
1045 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1049 /* Statistics ID are global per chip/path, while Client IDs for E1x are per
1052 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1054 struct bnx2x *bp = fp->bp;
1055 if (!CHIP_IS_E1x(bp)) {
1056 /* there are special statistics counters for FCoE 136..140 */
1058 return bp->cnic_base_cl_id + (bp->pf_num >> 1);
1061 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
1064 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
1065 bnx2x_obj_type obj_type)
1067 struct bnx2x *bp = fp->bp;
1069 /* Configure classification DBs */
1070 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id,
1071 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
1072 bnx2x_sp_mapping(bp, mac_rdata),
1073 BNX2X_FILTER_MAC_PENDING,
1074 &bp->sp_state, obj_type,
1077 if (!CHIP_IS_E1x(bp))
1078 bnx2x_init_vlan_obj(bp, &bnx2x_sp_obj(bp, fp).vlan_obj,
1079 fp->cl_id, fp->cid, BP_FUNC(bp),
1080 bnx2x_sp(bp, vlan_rdata),
1081 bnx2x_sp_mapping(bp, vlan_rdata),
1082 BNX2X_FILTER_VLAN_PENDING,
1083 &bp->sp_state, obj_type,
1088 * bnx2x_get_path_func_num - get number of active functions
1090 * @bp: driver handle
1092 * Calculates the number of active (not hidden) functions on the
1095 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
1099 /* 57710 has only one function per-port */
1103 /* Calculate a number of functions enabled on the current
1106 if (CHIP_REV_IS_SLOW(bp)) {
1112 for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1115 func_mf_config[BP_PORT(bp) + 2 * i].
1118 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1127 static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1129 /* RX_MODE controlling object */
1130 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1132 /* multicast configuration controlling object */
1133 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1134 BP_FUNC(bp), BP_FUNC(bp),
1135 bnx2x_sp(bp, mcast_rdata),
1136 bnx2x_sp_mapping(bp, mcast_rdata),
1137 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1140 /* Setup CAM credit pools */
1141 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1142 bnx2x_get_path_func_num(bp));
1144 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_FUNC(bp),
1145 bnx2x_get_path_func_num(bp));
1147 /* RSS configuration object */
1148 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1149 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1150 bnx2x_sp(bp, rss_rdata),
1151 bnx2x_sp_mapping(bp, rss_rdata),
1152 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1155 bp->vlan_credit = PF_VLAN_CREDIT_E2(bp, bnx2x_get_path_func_num(bp));
1158 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1160 if (CHIP_IS_E1x(fp->bp))
1161 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1166 static inline void bnx2x_init_txdata(struct bnx2x *bp,
1167 struct bnx2x_fp_txdata *txdata, u32 cid,
1168 int txq_index, __le16 *tx_cons_sb,
1169 struct bnx2x_fastpath *fp)
1172 txdata->txq_index = txq_index;
1173 txdata->tx_cons_sb = tx_cons_sb;
1174 txdata->parent_fp = fp;
1175 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size;
1177 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1178 txdata->cid, txdata->txq_index);
1181 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
1183 return bp->cnic_base_cl_id + cl_idx +
1184 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1187 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1189 /* the 'first' id is allocated for the cnic */
1190 return bp->base_fw_ndsb;
1193 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1195 return bp->igu_base_sb;
1198 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1199 struct bnx2x_fp_txdata *txdata)
1203 while (bnx2x_has_tx_work_unload(txdata)) {
1205 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1206 txdata->txq_index, txdata->tx_pkt_prod,
1207 txdata->tx_pkt_cons);
1208 #ifdef BNX2X_STOP_ON_ERROR
1216 usleep_range(1000, 2000);
1222 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1224 static inline void __storm_memset_struct(struct bnx2x *bp,
1225 u32 addr, size_t size, u32 *data)
1228 for (i = 0; i < size/4; i++)
1229 REG_WR(bp, addr + (i * 4), data[i]);
1233 * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1235 * @bp: driver handle
1236 * @mask: bits that need to be cleared
1238 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1240 int tout = 5000; /* Wait for 5 secs tops */
1244 netif_addr_lock_bh(bp->dev);
1245 if (!(bp->sp_state & mask)) {
1246 netif_addr_unlock_bh(bp->dev);
1249 netif_addr_unlock_bh(bp->dev);
1251 usleep_range(1000, 2000);
1256 netif_addr_lock_bh(bp->dev);
1257 if (bp->sp_state & mask) {
1258 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1259 bp->sp_state, mask);
1260 netif_addr_unlock_bh(bp->dev);
1263 netif_addr_unlock_bh(bp->dev);
1269 * bnx2x_set_ctx_validation - set CDU context validation values
1271 * @bp: driver handle
1272 * @cxt: context of the connection on the host memory
1273 * @cid: SW CID of the connection to be configured
1275 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1278 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
1279 u8 sb_index, u8 disable, u16 usec);
1280 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1281 void bnx2x_release_phy_lock(struct bnx2x *bp);
1284 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1286 * @bp: driver handle
1287 * @mf_cfg: MF configuration
1290 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1292 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1293 FUNC_MF_CFG_MAX_BW_SHIFT;
1295 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1296 "Max BW configured to 0 - using 100 instead\n");
1302 /* checks if HW supports GRO for given MTU */
1303 static inline bool bnx2x_mtu_allows_gro(int mtu)
1305 /* gro frags per page */
1306 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1309 * 1. Number of frags should not grow above MAX_SKB_FRAGS
1310 * 2. Frag must fit the page
1312 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1316 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
1318 * @bp: driver handle
1321 void bnx2x_get_iscsi_info(struct bnx2x *bp);
1324 * bnx2x_link_sync_notify - send notification to other functions.
1326 * @bp: driver handle
1329 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1334 /* Set the attention towards other drivers on the same port */
1335 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1336 if (vn == BP_VN(bp))
1339 func = func_by_vn(bp, vn);
1340 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1341 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1346 * bnx2x_update_drv_flags - update flags in shmem
1348 * @bp: driver handle
1349 * @flags: flags to update
1350 * @set: set or clear
1353 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1355 if (SHMEM2_HAS(bp, drv_flags)) {
1357 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1358 drv_flags = SHMEM2_RD(bp, drv_flags);
1361 SET_FLAGS(drv_flags, flags);
1363 RESET_FLAGS(drv_flags, flags);
1365 SHMEM2_WR(bp, drv_flags, drv_flags);
1366 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1367 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1374 * bnx2x_fill_fw_str - Fill buffer with FW version string
1376 * @bp: driver handle
1377 * @buf: character buffer to fill with the fw name
1378 * @buf_len: length of the above buffer
1381 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len);
1383 int bnx2x_drain_tx_queues(struct bnx2x *bp);
1384 void bnx2x_squeeze_objects(struct bnx2x *bp);
1386 void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag,
1390 * bnx2x_set_os_driver_state - write driver state for management FW usage
1392 * @bp: driver handle
1393 * @state: OS_DRIVER_STATE_* value reflecting current driver state
1395 void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state);
1398 * bnx2x_nvram_read - reads data from nvram [might sleep]
1400 * @bp: driver handle
1401 * @offset: byte offset in nvram
1402 * @ret_buf: pointer to buffer where data is to be stored
1403 * @buf_size: Length of 'ret_buf' in bytes
1405 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1408 #endif /* BNX2X_CMN_H */