1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/mdio.h>
36 #include <linux/if_vlan.h>
37 #include <linux/if_bridge.h>
38 #include <linux/rtc.h>
39 #include <linux/bpf.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <net/udp_tunnel.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53 #include <linux/cpumask.h>
54 #include <net/pkt_cls.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
61 #include "bnxt_sriov.h"
62 #include "bnxt_ethtool.h"
67 #include "bnxt_devlink.h"
68 #include "bnxt_debugfs.h"
70 #define BNXT_TX_TIMEOUT (5 * HZ)
72 static const char version[] =
73 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
75 MODULE_LICENSE("GPL");
76 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
77 MODULE_VERSION(DRV_MODULE_VERSION);
79 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
80 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
81 #define BNXT_RX_COPY_THRESH 256
83 #define BNXT_TX_PUSH_THRESH 164
126 /* indexed by enum above */
127 static const struct {
130 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
131 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
132 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
133 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
134 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
135 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
136 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
137 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
138 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
139 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
140 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
141 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
142 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
143 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
144 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
145 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
146 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
147 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
148 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
149 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
150 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
151 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
152 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
153 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
154 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
155 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
156 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
157 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
158 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
159 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
160 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
161 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
162 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
163 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
164 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
165 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
166 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
167 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
170 static const struct pci_device_id bnxt_pci_tbl[] = {
171 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
172 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
173 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
174 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
175 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
176 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
177 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
178 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
179 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
180 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
181 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
182 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
183 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
184 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
185 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
186 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
187 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
188 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
189 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
190 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
191 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
192 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
193 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
194 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
195 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
196 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
197 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
198 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
199 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
200 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
201 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
202 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
203 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
204 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
205 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
206 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
207 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
208 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
209 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
210 #ifdef CONFIG_BNXT_SRIOV
211 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
212 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
213 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
214 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
215 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
216 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
217 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
218 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
219 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
220 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
225 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
227 static const u16 bnxt_vf_req_snif[] = {
231 HWRM_CFA_L2_FILTER_ALLOC,
234 static const u16 bnxt_async_events_arr[] = {
235 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
236 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
237 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
238 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
239 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
242 static struct workqueue_struct *bnxt_pf_wq;
244 static bool bnxt_vf_pciid(enum board_idx idx)
246 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
247 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
250 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
251 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
252 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
254 #define BNXT_CP_DB_IRQ_DIS(db) \
255 writel(DB_CP_IRQ_DIS_FLAGS, db)
257 #define BNXT_DB_CQ(db, idx) \
258 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
260 #define BNXT_DB_NQ_P5(db, idx) \
261 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
263 #define BNXT_DB_CQ_ARM(db, idx) \
264 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
266 #define BNXT_DB_NQ_ARM_P5(db, idx) \
267 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
269 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
271 if (bp->flags & BNXT_FLAG_CHIP_P5)
272 BNXT_DB_NQ_P5(db, idx);
277 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
279 if (bp->flags & BNXT_FLAG_CHIP_P5)
280 BNXT_DB_NQ_ARM_P5(db, idx);
282 BNXT_DB_CQ_ARM(db, idx);
285 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
287 if (bp->flags & BNXT_FLAG_CHIP_P5)
288 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
294 const u16 bnxt_lhint_arr[] = {
295 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
296 TX_BD_FLAGS_LHINT_512_TO_1023,
297 TX_BD_FLAGS_LHINT_1024_TO_2047,
298 TX_BD_FLAGS_LHINT_1024_TO_2047,
299 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
300 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
301 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
302 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
303 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
304 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
305 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
306 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
307 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
308 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
309 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
310 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
311 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
312 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
313 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
316 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
318 struct metadata_dst *md_dst = skb_metadata_dst(skb);
320 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
323 return md_dst->u.port_info.port_id;
326 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
328 struct bnxt *bp = netdev_priv(dev);
330 struct tx_bd_ext *txbd1;
331 struct netdev_queue *txq;
334 unsigned int length, pad = 0;
335 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
337 struct pci_dev *pdev = bp->pdev;
338 struct bnxt_tx_ring_info *txr;
339 struct bnxt_sw_tx_bd *tx_buf;
341 i = skb_get_queue_mapping(skb);
342 if (unlikely(i >= bp->tx_nr_rings)) {
343 dev_kfree_skb_any(skb);
347 txq = netdev_get_tx_queue(dev, i);
348 txr = &bp->tx_ring[bp->tx_ring_map[i]];
351 free_size = bnxt_tx_avail(bp, txr);
352 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
353 netif_tx_stop_queue(txq);
354 return NETDEV_TX_BUSY;
358 len = skb_headlen(skb);
359 last_frag = skb_shinfo(skb)->nr_frags;
361 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
363 txbd->tx_bd_opaque = prod;
365 tx_buf = &txr->tx_buf_ring[prod];
367 tx_buf->nr_frags = last_frag;
370 cfa_action = bnxt_xmit_get_cfa_action(skb);
371 if (skb_vlan_tag_present(skb)) {
372 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
373 skb_vlan_tag_get(skb);
374 /* Currently supports 8021Q, 8021AD vlan offloads
375 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
377 if (skb->vlan_proto == htons(ETH_P_8021Q))
378 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
381 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
382 struct tx_push_buffer *tx_push_buf = txr->tx_push;
383 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
384 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
385 void __iomem *db = txr->tx_db.doorbell;
386 void *pdata = tx_push_buf->data;
390 /* Set COAL_NOW to be ready quickly for the next push */
391 tx_push->tx_bd_len_flags_type =
392 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
393 TX_BD_TYPE_LONG_TX_BD |
394 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
395 TX_BD_FLAGS_COAL_NOW |
396 TX_BD_FLAGS_PACKET_END |
397 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
399 if (skb->ip_summed == CHECKSUM_PARTIAL)
400 tx_push1->tx_bd_hsize_lflags =
401 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
403 tx_push1->tx_bd_hsize_lflags = 0;
405 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
406 tx_push1->tx_bd_cfa_action =
407 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
409 end = pdata + length;
410 end = PTR_ALIGN(end, 8) - 1;
413 skb_copy_from_linear_data(skb, pdata, len);
415 for (j = 0; j < last_frag; j++) {
416 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
419 fptr = skb_frag_address_safe(frag);
423 memcpy(pdata, fptr, skb_frag_size(frag));
424 pdata += skb_frag_size(frag);
427 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
428 txbd->tx_bd_haddr = txr->data_mapping;
429 prod = NEXT_TX(prod);
430 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
431 memcpy(txbd, tx_push1, sizeof(*txbd));
432 prod = NEXT_TX(prod);
434 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
438 netdev_tx_sent_queue(txq, skb->len);
439 wmb(); /* Sync is_push and byte queue before pushing data */
441 push_len = (length + sizeof(*tx_push) + 7) / 8;
443 __iowrite64_copy(db, tx_push_buf, 16);
444 __iowrite32_copy(db + 4, tx_push_buf + 1,
445 (push_len - 16) << 1);
447 __iowrite64_copy(db, tx_push_buf, push_len);
454 if (length < BNXT_MIN_PKT_SIZE) {
455 pad = BNXT_MIN_PKT_SIZE - length;
456 if (skb_pad(skb, pad)) {
457 /* SKB already freed. */
461 length = BNXT_MIN_PKT_SIZE;
464 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
466 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
467 dev_kfree_skb_any(skb);
472 dma_unmap_addr_set(tx_buf, mapping, mapping);
473 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
474 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
476 txbd->tx_bd_haddr = cpu_to_le64(mapping);
478 prod = NEXT_TX(prod);
479 txbd1 = (struct tx_bd_ext *)
480 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
482 txbd1->tx_bd_hsize_lflags = 0;
483 if (skb_is_gso(skb)) {
486 if (skb->encapsulation)
487 hdr_len = skb_inner_network_offset(skb) +
488 skb_inner_network_header_len(skb) +
489 inner_tcp_hdrlen(skb);
491 hdr_len = skb_transport_offset(skb) +
494 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
496 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
497 length = skb_shinfo(skb)->gso_size;
498 txbd1->tx_bd_mss = cpu_to_le32(length);
500 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
501 txbd1->tx_bd_hsize_lflags =
502 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
503 txbd1->tx_bd_mss = 0;
507 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
508 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
513 flags |= bnxt_lhint_arr[length];
514 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
516 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
517 txbd1->tx_bd_cfa_action =
518 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
519 for (i = 0; i < last_frag; i++) {
520 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
522 prod = NEXT_TX(prod);
523 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
525 len = skb_frag_size(frag);
526 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
529 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
532 tx_buf = &txr->tx_buf_ring[prod];
533 dma_unmap_addr_set(tx_buf, mapping, mapping);
535 txbd->tx_bd_haddr = cpu_to_le64(mapping);
537 flags = len << TX_BD_LEN_SHIFT;
538 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
542 txbd->tx_bd_len_flags_type =
543 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
544 TX_BD_FLAGS_PACKET_END);
546 netdev_tx_sent_queue(txq, skb->len);
548 /* Sync BD data before updating doorbell */
551 prod = NEXT_TX(prod);
554 if (!skb->xmit_more || netif_xmit_stopped(txq))
555 bnxt_db_write(bp, &txr->tx_db, prod);
561 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
562 if (skb->xmit_more && !tx_buf->is_push)
563 bnxt_db_write(bp, &txr->tx_db, prod);
565 netif_tx_stop_queue(txq);
567 /* netif_tx_stop_queue() must be done before checking
568 * tx index in bnxt_tx_avail() below, because in
569 * bnxt_tx_int(), we update tx index before checking for
570 * netif_tx_queue_stopped().
573 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
574 netif_tx_wake_queue(txq);
581 /* start back at beginning and unmap skb */
583 tx_buf = &txr->tx_buf_ring[prod];
585 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
586 skb_headlen(skb), PCI_DMA_TODEVICE);
587 prod = NEXT_TX(prod);
589 /* unmap remaining mapped pages */
590 for (i = 0; i < last_frag; i++) {
591 prod = NEXT_TX(prod);
592 tx_buf = &txr->tx_buf_ring[prod];
593 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
594 skb_frag_size(&skb_shinfo(skb)->frags[i]),
598 dev_kfree_skb_any(skb);
602 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
604 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
605 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
606 u16 cons = txr->tx_cons;
607 struct pci_dev *pdev = bp->pdev;
609 unsigned int tx_bytes = 0;
611 for (i = 0; i < nr_pkts; i++) {
612 struct bnxt_sw_tx_bd *tx_buf;
616 tx_buf = &txr->tx_buf_ring[cons];
617 cons = NEXT_TX(cons);
621 if (tx_buf->is_push) {
626 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
627 skb_headlen(skb), PCI_DMA_TODEVICE);
628 last = tx_buf->nr_frags;
630 for (j = 0; j < last; j++) {
631 cons = NEXT_TX(cons);
632 tx_buf = &txr->tx_buf_ring[cons];
635 dma_unmap_addr(tx_buf, mapping),
636 skb_frag_size(&skb_shinfo(skb)->frags[j]),
641 cons = NEXT_TX(cons);
643 tx_bytes += skb->len;
644 dev_kfree_skb_any(skb);
647 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
650 /* Need to make the tx_cons update visible to bnxt_start_xmit()
651 * before checking for netif_tx_queue_stopped(). Without the
652 * memory barrier, there is a small possibility that bnxt_start_xmit()
653 * will miss it and cause the queue to be stopped forever.
657 if (unlikely(netif_tx_queue_stopped(txq)) &&
658 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
659 __netif_tx_lock(txq, smp_processor_id());
660 if (netif_tx_queue_stopped(txq) &&
661 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
662 txr->dev_state != BNXT_DEV_STATE_CLOSING)
663 netif_tx_wake_queue(txq);
664 __netif_tx_unlock(txq);
668 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
671 struct device *dev = &bp->pdev->dev;
674 page = alloc_page(gfp);
678 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
679 DMA_ATTR_WEAK_ORDERING);
680 if (dma_mapping_error(dev, *mapping)) {
684 *mapping += bp->rx_dma_offset;
688 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
692 struct pci_dev *pdev = bp->pdev;
694 data = kmalloc(bp->rx_buf_size, gfp);
698 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
699 bp->rx_buf_use_size, bp->rx_dir,
700 DMA_ATTR_WEAK_ORDERING);
702 if (dma_mapping_error(&pdev->dev, *mapping)) {
709 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
712 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
713 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
716 if (BNXT_RX_PAGE_MODE(bp)) {
717 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
723 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
725 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
731 rx_buf->data_ptr = data + bp->rx_offset;
733 rx_buf->mapping = mapping;
735 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
739 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
741 u16 prod = rxr->rx_prod;
742 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
743 struct rx_bd *cons_bd, *prod_bd;
745 prod_rx_buf = &rxr->rx_buf_ring[prod];
746 cons_rx_buf = &rxr->rx_buf_ring[cons];
748 prod_rx_buf->data = data;
749 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
751 prod_rx_buf->mapping = cons_rx_buf->mapping;
753 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
754 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
756 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
759 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
761 u16 next, max = rxr->rx_agg_bmap_size;
763 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
765 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
769 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
770 struct bnxt_rx_ring_info *rxr,
774 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
775 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
776 struct pci_dev *pdev = bp->pdev;
779 u16 sw_prod = rxr->rx_sw_agg_prod;
780 unsigned int offset = 0;
782 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
785 page = alloc_page(gfp);
789 rxr->rx_page_offset = 0;
791 offset = rxr->rx_page_offset;
792 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
793 if (rxr->rx_page_offset == PAGE_SIZE)
798 page = alloc_page(gfp);
803 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
804 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
805 DMA_ATTR_WEAK_ORDERING);
806 if (dma_mapping_error(&pdev->dev, mapping)) {
811 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
812 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
814 __set_bit(sw_prod, rxr->rx_agg_bmap);
815 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
816 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
818 rx_agg_buf->page = page;
819 rx_agg_buf->offset = offset;
820 rx_agg_buf->mapping = mapping;
821 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
822 rxbd->rx_bd_opaque = sw_prod;
826 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
829 struct bnxt_napi *bnapi = cpr->bnapi;
830 struct bnxt *bp = bnapi->bp;
831 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
832 u16 prod = rxr->rx_agg_prod;
833 u16 sw_prod = rxr->rx_sw_agg_prod;
836 for (i = 0; i < agg_bufs; i++) {
838 struct rx_agg_cmp *agg;
839 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
840 struct rx_bd *prod_bd;
843 agg = (struct rx_agg_cmp *)
844 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
845 cons = agg->rx_agg_cmp_opaque;
846 __clear_bit(cons, rxr->rx_agg_bmap);
848 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
849 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
851 __set_bit(sw_prod, rxr->rx_agg_bmap);
852 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
853 cons_rx_buf = &rxr->rx_agg_ring[cons];
855 /* It is possible for sw_prod to be equal to cons, so
856 * set cons_rx_buf->page to NULL first.
858 page = cons_rx_buf->page;
859 cons_rx_buf->page = NULL;
860 prod_rx_buf->page = page;
861 prod_rx_buf->offset = cons_rx_buf->offset;
863 prod_rx_buf->mapping = cons_rx_buf->mapping;
865 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
867 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
868 prod_bd->rx_bd_opaque = sw_prod;
870 prod = NEXT_RX_AGG(prod);
871 sw_prod = NEXT_RX_AGG(sw_prod);
872 cp_cons = NEXT_CMP(cp_cons);
874 rxr->rx_agg_prod = prod;
875 rxr->rx_sw_agg_prod = sw_prod;
878 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
879 struct bnxt_rx_ring_info *rxr,
880 u16 cons, void *data, u8 *data_ptr,
882 unsigned int offset_and_len)
884 unsigned int payload = offset_and_len >> 16;
885 unsigned int len = offset_and_len & 0xffff;
886 struct skb_frag_struct *frag;
887 struct page *page = data;
888 u16 prod = rxr->rx_prod;
892 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
894 bnxt_reuse_rx_data(rxr, cons, data);
897 dma_addr -= bp->rx_dma_offset;
898 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
899 DMA_ATTR_WEAK_ORDERING);
901 if (unlikely(!payload))
902 payload = eth_get_headlen(data_ptr, len);
904 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
910 off = (void *)data_ptr - page_address(page);
911 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
912 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
913 payload + NET_IP_ALIGN);
915 frag = &skb_shinfo(skb)->frags[0];
916 skb_frag_size_sub(frag, payload);
917 frag->page_offset += payload;
918 skb->data_len -= payload;
919 skb->tail += payload;
924 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
925 struct bnxt_rx_ring_info *rxr, u16 cons,
926 void *data, u8 *data_ptr,
928 unsigned int offset_and_len)
930 u16 prod = rxr->rx_prod;
934 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
936 bnxt_reuse_rx_data(rxr, cons, data);
940 skb = build_skb(data, 0);
941 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
942 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
948 skb_reserve(skb, bp->rx_offset);
949 skb_put(skb, offset_and_len & 0xffff);
953 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
954 struct bnxt_cp_ring_info *cpr,
955 struct sk_buff *skb, u16 cp_cons,
958 struct bnxt_napi *bnapi = cpr->bnapi;
959 struct pci_dev *pdev = bp->pdev;
960 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
961 u16 prod = rxr->rx_agg_prod;
964 for (i = 0; i < agg_bufs; i++) {
966 struct rx_agg_cmp *agg;
967 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
971 agg = (struct rx_agg_cmp *)
972 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
973 cons = agg->rx_agg_cmp_opaque;
974 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
975 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
977 cons_rx_buf = &rxr->rx_agg_ring[cons];
978 skb_fill_page_desc(skb, i, cons_rx_buf->page,
979 cons_rx_buf->offset, frag_len);
980 __clear_bit(cons, rxr->rx_agg_bmap);
982 /* It is possible for bnxt_alloc_rx_page() to allocate
983 * a sw_prod index that equals the cons index, so we
984 * need to clear the cons entry now.
986 mapping = cons_rx_buf->mapping;
987 page = cons_rx_buf->page;
988 cons_rx_buf->page = NULL;
990 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
991 struct skb_shared_info *shinfo;
992 unsigned int nr_frags;
994 shinfo = skb_shinfo(skb);
995 nr_frags = --shinfo->nr_frags;
996 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1000 cons_rx_buf->page = page;
1002 /* Update prod since possibly some pages have been
1003 * allocated already.
1005 rxr->rx_agg_prod = prod;
1006 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1010 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1012 DMA_ATTR_WEAK_ORDERING);
1014 skb->data_len += frag_len;
1015 skb->len += frag_len;
1016 skb->truesize += PAGE_SIZE;
1018 prod = NEXT_RX_AGG(prod);
1019 cp_cons = NEXT_CMP(cp_cons);
1021 rxr->rx_agg_prod = prod;
1025 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1026 u8 agg_bufs, u32 *raw_cons)
1029 struct rx_agg_cmp *agg;
1031 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1032 last = RING_CMP(*raw_cons);
1033 agg = (struct rx_agg_cmp *)
1034 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1035 return RX_AGG_CMP_VALID(agg, *raw_cons);
1038 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1042 struct bnxt *bp = bnapi->bp;
1043 struct pci_dev *pdev = bp->pdev;
1044 struct sk_buff *skb;
1046 skb = napi_alloc_skb(&bnapi->napi, len);
1050 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1053 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1054 len + NET_IP_ALIGN);
1056 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1063 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1064 u32 *raw_cons, void *cmp)
1066 struct rx_cmp *rxcmp = cmp;
1067 u32 tmp_raw_cons = *raw_cons;
1068 u8 cmp_type, agg_bufs = 0;
1070 cmp_type = RX_CMP_TYPE(rxcmp);
1072 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1073 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1075 RX_CMP_AGG_BUFS_SHIFT;
1076 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1077 struct rx_tpa_end_cmp *tpa_end = cmp;
1079 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1080 RX_TPA_END_CMP_AGG_BUFS) >>
1081 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1085 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1088 *raw_cons = tmp_raw_cons;
1092 static void bnxt_queue_sp_work(struct bnxt *bp)
1095 queue_work(bnxt_pf_wq, &bp->sp_task);
1097 schedule_work(&bp->sp_task);
1100 static void bnxt_cancel_sp_work(struct bnxt *bp)
1103 flush_workqueue(bnxt_pf_wq);
1105 cancel_work_sync(&bp->sp_task);
1108 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1110 if (!rxr->bnapi->in_reset) {
1111 rxr->bnapi->in_reset = true;
1112 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1113 bnxt_queue_sp_work(bp);
1115 rxr->rx_next_cons = 0xffff;
1118 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1119 struct rx_tpa_start_cmp *tpa_start,
1120 struct rx_tpa_start_cmp_ext *tpa_start1)
1122 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1124 struct bnxt_tpa_info *tpa_info;
1125 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1126 struct rx_bd *prod_bd;
1129 cons = tpa_start->rx_tpa_start_cmp_opaque;
1130 prod = rxr->rx_prod;
1131 cons_rx_buf = &rxr->rx_buf_ring[cons];
1132 prod_rx_buf = &rxr->rx_buf_ring[prod];
1133 tpa_info = &rxr->rx_tpa[agg_id];
1135 if (unlikely(cons != rxr->rx_next_cons)) {
1136 bnxt_sched_reset(bp, rxr);
1139 /* Store cfa_code in tpa_info to use in tpa_end
1140 * completion processing.
1142 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1143 prod_rx_buf->data = tpa_info->data;
1144 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1146 mapping = tpa_info->mapping;
1147 prod_rx_buf->mapping = mapping;
1149 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1151 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1153 tpa_info->data = cons_rx_buf->data;
1154 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1155 cons_rx_buf->data = NULL;
1156 tpa_info->mapping = cons_rx_buf->mapping;
1159 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1160 RX_TPA_START_CMP_LEN_SHIFT;
1161 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1162 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1164 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1165 tpa_info->gso_type = SKB_GSO_TCPV4;
1166 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1167 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1168 tpa_info->gso_type = SKB_GSO_TCPV6;
1169 tpa_info->rss_hash =
1170 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1172 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1173 tpa_info->gso_type = 0;
1174 if (netif_msg_rx_err(bp))
1175 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1177 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1178 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1179 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1181 rxr->rx_prod = NEXT_RX(prod);
1182 cons = NEXT_RX(cons);
1183 rxr->rx_next_cons = NEXT_RX(cons);
1184 cons_rx_buf = &rxr->rx_buf_ring[cons];
1186 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1187 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1188 cons_rx_buf->data = NULL;
1191 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1195 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1198 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1199 int payload_off, int tcp_ts,
1200 struct sk_buff *skb)
1205 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1206 u32 hdr_info = tpa_info->hdr_info;
1207 bool loopback = false;
1209 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1210 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1211 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1213 /* If the packet is an internal loopback packet, the offsets will
1214 * have an extra 4 bytes.
1216 if (inner_mac_off == 4) {
1218 } else if (inner_mac_off > 4) {
1219 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1222 /* We only support inner iPv4/ipv6. If we don't see the
1223 * correct protocol ID, it must be a loopback packet where
1224 * the offsets are off by 4.
1226 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1230 /* internal loopback packet, subtract all offsets by 4 */
1236 nw_off = inner_ip_off - ETH_HLEN;
1237 skb_set_network_header(skb, nw_off);
1238 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1239 struct ipv6hdr *iph = ipv6_hdr(skb);
1241 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1242 len = skb->len - skb_transport_offset(skb);
1244 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1246 struct iphdr *iph = ip_hdr(skb);
1248 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1249 len = skb->len - skb_transport_offset(skb);
1251 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1254 if (inner_mac_off) { /* tunnel */
1255 struct udphdr *uh = NULL;
1256 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1259 if (proto == htons(ETH_P_IP)) {
1260 struct iphdr *iph = (struct iphdr *)skb->data;
1262 if (iph->protocol == IPPROTO_UDP)
1263 uh = (struct udphdr *)(iph + 1);
1265 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1267 if (iph->nexthdr == IPPROTO_UDP)
1268 uh = (struct udphdr *)(iph + 1);
1272 skb_shinfo(skb)->gso_type |=
1273 SKB_GSO_UDP_TUNNEL_CSUM;
1275 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1282 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1283 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1285 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1286 int payload_off, int tcp_ts,
1287 struct sk_buff *skb)
1291 int len, nw_off, tcp_opt_len = 0;
1296 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1299 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1301 skb_set_network_header(skb, nw_off);
1303 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1304 len = skb->len - skb_transport_offset(skb);
1306 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1307 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1308 struct ipv6hdr *iph;
1310 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1312 skb_set_network_header(skb, nw_off);
1313 iph = ipv6_hdr(skb);
1314 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1315 len = skb->len - skb_transport_offset(skb);
1317 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1319 dev_kfree_skb_any(skb);
1323 if (nw_off) { /* tunnel */
1324 struct udphdr *uh = NULL;
1326 if (skb->protocol == htons(ETH_P_IP)) {
1327 struct iphdr *iph = (struct iphdr *)skb->data;
1329 if (iph->protocol == IPPROTO_UDP)
1330 uh = (struct udphdr *)(iph + 1);
1332 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1334 if (iph->nexthdr == IPPROTO_UDP)
1335 uh = (struct udphdr *)(iph + 1);
1339 skb_shinfo(skb)->gso_type |=
1340 SKB_GSO_UDP_TUNNEL_CSUM;
1342 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1349 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1350 struct bnxt_tpa_info *tpa_info,
1351 struct rx_tpa_end_cmp *tpa_end,
1352 struct rx_tpa_end_cmp_ext *tpa_end1,
1353 struct sk_buff *skb)
1359 segs = TPA_END_TPA_SEGS(tpa_end);
1363 NAPI_GRO_CB(skb)->count = segs;
1364 skb_shinfo(skb)->gso_size =
1365 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1366 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1367 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1368 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1369 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1370 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1372 tcp_gro_complete(skb);
1377 /* Given the cfa_code of a received packet determine which
1378 * netdev (vf-rep or PF) the packet is destined to.
1380 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1382 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1384 /* if vf-rep dev is NULL, the must belongs to the PF */
1385 return dev ? dev : bp->dev;
1388 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1389 struct bnxt_cp_ring_info *cpr,
1391 struct rx_tpa_end_cmp *tpa_end,
1392 struct rx_tpa_end_cmp_ext *tpa_end1,
1395 struct bnxt_napi *bnapi = cpr->bnapi;
1396 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1397 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1398 u8 *data_ptr, agg_bufs;
1399 u16 cp_cons = RING_CMP(*raw_cons);
1401 struct bnxt_tpa_info *tpa_info;
1403 struct sk_buff *skb;
1406 if (unlikely(bnapi->in_reset)) {
1407 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1410 return ERR_PTR(-EBUSY);
1414 tpa_info = &rxr->rx_tpa[agg_id];
1415 data = tpa_info->data;
1416 data_ptr = tpa_info->data_ptr;
1418 len = tpa_info->len;
1419 mapping = tpa_info->mapping;
1421 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1422 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1425 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1426 return ERR_PTR(-EBUSY);
1428 *event |= BNXT_AGG_EVENT;
1429 cp_cons = NEXT_CMP(cp_cons);
1432 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1433 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1434 if (agg_bufs > MAX_SKB_FRAGS)
1435 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1436 agg_bufs, (int)MAX_SKB_FRAGS);
1440 if (len <= bp->rx_copy_thresh) {
1441 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1443 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1448 dma_addr_t new_mapping;
1450 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1452 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1456 tpa_info->data = new_data;
1457 tpa_info->data_ptr = new_data + bp->rx_offset;
1458 tpa_info->mapping = new_mapping;
1460 skb = build_skb(data, 0);
1461 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1462 bp->rx_buf_use_size, bp->rx_dir,
1463 DMA_ATTR_WEAK_ORDERING);
1467 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1470 skb_reserve(skb, bp->rx_offset);
1475 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1477 /* Page reuse already handled by bnxt_rx_pages(). */
1483 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1485 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1486 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1488 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1489 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1490 u16 vlan_proto = tpa_info->metadata >>
1491 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1492 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1494 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1497 skb_checksum_none_assert(skb);
1498 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1499 skb->ip_summed = CHECKSUM_UNNECESSARY;
1501 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1504 if (TPA_END_GRO(tpa_end))
1505 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1510 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1511 struct sk_buff *skb)
1513 if (skb->dev != bp->dev) {
1514 /* this packet belongs to a vf-rep */
1515 bnxt_vf_rep_rx(bp, skb);
1518 skb_record_rx_queue(skb, bnapi->index);
1519 napi_gro_receive(&bnapi->napi, skb);
1522 /* returns the following:
1523 * 1 - 1 packet successfully received
1524 * 0 - successful TPA_START, packet not completed yet
1525 * -EBUSY - completion ring does not have all the agg buffers yet
1526 * -ENOMEM - packet aborted due to out of memory
1527 * -EIO - packet aborted due to hw error indicated in BD
1529 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1530 u32 *raw_cons, u8 *event)
1532 struct bnxt_napi *bnapi = cpr->bnapi;
1533 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1534 struct net_device *dev = bp->dev;
1535 struct rx_cmp *rxcmp;
1536 struct rx_cmp_ext *rxcmp1;
1537 u32 tmp_raw_cons = *raw_cons;
1538 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1539 struct bnxt_sw_rx_bd *rx_buf;
1541 u8 *data_ptr, agg_bufs, cmp_type;
1542 dma_addr_t dma_addr;
1543 struct sk_buff *skb;
1548 rxcmp = (struct rx_cmp *)
1549 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1551 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1552 cp_cons = RING_CMP(tmp_raw_cons);
1553 rxcmp1 = (struct rx_cmp_ext *)
1554 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1556 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1559 cmp_type = RX_CMP_TYPE(rxcmp);
1561 prod = rxr->rx_prod;
1563 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1564 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1565 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1567 *event |= BNXT_RX_EVENT;
1568 goto next_rx_no_prod_no_len;
1570 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1571 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1572 (struct rx_tpa_end_cmp *)rxcmp,
1573 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1580 bnxt_deliver_skb(bp, bnapi, skb);
1583 *event |= BNXT_RX_EVENT;
1584 goto next_rx_no_prod_no_len;
1587 cons = rxcmp->rx_cmp_opaque;
1588 rx_buf = &rxr->rx_buf_ring[cons];
1589 data = rx_buf->data;
1590 data_ptr = rx_buf->data_ptr;
1591 if (unlikely(cons != rxr->rx_next_cons)) {
1592 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1594 bnxt_sched_reset(bp, rxr);
1599 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1600 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1603 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1606 cp_cons = NEXT_CMP(cp_cons);
1607 *event |= BNXT_AGG_EVENT;
1609 *event |= BNXT_RX_EVENT;
1611 rx_buf->data = NULL;
1612 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1613 bnxt_reuse_rx_data(rxr, cons, data);
1615 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1621 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1622 dma_addr = rx_buf->mapping;
1624 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1629 if (len <= bp->rx_copy_thresh) {
1630 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1631 bnxt_reuse_rx_data(rxr, cons, data);
1639 if (rx_buf->data_ptr == data_ptr)
1640 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1643 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1652 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1659 if (RX_CMP_HASH_VALID(rxcmp)) {
1660 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1661 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1663 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1664 if (hash_type != 1 && hash_type != 3)
1665 type = PKT_HASH_TYPE_L3;
1666 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1669 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1670 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1672 if ((rxcmp1->rx_cmp_flags2 &
1673 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1674 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1675 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1676 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1677 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1679 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1682 skb_checksum_none_assert(skb);
1683 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1684 if (dev->features & NETIF_F_RXCSUM) {
1685 skb->ip_summed = CHECKSUM_UNNECESSARY;
1686 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1689 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1690 if (dev->features & NETIF_F_RXCSUM)
1691 bnapi->cp_ring.rx_l4_csum_errors++;
1695 bnxt_deliver_skb(bp, bnapi, skb);
1699 rxr->rx_prod = NEXT_RX(prod);
1700 rxr->rx_next_cons = NEXT_RX(cons);
1702 cpr->rx_packets += 1;
1703 cpr->rx_bytes += len;
1705 next_rx_no_prod_no_len:
1706 *raw_cons = tmp_raw_cons;
1711 /* In netpoll mode, if we are using a combined completion ring, we need to
1712 * discard the rx packets and recycle the buffers.
1714 static int bnxt_force_rx_discard(struct bnxt *bp,
1715 struct bnxt_cp_ring_info *cpr,
1716 u32 *raw_cons, u8 *event)
1718 u32 tmp_raw_cons = *raw_cons;
1719 struct rx_cmp_ext *rxcmp1;
1720 struct rx_cmp *rxcmp;
1724 cp_cons = RING_CMP(tmp_raw_cons);
1725 rxcmp = (struct rx_cmp *)
1726 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1728 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1729 cp_cons = RING_CMP(tmp_raw_cons);
1730 rxcmp1 = (struct rx_cmp_ext *)
1731 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1733 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1736 cmp_type = RX_CMP_TYPE(rxcmp);
1737 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1738 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1739 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1740 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1741 struct rx_tpa_end_cmp_ext *tpa_end1;
1743 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1744 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1745 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1747 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1750 #define BNXT_GET_EVENT_PORT(data) \
1752 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1754 static int bnxt_async_event_process(struct bnxt *bp,
1755 struct hwrm_async_event_cmpl *cmpl)
1757 u16 event_id = le16_to_cpu(cmpl->event_id);
1759 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1761 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1762 u32 data1 = le32_to_cpu(cmpl->event_data1);
1763 struct bnxt_link_info *link_info = &bp->link_info;
1766 goto async_event_process_exit;
1768 /* print unsupported speed warning in forced speed mode only */
1769 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1770 (data1 & 0x20000)) {
1771 u16 fw_speed = link_info->force_link_speed;
1772 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1774 if (speed != SPEED_UNKNOWN)
1775 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1778 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1781 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1782 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1784 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1785 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1787 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1788 u32 data1 = le32_to_cpu(cmpl->event_data1);
1789 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1794 if (bp->pf.port_id != port_id)
1797 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1800 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1802 goto async_event_process_exit;
1803 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1806 goto async_event_process_exit;
1808 bnxt_queue_sp_work(bp);
1809 async_event_process_exit:
1810 bnxt_ulp_async_events(bp, cmpl);
1814 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1816 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1817 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1818 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1819 (struct hwrm_fwd_req_cmpl *)txcmp;
1821 switch (cmpl_type) {
1822 case CMPL_BASE_TYPE_HWRM_DONE:
1823 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1824 if (seq_id == bp->hwrm_intr_seq_id)
1825 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1827 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1830 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1831 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1833 if ((vf_id < bp->pf.first_vf_id) ||
1834 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1835 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1840 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1841 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1842 bnxt_queue_sp_work(bp);
1845 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1846 bnxt_async_event_process(bp,
1847 (struct hwrm_async_event_cmpl *)txcmp);
1856 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1858 struct bnxt_napi *bnapi = dev_instance;
1859 struct bnxt *bp = bnapi->bp;
1860 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1861 u32 cons = RING_CMP(cpr->cp_raw_cons);
1864 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1865 napi_schedule(&bnapi->napi);
1869 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1871 u32 raw_cons = cpr->cp_raw_cons;
1872 u16 cons = RING_CMP(raw_cons);
1873 struct tx_cmp *txcmp;
1875 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1877 return TX_CMP_VALID(txcmp, raw_cons);
1880 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1882 struct bnxt_napi *bnapi = dev_instance;
1883 struct bnxt *bp = bnapi->bp;
1884 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1885 u32 cons = RING_CMP(cpr->cp_raw_cons);
1888 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1890 if (!bnxt_has_work(bp, cpr)) {
1891 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1892 /* return if erroneous interrupt */
1893 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1897 /* disable ring IRQ */
1898 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1900 /* Return here if interrupt is shared and is disabled. */
1901 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1904 napi_schedule(&bnapi->napi);
1908 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1911 struct bnxt_napi *bnapi = cpr->bnapi;
1912 u32 raw_cons = cpr->cp_raw_cons;
1917 struct tx_cmp *txcmp;
1919 cpr->has_more_work = 0;
1923 cons = RING_CMP(raw_cons);
1924 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1926 if (!TX_CMP_VALID(txcmp, raw_cons))
1929 /* The valid test of the entry must be done first before
1930 * reading any further.
1933 cpr->had_work_done = 1;
1934 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1936 /* return full budget so NAPI will complete. */
1937 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1939 raw_cons = NEXT_RAW_CMP(raw_cons);
1941 cpr->has_more_work = 1;
1944 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1946 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1948 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1950 if (likely(rc >= 0))
1952 /* Increment rx_pkts when rc is -ENOMEM to count towards
1953 * the NAPI budget. Otherwise, we may potentially loop
1954 * here forever if we consistently cannot allocate
1957 else if (rc == -ENOMEM && budget)
1959 else if (rc == -EBUSY) /* partial completion */
1961 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1962 CMPL_BASE_TYPE_HWRM_DONE) ||
1963 (TX_CMP_TYPE(txcmp) ==
1964 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1965 (TX_CMP_TYPE(txcmp) ==
1966 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1967 bnxt_hwrm_handler(bp, txcmp);
1969 raw_cons = NEXT_RAW_CMP(raw_cons);
1971 if (rx_pkts && rx_pkts == budget) {
1972 cpr->has_more_work = 1;
1977 if (event & BNXT_TX_EVENT) {
1978 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1979 u16 prod = txr->tx_prod;
1981 /* Sync BD data before updating doorbell */
1984 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
1987 cpr->cp_raw_cons = raw_cons;
1988 bnapi->tx_pkts += tx_pkts;
1989 bnapi->events |= event;
1993 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
1995 if (bnapi->tx_pkts) {
1996 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2000 if (bnapi->events & BNXT_RX_EVENT) {
2001 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2003 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2004 if (bnapi->events & BNXT_AGG_EVENT)
2005 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2010 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2013 struct bnxt_napi *bnapi = cpr->bnapi;
2016 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2018 /* ACK completion ring before freeing tx ring and producing new
2019 * buffers in rx/agg rings to prevent overflowing the completion
2022 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2024 __bnxt_poll_work_done(bp, bnapi);
2028 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2030 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2031 struct bnxt *bp = bnapi->bp;
2032 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2033 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2034 struct tx_cmp *txcmp;
2035 struct rx_cmp_ext *rxcmp1;
2036 u32 cp_cons, tmp_raw_cons;
2037 u32 raw_cons = cpr->cp_raw_cons;
2044 cp_cons = RING_CMP(raw_cons);
2045 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2047 if (!TX_CMP_VALID(txcmp, raw_cons))
2050 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2051 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2052 cp_cons = RING_CMP(tmp_raw_cons);
2053 rxcmp1 = (struct rx_cmp_ext *)
2054 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2056 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2059 /* force an error to recycle the buffer */
2060 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2061 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2063 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2064 if (likely(rc == -EIO) && budget)
2066 else if (rc == -EBUSY) /* partial completion */
2068 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2069 CMPL_BASE_TYPE_HWRM_DONE)) {
2070 bnxt_hwrm_handler(bp, txcmp);
2073 "Invalid completion received on special ring\n");
2075 raw_cons = NEXT_RAW_CMP(raw_cons);
2077 if (rx_pkts == budget)
2081 cpr->cp_raw_cons = raw_cons;
2082 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2083 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2085 if (event & BNXT_AGG_EVENT)
2086 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2088 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2089 napi_complete_done(napi, rx_pkts);
2090 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2095 static int bnxt_poll(struct napi_struct *napi, int budget)
2097 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2098 struct bnxt *bp = bnapi->bp;
2099 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2103 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2105 if (work_done >= budget) {
2107 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2111 if (!bnxt_has_work(bp, cpr)) {
2112 if (napi_complete_done(napi, work_done))
2113 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2117 if (bp->flags & BNXT_FLAG_DIM) {
2118 struct net_dim_sample dim_sample;
2120 net_dim_sample(cpr->event_ctr,
2124 net_dim(&cpr->dim, dim_sample);
2130 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2132 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2133 int i, work_done = 0;
2135 for (i = 0; i < 2; i++) {
2136 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2139 work_done += __bnxt_poll_work(bp, cpr2,
2140 budget - work_done);
2141 cpr->has_more_work |= cpr2->has_more_work;
2147 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2148 u64 dbr_type, bool all)
2150 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2153 for (i = 0; i < 2; i++) {
2154 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2155 struct bnxt_db_info *db;
2157 if (cpr2 && (all || cpr2->had_work_done)) {
2159 writeq(db->db_key64 | dbr_type |
2160 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2161 cpr2->had_work_done = 0;
2164 __bnxt_poll_work_done(bp, bnapi);
2167 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2169 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2170 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2171 u32 raw_cons = cpr->cp_raw_cons;
2172 struct bnxt *bp = bnapi->bp;
2173 struct nqe_cn *nqcmp;
2177 if (cpr->has_more_work) {
2178 cpr->has_more_work = 0;
2179 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2180 if (cpr->has_more_work) {
2181 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2184 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2185 if (napi_complete_done(napi, work_done))
2186 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2190 cons = RING_CMP(raw_cons);
2191 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2193 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2194 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2196 cpr->cp_raw_cons = raw_cons;
2197 if (napi_complete_done(napi, work_done))
2198 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2203 /* The valid test of the entry must be done first before
2204 * reading any further.
2208 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2209 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2210 struct bnxt_cp_ring_info *cpr2;
2212 cpr2 = cpr->cp_ring_arr[idx];
2213 work_done += __bnxt_poll_work(bp, cpr2,
2214 budget - work_done);
2215 cpr->has_more_work = cpr2->has_more_work;
2217 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2219 raw_cons = NEXT_RAW_CMP(raw_cons);
2220 if (cpr->has_more_work)
2223 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2224 cpr->cp_raw_cons = raw_cons;
2228 static void bnxt_free_tx_skbs(struct bnxt *bp)
2231 struct pci_dev *pdev = bp->pdev;
2236 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2237 for (i = 0; i < bp->tx_nr_rings; i++) {
2238 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2241 for (j = 0; j < max_idx;) {
2242 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2243 struct sk_buff *skb = tx_buf->skb;
2253 if (tx_buf->is_push) {
2259 dma_unmap_single(&pdev->dev,
2260 dma_unmap_addr(tx_buf, mapping),
2264 last = tx_buf->nr_frags;
2266 for (k = 0; k < last; k++, j++) {
2267 int ring_idx = j & bp->tx_ring_mask;
2268 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2270 tx_buf = &txr->tx_buf_ring[ring_idx];
2273 dma_unmap_addr(tx_buf, mapping),
2274 skb_frag_size(frag), PCI_DMA_TODEVICE);
2278 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2282 static void bnxt_free_rx_skbs(struct bnxt *bp)
2284 int i, max_idx, max_agg_idx;
2285 struct pci_dev *pdev = bp->pdev;
2290 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2291 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2292 for (i = 0; i < bp->rx_nr_rings; i++) {
2293 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2297 for (j = 0; j < MAX_TPA; j++) {
2298 struct bnxt_tpa_info *tpa_info =
2300 u8 *data = tpa_info->data;
2305 dma_unmap_single_attrs(&pdev->dev,
2307 bp->rx_buf_use_size,
2309 DMA_ATTR_WEAK_ORDERING);
2311 tpa_info->data = NULL;
2317 for (j = 0; j < max_idx; j++) {
2318 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2319 dma_addr_t mapping = rx_buf->mapping;
2320 void *data = rx_buf->data;
2325 rx_buf->data = NULL;
2327 if (BNXT_RX_PAGE_MODE(bp)) {
2328 mapping -= bp->rx_dma_offset;
2329 dma_unmap_page_attrs(&pdev->dev, mapping,
2330 PAGE_SIZE, bp->rx_dir,
2331 DMA_ATTR_WEAK_ORDERING);
2334 dma_unmap_single_attrs(&pdev->dev, mapping,
2335 bp->rx_buf_use_size,
2337 DMA_ATTR_WEAK_ORDERING);
2342 for (j = 0; j < max_agg_idx; j++) {
2343 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2344 &rxr->rx_agg_ring[j];
2345 struct page *page = rx_agg_buf->page;
2350 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2353 DMA_ATTR_WEAK_ORDERING);
2355 rx_agg_buf->page = NULL;
2356 __clear_bit(j, rxr->rx_agg_bmap);
2361 __free_page(rxr->rx_page);
2362 rxr->rx_page = NULL;
2367 static void bnxt_free_skbs(struct bnxt *bp)
2369 bnxt_free_tx_skbs(bp);
2370 bnxt_free_rx_skbs(bp);
2373 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2375 struct pci_dev *pdev = bp->pdev;
2378 for (i = 0; i < rmem->nr_pages; i++) {
2379 if (!rmem->pg_arr[i])
2382 dma_free_coherent(&pdev->dev, rmem->page_size,
2383 rmem->pg_arr[i], rmem->dma_arr[i]);
2385 rmem->pg_arr[i] = NULL;
2388 size_t pg_tbl_size = rmem->nr_pages * 8;
2390 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2391 pg_tbl_size = rmem->page_size;
2392 dma_free_coherent(&pdev->dev, pg_tbl_size,
2393 rmem->pg_tbl, rmem->pg_tbl_map);
2394 rmem->pg_tbl = NULL;
2396 if (rmem->vmem_size && *rmem->vmem) {
2402 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2404 struct pci_dev *pdev = bp->pdev;
2408 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2409 valid_bit = PTU_PTE_VALID;
2410 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2411 size_t pg_tbl_size = rmem->nr_pages * 8;
2413 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2414 pg_tbl_size = rmem->page_size;
2415 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2422 for (i = 0; i < rmem->nr_pages; i++) {
2423 u64 extra_bits = valid_bit;
2425 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2429 if (!rmem->pg_arr[i])
2432 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2433 if (i == rmem->nr_pages - 2 &&
2434 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2435 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2436 else if (i == rmem->nr_pages - 1 &&
2437 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2438 extra_bits |= PTU_PTE_LAST;
2440 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2444 if (rmem->vmem_size) {
2445 *rmem->vmem = vzalloc(rmem->vmem_size);
2452 static void bnxt_free_rx_rings(struct bnxt *bp)
2459 for (i = 0; i < bp->rx_nr_rings; i++) {
2460 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2461 struct bnxt_ring_struct *ring;
2464 bpf_prog_put(rxr->xdp_prog);
2466 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2467 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2472 kfree(rxr->rx_agg_bmap);
2473 rxr->rx_agg_bmap = NULL;
2475 ring = &rxr->rx_ring_struct;
2476 bnxt_free_ring(bp, &ring->ring_mem);
2478 ring = &rxr->rx_agg_ring_struct;
2479 bnxt_free_ring(bp, &ring->ring_mem);
2483 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2485 int i, rc, agg_rings = 0, tpa_rings = 0;
2490 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2493 if (bp->flags & BNXT_FLAG_TPA)
2496 for (i = 0; i < bp->rx_nr_rings; i++) {
2497 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2498 struct bnxt_ring_struct *ring;
2500 ring = &rxr->rx_ring_struct;
2502 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2506 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2514 ring = &rxr->rx_agg_ring_struct;
2515 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2520 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2521 mem_size = rxr->rx_agg_bmap_size / 8;
2522 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2523 if (!rxr->rx_agg_bmap)
2527 rxr->rx_tpa = kcalloc(MAX_TPA,
2528 sizeof(struct bnxt_tpa_info),
2538 static void bnxt_free_tx_rings(struct bnxt *bp)
2541 struct pci_dev *pdev = bp->pdev;
2546 for (i = 0; i < bp->tx_nr_rings; i++) {
2547 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2548 struct bnxt_ring_struct *ring;
2551 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2552 txr->tx_push, txr->tx_push_mapping);
2553 txr->tx_push = NULL;
2556 ring = &txr->tx_ring_struct;
2558 bnxt_free_ring(bp, &ring->ring_mem);
2562 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2565 struct pci_dev *pdev = bp->pdev;
2567 bp->tx_push_size = 0;
2568 if (bp->tx_push_thresh) {
2571 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2572 bp->tx_push_thresh);
2574 if (push_size > 256) {
2576 bp->tx_push_thresh = 0;
2579 bp->tx_push_size = push_size;
2582 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2583 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2584 struct bnxt_ring_struct *ring;
2587 ring = &txr->tx_ring_struct;
2589 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2593 ring->grp_idx = txr->bnapi->index;
2594 if (bp->tx_push_size) {
2597 /* One pre-allocated DMA buffer to backup
2600 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2602 &txr->tx_push_mapping,
2608 mapping = txr->tx_push_mapping +
2609 sizeof(struct tx_push_bd);
2610 txr->data_mapping = cpu_to_le64(mapping);
2612 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2614 qidx = bp->tc_to_qidx[j];
2615 ring->queue_id = bp->q_info[qidx].queue_id;
2616 if (i < bp->tx_nr_rings_xdp)
2618 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2624 static void bnxt_free_cp_rings(struct bnxt *bp)
2631 for (i = 0; i < bp->cp_nr_rings; i++) {
2632 struct bnxt_napi *bnapi = bp->bnapi[i];
2633 struct bnxt_cp_ring_info *cpr;
2634 struct bnxt_ring_struct *ring;
2640 cpr = &bnapi->cp_ring;
2641 ring = &cpr->cp_ring_struct;
2643 bnxt_free_ring(bp, &ring->ring_mem);
2645 for (j = 0; j < 2; j++) {
2646 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2649 ring = &cpr2->cp_ring_struct;
2650 bnxt_free_ring(bp, &ring->ring_mem);
2652 cpr->cp_ring_arr[j] = NULL;
2658 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2660 struct bnxt_ring_mem_info *rmem;
2661 struct bnxt_ring_struct *ring;
2662 struct bnxt_cp_ring_info *cpr;
2665 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2669 ring = &cpr->cp_ring_struct;
2670 rmem = &ring->ring_mem;
2671 rmem->nr_pages = bp->cp_nr_pages;
2672 rmem->page_size = HW_CMPD_RING_SIZE;
2673 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2674 rmem->dma_arr = cpr->cp_desc_mapping;
2675 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2676 rc = bnxt_alloc_ring(bp, rmem);
2678 bnxt_free_ring(bp, rmem);
2685 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2687 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2688 int i, rc, ulp_base_vec, ulp_msix;
2690 ulp_msix = bnxt_get_ulp_msix_num(bp);
2691 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2692 for (i = 0; i < bp->cp_nr_rings; i++) {
2693 struct bnxt_napi *bnapi = bp->bnapi[i];
2694 struct bnxt_cp_ring_info *cpr;
2695 struct bnxt_ring_struct *ring;
2700 cpr = &bnapi->cp_ring;
2702 ring = &cpr->cp_ring_struct;
2704 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2708 if (ulp_msix && i >= ulp_base_vec)
2709 ring->map_idx = i + ulp_msix;
2713 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2716 if (i < bp->rx_nr_rings) {
2717 struct bnxt_cp_ring_info *cpr2 =
2718 bnxt_alloc_cp_sub_ring(bp);
2720 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2723 cpr2->bnapi = bnapi;
2725 if ((sh && i < bp->tx_nr_rings) ||
2726 (!sh && i >= bp->rx_nr_rings)) {
2727 struct bnxt_cp_ring_info *cpr2 =
2728 bnxt_alloc_cp_sub_ring(bp);
2730 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2733 cpr2->bnapi = bnapi;
2739 static void bnxt_init_ring_struct(struct bnxt *bp)
2743 for (i = 0; i < bp->cp_nr_rings; i++) {
2744 struct bnxt_napi *bnapi = bp->bnapi[i];
2745 struct bnxt_ring_mem_info *rmem;
2746 struct bnxt_cp_ring_info *cpr;
2747 struct bnxt_rx_ring_info *rxr;
2748 struct bnxt_tx_ring_info *txr;
2749 struct bnxt_ring_struct *ring;
2754 cpr = &bnapi->cp_ring;
2755 ring = &cpr->cp_ring_struct;
2756 rmem = &ring->ring_mem;
2757 rmem->nr_pages = bp->cp_nr_pages;
2758 rmem->page_size = HW_CMPD_RING_SIZE;
2759 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2760 rmem->dma_arr = cpr->cp_desc_mapping;
2761 rmem->vmem_size = 0;
2763 rxr = bnapi->rx_ring;
2767 ring = &rxr->rx_ring_struct;
2768 rmem = &ring->ring_mem;
2769 rmem->nr_pages = bp->rx_nr_pages;
2770 rmem->page_size = HW_RXBD_RING_SIZE;
2771 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2772 rmem->dma_arr = rxr->rx_desc_mapping;
2773 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2774 rmem->vmem = (void **)&rxr->rx_buf_ring;
2776 ring = &rxr->rx_agg_ring_struct;
2777 rmem = &ring->ring_mem;
2778 rmem->nr_pages = bp->rx_agg_nr_pages;
2779 rmem->page_size = HW_RXBD_RING_SIZE;
2780 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2781 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2782 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2783 rmem->vmem = (void **)&rxr->rx_agg_ring;
2786 txr = bnapi->tx_ring;
2790 ring = &txr->tx_ring_struct;
2791 rmem = &ring->ring_mem;
2792 rmem->nr_pages = bp->tx_nr_pages;
2793 rmem->page_size = HW_RXBD_RING_SIZE;
2794 rmem->pg_arr = (void **)txr->tx_desc_ring;
2795 rmem->dma_arr = txr->tx_desc_mapping;
2796 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2797 rmem->vmem = (void **)&txr->tx_buf_ring;
2801 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2805 struct rx_bd **rx_buf_ring;
2807 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2808 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2812 rxbd = rx_buf_ring[i];
2816 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2817 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2818 rxbd->rx_bd_opaque = prod;
2823 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2825 struct net_device *dev = bp->dev;
2826 struct bnxt_rx_ring_info *rxr;
2827 struct bnxt_ring_struct *ring;
2831 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2832 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2834 if (NET_IP_ALIGN == 2)
2835 type |= RX_BD_FLAGS_SOP;
2837 rxr = &bp->rx_ring[ring_nr];
2838 ring = &rxr->rx_ring_struct;
2839 bnxt_init_rxbd_pages(ring, type);
2841 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2842 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2843 if (IS_ERR(rxr->xdp_prog)) {
2844 int rc = PTR_ERR(rxr->xdp_prog);
2846 rxr->xdp_prog = NULL;
2850 prod = rxr->rx_prod;
2851 for (i = 0; i < bp->rx_ring_size; i++) {
2852 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2853 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2854 ring_nr, i, bp->rx_ring_size);
2857 prod = NEXT_RX(prod);
2859 rxr->rx_prod = prod;
2860 ring->fw_ring_id = INVALID_HW_RING_ID;
2862 ring = &rxr->rx_agg_ring_struct;
2863 ring->fw_ring_id = INVALID_HW_RING_ID;
2865 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2868 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2869 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2871 bnxt_init_rxbd_pages(ring, type);
2873 prod = rxr->rx_agg_prod;
2874 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2875 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2876 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2877 ring_nr, i, bp->rx_ring_size);
2880 prod = NEXT_RX_AGG(prod);
2882 rxr->rx_agg_prod = prod;
2884 if (bp->flags & BNXT_FLAG_TPA) {
2889 for (i = 0; i < MAX_TPA; i++) {
2890 data = __bnxt_alloc_rx_data(bp, &mapping,
2895 rxr->rx_tpa[i].data = data;
2896 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2897 rxr->rx_tpa[i].mapping = mapping;
2900 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2908 static void bnxt_init_cp_rings(struct bnxt *bp)
2912 for (i = 0; i < bp->cp_nr_rings; i++) {
2913 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2914 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2916 ring->fw_ring_id = INVALID_HW_RING_ID;
2917 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2918 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2919 for (j = 0; j < 2; j++) {
2920 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2925 ring = &cpr2->cp_ring_struct;
2926 ring->fw_ring_id = INVALID_HW_RING_ID;
2927 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2928 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2933 static int bnxt_init_rx_rings(struct bnxt *bp)
2937 if (BNXT_RX_PAGE_MODE(bp)) {
2938 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2939 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2941 bp->rx_offset = BNXT_RX_OFFSET;
2942 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2945 for (i = 0; i < bp->rx_nr_rings; i++) {
2946 rc = bnxt_init_one_rx_ring(bp, i);
2954 static int bnxt_init_tx_rings(struct bnxt *bp)
2958 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2961 for (i = 0; i < bp->tx_nr_rings; i++) {
2962 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2963 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2965 ring->fw_ring_id = INVALID_HW_RING_ID;
2971 static void bnxt_free_ring_grps(struct bnxt *bp)
2973 kfree(bp->grp_info);
2974 bp->grp_info = NULL;
2977 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2982 bp->grp_info = kcalloc(bp->cp_nr_rings,
2983 sizeof(struct bnxt_ring_grp_info),
2988 for (i = 0; i < bp->cp_nr_rings; i++) {
2990 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2991 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2992 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2993 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2994 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2999 static void bnxt_free_vnics(struct bnxt *bp)
3001 kfree(bp->vnic_info);
3002 bp->vnic_info = NULL;
3006 static int bnxt_alloc_vnics(struct bnxt *bp)
3010 #ifdef CONFIG_RFS_ACCEL
3011 if (bp->flags & BNXT_FLAG_RFS)
3012 num_vnics += bp->rx_nr_rings;
3015 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3018 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3023 bp->nr_vnics = num_vnics;
3027 static void bnxt_init_vnics(struct bnxt *bp)
3031 for (i = 0; i < bp->nr_vnics; i++) {
3032 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3035 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3036 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3037 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3039 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3041 if (bp->vnic_info[i].rss_hash_key) {
3043 prandom_bytes(vnic->rss_hash_key,
3046 memcpy(vnic->rss_hash_key,
3047 bp->vnic_info[0].rss_hash_key,
3053 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3057 pages = ring_size / desc_per_pg;
3064 while (pages & (pages - 1))
3070 void bnxt_set_tpa_flags(struct bnxt *bp)
3072 bp->flags &= ~BNXT_FLAG_TPA;
3073 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3075 if (bp->dev->features & NETIF_F_LRO)
3076 bp->flags |= BNXT_FLAG_LRO;
3077 else if (bp->dev->features & NETIF_F_GRO_HW)
3078 bp->flags |= BNXT_FLAG_GRO;
3081 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3084 void bnxt_set_ring_params(struct bnxt *bp)
3086 u32 ring_size, rx_size, rx_space;
3087 u32 agg_factor = 0, agg_ring_size = 0;
3089 /* 8 for CRC and VLAN */
3090 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3092 rx_space = rx_size + NET_SKB_PAD +
3093 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3095 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3096 ring_size = bp->rx_ring_size;
3097 bp->rx_agg_ring_size = 0;
3098 bp->rx_agg_nr_pages = 0;
3100 if (bp->flags & BNXT_FLAG_TPA)
3101 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3103 bp->flags &= ~BNXT_FLAG_JUMBO;
3104 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3107 bp->flags |= BNXT_FLAG_JUMBO;
3108 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3109 if (jumbo_factor > agg_factor)
3110 agg_factor = jumbo_factor;
3112 agg_ring_size = ring_size * agg_factor;
3114 if (agg_ring_size) {
3115 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3117 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3118 u32 tmp = agg_ring_size;
3120 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3121 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3122 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3123 tmp, agg_ring_size);
3125 bp->rx_agg_ring_size = agg_ring_size;
3126 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3127 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3128 rx_space = rx_size + NET_SKB_PAD +
3129 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3132 bp->rx_buf_use_size = rx_size;
3133 bp->rx_buf_size = rx_space;
3135 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3136 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3138 ring_size = bp->tx_ring_size;
3139 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3140 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3142 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3143 bp->cp_ring_size = ring_size;
3145 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3146 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3147 bp->cp_nr_pages = MAX_CP_PAGES;
3148 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3149 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3150 ring_size, bp->cp_ring_size);
3152 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3153 bp->cp_ring_mask = bp->cp_bit - 1;
3156 /* Changing allocation mode of RX rings.
3157 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3159 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3162 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3165 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3166 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3167 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3168 bp->rx_dir = DMA_BIDIRECTIONAL;
3169 bp->rx_skb_func = bnxt_rx_page_skb;
3170 /* Disable LRO or GRO_HW */
3171 netdev_update_features(bp->dev);
3173 bp->dev->max_mtu = bp->max_mtu;
3174 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3175 bp->rx_dir = DMA_FROM_DEVICE;
3176 bp->rx_skb_func = bnxt_rx_skb;
3181 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3184 struct bnxt_vnic_info *vnic;
3185 struct pci_dev *pdev = bp->pdev;
3190 for (i = 0; i < bp->nr_vnics; i++) {
3191 vnic = &bp->vnic_info[i];
3193 kfree(vnic->fw_grp_ids);
3194 vnic->fw_grp_ids = NULL;
3196 kfree(vnic->uc_list);
3197 vnic->uc_list = NULL;
3199 if (vnic->mc_list) {
3200 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3201 vnic->mc_list, vnic->mc_list_mapping);
3202 vnic->mc_list = NULL;
3205 if (vnic->rss_table) {
3206 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3208 vnic->rss_table_dma_addr);
3209 vnic->rss_table = NULL;
3212 vnic->rss_hash_key = NULL;
3217 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3219 int i, rc = 0, size;
3220 struct bnxt_vnic_info *vnic;
3221 struct pci_dev *pdev = bp->pdev;
3224 for (i = 0; i < bp->nr_vnics; i++) {
3225 vnic = &bp->vnic_info[i];
3227 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3228 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3231 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3232 if (!vnic->uc_list) {
3239 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3240 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3242 dma_alloc_coherent(&pdev->dev,
3244 &vnic->mc_list_mapping,
3246 if (!vnic->mc_list) {
3252 if (bp->flags & BNXT_FLAG_CHIP_P5)
3253 goto vnic_skip_grps;
3255 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3256 max_rings = bp->rx_nr_rings;
3260 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3261 if (!vnic->fw_grp_ids) {
3266 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3267 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3270 /* Allocate rss table and hash key */
3271 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3272 &vnic->rss_table_dma_addr,
3274 if (!vnic->rss_table) {
3279 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3281 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3282 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3290 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3292 struct pci_dev *pdev = bp->pdev;
3294 if (bp->hwrm_cmd_resp_addr) {
3295 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3296 bp->hwrm_cmd_resp_dma_addr);
3297 bp->hwrm_cmd_resp_addr = NULL;
3300 if (bp->hwrm_cmd_kong_resp_addr) {
3301 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3302 bp->hwrm_cmd_kong_resp_addr,
3303 bp->hwrm_cmd_kong_resp_dma_addr);
3304 bp->hwrm_cmd_kong_resp_addr = NULL;
3308 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3310 struct pci_dev *pdev = bp->pdev;
3312 bp->hwrm_cmd_kong_resp_addr =
3313 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3314 &bp->hwrm_cmd_kong_resp_dma_addr,
3316 if (!bp->hwrm_cmd_kong_resp_addr)
3322 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3324 struct pci_dev *pdev = bp->pdev;
3326 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3327 &bp->hwrm_cmd_resp_dma_addr,
3329 if (!bp->hwrm_cmd_resp_addr)
3335 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3337 if (bp->hwrm_short_cmd_req_addr) {
3338 struct pci_dev *pdev = bp->pdev;
3340 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3341 bp->hwrm_short_cmd_req_addr,
3342 bp->hwrm_short_cmd_req_dma_addr);
3343 bp->hwrm_short_cmd_req_addr = NULL;
3347 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3349 struct pci_dev *pdev = bp->pdev;
3351 bp->hwrm_short_cmd_req_addr =
3352 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3353 &bp->hwrm_short_cmd_req_dma_addr,
3355 if (!bp->hwrm_short_cmd_req_addr)
3361 static void bnxt_free_port_stats(struct bnxt *bp)
3363 struct pci_dev *pdev = bp->pdev;
3365 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3366 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3368 if (bp->hw_rx_port_stats) {
3369 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3370 bp->hw_rx_port_stats,
3371 bp->hw_rx_port_stats_map);
3372 bp->hw_rx_port_stats = NULL;
3375 if (bp->hw_tx_port_stats_ext) {
3376 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3377 bp->hw_tx_port_stats_ext,
3378 bp->hw_tx_port_stats_ext_map);
3379 bp->hw_tx_port_stats_ext = NULL;
3382 if (bp->hw_rx_port_stats_ext) {
3383 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3384 bp->hw_rx_port_stats_ext,
3385 bp->hw_rx_port_stats_ext_map);
3386 bp->hw_rx_port_stats_ext = NULL;
3390 static void bnxt_free_ring_stats(struct bnxt *bp)
3392 struct pci_dev *pdev = bp->pdev;
3398 size = sizeof(struct ctx_hw_stats);
3400 for (i = 0; i < bp->cp_nr_rings; i++) {
3401 struct bnxt_napi *bnapi = bp->bnapi[i];
3402 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3404 if (cpr->hw_stats) {
3405 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3407 cpr->hw_stats = NULL;
3412 static int bnxt_alloc_stats(struct bnxt *bp)
3415 struct pci_dev *pdev = bp->pdev;
3417 size = sizeof(struct ctx_hw_stats);
3419 for (i = 0; i < bp->cp_nr_rings; i++) {
3420 struct bnxt_napi *bnapi = bp->bnapi[i];
3421 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3423 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3429 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3432 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3433 if (bp->hw_rx_port_stats)
3434 goto alloc_ext_stats;
3436 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3437 sizeof(struct tx_port_stats) + 1024;
3439 bp->hw_rx_port_stats =
3440 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3441 &bp->hw_rx_port_stats_map,
3443 if (!bp->hw_rx_port_stats)
3446 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3448 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3449 sizeof(struct rx_port_stats) + 512;
3450 bp->flags |= BNXT_FLAG_PORT_STATS;
3453 /* Display extended statistics only if FW supports it */
3454 if (bp->hwrm_spec_code < 0x10804 ||
3455 bp->hwrm_spec_code == 0x10900)
3458 if (bp->hw_rx_port_stats_ext)
3459 goto alloc_tx_ext_stats;
3461 bp->hw_rx_port_stats_ext =
3462 dma_alloc_coherent(&pdev->dev,
3463 sizeof(struct rx_port_stats_ext),
3464 &bp->hw_rx_port_stats_ext_map,
3466 if (!bp->hw_rx_port_stats_ext)
3470 if (bp->hw_tx_port_stats_ext)
3473 if (bp->hwrm_spec_code >= 0x10902) {
3474 bp->hw_tx_port_stats_ext =
3475 dma_alloc_coherent(&pdev->dev,
3476 sizeof(struct tx_port_stats_ext),
3477 &bp->hw_tx_port_stats_ext_map,
3480 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3485 static void bnxt_clear_ring_indices(struct bnxt *bp)
3492 for (i = 0; i < bp->cp_nr_rings; i++) {
3493 struct bnxt_napi *bnapi = bp->bnapi[i];
3494 struct bnxt_cp_ring_info *cpr;
3495 struct bnxt_rx_ring_info *rxr;
3496 struct bnxt_tx_ring_info *txr;
3501 cpr = &bnapi->cp_ring;
3502 cpr->cp_raw_cons = 0;
3504 txr = bnapi->tx_ring;
3510 rxr = bnapi->rx_ring;
3513 rxr->rx_agg_prod = 0;
3514 rxr->rx_sw_agg_prod = 0;
3515 rxr->rx_next_cons = 0;
3520 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3522 #ifdef CONFIG_RFS_ACCEL
3525 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3526 * safe to delete the hash table.
3528 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3529 struct hlist_head *head;
3530 struct hlist_node *tmp;
3531 struct bnxt_ntuple_filter *fltr;
3533 head = &bp->ntp_fltr_hash_tbl[i];
3534 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3535 hlist_del(&fltr->hash);
3540 kfree(bp->ntp_fltr_bmap);
3541 bp->ntp_fltr_bmap = NULL;
3543 bp->ntp_fltr_count = 0;
3547 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3549 #ifdef CONFIG_RFS_ACCEL
3552 if (!(bp->flags & BNXT_FLAG_RFS))
3555 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3556 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3558 bp->ntp_fltr_count = 0;
3559 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3563 if (!bp->ntp_fltr_bmap)
3572 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3574 bnxt_free_vnic_attributes(bp);
3575 bnxt_free_tx_rings(bp);
3576 bnxt_free_rx_rings(bp);
3577 bnxt_free_cp_rings(bp);
3578 bnxt_free_ntp_fltrs(bp, irq_re_init);
3580 bnxt_free_ring_stats(bp);
3581 bnxt_free_ring_grps(bp);
3582 bnxt_free_vnics(bp);
3583 kfree(bp->tx_ring_map);
3584 bp->tx_ring_map = NULL;
3592 bnxt_clear_ring_indices(bp);
3596 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3598 int i, j, rc, size, arr_size;
3602 /* Allocate bnapi mem pointer array and mem block for
3605 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3607 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3608 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3614 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3615 bp->bnapi[i] = bnapi;
3616 bp->bnapi[i]->index = i;
3617 bp->bnapi[i]->bp = bp;
3618 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3619 struct bnxt_cp_ring_info *cpr =
3620 &bp->bnapi[i]->cp_ring;
3622 cpr->cp_ring_struct.ring_mem.flags =
3623 BNXT_RMEM_RING_PTE_FLAG;
3627 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3628 sizeof(struct bnxt_rx_ring_info),
3633 for (i = 0; i < bp->rx_nr_rings; i++) {
3634 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3636 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3637 rxr->rx_ring_struct.ring_mem.flags =
3638 BNXT_RMEM_RING_PTE_FLAG;
3639 rxr->rx_agg_ring_struct.ring_mem.flags =
3640 BNXT_RMEM_RING_PTE_FLAG;
3642 rxr->bnapi = bp->bnapi[i];
3643 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3646 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3647 sizeof(struct bnxt_tx_ring_info),
3652 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3655 if (!bp->tx_ring_map)
3658 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3661 j = bp->rx_nr_rings;
3663 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3664 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3666 if (bp->flags & BNXT_FLAG_CHIP_P5)
3667 txr->tx_ring_struct.ring_mem.flags =
3668 BNXT_RMEM_RING_PTE_FLAG;
3669 txr->bnapi = bp->bnapi[j];
3670 bp->bnapi[j]->tx_ring = txr;
3671 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3672 if (i >= bp->tx_nr_rings_xdp) {
3673 txr->txq_index = i - bp->tx_nr_rings_xdp;
3674 bp->bnapi[j]->tx_int = bnxt_tx_int;
3676 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3677 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3681 rc = bnxt_alloc_stats(bp);
3685 rc = bnxt_alloc_ntp_fltrs(bp);
3689 rc = bnxt_alloc_vnics(bp);
3694 bnxt_init_ring_struct(bp);
3696 rc = bnxt_alloc_rx_rings(bp);
3700 rc = bnxt_alloc_tx_rings(bp);
3704 rc = bnxt_alloc_cp_rings(bp);
3708 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3709 BNXT_VNIC_UCAST_FLAG;
3710 rc = bnxt_alloc_vnic_attributes(bp);
3716 bnxt_free_mem(bp, true);
3720 static void bnxt_disable_int(struct bnxt *bp)
3727 for (i = 0; i < bp->cp_nr_rings; i++) {
3728 struct bnxt_napi *bnapi = bp->bnapi[i];
3729 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3730 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3732 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3733 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3737 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3739 struct bnxt_napi *bnapi = bp->bnapi[n];
3740 struct bnxt_cp_ring_info *cpr;
3742 cpr = &bnapi->cp_ring;
3743 return cpr->cp_ring_struct.map_idx;
3746 static void bnxt_disable_int_sync(struct bnxt *bp)
3750 atomic_inc(&bp->intr_sem);
3752 bnxt_disable_int(bp);
3753 for (i = 0; i < bp->cp_nr_rings; i++) {
3754 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3756 synchronize_irq(bp->irq_tbl[map_idx].vector);
3760 static void bnxt_enable_int(struct bnxt *bp)
3764 atomic_set(&bp->intr_sem, 0);
3765 for (i = 0; i < bp->cp_nr_rings; i++) {
3766 struct bnxt_napi *bnapi = bp->bnapi[i];
3767 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3769 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3773 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3774 u16 cmpl_ring, u16 target_id)
3776 struct input *req = request;
3778 req->req_type = cpu_to_le16(req_type);
3779 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3780 req->target_id = cpu_to_le16(target_id);
3781 if (bnxt_kong_hwrm_message(bp, req))
3782 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3784 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3787 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3788 int timeout, bool silent)
3790 int i, intr_process, rc, tmo_count;
3791 struct input *req = msg;
3795 u16 cp_ring_id, len = 0;
3796 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3797 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3798 struct hwrm_short_input short_input = {0};
3799 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3800 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3801 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3802 u16 dst = BNXT_HWRM_CHNL_CHIMP;
3804 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3805 if (msg_len > bp->hwrm_max_ext_req_len ||
3806 !bp->hwrm_short_cmd_req_addr)
3810 if (bnxt_hwrm_kong_chnl(bp, req)) {
3811 dst = BNXT_HWRM_CHNL_KONG;
3812 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3813 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3814 resp = bp->hwrm_cmd_kong_resp_addr;
3815 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3818 memset(resp, 0, PAGE_SIZE);
3819 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3820 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3822 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3823 /* currently supports only one outstanding message */
3825 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3827 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3828 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3829 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3832 /* Set boundary for maximum extended request length for short
3833 * cmd format. If passed up from device use the max supported
3834 * internal req length.
3836 max_msg_len = bp->hwrm_max_ext_req_len;
3838 memcpy(short_cmd_req, req, msg_len);
3839 if (msg_len < max_msg_len)
3840 memset(short_cmd_req + msg_len, 0,
3841 max_msg_len - msg_len);
3843 short_input.req_type = req->req_type;
3844 short_input.signature =
3845 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3846 short_input.size = cpu_to_le16(msg_len);
3847 short_input.req_addr =
3848 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3850 data = (u32 *)&short_input;
3851 msg_len = sizeof(short_input);
3853 /* Sync memory write before updating doorbell */
3856 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3859 /* Write request msg to hwrm channel */
3860 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3862 for (i = msg_len; i < max_req_len; i += 4)
3863 writel(0, bp->bar0 + bar_offset + i);
3865 /* Ring channel doorbell */
3866 writel(1, bp->bar0 + doorbell_offset);
3869 timeout = DFLT_HWRM_CMD_TIMEOUT;
3870 /* convert timeout to usec */
3874 /* Short timeout for the first few iterations:
3875 * number of loops = number of loops for short timeout +
3876 * number of loops for standard timeout.
3878 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3879 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3880 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3881 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3884 u16 seq_id = bp->hwrm_intr_seq_id;
3886 /* Wait until hwrm response cmpl interrupt is processed */
3887 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3889 /* on first few passes, just barely sleep */
3890 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3891 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3892 HWRM_SHORT_MAX_TIMEOUT);
3894 usleep_range(HWRM_MIN_TIMEOUT,
3898 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3899 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3900 le16_to_cpu(req->req_type));
3903 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3905 valid = resp_addr + len - 1;
3909 /* Check if response len is updated */
3910 for (i = 0; i < tmo_count; i++) {
3911 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3915 /* on first few passes, just barely sleep */
3916 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3917 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3918 HWRM_SHORT_MAX_TIMEOUT);
3920 usleep_range(HWRM_MIN_TIMEOUT,
3924 if (i >= tmo_count) {
3925 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3926 HWRM_TOTAL_TIMEOUT(i),
3927 le16_to_cpu(req->req_type),
3928 le16_to_cpu(req->seq_id), len);
3932 /* Last byte of resp contains valid bit */
3933 valid = resp_addr + len - 1;
3934 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3935 /* make sure we read from updated DMA memory */
3942 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3943 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3944 HWRM_TOTAL_TIMEOUT(i),
3945 le16_to_cpu(req->req_type),
3946 le16_to_cpu(req->seq_id), len, *valid);
3951 /* Zero valid bit for compatibility. Valid bit in an older spec
3952 * may become a new field in a newer spec. We must make sure that
3953 * a new field not implemented by old spec will read zero.
3956 rc = le16_to_cpu(resp->error_code);
3958 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3959 le16_to_cpu(resp->req_type),
3960 le16_to_cpu(resp->seq_id), rc);
3964 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3966 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3969 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3972 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3975 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3979 mutex_lock(&bp->hwrm_cmd_lock);
3980 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3981 mutex_unlock(&bp->hwrm_cmd_lock);
3985 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3990 mutex_lock(&bp->hwrm_cmd_lock);
3991 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3992 mutex_unlock(&bp->hwrm_cmd_lock);
3996 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3999 struct hwrm_func_drv_rgtr_input req = {0};
4000 DECLARE_BITMAP(async_events_bmap, 256);
4001 u32 *events = (u32 *)async_events_bmap;
4004 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4007 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4009 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4010 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4011 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4013 if (bmap && bmap_size) {
4014 for (i = 0; i < bmap_size; i++) {
4015 if (test_bit(i, bmap))
4016 __set_bit(i, async_events_bmap);
4020 for (i = 0; i < 8; i++)
4021 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4023 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4026 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4028 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4029 struct hwrm_func_drv_rgtr_input req = {0};
4032 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4035 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4036 FUNC_DRV_RGTR_REQ_ENABLES_VER);
4038 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4039 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4040 req.ver_maj_8b = DRV_VER_MAJ;
4041 req.ver_min_8b = DRV_VER_MIN;
4042 req.ver_upd_8b = DRV_VER_UPD;
4043 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4044 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4045 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4051 memset(data, 0, sizeof(data));
4052 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4053 u16 cmd = bnxt_vf_req_snif[i];
4054 unsigned int bit, idx;
4058 data[idx] |= 1 << bit;
4061 for (i = 0; i < 8; i++)
4062 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4065 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4068 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4069 req.flags |= cpu_to_le32(
4070 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4072 mutex_lock(&bp->hwrm_cmd_lock);
4073 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4076 else if (resp->flags &
4077 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4078 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4079 mutex_unlock(&bp->hwrm_cmd_lock);
4083 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4085 struct hwrm_func_drv_unrgtr_input req = {0};
4087 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4088 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4091 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4094 struct hwrm_tunnel_dst_port_free_input req = {0};
4096 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4097 req.tunnel_type = tunnel_type;
4099 switch (tunnel_type) {
4100 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4101 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4103 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4104 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4110 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4112 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4117 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4121 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4122 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4124 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4126 req.tunnel_type = tunnel_type;
4127 req.tunnel_dst_port_val = port;
4129 mutex_lock(&bp->hwrm_cmd_lock);
4130 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4132 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4137 switch (tunnel_type) {
4138 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4139 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4141 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4142 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4149 mutex_unlock(&bp->hwrm_cmd_lock);
4153 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4155 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4156 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4158 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4159 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4161 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4162 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4163 req.mask = cpu_to_le32(vnic->rx_mask);
4164 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4167 #ifdef CONFIG_RFS_ACCEL
4168 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4169 struct bnxt_ntuple_filter *fltr)
4171 struct hwrm_cfa_ntuple_filter_free_input req = {0};
4173 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4174 req.ntuple_filter_id = fltr->filter_id;
4175 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4178 #define BNXT_NTP_FLTR_FLAGS \
4179 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4180 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4181 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4182 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4183 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4184 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4185 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4186 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4187 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4188 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4189 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4190 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4191 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4192 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4194 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4195 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4197 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4198 struct bnxt_ntuple_filter *fltr)
4200 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
4201 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4202 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4203 struct flow_keys *keys = &fltr->fkeys;
4206 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4207 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4209 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4211 req.ethertype = htons(ETH_P_IP);
4212 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4213 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4214 req.ip_protocol = keys->basic.ip_proto;
4216 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4219 req.ethertype = htons(ETH_P_IPV6);
4221 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4222 *(struct in6_addr *)&req.src_ipaddr[0] =
4223 keys->addrs.v6addrs.src;
4224 *(struct in6_addr *)&req.dst_ipaddr[0] =
4225 keys->addrs.v6addrs.dst;
4226 for (i = 0; i < 4; i++) {
4227 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4228 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4231 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4232 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4233 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4234 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4236 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4237 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4239 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4242 req.src_port = keys->ports.src;
4243 req.src_port_mask = cpu_to_be16(0xffff);
4244 req.dst_port = keys->ports.dst;
4245 req.dst_port_mask = cpu_to_be16(0xffff);
4247 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4248 mutex_lock(&bp->hwrm_cmd_lock);
4249 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4251 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4252 fltr->filter_id = resp->ntuple_filter_id;
4254 mutex_unlock(&bp->hwrm_cmd_lock);
4259 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4263 struct hwrm_cfa_l2_filter_alloc_input req = {0};
4264 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4266 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4267 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4268 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4270 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4271 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4273 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4274 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4275 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4276 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4277 req.l2_addr_mask[0] = 0xff;
4278 req.l2_addr_mask[1] = 0xff;
4279 req.l2_addr_mask[2] = 0xff;
4280 req.l2_addr_mask[3] = 0xff;
4281 req.l2_addr_mask[4] = 0xff;
4282 req.l2_addr_mask[5] = 0xff;
4284 mutex_lock(&bp->hwrm_cmd_lock);
4285 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4287 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4289 mutex_unlock(&bp->hwrm_cmd_lock);
4293 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4295 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4298 /* Any associated ntuple filters will also be cleared by firmware. */
4299 mutex_lock(&bp->hwrm_cmd_lock);
4300 for (i = 0; i < num_of_vnics; i++) {
4301 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4303 for (j = 0; j < vnic->uc_filter_count; j++) {
4304 struct hwrm_cfa_l2_filter_free_input req = {0};
4306 bnxt_hwrm_cmd_hdr_init(bp, &req,
4307 HWRM_CFA_L2_FILTER_FREE, -1, -1);
4309 req.l2_filter_id = vnic->fw_l2_filter_id[j];
4311 rc = _hwrm_send_message(bp, &req, sizeof(req),
4314 vnic->uc_filter_count = 0;
4316 mutex_unlock(&bp->hwrm_cmd_lock);
4321 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4323 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4324 struct hwrm_vnic_tpa_cfg_input req = {0};
4326 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4329 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4332 u16 mss = bp->dev->mtu - 40;
4333 u32 nsegs, n, segs = 0, flags;
4335 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4336 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4337 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4338 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4339 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4340 if (tpa_flags & BNXT_FLAG_GRO)
4341 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4343 req.flags = cpu_to_le32(flags);
4346 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4347 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4348 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4350 /* Number of segs are log2 units, and first packet is not
4351 * included as part of this units.
4353 if (mss <= BNXT_RX_PAGE_SIZE) {
4354 n = BNXT_RX_PAGE_SIZE / mss;
4355 nsegs = (MAX_SKB_FRAGS - 1) * n;
4357 n = mss / BNXT_RX_PAGE_SIZE;
4358 if (mss & (BNXT_RX_PAGE_SIZE - 1))
4360 nsegs = (MAX_SKB_FRAGS - n) / n;
4363 segs = ilog2(nsegs);
4364 req.max_agg_segs = cpu_to_le16(segs);
4365 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4367 req.min_agg_len = cpu_to_le32(512);
4369 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4371 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4374 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4376 struct bnxt_ring_grp_info *grp_info;
4378 grp_info = &bp->grp_info[ring->grp_idx];
4379 return grp_info->cp_fw_ring_id;
4382 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4384 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4385 struct bnxt_napi *bnapi = rxr->bnapi;
4386 struct bnxt_cp_ring_info *cpr;
4388 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4389 return cpr->cp_ring_struct.fw_ring_id;
4391 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4395 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4397 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4398 struct bnxt_napi *bnapi = txr->bnapi;
4399 struct bnxt_cp_ring_info *cpr;
4401 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4402 return cpr->cp_ring_struct.fw_ring_id;
4404 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4408 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4410 u32 i, j, max_rings;
4411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4412 struct hwrm_vnic_rss_cfg_input req = {0};
4414 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4415 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4418 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4420 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4421 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4422 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4423 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4424 max_rings = bp->rx_nr_rings - 1;
4426 max_rings = bp->rx_nr_rings;
4431 /* Fill the RSS indirection table with ring group ids */
4432 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4435 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4438 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4439 req.hash_key_tbl_addr =
4440 cpu_to_le64(vnic->rss_hash_key_dma_addr);
4442 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4443 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4446 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4448 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4449 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4450 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4451 struct hwrm_vnic_rss_cfg_input req = {0};
4453 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4454 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4456 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4459 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4460 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4461 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4462 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4463 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4464 for (i = 0, k = 0; i < nr_ctxs; i++) {
4465 __le16 *ring_tbl = vnic->rss_table;
4468 req.ring_table_pair_index = i;
4469 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4470 for (j = 0; j < 64; j++) {
4473 ring_id = rxr->rx_ring_struct.fw_ring_id;
4474 *ring_tbl++ = cpu_to_le16(ring_id);
4475 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4476 *ring_tbl++ = cpu_to_le16(ring_id);
4479 if (k == max_rings) {
4481 rxr = &bp->rx_ring[0];
4484 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4491 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4493 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4494 struct hwrm_vnic_plcmodes_cfg_input req = {0};
4496 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4497 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4498 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4499 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4501 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4502 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4503 /* thresholds not implemented in firmware yet */
4504 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4505 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4506 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4507 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4510 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4513 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4515 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4516 req.rss_cos_lb_ctx_id =
4517 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4519 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4520 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4523 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4527 for (i = 0; i < bp->nr_vnics; i++) {
4528 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4530 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4531 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4532 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4535 bp->rsscos_nr_ctxs = 0;
4538 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4541 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4542 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4543 bp->hwrm_cmd_resp_addr;
4545 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4548 mutex_lock(&bp->hwrm_cmd_lock);
4549 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4551 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4552 le16_to_cpu(resp->rss_cos_lb_ctx_id);
4553 mutex_unlock(&bp->hwrm_cmd_lock);
4558 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4560 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4561 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4562 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4565 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4567 unsigned int ring = 0, grp_idx;
4568 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4569 struct hwrm_vnic_cfg_input req = {0};
4572 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4574 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4575 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4577 req.default_rx_ring_id =
4578 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4579 req.default_cmpl_ring_id =
4580 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4582 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4583 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4586 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4587 /* Only RSS support for now TBD: COS & LB */
4588 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4589 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4590 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4591 VNIC_CFG_REQ_ENABLES_MRU);
4592 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4594 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4595 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4596 VNIC_CFG_REQ_ENABLES_MRU);
4597 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4599 req.rss_rule = cpu_to_le16(0xffff);
4602 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4603 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4604 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4605 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4607 req.cos_rule = cpu_to_le16(0xffff);
4610 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4612 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4614 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4615 ring = bp->rx_nr_rings - 1;
4617 grp_idx = bp->rx_ring[ring].bnapi->index;
4618 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4619 req.lb_rule = cpu_to_le16(0xffff);
4621 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4624 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4625 #ifdef CONFIG_BNXT_SRIOV
4627 def_vlan = bp->vf.vlan;
4629 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4630 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4631 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4632 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4634 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4637 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4641 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4642 struct hwrm_vnic_free_input req = {0};
4644 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4646 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4648 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4651 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4656 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4660 for (i = 0; i < bp->nr_vnics; i++)
4661 bnxt_hwrm_vnic_free_one(bp, i);
4664 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4665 unsigned int start_rx_ring_idx,
4666 unsigned int nr_rings)
4669 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4670 struct hwrm_vnic_alloc_input req = {0};
4671 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4672 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4674 if (bp->flags & BNXT_FLAG_CHIP_P5)
4675 goto vnic_no_ring_grps;
4677 /* map ring groups to this vnic */
4678 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4679 grp_idx = bp->rx_ring[i].bnapi->index;
4680 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4681 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4685 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4689 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4690 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4692 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4694 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4696 mutex_lock(&bp->hwrm_cmd_lock);
4697 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4699 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4700 mutex_unlock(&bp->hwrm_cmd_lock);
4704 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4706 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4707 struct hwrm_vnic_qcaps_input req = {0};
4710 if (bp->hwrm_spec_code < 0x10600)
4713 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4714 mutex_lock(&bp->hwrm_cmd_lock);
4715 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4717 u32 flags = le32_to_cpu(resp->flags);
4719 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4720 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4721 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4723 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4724 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4726 mutex_unlock(&bp->hwrm_cmd_lock);
4730 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4735 if (bp->flags & BNXT_FLAG_CHIP_P5)
4738 mutex_lock(&bp->hwrm_cmd_lock);
4739 for (i = 0; i < bp->rx_nr_rings; i++) {
4740 struct hwrm_ring_grp_alloc_input req = {0};
4741 struct hwrm_ring_grp_alloc_output *resp =
4742 bp->hwrm_cmd_resp_addr;
4743 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4745 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4747 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4748 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4749 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4750 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4752 rc = _hwrm_send_message(bp, &req, sizeof(req),
4757 bp->grp_info[grp_idx].fw_grp_id =
4758 le32_to_cpu(resp->ring_group_id);
4760 mutex_unlock(&bp->hwrm_cmd_lock);
4764 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4768 struct hwrm_ring_grp_free_input req = {0};
4770 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4773 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4775 mutex_lock(&bp->hwrm_cmd_lock);
4776 for (i = 0; i < bp->cp_nr_rings; i++) {
4777 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4780 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4782 rc = _hwrm_send_message(bp, &req, sizeof(req),
4786 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4788 mutex_unlock(&bp->hwrm_cmd_lock);
4792 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4793 struct bnxt_ring_struct *ring,
4794 u32 ring_type, u32 map_index)
4796 int rc = 0, err = 0;
4797 struct hwrm_ring_alloc_input req = {0};
4798 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4799 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4800 struct bnxt_ring_grp_info *grp_info;
4803 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4806 if (rmem->nr_pages > 1) {
4807 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4808 /* Page size is in log2 units */
4809 req.page_size = BNXT_PAGE_SHIFT;
4810 req.page_tbl_depth = 1;
4812 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
4815 /* Association of ring index with doorbell index and MSIX number */
4816 req.logical_id = cpu_to_le16(map_index);
4818 switch (ring_type) {
4819 case HWRM_RING_ALLOC_TX: {
4820 struct bnxt_tx_ring_info *txr;
4822 txr = container_of(ring, struct bnxt_tx_ring_info,
4824 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4825 /* Association of transmit ring with completion ring */
4826 grp_info = &bp->grp_info[ring->grp_idx];
4827 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4828 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4829 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4830 req.queue_id = cpu_to_le16(ring->queue_id);
4833 case HWRM_RING_ALLOC_RX:
4834 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4835 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4836 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4839 /* Association of rx ring with stats context */
4840 grp_info = &bp->grp_info[ring->grp_idx];
4841 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4842 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4843 req.enables |= cpu_to_le32(
4844 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4845 if (NET_IP_ALIGN == 2)
4846 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4847 req.flags = cpu_to_le16(flags);
4850 case HWRM_RING_ALLOC_AGG:
4851 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4852 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4853 /* Association of agg ring with rx ring */
4854 grp_info = &bp->grp_info[ring->grp_idx];
4855 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4856 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4857 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4858 req.enables |= cpu_to_le32(
4859 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4860 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4862 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4864 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4866 case HWRM_RING_ALLOC_CMPL:
4867 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4868 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4869 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4870 /* Association of cp ring with nq */
4871 grp_info = &bp->grp_info[map_index];
4872 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4873 req.cq_handle = cpu_to_le64(ring->handle);
4874 req.enables |= cpu_to_le32(
4875 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4876 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4877 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4880 case HWRM_RING_ALLOC_NQ:
4881 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4882 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4883 if (bp->flags & BNXT_FLAG_USING_MSIX)
4884 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4887 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4892 mutex_lock(&bp->hwrm_cmd_lock);
4893 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4894 err = le16_to_cpu(resp->error_code);
4895 ring_id = le16_to_cpu(resp->ring_id);
4896 mutex_unlock(&bp->hwrm_cmd_lock);
4899 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4900 ring_type, rc, err);
4903 ring->fw_ring_id = ring_id;
4907 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4912 struct hwrm_func_cfg_input req = {0};
4914 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4915 req.fid = cpu_to_le16(0xffff);
4916 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4917 req.async_event_cr = cpu_to_le16(idx);
4918 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4920 struct hwrm_func_vf_cfg_input req = {0};
4922 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4924 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4925 req.async_event_cr = cpu_to_le16(idx);
4926 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4931 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
4932 u32 map_idx, u32 xid)
4934 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4936 db->doorbell = bp->bar1 + 0x10000;
4938 db->doorbell = bp->bar1 + 0x4000;
4939 switch (ring_type) {
4940 case HWRM_RING_ALLOC_TX:
4941 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
4943 case HWRM_RING_ALLOC_RX:
4944 case HWRM_RING_ALLOC_AGG:
4945 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
4947 case HWRM_RING_ALLOC_CMPL:
4948 db->db_key64 = DBR_PATH_L2;
4950 case HWRM_RING_ALLOC_NQ:
4951 db->db_key64 = DBR_PATH_L2;
4954 db->db_key64 |= (u64)xid << DBR_XID_SFT;
4956 db->doorbell = bp->bar1 + map_idx * 0x80;
4957 switch (ring_type) {
4958 case HWRM_RING_ALLOC_TX:
4959 db->db_key32 = DB_KEY_TX;
4961 case HWRM_RING_ALLOC_RX:
4962 case HWRM_RING_ALLOC_AGG:
4963 db->db_key32 = DB_KEY_RX;
4965 case HWRM_RING_ALLOC_CMPL:
4966 db->db_key32 = DB_KEY_CP;
4972 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4977 if (bp->flags & BNXT_FLAG_CHIP_P5)
4978 type = HWRM_RING_ALLOC_NQ;
4980 type = HWRM_RING_ALLOC_CMPL;
4981 for (i = 0; i < bp->cp_nr_rings; i++) {
4982 struct bnxt_napi *bnapi = bp->bnapi[i];
4983 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4984 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4985 u32 map_idx = ring->map_idx;
4986 unsigned int vector;
4988 vector = bp->irq_tbl[map_idx].vector;
4989 disable_irq_nosync(vector);
4990 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
4995 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
4996 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4998 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5001 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5003 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5007 type = HWRM_RING_ALLOC_TX;
5008 for (i = 0; i < bp->tx_nr_rings; i++) {
5009 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5010 struct bnxt_ring_struct *ring;
5013 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5014 struct bnxt_napi *bnapi = txr->bnapi;
5015 struct bnxt_cp_ring_info *cpr, *cpr2;
5016 u32 type2 = HWRM_RING_ALLOC_CMPL;
5018 cpr = &bnapi->cp_ring;
5019 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5020 ring = &cpr2->cp_ring_struct;
5021 ring->handle = BNXT_TX_HDL;
5022 map_idx = bnapi->index;
5023 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5026 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5028 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5030 ring = &txr->tx_ring_struct;
5032 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5035 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5038 type = HWRM_RING_ALLOC_RX;
5039 for (i = 0; i < bp->rx_nr_rings; i++) {
5040 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5041 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5042 struct bnxt_napi *bnapi = rxr->bnapi;
5043 u32 map_idx = bnapi->index;
5045 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5048 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5049 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5050 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5051 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5052 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5053 u32 type2 = HWRM_RING_ALLOC_CMPL;
5054 struct bnxt_cp_ring_info *cpr2;
5056 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5057 ring = &cpr2->cp_ring_struct;
5058 ring->handle = BNXT_RX_HDL;
5059 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5062 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5064 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5068 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5069 type = HWRM_RING_ALLOC_AGG;
5070 for (i = 0; i < bp->rx_nr_rings; i++) {
5071 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5072 struct bnxt_ring_struct *ring =
5073 &rxr->rx_agg_ring_struct;
5074 u32 grp_idx = ring->grp_idx;
5075 u32 map_idx = grp_idx + bp->rx_nr_rings;
5077 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5081 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5083 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5084 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5091 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5092 struct bnxt_ring_struct *ring,
5093 u32 ring_type, int cmpl_ring_id)
5096 struct hwrm_ring_free_input req = {0};
5097 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5100 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5101 req.ring_type = ring_type;
5102 req.ring_id = cpu_to_le16(ring->fw_ring_id);
5104 mutex_lock(&bp->hwrm_cmd_lock);
5105 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5106 error_code = le16_to_cpu(resp->error_code);
5107 mutex_unlock(&bp->hwrm_cmd_lock);
5109 if (rc || error_code) {
5110 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5111 ring_type, rc, error_code);
5117 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5125 for (i = 0; i < bp->tx_nr_rings; i++) {
5126 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5127 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5130 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5131 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5132 hwrm_ring_free_send_msg(bp, ring,
5133 RING_FREE_REQ_RING_TYPE_TX,
5134 close_path ? cmpl_ring_id :
5135 INVALID_HW_RING_ID);
5136 ring->fw_ring_id = INVALID_HW_RING_ID;
5140 for (i = 0; i < bp->rx_nr_rings; i++) {
5141 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5142 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5143 u32 grp_idx = rxr->bnapi->index;
5146 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5147 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5148 hwrm_ring_free_send_msg(bp, ring,
5149 RING_FREE_REQ_RING_TYPE_RX,
5150 close_path ? cmpl_ring_id :
5151 INVALID_HW_RING_ID);
5152 ring->fw_ring_id = INVALID_HW_RING_ID;
5153 bp->grp_info[grp_idx].rx_fw_ring_id =
5158 if (bp->flags & BNXT_FLAG_CHIP_P5)
5159 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5161 type = RING_FREE_REQ_RING_TYPE_RX;
5162 for (i = 0; i < bp->rx_nr_rings; i++) {
5163 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5164 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5165 u32 grp_idx = rxr->bnapi->index;
5168 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5169 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5170 hwrm_ring_free_send_msg(bp, ring, type,
5171 close_path ? cmpl_ring_id :
5172 INVALID_HW_RING_ID);
5173 ring->fw_ring_id = INVALID_HW_RING_ID;
5174 bp->grp_info[grp_idx].agg_fw_ring_id =
5179 /* The completion rings are about to be freed. After that the
5180 * IRQ doorbell will not work anymore. So we need to disable
5183 bnxt_disable_int_sync(bp);
5185 if (bp->flags & BNXT_FLAG_CHIP_P5)
5186 type = RING_FREE_REQ_RING_TYPE_NQ;
5188 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5189 for (i = 0; i < bp->cp_nr_rings; i++) {
5190 struct bnxt_napi *bnapi = bp->bnapi[i];
5191 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5192 struct bnxt_ring_struct *ring;
5195 for (j = 0; j < 2; j++) {
5196 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5199 ring = &cpr2->cp_ring_struct;
5200 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5202 hwrm_ring_free_send_msg(bp, ring,
5203 RING_FREE_REQ_RING_TYPE_L2_CMPL,
5204 INVALID_HW_RING_ID);
5205 ring->fw_ring_id = INVALID_HW_RING_ID;
5208 ring = &cpr->cp_ring_struct;
5209 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5210 hwrm_ring_free_send_msg(bp, ring, type,
5211 INVALID_HW_RING_ID);
5212 ring->fw_ring_id = INVALID_HW_RING_ID;
5213 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5218 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5221 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5223 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5224 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5225 struct hwrm_func_qcfg_input req = {0};
5228 if (bp->hwrm_spec_code < 0x10601)
5231 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5232 req.fid = cpu_to_le16(0xffff);
5233 mutex_lock(&bp->hwrm_cmd_lock);
5234 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5236 mutex_unlock(&bp->hwrm_cmd_lock);
5240 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5241 if (BNXT_NEW_RM(bp)) {
5244 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5245 hw_resc->resv_hw_ring_grps =
5246 le32_to_cpu(resp->alloc_hw_ring_grps);
5247 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5248 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5249 stats = le16_to_cpu(resp->alloc_stat_ctx);
5250 hw_resc->resv_irqs = cp;
5251 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5252 int rx = hw_resc->resv_rx_rings;
5253 int tx = hw_resc->resv_tx_rings;
5255 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5257 if (cp < (rx + tx)) {
5258 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5259 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5261 hw_resc->resv_rx_rings = rx;
5262 hw_resc->resv_tx_rings = tx;
5264 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5265 hw_resc->resv_hw_ring_grps = rx;
5267 hw_resc->resv_cp_rings = cp;
5268 hw_resc->resv_stat_ctxs = stats;
5270 mutex_unlock(&bp->hwrm_cmd_lock);
5274 /* Caller must hold bp->hwrm_cmd_lock */
5275 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5277 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5278 struct hwrm_func_qcfg_input req = {0};
5281 if (bp->hwrm_spec_code < 0x10601)
5284 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5285 req.fid = cpu_to_le16(fid);
5286 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5288 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5293 static bool bnxt_rfs_supported(struct bnxt *bp);
5296 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5297 int tx_rings, int rx_rings, int ring_grps,
5298 int cp_rings, int stats, int vnics)
5302 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5303 req->fid = cpu_to_le16(0xffff);
5304 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5305 req->num_tx_rings = cpu_to_le16(tx_rings);
5306 if (BNXT_NEW_RM(bp)) {
5307 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5308 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5309 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5310 enables |= tx_rings + ring_grps ?
5311 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5312 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5313 enables |= rx_rings ?
5314 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5316 enables |= cp_rings ?
5317 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5318 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5319 enables |= ring_grps ?
5320 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5321 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5323 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5325 req->num_rx_rings = cpu_to_le16(rx_rings);
5326 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5327 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5328 req->num_msix = cpu_to_le16(cp_rings);
5329 req->num_rsscos_ctxs =
5330 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5332 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5333 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5334 req->num_rsscos_ctxs = cpu_to_le16(1);
5335 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5336 bnxt_rfs_supported(bp))
5337 req->num_rsscos_ctxs =
5338 cpu_to_le16(ring_grps + 1);
5340 req->num_stat_ctxs = cpu_to_le16(stats);
5341 req->num_vnics = cpu_to_le16(vnics);
5343 req->enables = cpu_to_le32(enables);
5347 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5348 struct hwrm_func_vf_cfg_input *req, int tx_rings,
5349 int rx_rings, int ring_grps, int cp_rings,
5350 int stats, int vnics)
5354 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5355 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5356 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5357 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5358 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5359 enables |= tx_rings + ring_grps ?
5360 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5361 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5363 enables |= cp_rings ?
5364 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5365 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5366 enables |= ring_grps ?
5367 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5369 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5370 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5372 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5373 req->num_tx_rings = cpu_to_le16(tx_rings);
5374 req->num_rx_rings = cpu_to_le16(rx_rings);
5375 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5376 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5377 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5379 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5380 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5381 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5383 req->num_stat_ctxs = cpu_to_le16(stats);
5384 req->num_vnics = cpu_to_le16(vnics);
5386 req->enables = cpu_to_le32(enables);
5390 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5391 int ring_grps, int cp_rings, int stats, int vnics)
5393 struct hwrm_func_cfg_input req = {0};
5396 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5397 cp_rings, stats, vnics);
5401 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5405 if (bp->hwrm_spec_code < 0x10601)
5406 bp->hw_resc.resv_tx_rings = tx_rings;
5408 rc = bnxt_hwrm_get_rings(bp);
5413 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5414 int ring_grps, int cp_rings, int stats, int vnics)
5416 struct hwrm_func_vf_cfg_input req = {0};
5419 if (!BNXT_NEW_RM(bp)) {
5420 bp->hw_resc.resv_tx_rings = tx_rings;
5424 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5425 cp_rings, stats, vnics);
5426 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5430 rc = bnxt_hwrm_get_rings(bp);
5434 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5435 int cp, int stat, int vnic)
5438 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5441 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5445 int bnxt_nq_rings_in_use(struct bnxt *bp)
5447 int cp = bp->cp_nr_rings;
5448 int ulp_msix, ulp_base;
5450 ulp_msix = bnxt_get_ulp_msix_num(bp);
5452 ulp_base = bnxt_get_ulp_msix_base(bp);
5454 if ((ulp_base + ulp_msix) > cp)
5455 cp = ulp_base + ulp_msix;
5460 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5464 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5465 return bnxt_nq_rings_in_use(bp);
5467 cp = bp->tx_nr_rings + bp->rx_nr_rings;
5471 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5473 return bp->cp_nr_rings + bnxt_get_ulp_stat_ctxs(bp);
5476 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5478 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5479 int cp = bnxt_cp_rings_in_use(bp);
5480 int nq = bnxt_nq_rings_in_use(bp);
5481 int rx = bp->rx_nr_rings, stat;
5482 int vnic = 1, grp = rx;
5484 if (bp->hwrm_spec_code < 0x10601)
5487 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5490 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5492 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5494 stat = bnxt_get_func_stat_ctxs(bp);
5495 if (BNXT_NEW_RM(bp) &&
5496 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5497 hw_resc->resv_irqs < nq || hw_resc->resv_vnics != vnic ||
5498 hw_resc->resv_stat_ctxs != stat ||
5499 (hw_resc->resv_hw_ring_grps != grp &&
5500 !(bp->flags & BNXT_FLAG_CHIP_P5))))
5505 static int __bnxt_reserve_rings(struct bnxt *bp)
5507 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5508 int cp = bnxt_nq_rings_in_use(bp);
5509 int tx = bp->tx_nr_rings;
5510 int rx = bp->rx_nr_rings;
5511 int grp, rx_rings, rc;
5515 if (!bnxt_need_reserve_rings(bp))
5518 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5520 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5522 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5524 grp = bp->rx_nr_rings;
5525 stat = bnxt_get_func_stat_ctxs(bp);
5527 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5531 tx = hw_resc->resv_tx_rings;
5532 if (BNXT_NEW_RM(bp)) {
5533 rx = hw_resc->resv_rx_rings;
5534 cp = hw_resc->resv_irqs;
5535 grp = hw_resc->resv_hw_ring_grps;
5536 vnic = hw_resc->resv_vnics;
5537 stat = hw_resc->resv_stat_ctxs;
5541 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5545 if (netif_running(bp->dev))
5548 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5549 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5550 bp->dev->hw_features &= ~NETIF_F_LRO;
5551 bp->dev->features &= ~NETIF_F_LRO;
5552 bnxt_set_ring_params(bp);
5555 rx_rings = min_t(int, rx_rings, grp);
5556 cp = min_t(int, cp, bp->cp_nr_rings);
5557 if (stat > bnxt_get_ulp_stat_ctxs(bp))
5558 stat -= bnxt_get_ulp_stat_ctxs(bp);
5559 cp = min_t(int, cp, stat);
5560 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5561 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5563 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5564 bp->tx_nr_rings = tx;
5565 bp->rx_nr_rings = rx_rings;
5566 bp->cp_nr_rings = cp;
5568 if (!tx || !rx || !cp || !grp || !vnic || !stat)
5574 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5575 int ring_grps, int cp_rings, int stats,
5578 struct hwrm_func_vf_cfg_input req = {0};
5582 if (!BNXT_NEW_RM(bp))
5585 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5586 cp_rings, stats, vnics);
5587 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5588 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5589 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5590 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5591 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5592 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5593 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5594 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5596 req.flags = cpu_to_le32(flags);
5597 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5603 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5604 int ring_grps, int cp_rings, int stats,
5607 struct hwrm_func_cfg_input req = {0};
5611 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5612 cp_rings, stats, vnics);
5613 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5614 if (BNXT_NEW_RM(bp)) {
5615 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5616 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5617 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5618 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5619 if (bp->flags & BNXT_FLAG_CHIP_P5)
5620 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
5621 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
5623 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5626 req.flags = cpu_to_le32(flags);
5627 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5633 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5634 int ring_grps, int cp_rings, int stats,
5637 if (bp->hwrm_spec_code < 0x10801)
5641 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5642 ring_grps, cp_rings, stats,
5645 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5646 cp_rings, stats, vnics);
5649 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5651 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5652 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5653 struct hwrm_ring_aggint_qcaps_input req = {0};
5656 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5657 coal_cap->num_cmpl_dma_aggr_max = 63;
5658 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5659 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5660 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5661 coal_cap->int_lat_tmr_min_max = 65535;
5662 coal_cap->int_lat_tmr_max_max = 65535;
5663 coal_cap->num_cmpl_aggr_int_max = 65535;
5664 coal_cap->timer_units = 80;
5666 if (bp->hwrm_spec_code < 0x10902)
5669 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5670 mutex_lock(&bp->hwrm_cmd_lock);
5671 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5673 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5674 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5675 coal_cap->num_cmpl_dma_aggr_max =
5676 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5677 coal_cap->num_cmpl_dma_aggr_during_int_max =
5678 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5679 coal_cap->cmpl_aggr_dma_tmr_max =
5680 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5681 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5682 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5683 coal_cap->int_lat_tmr_min_max =
5684 le16_to_cpu(resp->int_lat_tmr_min_max);
5685 coal_cap->int_lat_tmr_max_max =
5686 le16_to_cpu(resp->int_lat_tmr_max_max);
5687 coal_cap->num_cmpl_aggr_int_max =
5688 le16_to_cpu(resp->num_cmpl_aggr_int_max);
5689 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5691 mutex_unlock(&bp->hwrm_cmd_lock);
5694 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5696 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5698 return usec * 1000 / coal_cap->timer_units;
5701 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5702 struct bnxt_coal *hw_coal,
5703 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5705 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5706 u32 cmpl_params = coal_cap->cmpl_params;
5707 u16 val, tmr, max, flags = 0;
5709 max = hw_coal->bufs_per_record * 128;
5710 if (hw_coal->budget)
5711 max = hw_coal->bufs_per_record * hw_coal->budget;
5712 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5714 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5715 req->num_cmpl_aggr_int = cpu_to_le16(val);
5717 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5718 req->num_cmpl_dma_aggr = cpu_to_le16(val);
5720 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5721 coal_cap->num_cmpl_dma_aggr_during_int_max);
5722 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5724 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5725 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5726 req->int_lat_tmr_max = cpu_to_le16(tmr);
5728 /* min timer set to 1/2 of interrupt timer */
5729 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5731 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5732 req->int_lat_tmr_min = cpu_to_le16(val);
5733 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5736 /* buf timer set to 1/4 of interrupt timer */
5737 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5738 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5741 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5742 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5743 val = clamp_t(u16, tmr, 1,
5744 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5745 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5747 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5750 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5751 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5752 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5753 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5754 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5755 req->flags = cpu_to_le16(flags);
5756 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5759 /* Caller holds bp->hwrm_cmd_lock */
5760 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5761 struct bnxt_coal *hw_coal)
5763 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5764 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5765 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5766 u32 nq_params = coal_cap->nq_params;
5769 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5772 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5774 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5776 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5778 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5779 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5780 req.int_lat_tmr_min = cpu_to_le16(tmr);
5781 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5782 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5785 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5787 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5788 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5789 struct bnxt_coal coal;
5791 /* Tick values in micro seconds.
5792 * 1 coal_buf x bufs_per_record = 1 completion record.
5794 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5796 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5797 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5799 if (!bnapi->rx_ring)
5802 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5803 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5805 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5807 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5809 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5813 int bnxt_hwrm_set_coal(struct bnxt *bp)
5816 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5819 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5820 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5821 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5822 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5824 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5825 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5827 mutex_lock(&bp->hwrm_cmd_lock);
5828 for (i = 0; i < bp->cp_nr_rings; i++) {
5829 struct bnxt_napi *bnapi = bp->bnapi[i];
5830 struct bnxt_coal *hw_coal;
5834 if (!bnapi->rx_ring) {
5835 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5838 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5840 req->ring_id = cpu_to_le16(ring_id);
5842 rc = _hwrm_send_message(bp, req, sizeof(*req),
5847 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5850 if (bnapi->rx_ring && bnapi->tx_ring) {
5852 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5853 req->ring_id = cpu_to_le16(ring_id);
5854 rc = _hwrm_send_message(bp, req, sizeof(*req),
5860 hw_coal = &bp->rx_coal;
5862 hw_coal = &bp->tx_coal;
5863 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5865 mutex_unlock(&bp->hwrm_cmd_lock);
5869 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5872 struct hwrm_stat_ctx_free_input req = {0};
5877 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5880 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5882 mutex_lock(&bp->hwrm_cmd_lock);
5883 for (i = 0; i < bp->cp_nr_rings; i++) {
5884 struct bnxt_napi *bnapi = bp->bnapi[i];
5885 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5887 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5888 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5890 rc = _hwrm_send_message(bp, &req, sizeof(req),
5895 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5898 mutex_unlock(&bp->hwrm_cmd_lock);
5902 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5905 struct hwrm_stat_ctx_alloc_input req = {0};
5906 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5908 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5911 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5913 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5915 mutex_lock(&bp->hwrm_cmd_lock);
5916 for (i = 0; i < bp->cp_nr_rings; i++) {
5917 struct bnxt_napi *bnapi = bp->bnapi[i];
5918 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5920 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5922 rc = _hwrm_send_message(bp, &req, sizeof(req),
5927 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5929 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5931 mutex_unlock(&bp->hwrm_cmd_lock);
5935 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5937 struct hwrm_func_qcfg_input req = {0};
5938 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5942 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5943 req.fid = cpu_to_le16(0xffff);
5944 mutex_lock(&bp->hwrm_cmd_lock);
5945 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5947 goto func_qcfg_exit;
5949 #ifdef CONFIG_BNXT_SRIOV
5951 struct bnxt_vf_info *vf = &bp->vf;
5953 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5956 flags = le16_to_cpu(resp->flags);
5957 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5958 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5959 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5960 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5961 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
5963 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5964 bp->flags |= BNXT_FLAG_MULTI_HOST;
5966 switch (resp->port_partition_type) {
5967 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5968 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5969 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5970 bp->port_partition_type = resp->port_partition_type;
5973 if (bp->hwrm_spec_code < 0x10707 ||
5974 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5975 bp->br_mode = BRIDGE_MODE_VEB;
5976 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5977 bp->br_mode = BRIDGE_MODE_VEPA;
5979 bp->br_mode = BRIDGE_MODE_UNDEF;
5981 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5983 bp->max_mtu = BNXT_MAX_MTU;
5986 mutex_unlock(&bp->hwrm_cmd_lock);
5990 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5992 struct hwrm_func_backing_store_qcaps_input req = {0};
5993 struct hwrm_func_backing_store_qcaps_output *resp =
5994 bp->hwrm_cmd_resp_addr;
5997 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6000 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6001 mutex_lock(&bp->hwrm_cmd_lock);
6002 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6004 struct bnxt_ctx_pg_info *ctx_pg;
6005 struct bnxt_ctx_mem_info *ctx;
6008 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6013 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6019 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6020 ctx->tqm_mem[i] = ctx_pg;
6023 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6024 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6025 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6026 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6027 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6028 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6029 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6030 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6031 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6032 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6033 ctx->vnic_max_vnic_entries =
6034 le16_to_cpu(resp->vnic_max_vnic_entries);
6035 ctx->vnic_max_ring_table_entries =
6036 le16_to_cpu(resp->vnic_max_ring_table_entries);
6037 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6038 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6039 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6040 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6041 ctx->tqm_min_entries_per_ring =
6042 le32_to_cpu(resp->tqm_min_entries_per_ring);
6043 ctx->tqm_max_entries_per_ring =
6044 le32_to_cpu(resp->tqm_max_entries_per_ring);
6045 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6046 if (!ctx->tqm_entries_multiple)
6047 ctx->tqm_entries_multiple = 1;
6048 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6049 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6050 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6051 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6056 mutex_unlock(&bp->hwrm_cmd_lock);
6060 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6065 if (BNXT_PAGE_SHIFT == 13)
6067 else if (BNXT_PAGE_SIZE == 16)
6071 if (rmem->depth >= 1) {
6072 if (rmem->depth == 2)
6076 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6078 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6082 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
6083 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
6084 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
6085 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
6086 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
6087 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6089 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6091 struct hwrm_func_backing_store_cfg_input req = {0};
6092 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6093 struct bnxt_ctx_pg_info *ctx_pg;
6094 __le32 *num_entries;
6103 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6104 req.enables = cpu_to_le32(enables);
6106 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6107 ctx_pg = &ctx->qp_mem;
6108 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6109 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6110 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6111 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6112 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6113 &req.qpc_pg_size_qpc_lvl,
6116 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6117 ctx_pg = &ctx->srq_mem;
6118 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6119 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6120 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6121 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6122 &req.srq_pg_size_srq_lvl,
6125 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6126 ctx_pg = &ctx->cq_mem;
6127 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6128 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6129 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6130 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6133 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6134 ctx_pg = &ctx->vnic_mem;
6135 req.vnic_num_vnic_entries =
6136 cpu_to_le16(ctx->vnic_max_vnic_entries);
6137 req.vnic_num_ring_table_entries =
6138 cpu_to_le16(ctx->vnic_max_ring_table_entries);
6139 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6140 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6141 &req.vnic_pg_size_vnic_lvl,
6142 &req.vnic_page_dir);
6144 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6145 ctx_pg = &ctx->stat_mem;
6146 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6147 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6148 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6149 &req.stat_pg_size_stat_lvl,
6150 &req.stat_page_dir);
6152 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6153 ctx_pg = &ctx->mrav_mem;
6154 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6155 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6156 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6157 &req.mrav_pg_size_mrav_lvl,
6158 &req.mrav_page_dir);
6160 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6161 ctx_pg = &ctx->tim_mem;
6162 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6163 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6164 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6165 &req.tim_pg_size_tim_lvl,
6168 for (i = 0, num_entries = &req.tqm_sp_num_entries,
6169 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6170 pg_dir = &req.tqm_sp_page_dir,
6171 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6172 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6173 if (!(enables & ena))
6176 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6177 ctx_pg = ctx->tqm_mem[i];
6178 *num_entries = cpu_to_le32(ctx_pg->entries);
6179 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6181 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6187 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6188 struct bnxt_ctx_pg_info *ctx_pg)
6190 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6192 rmem->page_size = BNXT_PAGE_SIZE;
6193 rmem->pg_arr = ctx_pg->ctx_pg_arr;
6194 rmem->dma_arr = ctx_pg->ctx_dma_arr;
6195 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6196 if (rmem->depth >= 1)
6197 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6198 return bnxt_alloc_ring(bp, rmem);
6201 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6202 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6205 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6211 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6212 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6213 ctx_pg->nr_pages = 0;
6216 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6220 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6222 if (!ctx_pg->ctx_pg_tbl)
6224 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6225 rmem->nr_pages = nr_tbls;
6226 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6229 for (i = 0; i < nr_tbls; i++) {
6230 struct bnxt_ctx_pg_info *pg_tbl;
6232 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6235 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6236 rmem = &pg_tbl->ring_mem;
6237 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6238 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6240 rmem->nr_pages = MAX_CTX_PAGES;
6241 if (i == (nr_tbls - 1)) {
6242 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6245 rmem->nr_pages = rem;
6247 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6252 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6253 if (rmem->nr_pages > 1 || depth)
6255 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6260 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6261 struct bnxt_ctx_pg_info *ctx_pg)
6263 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6265 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6266 ctx_pg->ctx_pg_tbl) {
6267 int i, nr_tbls = rmem->nr_pages;
6269 for (i = 0; i < nr_tbls; i++) {
6270 struct bnxt_ctx_pg_info *pg_tbl;
6271 struct bnxt_ring_mem_info *rmem2;
6273 pg_tbl = ctx_pg->ctx_pg_tbl[i];
6276 rmem2 = &pg_tbl->ring_mem;
6277 bnxt_free_ring(bp, rmem2);
6278 ctx_pg->ctx_pg_arr[i] = NULL;
6280 ctx_pg->ctx_pg_tbl[i] = NULL;
6282 kfree(ctx_pg->ctx_pg_tbl);
6283 ctx_pg->ctx_pg_tbl = NULL;
6285 bnxt_free_ring(bp, rmem);
6286 ctx_pg->nr_pages = 0;
6289 static void bnxt_free_ctx_mem(struct bnxt *bp)
6291 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6297 if (ctx->tqm_mem[0]) {
6298 for (i = 0; i < bp->max_q + 1; i++)
6299 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6300 kfree(ctx->tqm_mem[0]);
6301 ctx->tqm_mem[0] = NULL;
6304 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6305 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6306 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6307 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6308 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6309 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6310 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6311 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6314 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6316 struct bnxt_ctx_pg_info *ctx_pg;
6317 struct bnxt_ctx_mem_info *ctx;
6318 u32 mem_size, ena, entries;
6324 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6326 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6331 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6334 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
6340 ctx_pg = &ctx->qp_mem;
6341 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6343 mem_size = ctx->qp_entry_size * ctx_pg->entries;
6344 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6348 ctx_pg = &ctx->srq_mem;
6349 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6350 mem_size = ctx->srq_entry_size * ctx_pg->entries;
6351 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6355 ctx_pg = &ctx->cq_mem;
6356 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6357 mem_size = ctx->cq_entry_size * ctx_pg->entries;
6358 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6362 ctx_pg = &ctx->vnic_mem;
6363 ctx_pg->entries = ctx->vnic_max_vnic_entries +
6364 ctx->vnic_max_ring_table_entries;
6365 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6366 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6370 ctx_pg = &ctx->stat_mem;
6371 ctx_pg->entries = ctx->stat_max_entries;
6372 mem_size = ctx->stat_entry_size * ctx_pg->entries;
6373 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6378 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6381 ctx_pg = &ctx->mrav_mem;
6382 ctx_pg->entries = extra_qps * 4;
6383 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6384 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6387 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6389 ctx_pg = &ctx->tim_mem;
6390 ctx_pg->entries = ctx->qp_mem.entries;
6391 mem_size = ctx->tim_entry_size * ctx_pg->entries;
6392 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6395 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6398 entries = ctx->qp_max_l2_entries + extra_qps;
6399 entries = roundup(entries, ctx->tqm_entries_multiple);
6400 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6401 ctx->tqm_max_entries_per_ring);
6402 for (i = 0; i < bp->max_q + 1; i++) {
6403 ctx_pg = ctx->tqm_mem[i];
6404 ctx_pg->entries = entries;
6405 mem_size = ctx->tqm_entry_size * entries;
6406 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6409 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6411 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6412 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6414 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6417 ctx->flags |= BNXT_CTX_FLAG_INITED;
6422 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6424 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6425 struct hwrm_func_resource_qcaps_input req = {0};
6426 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6429 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6430 req.fid = cpu_to_le16(0xffff);
6432 mutex_lock(&bp->hwrm_cmd_lock);
6433 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6437 goto hwrm_func_resc_qcaps_exit;
6440 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6442 goto hwrm_func_resc_qcaps_exit;
6444 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6445 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6446 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6447 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6448 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6449 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6450 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6451 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6452 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6453 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6454 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6455 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6456 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6457 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6458 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6459 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6461 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6462 u16 max_msix = le16_to_cpu(resp->max_msix);
6464 hw_resc->max_nqs = max_msix;
6465 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6469 struct bnxt_pf_info *pf = &bp->pf;
6471 pf->vf_resv_strategy =
6472 le16_to_cpu(resp->vf_reservation_strategy);
6473 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6474 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6476 hwrm_func_resc_qcaps_exit:
6477 mutex_unlock(&bp->hwrm_cmd_lock);
6481 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6484 struct hwrm_func_qcaps_input req = {0};
6485 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6486 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6489 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6490 req.fid = cpu_to_le16(0xffff);
6492 mutex_lock(&bp->hwrm_cmd_lock);
6493 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6495 goto hwrm_func_qcaps_exit;
6497 flags = le32_to_cpu(resp->flags);
6498 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6499 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6500 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6501 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6503 bp->tx_push_thresh = 0;
6504 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6505 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6507 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6508 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6509 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6510 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6511 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6512 if (!hw_resc->max_hw_ring_grps)
6513 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6514 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6515 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6516 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6519 struct bnxt_pf_info *pf = &bp->pf;
6521 pf->fw_fid = le16_to_cpu(resp->fid);
6522 pf->port_id = le16_to_cpu(resp->port_id);
6523 bp->dev->dev_port = pf->port_id;
6524 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6525 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6526 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6527 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6528 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6529 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6530 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6531 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6532 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6533 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6534 bp->flags |= BNXT_FLAG_WOL_CAP;
6536 #ifdef CONFIG_BNXT_SRIOV
6537 struct bnxt_vf_info *vf = &bp->vf;
6539 vf->fw_fid = le16_to_cpu(resp->fid);
6540 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6544 hwrm_func_qcaps_exit:
6545 mutex_unlock(&bp->hwrm_cmd_lock);
6549 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6551 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6555 rc = __bnxt_hwrm_func_qcaps(bp);
6558 rc = bnxt_hwrm_queue_qportcfg(bp);
6560 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6563 if (bp->hwrm_spec_code >= 0x10803) {
6564 rc = bnxt_alloc_ctx_mem(bp);
6567 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6569 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6574 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6576 struct hwrm_func_reset_input req = {0};
6578 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6581 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6584 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6587 struct hwrm_queue_qportcfg_input req = {0};
6588 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6592 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6594 mutex_lock(&bp->hwrm_cmd_lock);
6595 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6599 if (!resp->max_configurable_queues) {
6603 bp->max_tc = resp->max_configurable_queues;
6604 bp->max_lltc = resp->max_configurable_lossless_queues;
6605 if (bp->max_tc > BNXT_MAX_QUEUE)
6606 bp->max_tc = BNXT_MAX_QUEUE;
6608 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6609 qptr = &resp->queue_id0;
6610 for (i = 0, j = 0; i < bp->max_tc; i++) {
6611 bp->q_info[j].queue_id = *qptr;
6612 bp->q_ids[i] = *qptr++;
6613 bp->q_info[j].queue_profile = *qptr++;
6614 bp->tc_to_qidx[j] = j;
6615 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6616 (no_rdma && BNXT_PF(bp)))
6619 bp->max_q = bp->max_tc;
6620 bp->max_tc = max_t(u8, j, 1);
6622 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6625 if (bp->max_lltc > bp->max_tc)
6626 bp->max_lltc = bp->max_tc;
6629 mutex_unlock(&bp->hwrm_cmd_lock);
6633 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6636 struct hwrm_ver_get_input req = {0};
6637 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6640 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6641 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6642 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6643 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6644 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6645 mutex_lock(&bp->hwrm_cmd_lock);
6646 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6648 goto hwrm_ver_get_exit;
6650 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6652 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6653 resp->hwrm_intf_min_8b << 8 |
6654 resp->hwrm_intf_upd_8b;
6655 if (resp->hwrm_intf_maj_8b < 1) {
6656 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6657 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6658 resp->hwrm_intf_upd_8b);
6659 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6661 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6662 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6663 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6665 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6666 if (!bp->hwrm_cmd_timeout)
6667 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6669 if (resp->hwrm_intf_maj_8b >= 1) {
6670 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6671 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6673 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6674 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6676 bp->chip_num = le16_to_cpu(resp->chip_num);
6677 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6679 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6681 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6682 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6683 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6684 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6686 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6687 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6690 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6691 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6694 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
6695 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
6698 mutex_unlock(&bp->hwrm_cmd_lock);
6702 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6704 struct hwrm_fw_set_time_input req = {0};
6706 time64_t now = ktime_get_real_seconds();
6708 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6709 bp->hwrm_spec_code < 0x10400)
6712 time64_to_tm(now, 0, &tm);
6713 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6714 req.year = cpu_to_le16(1900 + tm.tm_year);
6715 req.month = 1 + tm.tm_mon;
6716 req.day = tm.tm_mday;
6717 req.hour = tm.tm_hour;
6718 req.minute = tm.tm_min;
6719 req.second = tm.tm_sec;
6720 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6723 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6726 struct bnxt_pf_info *pf = &bp->pf;
6727 struct hwrm_port_qstats_input req = {0};
6729 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6732 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6733 req.port_id = cpu_to_le16(pf->port_id);
6734 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6735 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6736 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6740 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6742 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6743 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6744 struct hwrm_port_qstats_ext_input req = {0};
6745 struct bnxt_pf_info *pf = &bp->pf;
6748 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6751 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6752 req.port_id = cpu_to_le16(pf->port_id);
6753 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6754 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6755 req.tx_stat_size = cpu_to_le16(sizeof(struct tx_port_stats_ext));
6756 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6757 mutex_lock(&bp->hwrm_cmd_lock);
6758 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6760 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6761 bp->fw_tx_stats_ext_size = le16_to_cpu(resp->tx_stat_size) / 8;
6763 bp->fw_rx_stats_ext_size = 0;
6764 bp->fw_tx_stats_ext_size = 0;
6766 if (bp->fw_tx_stats_ext_size <=
6767 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6768 mutex_unlock(&bp->hwrm_cmd_lock);
6769 bp->pri2cos_valid = 0;
6773 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6774 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6776 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6778 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6782 resp2 = bp->hwrm_cmd_resp_addr;
6783 pri2cos = &resp2->pri0_cos_queue_id;
6784 for (i = 0; i < 8; i++) {
6785 u8 queue_id = pri2cos[i];
6787 for (j = 0; j < bp->max_q; j++) {
6788 if (bp->q_ids[j] == queue_id)
6792 bp->pri2cos_valid = 1;
6794 mutex_unlock(&bp->hwrm_cmd_lock);
6798 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6800 if (bp->vxlan_port_cnt) {
6801 bnxt_hwrm_tunnel_dst_port_free(
6802 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6804 bp->vxlan_port_cnt = 0;
6805 if (bp->nge_port_cnt) {
6806 bnxt_hwrm_tunnel_dst_port_free(
6807 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6809 bp->nge_port_cnt = 0;
6812 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6818 tpa_flags = bp->flags & BNXT_FLAG_TPA;
6819 for (i = 0; i < bp->nr_vnics; i++) {
6820 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
6822 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
6830 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
6834 for (i = 0; i < bp->nr_vnics; i++)
6835 bnxt_hwrm_vnic_set_rss(bp, i, false);
6838 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
6841 if (bp->vnic_info) {
6842 bnxt_hwrm_clear_vnic_filter(bp);
6843 /* clear all RSS setting before free vnic ctx */
6844 bnxt_hwrm_clear_vnic_rss(bp);
6845 bnxt_hwrm_vnic_ctx_free(bp);
6846 /* before free the vnic, undo the vnic tpa settings */
6847 if (bp->flags & BNXT_FLAG_TPA)
6848 bnxt_set_tpa(bp, false);
6849 bnxt_hwrm_vnic_free(bp);
6851 bnxt_hwrm_ring_free(bp, close_path);
6852 bnxt_hwrm_ring_grp_free(bp);
6854 bnxt_hwrm_stat_ctx_free(bp);
6855 bnxt_hwrm_free_tunnel_ports(bp);
6859 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
6861 struct hwrm_func_cfg_input req = {0};
6864 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6865 req.fid = cpu_to_le16(0xffff);
6866 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
6867 if (br_mode == BRIDGE_MODE_VEB)
6868 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
6869 else if (br_mode == BRIDGE_MODE_VEPA)
6870 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
6873 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6879 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
6881 struct hwrm_func_cfg_input req = {0};
6884 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
6887 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6888 req.fid = cpu_to_le16(0xffff);
6889 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
6890 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
6892 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
6894 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6900 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
6902 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
6905 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
6908 /* allocate context for vnic */
6909 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
6911 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
6913 goto vnic_setup_err;
6915 bp->rsscos_nr_ctxs++;
6917 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6918 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
6920 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
6922 goto vnic_setup_err;
6924 bp->rsscos_nr_ctxs++;
6928 /* configure default vnic, ring grp */
6929 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6931 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6933 goto vnic_setup_err;
6936 /* Enable RSS hashing on vnic */
6937 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
6939 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
6941 goto vnic_setup_err;
6944 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6945 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6947 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6956 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
6960 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
6961 for (i = 0; i < nr_ctxs; i++) {
6962 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
6964 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
6968 bp->rsscos_nr_ctxs++;
6973 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
6975 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
6979 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6981 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6985 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6986 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6988 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6995 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
6997 if (bp->flags & BNXT_FLAG_CHIP_P5)
6998 return __bnxt_setup_vnic_p5(bp, vnic_id);
7000 return __bnxt_setup_vnic(bp, vnic_id);
7003 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7005 #ifdef CONFIG_RFS_ACCEL
7008 for (i = 0; i < bp->rx_nr_rings; i++) {
7009 struct bnxt_vnic_info *vnic;
7010 u16 vnic_id = i + 1;
7013 if (vnic_id >= bp->nr_vnics)
7016 vnic = &bp->vnic_info[vnic_id];
7017 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7018 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7019 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7020 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7022 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7026 rc = bnxt_setup_vnic(bp, vnic_id);
7036 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7037 static bool bnxt_promisc_ok(struct bnxt *bp)
7039 #ifdef CONFIG_BNXT_SRIOV
7040 if (BNXT_VF(bp) && !bp->vf.vlan)
7046 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7048 unsigned int rc = 0;
7050 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7052 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7057 rc = bnxt_hwrm_vnic_cfg(bp, 1);
7059 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7066 static int bnxt_cfg_rx_mode(struct bnxt *);
7067 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7069 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7071 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7073 unsigned int rx_nr_rings = bp->rx_nr_rings;
7076 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7078 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7084 rc = bnxt_hwrm_ring_alloc(bp);
7086 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7090 rc = bnxt_hwrm_ring_grp_alloc(bp);
7092 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7096 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7099 /* default vnic 0 */
7100 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7102 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7106 rc = bnxt_setup_vnic(bp, 0);
7110 if (bp->flags & BNXT_FLAG_RFS) {
7111 rc = bnxt_alloc_rfs_vnics(bp);
7116 if (bp->flags & BNXT_FLAG_TPA) {
7117 rc = bnxt_set_tpa(bp, true);
7123 bnxt_update_vf_mac(bp);
7125 /* Filter for default vnic 0 */
7126 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7128 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7131 vnic->uc_filter_count = 1;
7134 if (bp->dev->flags & IFF_BROADCAST)
7135 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7137 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7138 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7140 if (bp->dev->flags & IFF_ALLMULTI) {
7141 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7142 vnic->mc_list_count = 0;
7146 bnxt_mc_list_updated(bp, &mask);
7147 vnic->rx_mask |= mask;
7150 rc = bnxt_cfg_rx_mode(bp);
7154 rc = bnxt_hwrm_set_coal(bp);
7156 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7159 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7160 rc = bnxt_setup_nitroa0_vnic(bp);
7162 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7167 bnxt_hwrm_func_qcfg(bp);
7168 netdev_update_features(bp->dev);
7174 bnxt_hwrm_resource_free(bp, 0, true);
7179 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7181 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7185 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7187 bnxt_init_cp_rings(bp);
7188 bnxt_init_rx_rings(bp);
7189 bnxt_init_tx_rings(bp);
7190 bnxt_init_ring_grps(bp, irq_re_init);
7191 bnxt_init_vnics(bp);
7193 return bnxt_init_chip(bp, irq_re_init);
7196 static int bnxt_set_real_num_queues(struct bnxt *bp)
7199 struct net_device *dev = bp->dev;
7201 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7202 bp->tx_nr_rings_xdp);
7206 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7210 #ifdef CONFIG_RFS_ACCEL
7211 if (bp->flags & BNXT_FLAG_RFS)
7212 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7218 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7221 int _rx = *rx, _tx = *tx;
7224 *rx = min_t(int, _rx, max);
7225 *tx = min_t(int, _tx, max);
7230 while (_rx + _tx > max) {
7231 if (_rx > _tx && _rx > 1)
7242 static void bnxt_setup_msix(struct bnxt *bp)
7244 const int len = sizeof(bp->irq_tbl[0].name);
7245 struct net_device *dev = bp->dev;
7248 tcs = netdev_get_num_tc(dev);
7252 for (i = 0; i < tcs; i++) {
7253 count = bp->tx_nr_rings_per_tc;
7255 netdev_set_tc_queue(dev, i, count, off);
7259 for (i = 0; i < bp->cp_nr_rings; i++) {
7260 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7263 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7265 else if (i < bp->rx_nr_rings)
7270 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7272 bp->irq_tbl[map_idx].handler = bnxt_msix;
7276 static void bnxt_setup_inta(struct bnxt *bp)
7278 const int len = sizeof(bp->irq_tbl[0].name);
7280 if (netdev_get_num_tc(bp->dev))
7281 netdev_reset_tc(bp->dev);
7283 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7285 bp->irq_tbl[0].handler = bnxt_inta;
7288 static int bnxt_setup_int_mode(struct bnxt *bp)
7292 if (bp->flags & BNXT_FLAG_USING_MSIX)
7293 bnxt_setup_msix(bp);
7295 bnxt_setup_inta(bp);
7297 rc = bnxt_set_real_num_queues(bp);
7301 #ifdef CONFIG_RFS_ACCEL
7302 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7304 return bp->hw_resc.max_rsscos_ctxs;
7307 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7309 return bp->hw_resc.max_vnics;
7313 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7315 return bp->hw_resc.max_stat_ctxs;
7318 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7320 return bp->hw_resc.max_cp_rings;
7323 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7325 unsigned int cp = bp->hw_resc.max_cp_rings;
7327 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7328 cp -= bnxt_get_ulp_msix_num(bp);
7333 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7335 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7337 if (bp->flags & BNXT_FLAG_CHIP_P5)
7338 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7340 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7343 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7345 bp->hw_resc.max_irqs = max_irqs;
7348 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7352 cp = bnxt_get_max_func_cp_rings_for_en(bp);
7353 if (bp->flags & BNXT_FLAG_CHIP_P5)
7354 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7356 return cp - bp->cp_nr_rings;
7359 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7363 stat = bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_ulp_stat_ctxs(bp);
7364 stat -= bp->cp_nr_rings;
7368 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7370 int max_cp = bnxt_get_max_func_cp_rings(bp);
7371 int max_irq = bnxt_get_max_func_irqs(bp);
7372 int total_req = bp->cp_nr_rings + num;
7373 int max_idx, avail_msix;
7375 max_idx = bp->total_irqs;
7376 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7377 max_idx = min_t(int, bp->total_irqs, max_cp);
7378 avail_msix = max_idx - bp->cp_nr_rings;
7379 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7382 if (max_irq < total_req) {
7383 num = max_irq - bp->cp_nr_rings;
7390 static int bnxt_get_num_msix(struct bnxt *bp)
7392 if (!BNXT_NEW_RM(bp))
7393 return bnxt_get_max_func_irqs(bp);
7395 return bnxt_nq_rings_in_use(bp);
7398 static int bnxt_init_msix(struct bnxt *bp)
7400 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7401 struct msix_entry *msix_ent;
7403 total_vecs = bnxt_get_num_msix(bp);
7404 max = bnxt_get_max_func_irqs(bp);
7405 if (total_vecs > max)
7411 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7415 for (i = 0; i < total_vecs; i++) {
7416 msix_ent[i].entry = i;
7417 msix_ent[i].vector = 0;
7420 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7423 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7424 ulp_msix = bnxt_get_ulp_msix_num(bp);
7425 if (total_vecs < 0 || total_vecs < ulp_msix) {
7427 goto msix_setup_exit;
7430 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7432 for (i = 0; i < total_vecs; i++)
7433 bp->irq_tbl[i].vector = msix_ent[i].vector;
7435 bp->total_irqs = total_vecs;
7436 /* Trim rings based upon num of vectors allocated */
7437 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7438 total_vecs - ulp_msix, min == 1);
7440 goto msix_setup_exit;
7442 bp->cp_nr_rings = (min == 1) ?
7443 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7444 bp->tx_nr_rings + bp->rx_nr_rings;
7448 goto msix_setup_exit;
7450 bp->flags |= BNXT_FLAG_USING_MSIX;
7455 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7458 pci_disable_msix(bp->pdev);
7463 static int bnxt_init_inta(struct bnxt *bp)
7465 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7470 bp->rx_nr_rings = 1;
7471 bp->tx_nr_rings = 1;
7472 bp->cp_nr_rings = 1;
7473 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7474 bp->irq_tbl[0].vector = bp->pdev->irq;
7478 static int bnxt_init_int_mode(struct bnxt *bp)
7482 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7483 rc = bnxt_init_msix(bp);
7485 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7486 /* fallback to INTA */
7487 rc = bnxt_init_inta(bp);
7492 static void bnxt_clear_int_mode(struct bnxt *bp)
7494 if (bp->flags & BNXT_FLAG_USING_MSIX)
7495 pci_disable_msix(bp->pdev);
7499 bp->flags &= ~BNXT_FLAG_USING_MSIX;
7502 int bnxt_reserve_rings(struct bnxt *bp)
7504 int tcs = netdev_get_num_tc(bp->dev);
7505 bool reinit_irq = false;
7508 if (!bnxt_need_reserve_rings(bp))
7511 if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
7512 bnxt_ulp_irq_stop(bp);
7513 bnxt_clear_int_mode(bp);
7516 rc = __bnxt_reserve_rings(bp);
7519 rc = bnxt_init_int_mode(bp);
7520 bnxt_ulp_irq_restart(bp, rc);
7523 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7526 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7527 netdev_err(bp->dev, "tx ring reservation failure\n");
7528 netdev_reset_tc(bp->dev);
7529 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7535 static void bnxt_free_irq(struct bnxt *bp)
7537 struct bnxt_irq *irq;
7540 #ifdef CONFIG_RFS_ACCEL
7541 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7542 bp->dev->rx_cpu_rmap = NULL;
7544 if (!bp->irq_tbl || !bp->bnapi)
7547 for (i = 0; i < bp->cp_nr_rings; i++) {
7548 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7550 irq = &bp->irq_tbl[map_idx];
7551 if (irq->requested) {
7552 if (irq->have_cpumask) {
7553 irq_set_affinity_hint(irq->vector, NULL);
7554 free_cpumask_var(irq->cpu_mask);
7555 irq->have_cpumask = 0;
7557 free_irq(irq->vector, bp->bnapi[i]);
7564 static int bnxt_request_irq(struct bnxt *bp)
7567 unsigned long flags = 0;
7568 #ifdef CONFIG_RFS_ACCEL
7569 struct cpu_rmap *rmap;
7572 rc = bnxt_setup_int_mode(bp);
7574 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7578 #ifdef CONFIG_RFS_ACCEL
7579 rmap = bp->dev->rx_cpu_rmap;
7581 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7582 flags = IRQF_SHARED;
7584 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7585 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7586 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7588 #ifdef CONFIG_RFS_ACCEL
7589 if (rmap && bp->bnapi[i]->rx_ring) {
7590 rc = irq_cpu_rmap_add(rmap, irq->vector);
7592 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7597 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7604 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7605 int numa_node = dev_to_node(&bp->pdev->dev);
7607 irq->have_cpumask = 1;
7608 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7610 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7612 netdev_warn(bp->dev,
7613 "Set affinity failed, IRQ = %d\n",
7622 static void bnxt_del_napi(struct bnxt *bp)
7629 for (i = 0; i < bp->cp_nr_rings; i++) {
7630 struct bnxt_napi *bnapi = bp->bnapi[i];
7632 napi_hash_del(&bnapi->napi);
7633 netif_napi_del(&bnapi->napi);
7635 /* We called napi_hash_del() before netif_napi_del(), we need
7636 * to respect an RCU grace period before freeing napi structures.
7641 static void bnxt_init_napi(struct bnxt *bp)
7644 unsigned int cp_nr_rings = bp->cp_nr_rings;
7645 struct bnxt_napi *bnapi;
7647 if (bp->flags & BNXT_FLAG_USING_MSIX) {
7648 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7650 if (bp->flags & BNXT_FLAG_CHIP_P5)
7651 poll_fn = bnxt_poll_p5;
7652 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7654 for (i = 0; i < cp_nr_rings; i++) {
7655 bnapi = bp->bnapi[i];
7656 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7658 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7659 bnapi = bp->bnapi[cp_nr_rings];
7660 netif_napi_add(bp->dev, &bnapi->napi,
7661 bnxt_poll_nitroa0, 64);
7664 bnapi = bp->bnapi[0];
7665 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7669 static void bnxt_disable_napi(struct bnxt *bp)
7676 for (i = 0; i < bp->cp_nr_rings; i++) {
7677 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7679 if (bp->bnapi[i]->rx_ring)
7680 cancel_work_sync(&cpr->dim.work);
7682 napi_disable(&bp->bnapi[i]->napi);
7686 static void bnxt_enable_napi(struct bnxt *bp)
7690 for (i = 0; i < bp->cp_nr_rings; i++) {
7691 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7692 bp->bnapi[i]->in_reset = false;
7694 if (bp->bnapi[i]->rx_ring) {
7695 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7696 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7698 napi_enable(&bp->bnapi[i]->napi);
7702 void bnxt_tx_disable(struct bnxt *bp)
7705 struct bnxt_tx_ring_info *txr;
7708 for (i = 0; i < bp->tx_nr_rings; i++) {
7709 txr = &bp->tx_ring[i];
7710 txr->dev_state = BNXT_DEV_STATE_CLOSING;
7713 /* Stop all TX queues */
7714 netif_tx_disable(bp->dev);
7715 netif_carrier_off(bp->dev);
7718 void bnxt_tx_enable(struct bnxt *bp)
7721 struct bnxt_tx_ring_info *txr;
7723 for (i = 0; i < bp->tx_nr_rings; i++) {
7724 txr = &bp->tx_ring[i];
7727 netif_tx_wake_all_queues(bp->dev);
7728 if (bp->link_info.link_up)
7729 netif_carrier_on(bp->dev);
7732 static void bnxt_report_link(struct bnxt *bp)
7734 if (bp->link_info.link_up) {
7736 const char *flow_ctrl;
7740 netif_carrier_on(bp->dev);
7741 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7745 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7746 flow_ctrl = "ON - receive & transmit";
7747 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7748 flow_ctrl = "ON - transmit";
7749 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7750 flow_ctrl = "ON - receive";
7753 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7754 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7755 speed, duplex, flow_ctrl);
7756 if (bp->flags & BNXT_FLAG_EEE_CAP)
7757 netdev_info(bp->dev, "EEE is %s\n",
7758 bp->eee.eee_active ? "active" :
7760 fec = bp->link_info.fec_cfg;
7761 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7762 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7763 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7764 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7765 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7767 netif_carrier_off(bp->dev);
7768 netdev_err(bp->dev, "NIC Link is Down\n");
7772 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7775 struct hwrm_port_phy_qcaps_input req = {0};
7776 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7777 struct bnxt_link_info *link_info = &bp->link_info;
7779 if (bp->hwrm_spec_code < 0x10201)
7782 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7784 mutex_lock(&bp->hwrm_cmd_lock);
7785 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7787 goto hwrm_phy_qcaps_exit;
7789 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7790 struct ethtool_eee *eee = &bp->eee;
7791 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7793 bp->flags |= BNXT_FLAG_EEE_CAP;
7794 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7795 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7796 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7797 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7798 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7800 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7802 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7804 if (resp->supported_speeds_auto_mode)
7805 link_info->support_auto_speeds =
7806 le16_to_cpu(resp->supported_speeds_auto_mode);
7808 bp->port_count = resp->port_cnt;
7810 hwrm_phy_qcaps_exit:
7811 mutex_unlock(&bp->hwrm_cmd_lock);
7815 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7818 struct bnxt_link_info *link_info = &bp->link_info;
7819 struct hwrm_port_phy_qcfg_input req = {0};
7820 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7821 u8 link_up = link_info->link_up;
7824 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
7826 mutex_lock(&bp->hwrm_cmd_lock);
7827 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7829 mutex_unlock(&bp->hwrm_cmd_lock);
7833 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
7834 link_info->phy_link_status = resp->link;
7835 link_info->duplex = resp->duplex_cfg;
7836 if (bp->hwrm_spec_code >= 0x10800)
7837 link_info->duplex = resp->duplex_state;
7838 link_info->pause = resp->pause;
7839 link_info->auto_mode = resp->auto_mode;
7840 link_info->auto_pause_setting = resp->auto_pause;
7841 link_info->lp_pause = resp->link_partner_adv_pause;
7842 link_info->force_pause_setting = resp->force_pause;
7843 link_info->duplex_setting = resp->duplex_cfg;
7844 if (link_info->phy_link_status == BNXT_LINK_LINK)
7845 link_info->link_speed = le16_to_cpu(resp->link_speed);
7847 link_info->link_speed = 0;
7848 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
7849 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
7850 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
7851 link_info->lp_auto_link_speeds =
7852 le16_to_cpu(resp->link_partner_adv_speeds);
7853 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
7854 link_info->phy_ver[0] = resp->phy_maj;
7855 link_info->phy_ver[1] = resp->phy_min;
7856 link_info->phy_ver[2] = resp->phy_bld;
7857 link_info->media_type = resp->media_type;
7858 link_info->phy_type = resp->phy_type;
7859 link_info->transceiver = resp->xcvr_pkg_type;
7860 link_info->phy_addr = resp->eee_config_phy_addr &
7861 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
7862 link_info->module_status = resp->module_status;
7864 if (bp->flags & BNXT_FLAG_EEE_CAP) {
7865 struct ethtool_eee *eee = &bp->eee;
7868 eee->eee_active = 0;
7869 if (resp->eee_config_phy_addr &
7870 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
7871 eee->eee_active = 1;
7872 fw_speeds = le16_to_cpu(
7873 resp->link_partner_adv_eee_link_speed_mask);
7874 eee->lp_advertised =
7875 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7878 /* Pull initial EEE config */
7879 if (!chng_link_state) {
7880 if (resp->eee_config_phy_addr &
7881 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
7882 eee->eee_enabled = 1;
7884 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
7886 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7888 if (resp->eee_config_phy_addr &
7889 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
7892 eee->tx_lpi_enabled = 1;
7893 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
7894 eee->tx_lpi_timer = le32_to_cpu(tmr) &
7895 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
7900 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
7901 if (bp->hwrm_spec_code >= 0x10504)
7902 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
7904 /* TODO: need to add more logic to report VF link */
7905 if (chng_link_state) {
7906 if (link_info->phy_link_status == BNXT_LINK_LINK)
7907 link_info->link_up = 1;
7909 link_info->link_up = 0;
7910 if (link_up != link_info->link_up)
7911 bnxt_report_link(bp);
7913 /* alwasy link down if not require to update link state */
7914 link_info->link_up = 0;
7916 mutex_unlock(&bp->hwrm_cmd_lock);
7918 if (!BNXT_SINGLE_PF(bp))
7921 diff = link_info->support_auto_speeds ^ link_info->advertising;
7922 if ((link_info->support_auto_speeds | diff) !=
7923 link_info->support_auto_speeds) {
7924 /* An advertised speed is no longer supported, so we need to
7925 * update the advertisement settings. Caller holds RTNL
7926 * so we can modify link settings.
7928 link_info->advertising = link_info->support_auto_speeds;
7929 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
7930 bnxt_hwrm_set_link_setting(bp, true, false);
7935 static void bnxt_get_port_module_status(struct bnxt *bp)
7937 struct bnxt_link_info *link_info = &bp->link_info;
7938 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
7941 if (bnxt_update_link(bp, true))
7944 module_status = link_info->module_status;
7945 switch (module_status) {
7946 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
7947 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
7948 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
7949 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
7951 if (bp->hwrm_spec_code >= 0x10201) {
7952 netdev_warn(bp->dev, "Module part number %s\n",
7953 resp->phy_vendor_partnumber);
7955 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
7956 netdev_warn(bp->dev, "TX is disabled\n");
7957 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
7958 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
7963 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
7965 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
7966 if (bp->hwrm_spec_code >= 0x10201)
7968 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
7969 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7970 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
7971 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
7972 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
7974 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7976 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7977 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
7978 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
7979 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
7981 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
7982 if (bp->hwrm_spec_code >= 0x10201) {
7983 req->auto_pause = req->force_pause;
7984 req->enables |= cpu_to_le32(
7985 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7990 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
7991 struct hwrm_port_phy_cfg_input *req)
7993 u8 autoneg = bp->link_info.autoneg;
7994 u16 fw_link_speed = bp->link_info.req_link_speed;
7995 u16 advertising = bp->link_info.advertising;
7997 if (autoneg & BNXT_AUTONEG_SPEED) {
7999 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
8001 req->enables |= cpu_to_le32(
8002 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8003 req->auto_link_speed_mask = cpu_to_le16(advertising);
8005 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8007 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8009 req->force_link_speed = cpu_to_le16(fw_link_speed);
8010 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8013 /* tell chimp that the setting takes effect immediately */
8014 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8017 int bnxt_hwrm_set_pause(struct bnxt *bp)
8019 struct hwrm_port_phy_cfg_input req = {0};
8022 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8023 bnxt_hwrm_set_pause_common(bp, &req);
8025 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8026 bp->link_info.force_link_chng)
8027 bnxt_hwrm_set_link_common(bp, &req);
8029 mutex_lock(&bp->hwrm_cmd_lock);
8030 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8031 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8032 /* since changing of pause setting doesn't trigger any link
8033 * change event, the driver needs to update the current pause
8034 * result upon successfully return of the phy_cfg command
8036 bp->link_info.pause =
8037 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8038 bp->link_info.auto_pause_setting = 0;
8039 if (!bp->link_info.force_link_chng)
8040 bnxt_report_link(bp);
8042 bp->link_info.force_link_chng = false;
8043 mutex_unlock(&bp->hwrm_cmd_lock);
8047 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8048 struct hwrm_port_phy_cfg_input *req)
8050 struct ethtool_eee *eee = &bp->eee;
8052 if (eee->eee_enabled) {
8054 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8056 if (eee->tx_lpi_enabled)
8057 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8059 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8061 req->flags |= cpu_to_le32(flags);
8062 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8063 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8064 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8066 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8070 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8072 struct hwrm_port_phy_cfg_input req = {0};
8074 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8076 bnxt_hwrm_set_pause_common(bp, &req);
8078 bnxt_hwrm_set_link_common(bp, &req);
8081 bnxt_hwrm_set_eee(bp, &req);
8082 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8085 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8087 struct hwrm_port_phy_cfg_input req = {0};
8089 if (!BNXT_SINGLE_PF(bp))
8092 if (pci_num_vf(bp->pdev))
8095 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8096 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8097 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8100 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8102 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8103 struct hwrm_func_drv_if_change_input req = {0};
8104 bool resc_reinit = false;
8107 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8110 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8112 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8113 mutex_lock(&bp->hwrm_cmd_lock);
8114 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8115 if (!rc && (resp->flags &
8116 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8118 mutex_unlock(&bp->hwrm_cmd_lock);
8120 if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8121 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8123 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8124 hw_resc->resv_cp_rings = 0;
8125 hw_resc->resv_stat_ctxs = 0;
8126 hw_resc->resv_irqs = 0;
8127 hw_resc->resv_tx_rings = 0;
8128 hw_resc->resv_rx_rings = 0;
8129 hw_resc->resv_hw_ring_grps = 0;
8130 hw_resc->resv_vnics = 0;
8131 bp->tx_nr_rings = 0;
8132 bp->rx_nr_rings = 0;
8137 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8139 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8140 struct hwrm_port_led_qcaps_input req = {0};
8141 struct bnxt_pf_info *pf = &bp->pf;
8144 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8147 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8148 req.port_id = cpu_to_le16(pf->port_id);
8149 mutex_lock(&bp->hwrm_cmd_lock);
8150 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8152 mutex_unlock(&bp->hwrm_cmd_lock);
8155 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8158 bp->num_leds = resp->num_leds;
8159 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8161 for (i = 0; i < bp->num_leds; i++) {
8162 struct bnxt_led_info *led = &bp->leds[i];
8163 __le16 caps = led->led_state_caps;
8165 if (!led->led_group_id ||
8166 !BNXT_LED_ALT_BLINK_CAP(caps)) {
8172 mutex_unlock(&bp->hwrm_cmd_lock);
8176 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8178 struct hwrm_wol_filter_alloc_input req = {0};
8179 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8182 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8183 req.port_id = cpu_to_le16(bp->pf.port_id);
8184 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8185 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8186 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8187 mutex_lock(&bp->hwrm_cmd_lock);
8188 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8190 bp->wol_filter_id = resp->wol_filter_id;
8191 mutex_unlock(&bp->hwrm_cmd_lock);
8195 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8197 struct hwrm_wol_filter_free_input req = {0};
8200 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8201 req.port_id = cpu_to_le16(bp->pf.port_id);
8202 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8203 req.wol_filter_id = bp->wol_filter_id;
8204 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8208 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8210 struct hwrm_wol_filter_qcfg_input req = {0};
8211 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8212 u16 next_handle = 0;
8215 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8216 req.port_id = cpu_to_le16(bp->pf.port_id);
8217 req.handle = cpu_to_le16(handle);
8218 mutex_lock(&bp->hwrm_cmd_lock);
8219 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8221 next_handle = le16_to_cpu(resp->next_handle);
8222 if (next_handle != 0) {
8223 if (resp->wol_type ==
8224 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8226 bp->wol_filter_id = resp->wol_filter_id;
8230 mutex_unlock(&bp->hwrm_cmd_lock);
8234 static void bnxt_get_wol_settings(struct bnxt *bp)
8238 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8242 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8243 } while (handle && handle != 0xffff);
8246 #ifdef CONFIG_BNXT_HWMON
8247 static ssize_t bnxt_show_temp(struct device *dev,
8248 struct device_attribute *devattr, char *buf)
8250 struct hwrm_temp_monitor_query_input req = {0};
8251 struct hwrm_temp_monitor_query_output *resp;
8252 struct bnxt *bp = dev_get_drvdata(dev);
8255 resp = bp->hwrm_cmd_resp_addr;
8256 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8257 mutex_lock(&bp->hwrm_cmd_lock);
8258 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8259 temp = resp->temp * 1000; /* display millidegree */
8260 mutex_unlock(&bp->hwrm_cmd_lock);
8262 return sprintf(buf, "%u\n", temp);
8264 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8266 static struct attribute *bnxt_attrs[] = {
8267 &sensor_dev_attr_temp1_input.dev_attr.attr,
8270 ATTRIBUTE_GROUPS(bnxt);
8272 static void bnxt_hwmon_close(struct bnxt *bp)
8274 if (bp->hwmon_dev) {
8275 hwmon_device_unregister(bp->hwmon_dev);
8276 bp->hwmon_dev = NULL;
8280 static void bnxt_hwmon_open(struct bnxt *bp)
8282 struct pci_dev *pdev = bp->pdev;
8284 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8285 DRV_MODULE_NAME, bp,
8287 if (IS_ERR(bp->hwmon_dev)) {
8288 bp->hwmon_dev = NULL;
8289 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8293 static void bnxt_hwmon_close(struct bnxt *bp)
8297 static void bnxt_hwmon_open(struct bnxt *bp)
8302 static bool bnxt_eee_config_ok(struct bnxt *bp)
8304 struct ethtool_eee *eee = &bp->eee;
8305 struct bnxt_link_info *link_info = &bp->link_info;
8307 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8310 if (eee->eee_enabled) {
8312 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8314 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8315 eee->eee_enabled = 0;
8318 if (eee->advertised & ~advertising) {
8319 eee->advertised = advertising & eee->supported;
8326 static int bnxt_update_phy_setting(struct bnxt *bp)
8329 bool update_link = false;
8330 bool update_pause = false;
8331 bool update_eee = false;
8332 struct bnxt_link_info *link_info = &bp->link_info;
8334 rc = bnxt_update_link(bp, true);
8336 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8340 if (!BNXT_SINGLE_PF(bp))
8343 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8344 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8345 link_info->req_flow_ctrl)
8346 update_pause = true;
8347 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8348 link_info->force_pause_setting != link_info->req_flow_ctrl)
8349 update_pause = true;
8350 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8351 if (BNXT_AUTO_MODE(link_info->auto_mode))
8353 if (link_info->req_link_speed != link_info->force_link_speed)
8355 if (link_info->req_duplex != link_info->duplex_setting)
8358 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8360 if (link_info->advertising != link_info->auto_link_speeds)
8364 /* The last close may have shutdown the link, so need to call
8365 * PHY_CFG to bring it back up.
8367 if (!netif_carrier_ok(bp->dev))
8370 if (!bnxt_eee_config_ok(bp))
8374 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8375 else if (update_pause)
8376 rc = bnxt_hwrm_set_pause(bp);
8378 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8386 /* Common routine to pre-map certain register block to different GRC window.
8387 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8388 * in PF and 3 windows in VF that can be customized to map in different
8391 static void bnxt_preset_reg_win(struct bnxt *bp)
8394 /* CAG registers map to GRC window #4 */
8395 writel(BNXT_CAG_REG_BASE,
8396 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8400 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8402 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8406 bnxt_preset_reg_win(bp);
8407 netif_carrier_off(bp->dev);
8409 /* Reserve rings now if none were reserved at driver probe. */
8410 rc = bnxt_init_dflt_ring_mode(bp);
8412 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8416 rc = bnxt_reserve_rings(bp);
8419 if ((bp->flags & BNXT_FLAG_RFS) &&
8420 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8421 /* disable RFS if falling back to INTA */
8422 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8423 bp->flags &= ~BNXT_FLAG_RFS;
8426 rc = bnxt_alloc_mem(bp, irq_re_init);
8428 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8429 goto open_err_free_mem;
8434 rc = bnxt_request_irq(bp);
8436 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8441 bnxt_enable_napi(bp);
8442 bnxt_debug_dev_init(bp);
8444 rc = bnxt_init_nic(bp, irq_re_init);
8446 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8451 mutex_lock(&bp->link_lock);
8452 rc = bnxt_update_phy_setting(bp);
8453 mutex_unlock(&bp->link_lock);
8455 netdev_warn(bp->dev, "failed to update phy settings\n");
8456 if (BNXT_SINGLE_PF(bp)) {
8457 bp->link_info.phy_retry = true;
8458 bp->link_info.phy_retry_expires =
8465 udp_tunnel_get_rx_info(bp->dev);
8467 set_bit(BNXT_STATE_OPEN, &bp->state);
8468 bnxt_enable_int(bp);
8469 /* Enable TX queues */
8471 mod_timer(&bp->timer, jiffies + bp->current_interval);
8472 /* Poll link status and check for SFP+ module status */
8473 bnxt_get_port_module_status(bp);
8475 /* VF-reps may need to be re-opened after the PF is re-opened */
8477 bnxt_vf_reps_open(bp);
8481 bnxt_debug_dev_exit(bp);
8482 bnxt_disable_napi(bp);
8490 bnxt_free_mem(bp, true);
8494 /* rtnl_lock held */
8495 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8499 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8501 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8507 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8508 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
8511 int bnxt_half_open_nic(struct bnxt *bp)
8515 rc = bnxt_alloc_mem(bp, false);
8517 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8520 rc = bnxt_init_nic(bp, false);
8522 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8529 bnxt_free_mem(bp, false);
8534 /* rtnl_lock held, this call can only be made after a previous successful
8535 * call to bnxt_half_open_nic().
8537 void bnxt_half_close_nic(struct bnxt *bp)
8539 bnxt_hwrm_resource_free(bp, false, false);
8541 bnxt_free_mem(bp, false);
8544 static int bnxt_open(struct net_device *dev)
8546 struct bnxt *bp = netdev_priv(dev);
8549 bnxt_hwrm_if_change(bp, true);
8550 rc = __bnxt_open_nic(bp, true, true);
8552 bnxt_hwrm_if_change(bp, false);
8554 bnxt_hwmon_open(bp);
8559 static bool bnxt_drv_busy(struct bnxt *bp)
8561 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8562 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8565 static void bnxt_get_ring_stats(struct bnxt *bp,
8566 struct rtnl_link_stats64 *stats);
8568 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8571 /* Close the VF-reps before closing PF */
8573 bnxt_vf_reps_close(bp);
8575 /* Change device state to avoid TX queue wake up's */
8576 bnxt_tx_disable(bp);
8578 clear_bit(BNXT_STATE_OPEN, &bp->state);
8579 smp_mb__after_atomic();
8580 while (bnxt_drv_busy(bp))
8583 /* Flush rings and and disable interrupts */
8584 bnxt_shutdown_nic(bp, irq_re_init);
8586 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8588 bnxt_debug_dev_exit(bp);
8589 bnxt_disable_napi(bp);
8590 del_timer_sync(&bp->timer);
8593 /* Save ring stats before shutdown */
8595 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8600 bnxt_free_mem(bp, irq_re_init);
8603 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8607 #ifdef CONFIG_BNXT_SRIOV
8608 if (bp->sriov_cfg) {
8609 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8611 BNXT_SRIOV_CFG_WAIT_TMO);
8613 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8616 __bnxt_close_nic(bp, irq_re_init, link_re_init);
8620 static int bnxt_close(struct net_device *dev)
8622 struct bnxt *bp = netdev_priv(dev);
8624 bnxt_hwmon_close(bp);
8625 bnxt_close_nic(bp, true, true);
8626 bnxt_hwrm_shutdown_link(bp);
8627 bnxt_hwrm_if_change(bp, false);
8631 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
8634 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
8635 struct hwrm_port_phy_mdio_read_input req = {0};
8638 if (bp->hwrm_spec_code < 0x10a00)
8641 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
8642 req.port_id = cpu_to_le16(bp->pf.port_id);
8643 req.phy_addr = phy_addr;
8644 req.reg_addr = cpu_to_le16(reg & 0x1f);
8645 if (bp->link_info.support_speeds & BNXT_LINK_SPEED_MSK_10GB) {
8647 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8648 req.dev_addr = mdio_phy_id_devad(phy_addr);
8649 req.reg_addr = cpu_to_le16(reg);
8652 mutex_lock(&bp->hwrm_cmd_lock);
8653 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8655 *val = le16_to_cpu(resp->reg_data);
8656 mutex_unlock(&bp->hwrm_cmd_lock);
8660 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
8663 struct hwrm_port_phy_mdio_write_input req = {0};
8665 if (bp->hwrm_spec_code < 0x10a00)
8668 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
8669 req.port_id = cpu_to_le16(bp->pf.port_id);
8670 req.phy_addr = phy_addr;
8671 req.reg_addr = cpu_to_le16(reg & 0x1f);
8672 if (bp->link_info.support_speeds & BNXT_LINK_SPEED_MSK_10GB) {
8674 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8675 req.dev_addr = mdio_phy_id_devad(phy_addr);
8676 req.reg_addr = cpu_to_le16(reg);
8678 req.reg_data = cpu_to_le16(val);
8680 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8683 /* rtnl_lock held */
8684 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8686 struct mii_ioctl_data *mdio = if_mii(ifr);
8687 struct bnxt *bp = netdev_priv(dev);
8692 mdio->phy_id = bp->link_info.phy_addr;
8698 if (!netif_running(dev))
8701 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
8703 mdio->val_out = mii_regval;
8708 if (!netif_running(dev))
8711 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
8721 static void bnxt_get_ring_stats(struct bnxt *bp,
8722 struct rtnl_link_stats64 *stats)
8727 for (i = 0; i < bp->cp_nr_rings; i++) {
8728 struct bnxt_napi *bnapi = bp->bnapi[i];
8729 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8730 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8732 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8733 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8734 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8736 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8737 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8738 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8740 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8741 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8742 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8744 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8745 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8746 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8748 stats->rx_missed_errors +=
8749 le64_to_cpu(hw_stats->rx_discard_pkts);
8751 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8753 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8757 static void bnxt_add_prev_stats(struct bnxt *bp,
8758 struct rtnl_link_stats64 *stats)
8760 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8762 stats->rx_packets += prev_stats->rx_packets;
8763 stats->tx_packets += prev_stats->tx_packets;
8764 stats->rx_bytes += prev_stats->rx_bytes;
8765 stats->tx_bytes += prev_stats->tx_bytes;
8766 stats->rx_missed_errors += prev_stats->rx_missed_errors;
8767 stats->multicast += prev_stats->multicast;
8768 stats->tx_dropped += prev_stats->tx_dropped;
8772 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8774 struct bnxt *bp = netdev_priv(dev);
8776 set_bit(BNXT_STATE_READ_STATS, &bp->state);
8777 /* Make sure bnxt_close_nic() sees that we are reading stats before
8778 * we check the BNXT_STATE_OPEN flag.
8780 smp_mb__after_atomic();
8781 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8782 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8783 *stats = bp->net_stats_prev;
8787 bnxt_get_ring_stats(bp, stats);
8788 bnxt_add_prev_stats(bp, stats);
8790 if (bp->flags & BNXT_FLAG_PORT_STATS) {
8791 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8792 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8794 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8795 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8796 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8797 le64_to_cpu(rx->rx_ovrsz_frames) +
8798 le64_to_cpu(rx->rx_runt_frames);
8799 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8800 le64_to_cpu(rx->rx_jbr_frames);
8801 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8802 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8803 stats->tx_errors = le64_to_cpu(tx->tx_err);
8805 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8808 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8810 struct net_device *dev = bp->dev;
8811 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8812 struct netdev_hw_addr *ha;
8815 bool update = false;
8818 netdev_for_each_mc_addr(ha, dev) {
8819 if (mc_count >= BNXT_MAX_MC_ADDRS) {
8820 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8821 vnic->mc_list_count = 0;
8825 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
8826 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
8833 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
8835 if (mc_count != vnic->mc_list_count) {
8836 vnic->mc_list_count = mc_count;
8842 static bool bnxt_uc_list_updated(struct bnxt *bp)
8844 struct net_device *dev = bp->dev;
8845 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8846 struct netdev_hw_addr *ha;
8849 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
8852 netdev_for_each_uc_addr(ha, dev) {
8853 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
8861 static void bnxt_set_rx_mode(struct net_device *dev)
8863 struct bnxt *bp = netdev_priv(dev);
8864 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8865 u32 mask = vnic->rx_mask;
8866 bool mc_update = false;
8869 if (!netif_running(dev))
8872 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
8873 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
8874 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
8875 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
8877 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
8878 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8880 uc_update = bnxt_uc_list_updated(bp);
8882 if (dev->flags & IFF_BROADCAST)
8883 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8884 if (dev->flags & IFF_ALLMULTI) {
8885 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8886 vnic->mc_list_count = 0;
8888 mc_update = bnxt_mc_list_updated(bp, &mask);
8891 if (mask != vnic->rx_mask || uc_update || mc_update) {
8892 vnic->rx_mask = mask;
8894 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
8895 bnxt_queue_sp_work(bp);
8899 static int bnxt_cfg_rx_mode(struct bnxt *bp)
8901 struct net_device *dev = bp->dev;
8902 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8903 struct netdev_hw_addr *ha;
8907 netif_addr_lock_bh(dev);
8908 uc_update = bnxt_uc_list_updated(bp);
8909 netif_addr_unlock_bh(dev);
8914 mutex_lock(&bp->hwrm_cmd_lock);
8915 for (i = 1; i < vnic->uc_filter_count; i++) {
8916 struct hwrm_cfa_l2_filter_free_input req = {0};
8918 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
8921 req.l2_filter_id = vnic->fw_l2_filter_id[i];
8923 rc = _hwrm_send_message(bp, &req, sizeof(req),
8926 mutex_unlock(&bp->hwrm_cmd_lock);
8928 vnic->uc_filter_count = 1;
8930 netif_addr_lock_bh(dev);
8931 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
8932 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8934 netdev_for_each_uc_addr(ha, dev) {
8935 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
8937 vnic->uc_filter_count++;
8940 netif_addr_unlock_bh(dev);
8942 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
8943 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
8945 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
8947 vnic->uc_filter_count = i;
8953 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
8955 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
8961 static bool bnxt_can_reserve_rings(struct bnxt *bp)
8963 #ifdef CONFIG_BNXT_SRIOV
8964 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
8965 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8967 /* No minimum rings were provisioned by the PF. Don't
8968 * reserve rings by default when device is down.
8970 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
8973 if (!netif_running(bp->dev))
8980 /* If the chip and firmware supports RFS */
8981 static bool bnxt_rfs_supported(struct bnxt *bp)
8983 if (bp->flags & BNXT_FLAG_CHIP_P5)
8985 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
8987 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8992 /* If runtime conditions support RFS */
8993 static bool bnxt_rfs_capable(struct bnxt *bp)
8995 #ifdef CONFIG_RFS_ACCEL
8996 int vnics, max_vnics, max_rss_ctxs;
8998 if (bp->flags & BNXT_FLAG_CHIP_P5)
9000 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
9003 vnics = 1 + bp->rx_nr_rings;
9004 max_vnics = bnxt_get_max_func_vnics(bp);
9005 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9007 /* RSS contexts not a limiting factor */
9008 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9009 max_rss_ctxs = max_vnics;
9010 if (vnics > max_vnics || vnics > max_rss_ctxs) {
9011 if (bp->rx_nr_rings > 1)
9012 netdev_warn(bp->dev,
9013 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9014 min(max_rss_ctxs - 1, max_vnics - 1));
9018 if (!BNXT_NEW_RM(bp))
9021 if (vnics == bp->hw_resc.resv_vnics)
9024 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9025 if (vnics <= bp->hw_resc.resv_vnics)
9028 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9029 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9036 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9037 netdev_features_t features)
9039 struct bnxt *bp = netdev_priv(dev);
9041 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9042 features &= ~NETIF_F_NTUPLE;
9044 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9045 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9047 if (!(features & NETIF_F_GRO))
9048 features &= ~NETIF_F_GRO_HW;
9050 if (features & NETIF_F_GRO_HW)
9051 features &= ~NETIF_F_LRO;
9053 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
9054 * turned on or off together.
9056 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
9057 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
9058 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9059 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9060 NETIF_F_HW_VLAN_STAG_RX);
9062 features |= NETIF_F_HW_VLAN_CTAG_RX |
9063 NETIF_F_HW_VLAN_STAG_RX;
9065 #ifdef CONFIG_BNXT_SRIOV
9068 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9069 NETIF_F_HW_VLAN_STAG_RX);
9076 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9078 struct bnxt *bp = netdev_priv(dev);
9079 u32 flags = bp->flags;
9082 bool re_init = false;
9083 bool update_tpa = false;
9085 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9086 if (features & NETIF_F_GRO_HW)
9087 flags |= BNXT_FLAG_GRO;
9088 else if (features & NETIF_F_LRO)
9089 flags |= BNXT_FLAG_LRO;
9091 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9092 flags &= ~BNXT_FLAG_TPA;
9094 if (features & NETIF_F_HW_VLAN_CTAG_RX)
9095 flags |= BNXT_FLAG_STRIP_VLAN;
9097 if (features & NETIF_F_NTUPLE)
9098 flags |= BNXT_FLAG_RFS;
9100 changes = flags ^ bp->flags;
9101 if (changes & BNXT_FLAG_TPA) {
9103 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9104 (flags & BNXT_FLAG_TPA) == 0)
9108 if (changes & ~BNXT_FLAG_TPA)
9111 if (flags != bp->flags) {
9112 u32 old_flags = bp->flags;
9116 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9118 bnxt_set_ring_params(bp);
9123 bnxt_close_nic(bp, false, false);
9125 bnxt_set_ring_params(bp);
9127 return bnxt_open_nic(bp, false, false);
9130 rc = bnxt_set_tpa(bp,
9131 (flags & BNXT_FLAG_TPA) ?
9134 bp->flags = old_flags;
9140 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9141 u32 ring_id, u32 *prod, u32 *cons)
9143 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9144 struct hwrm_dbg_ring_info_get_input req = {0};
9147 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9148 req.ring_type = ring_type;
9149 req.fw_ring_id = cpu_to_le32(ring_id);
9150 mutex_lock(&bp->hwrm_cmd_lock);
9151 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9153 *prod = le32_to_cpu(resp->producer_index);
9154 *cons = le32_to_cpu(resp->consumer_index);
9156 mutex_unlock(&bp->hwrm_cmd_lock);
9160 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9162 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9163 int i = bnapi->index;
9168 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9169 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9173 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9175 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9176 int i = bnapi->index;
9181 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9182 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9183 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9184 rxr->rx_sw_agg_prod);
9187 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9189 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9190 int i = bnapi->index;
9192 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9193 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9196 static void bnxt_dbg_dump_states(struct bnxt *bp)
9199 struct bnxt_napi *bnapi;
9201 for (i = 0; i < bp->cp_nr_rings; i++) {
9202 bnapi = bp->bnapi[i];
9203 if (netif_msg_drv(bp)) {
9204 bnxt_dump_tx_sw_state(bnapi);
9205 bnxt_dump_rx_sw_state(bnapi);
9206 bnxt_dump_cp_sw_state(bnapi);
9211 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9214 bnxt_dbg_dump_states(bp);
9215 if (netif_running(bp->dev)) {
9220 bnxt_close_nic(bp, false, false);
9221 rc = bnxt_open_nic(bp, false, false);
9227 static void bnxt_tx_timeout(struct net_device *dev)
9229 struct bnxt *bp = netdev_priv(dev);
9231 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
9232 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9233 bnxt_queue_sp_work(bp);
9236 static void bnxt_timer(struct timer_list *t)
9238 struct bnxt *bp = from_timer(bp, t, timer);
9239 struct net_device *dev = bp->dev;
9241 if (!netif_running(dev))
9244 if (atomic_read(&bp->intr_sem) != 0)
9245 goto bnxt_restart_timer;
9247 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9248 bp->stats_coal_ticks) {
9249 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9250 bnxt_queue_sp_work(bp);
9253 if (bnxt_tc_flower_enabled(bp)) {
9254 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9255 bnxt_queue_sp_work(bp);
9258 if (bp->link_info.phy_retry) {
9259 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9260 bp->link_info.phy_retry = 0;
9261 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9263 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9264 bnxt_queue_sp_work(bp);
9268 if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9269 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9270 bnxt_queue_sp_work(bp);
9273 mod_timer(&bp->timer, jiffies + bp->current_interval);
9276 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9278 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9279 * set. If the device is being closed, bnxt_close() may be holding
9280 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
9281 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9283 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9287 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9289 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9293 /* Only called from bnxt_sp_task() */
9294 static void bnxt_reset(struct bnxt *bp, bool silent)
9296 bnxt_rtnl_lock_sp(bp);
9297 if (test_bit(BNXT_STATE_OPEN, &bp->state))
9298 bnxt_reset_task(bp, silent);
9299 bnxt_rtnl_unlock_sp(bp);
9302 static void bnxt_chk_missed_irq(struct bnxt *bp)
9306 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9309 for (i = 0; i < bp->cp_nr_rings; i++) {
9310 struct bnxt_napi *bnapi = bp->bnapi[i];
9311 struct bnxt_cp_ring_info *cpr;
9318 cpr = &bnapi->cp_ring;
9319 for (j = 0; j < 2; j++) {
9320 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9323 if (!cpr2 || cpr2->has_more_work ||
9324 !bnxt_has_work(bp, cpr2))
9327 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9328 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9331 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9332 bnxt_dbg_hwrm_ring_info_get(bp,
9333 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9334 fw_ring_id, &val[0], &val[1]);
9340 static void bnxt_cfg_ntp_filters(struct bnxt *);
9342 static void bnxt_sp_task(struct work_struct *work)
9344 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9346 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9347 smp_mb__after_atomic();
9348 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9349 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9353 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9354 bnxt_cfg_rx_mode(bp);
9356 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9357 bnxt_cfg_ntp_filters(bp);
9358 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9359 bnxt_hwrm_exec_fwd_req(bp);
9360 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9361 bnxt_hwrm_tunnel_dst_port_alloc(
9363 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9365 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9366 bnxt_hwrm_tunnel_dst_port_free(
9367 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9369 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9370 bnxt_hwrm_tunnel_dst_port_alloc(
9372 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9374 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9375 bnxt_hwrm_tunnel_dst_port_free(
9376 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9378 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9379 bnxt_hwrm_port_qstats(bp);
9380 bnxt_hwrm_port_qstats_ext(bp);
9383 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9386 mutex_lock(&bp->link_lock);
9387 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9389 bnxt_hwrm_phy_qcaps(bp);
9391 rc = bnxt_update_link(bp, true);
9392 mutex_unlock(&bp->link_lock);
9394 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9397 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9400 mutex_lock(&bp->link_lock);
9401 rc = bnxt_update_phy_setting(bp);
9402 mutex_unlock(&bp->link_lock);
9404 netdev_warn(bp->dev, "update phy settings retry failed\n");
9406 bp->link_info.phy_retry = false;
9407 netdev_info(bp->dev, "update phy settings retry succeeded\n");
9410 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9411 mutex_lock(&bp->link_lock);
9412 bnxt_get_port_module_status(bp);
9413 mutex_unlock(&bp->link_lock);
9416 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9417 bnxt_tc_flow_stats_work(bp);
9419 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9420 bnxt_chk_missed_irq(bp);
9422 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
9423 * must be the last functions to be called before exiting.
9425 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9426 bnxt_reset(bp, false);
9428 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9429 bnxt_reset(bp, true);
9431 smp_mb__before_atomic();
9432 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9435 /* Under rtnl_lock */
9436 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9439 int max_rx, max_tx, tx_sets = 1;
9440 int tx_rings_needed, stats;
9447 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9454 tx_rings_needed = tx * tx_sets + tx_xdp;
9455 if (max_tx < tx_rings_needed)
9459 if (bp->flags & BNXT_FLAG_RFS)
9462 if (bp->flags & BNXT_FLAG_AGG_RINGS)
9464 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9466 if (BNXT_NEW_RM(bp)) {
9467 cp += bnxt_get_ulp_msix_num(bp);
9468 stats += bnxt_get_ulp_stat_ctxs(bp);
9470 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9474 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9477 pci_iounmap(pdev, bp->bar2);
9482 pci_iounmap(pdev, bp->bar1);
9487 pci_iounmap(pdev, bp->bar0);
9492 static void bnxt_cleanup_pci(struct bnxt *bp)
9494 bnxt_unmap_bars(bp, bp->pdev);
9495 pci_release_regions(bp->pdev);
9496 pci_disable_device(bp->pdev);
9499 static void bnxt_init_dflt_coal(struct bnxt *bp)
9501 struct bnxt_coal *coal;
9503 /* Tick values in micro seconds.
9504 * 1 coal_buf x bufs_per_record = 1 completion record.
9506 coal = &bp->rx_coal;
9507 coal->coal_ticks = 10;
9508 coal->coal_bufs = 30;
9509 coal->coal_ticks_irq = 1;
9510 coal->coal_bufs_irq = 2;
9511 coal->idle_thresh = 50;
9512 coal->bufs_per_record = 2;
9513 coal->budget = 64; /* NAPI budget */
9515 coal = &bp->tx_coal;
9516 coal->coal_ticks = 28;
9517 coal->coal_bufs = 30;
9518 coal->coal_ticks_irq = 2;
9519 coal->coal_bufs_irq = 2;
9520 coal->bufs_per_record = 1;
9522 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9525 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9528 struct bnxt *bp = netdev_priv(dev);
9530 SET_NETDEV_DEV(dev, &pdev->dev);
9532 /* enable device (incl. PCI PM wakeup), and bus-mastering */
9533 rc = pci_enable_device(pdev);
9535 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9539 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9541 "Cannot find PCI device base address, aborting\n");
9543 goto init_err_disable;
9546 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9548 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9549 goto init_err_disable;
9552 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9553 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9554 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9555 goto init_err_disable;
9558 pci_set_master(pdev);
9563 bp->bar0 = pci_ioremap_bar(pdev, 0);
9565 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9567 goto init_err_release;
9570 bp->bar1 = pci_ioremap_bar(pdev, 2);
9572 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9574 goto init_err_release;
9577 bp->bar2 = pci_ioremap_bar(pdev, 4);
9579 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9581 goto init_err_release;
9584 pci_enable_pcie_error_reporting(pdev);
9586 INIT_WORK(&bp->sp_task, bnxt_sp_task);
9588 spin_lock_init(&bp->ntp_fltr_lock);
9589 #if BITS_PER_LONG == 32
9590 spin_lock_init(&bp->db_lock);
9593 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9594 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9596 bnxt_init_dflt_coal(bp);
9598 timer_setup(&bp->timer, bnxt_timer, 0);
9599 bp->current_interval = BNXT_TIMER_INTERVAL;
9601 clear_bit(BNXT_STATE_OPEN, &bp->state);
9605 bnxt_unmap_bars(bp, pdev);
9606 pci_release_regions(pdev);
9609 pci_disable_device(pdev);
9615 /* rtnl_lock held */
9616 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9618 struct sockaddr *addr = p;
9619 struct bnxt *bp = netdev_priv(dev);
9622 if (!is_valid_ether_addr(addr->sa_data))
9623 return -EADDRNOTAVAIL;
9625 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9628 rc = bnxt_approve_mac(bp, addr->sa_data, true);
9632 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9633 if (netif_running(dev)) {
9634 bnxt_close_nic(bp, false, false);
9635 rc = bnxt_open_nic(bp, false, false);
9641 /* rtnl_lock held */
9642 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9644 struct bnxt *bp = netdev_priv(dev);
9646 if (netif_running(dev))
9647 bnxt_close_nic(bp, false, false);
9650 bnxt_set_ring_params(bp);
9652 if (netif_running(dev))
9653 return bnxt_open_nic(bp, false, false);
9658 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9660 struct bnxt *bp = netdev_priv(dev);
9664 if (tc > bp->max_tc) {
9665 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9670 if (netdev_get_num_tc(dev) == tc)
9673 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9676 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9677 sh, tc, bp->tx_nr_rings_xdp);
9681 /* Needs to close the device and do hw resource re-allocations */
9682 if (netif_running(bp->dev))
9683 bnxt_close_nic(bp, true, false);
9686 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9687 netdev_set_num_tc(dev, tc);
9689 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9690 netdev_reset_tc(dev);
9692 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9693 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9694 bp->tx_nr_rings + bp->rx_nr_rings;
9696 if (netif_running(bp->dev))
9697 return bnxt_open_nic(bp, true, false);
9702 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9705 struct bnxt *bp = cb_priv;
9707 if (!bnxt_tc_flower_enabled(bp) ||
9708 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9712 case TC_SETUP_CLSFLOWER:
9713 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9719 static int bnxt_setup_tc_block(struct net_device *dev,
9720 struct tc_block_offload *f)
9722 struct bnxt *bp = netdev_priv(dev);
9724 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9727 switch (f->command) {
9729 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
9731 case TC_BLOCK_UNBIND:
9732 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
9739 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9743 case TC_SETUP_BLOCK:
9744 return bnxt_setup_tc_block(dev, type_data);
9745 case TC_SETUP_QDISC_MQPRIO: {
9746 struct tc_mqprio_qopt *mqprio = type_data;
9748 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9750 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9757 #ifdef CONFIG_RFS_ACCEL
9758 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9759 struct bnxt_ntuple_filter *f2)
9761 struct flow_keys *keys1 = &f1->fkeys;
9762 struct flow_keys *keys2 = &f2->fkeys;
9764 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9765 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9766 keys1->ports.ports == keys2->ports.ports &&
9767 keys1->basic.ip_proto == keys2->basic.ip_proto &&
9768 keys1->basic.n_proto == keys2->basic.n_proto &&
9769 keys1->control.flags == keys2->control.flags &&
9770 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9771 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9777 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9778 u16 rxq_index, u32 flow_id)
9780 struct bnxt *bp = netdev_priv(dev);
9781 struct bnxt_ntuple_filter *fltr, *new_fltr;
9782 struct flow_keys *fkeys;
9783 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9784 int rc = 0, idx, bit_id, l2_idx = 0;
9785 struct hlist_head *head;
9787 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9788 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9791 netif_addr_lock_bh(dev);
9792 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9793 if (ether_addr_equal(eth->h_dest,
9794 vnic->uc_list + off)) {
9799 netif_addr_unlock_bh(dev);
9803 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9807 fkeys = &new_fltr->fkeys;
9808 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
9809 rc = -EPROTONOSUPPORT;
9813 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
9814 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
9815 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
9816 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
9817 rc = -EPROTONOSUPPORT;
9820 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
9821 bp->hwrm_spec_code < 0x10601) {
9822 rc = -EPROTONOSUPPORT;
9825 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
9826 bp->hwrm_spec_code < 0x10601) {
9827 rc = -EPROTONOSUPPORT;
9831 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
9832 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
9834 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
9835 head = &bp->ntp_fltr_hash_tbl[idx];
9837 hlist_for_each_entry_rcu(fltr, head, hash) {
9838 if (bnxt_fltr_match(fltr, new_fltr)) {
9846 spin_lock_bh(&bp->ntp_fltr_lock);
9847 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
9848 BNXT_NTP_FLTR_MAX_FLTR, 0);
9850 spin_unlock_bh(&bp->ntp_fltr_lock);
9855 new_fltr->sw_id = (u16)bit_id;
9856 new_fltr->flow_id = flow_id;
9857 new_fltr->l2_fltr_idx = l2_idx;
9858 new_fltr->rxq = rxq_index;
9859 hlist_add_head_rcu(&new_fltr->hash, head);
9860 bp->ntp_fltr_count++;
9861 spin_unlock_bh(&bp->ntp_fltr_lock);
9863 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
9864 bnxt_queue_sp_work(bp);
9866 return new_fltr->sw_id;
9873 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9877 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
9878 struct hlist_head *head;
9879 struct hlist_node *tmp;
9880 struct bnxt_ntuple_filter *fltr;
9883 head = &bp->ntp_fltr_hash_tbl[i];
9884 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
9887 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
9888 if (rps_may_expire_flow(bp->dev, fltr->rxq,
9891 bnxt_hwrm_cfa_ntuple_filter_free(bp,
9896 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
9901 set_bit(BNXT_FLTR_VALID, &fltr->state);
9905 spin_lock_bh(&bp->ntp_fltr_lock);
9906 hlist_del_rcu(&fltr->hash);
9907 bp->ntp_fltr_count--;
9908 spin_unlock_bh(&bp->ntp_fltr_lock);
9910 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
9915 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
9916 netdev_info(bp->dev, "Receive PF driver unload event!");
9921 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9925 #endif /* CONFIG_RFS_ACCEL */
9927 static void bnxt_udp_tunnel_add(struct net_device *dev,
9928 struct udp_tunnel_info *ti)
9930 struct bnxt *bp = netdev_priv(dev);
9932 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
9935 if (!netif_running(dev))
9939 case UDP_TUNNEL_TYPE_VXLAN:
9940 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
9943 bp->vxlan_port_cnt++;
9944 if (bp->vxlan_port_cnt == 1) {
9945 bp->vxlan_port = ti->port;
9946 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
9947 bnxt_queue_sp_work(bp);
9950 case UDP_TUNNEL_TYPE_GENEVE:
9951 if (bp->nge_port_cnt && bp->nge_port != ti->port)
9955 if (bp->nge_port_cnt == 1) {
9956 bp->nge_port = ti->port;
9957 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
9964 bnxt_queue_sp_work(bp);
9967 static void bnxt_udp_tunnel_del(struct net_device *dev,
9968 struct udp_tunnel_info *ti)
9970 struct bnxt *bp = netdev_priv(dev);
9972 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
9975 if (!netif_running(dev))
9979 case UDP_TUNNEL_TYPE_VXLAN:
9980 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
9982 bp->vxlan_port_cnt--;
9984 if (bp->vxlan_port_cnt != 0)
9987 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
9989 case UDP_TUNNEL_TYPE_GENEVE:
9990 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
9994 if (bp->nge_port_cnt != 0)
9997 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
10003 bnxt_queue_sp_work(bp);
10006 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10007 struct net_device *dev, u32 filter_mask,
10010 struct bnxt *bp = netdev_priv(dev);
10012 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
10013 nlflags, filter_mask, NULL);
10016 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
10017 u16 flags, struct netlink_ext_ack *extack)
10019 struct bnxt *bp = netdev_priv(dev);
10020 struct nlattr *attr, *br_spec;
10023 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
10024 return -EOPNOTSUPP;
10026 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10030 nla_for_each_nested(attr, br_spec, rem) {
10033 if (nla_type(attr) != IFLA_BRIDGE_MODE)
10036 if (nla_len(attr) < sizeof(mode))
10039 mode = nla_get_u16(attr);
10040 if (mode == bp->br_mode)
10043 rc = bnxt_hwrm_set_br_mode(bp, mode);
10045 bp->br_mode = mode;
10051 int bnxt_get_port_parent_id(struct net_device *dev,
10052 struct netdev_phys_item_id *ppid)
10054 struct bnxt *bp = netdev_priv(dev);
10056 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
10057 return -EOPNOTSUPP;
10059 /* The PF and it's VF-reps only support the switchdev framework */
10061 return -EOPNOTSUPP;
10063 ppid->id_len = sizeof(bp->switch_id);
10064 memcpy(ppid->id, bp->switch_id, ppid->id_len);
10069 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
10071 struct bnxt *bp = netdev_priv(dev);
10073 return &bp->dl_port;
10076 static const struct net_device_ops bnxt_netdev_ops = {
10077 .ndo_open = bnxt_open,
10078 .ndo_start_xmit = bnxt_start_xmit,
10079 .ndo_stop = bnxt_close,
10080 .ndo_get_stats64 = bnxt_get_stats64,
10081 .ndo_set_rx_mode = bnxt_set_rx_mode,
10082 .ndo_do_ioctl = bnxt_ioctl,
10083 .ndo_validate_addr = eth_validate_addr,
10084 .ndo_set_mac_address = bnxt_change_mac_addr,
10085 .ndo_change_mtu = bnxt_change_mtu,
10086 .ndo_fix_features = bnxt_fix_features,
10087 .ndo_set_features = bnxt_set_features,
10088 .ndo_tx_timeout = bnxt_tx_timeout,
10089 #ifdef CONFIG_BNXT_SRIOV
10090 .ndo_get_vf_config = bnxt_get_vf_config,
10091 .ndo_set_vf_mac = bnxt_set_vf_mac,
10092 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
10093 .ndo_set_vf_rate = bnxt_set_vf_bw,
10094 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
10095 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
10096 .ndo_set_vf_trust = bnxt_set_vf_trust,
10098 .ndo_setup_tc = bnxt_setup_tc,
10099 #ifdef CONFIG_RFS_ACCEL
10100 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
10102 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
10103 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
10104 .ndo_bpf = bnxt_xdp,
10105 .ndo_bridge_getlink = bnxt_bridge_getlink,
10106 .ndo_bridge_setlink = bnxt_bridge_setlink,
10107 .ndo_get_port_parent_id = bnxt_get_port_parent_id,
10108 .ndo_get_devlink_port = bnxt_get_devlink_port,
10111 static void bnxt_remove_one(struct pci_dev *pdev)
10113 struct net_device *dev = pci_get_drvdata(pdev);
10114 struct bnxt *bp = netdev_priv(dev);
10117 bnxt_sriov_disable(bp);
10118 bnxt_dl_unregister(bp);
10121 pci_disable_pcie_error_reporting(pdev);
10122 unregister_netdev(dev);
10123 bnxt_shutdown_tc(bp);
10124 bnxt_cancel_sp_work(bp);
10127 bnxt_clear_int_mode(bp);
10128 bnxt_hwrm_func_drv_unrgtr(bp);
10129 bnxt_free_hwrm_resources(bp);
10130 bnxt_free_hwrm_short_cmd_req(bp);
10131 bnxt_ethtool_free(bp);
10135 bnxt_free_ctx_mem(bp);
10138 bnxt_cleanup_pci(bp);
10139 bnxt_free_port_stats(bp);
10143 static int bnxt_probe_phy(struct bnxt *bp)
10146 struct bnxt_link_info *link_info = &bp->link_info;
10148 rc = bnxt_hwrm_phy_qcaps(bp);
10150 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10154 mutex_init(&bp->link_lock);
10156 rc = bnxt_update_link(bp, false);
10158 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10163 /* Older firmware does not have supported_auto_speeds, so assume
10164 * that all supported speeds can be autonegotiated.
10166 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10167 link_info->support_auto_speeds = link_info->support_speeds;
10169 /*initialize the ethool setting copy with NVM settings */
10170 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10171 link_info->autoneg = BNXT_AUTONEG_SPEED;
10172 if (bp->hwrm_spec_code >= 0x10201) {
10173 if (link_info->auto_pause_setting &
10174 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10175 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10177 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10179 link_info->advertising = link_info->auto_link_speeds;
10181 link_info->req_link_speed = link_info->force_link_speed;
10182 link_info->req_duplex = link_info->duplex_setting;
10184 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10185 link_info->req_flow_ctrl =
10186 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10188 link_info->req_flow_ctrl = link_info->force_pause_setting;
10192 static int bnxt_get_max_irq(struct pci_dev *pdev)
10196 if (!pdev->msix_cap)
10199 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10200 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10203 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10206 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10207 int max_ring_grps = 0, max_irq;
10209 *max_tx = hw_resc->max_tx_rings;
10210 *max_rx = hw_resc->max_rx_rings;
10211 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10212 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10213 bnxt_get_ulp_msix_num(bp),
10214 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10215 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10216 *max_cp = min_t(int, *max_cp, max_irq);
10217 max_ring_grps = hw_resc->max_hw_ring_grps;
10218 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10222 if (bp->flags & BNXT_FLAG_AGG_RINGS)
10224 if (bp->flags & BNXT_FLAG_CHIP_P5) {
10225 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10226 /* On P5 chips, max_cp output param should be available NQs */
10229 *max_rx = min_t(int, *max_rx, max_ring_grps);
10232 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10236 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10239 if (!rx || !tx || !cp)
10242 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10245 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10250 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10251 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10252 /* Not enough rings, try disabling agg rings. */
10253 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10254 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10256 /* set BNXT_FLAG_AGG_RINGS back for consistency */
10257 bp->flags |= BNXT_FLAG_AGG_RINGS;
10260 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10261 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10262 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10263 bnxt_set_ring_params(bp);
10266 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10267 int max_cp, max_stat, max_irq;
10269 /* Reserve minimum resources for RoCE */
10270 max_cp = bnxt_get_max_func_cp_rings(bp);
10271 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10272 max_irq = bnxt_get_max_func_irqs(bp);
10273 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10274 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10275 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10278 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10279 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10280 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10281 max_cp = min_t(int, max_cp, max_irq);
10282 max_cp = min_t(int, max_cp, max_stat);
10283 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10290 /* In initial default shared ring setting, each shared ring must have a
10293 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10295 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10296 bp->rx_nr_rings = bp->cp_nr_rings;
10297 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10298 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10301 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10303 int dflt_rings, max_rx_rings, max_tx_rings, rc;
10305 if (!bnxt_can_reserve_rings(bp))
10309 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10310 dflt_rings = netif_get_num_default_rss_queues();
10311 /* Reduce default rings on multi-port cards so that total default
10312 * rings do not exceed CPU count.
10314 if (bp->port_count > 1) {
10316 max_t(int, num_online_cpus() / bp->port_count, 1);
10318 dflt_rings = min_t(int, dflt_rings, max_rings);
10320 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10323 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10324 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10326 bnxt_trim_dflt_sh_rings(bp);
10328 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10329 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10331 rc = __bnxt_reserve_rings(bp);
10333 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10334 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10336 bnxt_trim_dflt_sh_rings(bp);
10338 /* Rings may have been trimmed, re-reserve the trimmed rings. */
10339 if (bnxt_need_reserve_rings(bp)) {
10340 rc = __bnxt_reserve_rings(bp);
10342 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10343 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10345 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10352 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10356 if (bp->tx_nr_rings)
10359 bnxt_ulp_irq_stop(bp);
10360 bnxt_clear_int_mode(bp);
10361 rc = bnxt_set_dflt_rings(bp, true);
10363 netdev_err(bp->dev, "Not enough rings available.\n");
10364 goto init_dflt_ring_err;
10366 rc = bnxt_init_int_mode(bp);
10368 goto init_dflt_ring_err;
10370 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10371 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10372 bp->flags |= BNXT_FLAG_RFS;
10373 bp->dev->features |= NETIF_F_NTUPLE;
10375 init_dflt_ring_err:
10376 bnxt_ulp_irq_restart(bp, rc);
10380 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10385 bnxt_hwrm_func_qcaps(bp);
10387 if (netif_running(bp->dev))
10388 __bnxt_close_nic(bp, true, false);
10390 bnxt_ulp_irq_stop(bp);
10391 bnxt_clear_int_mode(bp);
10392 rc = bnxt_init_int_mode(bp);
10393 bnxt_ulp_irq_restart(bp, rc);
10395 if (netif_running(bp->dev)) {
10397 dev_close(bp->dev);
10399 rc = bnxt_open_nic(bp, true, false);
10405 static int bnxt_init_mac_addr(struct bnxt *bp)
10410 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10412 #ifdef CONFIG_BNXT_SRIOV
10413 struct bnxt_vf_info *vf = &bp->vf;
10414 bool strict_approval = true;
10416 if (is_valid_ether_addr(vf->mac_addr)) {
10417 /* overwrite netdev dev_addr with admin VF MAC */
10418 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10419 /* Older PF driver or firmware may not approve this
10422 strict_approval = false;
10424 eth_hw_addr_random(bp->dev);
10426 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10432 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10434 static int version_printed;
10435 struct net_device *dev;
10439 if (pci_is_bridge(pdev))
10442 if (version_printed++ == 0)
10443 pr_info("%s", version);
10445 max_irqs = bnxt_get_max_irq(pdev);
10446 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10450 bp = netdev_priv(dev);
10451 bnxt_set_max_func_irqs(bp, max_irqs);
10453 if (bnxt_vf_pciid(ent->driver_data))
10454 bp->flags |= BNXT_FLAG_VF;
10456 if (pdev->msix_cap)
10457 bp->flags |= BNXT_FLAG_MSIX_CAP;
10459 rc = bnxt_init_board(pdev, dev);
10461 goto init_err_free;
10463 dev->netdev_ops = &bnxt_netdev_ops;
10464 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10465 dev->ethtool_ops = &bnxt_ethtool_ops;
10466 pci_set_drvdata(pdev, dev);
10468 rc = bnxt_alloc_hwrm_resources(bp);
10470 goto init_err_pci_clean;
10472 mutex_init(&bp->hwrm_cmd_lock);
10473 rc = bnxt_hwrm_ver_get(bp);
10475 goto init_err_pci_clean;
10477 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10478 rc = bnxt_alloc_kong_hwrm_resources(bp);
10480 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10483 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10484 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10485 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10487 goto init_err_pci_clean;
10490 if (BNXT_CHIP_P5(bp))
10491 bp->flags |= BNXT_FLAG_CHIP_P5;
10493 rc = bnxt_hwrm_func_reset(bp);
10495 goto init_err_pci_clean;
10497 bnxt_hwrm_fw_set_time(bp);
10499 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10500 NETIF_F_TSO | NETIF_F_TSO6 |
10501 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10502 NETIF_F_GSO_IPXIP4 |
10503 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10504 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10505 NETIF_F_RXCSUM | NETIF_F_GRO;
10507 if (BNXT_SUPPORTS_TPA(bp))
10508 dev->hw_features |= NETIF_F_LRO;
10510 dev->hw_enc_features =
10511 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10512 NETIF_F_TSO | NETIF_F_TSO6 |
10513 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10514 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10515 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10516 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10517 NETIF_F_GSO_GRE_CSUM;
10518 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10519 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10520 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10521 if (BNXT_SUPPORTS_TPA(bp))
10522 dev->hw_features |= NETIF_F_GRO_HW;
10523 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10524 if (dev->features & NETIF_F_GRO_HW)
10525 dev->features &= ~NETIF_F_LRO;
10526 dev->priv_flags |= IFF_UNICAST_FLT;
10528 #ifdef CONFIG_BNXT_SRIOV
10529 init_waitqueue_head(&bp->sriov_cfg_wait);
10530 mutex_init(&bp->sriov_lock);
10532 if (BNXT_SUPPORTS_TPA(bp)) {
10533 bp->gro_func = bnxt_gro_func_5730x;
10534 if (BNXT_CHIP_P4(bp))
10535 bp->gro_func = bnxt_gro_func_5731x;
10537 if (!BNXT_CHIP_P4_PLUS(bp))
10538 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10540 rc = bnxt_hwrm_func_drv_rgtr(bp);
10542 goto init_err_pci_clean;
10544 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10546 goto init_err_pci_clean;
10548 bp->ulp_probe = bnxt_ulp_probe;
10550 rc = bnxt_hwrm_queue_qportcfg(bp);
10552 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10555 goto init_err_pci_clean;
10557 /* Get the MAX capabilities for this function */
10558 rc = bnxt_hwrm_func_qcaps(bp);
10560 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10563 goto init_err_pci_clean;
10565 rc = bnxt_init_mac_addr(bp);
10567 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10568 rc = -EADDRNOTAVAIL;
10569 goto init_err_pci_clean;
10572 bnxt_hwrm_func_qcfg(bp);
10573 bnxt_hwrm_vnic_qcaps(bp);
10574 bnxt_hwrm_port_led_qcaps(bp);
10575 bnxt_ethtool_init(bp);
10578 /* MTU range: 60 - FW defined max */
10579 dev->min_mtu = ETH_ZLEN;
10580 dev->max_mtu = bp->max_mtu;
10582 rc = bnxt_probe_phy(bp);
10584 goto init_err_pci_clean;
10586 bnxt_set_rx_skb_mode(bp, false);
10587 bnxt_set_tpa_flags(bp);
10588 bnxt_set_ring_params(bp);
10589 rc = bnxt_set_dflt_rings(bp, true);
10591 netdev_err(bp->dev, "Not enough rings available.\n");
10593 goto init_err_pci_clean;
10596 /* Default RSS hash cfg. */
10597 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10598 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10599 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10600 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10601 if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10602 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10603 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10604 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10607 if (bnxt_rfs_supported(bp)) {
10608 dev->hw_features |= NETIF_F_NTUPLE;
10609 if (bnxt_rfs_capable(bp)) {
10610 bp->flags |= BNXT_FLAG_RFS;
10611 dev->features |= NETIF_F_NTUPLE;
10615 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10616 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10618 rc = bnxt_init_int_mode(bp);
10620 goto init_err_pci_clean;
10622 /* No TC has been set yet and rings may have been trimmed due to
10623 * limited MSIX, so we re-initialize the TX rings per TC.
10625 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10627 bnxt_get_wol_settings(bp);
10628 if (bp->flags & BNXT_FLAG_WOL_CAP)
10629 device_set_wakeup_enable(&pdev->dev, bp->wol);
10631 device_set_wakeup_capable(&pdev->dev, false);
10633 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10635 bnxt_hwrm_coal_params_qcaps(bp);
10640 create_singlethread_workqueue("bnxt_pf_wq");
10642 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10643 goto init_err_pci_clean;
10649 rc = register_netdev(dev);
10651 goto init_err_cleanup_tc;
10654 bnxt_dl_register(bp);
10656 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10657 board_info[ent->driver_data].name,
10658 (long)pci_resource_start(pdev, 0), dev->dev_addr);
10659 pcie_print_link_status(pdev);
10663 init_err_cleanup_tc:
10664 bnxt_shutdown_tc(bp);
10665 bnxt_clear_int_mode(bp);
10667 init_err_pci_clean:
10668 bnxt_free_hwrm_resources(bp);
10669 bnxt_free_ctx_mem(bp);
10672 bnxt_cleanup_pci(bp);
10679 static void bnxt_shutdown(struct pci_dev *pdev)
10681 struct net_device *dev = pci_get_drvdata(pdev);
10688 bp = netdev_priv(dev);
10690 goto shutdown_exit;
10692 if (netif_running(dev))
10695 bnxt_ulp_shutdown(bp);
10697 if (system_state == SYSTEM_POWER_OFF) {
10698 bnxt_clear_int_mode(bp);
10699 pci_wake_from_d3(pdev, bp->wol);
10700 pci_set_power_state(pdev, PCI_D3hot);
10707 #ifdef CONFIG_PM_SLEEP
10708 static int bnxt_suspend(struct device *device)
10710 struct pci_dev *pdev = to_pci_dev(device);
10711 struct net_device *dev = pci_get_drvdata(pdev);
10712 struct bnxt *bp = netdev_priv(dev);
10716 if (netif_running(dev)) {
10717 netif_device_detach(dev);
10718 rc = bnxt_close(dev);
10720 bnxt_hwrm_func_drv_unrgtr(bp);
10725 static int bnxt_resume(struct device *device)
10727 struct pci_dev *pdev = to_pci_dev(device);
10728 struct net_device *dev = pci_get_drvdata(pdev);
10729 struct bnxt *bp = netdev_priv(dev);
10733 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10737 rc = bnxt_hwrm_func_reset(bp);
10742 bnxt_get_wol_settings(bp);
10743 if (netif_running(dev)) {
10744 rc = bnxt_open(dev);
10746 netif_device_attach(dev);
10754 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10755 #define BNXT_PM_OPS (&bnxt_pm_ops)
10759 #define BNXT_PM_OPS NULL
10761 #endif /* CONFIG_PM_SLEEP */
10764 * bnxt_io_error_detected - called when PCI error is detected
10765 * @pdev: Pointer to PCI device
10766 * @state: The current pci connection state
10768 * This function is called after a PCI bus error affecting
10769 * this device has been detected.
10771 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10772 pci_channel_state_t state)
10774 struct net_device *netdev = pci_get_drvdata(pdev);
10775 struct bnxt *bp = netdev_priv(netdev);
10777 netdev_info(netdev, "PCI I/O error detected\n");
10780 netif_device_detach(netdev);
10784 if (state == pci_channel_io_perm_failure) {
10786 return PCI_ERS_RESULT_DISCONNECT;
10789 if (netif_running(netdev))
10790 bnxt_close(netdev);
10792 pci_disable_device(pdev);
10795 /* Request a slot slot reset. */
10796 return PCI_ERS_RESULT_NEED_RESET;
10800 * bnxt_io_slot_reset - called after the pci bus has been reset.
10801 * @pdev: Pointer to PCI device
10803 * Restart the card from scratch, as if from a cold-boot.
10804 * At this point, the card has exprienced a hard reset,
10805 * followed by fixups by BIOS, and has its config space
10806 * set up identically to what it was at cold boot.
10808 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
10810 struct net_device *netdev = pci_get_drvdata(pdev);
10811 struct bnxt *bp = netdev_priv(netdev);
10813 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
10815 netdev_info(bp->dev, "PCI Slot Reset\n");
10819 if (pci_enable_device(pdev)) {
10820 dev_err(&pdev->dev,
10821 "Cannot re-enable PCI device after reset.\n");
10823 pci_set_master(pdev);
10825 err = bnxt_hwrm_func_reset(bp);
10826 if (!err && netif_running(netdev))
10827 err = bnxt_open(netdev);
10830 result = PCI_ERS_RESULT_RECOVERED;
10831 bnxt_ulp_start(bp);
10835 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
10840 return PCI_ERS_RESULT_RECOVERED;
10844 * bnxt_io_resume - called when traffic can start flowing again.
10845 * @pdev: Pointer to PCI device
10847 * This callback is called when the error recovery driver tells
10848 * us that its OK to resume normal operation.
10850 static void bnxt_io_resume(struct pci_dev *pdev)
10852 struct net_device *netdev = pci_get_drvdata(pdev);
10856 netif_device_attach(netdev);
10861 static const struct pci_error_handlers bnxt_err_handler = {
10862 .error_detected = bnxt_io_error_detected,
10863 .slot_reset = bnxt_io_slot_reset,
10864 .resume = bnxt_io_resume
10867 static struct pci_driver bnxt_pci_driver = {
10868 .name = DRV_MODULE_NAME,
10869 .id_table = bnxt_pci_tbl,
10870 .probe = bnxt_init_one,
10871 .remove = bnxt_remove_one,
10872 .shutdown = bnxt_shutdown,
10873 .driver.pm = BNXT_PM_OPS,
10874 .err_handler = &bnxt_err_handler,
10875 #if defined(CONFIG_BNXT_SRIOV)
10876 .sriov_configure = bnxt_sriov_configure,
10880 static int __init bnxt_init(void)
10883 return pci_register_driver(&bnxt_pci_driver);
10886 static void __exit bnxt_exit(void)
10888 pci_unregister_driver(&bnxt_pci_driver);
10890 destroy_workqueue(bnxt_pf_wq);
10894 module_init(bnxt_init);
10895 module_exit(bnxt_exit);