drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2019 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/mdio.h>
  35 #include <linux/if.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/if_bridge.h>
  38 #include <linux/rtc.h>
  39 #include <linux/bpf.h>
  40 #include <net/ip.h>
  41 #include <net/tcp.h>
  42 #include <net/udp.h>
  43 #include <net/checksum.h>
  44 #include <net/ip6_checksum.h>
  45 #include <net/udp_tunnel.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53 #include <linux/cpumask.h>
  54 #include <net/pkt_cls.h>
  55 #include <linux/hwmon.h>
  56 #include <linux/hwmon-sysfs.h>
  57
  58 #include "bnxt_hsi.h"
  59 #include "bnxt.h"
  60 #include "bnxt_ulp.h"
  61 #include "bnxt_sriov.h"
  62 #include "bnxt_ethtool.h"
  63 #include "bnxt_dcb.h"
  64 #include "bnxt_xdp.h"
  65 #include "bnxt_vfr.h"
  66 #include "bnxt_tc.h"
  67 #include "bnxt_devlink.h"
  68 #include "bnxt_debugfs.h"
  69
  70 #define BNXT_TX_TIMEOUT         (5 * HZ)
  71
  72 static const char version[] =
  73         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  74
  75 MODULE_LICENSE("GPL");
  76 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  77 MODULE_VERSION(DRV_MODULE_VERSION);
  78
  79 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  80 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  81 #define BNXT_RX_COPY_THRESH 256
  82
  83 #define BNXT_TX_PUSH_THRESH 164
  84
  85 enum board_idx {
  86         BCM57301,
  87         BCM57302,
  88         BCM57304,
  89         BCM57417_NPAR,
  90         BCM58700,
  91         BCM57311,
  92         BCM57312,
  93         BCM57402,
  94         BCM57404,
  95         BCM57406,
  96         BCM57402_NPAR,
  97         BCM57407,
  98         BCM57412,
  99         BCM57414,
 100         BCM57416,
 101         BCM57417,
 102         BCM57412_NPAR,
 103         BCM57314,
 104         BCM57417_SFP,
 105         BCM57416_SFP,
 106         BCM57404_NPAR,
 107         BCM57406_NPAR,
 108         BCM57407_SFP,
 109         BCM57407_NPAR,
 110         BCM57414_NPAR,
 111         BCM57416_NPAR,
 112         BCM57452,
 113         BCM57454,
 114         BCM5745x_NPAR,
 115         BCM57508,
 116         BCM57504,
 117         BCM58802,
 118         BCM58804,
 119         BCM58808,
 120         NETXTREME_E_VF,
 121         NETXTREME_C_VF,
 122         NETXTREME_S_VF,
 123         NETXTREME_E_P5_VF,
 124 };
 125
 126 /* indexed by enum above */
 127 static const struct {
 128         char *name;
 129 } board_info[] = {
 130         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 131         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 132         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 133         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 134         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 135         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 136         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 137         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 138         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 139         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 140         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 141         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 142         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 143         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 144         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 145         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 146         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 147         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 148         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 149         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 150         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 151         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 152         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 153         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 154         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 155         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 156         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 157         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 158         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 159         [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 160         [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 161         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 162         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 163         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 164         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 165         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 166         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 167         [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
 168 };
 169
 170 static const struct pci_device_id bnxt_pci_tbl[] = {
 171         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 173         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 174         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 175         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 176         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 177         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 178         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 179         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 180         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 181         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 182         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 183         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 184         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 185         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 186         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 187         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 188         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 189         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 190         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 191         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 192         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 193         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 194         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 195         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 196         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 197         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 198         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 199         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 200         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 201         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 202         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 203         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 204         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 205         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 206         { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
 207         { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
 208         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 209         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 210 #ifdef CONFIG_BNXT_SRIOV
 211         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 212         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 213         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 214         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 215         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 216         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 217         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 218         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 219         { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
 220         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 221 #endif
 222         { 0 }
 223 };
 224
 225 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 226
 227 static const u16 bnxt_vf_req_snif[] = {
 228         HWRM_FUNC_CFG,
 229         HWRM_FUNC_VF_CFG,
 230         HWRM_PORT_PHY_QCFG,
 231         HWRM_CFA_L2_FILTER_ALLOC,
 232 };
 233
 234 static const u16 bnxt_async_events_arr[] = {
 235         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 236         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 237         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 238         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 239         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 240 };
 241
 242 static struct workqueue_struct *bnxt_pf_wq;
 243
 244 static bool bnxt_vf_pciid(enum board_idx idx)
 245 {
 246         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 247                 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
 248 }
 249
 250 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 251 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 252 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 253
 254 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 255                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 256
 257 #define BNXT_DB_CQ(db, idx)                                             \
 258         writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
 259
 260 #define BNXT_DB_NQ_P5(db, idx)                                          \
 261         writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
 262
 263 #define BNXT_DB_CQ_ARM(db, idx)                                         \
 264         writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
 265
 266 #define BNXT_DB_NQ_ARM_P5(db, idx)                                      \
 267         writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
 268
 269 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 270 {
 271         if (bp->flags & BNXT_FLAG_CHIP_P5)
 272                 BNXT_DB_NQ_P5(db, idx);
 273         else
 274                 BNXT_DB_CQ(db, idx);
 275 }
 276
 277 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 278 {
 279         if (bp->flags & BNXT_FLAG_CHIP_P5)
 280                 BNXT_DB_NQ_ARM_P5(db, idx);
 281         else
 282                 BNXT_DB_CQ_ARM(db, idx);
 283 }
 284
 285 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 286 {
 287         if (bp->flags & BNXT_FLAG_CHIP_P5)
 288                 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
 289                        db->doorbell);
 290         else
 291                 BNXT_DB_CQ(db, idx);
 292 }
 293
 294 const u16 bnxt_lhint_arr[] = {
 295         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 296         TX_BD_FLAGS_LHINT_512_TO_1023,
 297         TX_BD_FLAGS_LHINT_1024_TO_2047,
 298         TX_BD_FLAGS_LHINT_1024_TO_2047,
 299         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 300         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 301         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 302         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 303         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 304         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 305         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 306         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 307         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 308         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 309         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 310         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 311         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 312         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 313         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 314 };
 315
 316 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 317 {
 318         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 319
 320         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 321                 return 0;
 322
 323         return md_dst->u.port_info.port_id;
 324 }
 325
 326 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 327 {
 328         struct bnxt *bp = netdev_priv(dev);
 329         struct tx_bd *txbd;
 330         struct tx_bd_ext *txbd1;
 331         struct netdev_queue *txq;
 332         int i;
 333         dma_addr_t mapping;
 334         unsigned int length, pad = 0;
 335         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 336         u16 prod, last_frag;
 337         struct pci_dev *pdev = bp->pdev;
 338         struct bnxt_tx_ring_info *txr;
 339         struct bnxt_sw_tx_bd *tx_buf;
 340
 341         i = skb_get_queue_mapping(skb);
 342         if (unlikely(i >= bp->tx_nr_rings)) {
 343                 dev_kfree_skb_any(skb);
 344                 return NETDEV_TX_OK;
 345         }
 346
 347         txq = netdev_get_tx_queue(dev, i);
 348         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 349         prod = txr->tx_prod;
 350
 351         free_size = bnxt_tx_avail(bp, txr);
 352         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 353                 netif_tx_stop_queue(txq);
 354                 return NETDEV_TX_BUSY;
 355         }
 356
 357         length = skb->len;
 358         len = skb_headlen(skb);
 359         last_frag = skb_shinfo(skb)->nr_frags;
 360
 361         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 362
 363         txbd->tx_bd_opaque = prod;
 364
 365         tx_buf = &txr->tx_buf_ring[prod];
 366         tx_buf->skb = skb;
 367         tx_buf->nr_frags = last_frag;
 368
 369         vlan_tag_flags = 0;
 370         cfa_action = bnxt_xmit_get_cfa_action(skb);
 371         if (skb_vlan_tag_present(skb)) {
 372                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 373                                  skb_vlan_tag_get(skb);
 374                 /* Currently supports 8021Q, 8021AD vlan offloads
 375                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 376                  */
 377                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 378                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 379         }
 380
 381         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 382                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 383                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 384                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 385                 void __iomem *db = txr->tx_db.doorbell;
 386                 void *pdata = tx_push_buf->data;
 387                 u64 *end;
 388                 int j, push_len;
 389
 390                 /* Set COAL_NOW to be ready quickly for the next push */
 391                 tx_push->tx_bd_len_flags_type =
 392                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 393                                         TX_BD_TYPE_LONG_TX_BD |
 394                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 395                                         TX_BD_FLAGS_COAL_NOW |
 396                                         TX_BD_FLAGS_PACKET_END |
 397                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 398
 399                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 400                         tx_push1->tx_bd_hsize_lflags =
 401                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 402                 else
 403                         tx_push1->tx_bd_hsize_lflags = 0;
 404
 405                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 406                 tx_push1->tx_bd_cfa_action =
 407                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 408
 409                 end = pdata + length;
 410                 end = PTR_ALIGN(end, 8) - 1;
 411                 *end = 0;
 412
 413                 skb_copy_from_linear_data(skb, pdata, len);
 414                 pdata += len;
 415                 for (j = 0; j < last_frag; j++) {
 416                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 417                         void *fptr;
 418
 419                         fptr = skb_frag_address_safe(frag);
 420                         if (!fptr)
 421                                 goto normal_tx;
 422
 423                         memcpy(pdata, fptr, skb_frag_size(frag));
 424                         pdata += skb_frag_size(frag);
 425                 }
 426
 427                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 428                 txbd->tx_bd_haddr = txr->data_mapping;
 429                 prod = NEXT_TX(prod);
 430                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 431                 memcpy(txbd, tx_push1, sizeof(*txbd));
 432                 prod = NEXT_TX(prod);
 433                 tx_push->doorbell =
 434                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 435                 txr->tx_prod = prod;
 436
 437                 tx_buf->is_push = 1;
 438                 netdev_tx_sent_queue(txq, skb->len);
 439                 wmb();  /* Sync is_push and byte queue before pushing data */
 440
 441                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 442                 if (push_len > 16) {
 443                         __iowrite64_copy(db, tx_push_buf, 16);
 444                         __iowrite32_copy(db + 4, tx_push_buf + 1,
 445                                          (push_len - 16) << 1);
 446                 } else {
 447                         __iowrite64_copy(db, tx_push_buf, push_len);
 448                 }
 449
 450                 goto tx_done;
 451         }
 452
 453 normal_tx:
 454         if (length < BNXT_MIN_PKT_SIZE) {
 455                 pad = BNXT_MIN_PKT_SIZE - length;
 456                 if (skb_pad(skb, pad)) {
 457                         /* SKB already freed. */
 458                         tx_buf->skb = NULL;
 459                         return NETDEV_TX_OK;
 460                 }
 461                 length = BNXT_MIN_PKT_SIZE;
 462         }
 463
 464         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 465
 466         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 467                 dev_kfree_skb_any(skb);
 468                 tx_buf->skb = NULL;
 469                 return NETDEV_TX_OK;
 470         }
 471
 472         dma_unmap_addr_set(tx_buf, mapping, mapping);
 473         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 474                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 475
 476         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 477
 478         prod = NEXT_TX(prod);
 479         txbd1 = (struct tx_bd_ext *)
 480                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 481
 482         txbd1->tx_bd_hsize_lflags = 0;
 483         if (skb_is_gso(skb)) {
 484                 u32 hdr_len;
 485
 486                 if (skb->encapsulation)
 487                         hdr_len = skb_inner_network_offset(skb) +
 488                                 skb_inner_network_header_len(skb) +
 489                                 inner_tcp_hdrlen(skb);
 490                 else
 491                         hdr_len = skb_transport_offset(skb) +
 492                                 tcp_hdrlen(skb);
 493
 494                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 495                                         TX_BD_FLAGS_T_IPID |
 496                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 497                 length = skb_shinfo(skb)->gso_size;
 498                 txbd1->tx_bd_mss = cpu_to_le32(length);
 499                 length += hdr_len;
 500         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 501                 txbd1->tx_bd_hsize_lflags =
 502                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 503                 txbd1->tx_bd_mss = 0;
 504         }
 505
 506         length >>= 9;
 507         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 508                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 509                                      skb->len);
 510                 i = 0;
 511                 goto tx_dma_error;
 512         }
 513         flags |= bnxt_lhint_arr[length];
 514         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 515
 516         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 517         txbd1->tx_bd_cfa_action =
 518                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 519         for (i = 0; i < last_frag; i++) {
 520                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 521
 522                 prod = NEXT_TX(prod);
 523                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 524
 525                 len = skb_frag_size(frag);
 526                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 527                                            DMA_TO_DEVICE);
 528
 529                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 530                         goto tx_dma_error;
 531
 532                 tx_buf = &txr->tx_buf_ring[prod];
 533                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 534
 535                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 536
 537                 flags = len << TX_BD_LEN_SHIFT;
 538                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 539         }
 540
 541         flags &= ~TX_BD_LEN;
 542         txbd->tx_bd_len_flags_type =
 543                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 544                             TX_BD_FLAGS_PACKET_END);
 545
 546         netdev_tx_sent_queue(txq, skb->len);
 547
 548         /* Sync BD data before updating doorbell */
 549         wmb();
 550
 551         prod = NEXT_TX(prod);
 552         txr->tx_prod = prod;
 553
 554         if (!netdev_xmit_more() || netif_xmit_stopped(txq))
 555                 bnxt_db_write(bp, &txr->tx_db, prod);
 556
 557 tx_done:
 558
 559         mmiowb();
 560
 561         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 562                 if (netdev_xmit_more() && !tx_buf->is_push)
 563                         bnxt_db_write(bp, &txr->tx_db, prod);
 564
 565                 netif_tx_stop_queue(txq);
 566
 567                 /* netif_tx_stop_queue() must be done before checking
 568                  * tx index in bnxt_tx_avail() below, because in
 569                  * bnxt_tx_int(), we update tx index before checking for
 570                  * netif_tx_queue_stopped().
 571                  */
 572                 smp_mb();
 573                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 574                         netif_tx_wake_queue(txq);
 575         }
 576         return NETDEV_TX_OK;
 577
 578 tx_dma_error:
 579         last_frag = i;
 580
 581         /* start back at beginning and unmap skb */
 582         prod = txr->tx_prod;
 583         tx_buf = &txr->tx_buf_ring[prod];
 584         tx_buf->skb = NULL;
 585         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 586                          skb_headlen(skb), PCI_DMA_TODEVICE);
 587         prod = NEXT_TX(prod);
 588
 589         /* unmap remaining mapped pages */
 590         for (i = 0; i < last_frag; i++) {
 591                 prod = NEXT_TX(prod);
 592                 tx_buf = &txr->tx_buf_ring[prod];
 593                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 594                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 595                                PCI_DMA_TODEVICE);
 596         }
 597
 598         dev_kfree_skb_any(skb);
 599         return NETDEV_TX_OK;
 600 }
 601
 602 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 603 {
 604         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 605         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 606         u16 cons = txr->tx_cons;
 607         struct pci_dev *pdev = bp->pdev;
 608         int i;
 609         unsigned int tx_bytes = 0;
 610
 611         for (i = 0; i < nr_pkts; i++) {
 612                 struct bnxt_sw_tx_bd *tx_buf;
 613                 struct sk_buff *skb;
 614                 int j, last;
 615
 616                 tx_buf = &txr->tx_buf_ring[cons];
 617                 cons = NEXT_TX(cons);
 618                 skb = tx_buf->skb;
 619                 tx_buf->skb = NULL;
 620
 621                 if (tx_buf->is_push) {
 622                         tx_buf->is_push = 0;
 623                         goto next_tx_int;
 624                 }
 625
 626                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 627                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 628                 last = tx_buf->nr_frags;
 629
 630                 for (j = 0; j < last; j++) {
 631                         cons = NEXT_TX(cons);
 632                         tx_buf = &txr->tx_buf_ring[cons];
 633                         dma_unmap_page(
 634                                 &pdev->dev,
 635                                 dma_unmap_addr(tx_buf, mapping),
 636                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 637                                 PCI_DMA_TODEVICE);
 638                 }
 639
 640 next_tx_int:
 641                 cons = NEXT_TX(cons);
 642
 643                 tx_bytes += skb->len;
 644                 dev_kfree_skb_any(skb);
 645         }
 646
 647         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 648         txr->tx_cons = cons;
 649
 650         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 651          * before checking for netif_tx_queue_stopped().  Without the
 652          * memory barrier, there is a small possibility that bnxt_start_xmit()
 653          * will miss it and cause the queue to be stopped forever.
 654          */
 655         smp_mb();
 656
 657         if (unlikely(netif_tx_queue_stopped(txq)) &&
 658             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 659                 __netif_tx_lock(txq, smp_processor_id());
 660                 if (netif_tx_queue_stopped(txq) &&
 661                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 662                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 663                         netif_tx_wake_queue(txq);
 664                 __netif_tx_unlock(txq);
 665         }
 666 }
 667
 668 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 669                                          gfp_t gfp)
 670 {
 671         struct device *dev = &bp->pdev->dev;
 672         struct page *page;
 673
 674         page = alloc_page(gfp);
 675         if (!page)
 676                 return NULL;
 677
 678         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 679                                       DMA_ATTR_WEAK_ORDERING);
 680         if (dma_mapping_error(dev, *mapping)) {
 681                 __free_page(page);
 682                 return NULL;
 683         }
 684         *mapping += bp->rx_dma_offset;
 685         return page;
 686 }
 687
 688 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 689                                        gfp_t gfp)
 690 {
 691         u8 *data;
 692         struct pci_dev *pdev = bp->pdev;
 693
 694         data = kmalloc(bp->rx_buf_size, gfp);
 695         if (!data)
 696                 return NULL;
 697
 698         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 699                                         bp->rx_buf_use_size, bp->rx_dir,
 700                                         DMA_ATTR_WEAK_ORDERING);
 701
 702         if (dma_mapping_error(&pdev->dev, *mapping)) {
 703                 kfree(data);
 704                 data = NULL;
 705         }
 706         return data;
 707 }
 708
 709 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 710                        u16 prod, gfp_t gfp)
 711 {
 712         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 713         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 714         dma_addr_t mapping;
 715
 716         if (BNXT_RX_PAGE_MODE(bp)) {
 717                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 718
 719                 if (!page)
 720                         return -ENOMEM;
 721
 722                 rx_buf->data = page;
 723                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 724         } else {
 725                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 726
 727                 if (!data)
 728                         return -ENOMEM;
 729
 730                 rx_buf->data = data;
 731                 rx_buf->data_ptr = data + bp->rx_offset;
 732         }
 733         rx_buf->mapping = mapping;
 734
 735         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 736         return 0;
 737 }
 738
 739 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 740 {
 741         u16 prod = rxr->rx_prod;
 742         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 743         struct rx_bd *cons_bd, *prod_bd;
 744
 745         prod_rx_buf = &rxr->rx_buf_ring[prod];
 746         cons_rx_buf = &rxr->rx_buf_ring[cons];
 747
 748         prod_rx_buf->data = data;
 749         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 750
 751         prod_rx_buf->mapping = cons_rx_buf->mapping;
 752
 753         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 754         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 755
 756         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 757 }
 758
 759 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 760 {
 761         u16 next, max = rxr->rx_agg_bmap_size;
 762
 763         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 764         if (next >= max)
 765                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 766         return next;
 767 }
 768
 769 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 770                                      struct bnxt_rx_ring_info *rxr,
 771                                      u16 prod, gfp_t gfp)
 772 {
 773         struct rx_bd *rxbd =
 774                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 775         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 776         struct pci_dev *pdev = bp->pdev;
 777         struct page *page;
 778         dma_addr_t mapping;
 779         u16 sw_prod = rxr->rx_sw_agg_prod;
 780         unsigned int offset = 0;
 781
 782         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 783                 page = rxr->rx_page;
 784                 if (!page) {
 785                         page = alloc_page(gfp);
 786                         if (!page)
 787                                 return -ENOMEM;
 788                         rxr->rx_page = page;
 789                         rxr->rx_page_offset = 0;
 790                 }
 791                 offset = rxr->rx_page_offset;
 792                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 793                 if (rxr->rx_page_offset == PAGE_SIZE)
 794                         rxr->rx_page = NULL;
 795                 else
 796                         get_page(page);
 797         } else {
 798                 page = alloc_page(gfp);
 799                 if (!page)
 800                         return -ENOMEM;
 801         }
 802
 803         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 804                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 805                                      DMA_ATTR_WEAK_ORDERING);
 806         if (dma_mapping_error(&pdev->dev, mapping)) {
 807                 __free_page(page);
 808                 return -EIO;
 809         }
 810
 811         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 812                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 813
 814         __set_bit(sw_prod, rxr->rx_agg_bmap);
 815         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 816         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 817
 818         rx_agg_buf->page = page;
 819         rx_agg_buf->offset = offset;
 820         rx_agg_buf->mapping = mapping;
 821         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 822         rxbd->rx_bd_opaque = sw_prod;
 823         return 0;
 824 }
 825
 826 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
 827                                    u32 agg_bufs)
 828 {
 829         struct bnxt_napi *bnapi = cpr->bnapi;
 830         struct bnxt *bp = bnapi->bp;
 831         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 832         u16 prod = rxr->rx_agg_prod;
 833         u16 sw_prod = rxr->rx_sw_agg_prod;
 834         u32 i;
 835
 836         for (i = 0; i < agg_bufs; i++) {
 837                 u16 cons;
 838                 struct rx_agg_cmp *agg;
 839                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 840                 struct rx_bd *prod_bd;
 841                 struct page *page;
 842
 843                 agg = (struct rx_agg_cmp *)
 844                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 845                 cons = agg->rx_agg_cmp_opaque;
 846                 __clear_bit(cons, rxr->rx_agg_bmap);
 847
 848                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 849                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 850
 851                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 852                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 853                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 854
 855                 /* It is possible for sw_prod to be equal to cons, so
 856                  * set cons_rx_buf->page to NULL first.
 857                  */
 858                 page = cons_rx_buf->page;
 859                 cons_rx_buf->page = NULL;
 860                 prod_rx_buf->page = page;
 861                 prod_rx_buf->offset = cons_rx_buf->offset;
 862
 863                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 864
 865                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 866
 867                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 868                 prod_bd->rx_bd_opaque = sw_prod;
 869
 870                 prod = NEXT_RX_AGG(prod);
 871                 sw_prod = NEXT_RX_AGG(sw_prod);
 872                 cp_cons = NEXT_CMP(cp_cons);
 873         }
 874         rxr->rx_agg_prod = prod;
 875         rxr->rx_sw_agg_prod = sw_prod;
 876 }
 877
 878 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 879                                         struct bnxt_rx_ring_info *rxr,
 880                                         u16 cons, void *data, u8 *data_ptr,
 881                                         dma_addr_t dma_addr,
 882                                         unsigned int offset_and_len)
 883 {
 884         unsigned int payload = offset_and_len >> 16;
 885         unsigned int len = offset_and_len & 0xffff;
 886         struct skb_frag_struct *frag;
 887         struct page *page = data;
 888         u16 prod = rxr->rx_prod;
 889         struct sk_buff *skb;
 890         int off, err;
 891
 892         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 893         if (unlikely(err)) {
 894                 bnxt_reuse_rx_data(rxr, cons, data);
 895                 return NULL;
 896         }
 897         dma_addr -= bp->rx_dma_offset;
 898         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 899                              DMA_ATTR_WEAK_ORDERING);
 900
 901         if (unlikely(!payload))
 902                 payload = eth_get_headlen(data_ptr, len);
 903
 904         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 905         if (!skb) {
 906                 __free_page(page);
 907                 return NULL;
 908         }
 909
 910         off = (void *)data_ptr - page_address(page);
 911         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 912         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 913                payload + NET_IP_ALIGN);
 914
 915         frag = &skb_shinfo(skb)->frags[0];
 916         skb_frag_size_sub(frag, payload);
 917         frag->page_offset += payload;
 918         skb->data_len -= payload;
 919         skb->tail += payload;
 920
 921         return skb;
 922 }
 923
 924 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 925                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 926                                    void *data, u8 *data_ptr,
 927                                    dma_addr_t dma_addr,
 928                                    unsigned int offset_and_len)
 929 {
 930         u16 prod = rxr->rx_prod;
 931         struct sk_buff *skb;
 932         int err;
 933
 934         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 935         if (unlikely(err)) {
 936                 bnxt_reuse_rx_data(rxr, cons, data);
 937                 return NULL;
 938         }
 939
 940         skb = build_skb(data, 0);
 941         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 942                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 943         if (!skb) {
 944                 kfree(data);
 945                 return NULL;
 946         }
 947
 948         skb_reserve(skb, bp->rx_offset);
 949         skb_put(skb, offset_and_len & 0xffff);
 950         return skb;
 951 }
 952
 953 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
 954                                      struct bnxt_cp_ring_info *cpr,
 955                                      struct sk_buff *skb, u16 cp_cons,
 956                                      u32 agg_bufs)
 957 {
 958         struct bnxt_napi *bnapi = cpr->bnapi;
 959         struct pci_dev *pdev = bp->pdev;
 960         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 961         u16 prod = rxr->rx_agg_prod;
 962         u32 i;
 963
 964         for (i = 0; i < agg_bufs; i++) {
 965                 u16 cons, frag_len;
 966                 struct rx_agg_cmp *agg;
 967                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 968                 struct page *page;
 969                 dma_addr_t mapping;
 970
 971                 agg = (struct rx_agg_cmp *)
 972                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 973                 cons = agg->rx_agg_cmp_opaque;
 974                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 975                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 976
 977                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 978                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 979                                    cons_rx_buf->offset, frag_len);
 980                 __clear_bit(cons, rxr->rx_agg_bmap);
 981
 982                 /* It is possible for bnxt_alloc_rx_page() to allocate
 983                  * a sw_prod index that equals the cons index, so we
 984                  * need to clear the cons entry now.
 985                  */
 986                 mapping = cons_rx_buf->mapping;
 987                 page = cons_rx_buf->page;
 988                 cons_rx_buf->page = NULL;
 989
 990                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 991                         struct skb_shared_info *shinfo;
 992                         unsigned int nr_frags;
 993
 994                         shinfo = skb_shinfo(skb);
 995                         nr_frags = --shinfo->nr_frags;
 996                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 997
 998                         dev_kfree_skb(skb);
 999
1000                         cons_rx_buf->page = page;
1001
1002                         /* Update prod since possibly some pages have been
1003                          * allocated already.
1004                          */
1005                         rxr->rx_agg_prod = prod;
1006                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1007                         return NULL;
1008                 }
1009
1010                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1011                                      PCI_DMA_FROMDEVICE,
1012                                      DMA_ATTR_WEAK_ORDERING);
1013
1014                 skb->data_len += frag_len;
1015                 skb->len += frag_len;
1016                 skb->truesize += PAGE_SIZE;
1017
1018                 prod = NEXT_RX_AGG(prod);
1019                 cp_cons = NEXT_CMP(cp_cons);
1020         }
1021         rxr->rx_agg_prod = prod;
1022         return skb;
1023 }
1024
1025 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1026                                u8 agg_bufs, u32 *raw_cons)
1027 {
1028         u16 last;
1029         struct rx_agg_cmp *agg;
1030
1031         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1032         last = RING_CMP(*raw_cons);
1033         agg = (struct rx_agg_cmp *)
1034                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1035         return RX_AGG_CMP_VALID(agg, *raw_cons);
1036 }
1037
1038 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1039                                             unsigned int len,
1040                                             dma_addr_t mapping)
1041 {
1042         struct bnxt *bp = bnapi->bp;
1043         struct pci_dev *pdev = bp->pdev;
1044         struct sk_buff *skb;
1045
1046         skb = napi_alloc_skb(&bnapi->napi, len);
1047         if (!skb)
1048                 return NULL;
1049
1050         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1051                                 bp->rx_dir);
1052
1053         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1054                len + NET_IP_ALIGN);
1055
1056         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1057                                    bp->rx_dir);
1058
1059         skb_put(skb, len);
1060         return skb;
1061 }
1062
1063 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1064                            u32 *raw_cons, void *cmp)
1065 {
1066         struct rx_cmp *rxcmp = cmp;
1067         u32 tmp_raw_cons = *raw_cons;
1068         u8 cmp_type, agg_bufs = 0;
1069
1070         cmp_type = RX_CMP_TYPE(rxcmp);
1071
1072         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1073                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1074                             RX_CMP_AGG_BUFS) >>
1075                            RX_CMP_AGG_BUFS_SHIFT;
1076         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1077                 struct rx_tpa_end_cmp *tpa_end = cmp;
1078
1079                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1080                             RX_TPA_END_CMP_AGG_BUFS) >>
1081                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1082         }
1083
1084         if (agg_bufs) {
1085                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1086                         return -EBUSY;
1087         }
1088         *raw_cons = tmp_raw_cons;
1089         return 0;
1090 }
1091
1092 static void bnxt_queue_sp_work(struct bnxt *bp)
1093 {
1094         if (BNXT_PF(bp))
1095                 queue_work(bnxt_pf_wq, &bp->sp_task);
1096         else
1097                 schedule_work(&bp->sp_task);
1098 }
1099
1100 static void bnxt_cancel_sp_work(struct bnxt *bp)
1101 {
1102         if (BNXT_PF(bp))
1103                 flush_workqueue(bnxt_pf_wq);
1104         else
1105                 cancel_work_sync(&bp->sp_task);
1106 }
1107
1108 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1109 {
1110         if (!rxr->bnapi->in_reset) {
1111                 rxr->bnapi->in_reset = true;
1112                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1113                 bnxt_queue_sp_work(bp);
1114         }
1115         rxr->rx_next_cons = 0xffff;
1116 }
1117
1118 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1119                            struct rx_tpa_start_cmp *tpa_start,
1120                            struct rx_tpa_start_cmp_ext *tpa_start1)
1121 {
1122         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1123         u16 cons, prod;
1124         struct bnxt_tpa_info *tpa_info;
1125         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1126         struct rx_bd *prod_bd;
1127         dma_addr_t mapping;
1128
1129         cons = tpa_start->rx_tpa_start_cmp_opaque;
1130         prod = rxr->rx_prod;
1131         cons_rx_buf = &rxr->rx_buf_ring[cons];
1132         prod_rx_buf = &rxr->rx_buf_ring[prod];
1133         tpa_info = &rxr->rx_tpa[agg_id];
1134
1135         if (unlikely(cons != rxr->rx_next_cons)) {
1136                 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1137                             cons, rxr->rx_next_cons);
1138                 bnxt_sched_reset(bp, rxr);
1139                 return;
1140         }
1141         /* Store cfa_code in tpa_info to use in tpa_end
1142          * completion processing.
1143          */
1144         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1145         prod_rx_buf->data = tpa_info->data;
1146         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1147
1148         mapping = tpa_info->mapping;
1149         prod_rx_buf->mapping = mapping;
1150
1151         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1152
1153         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1154
1155         tpa_info->data = cons_rx_buf->data;
1156         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1157         cons_rx_buf->data = NULL;
1158         tpa_info->mapping = cons_rx_buf->mapping;
1159
1160         tpa_info->len =
1161                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1162                                 RX_TPA_START_CMP_LEN_SHIFT;
1163         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1164                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1165
1166                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1167                 tpa_info->gso_type = SKB_GSO_TCPV4;
1168                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1169                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1170                         tpa_info->gso_type = SKB_GSO_TCPV6;
1171                 tpa_info->rss_hash =
1172                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1173         } else {
1174                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1175                 tpa_info->gso_type = 0;
1176                 if (netif_msg_rx_err(bp))
1177                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1178         }
1179         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1180         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1181         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1182
1183         rxr->rx_prod = NEXT_RX(prod);
1184         cons = NEXT_RX(cons);
1185         rxr->rx_next_cons = NEXT_RX(cons);
1186         cons_rx_buf = &rxr->rx_buf_ring[cons];
1187
1188         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1189         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1190         cons_rx_buf->data = NULL;
1191 }
1192
1193 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1194                            u32 agg_bufs)
1195 {
1196         if (agg_bufs)
1197                 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1198 }
1199
1200 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1201                                            int payload_off, int tcp_ts,
1202                                            struct sk_buff *skb)
1203 {
1204 #ifdef CONFIG_INET
1205         struct tcphdr *th;
1206         int len, nw_off;
1207         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1208         u32 hdr_info = tpa_info->hdr_info;
1209         bool loopback = false;
1210
1211         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1212         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1213         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1214
1215         /* If the packet is an internal loopback packet, the offsets will
1216          * have an extra 4 bytes.
1217          */
1218         if (inner_mac_off == 4) {
1219                 loopback = true;
1220         } else if (inner_mac_off > 4) {
1221                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1222                                             ETH_HLEN - 2));
1223
1224                 /* We only support inner iPv4/ipv6.  If we don't see the
1225                  * correct protocol ID, it must be a loopback packet where
1226                  * the offsets are off by 4.
1227                  */
1228                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1229                         loopback = true;
1230         }
1231         if (loopback) {
1232                 /* internal loopback packet, subtract all offsets by 4 */
1233                 inner_ip_off -= 4;
1234                 inner_mac_off -= 4;
1235                 outer_ip_off -= 4;
1236         }
1237
1238         nw_off = inner_ip_off - ETH_HLEN;
1239         skb_set_network_header(skb, nw_off);
1240         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1241                 struct ipv6hdr *iph = ipv6_hdr(skb);
1242
1243                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1244                 len = skb->len - skb_transport_offset(skb);
1245                 th = tcp_hdr(skb);
1246                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1247         } else {
1248                 struct iphdr *iph = ip_hdr(skb);
1249
1250                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1251                 len = skb->len - skb_transport_offset(skb);
1252                 th = tcp_hdr(skb);
1253                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1254         }
1255
1256         if (inner_mac_off) { /* tunnel */
1257                 struct udphdr *uh = NULL;
1258                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1259                                             ETH_HLEN - 2));
1260
1261                 if (proto == htons(ETH_P_IP)) {
1262                         struct iphdr *iph = (struct iphdr *)skb->data;
1263
1264                         if (iph->protocol == IPPROTO_UDP)
1265                                 uh = (struct udphdr *)(iph + 1);
1266                 } else {
1267                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1268
1269                         if (iph->nexthdr == IPPROTO_UDP)
1270                                 uh = (struct udphdr *)(iph + 1);
1271                 }
1272                 if (uh) {
1273                         if (uh->check)
1274                                 skb_shinfo(skb)->gso_type |=
1275                                         SKB_GSO_UDP_TUNNEL_CSUM;
1276                         else
1277                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1278                 }
1279         }
1280 #endif
1281         return skb;
1282 }
1283
1284 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1285 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1286
1287 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1288                                            int payload_off, int tcp_ts,
1289                                            struct sk_buff *skb)
1290 {
1291 #ifdef CONFIG_INET
1292         struct tcphdr *th;
1293         int len, nw_off, tcp_opt_len = 0;
1294
1295         if (tcp_ts)
1296                 tcp_opt_len = 12;
1297
1298         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1299                 struct iphdr *iph;
1300
1301                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1302                          ETH_HLEN;
1303                 skb_set_network_header(skb, nw_off);
1304                 iph = ip_hdr(skb);
1305                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1306                 len = skb->len - skb_transport_offset(skb);
1307                 th = tcp_hdr(skb);
1308                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1309         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1310                 struct ipv6hdr *iph;
1311
1312                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1313                          ETH_HLEN;
1314                 skb_set_network_header(skb, nw_off);
1315                 iph = ipv6_hdr(skb);
1316                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1317                 len = skb->len - skb_transport_offset(skb);
1318                 th = tcp_hdr(skb);
1319                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1320         } else {
1321                 dev_kfree_skb_any(skb);
1322                 return NULL;
1323         }
1324
1325         if (nw_off) { /* tunnel */
1326                 struct udphdr *uh = NULL;
1327
1328                 if (skb->protocol == htons(ETH_P_IP)) {
1329                         struct iphdr *iph = (struct iphdr *)skb->data;
1330
1331                         if (iph->protocol == IPPROTO_UDP)
1332                                 uh = (struct udphdr *)(iph + 1);
1333                 } else {
1334                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1335
1336                         if (iph->nexthdr == IPPROTO_UDP)
1337                                 uh = (struct udphdr *)(iph + 1);
1338                 }
1339                 if (uh) {
1340                         if (uh->check)
1341                                 skb_shinfo(skb)->gso_type |=
1342                                         SKB_GSO_UDP_TUNNEL_CSUM;
1343                         else
1344                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1345                 }
1346         }
1347 #endif
1348         return skb;
1349 }
1350
1351 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1352                                            struct bnxt_tpa_info *tpa_info,
1353                                            struct rx_tpa_end_cmp *tpa_end,
1354                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1355                                            struct sk_buff *skb)
1356 {
1357 #ifdef CONFIG_INET
1358         int payload_off;
1359         u16 segs;
1360
1361         segs = TPA_END_TPA_SEGS(tpa_end);
1362         if (segs == 1)
1363                 return skb;
1364
1365         NAPI_GRO_CB(skb)->count = segs;
1366         skb_shinfo(skb)->gso_size =
1367                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1368         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1369         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1370                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1371                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1372         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1373         if (likely(skb))
1374                 tcp_gro_complete(skb);
1375 #endif
1376         return skb;
1377 }
1378
1379 /* Given the cfa_code of a received packet determine which
1380  * netdev (vf-rep or PF) the packet is destined to.
1381  */
1382 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1383 {
1384         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1385
1386         /* if vf-rep dev is NULL, the must belongs to the PF */
1387         return dev ? dev : bp->dev;
1388 }
1389
1390 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1391                                            struct bnxt_cp_ring_info *cpr,
1392                                            u32 *raw_cons,
1393                                            struct rx_tpa_end_cmp *tpa_end,
1394                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1395                                            u8 *event)
1396 {
1397         struct bnxt_napi *bnapi = cpr->bnapi;
1398         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1399         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1400         u8 *data_ptr, agg_bufs;
1401         u16 cp_cons = RING_CMP(*raw_cons);
1402         unsigned int len;
1403         struct bnxt_tpa_info *tpa_info;
1404         dma_addr_t mapping;
1405         struct sk_buff *skb;
1406         void *data;
1407
1408         if (unlikely(bnapi->in_reset)) {
1409                 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1410
1411                 if (rc < 0)
1412                         return ERR_PTR(-EBUSY);
1413                 return NULL;
1414         }
1415
1416         tpa_info = &rxr->rx_tpa[agg_id];
1417         data = tpa_info->data;
1418         data_ptr = tpa_info->data_ptr;
1419         prefetch(data_ptr);
1420         len = tpa_info->len;
1421         mapping = tpa_info->mapping;
1422
1423         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1424                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1425
1426         if (agg_bufs) {
1427                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1428                         return ERR_PTR(-EBUSY);
1429
1430                 *event |= BNXT_AGG_EVENT;
1431                 cp_cons = NEXT_CMP(cp_cons);
1432         }
1433
1434         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1435                 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1436                 if (agg_bufs > MAX_SKB_FRAGS)
1437                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1438                                     agg_bufs, (int)MAX_SKB_FRAGS);
1439                 return NULL;
1440         }
1441
1442         if (len <= bp->rx_copy_thresh) {
1443                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1444                 if (!skb) {
1445                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1446                         return NULL;
1447                 }
1448         } else {
1449                 u8 *new_data;
1450                 dma_addr_t new_mapping;
1451
1452                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1453                 if (!new_data) {
1454                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1455                         return NULL;
1456                 }
1457
1458                 tpa_info->data = new_data;
1459                 tpa_info->data_ptr = new_data + bp->rx_offset;
1460                 tpa_info->mapping = new_mapping;
1461
1462                 skb = build_skb(data, 0);
1463                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1464                                        bp->rx_buf_use_size, bp->rx_dir,
1465                                        DMA_ATTR_WEAK_ORDERING);
1466
1467                 if (!skb) {
1468                         kfree(data);
1469                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1470                         return NULL;
1471                 }
1472                 skb_reserve(skb, bp->rx_offset);
1473                 skb_put(skb, len);
1474         }
1475
1476         if (agg_bufs) {
1477                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1478                 if (!skb) {
1479                         /* Page reuse already handled by bnxt_rx_pages(). */
1480                         return NULL;
1481                 }
1482         }
1483
1484         skb->protocol =
1485                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1486
1487         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1488                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1489
1490         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1491             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1492                 u16 vlan_proto = tpa_info->metadata >>
1493                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1494                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1495
1496                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1497         }
1498
1499         skb_checksum_none_assert(skb);
1500         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1501                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1502                 skb->csum_level =
1503                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1504         }
1505
1506         if (TPA_END_GRO(tpa_end))
1507                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1508
1509         return skb;
1510 }
1511
1512 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1513                              struct sk_buff *skb)
1514 {
1515         if (skb->dev != bp->dev) {
1516                 /* this packet belongs to a vf-rep */
1517                 bnxt_vf_rep_rx(bp, skb);
1518                 return;
1519         }
1520         skb_record_rx_queue(skb, bnapi->index);
1521         napi_gro_receive(&bnapi->napi, skb);
1522 }
1523
1524 /* returns the following:
1525  * 1       - 1 packet successfully received
1526  * 0       - successful TPA_START, packet not completed yet
1527  * -EBUSY  - completion ring does not have all the agg buffers yet
1528  * -ENOMEM - packet aborted due to out of memory
1529  * -EIO    - packet aborted due to hw error indicated in BD
1530  */
1531 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1532                        u32 *raw_cons, u8 *event)
1533 {
1534         struct bnxt_napi *bnapi = cpr->bnapi;
1535         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1536         struct net_device *dev = bp->dev;
1537         struct rx_cmp *rxcmp;
1538         struct rx_cmp_ext *rxcmp1;
1539         u32 tmp_raw_cons = *raw_cons;
1540         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1541         struct bnxt_sw_rx_bd *rx_buf;
1542         unsigned int len;
1543         u8 *data_ptr, agg_bufs, cmp_type;
1544         dma_addr_t dma_addr;
1545         struct sk_buff *skb;
1546         void *data;
1547         int rc = 0;
1548         u32 misc;
1549
1550         rxcmp = (struct rx_cmp *)
1551                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1552
1553         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1554         cp_cons = RING_CMP(tmp_raw_cons);
1555         rxcmp1 = (struct rx_cmp_ext *)
1556                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1557
1558         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1559                 return -EBUSY;
1560
1561         cmp_type = RX_CMP_TYPE(rxcmp);
1562
1563         prod = rxr->rx_prod;
1564
1565         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1566                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1567                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1568
1569                 *event |= BNXT_RX_EVENT;
1570                 goto next_rx_no_prod_no_len;
1571
1572         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1573                 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1574                                    (struct rx_tpa_end_cmp *)rxcmp,
1575                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1576
1577                 if (IS_ERR(skb))
1578                         return -EBUSY;
1579
1580                 rc = -ENOMEM;
1581                 if (likely(skb)) {
1582                         bnxt_deliver_skb(bp, bnapi, skb);
1583                         rc = 1;
1584                 }
1585                 *event |= BNXT_RX_EVENT;
1586                 goto next_rx_no_prod_no_len;
1587         }
1588
1589         cons = rxcmp->rx_cmp_opaque;
1590         if (unlikely(cons != rxr->rx_next_cons)) {
1591                 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1592
1593                 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1594                             cons, rxr->rx_next_cons);
1595                 bnxt_sched_reset(bp, rxr);
1596                 return rc1;
1597         }
1598         rx_buf = &rxr->rx_buf_ring[cons];
1599         data = rx_buf->data;
1600         data_ptr = rx_buf->data_ptr;
1601         prefetch(data_ptr);
1602
1603         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1604         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1605
1606         if (agg_bufs) {
1607                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1608                         return -EBUSY;
1609
1610                 cp_cons = NEXT_CMP(cp_cons);
1611                 *event |= BNXT_AGG_EVENT;
1612         }
1613         *event |= BNXT_RX_EVENT;
1614
1615         rx_buf->data = NULL;
1616         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1617                 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1618
1619                 bnxt_reuse_rx_data(rxr, cons, data);
1620                 if (agg_bufs)
1621                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1622
1623                 rc = -EIO;
1624                 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1625                         netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1626                         bnxt_sched_reset(bp, rxr);
1627                 }
1628                 goto next_rx;
1629         }
1630
1631         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1632         dma_addr = rx_buf->mapping;
1633
1634         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1635                 rc = 1;
1636                 goto next_rx;
1637         }
1638
1639         if (len <= bp->rx_copy_thresh) {
1640                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1641                 bnxt_reuse_rx_data(rxr, cons, data);
1642                 if (!skb) {
1643                         rc = -ENOMEM;
1644                         goto next_rx;
1645                 }
1646         } else {
1647                 u32 payload;
1648
1649                 if (rx_buf->data_ptr == data_ptr)
1650                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1651                 else
1652                         payload = 0;
1653                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1654                                       payload | len);
1655                 if (!skb) {
1656                         rc = -ENOMEM;
1657                         goto next_rx;
1658                 }
1659         }
1660
1661         if (agg_bufs) {
1662                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1663                 if (!skb) {
1664                         rc = -ENOMEM;
1665                         goto next_rx;
1666                 }
1667         }
1668
1669         if (RX_CMP_HASH_VALID(rxcmp)) {
1670                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1671                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1672
1673                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1674                 if (hash_type != 1 && hash_type != 3)
1675                         type = PKT_HASH_TYPE_L3;
1676                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1677         }
1678
1679         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1680         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1681
1682         if ((rxcmp1->rx_cmp_flags2 &
1683              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1684             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1685                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1686                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1687                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1688
1689                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1690         }
1691
1692         skb_checksum_none_assert(skb);
1693         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1694                 if (dev->features & NETIF_F_RXCSUM) {
1695                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1696                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1697                 }
1698         } else {
1699                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1700                         if (dev->features & NETIF_F_RXCSUM)
1701                                 bnapi->cp_ring.rx_l4_csum_errors++;
1702                 }
1703         }
1704
1705         bnxt_deliver_skb(bp, bnapi, skb);
1706         rc = 1;
1707
1708 next_rx:
1709         rxr->rx_prod = NEXT_RX(prod);
1710         rxr->rx_next_cons = NEXT_RX(cons);
1711
1712         cpr->rx_packets += 1;
1713         cpr->rx_bytes += len;
1714
1715 next_rx_no_prod_no_len:
1716         *raw_cons = tmp_raw_cons;
1717
1718         return rc;
1719 }
1720
1721 /* In netpoll mode, if we are using a combined completion ring, we need to
1722  * discard the rx packets and recycle the buffers.
1723  */
1724 static int bnxt_force_rx_discard(struct bnxt *bp,
1725                                  struct bnxt_cp_ring_info *cpr,
1726                                  u32 *raw_cons, u8 *event)
1727 {
1728         u32 tmp_raw_cons = *raw_cons;
1729         struct rx_cmp_ext *rxcmp1;
1730         struct rx_cmp *rxcmp;
1731         u16 cp_cons;
1732         u8 cmp_type;
1733
1734         cp_cons = RING_CMP(tmp_raw_cons);
1735         rxcmp = (struct rx_cmp *)
1736                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1737
1738         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1739         cp_cons = RING_CMP(tmp_raw_cons);
1740         rxcmp1 = (struct rx_cmp_ext *)
1741                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1742
1743         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1744                 return -EBUSY;
1745
1746         cmp_type = RX_CMP_TYPE(rxcmp);
1747         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1748                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1749                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1750         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1751                 struct rx_tpa_end_cmp_ext *tpa_end1;
1752
1753                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1754                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1755                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1756         }
1757         return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1758 }
1759
1760 #define BNXT_GET_EVENT_PORT(data)       \
1761         ((data) &                       \
1762          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1763
1764 static int bnxt_async_event_process(struct bnxt *bp,
1765                                     struct hwrm_async_event_cmpl *cmpl)
1766 {
1767         u16 event_id = le16_to_cpu(cmpl->event_id);
1768
1769         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1770         switch (event_id) {
1771         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1772                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1773                 struct bnxt_link_info *link_info = &bp->link_info;
1774
1775                 if (BNXT_VF(bp))
1776                         goto async_event_process_exit;
1777
1778                 /* print unsupported speed warning in forced speed mode only */
1779                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1780                     (data1 & 0x20000)) {
1781                         u16 fw_speed = link_info->force_link_speed;
1782                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1783
1784                         if (speed != SPEED_UNKNOWN)
1785                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1786                                             speed);
1787                 }
1788                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1789         }
1790         /* fall through */
1791         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1792                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1793                 break;
1794         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1795                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1796                 break;
1797         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1798                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1799                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1800
1801                 if (BNXT_VF(bp))
1802                         break;
1803
1804                 if (bp->pf.port_id != port_id)
1805                         break;
1806
1807                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1808                 break;
1809         }
1810         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1811                 if (BNXT_PF(bp))
1812                         goto async_event_process_exit;
1813                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1814                 break;
1815         default:
1816                 goto async_event_process_exit;
1817         }
1818         bnxt_queue_sp_work(bp);
1819 async_event_process_exit:
1820         bnxt_ulp_async_events(bp, cmpl);
1821         return 0;
1822 }
1823
1824 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1825 {
1826         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1827         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1828         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1829                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1830
1831         switch (cmpl_type) {
1832         case CMPL_BASE_TYPE_HWRM_DONE:
1833                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1834                 if (seq_id == bp->hwrm_intr_seq_id)
1835                         bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1836                 else
1837                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1838                 break;
1839
1840         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1841                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1842
1843                 if ((vf_id < bp->pf.first_vf_id) ||
1844                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1845                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1846                                    vf_id);
1847                         return -EINVAL;
1848                 }
1849
1850                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1851                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1852                 bnxt_queue_sp_work(bp);
1853                 break;
1854
1855         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1856                 bnxt_async_event_process(bp,
1857                                          (struct hwrm_async_event_cmpl *)txcmp);
1858
1859         default:
1860                 break;
1861         }
1862
1863         return 0;
1864 }
1865
1866 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1867 {
1868         struct bnxt_napi *bnapi = dev_instance;
1869         struct bnxt *bp = bnapi->bp;
1870         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1871         u32 cons = RING_CMP(cpr->cp_raw_cons);
1872
1873         cpr->event_ctr++;
1874         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1875         napi_schedule(&bnapi->napi);
1876         return IRQ_HANDLED;
1877 }
1878
1879 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1880 {
1881         u32 raw_cons = cpr->cp_raw_cons;
1882         u16 cons = RING_CMP(raw_cons);
1883         struct tx_cmp *txcmp;
1884
1885         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1886
1887         return TX_CMP_VALID(txcmp, raw_cons);
1888 }
1889
1890 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1891 {
1892         struct bnxt_napi *bnapi = dev_instance;
1893         struct bnxt *bp = bnapi->bp;
1894         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1895         u32 cons = RING_CMP(cpr->cp_raw_cons);
1896         u32 int_status;
1897
1898         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1899
1900         if (!bnxt_has_work(bp, cpr)) {
1901                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1902                 /* return if erroneous interrupt */
1903                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1904                         return IRQ_NONE;
1905         }
1906
1907         /* disable ring IRQ */
1908         BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1909
1910         /* Return here if interrupt is shared and is disabled. */
1911         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1912                 return IRQ_HANDLED;
1913
1914         napi_schedule(&bnapi->napi);
1915         return IRQ_HANDLED;
1916 }
1917
1918 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1919                             int budget)
1920 {
1921         struct bnxt_napi *bnapi = cpr->bnapi;
1922         u32 raw_cons = cpr->cp_raw_cons;
1923         u32 cons;
1924         int tx_pkts = 0;
1925         int rx_pkts = 0;
1926         u8 event = 0;
1927         struct tx_cmp *txcmp;
1928
1929         cpr->has_more_work = 0;
1930         while (1) {
1931                 int rc;
1932
1933                 cons = RING_CMP(raw_cons);
1934                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1935
1936                 if (!TX_CMP_VALID(txcmp, raw_cons))
1937                         break;
1938
1939                 /* The valid test of the entry must be done first before
1940                  * reading any further.
1941                  */
1942                 dma_rmb();
1943                 cpr->had_work_done = 1;
1944                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1945                         tx_pkts++;
1946                         /* return full budget so NAPI will complete. */
1947                         if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1948                                 rx_pkts = budget;
1949                                 raw_cons = NEXT_RAW_CMP(raw_cons);
1950                                 if (budget)
1951                                         cpr->has_more_work = 1;
1952                                 break;
1953                         }
1954                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1955                         if (likely(budget))
1956                                 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1957                         else
1958                                 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1959                                                            &event);
1960                         if (likely(rc >= 0))
1961                                 rx_pkts += rc;
1962                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1963                          * the NAPI budget.  Otherwise, we may potentially loop
1964                          * here forever if we consistently cannot allocate
1965                          * buffers.
1966                          */
1967                         else if (rc == -ENOMEM && budget)
1968                                 rx_pkts++;
1969                         else if (rc == -EBUSY)  /* partial completion */
1970                                 break;
1971                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1972                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1973                                     (TX_CMP_TYPE(txcmp) ==
1974                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1975                                     (TX_CMP_TYPE(txcmp) ==
1976                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1977                         bnxt_hwrm_handler(bp, txcmp);
1978                 }
1979                 raw_cons = NEXT_RAW_CMP(raw_cons);
1980
1981                 if (rx_pkts && rx_pkts == budget) {
1982                         cpr->has_more_work = 1;
1983                         break;
1984                 }
1985         }
1986
1987         if (event & BNXT_TX_EVENT) {
1988                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1989                 u16 prod = txr->tx_prod;
1990
1991                 /* Sync BD data before updating doorbell */
1992                 wmb();
1993
1994                 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
1995         }
1996
1997         cpr->cp_raw_cons = raw_cons;
1998         bnapi->tx_pkts += tx_pkts;
1999         bnapi->events |= event;
2000         return rx_pkts;
2001 }
2002
2003 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2004 {
2005         if (bnapi->tx_pkts) {
2006                 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2007                 bnapi->tx_pkts = 0;
2008         }
2009
2010         if (bnapi->events & BNXT_RX_EVENT) {
2011                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2012
2013                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2014                 if (bnapi->events & BNXT_AGG_EVENT)
2015                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2016         }
2017         bnapi->events = 0;
2018 }
2019
2020 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2021                           int budget)
2022 {
2023         struct bnxt_napi *bnapi = cpr->bnapi;
2024         int rx_pkts;
2025
2026         rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2027
2028         /* ACK completion ring before freeing tx ring and producing new
2029          * buffers in rx/agg rings to prevent overflowing the completion
2030          * ring.
2031          */
2032         bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2033
2034         __bnxt_poll_work_done(bp, bnapi);
2035         return rx_pkts;
2036 }
2037
2038 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2039 {
2040         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2041         struct bnxt *bp = bnapi->bp;
2042         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2043         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2044         struct tx_cmp *txcmp;
2045         struct rx_cmp_ext *rxcmp1;
2046         u32 cp_cons, tmp_raw_cons;
2047         u32 raw_cons = cpr->cp_raw_cons;
2048         u32 rx_pkts = 0;
2049         u8 event = 0;
2050
2051         while (1) {
2052                 int rc;
2053
2054                 cp_cons = RING_CMP(raw_cons);
2055                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2056
2057                 if (!TX_CMP_VALID(txcmp, raw_cons))
2058                         break;
2059
2060                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2061                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2062                         cp_cons = RING_CMP(tmp_raw_cons);
2063                         rxcmp1 = (struct rx_cmp_ext *)
2064                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2065
2066                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2067                                 break;
2068
2069                         /* force an error to recycle the buffer */
2070                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2071                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2072
2073                         rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2074                         if (likely(rc == -EIO) && budget)
2075                                 rx_pkts++;
2076                         else if (rc == -EBUSY)  /* partial completion */
2077                                 break;
2078                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2079                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2080                         bnxt_hwrm_handler(bp, txcmp);
2081                 } else {
2082                         netdev_err(bp->dev,
2083                                    "Invalid completion received on special ring\n");
2084                 }
2085                 raw_cons = NEXT_RAW_CMP(raw_cons);
2086
2087                 if (rx_pkts == budget)
2088                         break;
2089         }
2090
2091         cpr->cp_raw_cons = raw_cons;
2092         BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2093         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2094
2095         if (event & BNXT_AGG_EVENT)
2096                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2097
2098         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2099                 napi_complete_done(napi, rx_pkts);
2100                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2101         }
2102         return rx_pkts;
2103 }
2104
2105 static int bnxt_poll(struct napi_struct *napi, int budget)
2106 {
2107         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2108         struct bnxt *bp = bnapi->bp;
2109         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2110         int work_done = 0;
2111
2112         while (1) {
2113                 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2114
2115                 if (work_done >= budget) {
2116                         if (!budget)
2117                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2118                         break;
2119                 }
2120
2121                 if (!bnxt_has_work(bp, cpr)) {
2122                         if (napi_complete_done(napi, work_done))
2123                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2124                         break;
2125                 }
2126         }
2127         if (bp->flags & BNXT_FLAG_DIM) {
2128                 struct net_dim_sample dim_sample;
2129
2130                 net_dim_sample(cpr->event_ctr,
2131                                cpr->rx_packets,
2132                                cpr->rx_bytes,
2133                                &dim_sample);
2134                 net_dim(&cpr->dim, dim_sample);
2135         }
2136         mmiowb();
2137         return work_done;
2138 }
2139
2140 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2141 {
2142         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2143         int i, work_done = 0;
2144
2145         for (i = 0; i < 2; i++) {
2146                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2147
2148                 if (cpr2) {
2149                         work_done += __bnxt_poll_work(bp, cpr2,
2150                                                       budget - work_done);
2151                         cpr->has_more_work |= cpr2->has_more_work;
2152                 }
2153         }
2154         return work_done;
2155 }
2156
2157 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2158                                  u64 dbr_type, bool all)
2159 {
2160         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2161         int i;
2162
2163         for (i = 0; i < 2; i++) {
2164                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2165                 struct bnxt_db_info *db;
2166
2167                 if (cpr2 && (all || cpr2->had_work_done)) {
2168                         db = &cpr2->cp_db;
2169                         writeq(db->db_key64 | dbr_type |
2170                                RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2171                         cpr2->had_work_done = 0;
2172                 }
2173         }
2174         __bnxt_poll_work_done(bp, bnapi);
2175 }
2176
2177 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2178 {
2179         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2180         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2181         u32 raw_cons = cpr->cp_raw_cons;
2182         struct bnxt *bp = bnapi->bp;
2183         struct nqe_cn *nqcmp;
2184         int work_done = 0;
2185         u32 cons;
2186
2187         if (cpr->has_more_work) {
2188                 cpr->has_more_work = 0;
2189                 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2190                 if (cpr->has_more_work) {
2191                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2192                         return work_done;
2193                 }
2194                 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2195                 if (napi_complete_done(napi, work_done))
2196                         BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2197                 return work_done;
2198         }
2199         while (1) {
2200                 cons = RING_CMP(raw_cons);
2201                 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2202
2203                 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2204                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2205                                              false);
2206                         cpr->cp_raw_cons = raw_cons;
2207                         if (napi_complete_done(napi, work_done))
2208                                 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2209                                                   cpr->cp_raw_cons);
2210                         return work_done;
2211                 }
2212
2213                 /* The valid test of the entry must be done first before
2214                  * reading any further.
2215                  */
2216                 dma_rmb();
2217
2218                 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2219                         u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2220                         struct bnxt_cp_ring_info *cpr2;
2221
2222                         cpr2 = cpr->cp_ring_arr[idx];
2223                         work_done += __bnxt_poll_work(bp, cpr2,
2224                                                       budget - work_done);
2225                         cpr->has_more_work = cpr2->has_more_work;
2226                 } else {
2227                         bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2228                 }
2229                 raw_cons = NEXT_RAW_CMP(raw_cons);
2230                 if (cpr->has_more_work)
2231                         break;
2232         }
2233         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2234         cpr->cp_raw_cons = raw_cons;
2235         return work_done;
2236 }
2237
2238 static void bnxt_free_tx_skbs(struct bnxt *bp)
2239 {
2240         int i, max_idx;
2241         struct pci_dev *pdev = bp->pdev;
2242
2243         if (!bp->tx_ring)
2244                 return;
2245
2246         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2247         for (i = 0; i < bp->tx_nr_rings; i++) {
2248                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2249                 int j;
2250
2251                 for (j = 0; j < max_idx;) {
2252                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2253                         struct sk_buff *skb = tx_buf->skb;
2254                         int k, last;
2255
2256                         if (!skb) {
2257                                 j++;
2258                                 continue;
2259                         }
2260
2261                         tx_buf->skb = NULL;
2262
2263                         if (tx_buf->is_push) {
2264                                 dev_kfree_skb(skb);
2265                                 j += 2;
2266                                 continue;
2267                         }
2268
2269                         dma_unmap_single(&pdev->dev,
2270                                          dma_unmap_addr(tx_buf, mapping),
2271                                          skb_headlen(skb),
2272                                          PCI_DMA_TODEVICE);
2273
2274                         last = tx_buf->nr_frags;
2275                         j += 2;
2276                         for (k = 0; k < last; k++, j++) {
2277                                 int ring_idx = j & bp->tx_ring_mask;
2278                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2279
2280                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2281                                 dma_unmap_page(
2282                                         &pdev->dev,
2283                                         dma_unmap_addr(tx_buf, mapping),
2284                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2285                         }
2286                         dev_kfree_skb(skb);
2287                 }
2288                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2289         }
2290 }
2291
2292 static void bnxt_free_rx_skbs(struct bnxt *bp)
2293 {
2294         int i, max_idx, max_agg_idx;
2295         struct pci_dev *pdev = bp->pdev;
2296
2297         if (!bp->rx_ring)
2298                 return;
2299
2300         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2301         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2302         for (i = 0; i < bp->rx_nr_rings; i++) {
2303                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2304                 int j;
2305
2306                 if (rxr->rx_tpa) {
2307                         for (j = 0; j < MAX_TPA; j++) {
2308                                 struct bnxt_tpa_info *tpa_info =
2309                                                         &rxr->rx_tpa[j];
2310                                 u8 *data = tpa_info->data;
2311
2312                                 if (!data)
2313                                         continue;
2314
2315                                 dma_unmap_single_attrs(&pdev->dev,
2316                                                        tpa_info->mapping,
2317                                                        bp->rx_buf_use_size,
2318                                                        bp->rx_dir,
2319                                                        DMA_ATTR_WEAK_ORDERING);
2320
2321                                 tpa_info->data = NULL;
2322
2323                                 kfree(data);
2324                         }
2325                 }
2326
2327                 for (j = 0; j < max_idx; j++) {
2328                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2329                         dma_addr_t mapping = rx_buf->mapping;
2330                         void *data = rx_buf->data;
2331
2332                         if (!data)
2333                                 continue;
2334
2335                         rx_buf->data = NULL;
2336
2337                         if (BNXT_RX_PAGE_MODE(bp)) {
2338                                 mapping -= bp->rx_dma_offset;
2339                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2340                                                      PAGE_SIZE, bp->rx_dir,
2341                                                      DMA_ATTR_WEAK_ORDERING);
2342                                 __free_page(data);
2343                         } else {
2344                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2345                                                        bp->rx_buf_use_size,
2346                                                        bp->rx_dir,
2347                                                        DMA_ATTR_WEAK_ORDERING);
2348                                 kfree(data);
2349                         }
2350                 }
2351
2352                 for (j = 0; j < max_agg_idx; j++) {
2353                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2354                                 &rxr->rx_agg_ring[j];
2355                         struct page *page = rx_agg_buf->page;
2356
2357                         if (!page)
2358                                 continue;
2359
2360                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2361                                              BNXT_RX_PAGE_SIZE,
2362                                              PCI_DMA_FROMDEVICE,
2363                                              DMA_ATTR_WEAK_ORDERING);
2364
2365                         rx_agg_buf->page = NULL;
2366                         __clear_bit(j, rxr->rx_agg_bmap);
2367
2368                         __free_page(page);
2369                 }
2370                 if (rxr->rx_page) {
2371                         __free_page(rxr->rx_page);
2372                         rxr->rx_page = NULL;
2373                 }
2374         }
2375 }
2376
2377 static void bnxt_free_skbs(struct bnxt *bp)
2378 {
2379         bnxt_free_tx_skbs(bp);
2380         bnxt_free_rx_skbs(bp);
2381 }
2382
2383 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2384 {
2385         struct pci_dev *pdev = bp->pdev;
2386         int i;
2387
2388         for (i = 0; i < rmem->nr_pages; i++) {
2389                 if (!rmem->pg_arr[i])
2390                         continue;
2391
2392                 dma_free_coherent(&pdev->dev, rmem->page_size,
2393                                   rmem->pg_arr[i], rmem->dma_arr[i]);
2394
2395                 rmem->pg_arr[i] = NULL;
2396         }
2397         if (rmem->pg_tbl) {
2398                 size_t pg_tbl_size = rmem->nr_pages * 8;
2399
2400                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2401                         pg_tbl_size = rmem->page_size;
2402                 dma_free_coherent(&pdev->dev, pg_tbl_size,
2403                                   rmem->pg_tbl, rmem->pg_tbl_map);
2404                 rmem->pg_tbl = NULL;
2405         }
2406         if (rmem->vmem_size && *rmem->vmem) {
2407                 vfree(*rmem->vmem);
2408                 *rmem->vmem = NULL;
2409         }
2410 }
2411
2412 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2413 {
2414         struct pci_dev *pdev = bp->pdev;
2415         u64 valid_bit = 0;
2416         int i;
2417
2418         if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2419                 valid_bit = PTU_PTE_VALID;
2420         if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2421                 size_t pg_tbl_size = rmem->nr_pages * 8;
2422
2423                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2424                         pg_tbl_size = rmem->page_size;
2425                 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2426                                                   &rmem->pg_tbl_map,
2427                                                   GFP_KERNEL);
2428                 if (!rmem->pg_tbl)
2429                         return -ENOMEM;
2430         }
2431
2432         for (i = 0; i < rmem->nr_pages; i++) {
2433                 u64 extra_bits = valid_bit;
2434
2435                 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2436                                                      rmem->page_size,
2437                                                      &rmem->dma_arr[i],
2438                                                      GFP_KERNEL);
2439                 if (!rmem->pg_arr[i])
2440                         return -ENOMEM;
2441
2442                 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2443                         if (i == rmem->nr_pages - 2 &&
2444                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2445                                 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2446                         else if (i == rmem->nr_pages - 1 &&
2447                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2448                                 extra_bits |= PTU_PTE_LAST;
2449                         rmem->pg_tbl[i] =
2450                                 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2451                 }
2452         }
2453
2454         if (rmem->vmem_size) {
2455                 *rmem->vmem = vzalloc(rmem->vmem_size);
2456                 if (!(*rmem->vmem))
2457                         return -ENOMEM;
2458         }
2459         return 0;
2460 }
2461
2462 static void bnxt_free_rx_rings(struct bnxt *bp)
2463 {
2464         int i;
2465
2466         if (!bp->rx_ring)
2467                 return;
2468
2469         for (i = 0; i < bp->rx_nr_rings; i++) {
2470                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2471                 struct bnxt_ring_struct *ring;
2472
2473                 if (rxr->xdp_prog)
2474                         bpf_prog_put(rxr->xdp_prog);
2475
2476                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2477                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2478
2479                 kfree(rxr->rx_tpa);
2480                 rxr->rx_tpa = NULL;
2481
2482                 kfree(rxr->rx_agg_bmap);
2483                 rxr->rx_agg_bmap = NULL;
2484
2485                 ring = &rxr->rx_ring_struct;
2486                 bnxt_free_ring(bp, &ring->ring_mem);
2487
2488                 ring = &rxr->rx_agg_ring_struct;
2489                 bnxt_free_ring(bp, &ring->ring_mem);
2490         }
2491 }
2492
2493 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2494 {
2495         int i, rc, agg_rings = 0, tpa_rings = 0;
2496
2497         if (!bp->rx_ring)
2498                 return -ENOMEM;
2499
2500         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2501                 agg_rings = 1;
2502
2503         if (bp->flags & BNXT_FLAG_TPA)
2504                 tpa_rings = 1;
2505
2506         for (i = 0; i < bp->rx_nr_rings; i++) {
2507                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2508                 struct bnxt_ring_struct *ring;
2509
2510                 ring = &rxr->rx_ring_struct;
2511
2512                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2513                 if (rc < 0)
2514                         return rc;
2515
2516                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2517                 if (rc)
2518                         return rc;
2519
2520                 ring->grp_idx = i;
2521                 if (agg_rings) {
2522                         u16 mem_size;
2523
2524                         ring = &rxr->rx_agg_ring_struct;
2525                         rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2526                         if (rc)
2527                                 return rc;
2528
2529                         ring->grp_idx = i;
2530                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2531                         mem_size = rxr->rx_agg_bmap_size / 8;
2532                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2533                         if (!rxr->rx_agg_bmap)
2534                                 return -ENOMEM;
2535
2536                         if (tpa_rings) {
2537                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2538                                                 sizeof(struct bnxt_tpa_info),
2539                                                 GFP_KERNEL);
2540                                 if (!rxr->rx_tpa)
2541                                         return -ENOMEM;
2542                         }
2543                 }
2544         }
2545         return 0;
2546 }
2547
2548 static void bnxt_free_tx_rings(struct bnxt *bp)
2549 {
2550         int i;
2551         struct pci_dev *pdev = bp->pdev;
2552
2553         if (!bp->tx_ring)
2554                 return;
2555
2556         for (i = 0; i < bp->tx_nr_rings; i++) {
2557                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2558                 struct bnxt_ring_struct *ring;
2559
2560                 if (txr->tx_push) {
2561                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2562                                           txr->tx_push, txr->tx_push_mapping);
2563                         txr->tx_push = NULL;
2564                 }
2565
2566                 ring = &txr->tx_ring_struct;
2567
2568                 bnxt_free_ring(bp, &ring->ring_mem);
2569         }
2570 }
2571
2572 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2573 {
2574         int i, j, rc;
2575         struct pci_dev *pdev = bp->pdev;
2576
2577         bp->tx_push_size = 0;
2578         if (bp->tx_push_thresh) {
2579                 int push_size;
2580
2581                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2582                                         bp->tx_push_thresh);
2583
2584                 if (push_size > 256) {
2585                         push_size = 0;
2586                         bp->tx_push_thresh = 0;
2587                 }
2588
2589                 bp->tx_push_size = push_size;
2590         }
2591
2592         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2593                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2594                 struct bnxt_ring_struct *ring;
2595                 u8 qidx;
2596
2597                 ring = &txr->tx_ring_struct;
2598
2599                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2600                 if (rc)
2601                         return rc;
2602
2603                 ring->grp_idx = txr->bnapi->index;
2604                 if (bp->tx_push_size) {
2605                         dma_addr_t mapping;
2606
2607                         /* One pre-allocated DMA buffer to backup
2608                          * TX push operation
2609                          */
2610                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2611                                                 bp->tx_push_size,
2612                                                 &txr->tx_push_mapping,
2613                                                 GFP_KERNEL);
2614
2615                         if (!txr->tx_push)
2616                                 return -ENOMEM;
2617
2618                         mapping = txr->tx_push_mapping +
2619                                 sizeof(struct tx_push_bd);
2620                         txr->data_mapping = cpu_to_le64(mapping);
2621
2622                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2623                 }
2624                 qidx = bp->tc_to_qidx[j];
2625                 ring->queue_id = bp->q_info[qidx].queue_id;
2626                 if (i < bp->tx_nr_rings_xdp)
2627                         continue;
2628                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2629                         j++;
2630         }
2631         return 0;
2632 }
2633
2634 static void bnxt_free_cp_rings(struct bnxt *bp)
2635 {
2636         int i;
2637
2638         if (!bp->bnapi)
2639                 return;
2640
2641         for (i = 0; i < bp->cp_nr_rings; i++) {
2642                 struct bnxt_napi *bnapi = bp->bnapi[i];
2643                 struct bnxt_cp_ring_info *cpr;
2644                 struct bnxt_ring_struct *ring;
2645                 int j;
2646
2647                 if (!bnapi)
2648                         continue;
2649
2650                 cpr = &bnapi->cp_ring;
2651                 ring = &cpr->cp_ring_struct;
2652
2653                 bnxt_free_ring(bp, &ring->ring_mem);
2654
2655                 for (j = 0; j < 2; j++) {
2656                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2657
2658                         if (cpr2) {
2659                                 ring = &cpr2->cp_ring_struct;
2660                                 bnxt_free_ring(bp, &ring->ring_mem);
2661                                 kfree(cpr2);
2662                                 cpr->cp_ring_arr[j] = NULL;
2663                         }
2664                 }
2665         }
2666 }
2667
2668 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2669 {
2670         struct bnxt_ring_mem_info *rmem;
2671         struct bnxt_ring_struct *ring;
2672         struct bnxt_cp_ring_info *cpr;
2673         int rc;
2674
2675         cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2676         if (!cpr)
2677                 return NULL;
2678
2679         ring = &cpr->cp_ring_struct;
2680         rmem = &ring->ring_mem;
2681         rmem->nr_pages = bp->cp_nr_pages;
2682         rmem->page_size = HW_CMPD_RING_SIZE;
2683         rmem->pg_arr = (void **)cpr->cp_desc_ring;
2684         rmem->dma_arr = cpr->cp_desc_mapping;
2685         rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2686         rc = bnxt_alloc_ring(bp, rmem);
2687         if (rc) {
2688                 bnxt_free_ring(bp, rmem);
2689                 kfree(cpr);
2690                 cpr = NULL;
2691         }
2692         return cpr;
2693 }
2694
2695 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2696 {
2697         bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2698         int i, rc, ulp_base_vec, ulp_msix;
2699
2700         ulp_msix = bnxt_get_ulp_msix_num(bp);
2701         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2702         for (i = 0; i < bp->cp_nr_rings; i++) {
2703                 struct bnxt_napi *bnapi = bp->bnapi[i];
2704                 struct bnxt_cp_ring_info *cpr;
2705                 struct bnxt_ring_struct *ring;
2706
2707                 if (!bnapi)
2708                         continue;
2709
2710                 cpr = &bnapi->cp_ring;
2711                 cpr->bnapi = bnapi;
2712                 ring = &cpr->cp_ring_struct;
2713
2714                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2715                 if (rc)
2716                         return rc;
2717
2718                 if (ulp_msix && i >= ulp_base_vec)
2719                         ring->map_idx = i + ulp_msix;
2720                 else
2721                         ring->map_idx = i;
2722
2723                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2724                         continue;
2725
2726                 if (i < bp->rx_nr_rings) {
2727                         struct bnxt_cp_ring_info *cpr2 =
2728                                 bnxt_alloc_cp_sub_ring(bp);
2729
2730                         cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2731                         if (!cpr2)
2732                                 return -ENOMEM;
2733                         cpr2->bnapi = bnapi;
2734                 }
2735                 if ((sh && i < bp->tx_nr_rings) ||
2736                     (!sh && i >= bp->rx_nr_rings)) {
2737                         struct bnxt_cp_ring_info *cpr2 =
2738                                 bnxt_alloc_cp_sub_ring(bp);
2739
2740                         cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2741                         if (!cpr2)
2742                                 return -ENOMEM;
2743                         cpr2->bnapi = bnapi;
2744                 }
2745         }
2746         return 0;
2747 }
2748
2749 static void bnxt_init_ring_struct(struct bnxt *bp)
2750 {
2751         int i;
2752
2753         for (i = 0; i < bp->cp_nr_rings; i++) {
2754                 struct bnxt_napi *bnapi = bp->bnapi[i];
2755                 struct bnxt_ring_mem_info *rmem;
2756                 struct bnxt_cp_ring_info *cpr;
2757                 struct bnxt_rx_ring_info *rxr;
2758                 struct bnxt_tx_ring_info *txr;
2759                 struct bnxt_ring_struct *ring;
2760
2761                 if (!bnapi)
2762                         continue;
2763
2764                 cpr = &bnapi->cp_ring;
2765                 ring = &cpr->cp_ring_struct;
2766                 rmem = &ring->ring_mem;
2767                 rmem->nr_pages = bp->cp_nr_pages;
2768                 rmem->page_size = HW_CMPD_RING_SIZE;
2769                 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2770                 rmem->dma_arr = cpr->cp_desc_mapping;
2771                 rmem->vmem_size = 0;
2772
2773                 rxr = bnapi->rx_ring;
2774                 if (!rxr)
2775                         goto skip_rx;
2776
2777                 ring = &rxr->rx_ring_struct;
2778                 rmem = &ring->ring_mem;
2779                 rmem->nr_pages = bp->rx_nr_pages;
2780                 rmem->page_size = HW_RXBD_RING_SIZE;
2781                 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2782                 rmem->dma_arr = rxr->rx_desc_mapping;
2783                 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2784                 rmem->vmem = (void **)&rxr->rx_buf_ring;
2785
2786                 ring = &rxr->rx_agg_ring_struct;
2787                 rmem = &ring->ring_mem;
2788                 rmem->nr_pages = bp->rx_agg_nr_pages;
2789                 rmem->page_size = HW_RXBD_RING_SIZE;
2790                 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2791                 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2792                 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2793                 rmem->vmem = (void **)&rxr->rx_agg_ring;
2794
2795 skip_rx:
2796                 txr = bnapi->tx_ring;
2797                 if (!txr)
2798                         continue;
2799
2800                 ring = &txr->tx_ring_struct;
2801                 rmem = &ring->ring_mem;
2802                 rmem->nr_pages = bp->tx_nr_pages;
2803                 rmem->page_size = HW_RXBD_RING_SIZE;
2804                 rmem->pg_arr = (void **)txr->tx_desc_ring;
2805                 rmem->dma_arr = txr->tx_desc_mapping;
2806                 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2807                 rmem->vmem = (void **)&txr->tx_buf_ring;
2808         }
2809 }
2810
2811 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2812 {
2813         int i;
2814         u32 prod;
2815         struct rx_bd **rx_buf_ring;
2816
2817         rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2818         for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2819                 int j;
2820                 struct rx_bd *rxbd;
2821
2822                 rxbd = rx_buf_ring[i];
2823                 if (!rxbd)
2824                         continue;
2825
2826                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2827                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2828                         rxbd->rx_bd_opaque = prod;
2829                 }
2830         }
2831 }
2832
2833 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2834 {
2835         struct net_device *dev = bp->dev;
2836         struct bnxt_rx_ring_info *rxr;
2837         struct bnxt_ring_struct *ring;
2838         u32 prod, type;
2839         int i;
2840
2841         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2842                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2843
2844         if (NET_IP_ALIGN == 2)
2845                 type |= RX_BD_FLAGS_SOP;
2846
2847         rxr = &bp->rx_ring[ring_nr];
2848         ring = &rxr->rx_ring_struct;
2849         bnxt_init_rxbd_pages(ring, type);
2850
2851         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2852                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2853                 if (IS_ERR(rxr->xdp_prog)) {
2854                         int rc = PTR_ERR(rxr->xdp_prog);
2855
2856                         rxr->xdp_prog = NULL;
2857                         return rc;
2858                 }
2859         }
2860         prod = rxr->rx_prod;
2861         for (i = 0; i < bp->rx_ring_size; i++) {
2862                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2863                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2864                                     ring_nr, i, bp->rx_ring_size);
2865                         break;
2866                 }
2867                 prod = NEXT_RX(prod);
2868         }
2869         rxr->rx_prod = prod;
2870         ring->fw_ring_id = INVALID_HW_RING_ID;
2871
2872         ring = &rxr->rx_agg_ring_struct;
2873         ring->fw_ring_id = INVALID_HW_RING_ID;
2874
2875         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2876                 return 0;
2877
2878         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2879                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2880
2881         bnxt_init_rxbd_pages(ring, type);
2882
2883         prod = rxr->rx_agg_prod;
2884         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2885                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2886                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2887                                     ring_nr, i, bp->rx_ring_size);
2888                         break;
2889                 }
2890                 prod = NEXT_RX_AGG(prod);
2891         }
2892         rxr->rx_agg_prod = prod;
2893
2894         if (bp->flags & BNXT_FLAG_TPA) {
2895                 if (rxr->rx_tpa) {
2896                         u8 *data;
2897                         dma_addr_t mapping;
2898
2899                         for (i = 0; i < MAX_TPA; i++) {
2900                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2901                                                             GFP_KERNEL);
2902                                 if (!data)
2903                                         return -ENOMEM;
2904
2905                                 rxr->rx_tpa[i].data = data;
2906                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2907                                 rxr->rx_tpa[i].mapping = mapping;
2908                         }
2909                 } else {
2910                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2911                         return -ENOMEM;
2912                 }
2913         }
2914
2915         return 0;
2916 }
2917
2918 static void bnxt_init_cp_rings(struct bnxt *bp)
2919 {
2920         int i, j;
2921
2922         for (i = 0; i < bp->cp_nr_rings; i++) {
2923                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2924                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2925
2926                 ring->fw_ring_id = INVALID_HW_RING_ID;
2927                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2928                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2929                 for (j = 0; j < 2; j++) {
2930                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2931
2932                         if (!cpr2)
2933                                 continue;
2934
2935                         ring = &cpr2->cp_ring_struct;
2936                         ring->fw_ring_id = INVALID_HW_RING_ID;
2937                         cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2938                         cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2939                 }
2940         }
2941 }
2942
2943 static int bnxt_init_rx_rings(struct bnxt *bp)
2944 {
2945         int i, rc = 0;
2946
2947         if (BNXT_RX_PAGE_MODE(bp)) {
2948                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2949                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2950         } else {
2951                 bp->rx_offset = BNXT_RX_OFFSET;
2952                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2953         }
2954
2955         for (i = 0; i < bp->rx_nr_rings; i++) {
2956                 rc = bnxt_init_one_rx_ring(bp, i);
2957                 if (rc)
2958                         break;
2959         }
2960
2961         return rc;
2962 }
2963
2964 static int bnxt_init_tx_rings(struct bnxt *bp)
2965 {
2966         u16 i;
2967
2968         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2969                                    MAX_SKB_FRAGS + 1);
2970
2971         for (i = 0; i < bp->tx_nr_rings; i++) {
2972                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2973                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2974
2975                 ring->fw_ring_id = INVALID_HW_RING_ID;
2976         }
2977
2978         return 0;
2979 }
2980
2981 static void bnxt_free_ring_grps(struct bnxt *bp)
2982 {
2983         kfree(bp->grp_info);
2984         bp->grp_info = NULL;
2985 }
2986
2987 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2988 {
2989         int i;
2990
2991         if (irq_re_init) {
2992                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2993                                        sizeof(struct bnxt_ring_grp_info),
2994                                        GFP_KERNEL);
2995                 if (!bp->grp_info)
2996                         return -ENOMEM;
2997         }
2998         for (i = 0; i < bp->cp_nr_rings; i++) {
2999                 if (irq_re_init)
3000                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3001                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3002                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3003                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3004                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3005         }
3006         return 0;
3007 }
3008
3009 static void bnxt_free_vnics(struct bnxt *bp)
3010 {
3011         kfree(bp->vnic_info);
3012         bp->vnic_info = NULL;
3013         bp->nr_vnics = 0;
3014 }
3015
3016 static int bnxt_alloc_vnics(struct bnxt *bp)
3017 {
3018         int num_vnics = 1;
3019
3020 #ifdef CONFIG_RFS_ACCEL
3021         if (bp->flags & BNXT_FLAG_RFS)
3022                 num_vnics += bp->rx_nr_rings;
3023 #endif
3024
3025         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3026                 num_vnics++;
3027
3028         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3029                                 GFP_KERNEL);
3030         if (!bp->vnic_info)
3031                 return -ENOMEM;
3032
3033         bp->nr_vnics = num_vnics;
3034         return 0;
3035 }
3036
3037 static void bnxt_init_vnics(struct bnxt *bp)
3038 {
3039         int i;
3040
3041         for (i = 0; i < bp->nr_vnics; i++) {
3042                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3043                 int j;
3044
3045                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3046                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3047                         vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3048
3049                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3050
3051                 if (bp->vnic_info[i].rss_hash_key) {
3052                         if (i == 0)
3053                                 prandom_bytes(vnic->rss_hash_key,
3054                                               HW_HASH_KEY_SIZE);
3055                         else
3056                                 memcpy(vnic->rss_hash_key,
3057                                        bp->vnic_info[0].rss_hash_key,
3058                                        HW_HASH_KEY_SIZE);
3059                 }
3060         }
3061 }
3062
3063 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3064 {
3065         int pages;
3066
3067         pages = ring_size / desc_per_pg;
3068
3069         if (!pages)
3070                 return 1;
3071
3072         pages++;
3073
3074         while (pages & (pages - 1))
3075                 pages++;
3076
3077         return pages;
3078 }
3079
3080 void bnxt_set_tpa_flags(struct bnxt *bp)
3081 {
3082         bp->flags &= ~BNXT_FLAG_TPA;
3083         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3084                 return;
3085         if (bp->dev->features & NETIF_F_LRO)
3086                 bp->flags |= BNXT_FLAG_LRO;
3087         else if (bp->dev->features & NETIF_F_GRO_HW)
3088                 bp->flags |= BNXT_FLAG_GRO;
3089 }
3090
3091 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3092  * be set on entry.
3093  */
3094 void bnxt_set_ring_params(struct bnxt *bp)
3095 {
3096         u32 ring_size, rx_size, rx_space;
3097         u32 agg_factor = 0, agg_ring_size = 0;
3098
3099         /* 8 for CRC and VLAN */
3100         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3101
3102         rx_space = rx_size + NET_SKB_PAD +
3103                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3104
3105         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3106         ring_size = bp->rx_ring_size;
3107         bp->rx_agg_ring_size = 0;
3108         bp->rx_agg_nr_pages = 0;
3109
3110         if (bp->flags & BNXT_FLAG_TPA)
3111                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3112
3113         bp->flags &= ~BNXT_FLAG_JUMBO;
3114         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3115                 u32 jumbo_factor;
3116
3117                 bp->flags |= BNXT_FLAG_JUMBO;
3118                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3119                 if (jumbo_factor > agg_factor)
3120                         agg_factor = jumbo_factor;
3121         }
3122         agg_ring_size = ring_size * agg_factor;
3123
3124         if (agg_ring_size) {
3125                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3126                                                         RX_DESC_CNT);
3127                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3128                         u32 tmp = agg_ring_size;
3129
3130                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3131                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3132                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3133                                     tmp, agg_ring_size);
3134                 }
3135                 bp->rx_agg_ring_size = agg_ring_size;
3136                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3137                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3138                 rx_space = rx_size + NET_SKB_PAD +
3139                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3140         }
3141
3142         bp->rx_buf_use_size = rx_size;
3143         bp->rx_buf_size = rx_space;
3144
3145         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3146         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3147
3148         ring_size = bp->tx_ring_size;
3149         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3150         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3151
3152         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3153         bp->cp_ring_size = ring_size;
3154
3155         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3156         if (bp->cp_nr_pages > MAX_CP_PAGES) {
3157                 bp->cp_nr_pages = MAX_CP_PAGES;
3158                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3159                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3160                             ring_size, bp->cp_ring_size);
3161         }
3162         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3163         bp->cp_ring_mask = bp->cp_bit - 1;
3164 }
3165
3166 /* Changing allocation mode of RX rings.
3167  * TODO: Update when extending xdp_rxq_info to support allocation modes.
3168  */
3169 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3170 {
3171         if (page_mode) {
3172                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3173                         return -EOPNOTSUPP;
3174                 bp->dev->max_mtu =
3175                         min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3176                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3177                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3178                 bp->rx_dir = DMA_BIDIRECTIONAL;
3179                 bp->rx_skb_func = bnxt_rx_page_skb;
3180                 /* Disable LRO or GRO_HW */
3181                 netdev_update_features(bp->dev);
3182         } else {
3183                 bp->dev->max_mtu = bp->max_mtu;
3184                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3185                 bp->rx_dir = DMA_FROM_DEVICE;
3186                 bp->rx_skb_func = bnxt_rx_skb;
3187         }
3188         return 0;
3189 }
3190
3191 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3192 {
3193         int i;
3194         struct bnxt_vnic_info *vnic;
3195         struct pci_dev *pdev = bp->pdev;
3196
3197         if (!bp->vnic_info)
3198                 return;
3199
3200         for (i = 0; i < bp->nr_vnics; i++) {
3201                 vnic = &bp->vnic_info[i];
3202
3203                 kfree(vnic->fw_grp_ids);
3204                 vnic->fw_grp_ids = NULL;
3205
3206                 kfree(vnic->uc_list);
3207                 vnic->uc_list = NULL;
3208
3209                 if (vnic->mc_list) {
3210                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3211                                           vnic->mc_list, vnic->mc_list_mapping);
3212                         vnic->mc_list = NULL;
3213                 }
3214
3215                 if (vnic->rss_table) {
3216                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
3217                                           vnic->rss_table,
3218                                           vnic->rss_table_dma_addr);
3219                         vnic->rss_table = NULL;
3220                 }
3221
3222                 vnic->rss_hash_key = NULL;
3223                 vnic->flags = 0;
3224         }
3225 }
3226
3227 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3228 {
3229         int i, rc = 0, size;
3230         struct bnxt_vnic_info *vnic;
3231         struct pci_dev *pdev = bp->pdev;
3232         int max_rings;
3233
3234         for (i = 0; i < bp->nr_vnics; i++) {
3235                 vnic = &bp->vnic_info[i];
3236
3237                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3238                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3239
3240                         if (mem_size > 0) {
3241                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3242                                 if (!vnic->uc_list) {
3243                                         rc = -ENOMEM;
3244                                         goto out;
3245                                 }
3246                         }
3247                 }
3248
3249                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3250                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3251                         vnic->mc_list =
3252                                 dma_alloc_coherent(&pdev->dev,
3253                                                    vnic->mc_list_size,
3254                                                    &vnic->mc_list_mapping,
3255                                                    GFP_KERNEL);
3256                         if (!vnic->mc_list) {
3257                                 rc = -ENOMEM;
3258                                 goto out;
3259                         }
3260                 }
3261
3262                 if (bp->flags & BNXT_FLAG_CHIP_P5)
3263                         goto vnic_skip_grps;
3264
3265                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3266                         max_rings = bp->rx_nr_rings;
3267                 else
3268                         max_rings = 1;
3269
3270                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3271                 if (!vnic->fw_grp_ids) {
3272                         rc = -ENOMEM;
3273                         goto out;
3274                 }
3275 vnic_skip_grps:
3276                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3277                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3278                         continue;
3279
3280                 /* Allocate rss table and hash key */
3281                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3282                                                      &vnic->rss_table_dma_addr,
3283                                                      GFP_KERNEL);
3284                 if (!vnic->rss_table) {
3285                         rc = -ENOMEM;
3286                         goto out;
3287                 }
3288
3289                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3290
3291                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3292                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3293         }
3294         return 0;
3295
3296 out:
3297         return rc;
3298 }
3299
3300 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3301 {
3302         struct pci_dev *pdev = bp->pdev;
3303
3304         if (bp->hwrm_cmd_resp_addr) {
3305                 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3306                                   bp->hwrm_cmd_resp_dma_addr);
3307                 bp->hwrm_cmd_resp_addr = NULL;
3308         }
3309
3310         if (bp->hwrm_cmd_kong_resp_addr) {
3311                 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3312                                   bp->hwrm_cmd_kong_resp_addr,
3313                                   bp->hwrm_cmd_kong_resp_dma_addr);
3314                 bp->hwrm_cmd_kong_resp_addr = NULL;
3315         }
3316 }
3317
3318 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3319 {
3320         struct pci_dev *pdev = bp->pdev;
3321
3322         bp->hwrm_cmd_kong_resp_addr =
3323                 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3324                                    &bp->hwrm_cmd_kong_resp_dma_addr,
3325                                    GFP_KERNEL);
3326         if (!bp->hwrm_cmd_kong_resp_addr)
3327                 return -ENOMEM;
3328
3329         return 0;
3330 }
3331
3332 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3333 {
3334         struct pci_dev *pdev = bp->pdev;
3335
3336         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3337                                                    &bp->hwrm_cmd_resp_dma_addr,
3338                                                    GFP_KERNEL);
3339         if (!bp->hwrm_cmd_resp_addr)
3340                 return -ENOMEM;
3341
3342         return 0;
3343 }
3344
3345 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3346 {
3347         if (bp->hwrm_short_cmd_req_addr) {
3348                 struct pci_dev *pdev = bp->pdev;
3349
3350                 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3351                                   bp->hwrm_short_cmd_req_addr,
3352                                   bp->hwrm_short_cmd_req_dma_addr);
3353                 bp->hwrm_short_cmd_req_addr = NULL;
3354         }
3355 }
3356
3357 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3358 {
3359         struct pci_dev *pdev = bp->pdev;
3360
3361         bp->hwrm_short_cmd_req_addr =
3362                 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3363                                    &bp->hwrm_short_cmd_req_dma_addr,
3364                                    GFP_KERNEL);
3365         if (!bp->hwrm_short_cmd_req_addr)
3366                 return -ENOMEM;
3367
3368         return 0;
3369 }
3370
3371 static void bnxt_free_port_stats(struct bnxt *bp)
3372 {
3373         struct pci_dev *pdev = bp->pdev;
3374
3375         bp->flags &= ~BNXT_FLAG_PORT_STATS;
3376         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3377
3378         if (bp->hw_rx_port_stats) {
3379                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3380                                   bp->hw_rx_port_stats,
3381                                   bp->hw_rx_port_stats_map);
3382                 bp->hw_rx_port_stats = NULL;
3383         }
3384
3385         if (bp->hw_tx_port_stats_ext) {
3386                 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3387                                   bp->hw_tx_port_stats_ext,
3388                                   bp->hw_tx_port_stats_ext_map);
3389                 bp->hw_tx_port_stats_ext = NULL;
3390         }
3391
3392         if (bp->hw_rx_port_stats_ext) {
3393                 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3394                                   bp->hw_rx_port_stats_ext,
3395                                   bp->hw_rx_port_stats_ext_map);
3396                 bp->hw_rx_port_stats_ext = NULL;
3397         }
3398 }
3399
3400 static void bnxt_free_ring_stats(struct bnxt *bp)
3401 {
3402         struct pci_dev *pdev = bp->pdev;
3403         int size, i;
3404
3405         if (!bp->bnapi)
3406                 return;
3407
3408         size = sizeof(struct ctx_hw_stats);
3409
3410         for (i = 0; i < bp->cp_nr_rings; i++) {
3411                 struct bnxt_napi *bnapi = bp->bnapi[i];
3412                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3413
3414                 if (cpr->hw_stats) {
3415                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3416                                           cpr->hw_stats_map);
3417                         cpr->hw_stats = NULL;
3418                 }
3419         }
3420 }
3421
3422 static int bnxt_alloc_stats(struct bnxt *bp)
3423 {
3424         u32 size, i;
3425         struct pci_dev *pdev = bp->pdev;
3426
3427         size = sizeof(struct ctx_hw_stats);
3428
3429         for (i = 0; i < bp->cp_nr_rings; i++) {
3430                 struct bnxt_napi *bnapi = bp->bnapi[i];
3431                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3432
3433                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3434                                                    &cpr->hw_stats_map,
3435                                                    GFP_KERNEL);
3436                 if (!cpr->hw_stats)
3437                         return -ENOMEM;
3438
3439                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3440         }
3441
3442         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3443                 if (bp->hw_rx_port_stats)
3444                         goto alloc_ext_stats;
3445
3446                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3447                                          sizeof(struct tx_port_stats) + 1024;
3448
3449                 bp->hw_rx_port_stats =
3450                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3451                                            &bp->hw_rx_port_stats_map,
3452                                            GFP_KERNEL);
3453                 if (!bp->hw_rx_port_stats)
3454                         return -ENOMEM;
3455
3456                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3457                                        512;
3458                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3459                                            sizeof(struct rx_port_stats) + 512;
3460                 bp->flags |= BNXT_FLAG_PORT_STATS;
3461
3462 alloc_ext_stats:
3463                 /* Display extended statistics only if FW supports it */
3464                 if (bp->hwrm_spec_code < 0x10804 ||
3465                     bp->hwrm_spec_code == 0x10900)
3466                         return 0;
3467
3468                 if (bp->hw_rx_port_stats_ext)
3469                         goto alloc_tx_ext_stats;
3470
3471                 bp->hw_rx_port_stats_ext =
3472                         dma_alloc_coherent(&pdev->dev,
3473                                            sizeof(struct rx_port_stats_ext),
3474                                            &bp->hw_rx_port_stats_ext_map,
3475                                            GFP_KERNEL);
3476                 if (!bp->hw_rx_port_stats_ext)
3477                         return 0;
3478
3479 alloc_tx_ext_stats:
3480                 if (bp->hw_tx_port_stats_ext)
3481                         return 0;
3482
3483                 if (bp->hwrm_spec_code >= 0x10902) {
3484                         bp->hw_tx_port_stats_ext =
3485                                 dma_alloc_coherent(&pdev->dev,
3486                                                    sizeof(struct tx_port_stats_ext),
3487                                                    &bp->hw_tx_port_stats_ext_map,
3488                                                    GFP_KERNEL);
3489                 }
3490                 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3491         }
3492         return 0;
3493 }
3494
3495 static void bnxt_clear_ring_indices(struct bnxt *bp)
3496 {
3497         int i;
3498
3499         if (!bp->bnapi)
3500                 return;
3501
3502         for (i = 0; i < bp->cp_nr_rings; i++) {
3503                 struct bnxt_napi *bnapi = bp->bnapi[i];
3504                 struct bnxt_cp_ring_info *cpr;
3505                 struct bnxt_rx_ring_info *rxr;
3506                 struct bnxt_tx_ring_info *txr;
3507
3508                 if (!bnapi)
3509                         continue;
3510
3511                 cpr = &bnapi->cp_ring;
3512                 cpr->cp_raw_cons = 0;
3513
3514                 txr = bnapi->tx_ring;
3515                 if (txr) {
3516                         txr->tx_prod = 0;
3517                         txr->tx_cons = 0;
3518                 }
3519
3520                 rxr = bnapi->rx_ring;
3521                 if (rxr) {
3522                         rxr->rx_prod = 0;
3523                         rxr->rx_agg_prod = 0;
3524                         rxr->rx_sw_agg_prod = 0;
3525                         rxr->rx_next_cons = 0;
3526                 }
3527         }
3528 }
3529
3530 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3531 {
3532 #ifdef CONFIG_RFS_ACCEL
3533         int i;
3534
3535         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3536          * safe to delete the hash table.
3537          */
3538         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3539                 struct hlist_head *head;
3540                 struct hlist_node *tmp;
3541                 struct bnxt_ntuple_filter *fltr;
3542
3543                 head = &bp->ntp_fltr_hash_tbl[i];
3544                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3545                         hlist_del(&fltr->hash);
3546                         kfree(fltr);
3547                 }
3548         }
3549         if (irq_reinit) {
3550                 kfree(bp->ntp_fltr_bmap);
3551                 bp->ntp_fltr_bmap = NULL;
3552         }
3553         bp->ntp_fltr_count = 0;
3554 #endif
3555 }
3556
3557 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3558 {
3559 #ifdef CONFIG_RFS_ACCEL
3560         int i, rc = 0;
3561
3562         if (!(bp->flags & BNXT_FLAG_RFS))
3563                 return 0;
3564
3565         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3566                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3567
3568         bp->ntp_fltr_count = 0;
3569         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3570                                     sizeof(long),
3571                                     GFP_KERNEL);
3572
3573         if (!bp->ntp_fltr_bmap)
3574                 rc = -ENOMEM;
3575
3576         return rc;
3577 #else
3578         return 0;
3579 #endif
3580 }
3581
3582 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3583 {
3584         bnxt_free_vnic_attributes(bp);
3585         bnxt_free_tx_rings(bp);
3586         bnxt_free_rx_rings(bp);
3587         bnxt_free_cp_rings(bp);
3588         bnxt_free_ntp_fltrs(bp, irq_re_init);
3589         if (irq_re_init) {
3590                 bnxt_free_ring_stats(bp);
3591                 bnxt_free_ring_grps(bp);
3592                 bnxt_free_vnics(bp);
3593                 kfree(bp->tx_ring_map);
3594                 bp->tx_ring_map = NULL;
3595                 kfree(bp->tx_ring);
3596                 bp->tx_ring = NULL;
3597                 kfree(bp->rx_ring);
3598                 bp->rx_ring = NULL;
3599                 kfree(bp->bnapi);
3600                 bp->bnapi = NULL;
3601         } else {
3602                 bnxt_clear_ring_indices(bp);
3603         }
3604 }
3605
3606 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3607 {
3608         int i, j, rc, size, arr_size;
3609         void *bnapi;
3610
3611         if (irq_re_init) {
3612                 /* Allocate bnapi mem pointer array and mem block for
3613                  * all queues
3614                  */
3615                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3616                                 bp->cp_nr_rings);
3617                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3618                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3619                 if (!bnapi)
3620                         return -ENOMEM;
3621
3622                 bp->bnapi = bnapi;
3623                 bnapi += arr_size;
3624                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3625                         bp->bnapi[i] = bnapi;
3626                         bp->bnapi[i]->index = i;
3627                         bp->bnapi[i]->bp = bp;
3628                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3629                                 struct bnxt_cp_ring_info *cpr =
3630                                         &bp->bnapi[i]->cp_ring;
3631
3632                                 cpr->cp_ring_struct.ring_mem.flags =
3633                                         BNXT_RMEM_RING_PTE_FLAG;
3634                         }
3635                 }
3636
3637                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3638                                       sizeof(struct bnxt_rx_ring_info),
3639                                       GFP_KERNEL);
3640                 if (!bp->rx_ring)
3641                         return -ENOMEM;
3642
3643                 for (i = 0; i < bp->rx_nr_rings; i++) {
3644                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3645
3646                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3647                                 rxr->rx_ring_struct.ring_mem.flags =
3648                                         BNXT_RMEM_RING_PTE_FLAG;
3649                                 rxr->rx_agg_ring_struct.ring_mem.flags =
3650                                         BNXT_RMEM_RING_PTE_FLAG;
3651                         }
3652                         rxr->bnapi = bp->bnapi[i];
3653                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3654                 }
3655
3656                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3657                                       sizeof(struct bnxt_tx_ring_info),
3658                                       GFP_KERNEL);
3659                 if (!bp->tx_ring)
3660                         return -ENOMEM;
3661
3662                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3663                                           GFP_KERNEL);
3664
3665                 if (!bp->tx_ring_map)
3666                         return -ENOMEM;
3667
3668                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3669                         j = 0;
3670                 else
3671                         j = bp->rx_nr_rings;
3672
3673                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3674                         struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3675
3676                         if (bp->flags & BNXT_FLAG_CHIP_P5)
3677                                 txr->tx_ring_struct.ring_mem.flags =
3678                                         BNXT_RMEM_RING_PTE_FLAG;
3679                         txr->bnapi = bp->bnapi[j];
3680                         bp->bnapi[j]->tx_ring = txr;
3681                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3682                         if (i >= bp->tx_nr_rings_xdp) {
3683                                 txr->txq_index = i - bp->tx_nr_rings_xdp;
3684                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3685                         } else {
3686                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3687                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3688                         }
3689                 }
3690
3691                 rc = bnxt_alloc_stats(bp);
3692                 if (rc)
3693                         goto alloc_mem_err;
3694
3695                 rc = bnxt_alloc_ntp_fltrs(bp);
3696                 if (rc)
3697                         goto alloc_mem_err;
3698
3699                 rc = bnxt_alloc_vnics(bp);
3700                 if (rc)
3701                         goto alloc_mem_err;
3702         }
3703
3704         bnxt_init_ring_struct(bp);
3705
3706         rc = bnxt_alloc_rx_rings(bp);
3707         if (rc)
3708                 goto alloc_mem_err;
3709
3710         rc = bnxt_alloc_tx_rings(bp);
3711         if (rc)
3712                 goto alloc_mem_err;
3713
3714         rc = bnxt_alloc_cp_rings(bp);
3715         if (rc)
3716                 goto alloc_mem_err;
3717
3718         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3719                                   BNXT_VNIC_UCAST_FLAG;
3720         rc = bnxt_alloc_vnic_attributes(bp);
3721         if (rc)
3722                 goto alloc_mem_err;
3723         return 0;
3724
3725 alloc_mem_err:
3726         bnxt_free_mem(bp, true);
3727         return rc;
3728 }
3729
3730 static void bnxt_disable_int(struct bnxt *bp)
3731 {
3732         int i;
3733
3734         if (!bp->bnapi)
3735                 return;
3736
3737         for (i = 0; i < bp->cp_nr_rings; i++) {
3738                 struct bnxt_napi *bnapi = bp->bnapi[i];
3739                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3740                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3741
3742                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3743                         bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3744         }
3745 }
3746
3747 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3748 {
3749         struct bnxt_napi *bnapi = bp->bnapi[n];
3750         struct bnxt_cp_ring_info *cpr;
3751
3752         cpr = &bnapi->cp_ring;
3753         return cpr->cp_ring_struct.map_idx;
3754 }
3755
3756 static void bnxt_disable_int_sync(struct bnxt *bp)
3757 {
3758         int i;
3759
3760         atomic_inc(&bp->intr_sem);
3761
3762         bnxt_disable_int(bp);
3763         for (i = 0; i < bp->cp_nr_rings; i++) {
3764                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3765
3766                 synchronize_irq(bp->irq_tbl[map_idx].vector);
3767         }
3768 }
3769
3770 static void bnxt_enable_int(struct bnxt *bp)
3771 {
3772         int i;
3773
3774         atomic_set(&bp->intr_sem, 0);
3775         for (i = 0; i < bp->cp_nr_rings; i++) {
3776                 struct bnxt_napi *bnapi = bp->bnapi[i];
3777                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3778
3779                 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3780         }
3781 }
3782
3783 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3784                             u16 cmpl_ring, u16 target_id)
3785 {
3786         struct input *req = request;
3787
3788         req->req_type = cpu_to_le16(req_type);
3789         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3790         req->target_id = cpu_to_le16(target_id);
3791         if (bnxt_kong_hwrm_message(bp, req))
3792                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3793         else
3794                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3795 }
3796
3797 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3798                                  int timeout, bool silent)
3799 {
3800         int i, intr_process, rc, tmo_count;
3801         struct input *req = msg;
3802         u32 *data = msg;
3803         __le32 *resp_len;
3804         u8 *valid;
3805         u16 cp_ring_id, len = 0;
3806         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3807         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3808         struct hwrm_short_input short_input = {0};
3809         u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3810         u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3811         u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3812         u16 dst = BNXT_HWRM_CHNL_CHIMP;
3813
3814         if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3815                 if (msg_len > bp->hwrm_max_ext_req_len ||
3816                     !bp->hwrm_short_cmd_req_addr)
3817                         return -EINVAL;
3818         }
3819
3820         if (bnxt_hwrm_kong_chnl(bp, req)) {
3821                 dst = BNXT_HWRM_CHNL_KONG;
3822                 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3823                 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3824                 resp = bp->hwrm_cmd_kong_resp_addr;
3825                 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3826         }
3827
3828         memset(resp, 0, PAGE_SIZE);
3829         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3830         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3831
3832         req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3833         /* currently supports only one outstanding message */
3834         if (intr_process)
3835                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3836
3837         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3838             msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3839                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3840                 u16 max_msg_len;
3841
3842                 /* Set boundary for maximum extended request length for short
3843                  * cmd format. If passed up from device use the max supported
3844                  * internal req length.
3845                  */
3846                 max_msg_len = bp->hwrm_max_ext_req_len;
3847
3848                 memcpy(short_cmd_req, req, msg_len);
3849                 if (msg_len < max_msg_len)
3850                         memset(short_cmd_req + msg_len, 0,
3851                                max_msg_len - msg_len);
3852
3853                 short_input.req_type = req->req_type;
3854                 short_input.signature =
3855                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3856                 short_input.size = cpu_to_le16(msg_len);
3857                 short_input.req_addr =
3858                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3859
3860                 data = (u32 *)&short_input;
3861                 msg_len = sizeof(short_input);
3862
3863                 /* Sync memory write before updating doorbell */
3864                 wmb();
3865
3866                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3867         }
3868
3869         /* Write request msg to hwrm channel */
3870         __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3871
3872         for (i = msg_len; i < max_req_len; i += 4)
3873                 writel(0, bp->bar0 + bar_offset + i);
3874
3875         /* Ring channel doorbell */
3876         writel(1, bp->bar0 + doorbell_offset);
3877
3878         if (!timeout)
3879                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3880         /* convert timeout to usec */
3881         timeout *= 1000;
3882
3883         i = 0;
3884         /* Short timeout for the first few iterations:
3885          * number of loops = number of loops for short timeout +
3886          * number of loops for standard timeout.
3887          */
3888         tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3889         timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3890         tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3891         resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3892
3893         if (intr_process) {
3894                 u16 seq_id = bp->hwrm_intr_seq_id;
3895
3896                 /* Wait until hwrm response cmpl interrupt is processed */
3897                 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3898                        i++ < tmo_count) {
3899                         /* on first few passes, just barely sleep */
3900                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3901                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3902                                              HWRM_SHORT_MAX_TIMEOUT);
3903                         else
3904                                 usleep_range(HWRM_MIN_TIMEOUT,
3905                                              HWRM_MAX_TIMEOUT);
3906                 }
3907
3908                 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3909                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3910                                    le16_to_cpu(req->req_type));
3911                         return -1;
3912                 }
3913                 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3914                       HWRM_RESP_LEN_SFT;
3915                 valid = resp_addr + len - 1;
3916         } else {
3917                 int j;
3918
3919                 /* Check if response len is updated */
3920                 for (i = 0; i < tmo_count; i++) {
3921                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3922                               HWRM_RESP_LEN_SFT;
3923                         if (len)
3924                                 break;
3925                         /* on first few passes, just barely sleep */
3926                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3927                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3928                                              HWRM_SHORT_MAX_TIMEOUT);
3929                         else
3930                                 usleep_range(HWRM_MIN_TIMEOUT,
3931                                              HWRM_MAX_TIMEOUT);
3932                 }
3933
3934                 if (i >= tmo_count) {
3935                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3936                                    HWRM_TOTAL_TIMEOUT(i),
3937                                    le16_to_cpu(req->req_type),
3938                                    le16_to_cpu(req->seq_id), len);
3939                         return -1;
3940                 }
3941
3942                 /* Last byte of resp contains valid bit */
3943                 valid = resp_addr + len - 1;
3944                 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3945                         /* make sure we read from updated DMA memory */
3946                         dma_rmb();
3947                         if (*valid)
3948                                 break;
3949                         usleep_range(1, 5);
3950                 }
3951
3952                 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3953                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3954                                    HWRM_TOTAL_TIMEOUT(i),
3955                                    le16_to_cpu(req->req_type),
3956                                    le16_to_cpu(req->seq_id), len, *valid);
3957                         return -1;
3958                 }
3959         }
3960
3961         /* Zero valid bit for compatibility.  Valid bit in an older spec
3962          * may become a new field in a newer spec.  We must make sure that
3963          * a new field not implemented by old spec will read zero.
3964          */
3965         *valid = 0;
3966         rc = le16_to_cpu(resp->error_code);
3967         if (rc && !silent)
3968                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3969                            le16_to_cpu(resp->req_type),
3970                            le16_to_cpu(resp->seq_id), rc);
3971         return rc;
3972 }
3973
3974 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3975 {
3976         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3977 }
3978
3979 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3980                               int timeout)
3981 {
3982         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3983 }
3984
3985 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3986 {
3987         int rc;
3988
3989         mutex_lock(&bp->hwrm_cmd_lock);
3990         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3991         mutex_unlock(&bp->hwrm_cmd_lock);
3992         return rc;
3993 }
3994
3995 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3996                              int timeout)
3997 {
3998         int rc;
3999
4000         mutex_lock(&bp->hwrm_cmd_lock);
4001         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4002         mutex_unlock(&bp->hwrm_cmd_lock);
4003         return rc;
4004 }
4005
4006 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
4007                                      int bmap_size)
4008 {
4009         struct hwrm_func_drv_rgtr_input req = {0};
4010         DECLARE_BITMAP(async_events_bmap, 256);
4011         u32 *events = (u32 *)async_events_bmap;
4012         int i;
4013
4014         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4015
4016         req.enables =
4017                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4018
4019         memset(async_events_bmap, 0, sizeof(async_events_bmap));
4020         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4021                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4022
4023         if (bmap && bmap_size) {
4024                 for (i = 0; i < bmap_size; i++) {
4025                         if (test_bit(i, bmap))
4026                                 __set_bit(i, async_events_bmap);
4027                 }
4028         }
4029
4030         for (i = 0; i < 8; i++)
4031                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4032
4033         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4034 }
4035
4036 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4037 {
4038         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4039         struct hwrm_func_drv_rgtr_input req = {0};
4040         int rc;
4041
4042         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4043
4044         req.enables =
4045                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4046                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
4047
4048         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4049         req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4050         req.ver_maj_8b = DRV_VER_MAJ;
4051         req.ver_min_8b = DRV_VER_MIN;
4052         req.ver_upd_8b = DRV_VER_UPD;
4053         req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4054         req.ver_min = cpu_to_le16(DRV_VER_MIN);
4055         req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4056
4057         if (BNXT_PF(bp)) {
4058                 u32 data[8];
4059                 int i;
4060
4061                 memset(data, 0, sizeof(data));
4062                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4063                         u16 cmd = bnxt_vf_req_snif[i];
4064                         unsigned int bit, idx;
4065
4066                         idx = cmd / 32;
4067                         bit = cmd % 32;
4068                         data[idx] |= 1 << bit;
4069                 }
4070
4071                 for (i = 0; i < 8; i++)
4072                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4073
4074                 req.enables |=
4075                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4076         }
4077
4078         if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4079                 req.flags |= cpu_to_le32(
4080                         FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4081
4082         mutex_lock(&bp->hwrm_cmd_lock);
4083         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4084         if (rc)
4085                 rc = -EIO;
4086         else if (resp->flags &
4087                  cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4088                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4089         mutex_unlock(&bp->hwrm_cmd_lock);
4090         return rc;
4091 }
4092
4093 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4094 {
4095         struct hwrm_func_drv_unrgtr_input req = {0};
4096
4097         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4098         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4099 }
4100
4101 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4102 {
4103         u32 rc = 0;
4104         struct hwrm_tunnel_dst_port_free_input req = {0};
4105
4106         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4107         req.tunnel_type = tunnel_type;
4108
4109         switch (tunnel_type) {
4110         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4111                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4112                 break;
4113         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4114                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4115                 break;
4116         default:
4117                 break;
4118         }
4119
4120         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4121         if (rc)
4122                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4123                            rc);
4124         return rc;
4125 }
4126
4127 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4128                                            u8 tunnel_type)
4129 {
4130         u32 rc = 0;
4131         struct hwrm_tunnel_dst_port_alloc_input req = {0};
4132         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4133
4134         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4135
4136         req.tunnel_type = tunnel_type;
4137         req.tunnel_dst_port_val = port;
4138
4139         mutex_lock(&bp->hwrm_cmd_lock);
4140         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4141         if (rc) {
4142                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4143                            rc);
4144                 goto err_out;
4145         }
4146
4147         switch (tunnel_type) {
4148         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4149                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4150                 break;
4151         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4152                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4153                 break;
4154         default:
4155                 break;
4156         }
4157
4158 err_out:
4159         mutex_unlock(&bp->hwrm_cmd_lock);
4160         return rc;
4161 }
4162
4163 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4164 {
4165         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4166         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4167
4168         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4169         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4170
4171         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4172         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4173         req.mask = cpu_to_le32(vnic->rx_mask);
4174         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4175 }
4176
4177 #ifdef CONFIG_RFS_ACCEL
4178 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4179                                             struct bnxt_ntuple_filter *fltr)
4180 {
4181         struct hwrm_cfa_ntuple_filter_free_input req = {0};
4182
4183         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4184         req.ntuple_filter_id = fltr->filter_id;
4185         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4186 }
4187
4188 #define BNXT_NTP_FLTR_FLAGS                                     \
4189         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
4190          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
4191          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
4192          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
4193          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
4194          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
4195          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
4196          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
4197          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
4198          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
4199          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
4200          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
4201          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
4202          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4203
4204 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
4205                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4206
4207 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4208                                              struct bnxt_ntuple_filter *fltr)
4209 {
4210         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
4211         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4212         struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4213         struct flow_keys *keys = &fltr->fkeys;
4214         int rc = 0;
4215
4216         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4217         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4218
4219         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4220
4221         req.ethertype = htons(ETH_P_IP);
4222         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4223         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4224         req.ip_protocol = keys->basic.ip_proto;
4225
4226         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4227                 int i;
4228
4229                 req.ethertype = htons(ETH_P_IPV6);
4230                 req.ip_addr_type =
4231                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4232                 *(struct in6_addr *)&req.src_ipaddr[0] =
4233                         keys->addrs.v6addrs.src;
4234                 *(struct in6_addr *)&req.dst_ipaddr[0] =
4235                         keys->addrs.v6addrs.dst;
4236                 for (i = 0; i < 4; i++) {
4237                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4238                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4239                 }
4240         } else {
4241                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4242                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4243                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4244                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4245         }
4246         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4247                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4248                 req.tunnel_type =
4249                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4250         }
4251
4252         req.src_port = keys->ports.src;
4253         req.src_port_mask = cpu_to_be16(0xffff);
4254         req.dst_port = keys->ports.dst;
4255         req.dst_port_mask = cpu_to_be16(0xffff);
4256
4257         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4258         mutex_lock(&bp->hwrm_cmd_lock);
4259         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4260         if (!rc) {
4261                 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4262                 fltr->filter_id = resp->ntuple_filter_id;
4263         }
4264         mutex_unlock(&bp->hwrm_cmd_lock);
4265         return rc;
4266 }
4267 #endif
4268
4269 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4270                                      u8 *mac_addr)
4271 {
4272         u32 rc = 0;
4273         struct hwrm_cfa_l2_filter_alloc_input req = {0};
4274         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4275
4276         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4277         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4278         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4279                 req.flags |=
4280                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4281         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4282         req.enables =
4283                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4284                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4285                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4286         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4287         req.l2_addr_mask[0] = 0xff;
4288         req.l2_addr_mask[1] = 0xff;
4289         req.l2_addr_mask[2] = 0xff;
4290         req.l2_addr_mask[3] = 0xff;
4291         req.l2_addr_mask[4] = 0xff;
4292         req.l2_addr_mask[5] = 0xff;
4293
4294         mutex_lock(&bp->hwrm_cmd_lock);
4295         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4296         if (!rc)
4297                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4298                                                         resp->l2_filter_id;
4299         mutex_unlock(&bp->hwrm_cmd_lock);
4300         return rc;
4301 }
4302
4303 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4304 {
4305         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4306         int rc = 0;
4307
4308         /* Any associated ntuple filters will also be cleared by firmware. */
4309         mutex_lock(&bp->hwrm_cmd_lock);
4310         for (i = 0; i < num_of_vnics; i++) {
4311                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4312
4313                 for (j = 0; j < vnic->uc_filter_count; j++) {
4314                         struct hwrm_cfa_l2_filter_free_input req = {0};
4315
4316                         bnxt_hwrm_cmd_hdr_init(bp, &req,
4317                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
4318
4319                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
4320
4321                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4322                                                 HWRM_CMD_TIMEOUT);
4323                 }
4324                 vnic->uc_filter_count = 0;
4325         }
4326         mutex_unlock(&bp->hwrm_cmd_lock);
4327
4328         return rc;
4329 }
4330
4331 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4332 {
4333         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4334         struct hwrm_vnic_tpa_cfg_input req = {0};
4335
4336         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4337                 return 0;
4338
4339         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4340
4341         if (tpa_flags) {
4342                 u16 mss = bp->dev->mtu - 40;
4343                 u32 nsegs, n, segs = 0, flags;
4344
4345                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4346                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4347                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4348                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4349                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4350                 if (tpa_flags & BNXT_FLAG_GRO)
4351                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4352
4353                 req.flags = cpu_to_le32(flags);
4354
4355                 req.enables =
4356                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4357                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4358                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4359
4360                 /* Number of segs are log2 units, and first packet is not
4361                  * included as part of this units.
4362                  */
4363                 if (mss <= BNXT_RX_PAGE_SIZE) {
4364                         n = BNXT_RX_PAGE_SIZE / mss;
4365                         nsegs = (MAX_SKB_FRAGS - 1) * n;
4366                 } else {
4367                         n = mss / BNXT_RX_PAGE_SIZE;
4368                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
4369                                 n++;
4370                         nsegs = (MAX_SKB_FRAGS - n) / n;
4371                 }
4372
4373                 segs = ilog2(nsegs);
4374                 req.max_agg_segs = cpu_to_le16(segs);
4375                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4376
4377                 req.min_agg_len = cpu_to_le32(512);
4378         }
4379         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4380
4381         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4382 }
4383
4384 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4385 {
4386         struct bnxt_ring_grp_info *grp_info;
4387
4388         grp_info = &bp->grp_info[ring->grp_idx];
4389         return grp_info->cp_fw_ring_id;
4390 }
4391
4392 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4393 {
4394         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4395                 struct bnxt_napi *bnapi = rxr->bnapi;
4396                 struct bnxt_cp_ring_info *cpr;
4397
4398                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4399                 return cpr->cp_ring_struct.fw_ring_id;
4400         } else {
4401                 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4402         }
4403 }
4404
4405 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4406 {
4407         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4408                 struct bnxt_napi *bnapi = txr->bnapi;
4409                 struct bnxt_cp_ring_info *cpr;
4410
4411                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4412                 return cpr->cp_ring_struct.fw_ring_id;
4413         } else {
4414                 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4415         }
4416 }
4417
4418 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4419 {
4420         u32 i, j, max_rings;
4421         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4422         struct hwrm_vnic_rss_cfg_input req = {0};
4423
4424         if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4425             vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4426                 return 0;
4427
4428         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4429         if (set_rss) {
4430                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4431                 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4432                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4433                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4434                                 max_rings = bp->rx_nr_rings - 1;
4435                         else
4436                                 max_rings = bp->rx_nr_rings;
4437                 } else {
4438                         max_rings = 1;
4439                 }
4440
4441                 /* Fill the RSS indirection table with ring group ids */
4442                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4443                         if (j == max_rings)
4444                                 j = 0;
4445                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4446                 }
4447
4448                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4449                 req.hash_key_tbl_addr =
4450                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
4451         }
4452         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4453         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4454 }
4455
4456 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4457 {
4458         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4459         u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4460         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4461         struct hwrm_vnic_rss_cfg_input req = {0};
4462
4463         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4464         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4465         if (!set_rss) {
4466                 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4467                 return 0;
4468         }
4469         req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4470         req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4471         req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4472         req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4473         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4474         for (i = 0, k = 0; i < nr_ctxs; i++) {
4475                 __le16 *ring_tbl = vnic->rss_table;
4476                 int rc;
4477
4478                 req.ring_table_pair_index = i;
4479                 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4480                 for (j = 0; j < 64; j++) {
4481                         u16 ring_id;
4482
4483                         ring_id = rxr->rx_ring_struct.fw_ring_id;
4484                         *ring_tbl++ = cpu_to_le16(ring_id);
4485                         ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4486                         *ring_tbl++ = cpu_to_le16(ring_id);
4487                         rxr++;
4488                         k++;
4489                         if (k == max_rings) {
4490                                 k = 0;
4491                                 rxr = &bp->rx_ring[0];
4492                         }
4493                 }
4494                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4495                 if (rc)
4496                         return -EIO;
4497         }
4498         return 0;
4499 }
4500
4501 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4502 {
4503         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4504         struct hwrm_vnic_plcmodes_cfg_input req = {0};
4505
4506         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4507         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4508                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4509                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4510         req.enables =
4511                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4512                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4513         /* thresholds not implemented in firmware yet */
4514         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4515         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4516         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4517         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4518 }
4519
4520 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4521                                         u16 ctx_idx)
4522 {
4523         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4524
4525         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4526         req.rss_cos_lb_ctx_id =
4527                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4528
4529         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4530         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4531 }
4532
4533 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4534 {
4535         int i, j;
4536
4537         for (i = 0; i < bp->nr_vnics; i++) {
4538                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4539
4540                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4541                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4542                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4543                 }
4544         }
4545         bp->rsscos_nr_ctxs = 0;
4546 }
4547
4548 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4549 {
4550         int rc;
4551         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4552         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4553                                                 bp->hwrm_cmd_resp_addr;
4554
4555         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4556                                -1);
4557
4558         mutex_lock(&bp->hwrm_cmd_lock);
4559         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4560         if (!rc)
4561                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4562                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
4563         mutex_unlock(&bp->hwrm_cmd_lock);
4564
4565         return rc;
4566 }
4567
4568 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4569 {
4570         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4571                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4572         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4573 }
4574
4575 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4576 {
4577         unsigned int ring = 0, grp_idx;
4578         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4579         struct hwrm_vnic_cfg_input req = {0};
4580         u16 def_vlan = 0;
4581
4582         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4583
4584         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4585                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4586
4587                 req.default_rx_ring_id =
4588                         cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4589                 req.default_cmpl_ring_id =
4590                         cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4591                 req.enables =
4592                         cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4593                                     VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4594                 goto vnic_mru;
4595         }
4596         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4597         /* Only RSS support for now TBD: COS & LB */
4598         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4599                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4600                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4601                                            VNIC_CFG_REQ_ENABLES_MRU);
4602         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4603                 req.rss_rule =
4604                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4605                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4606                                            VNIC_CFG_REQ_ENABLES_MRU);
4607                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4608         } else {
4609                 req.rss_rule = cpu_to_le16(0xffff);
4610         }
4611
4612         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4613             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4614                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4615                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4616         } else {
4617                 req.cos_rule = cpu_to_le16(0xffff);
4618         }
4619
4620         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4621                 ring = 0;
4622         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4623                 ring = vnic_id - 1;
4624         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4625                 ring = bp->rx_nr_rings - 1;
4626
4627         grp_idx = bp->rx_ring[ring].bnapi->index;
4628         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4629         req.lb_rule = cpu_to_le16(0xffff);
4630 vnic_mru:
4631         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4632                               VLAN_HLEN);
4633
4634         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4635 #ifdef CONFIG_BNXT_SRIOV
4636         if (BNXT_VF(bp))
4637                 def_vlan = bp->vf.vlan;
4638 #endif
4639         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4640                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4641         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4642                 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4643
4644         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4645 }
4646
4647 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4648 {
4649         u32 rc = 0;
4650
4651         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4652                 struct hwrm_vnic_free_input req = {0};
4653
4654                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4655                 req.vnic_id =
4656                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4657
4658                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4659                 if (rc)
4660                         return rc;
4661                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4662         }
4663         return rc;
4664 }
4665
4666 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4667 {
4668         u16 i;
4669
4670         for (i = 0; i < bp->nr_vnics; i++)
4671                 bnxt_hwrm_vnic_free_one(bp, i);
4672 }
4673
4674 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4675                                 unsigned int start_rx_ring_idx,
4676                                 unsigned int nr_rings)
4677 {
4678         int rc = 0;
4679         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4680         struct hwrm_vnic_alloc_input req = {0};
4681         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4682         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4683
4684         if (bp->flags & BNXT_FLAG_CHIP_P5)
4685                 goto vnic_no_ring_grps;
4686
4687         /* map ring groups to this vnic */
4688         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4689                 grp_idx = bp->rx_ring[i].bnapi->index;
4690                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4691                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4692                                    j, nr_rings);
4693                         break;
4694                 }
4695                 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4696         }
4697
4698 vnic_no_ring_grps:
4699         for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4700                 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4701         if (vnic_id == 0)
4702                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4703
4704         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4705
4706         mutex_lock(&bp->hwrm_cmd_lock);
4707         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4708         if (!rc)
4709                 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4710         mutex_unlock(&bp->hwrm_cmd_lock);
4711         return rc;
4712 }
4713
4714 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4715 {
4716         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4717         struct hwrm_vnic_qcaps_input req = {0};
4718         int rc;
4719
4720         if (bp->hwrm_spec_code < 0x10600)
4721                 return 0;
4722
4723         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4724         mutex_lock(&bp->hwrm_cmd_lock);
4725         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4726         if (!rc) {
4727                 u32 flags = le32_to_cpu(resp->flags);
4728
4729                 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4730                     (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4731                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4732                 if (flags &
4733                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4734                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4735         }
4736         mutex_unlock(&bp->hwrm_cmd_lock);
4737         return rc;
4738 }
4739
4740 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4741 {
4742         u16 i;
4743         u32 rc = 0;
4744
4745         if (bp->flags & BNXT_FLAG_CHIP_P5)
4746                 return 0;
4747
4748         mutex_lock(&bp->hwrm_cmd_lock);
4749         for (i = 0; i < bp->rx_nr_rings; i++) {
4750                 struct hwrm_ring_grp_alloc_input req = {0};
4751                 struct hwrm_ring_grp_alloc_output *resp =
4752                                         bp->hwrm_cmd_resp_addr;
4753                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4754
4755                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4756
4757                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4758                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4759                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4760                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4761
4762                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4763                                         HWRM_CMD_TIMEOUT);
4764                 if (rc)
4765                         break;
4766
4767                 bp->grp_info[grp_idx].fw_grp_id =
4768                         le32_to_cpu(resp->ring_group_id);
4769         }
4770         mutex_unlock(&bp->hwrm_cmd_lock);
4771         return rc;
4772 }
4773
4774 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4775 {
4776         u16 i;
4777         u32 rc = 0;
4778         struct hwrm_ring_grp_free_input req = {0};
4779
4780         if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4781                 return 0;
4782
4783         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4784
4785         mutex_lock(&bp->hwrm_cmd_lock);
4786         for (i = 0; i < bp->cp_nr_rings; i++) {
4787                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4788                         continue;
4789                 req.ring_group_id =
4790                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4791
4792                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4793                                         HWRM_CMD_TIMEOUT);
4794                 if (rc)
4795                         break;
4796                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4797         }
4798         mutex_unlock(&bp->hwrm_cmd_lock);
4799         return rc;
4800 }
4801
4802 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4803                                     struct bnxt_ring_struct *ring,
4804                                     u32 ring_type, u32 map_index)
4805 {
4806         int rc = 0, err = 0;
4807         struct hwrm_ring_alloc_input req = {0};
4808         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4809         struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4810         struct bnxt_ring_grp_info *grp_info;
4811         u16 ring_id;
4812
4813         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4814
4815         req.enables = 0;
4816         if (rmem->nr_pages > 1) {
4817                 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4818                 /* Page size is in log2 units */
4819                 req.page_size = BNXT_PAGE_SHIFT;
4820                 req.page_tbl_depth = 1;
4821         } else {
4822                 req.page_tbl_addr =  cpu_to_le64(rmem->dma_arr[0]);
4823         }
4824         req.fbo = 0;
4825         /* Association of ring index with doorbell index and MSIX number */
4826         req.logical_id = cpu_to_le16(map_index);
4827
4828         switch (ring_type) {
4829         case HWRM_RING_ALLOC_TX: {
4830                 struct bnxt_tx_ring_info *txr;
4831
4832                 txr = container_of(ring, struct bnxt_tx_ring_info,
4833                                    tx_ring_struct);
4834                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4835                 /* Association of transmit ring with completion ring */
4836                 grp_info = &bp->grp_info[ring->grp_idx];
4837                 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4838                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4839                 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4840                 req.queue_id = cpu_to_le16(ring->queue_id);
4841                 break;
4842         }
4843         case HWRM_RING_ALLOC_RX:
4844                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4845                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4846                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4847                         u16 flags = 0;
4848
4849                         /* Association of rx ring with stats context */
4850                         grp_info = &bp->grp_info[ring->grp_idx];
4851                         req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4852                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4853                         req.enables |= cpu_to_le32(
4854                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4855                         if (NET_IP_ALIGN == 2)
4856                                 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4857                         req.flags = cpu_to_le16(flags);
4858                 }
4859                 break;
4860         case HWRM_RING_ALLOC_AGG:
4861                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4862                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4863                         /* Association of agg ring with rx ring */
4864                         grp_info = &bp->grp_info[ring->grp_idx];
4865                         req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4866                         req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4867                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4868                         req.enables |= cpu_to_le32(
4869                                 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4870                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4871                 } else {
4872                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4873                 }
4874                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4875                 break;
4876         case HWRM_RING_ALLOC_CMPL:
4877                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4878                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4879                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4880                         /* Association of cp ring with nq */
4881                         grp_info = &bp->grp_info[map_index];
4882                         req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4883                         req.cq_handle = cpu_to_le64(ring->handle);
4884                         req.enables |= cpu_to_le32(
4885                                 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4886                 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4887                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4888                 }
4889                 break;
4890         case HWRM_RING_ALLOC_NQ:
4891                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4892                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4893                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4894                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4895                 break;
4896         default:
4897                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4898                            ring_type);
4899                 return -1;
4900         }
4901
4902         mutex_lock(&bp->hwrm_cmd_lock);
4903         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4904         err = le16_to_cpu(resp->error_code);
4905         ring_id = le16_to_cpu(resp->ring_id);
4906         mutex_unlock(&bp->hwrm_cmd_lock);
4907
4908         if (rc || err) {
4909                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4910                            ring_type, rc, err);
4911                 return -EIO;
4912         }
4913         ring->fw_ring_id = ring_id;
4914         return rc;
4915 }
4916
4917 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4918 {
4919         int rc;
4920
4921         if (BNXT_PF(bp)) {
4922                 struct hwrm_func_cfg_input req = {0};
4923
4924                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4925                 req.fid = cpu_to_le16(0xffff);
4926                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4927                 req.async_event_cr = cpu_to_le16(idx);
4928                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4929         } else {
4930                 struct hwrm_func_vf_cfg_input req = {0};
4931
4932                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4933                 req.enables =
4934                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4935                 req.async_event_cr = cpu_to_le16(idx);
4936                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4937         }
4938         return rc;
4939 }
4940
4941 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
4942                         u32 map_idx, u32 xid)
4943 {
4944         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4945                 if (BNXT_PF(bp))
4946                         db->doorbell = bp->bar1 + 0x10000;
4947                 else
4948                         db->doorbell = bp->bar1 + 0x4000;
4949                 switch (ring_type) {
4950                 case HWRM_RING_ALLOC_TX:
4951                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
4952                         break;
4953                 case HWRM_RING_ALLOC_RX:
4954                 case HWRM_RING_ALLOC_AGG:
4955                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
4956                         break;
4957                 case HWRM_RING_ALLOC_CMPL:
4958                         db->db_key64 = DBR_PATH_L2;
4959                         break;
4960                 case HWRM_RING_ALLOC_NQ:
4961                         db->db_key64 = DBR_PATH_L2;
4962                         break;
4963                 }
4964                 db->db_key64 |= (u64)xid << DBR_XID_SFT;
4965         } else {
4966                 db->doorbell = bp->bar1 + map_idx * 0x80;
4967                 switch (ring_type) {
4968                 case HWRM_RING_ALLOC_TX:
4969                         db->db_key32 = DB_KEY_TX;
4970                         break;
4971                 case HWRM_RING_ALLOC_RX:
4972                 case HWRM_RING_ALLOC_AGG:
4973                         db->db_key32 = DB_KEY_RX;
4974                         break;
4975                 case HWRM_RING_ALLOC_CMPL:
4976                         db->db_key32 = DB_KEY_CP;
4977                         break;
4978                 }
4979         }
4980 }
4981
4982 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4983 {
4984         int i, rc = 0;
4985         u32 type;
4986
4987         if (bp->flags & BNXT_FLAG_CHIP_P5)
4988                 type = HWRM_RING_ALLOC_NQ;
4989         else
4990                 type = HWRM_RING_ALLOC_CMPL;
4991         for (i = 0; i < bp->cp_nr_rings; i++) {
4992                 struct bnxt_napi *bnapi = bp->bnapi[i];
4993                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4994                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4995                 u32 map_idx = ring->map_idx;
4996                 unsigned int vector;
4997
4998                 vector = bp->irq_tbl[map_idx].vector;
4999                 disable_irq_nosync(vector);
5000                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5001                 if (rc) {
5002                         enable_irq(vector);
5003                         goto err_out;
5004                 }
5005                 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5006                 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5007                 enable_irq(vector);
5008                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5009
5010                 if (!i) {
5011                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5012                         if (rc)
5013                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5014                 }
5015         }
5016
5017         type = HWRM_RING_ALLOC_TX;
5018         for (i = 0; i < bp->tx_nr_rings; i++) {
5019                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5020                 struct bnxt_ring_struct *ring;
5021                 u32 map_idx;
5022
5023                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5024                         struct bnxt_napi *bnapi = txr->bnapi;
5025                         struct bnxt_cp_ring_info *cpr, *cpr2;
5026                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5027
5028                         cpr = &bnapi->cp_ring;
5029                         cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5030                         ring = &cpr2->cp_ring_struct;
5031                         ring->handle = BNXT_TX_HDL;
5032                         map_idx = bnapi->index;
5033                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5034                         if (rc)
5035                                 goto err_out;
5036                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5037                                     ring->fw_ring_id);
5038                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5039                 }
5040                 ring = &txr->tx_ring_struct;
5041                 map_idx = i;
5042                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5043                 if (rc)
5044                         goto err_out;
5045                 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5046         }
5047
5048         type = HWRM_RING_ALLOC_RX;
5049         for (i = 0; i < bp->rx_nr_rings; i++) {
5050                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5051                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5052                 struct bnxt_napi *bnapi = rxr->bnapi;
5053                 u32 map_idx = bnapi->index;
5054
5055                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5056                 if (rc)
5057                         goto err_out;
5058                 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5059                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5060                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5061                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5062                         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5063                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5064                         struct bnxt_cp_ring_info *cpr2;
5065
5066                         cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5067                         ring = &cpr2->cp_ring_struct;
5068                         ring->handle = BNXT_RX_HDL;
5069                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5070                         if (rc)
5071                                 goto err_out;
5072                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5073                                     ring->fw_ring_id);
5074                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5075                 }
5076         }
5077
5078         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5079                 type = HWRM_RING_ALLOC_AGG;
5080                 for (i = 0; i < bp->rx_nr_rings; i++) {
5081                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5082                         struct bnxt_ring_struct *ring =
5083                                                 &rxr->rx_agg_ring_struct;
5084                         u32 grp_idx = ring->grp_idx;
5085                         u32 map_idx = grp_idx + bp->rx_nr_rings;
5086
5087                         rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5088                         if (rc)
5089                                 goto err_out;
5090
5091                         bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5092                                     ring->fw_ring_id);
5093                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5094                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5095                 }
5096         }
5097 err_out:
5098         return rc;
5099 }
5100
5101 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5102                                    struct bnxt_ring_struct *ring,
5103                                    u32 ring_type, int cmpl_ring_id)
5104 {
5105         int rc;
5106         struct hwrm_ring_free_input req = {0};
5107         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5108         u16 error_code;
5109
5110         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5111         req.ring_type = ring_type;
5112         req.ring_id = cpu_to_le16(ring->fw_ring_id);
5113
5114         mutex_lock(&bp->hwrm_cmd_lock);
5115         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5116         error_code = le16_to_cpu(resp->error_code);
5117         mutex_unlock(&bp->hwrm_cmd_lock);
5118
5119         if (rc || error_code) {
5120                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5121                            ring_type, rc, error_code);
5122                 return -EIO;
5123         }
5124         return 0;
5125 }
5126
5127 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5128 {
5129         u32 type;
5130         int i;
5131
5132         if (!bp->bnapi)
5133                 return;
5134
5135         for (i = 0; i < bp->tx_nr_rings; i++) {
5136                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5137                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5138                 u32 cmpl_ring_id;
5139
5140                 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5141                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5142                         hwrm_ring_free_send_msg(bp, ring,
5143                                                 RING_FREE_REQ_RING_TYPE_TX,
5144                                                 close_path ? cmpl_ring_id :
5145                                                 INVALID_HW_RING_ID);
5146                         ring->fw_ring_id = INVALID_HW_RING_ID;
5147                 }
5148         }
5149
5150         for (i = 0; i < bp->rx_nr_rings; i++) {
5151                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5152                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5153                 u32 grp_idx = rxr->bnapi->index;
5154                 u32 cmpl_ring_id;
5155
5156                 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5157                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5158                         hwrm_ring_free_send_msg(bp, ring,
5159                                                 RING_FREE_REQ_RING_TYPE_RX,
5160                                                 close_path ? cmpl_ring_id :
5161                                                 INVALID_HW_RING_ID);
5162                         ring->fw_ring_id = INVALID_HW_RING_ID;
5163                         bp->grp_info[grp_idx].rx_fw_ring_id =
5164                                 INVALID_HW_RING_ID;
5165                 }
5166         }
5167
5168         if (bp->flags & BNXT_FLAG_CHIP_P5)
5169                 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5170         else
5171                 type = RING_FREE_REQ_RING_TYPE_RX;
5172         for (i = 0; i < bp->rx_nr_rings; i++) {
5173                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5174                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5175                 u32 grp_idx = rxr->bnapi->index;
5176                 u32 cmpl_ring_id;
5177
5178                 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5179                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5180                         hwrm_ring_free_send_msg(bp, ring, type,
5181                                                 close_path ? cmpl_ring_id :
5182                                                 INVALID_HW_RING_ID);
5183                         ring->fw_ring_id = INVALID_HW_RING_ID;
5184                         bp->grp_info[grp_idx].agg_fw_ring_id =
5185                                 INVALID_HW_RING_ID;
5186                 }
5187         }
5188
5189         /* The completion rings are about to be freed.  After that the
5190          * IRQ doorbell will not work anymore.  So we need to disable
5191          * IRQ here.
5192          */
5193         bnxt_disable_int_sync(bp);
5194
5195         if (bp->flags & BNXT_FLAG_CHIP_P5)
5196                 type = RING_FREE_REQ_RING_TYPE_NQ;
5197         else
5198                 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5199         for (i = 0; i < bp->cp_nr_rings; i++) {
5200                 struct bnxt_napi *bnapi = bp->bnapi[i];
5201                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5202                 struct bnxt_ring_struct *ring;
5203                 int j;
5204
5205                 for (j = 0; j < 2; j++) {
5206                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5207
5208                         if (cpr2) {
5209                                 ring = &cpr2->cp_ring_struct;
5210                                 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5211                                         continue;
5212                                 hwrm_ring_free_send_msg(bp, ring,
5213                                         RING_FREE_REQ_RING_TYPE_L2_CMPL,
5214                                         INVALID_HW_RING_ID);
5215                                 ring->fw_ring_id = INVALID_HW_RING_ID;
5216                         }
5217                 }
5218                 ring = &cpr->cp_ring_struct;
5219                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5220                         hwrm_ring_free_send_msg(bp, ring, type,
5221                                                 INVALID_HW_RING_ID);
5222                         ring->fw_ring_id = INVALID_HW_RING_ID;
5223                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5224                 }
5225         }
5226 }
5227
5228 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5229                            bool shared);
5230
5231 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5232 {
5233         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5234         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5235         struct hwrm_func_qcfg_input req = {0};
5236         int rc;
5237
5238         if (bp->hwrm_spec_code < 0x10601)
5239                 return 0;
5240
5241         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5242         req.fid = cpu_to_le16(0xffff);
5243         mutex_lock(&bp->hwrm_cmd_lock);
5244         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5245         if (rc) {
5246                 mutex_unlock(&bp->hwrm_cmd_lock);
5247                 return -EIO;
5248         }
5249
5250         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5251         if (BNXT_NEW_RM(bp)) {
5252                 u16 cp, stats;
5253
5254                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5255                 hw_resc->resv_hw_ring_grps =
5256                         le32_to_cpu(resp->alloc_hw_ring_grps);
5257                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5258                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5259                 stats = le16_to_cpu(resp->alloc_stat_ctx);
5260                 hw_resc->resv_irqs = cp;
5261                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5262                         int rx = hw_resc->resv_rx_rings;
5263                         int tx = hw_resc->resv_tx_rings;
5264
5265                         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5266                                 rx >>= 1;
5267                         if (cp < (rx + tx)) {
5268                                 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5269                                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5270                                         rx <<= 1;
5271                                 hw_resc->resv_rx_rings = rx;
5272                                 hw_resc->resv_tx_rings = tx;
5273                         }
5274                         hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5275                         hw_resc->resv_hw_ring_grps = rx;
5276                 }
5277                 hw_resc->resv_cp_rings = cp;
5278                 hw_resc->resv_stat_ctxs = stats;
5279         }
5280         mutex_unlock(&bp->hwrm_cmd_lock);
5281         return 0;
5282 }
5283
5284 /* Caller must hold bp->hwrm_cmd_lock */
5285 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5286 {
5287         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5288         struct hwrm_func_qcfg_input req = {0};
5289         int rc;
5290
5291         if (bp->hwrm_spec_code < 0x10601)
5292                 return 0;
5293
5294         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5295         req.fid = cpu_to_le16(fid);
5296         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5297         if (!rc)
5298                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5299
5300         return rc;
5301 }
5302
5303 static bool bnxt_rfs_supported(struct bnxt *bp);
5304
5305 static void
5306 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5307                              int tx_rings, int rx_rings, int ring_grps,
5308                              int cp_rings, int stats, int vnics)
5309 {
5310         u32 enables = 0;
5311
5312         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5313         req->fid = cpu_to_le16(0xffff);
5314         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5315         req->num_tx_rings = cpu_to_le16(tx_rings);
5316         if (BNXT_NEW_RM(bp)) {
5317                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5318                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5319                         enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5320                         enables |= tx_rings + ring_grps ?
5321                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5322                                    FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5323                         enables |= rx_rings ?
5324                                 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5325                 } else {
5326                         enables |= cp_rings ?
5327                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5328                                    FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5329                         enables |= ring_grps ?
5330                                    FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5331                                    FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5332                 }
5333                 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5334
5335                 req->num_rx_rings = cpu_to_le16(rx_rings);
5336                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5337                         req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5338                         req->num_msix = cpu_to_le16(cp_rings);
5339                         req->num_rsscos_ctxs =
5340                                 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5341                 } else {
5342                         req->num_cmpl_rings = cpu_to_le16(cp_rings);
5343                         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5344                         req->num_rsscos_ctxs = cpu_to_le16(1);
5345                         if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5346                             bnxt_rfs_supported(bp))
5347                                 req->num_rsscos_ctxs =
5348                                         cpu_to_le16(ring_grps + 1);
5349                 }
5350                 req->num_stat_ctxs = cpu_to_le16(stats);
5351                 req->num_vnics = cpu_to_le16(vnics);
5352         }
5353         req->enables = cpu_to_le32(enables);
5354 }
5355
5356 static void
5357 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5358                              struct hwrm_func_vf_cfg_input *req, int tx_rings,
5359                              int rx_rings, int ring_grps, int cp_rings,
5360                              int stats, int vnics)
5361 {
5362         u32 enables = 0;
5363
5364         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5365         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5366         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5367                               FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5368         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5369                 enables |= tx_rings + ring_grps ?
5370                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5371                            FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5372         } else {
5373                 enables |= cp_rings ?
5374                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5375                            FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5376                 enables |= ring_grps ?
5377                            FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5378         }
5379         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5380         enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5381
5382         req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5383         req->num_tx_rings = cpu_to_le16(tx_rings);
5384         req->num_rx_rings = cpu_to_le16(rx_rings);
5385         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5386                 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5387                 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5388         } else {
5389                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5390                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5391                 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5392         }
5393         req->num_stat_ctxs = cpu_to_le16(stats);
5394         req->num_vnics = cpu_to_le16(vnics);
5395
5396         req->enables = cpu_to_le32(enables);
5397 }
5398
5399 static int
5400 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5401                            int ring_grps, int cp_rings, int stats, int vnics)
5402 {
5403         struct hwrm_func_cfg_input req = {0};
5404         int rc;
5405
5406         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5407                                      cp_rings, stats, vnics);
5408         if (!req.enables)
5409                 return 0;
5410
5411         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5412         if (rc)
5413                 return -ENOMEM;
5414
5415         if (bp->hwrm_spec_code < 0x10601)
5416                 bp->hw_resc.resv_tx_rings = tx_rings;
5417
5418         rc = bnxt_hwrm_get_rings(bp);
5419         return rc;
5420 }
5421
5422 static int
5423 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5424                            int ring_grps, int cp_rings, int stats, int vnics)
5425 {
5426         struct hwrm_func_vf_cfg_input req = {0};
5427         int rc;
5428
5429         if (!BNXT_NEW_RM(bp)) {
5430                 bp->hw_resc.resv_tx_rings = tx_rings;
5431                 return 0;
5432         }
5433
5434         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5435                                      cp_rings, stats, vnics);
5436         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5437         if (rc)
5438                 return -ENOMEM;
5439
5440         rc = bnxt_hwrm_get_rings(bp);
5441         return rc;
5442 }
5443
5444 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5445                                    int cp, int stat, int vnic)
5446 {
5447         if (BNXT_PF(bp))
5448                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5449                                                   vnic);
5450         else
5451                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5452                                                   vnic);
5453 }
5454
5455 int bnxt_nq_rings_in_use(struct bnxt *bp)
5456 {
5457         int cp = bp->cp_nr_rings;
5458         int ulp_msix, ulp_base;
5459
5460         ulp_msix = bnxt_get_ulp_msix_num(bp);
5461         if (ulp_msix) {
5462                 ulp_base = bnxt_get_ulp_msix_base(bp);
5463                 cp += ulp_msix;
5464                 if ((ulp_base + ulp_msix) > cp)
5465                         cp = ulp_base + ulp_msix;
5466         }
5467         return cp;
5468 }
5469
5470 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5471 {
5472         int cp;
5473
5474         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5475                 return bnxt_nq_rings_in_use(bp);
5476
5477         cp = bp->tx_nr_rings + bp->rx_nr_rings;
5478         return cp;
5479 }
5480
5481 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5482 {
5483         return bp->cp_nr_rings + bnxt_get_ulp_stat_ctxs(bp);
5484 }
5485
5486 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5487 {
5488         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5489         int cp = bnxt_cp_rings_in_use(bp);
5490         int nq = bnxt_nq_rings_in_use(bp);
5491         int rx = bp->rx_nr_rings, stat;
5492         int vnic = 1, grp = rx;
5493
5494         if (bp->hwrm_spec_code < 0x10601)
5495                 return false;
5496
5497         if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5498                 return true;
5499
5500         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5501                 vnic = rx + 1;
5502         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5503                 rx <<= 1;
5504         stat = bnxt_get_func_stat_ctxs(bp);
5505         if (BNXT_NEW_RM(bp) &&
5506             (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5507              hw_resc->resv_irqs < nq || hw_resc->resv_vnics != vnic ||
5508              hw_resc->resv_stat_ctxs != stat ||
5509              (hw_resc->resv_hw_ring_grps != grp &&
5510               !(bp->flags & BNXT_FLAG_CHIP_P5))))
5511                 return true;
5512         return false;
5513 }
5514
5515 static int __bnxt_reserve_rings(struct bnxt *bp)
5516 {
5517         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5518         int cp = bnxt_nq_rings_in_use(bp);
5519         int tx = bp->tx_nr_rings;
5520         int rx = bp->rx_nr_rings;
5521         int grp, rx_rings, rc;
5522         int vnic = 1, stat;
5523         bool sh = false;
5524
5525         if (!bnxt_need_reserve_rings(bp))
5526                 return 0;
5527
5528         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5529                 sh = true;
5530         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5531                 vnic = rx + 1;
5532         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5533                 rx <<= 1;
5534         grp = bp->rx_nr_rings;
5535         stat = bnxt_get_func_stat_ctxs(bp);
5536
5537         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5538         if (rc)
5539                 return rc;
5540
5541         tx = hw_resc->resv_tx_rings;
5542         if (BNXT_NEW_RM(bp)) {
5543                 rx = hw_resc->resv_rx_rings;
5544                 cp = hw_resc->resv_irqs;
5545                 grp = hw_resc->resv_hw_ring_grps;
5546                 vnic = hw_resc->resv_vnics;
5547                 stat = hw_resc->resv_stat_ctxs;
5548         }
5549
5550         rx_rings = rx;
5551         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5552                 if (rx >= 2) {
5553                         rx_rings = rx >> 1;
5554                 } else {
5555                         if (netif_running(bp->dev))
5556                                 return -ENOMEM;
5557
5558                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5559                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5560                         bp->dev->hw_features &= ~NETIF_F_LRO;
5561                         bp->dev->features &= ~NETIF_F_LRO;
5562                         bnxt_set_ring_params(bp);
5563                 }
5564         }
5565         rx_rings = min_t(int, rx_rings, grp);
5566         cp = min_t(int, cp, bp->cp_nr_rings);
5567         if (stat > bnxt_get_ulp_stat_ctxs(bp))
5568                 stat -= bnxt_get_ulp_stat_ctxs(bp);
5569         cp = min_t(int, cp, stat);
5570         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5571         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5572                 rx = rx_rings << 1;
5573         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5574         bp->tx_nr_rings = tx;
5575         bp->rx_nr_rings = rx_rings;
5576         bp->cp_nr_rings = cp;
5577
5578         if (!tx || !rx || !cp || !grp || !vnic || !stat)
5579                 return -ENOMEM;
5580
5581         return rc;
5582 }
5583
5584 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5585                                     int ring_grps, int cp_rings, int stats,
5586                                     int vnics)
5587 {
5588         struct hwrm_func_vf_cfg_input req = {0};
5589         u32 flags;
5590         int rc;
5591
5592         if (!BNXT_NEW_RM(bp))
5593                 return 0;
5594
5595         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5596                                      cp_rings, stats, vnics);
5597         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5598                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5599                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5600                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5601                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5602                 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5603         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5604                 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5605
5606         req.flags = cpu_to_le32(flags);
5607         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5608         if (rc)
5609                 return -ENOMEM;
5610         return 0;
5611 }
5612
5613 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5614                                     int ring_grps, int cp_rings, int stats,
5615                                     int vnics)
5616 {
5617         struct hwrm_func_cfg_input req = {0};
5618         u32 flags;
5619         int rc;
5620
5621         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5622                                      cp_rings, stats, vnics);
5623         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5624         if (BNXT_NEW_RM(bp)) {
5625                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5626                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5627                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5628                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5629                 if (bp->flags & BNXT_FLAG_CHIP_P5)
5630                         flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
5631                                  FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
5632                 else
5633                         flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5634         }
5635
5636         req.flags = cpu_to_le32(flags);
5637         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5638         if (rc)
5639                 return -ENOMEM;
5640         return 0;
5641 }
5642
5643 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5644                                  int ring_grps, int cp_rings, int stats,
5645                                  int vnics)
5646 {
5647         if (bp->hwrm_spec_code < 0x10801)
5648                 return 0;
5649
5650         if (BNXT_PF(bp))
5651                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5652                                                 ring_grps, cp_rings, stats,
5653                                                 vnics);
5654
5655         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5656                                         cp_rings, stats, vnics);
5657 }
5658
5659 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5660 {
5661         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5662         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5663         struct hwrm_ring_aggint_qcaps_input req = {0};
5664         int rc;
5665
5666         coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5667         coal_cap->num_cmpl_dma_aggr_max = 63;
5668         coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5669         coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5670         coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5671         coal_cap->int_lat_tmr_min_max = 65535;
5672         coal_cap->int_lat_tmr_max_max = 65535;
5673         coal_cap->num_cmpl_aggr_int_max = 65535;
5674         coal_cap->timer_units = 80;
5675
5676         if (bp->hwrm_spec_code < 0x10902)
5677                 return;
5678
5679         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5680         mutex_lock(&bp->hwrm_cmd_lock);
5681         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5682         if (!rc) {
5683                 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5684                 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5685                 coal_cap->num_cmpl_dma_aggr_max =
5686                         le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5687                 coal_cap->num_cmpl_dma_aggr_during_int_max =
5688                         le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5689                 coal_cap->cmpl_aggr_dma_tmr_max =
5690                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5691                 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5692                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5693                 coal_cap->int_lat_tmr_min_max =
5694                         le16_to_cpu(resp->int_lat_tmr_min_max);
5695                 coal_cap->int_lat_tmr_max_max =
5696                         le16_to_cpu(resp->int_lat_tmr_max_max);
5697                 coal_cap->num_cmpl_aggr_int_max =
5698                         le16_to_cpu(resp->num_cmpl_aggr_int_max);
5699                 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5700         }
5701         mutex_unlock(&bp->hwrm_cmd_lock);
5702 }
5703
5704 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5705 {
5706         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5707
5708         return usec * 1000 / coal_cap->timer_units;
5709 }
5710
5711 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5712         struct bnxt_coal *hw_coal,
5713         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5714 {
5715         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5716         u32 cmpl_params = coal_cap->cmpl_params;
5717         u16 val, tmr, max, flags = 0;
5718
5719         max = hw_coal->bufs_per_record * 128;
5720         if (hw_coal->budget)
5721                 max = hw_coal->bufs_per_record * hw_coal->budget;
5722         max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5723
5724         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5725         req->num_cmpl_aggr_int = cpu_to_le16(val);
5726
5727         val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5728         req->num_cmpl_dma_aggr = cpu_to_le16(val);
5729
5730         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5731                       coal_cap->num_cmpl_dma_aggr_during_int_max);
5732         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5733
5734         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5735         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5736         req->int_lat_tmr_max = cpu_to_le16(tmr);
5737
5738         /* min timer set to 1/2 of interrupt timer */
5739         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5740                 val = tmr / 2;
5741                 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5742                 req->int_lat_tmr_min = cpu_to_le16(val);
5743                 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5744         }
5745
5746         /* buf timer set to 1/4 of interrupt timer */
5747         val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5748         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5749
5750         if (cmpl_params &
5751             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5752                 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5753                 val = clamp_t(u16, tmr, 1,
5754                               coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5755                 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5756                 req->enables |=
5757                         cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5758         }
5759
5760         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5761                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5762         if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5763             hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5764                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5765         req->flags = cpu_to_le16(flags);
5766         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5767 }
5768
5769 /* Caller holds bp->hwrm_cmd_lock */
5770 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5771                                    struct bnxt_coal *hw_coal)
5772 {
5773         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5774         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5775         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5776         u32 nq_params = coal_cap->nq_params;
5777         u16 tmr;
5778
5779         if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5780                 return 0;
5781
5782         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5783                                -1, -1);
5784         req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5785         req.flags =
5786                 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5787
5788         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5789         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5790         req.int_lat_tmr_min = cpu_to_le16(tmr);
5791         req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5792         return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5793 }
5794
5795 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5796 {
5797         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5798         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5799         struct bnxt_coal coal;
5800
5801         /* Tick values in micro seconds.
5802          * 1 coal_buf x bufs_per_record = 1 completion record.
5803          */
5804         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5805
5806         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5807         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5808
5809         if (!bnapi->rx_ring)
5810                 return -ENODEV;
5811
5812         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5813                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5814
5815         bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5816
5817         req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5818
5819         return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5820                                  HWRM_CMD_TIMEOUT);
5821 }
5822
5823 int bnxt_hwrm_set_coal(struct bnxt *bp)
5824 {
5825         int i, rc = 0;
5826         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5827                                                            req_tx = {0}, *req;
5828
5829         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5830                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5831         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5832                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5833
5834         bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5835         bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5836
5837         mutex_lock(&bp->hwrm_cmd_lock);
5838         for (i = 0; i < bp->cp_nr_rings; i++) {
5839                 struct bnxt_napi *bnapi = bp->bnapi[i];
5840                 struct bnxt_coal *hw_coal;
5841                 u16 ring_id;
5842
5843                 req = &req_rx;
5844                 if (!bnapi->rx_ring) {
5845                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5846                         req = &req_tx;
5847                 } else {
5848                         ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5849                 }
5850                 req->ring_id = cpu_to_le16(ring_id);
5851
5852                 rc = _hwrm_send_message(bp, req, sizeof(*req),
5853                                         HWRM_CMD_TIMEOUT);
5854                 if (rc)
5855                         break;
5856
5857                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5858                         continue;
5859
5860                 if (bnapi->rx_ring && bnapi->tx_ring) {
5861                         req = &req_tx;
5862                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5863                         req->ring_id = cpu_to_le16(ring_id);
5864                         rc = _hwrm_send_message(bp, req, sizeof(*req),
5865                                                 HWRM_CMD_TIMEOUT);
5866                         if (rc)
5867                                 break;
5868                 }
5869                 if (bnapi->rx_ring)
5870                         hw_coal = &bp->rx_coal;
5871                 else
5872                         hw_coal = &bp->tx_coal;
5873                 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5874         }
5875         mutex_unlock(&bp->hwrm_cmd_lock);
5876         return rc;
5877 }
5878
5879 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5880 {
5881         int rc = 0, i;
5882         struct hwrm_stat_ctx_free_input req = {0};
5883
5884         if (!bp->bnapi)
5885                 return 0;
5886
5887         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5888                 return 0;
5889
5890         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5891
5892         mutex_lock(&bp->hwrm_cmd_lock);
5893         for (i = 0; i < bp->cp_nr_rings; i++) {
5894                 struct bnxt_napi *bnapi = bp->bnapi[i];
5895                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5896
5897                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5898                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5899
5900                         rc = _hwrm_send_message(bp, &req, sizeof(req),
5901                                                 HWRM_CMD_TIMEOUT);
5902                         if (rc)
5903                                 break;
5904
5905                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5906                 }
5907         }
5908         mutex_unlock(&bp->hwrm_cmd_lock);
5909         return rc;
5910 }
5911
5912 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5913 {
5914         int rc = 0, i;
5915         struct hwrm_stat_ctx_alloc_input req = {0};
5916         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5917
5918         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5919                 return 0;
5920
5921         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5922
5923         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5924
5925         mutex_lock(&bp->hwrm_cmd_lock);
5926         for (i = 0; i < bp->cp_nr_rings; i++) {
5927                 struct bnxt_napi *bnapi = bp->bnapi[i];
5928                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5929
5930                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5931
5932                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5933                                         HWRM_CMD_TIMEOUT);
5934                 if (rc)
5935                         break;
5936
5937                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5938
5939                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5940         }
5941         mutex_unlock(&bp->hwrm_cmd_lock);
5942         return rc;
5943 }
5944
5945 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5946 {
5947         struct hwrm_func_qcfg_input req = {0};
5948         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5949         u16 flags;
5950         int rc;
5951
5952         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5953         req.fid = cpu_to_le16(0xffff);
5954         mutex_lock(&bp->hwrm_cmd_lock);
5955         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5956         if (rc)
5957                 goto func_qcfg_exit;
5958
5959 #ifdef CONFIG_BNXT_SRIOV
5960         if (BNXT_VF(bp)) {
5961                 struct bnxt_vf_info *vf = &bp->vf;
5962
5963                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5964         }
5965 #endif
5966         flags = le16_to_cpu(resp->flags);
5967         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5968                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5969                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5970                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5971                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
5972         }
5973         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5974                 bp->flags |= BNXT_FLAG_MULTI_HOST;
5975
5976         switch (resp->port_partition_type) {
5977         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5978         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5979         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5980                 bp->port_partition_type = resp->port_partition_type;
5981                 break;
5982         }
5983         if (bp->hwrm_spec_code < 0x10707 ||
5984             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5985                 bp->br_mode = BRIDGE_MODE_VEB;
5986         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5987                 bp->br_mode = BRIDGE_MODE_VEPA;
5988         else
5989                 bp->br_mode = BRIDGE_MODE_UNDEF;
5990
5991         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5992         if (!bp->max_mtu)
5993                 bp->max_mtu = BNXT_MAX_MTU;
5994
5995 func_qcfg_exit:
5996         mutex_unlock(&bp->hwrm_cmd_lock);
5997         return rc;
5998 }
5999
6000 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6001 {
6002         struct hwrm_func_backing_store_qcaps_input req = {0};
6003         struct hwrm_func_backing_store_qcaps_output *resp =
6004                 bp->hwrm_cmd_resp_addr;
6005         int rc;
6006
6007         if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6008                 return 0;
6009
6010         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6011         mutex_lock(&bp->hwrm_cmd_lock);
6012         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6013         if (!rc) {
6014                 struct bnxt_ctx_pg_info *ctx_pg;
6015                 struct bnxt_ctx_mem_info *ctx;
6016                 int i;
6017
6018                 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6019                 if (!ctx) {
6020                         rc = -ENOMEM;
6021                         goto ctx_err;
6022                 }
6023                 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6024                 if (!ctx_pg) {
6025                         kfree(ctx);
6026                         rc = -ENOMEM;
6027                         goto ctx_err;
6028                 }
6029                 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6030                         ctx->tqm_mem[i] = ctx_pg;
6031
6032                 bp->ctx = ctx;
6033                 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6034                 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6035                 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6036                 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6037                 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6038                 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6039                 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6040                 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6041                 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6042                 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6043                 ctx->vnic_max_vnic_entries =
6044                         le16_to_cpu(resp->vnic_max_vnic_entries);
6045                 ctx->vnic_max_ring_table_entries =
6046                         le16_to_cpu(resp->vnic_max_ring_table_entries);
6047                 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6048                 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6049                 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6050                 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6051                 ctx->tqm_min_entries_per_ring =
6052                         le32_to_cpu(resp->tqm_min_entries_per_ring);
6053                 ctx->tqm_max_entries_per_ring =
6054                         le32_to_cpu(resp->tqm_max_entries_per_ring);
6055                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6056                 if (!ctx->tqm_entries_multiple)
6057                         ctx->tqm_entries_multiple = 1;
6058                 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6059                 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6060                 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6061                 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6062         } else {
6063                 rc = 0;
6064         }
6065 ctx_err:
6066         mutex_unlock(&bp->hwrm_cmd_lock);
6067         return rc;
6068 }
6069
6070 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6071                                   __le64 *pg_dir)
6072 {
6073         u8 pg_size = 0;
6074
6075         if (BNXT_PAGE_SHIFT == 13)
6076                 pg_size = 1 << 4;
6077         else if (BNXT_PAGE_SIZE == 16)
6078                 pg_size = 2 << 4;
6079
6080         *pg_attr = pg_size;
6081         if (rmem->depth >= 1) {
6082                 if (rmem->depth == 2)
6083                         *pg_attr |= 2;
6084                 else
6085                         *pg_attr |= 1;
6086                 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6087         } else {
6088                 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6089         }
6090 }
6091
6092 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES                 \
6093         (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP |                \
6094          FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ |               \
6095          FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ |                \
6096          FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC |              \
6097          FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6098
6099 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6100 {
6101         struct hwrm_func_backing_store_cfg_input req = {0};
6102         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6103         struct bnxt_ctx_pg_info *ctx_pg;
6104         __le32 *num_entries;
6105         __le64 *pg_dir;
6106         u8 *pg_attr;
6107         int i, rc;
6108         u32 ena;
6109
6110         if (!ctx)
6111                 return 0;
6112
6113         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6114         req.enables = cpu_to_le32(enables);
6115
6116         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6117                 ctx_pg = &ctx->qp_mem;
6118                 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6119                 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6120                 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6121                 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6122                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6123                                       &req.qpc_pg_size_qpc_lvl,
6124                                       &req.qpc_page_dir);
6125         }
6126         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6127                 ctx_pg = &ctx->srq_mem;
6128                 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6129                 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6130                 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6131                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6132                                       &req.srq_pg_size_srq_lvl,
6133                                       &req.srq_page_dir);
6134         }
6135         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6136                 ctx_pg = &ctx->cq_mem;
6137                 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6138                 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6139                 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6140                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6141                                       &req.cq_page_dir);
6142         }
6143         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6144                 ctx_pg = &ctx->vnic_mem;
6145                 req.vnic_num_vnic_entries =
6146                         cpu_to_le16(ctx->vnic_max_vnic_entries);
6147                 req.vnic_num_ring_table_entries =
6148                         cpu_to_le16(ctx->vnic_max_ring_table_entries);
6149                 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6150                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6151                                       &req.vnic_pg_size_vnic_lvl,
6152                                       &req.vnic_page_dir);
6153         }
6154         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6155                 ctx_pg = &ctx->stat_mem;
6156                 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6157                 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6158                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6159                                       &req.stat_pg_size_stat_lvl,
6160                                       &req.stat_page_dir);
6161         }
6162         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6163                 ctx_pg = &ctx->mrav_mem;
6164                 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6165                 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6166                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6167                                       &req.mrav_pg_size_mrav_lvl,
6168                                       &req.mrav_page_dir);
6169         }
6170         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6171                 ctx_pg = &ctx->tim_mem;
6172                 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6173                 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6174                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6175                                       &req.tim_pg_size_tim_lvl,
6176                                       &req.tim_page_dir);
6177         }
6178         for (i = 0, num_entries = &req.tqm_sp_num_entries,
6179              pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6180              pg_dir = &req.tqm_sp_page_dir,
6181              ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6182              i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6183                 if (!(enables & ena))
6184                         continue;
6185
6186                 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6187                 ctx_pg = ctx->tqm_mem[i];
6188                 *num_entries = cpu_to_le32(ctx_pg->entries);
6189                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6190         }
6191         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6192         if (rc)
6193                 rc = -EIO;
6194         return rc;
6195 }
6196
6197 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6198                                   struct bnxt_ctx_pg_info *ctx_pg)
6199 {
6200         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6201
6202         rmem->page_size = BNXT_PAGE_SIZE;
6203         rmem->pg_arr = ctx_pg->ctx_pg_arr;
6204         rmem->dma_arr = ctx_pg->ctx_dma_arr;
6205         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6206         if (rmem->depth >= 1)
6207                 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6208         return bnxt_alloc_ring(bp, rmem);
6209 }
6210
6211 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6212                                   struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6213                                   u8 depth)
6214 {
6215         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6216         int rc;
6217
6218         if (!mem_size)
6219                 return 0;
6220
6221         ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6222         if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6223                 ctx_pg->nr_pages = 0;
6224                 return -EINVAL;
6225         }
6226         if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6227                 int nr_tbls, i;
6228
6229                 rmem->depth = 2;
6230                 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6231                                              GFP_KERNEL);
6232                 if (!ctx_pg->ctx_pg_tbl)
6233                         return -ENOMEM;
6234                 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6235                 rmem->nr_pages = nr_tbls;
6236                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6237                 if (rc)
6238                         return rc;
6239                 for (i = 0; i < nr_tbls; i++) {
6240                         struct bnxt_ctx_pg_info *pg_tbl;
6241
6242                         pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6243                         if (!pg_tbl)
6244                                 return -ENOMEM;
6245                         ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6246                         rmem = &pg_tbl->ring_mem;
6247                         rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6248                         rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6249                         rmem->depth = 1;
6250                         rmem->nr_pages = MAX_CTX_PAGES;
6251                         if (i == (nr_tbls - 1)) {
6252                                 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6253
6254                                 if (rem)
6255                                         rmem->nr_pages = rem;
6256                         }
6257                         rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6258                         if (rc)
6259                                 break;
6260                 }
6261         } else {
6262                 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6263                 if (rmem->nr_pages > 1 || depth)
6264                         rmem->depth = 1;
6265                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6266         }
6267         return rc;
6268 }
6269
6270 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6271                                   struct bnxt_ctx_pg_info *ctx_pg)
6272 {
6273         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6274
6275         if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6276             ctx_pg->ctx_pg_tbl) {
6277                 int i, nr_tbls = rmem->nr_pages;
6278
6279                 for (i = 0; i < nr_tbls; i++) {
6280                         struct bnxt_ctx_pg_info *pg_tbl;
6281                         struct bnxt_ring_mem_info *rmem2;
6282
6283                         pg_tbl = ctx_pg->ctx_pg_tbl[i];
6284                         if (!pg_tbl)
6285                                 continue;
6286                         rmem2 = &pg_tbl->ring_mem;
6287                         bnxt_free_ring(bp, rmem2);
6288                         ctx_pg->ctx_pg_arr[i] = NULL;
6289                         kfree(pg_tbl);
6290                         ctx_pg->ctx_pg_tbl[i] = NULL;
6291                 }
6292                 kfree(ctx_pg->ctx_pg_tbl);
6293                 ctx_pg->ctx_pg_tbl = NULL;
6294         }
6295         bnxt_free_ring(bp, rmem);
6296         ctx_pg->nr_pages = 0;
6297 }
6298
6299 static void bnxt_free_ctx_mem(struct bnxt *bp)
6300 {
6301         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6302         int i;
6303
6304         if (!ctx)
6305                 return;
6306
6307         if (ctx->tqm_mem[0]) {
6308                 for (i = 0; i < bp->max_q + 1; i++)
6309                         bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6310                 kfree(ctx->tqm_mem[0]);
6311                 ctx->tqm_mem[0] = NULL;
6312         }
6313
6314         bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6315         bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6316         bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6317         bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6318         bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6319         bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6320         bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6321         ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6322 }
6323
6324 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6325 {
6326         struct bnxt_ctx_pg_info *ctx_pg;
6327         struct bnxt_ctx_mem_info *ctx;
6328         u32 mem_size, ena, entries;
6329         u32 extra_srqs = 0;
6330         u32 extra_qps = 0;
6331         u8 pg_lvl = 1;
6332         int i, rc;
6333
6334         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6335         if (rc) {
6336                 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6337                            rc);
6338                 return rc;
6339         }
6340         ctx = bp->ctx;
6341         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6342                 return 0;
6343
6344         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
6345                 pg_lvl = 2;
6346                 extra_qps = 65536;
6347                 extra_srqs = 8192;
6348         }
6349
6350         ctx_pg = &ctx->qp_mem;
6351         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6352                           extra_qps;
6353         mem_size = ctx->qp_entry_size * ctx_pg->entries;
6354         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6355         if (rc)
6356                 return rc;
6357
6358         ctx_pg = &ctx->srq_mem;
6359         ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6360         mem_size = ctx->srq_entry_size * ctx_pg->entries;
6361         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6362         if (rc)
6363                 return rc;
6364
6365         ctx_pg = &ctx->cq_mem;
6366         ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6367         mem_size = ctx->cq_entry_size * ctx_pg->entries;
6368         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6369         if (rc)
6370                 return rc;
6371
6372         ctx_pg = &ctx->vnic_mem;
6373         ctx_pg->entries = ctx->vnic_max_vnic_entries +
6374                           ctx->vnic_max_ring_table_entries;
6375         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6376         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6377         if (rc)
6378                 return rc;
6379
6380         ctx_pg = &ctx->stat_mem;
6381         ctx_pg->entries = ctx->stat_max_entries;
6382         mem_size = ctx->stat_entry_size * ctx_pg->entries;
6383         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6384         if (rc)
6385                 return rc;
6386
6387         ena = 0;
6388         if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6389                 goto skip_rdma;
6390
6391         ctx_pg = &ctx->mrav_mem;
6392         ctx_pg->entries = extra_qps * 4;
6393         mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6394         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6395         if (rc)
6396                 return rc;
6397         ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6398
6399         ctx_pg = &ctx->tim_mem;
6400         ctx_pg->entries = ctx->qp_mem.entries;
6401         mem_size = ctx->tim_entry_size * ctx_pg->entries;
6402         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6403         if (rc)
6404                 return rc;
6405         ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6406
6407 skip_rdma:
6408         entries = ctx->qp_max_l2_entries + extra_qps;
6409         entries = roundup(entries, ctx->tqm_entries_multiple);
6410         entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6411                           ctx->tqm_max_entries_per_ring);
6412         for (i = 0; i < bp->max_q + 1; i++) {
6413                 ctx_pg = ctx->tqm_mem[i];
6414                 ctx_pg->entries = entries;
6415                 mem_size = ctx->tqm_entry_size * entries;
6416                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6417                 if (rc)
6418                         return rc;
6419                 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6420         }
6421         ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6422         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6423         if (rc)
6424                 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6425                            rc);
6426         else
6427                 ctx->flags |= BNXT_CTX_FLAG_INITED;
6428
6429         return 0;
6430 }
6431
6432 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6433 {
6434         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6435         struct hwrm_func_resource_qcaps_input req = {0};
6436         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6437         int rc;
6438
6439         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6440         req.fid = cpu_to_le16(0xffff);
6441
6442         mutex_lock(&bp->hwrm_cmd_lock);
6443         rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6444                                        HWRM_CMD_TIMEOUT);
6445         if (rc) {
6446                 rc = -EIO;
6447                 goto hwrm_func_resc_qcaps_exit;
6448         }
6449
6450         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6451         if (!all)
6452                 goto hwrm_func_resc_qcaps_exit;
6453
6454         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6455         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6456         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6457         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6458         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6459         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6460         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6461         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6462         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6463         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6464         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6465         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6466         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6467         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6468         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6469         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6470
6471         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6472                 u16 max_msix = le16_to_cpu(resp->max_msix);
6473
6474                 hw_resc->max_nqs = max_msix;
6475                 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6476         }
6477
6478         if (BNXT_PF(bp)) {
6479                 struct bnxt_pf_info *pf = &bp->pf;
6480
6481                 pf->vf_resv_strategy =
6482                         le16_to_cpu(resp->vf_reservation_strategy);
6483                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6484                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6485         }
6486 hwrm_func_resc_qcaps_exit:
6487         mutex_unlock(&bp->hwrm_cmd_lock);
6488         return rc;
6489 }
6490
6491 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6492 {
6493         int rc = 0;
6494         struct hwrm_func_qcaps_input req = {0};
6495         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6496         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6497         u32 flags;
6498
6499         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6500         req.fid = cpu_to_le16(0xffff);
6501
6502         mutex_lock(&bp->hwrm_cmd_lock);
6503         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6504         if (rc)
6505                 goto hwrm_func_qcaps_exit;
6506
6507         flags = le32_to_cpu(resp->flags);
6508         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6509                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6510         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6511                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6512
6513         bp->tx_push_thresh = 0;
6514         if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6515                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6516
6517         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6518         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6519         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6520         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6521         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6522         if (!hw_resc->max_hw_ring_grps)
6523                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6524         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6525         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6526         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6527
6528         if (BNXT_PF(bp)) {
6529                 struct bnxt_pf_info *pf = &bp->pf;
6530
6531                 pf->fw_fid = le16_to_cpu(resp->fid);
6532                 pf->port_id = le16_to_cpu(resp->port_id);
6533                 bp->dev->dev_port = pf->port_id;
6534                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6535                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6536                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6537                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6538                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6539                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6540                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6541                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6542                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6543                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6544                         bp->flags |= BNXT_FLAG_WOL_CAP;
6545         } else {
6546 #ifdef CONFIG_BNXT_SRIOV
6547                 struct bnxt_vf_info *vf = &bp->vf;
6548
6549                 vf->fw_fid = le16_to_cpu(resp->fid);
6550                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6551 #endif
6552         }
6553
6554 hwrm_func_qcaps_exit:
6555         mutex_unlock(&bp->hwrm_cmd_lock);
6556         return rc;
6557 }
6558
6559 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6560
6561 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6562 {
6563         int rc;
6564
6565         rc = __bnxt_hwrm_func_qcaps(bp);
6566         if (rc)
6567                 return rc;
6568         rc = bnxt_hwrm_queue_qportcfg(bp);
6569         if (rc) {
6570                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6571                 return rc;
6572         }
6573         if (bp->hwrm_spec_code >= 0x10803) {
6574                 rc = bnxt_alloc_ctx_mem(bp);
6575                 if (rc)
6576                         return rc;
6577                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6578                 if (!rc)
6579                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6580         }
6581         return 0;
6582 }
6583
6584 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6585 {
6586         struct hwrm_func_reset_input req = {0};
6587
6588         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6589         req.enables = 0;
6590
6591         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6592 }
6593
6594 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6595 {
6596         int rc = 0;
6597         struct hwrm_queue_qportcfg_input req = {0};
6598         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6599         u8 i, j, *qptr;
6600         bool no_rdma;
6601
6602         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6603
6604         mutex_lock(&bp->hwrm_cmd_lock);
6605         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6606         if (rc)
6607                 goto qportcfg_exit;
6608
6609         if (!resp->max_configurable_queues) {
6610                 rc = -EINVAL;
6611                 goto qportcfg_exit;
6612         }
6613         bp->max_tc = resp->max_configurable_queues;
6614         bp->max_lltc = resp->max_configurable_lossless_queues;
6615         if (bp->max_tc > BNXT_MAX_QUEUE)
6616                 bp->max_tc = BNXT_MAX_QUEUE;
6617
6618         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6619         qptr = &resp->queue_id0;
6620         for (i = 0, j = 0; i < bp->max_tc; i++) {
6621                 bp->q_info[j].queue_id = *qptr;
6622                 bp->q_ids[i] = *qptr++;
6623                 bp->q_info[j].queue_profile = *qptr++;
6624                 bp->tc_to_qidx[j] = j;
6625                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6626                     (no_rdma && BNXT_PF(bp)))
6627                         j++;
6628         }
6629         bp->max_q = bp->max_tc;
6630         bp->max_tc = max_t(u8, j, 1);
6631
6632         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6633                 bp->max_tc = 1;
6634
6635         if (bp->max_lltc > bp->max_tc)
6636                 bp->max_lltc = bp->max_tc;
6637
6638 qportcfg_exit:
6639         mutex_unlock(&bp->hwrm_cmd_lock);
6640         return rc;
6641 }
6642
6643 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6644 {
6645         int rc;
6646         struct hwrm_ver_get_input req = {0};
6647         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6648         u32 dev_caps_cfg;
6649
6650         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6651         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6652         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6653         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6654         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6655         mutex_lock(&bp->hwrm_cmd_lock);
6656         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6657         if (rc)
6658                 goto hwrm_ver_get_exit;
6659
6660         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6661
6662         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6663                              resp->hwrm_intf_min_8b << 8 |
6664                              resp->hwrm_intf_upd_8b;
6665         if (resp->hwrm_intf_maj_8b < 1) {
6666                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6667                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6668                             resp->hwrm_intf_upd_8b);
6669                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6670         }
6671         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6672                  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6673                  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6674
6675         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6676         if (!bp->hwrm_cmd_timeout)
6677                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6678
6679         if (resp->hwrm_intf_maj_8b >= 1) {
6680                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6681                 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6682         }
6683         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6684                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6685
6686         bp->chip_num = le16_to_cpu(resp->chip_num);
6687         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6688             !resp->chip_metal)
6689                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6690
6691         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6692         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6693             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6694                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6695
6696         if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6697                 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6698
6699         if (dev_caps_cfg &
6700             VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6701                 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6702
6703         if (dev_caps_cfg &
6704             VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
6705                 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
6706
6707 hwrm_ver_get_exit:
6708         mutex_unlock(&bp->hwrm_cmd_lock);
6709         return rc;
6710 }
6711
6712 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6713 {
6714         struct hwrm_fw_set_time_input req = {0};
6715         struct tm tm;
6716         time64_t now = ktime_get_real_seconds();
6717
6718         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6719             bp->hwrm_spec_code < 0x10400)
6720                 return -EOPNOTSUPP;
6721
6722         time64_to_tm(now, 0, &tm);
6723         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6724         req.year = cpu_to_le16(1900 + tm.tm_year);
6725         req.month = 1 + tm.tm_mon;
6726         req.day = tm.tm_mday;
6727         req.hour = tm.tm_hour;
6728         req.minute = tm.tm_min;
6729         req.second = tm.tm_sec;
6730         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6731 }
6732
6733 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6734 {
6735         int rc;
6736         struct bnxt_pf_info *pf = &bp->pf;
6737         struct hwrm_port_qstats_input req = {0};
6738
6739         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6740                 return 0;
6741
6742         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6743         req.port_id = cpu_to_le16(pf->port_id);
6744         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6745         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6746         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6747         return rc;
6748 }
6749
6750 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6751 {
6752         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6753         struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6754         struct hwrm_port_qstats_ext_input req = {0};
6755         struct bnxt_pf_info *pf = &bp->pf;
6756         int rc;
6757
6758         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6759                 return 0;
6760
6761         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6762         req.port_id = cpu_to_le16(pf->port_id);
6763         req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6764         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6765         req.tx_stat_size = cpu_to_le16(sizeof(struct tx_port_stats_ext));
6766         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6767         mutex_lock(&bp->hwrm_cmd_lock);
6768         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6769         if (!rc) {
6770                 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6771                 bp->fw_tx_stats_ext_size = le16_to_cpu(resp->tx_stat_size) / 8;
6772         } else {
6773                 bp->fw_rx_stats_ext_size = 0;
6774                 bp->fw_tx_stats_ext_size = 0;
6775         }
6776         if (bp->fw_tx_stats_ext_size <=
6777             offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6778                 mutex_unlock(&bp->hwrm_cmd_lock);
6779                 bp->pri2cos_valid = 0;
6780                 return rc;
6781         }
6782
6783         bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6784         req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6785
6786         rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6787         if (!rc) {
6788                 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6789                 u8 *pri2cos;
6790                 int i, j;
6791
6792                 resp2 = bp->hwrm_cmd_resp_addr;
6793                 pri2cos = &resp2->pri0_cos_queue_id;
6794                 for (i = 0; i < 8; i++) {
6795                         u8 queue_id = pri2cos[i];
6796
6797                         for (j = 0; j < bp->max_q; j++) {
6798                                 if (bp->q_ids[j] == queue_id)
6799                                         bp->pri2cos[i] = j;
6800                         }
6801                 }
6802                 bp->pri2cos_valid = 1;
6803         }
6804         mutex_unlock(&bp->hwrm_cmd_lock);
6805         return rc;
6806 }
6807
6808 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6809 {
6810         if (bp->vxlan_port_cnt) {
6811                 bnxt_hwrm_tunnel_dst_port_free(
6812                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6813         }
6814         bp->vxlan_port_cnt = 0;
6815         if (bp->nge_port_cnt) {
6816                 bnxt_hwrm_tunnel_dst_port_free(
6817                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6818         }
6819         bp->nge_port_cnt = 0;
6820 }
6821
6822 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6823 {
6824         int rc, i;
6825         u32 tpa_flags = 0;
6826
6827         if (set_tpa)
6828                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
6829         for (i = 0; i < bp->nr_vnics; i++) {
6830                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
6831                 if (rc) {
6832                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
6833                                    i, rc);
6834                         return rc;
6835                 }
6836         }
6837         return 0;
6838 }
6839
6840 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
6841 {
6842         int i;
6843
6844         for (i = 0; i < bp->nr_vnics; i++)
6845                 bnxt_hwrm_vnic_set_rss(bp, i, false);
6846 }
6847
6848 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
6849                                     bool irq_re_init)
6850 {
6851         if (bp->vnic_info) {
6852                 bnxt_hwrm_clear_vnic_filter(bp);
6853                 /* clear all RSS setting before free vnic ctx */
6854                 bnxt_hwrm_clear_vnic_rss(bp);
6855                 bnxt_hwrm_vnic_ctx_free(bp);
6856                 /* before free the vnic, undo the vnic tpa settings */
6857                 if (bp->flags & BNXT_FLAG_TPA)
6858                         bnxt_set_tpa(bp, false);
6859                 bnxt_hwrm_vnic_free(bp);
6860         }
6861         bnxt_hwrm_ring_free(bp, close_path);
6862         bnxt_hwrm_ring_grp_free(bp);
6863         if (irq_re_init) {
6864                 bnxt_hwrm_stat_ctx_free(bp);
6865                 bnxt_hwrm_free_tunnel_ports(bp);
6866         }
6867 }
6868
6869 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
6870 {
6871         struct hwrm_func_cfg_input req = {0};
6872         int rc;
6873
6874         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6875         req.fid = cpu_to_le16(0xffff);
6876         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
6877         if (br_mode == BRIDGE_MODE_VEB)
6878                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
6879         else if (br_mode == BRIDGE_MODE_VEPA)
6880                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
6881         else
6882                 return -EINVAL;
6883         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6884         if (rc)
6885                 rc = -EIO;
6886         return rc;
6887 }
6888
6889 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
6890 {
6891         struct hwrm_func_cfg_input req = {0};
6892         int rc;
6893
6894         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
6895                 return 0;
6896
6897         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6898         req.fid = cpu_to_le16(0xffff);
6899         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
6900         req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
6901         if (size == 128)
6902                 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
6903
6904         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6905         if (rc)
6906                 rc = -EIO;
6907         return rc;
6908 }
6909
6910 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
6911 {
6912         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
6913         int rc;
6914
6915         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
6916                 goto skip_rss_ctx;
6917
6918         /* allocate context for vnic */
6919         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
6920         if (rc) {
6921                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
6922                            vnic_id, rc);
6923                 goto vnic_setup_err;
6924         }
6925         bp->rsscos_nr_ctxs++;
6926
6927         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6928                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
6929                 if (rc) {
6930                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
6931                                    vnic_id, rc);
6932                         goto vnic_setup_err;
6933                 }
6934                 bp->rsscos_nr_ctxs++;
6935         }
6936
6937 skip_rss_ctx:
6938         /* configure default vnic, ring grp */
6939         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6940         if (rc) {
6941                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6942                            vnic_id, rc);
6943                 goto vnic_setup_err;
6944         }
6945
6946         /* Enable RSS hashing on vnic */
6947         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
6948         if (rc) {
6949                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
6950                            vnic_id, rc);
6951                 goto vnic_setup_err;
6952         }
6953
6954         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6955                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6956                 if (rc) {
6957                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6958                                    vnic_id, rc);
6959                 }
6960         }
6961
6962 vnic_setup_err:
6963         return rc;
6964 }
6965
6966 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
6967 {
6968         int rc, i, nr_ctxs;
6969
6970         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
6971         for (i = 0; i < nr_ctxs; i++) {
6972                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
6973                 if (rc) {
6974                         netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
6975                                    vnic_id, i, rc);
6976                         break;
6977                 }
6978                 bp->rsscos_nr_ctxs++;
6979         }
6980         if (i < nr_ctxs)
6981                 return -ENOMEM;
6982
6983         rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
6984         if (rc) {
6985                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
6986                            vnic_id, rc);
6987                 return rc;
6988         }
6989         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6990         if (rc) {
6991                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6992                            vnic_id, rc);
6993                 return rc;
6994         }
6995         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6996                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6997                 if (rc) {
6998                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6999                                    vnic_id, rc);
7000                 }
7001         }
7002         return rc;
7003 }
7004
7005 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7006 {
7007         if (bp->flags & BNXT_FLAG_CHIP_P5)
7008                 return __bnxt_setup_vnic_p5(bp, vnic_id);
7009         else
7010                 return __bnxt_setup_vnic(bp, vnic_id);
7011 }
7012
7013 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7014 {
7015 #ifdef CONFIG_RFS_ACCEL
7016         int i, rc = 0;
7017
7018         for (i = 0; i < bp->rx_nr_rings; i++) {
7019                 struct bnxt_vnic_info *vnic;
7020                 u16 vnic_id = i + 1;
7021                 u16 ring_id = i;
7022
7023                 if (vnic_id >= bp->nr_vnics)
7024                         break;
7025
7026                 vnic = &bp->vnic_info[vnic_id];
7027                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7028                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7029                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7030                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7031                 if (rc) {
7032                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7033                                    vnic_id, rc);
7034                         break;
7035                 }
7036                 rc = bnxt_setup_vnic(bp, vnic_id);
7037                 if (rc)
7038                         break;
7039         }
7040         return rc;
7041 #else
7042         return 0;
7043 #endif
7044 }
7045
7046 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7047 static bool bnxt_promisc_ok(struct bnxt *bp)
7048 {
7049 #ifdef CONFIG_BNXT_SRIOV
7050         if (BNXT_VF(bp) && !bp->vf.vlan)
7051                 return false;
7052 #endif
7053         return true;
7054 }
7055
7056 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7057 {
7058         unsigned int rc = 0;
7059
7060         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7061         if (rc) {
7062                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7063                            rc);
7064                 return rc;
7065         }
7066
7067         rc = bnxt_hwrm_vnic_cfg(bp, 1);
7068         if (rc) {
7069                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7070                            rc);
7071                 return rc;
7072         }
7073         return rc;
7074 }
7075
7076 static int bnxt_cfg_rx_mode(struct bnxt *);
7077 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7078
7079 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7080 {
7081         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7082         int rc = 0;
7083         unsigned int rx_nr_rings = bp->rx_nr_rings;
7084
7085         if (irq_re_init) {
7086                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7087                 if (rc) {
7088                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7089                                    rc);
7090                         goto err_out;
7091                 }
7092         }
7093
7094         rc = bnxt_hwrm_ring_alloc(bp);
7095         if (rc) {
7096                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7097                 goto err_out;
7098         }
7099
7100         rc = bnxt_hwrm_ring_grp_alloc(bp);
7101         if (rc) {
7102                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7103                 goto err_out;
7104         }
7105
7106         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7107                 rx_nr_rings--;
7108
7109         /* default vnic 0 */
7110         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7111         if (rc) {
7112                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7113                 goto err_out;
7114         }
7115
7116         rc = bnxt_setup_vnic(bp, 0);
7117         if (rc)
7118                 goto err_out;
7119
7120         if (bp->flags & BNXT_FLAG_RFS) {
7121                 rc = bnxt_alloc_rfs_vnics(bp);
7122                 if (rc)
7123                         goto err_out;
7124         }
7125
7126         if (bp->flags & BNXT_FLAG_TPA) {
7127                 rc = bnxt_set_tpa(bp, true);
7128                 if (rc)
7129                         goto err_out;
7130         }
7131
7132         if (BNXT_VF(bp))
7133                 bnxt_update_vf_mac(bp);
7134
7135         /* Filter for default vnic 0 */
7136         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7137         if (rc) {
7138                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7139                 goto err_out;
7140         }
7141         vnic->uc_filter_count = 1;
7142
7143         vnic->rx_mask = 0;
7144         if (bp->dev->flags & IFF_BROADCAST)
7145                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7146
7147         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7148                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7149
7150         if (bp->dev->flags & IFF_ALLMULTI) {
7151                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7152                 vnic->mc_list_count = 0;
7153         } else {
7154                 u32 mask = 0;
7155
7156                 bnxt_mc_list_updated(bp, &mask);
7157                 vnic->rx_mask |= mask;
7158         }
7159
7160         rc = bnxt_cfg_rx_mode(bp);
7161         if (rc)
7162                 goto err_out;
7163
7164         rc = bnxt_hwrm_set_coal(bp);
7165         if (rc)
7166                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7167                                 rc);
7168
7169         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7170                 rc = bnxt_setup_nitroa0_vnic(bp);
7171                 if (rc)
7172                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7173                                    rc);
7174         }
7175
7176         if (BNXT_VF(bp)) {
7177                 bnxt_hwrm_func_qcfg(bp);
7178                 netdev_update_features(bp->dev);
7179         }
7180
7181         return 0;
7182
7183 err_out:
7184         bnxt_hwrm_resource_free(bp, 0, true);
7185
7186         return rc;
7187 }
7188
7189 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7190 {
7191         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7192         return 0;
7193 }
7194
7195 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7196 {
7197         bnxt_init_cp_rings(bp);
7198         bnxt_init_rx_rings(bp);
7199         bnxt_init_tx_rings(bp);
7200         bnxt_init_ring_grps(bp, irq_re_init);
7201         bnxt_init_vnics(bp);
7202
7203         return bnxt_init_chip(bp, irq_re_init);
7204 }
7205
7206 static int bnxt_set_real_num_queues(struct bnxt *bp)
7207 {
7208         int rc;
7209         struct net_device *dev = bp->dev;
7210
7211         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7212                                           bp->tx_nr_rings_xdp);
7213         if (rc)
7214                 return rc;
7215
7216         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7217         if (rc)
7218                 return rc;
7219
7220 #ifdef CONFIG_RFS_ACCEL
7221         if (bp->flags & BNXT_FLAG_RFS)
7222                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7223 #endif
7224
7225         return rc;
7226 }
7227
7228 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7229                            bool shared)
7230 {
7231         int _rx = *rx, _tx = *tx;
7232
7233         if (shared) {
7234                 *rx = min_t(int, _rx, max);
7235                 *tx = min_t(int, _tx, max);
7236         } else {
7237                 if (max < 2)
7238                         return -ENOMEM;
7239
7240                 while (_rx + _tx > max) {
7241                         if (_rx > _tx && _rx > 1)
7242                                 _rx--;
7243                         else if (_tx > 1)
7244                                 _tx--;
7245                 }
7246                 *rx = _rx;
7247                 *tx = _tx;
7248         }
7249         return 0;
7250 }
7251
7252 static void bnxt_setup_msix(struct bnxt *bp)
7253 {
7254         const int len = sizeof(bp->irq_tbl[0].name);
7255         struct net_device *dev = bp->dev;
7256         int tcs, i;
7257
7258         tcs = netdev_get_num_tc(dev);
7259         if (tcs > 1) {
7260                 int i, off, count;
7261
7262                 for (i = 0; i < tcs; i++) {
7263                         count = bp->tx_nr_rings_per_tc;
7264                         off = i * count;
7265                         netdev_set_tc_queue(dev, i, count, off);
7266                 }
7267         }
7268
7269         for (i = 0; i < bp->cp_nr_rings; i++) {
7270                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7271                 char *attr;
7272
7273                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7274                         attr = "TxRx";
7275                 else if (i < bp->rx_nr_rings)
7276                         attr = "rx";
7277                 else
7278                         attr = "tx";
7279
7280                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7281                          attr, i);
7282                 bp->irq_tbl[map_idx].handler = bnxt_msix;
7283         }
7284 }
7285
7286 static void bnxt_setup_inta(struct bnxt *bp)
7287 {
7288         const int len = sizeof(bp->irq_tbl[0].name);
7289
7290         if (netdev_get_num_tc(bp->dev))
7291                 netdev_reset_tc(bp->dev);
7292
7293         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7294                  0);
7295         bp->irq_tbl[0].handler = bnxt_inta;
7296 }
7297
7298 static int bnxt_setup_int_mode(struct bnxt *bp)
7299 {
7300         int rc;
7301
7302         if (bp->flags & BNXT_FLAG_USING_MSIX)
7303                 bnxt_setup_msix(bp);
7304         else
7305                 bnxt_setup_inta(bp);
7306
7307         rc = bnxt_set_real_num_queues(bp);
7308         return rc;
7309 }
7310
7311 #ifdef CONFIG_RFS_ACCEL
7312 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7313 {
7314         return bp->hw_resc.max_rsscos_ctxs;
7315 }
7316
7317 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7318 {
7319         return bp->hw_resc.max_vnics;
7320 }
7321 #endif
7322
7323 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7324 {
7325         return bp->hw_resc.max_stat_ctxs;
7326 }
7327
7328 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7329 {
7330         return bp->hw_resc.max_cp_rings;
7331 }
7332
7333 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7334 {
7335         unsigned int cp = bp->hw_resc.max_cp_rings;
7336
7337         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7338                 cp -= bnxt_get_ulp_msix_num(bp);
7339
7340         return cp;
7341 }
7342
7343 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7344 {
7345         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7346
7347         if (bp->flags & BNXT_FLAG_CHIP_P5)
7348                 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7349
7350         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7351 }
7352
7353 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7354 {
7355         bp->hw_resc.max_irqs = max_irqs;
7356 }
7357
7358 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7359 {
7360         unsigned int cp;
7361
7362         cp = bnxt_get_max_func_cp_rings_for_en(bp);
7363         if (bp->flags & BNXT_FLAG_CHIP_P5)
7364                 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7365         else
7366                 return cp - bp->cp_nr_rings;
7367 }
7368
7369 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7370 {
7371         unsigned int stat;
7372
7373         stat = bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_ulp_stat_ctxs(bp);
7374         stat -= bp->cp_nr_rings;
7375         return stat;
7376 }
7377
7378 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7379 {
7380         int max_cp = bnxt_get_max_func_cp_rings(bp);
7381         int max_irq = bnxt_get_max_func_irqs(bp);
7382         int total_req = bp->cp_nr_rings + num;
7383         int max_idx, avail_msix;
7384
7385         max_idx = bp->total_irqs;
7386         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7387                 max_idx = min_t(int, bp->total_irqs, max_cp);
7388         avail_msix = max_idx - bp->cp_nr_rings;
7389         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7390                 return avail_msix;
7391
7392         if (max_irq < total_req) {
7393                 num = max_irq - bp->cp_nr_rings;
7394                 if (num <= 0)
7395                         return 0;
7396         }
7397         return num;
7398 }
7399
7400 static int bnxt_get_num_msix(struct bnxt *bp)
7401 {
7402         if (!BNXT_NEW_RM(bp))
7403                 return bnxt_get_max_func_irqs(bp);
7404
7405         return bnxt_nq_rings_in_use(bp);
7406 }
7407
7408 static int bnxt_init_msix(struct bnxt *bp)
7409 {
7410         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7411         struct msix_entry *msix_ent;
7412
7413         total_vecs = bnxt_get_num_msix(bp);
7414         max = bnxt_get_max_func_irqs(bp);
7415         if (total_vecs > max)
7416                 total_vecs = max;
7417
7418         if (!total_vecs)
7419                 return 0;
7420
7421         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7422         if (!msix_ent)
7423                 return -ENOMEM;
7424
7425         for (i = 0; i < total_vecs; i++) {
7426                 msix_ent[i].entry = i;
7427                 msix_ent[i].vector = 0;
7428         }
7429
7430         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7431                 min = 2;
7432
7433         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7434         ulp_msix = bnxt_get_ulp_msix_num(bp);
7435         if (total_vecs < 0 || total_vecs < ulp_msix) {
7436                 rc = -ENODEV;
7437                 goto msix_setup_exit;
7438         }
7439
7440         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7441         if (bp->irq_tbl) {
7442                 for (i = 0; i < total_vecs; i++)
7443                         bp->irq_tbl[i].vector = msix_ent[i].vector;
7444
7445                 bp->total_irqs = total_vecs;
7446                 /* Trim rings based upon num of vectors allocated */
7447                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7448                                      total_vecs - ulp_msix, min == 1);
7449                 if (rc)
7450                         goto msix_setup_exit;
7451
7452                 bp->cp_nr_rings = (min == 1) ?
7453                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7454                                   bp->tx_nr_rings + bp->rx_nr_rings;
7455
7456         } else {
7457                 rc = -ENOMEM;
7458                 goto msix_setup_exit;
7459         }
7460         bp->flags |= BNXT_FLAG_USING_MSIX;
7461         kfree(msix_ent);
7462         return 0;
7463
7464 msix_setup_exit:
7465         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7466         kfree(bp->irq_tbl);
7467         bp->irq_tbl = NULL;
7468         pci_disable_msix(bp->pdev);
7469         kfree(msix_ent);
7470         return rc;
7471 }
7472
7473 static int bnxt_init_inta(struct bnxt *bp)
7474 {
7475         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7476         if (!bp->irq_tbl)
7477                 return -ENOMEM;
7478
7479         bp->total_irqs = 1;
7480         bp->rx_nr_rings = 1;
7481         bp->tx_nr_rings = 1;
7482         bp->cp_nr_rings = 1;
7483         bp->flags |= BNXT_FLAG_SHARED_RINGS;
7484         bp->irq_tbl[0].vector = bp->pdev->irq;
7485         return 0;
7486 }
7487
7488 static int bnxt_init_int_mode(struct bnxt *bp)
7489 {
7490         int rc = 0;
7491
7492         if (bp->flags & BNXT_FLAG_MSIX_CAP)
7493                 rc = bnxt_init_msix(bp);
7494
7495         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7496                 /* fallback to INTA */
7497                 rc = bnxt_init_inta(bp);
7498         }
7499         return rc;
7500 }
7501
7502 static void bnxt_clear_int_mode(struct bnxt *bp)
7503 {
7504         if (bp->flags & BNXT_FLAG_USING_MSIX)
7505                 pci_disable_msix(bp->pdev);
7506
7507         kfree(bp->irq_tbl);
7508         bp->irq_tbl = NULL;
7509         bp->flags &= ~BNXT_FLAG_USING_MSIX;
7510 }
7511
7512 int bnxt_reserve_rings(struct bnxt *bp)
7513 {
7514         int tcs = netdev_get_num_tc(bp->dev);
7515         bool reinit_irq = false;
7516         int rc;
7517
7518         if (!bnxt_need_reserve_rings(bp))
7519                 return 0;
7520
7521         if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
7522                 bnxt_ulp_irq_stop(bp);
7523                 bnxt_clear_int_mode(bp);
7524                 reinit_irq = true;
7525         }
7526         rc = __bnxt_reserve_rings(bp);
7527         if (reinit_irq) {
7528                 if (!rc)
7529                         rc = bnxt_init_int_mode(bp);
7530                 bnxt_ulp_irq_restart(bp, rc);
7531         }
7532         if (rc) {
7533                 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7534                 return rc;
7535         }
7536         if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7537                 netdev_err(bp->dev, "tx ring reservation failure\n");
7538                 netdev_reset_tc(bp->dev);
7539                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7540                 return -ENOMEM;
7541         }
7542         return 0;
7543 }
7544
7545 static void bnxt_free_irq(struct bnxt *bp)
7546 {
7547         struct bnxt_irq *irq;
7548         int i;
7549
7550 #ifdef CONFIG_RFS_ACCEL
7551         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7552         bp->dev->rx_cpu_rmap = NULL;
7553 #endif
7554         if (!bp->irq_tbl || !bp->bnapi)
7555                 return;
7556
7557         for (i = 0; i < bp->cp_nr_rings; i++) {
7558                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7559
7560                 irq = &bp->irq_tbl[map_idx];
7561                 if (irq->requested) {
7562                         if (irq->have_cpumask) {
7563                                 irq_set_affinity_hint(irq->vector, NULL);
7564                                 free_cpumask_var(irq->cpu_mask);
7565                                 irq->have_cpumask = 0;
7566                         }
7567                         free_irq(irq->vector, bp->bnapi[i]);
7568                 }
7569
7570                 irq->requested = 0;
7571         }
7572 }
7573
7574 static int bnxt_request_irq(struct bnxt *bp)
7575 {
7576         int i, j, rc = 0;
7577         unsigned long flags = 0;
7578 #ifdef CONFIG_RFS_ACCEL
7579         struct cpu_rmap *rmap;
7580 #endif
7581
7582         rc = bnxt_setup_int_mode(bp);
7583         if (rc) {
7584                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7585                            rc);
7586                 return rc;
7587         }
7588 #ifdef CONFIG_RFS_ACCEL
7589         rmap = bp->dev->rx_cpu_rmap;
7590 #endif
7591         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7592                 flags = IRQF_SHARED;
7593
7594         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7595                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7596                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7597
7598 #ifdef CONFIG_RFS_ACCEL
7599                 if (rmap && bp->bnapi[i]->rx_ring) {
7600                         rc = irq_cpu_rmap_add(rmap, irq->vector);
7601                         if (rc)
7602                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7603                                             j);
7604                         j++;
7605                 }
7606 #endif
7607                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7608                                  bp->bnapi[i]);
7609                 if (rc)
7610                         break;
7611
7612                 irq->requested = 1;
7613
7614                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7615                         int numa_node = dev_to_node(&bp->pdev->dev);
7616
7617                         irq->have_cpumask = 1;
7618                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7619                                         irq->cpu_mask);
7620                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7621                         if (rc) {
7622                                 netdev_warn(bp->dev,
7623                                             "Set affinity failed, IRQ = %d\n",
7624                                             irq->vector);
7625                                 break;
7626                         }
7627                 }
7628         }
7629         return rc;
7630 }
7631
7632 static void bnxt_del_napi(struct bnxt *bp)
7633 {
7634         int i;
7635
7636         if (!bp->bnapi)
7637                 return;
7638
7639         for (i = 0; i < bp->cp_nr_rings; i++) {
7640                 struct bnxt_napi *bnapi = bp->bnapi[i];
7641
7642                 napi_hash_del(&bnapi->napi);
7643                 netif_napi_del(&bnapi->napi);
7644         }
7645         /* We called napi_hash_del() before netif_napi_del(), we need
7646          * to respect an RCU grace period before freeing napi structures.
7647          */
7648         synchronize_net();
7649 }
7650
7651 static void bnxt_init_napi(struct bnxt *bp)
7652 {
7653         int i;
7654         unsigned int cp_nr_rings = bp->cp_nr_rings;
7655         struct bnxt_napi *bnapi;
7656
7657         if (bp->flags & BNXT_FLAG_USING_MSIX) {
7658                 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7659
7660                 if (bp->flags & BNXT_FLAG_CHIP_P5)
7661                         poll_fn = bnxt_poll_p5;
7662                 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7663                         cp_nr_rings--;
7664                 for (i = 0; i < cp_nr_rings; i++) {
7665                         bnapi = bp->bnapi[i];
7666                         netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7667                 }
7668                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7669                         bnapi = bp->bnapi[cp_nr_rings];
7670                         netif_napi_add(bp->dev, &bnapi->napi,
7671                                        bnxt_poll_nitroa0, 64);
7672                 }
7673         } else {
7674                 bnapi = bp->bnapi[0];
7675                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7676         }
7677 }
7678
7679 static void bnxt_disable_napi(struct bnxt *bp)
7680 {
7681         int i;
7682
7683         if (!bp->bnapi)
7684                 return;
7685
7686         for (i = 0; i < bp->cp_nr_rings; i++) {
7687                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7688
7689                 if (bp->bnapi[i]->rx_ring)
7690                         cancel_work_sync(&cpr->dim.work);
7691
7692                 napi_disable(&bp->bnapi[i]->napi);
7693         }
7694 }
7695
7696 static void bnxt_enable_napi(struct bnxt *bp)
7697 {
7698         int i;
7699
7700         for (i = 0; i < bp->cp_nr_rings; i++) {
7701                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7702                 bp->bnapi[i]->in_reset = false;
7703
7704                 if (bp->bnapi[i]->rx_ring) {
7705                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7706                         cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7707                 }
7708                 napi_enable(&bp->bnapi[i]->napi);
7709         }
7710 }
7711
7712 void bnxt_tx_disable(struct bnxt *bp)
7713 {
7714         int i;
7715         struct bnxt_tx_ring_info *txr;
7716
7717         if (bp->tx_ring) {
7718                 for (i = 0; i < bp->tx_nr_rings; i++) {
7719                         txr = &bp->tx_ring[i];
7720                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
7721                 }
7722         }
7723         /* Stop all TX queues */
7724         netif_tx_disable(bp->dev);
7725         netif_carrier_off(bp->dev);
7726 }
7727
7728 void bnxt_tx_enable(struct bnxt *bp)
7729 {
7730         int i;
7731         struct bnxt_tx_ring_info *txr;
7732
7733         for (i = 0; i < bp->tx_nr_rings; i++) {
7734                 txr = &bp->tx_ring[i];
7735                 txr->dev_state = 0;
7736         }
7737         netif_tx_wake_all_queues(bp->dev);
7738         if (bp->link_info.link_up)
7739                 netif_carrier_on(bp->dev);
7740 }
7741
7742 static void bnxt_report_link(struct bnxt *bp)
7743 {
7744         if (bp->link_info.link_up) {
7745                 const char *duplex;
7746                 const char *flow_ctrl;
7747                 u32 speed;
7748                 u16 fec;
7749
7750                 netif_carrier_on(bp->dev);
7751                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7752                         duplex = "full";
7753                 else
7754                         duplex = "half";
7755                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7756                         flow_ctrl = "ON - receive & transmit";
7757                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7758                         flow_ctrl = "ON - transmit";
7759                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7760                         flow_ctrl = "ON - receive";
7761                 else
7762                         flow_ctrl = "none";
7763                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7764                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7765                             speed, duplex, flow_ctrl);
7766                 if (bp->flags & BNXT_FLAG_EEE_CAP)
7767                         netdev_info(bp->dev, "EEE is %s\n",
7768                                     bp->eee.eee_active ? "active" :
7769                                                          "not active");
7770                 fec = bp->link_info.fec_cfg;
7771                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7772                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7773                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7774                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7775                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7776         } else {
7777                 netif_carrier_off(bp->dev);
7778                 netdev_err(bp->dev, "NIC Link is Down\n");
7779         }
7780 }
7781
7782 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7783 {
7784         int rc = 0;
7785         struct hwrm_port_phy_qcaps_input req = {0};
7786         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7787         struct bnxt_link_info *link_info = &bp->link_info;
7788
7789         if (bp->hwrm_spec_code < 0x10201)
7790                 return 0;
7791
7792         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7793
7794         mutex_lock(&bp->hwrm_cmd_lock);
7795         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7796         if (rc)
7797                 goto hwrm_phy_qcaps_exit;
7798
7799         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7800                 struct ethtool_eee *eee = &bp->eee;
7801                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7802
7803                 bp->flags |= BNXT_FLAG_EEE_CAP;
7804                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7805                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7806                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7807                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7808                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7809         }
7810         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7811                 if (bp->test_info)
7812                         bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7813         }
7814         if (resp->supported_speeds_auto_mode)
7815                 link_info->support_auto_speeds =
7816                         le16_to_cpu(resp->supported_speeds_auto_mode);
7817
7818         bp->port_count = resp->port_cnt;
7819
7820 hwrm_phy_qcaps_exit:
7821         mutex_unlock(&bp->hwrm_cmd_lock);
7822         return rc;
7823 }
7824
7825 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7826 {
7827         int rc = 0;
7828         struct bnxt_link_info *link_info = &bp->link_info;
7829         struct hwrm_port_phy_qcfg_input req = {0};
7830         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7831         u8 link_up = link_info->link_up;
7832         u16 diff;
7833
7834         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
7835
7836         mutex_lock(&bp->hwrm_cmd_lock);
7837         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7838         if (rc) {
7839                 mutex_unlock(&bp->hwrm_cmd_lock);
7840                 return rc;
7841         }
7842
7843         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
7844         link_info->phy_link_status = resp->link;
7845         link_info->duplex = resp->duplex_cfg;
7846         if (bp->hwrm_spec_code >= 0x10800)
7847                 link_info->duplex = resp->duplex_state;
7848         link_info->pause = resp->pause;
7849         link_info->auto_mode = resp->auto_mode;
7850         link_info->auto_pause_setting = resp->auto_pause;
7851         link_info->lp_pause = resp->link_partner_adv_pause;
7852         link_info->force_pause_setting = resp->force_pause;
7853         link_info->duplex_setting = resp->duplex_cfg;
7854         if (link_info->phy_link_status == BNXT_LINK_LINK)
7855                 link_info->link_speed = le16_to_cpu(resp->link_speed);
7856         else
7857                 link_info->link_speed = 0;
7858         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
7859         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
7860         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
7861         link_info->lp_auto_link_speeds =
7862                 le16_to_cpu(resp->link_partner_adv_speeds);
7863         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
7864         link_info->phy_ver[0] = resp->phy_maj;
7865         link_info->phy_ver[1] = resp->phy_min;
7866         link_info->phy_ver[2] = resp->phy_bld;
7867         link_info->media_type = resp->media_type;
7868         link_info->phy_type = resp->phy_type;
7869         link_info->transceiver = resp->xcvr_pkg_type;
7870         link_info->phy_addr = resp->eee_config_phy_addr &
7871                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
7872         link_info->module_status = resp->module_status;
7873
7874         if (bp->flags & BNXT_FLAG_EEE_CAP) {
7875                 struct ethtool_eee *eee = &bp->eee;
7876                 u16 fw_speeds;
7877
7878                 eee->eee_active = 0;
7879                 if (resp->eee_config_phy_addr &
7880                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
7881                         eee->eee_active = 1;
7882                         fw_speeds = le16_to_cpu(
7883                                 resp->link_partner_adv_eee_link_speed_mask);
7884                         eee->lp_advertised =
7885                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7886                 }
7887
7888                 /* Pull initial EEE config */
7889                 if (!chng_link_state) {
7890                         if (resp->eee_config_phy_addr &
7891                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
7892                                 eee->eee_enabled = 1;
7893
7894                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
7895                         eee->advertised =
7896                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7897
7898                         if (resp->eee_config_phy_addr &
7899                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
7900                                 __le32 tmr;
7901
7902                                 eee->tx_lpi_enabled = 1;
7903                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
7904                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
7905                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
7906                         }
7907                 }
7908         }
7909
7910         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
7911         if (bp->hwrm_spec_code >= 0x10504)
7912                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
7913
7914         /* TODO: need to add more logic to report VF link */
7915         if (chng_link_state) {
7916                 if (link_info->phy_link_status == BNXT_LINK_LINK)
7917                         link_info->link_up = 1;
7918                 else
7919                         link_info->link_up = 0;
7920                 if (link_up != link_info->link_up)
7921                         bnxt_report_link(bp);
7922         } else {
7923                 /* alwasy link down if not require to update link state */
7924                 link_info->link_up = 0;
7925         }
7926         mutex_unlock(&bp->hwrm_cmd_lock);
7927
7928         if (!BNXT_SINGLE_PF(bp))
7929                 return 0;
7930
7931         diff = link_info->support_auto_speeds ^ link_info->advertising;
7932         if ((link_info->support_auto_speeds | diff) !=
7933             link_info->support_auto_speeds) {
7934                 /* An advertised speed is no longer supported, so we need to
7935                  * update the advertisement settings.  Caller holds RTNL
7936                  * so we can modify link settings.
7937                  */
7938                 link_info->advertising = link_info->support_auto_speeds;
7939                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
7940                         bnxt_hwrm_set_link_setting(bp, true, false);
7941         }
7942         return 0;
7943 }
7944
7945 static void bnxt_get_port_module_status(struct bnxt *bp)
7946 {
7947         struct bnxt_link_info *link_info = &bp->link_info;
7948         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
7949         u8 module_status;
7950
7951         if (bnxt_update_link(bp, true))
7952                 return;
7953
7954         module_status = link_info->module_status;
7955         switch (module_status) {
7956         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
7957         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
7958         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
7959                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
7960                             bp->pf.port_id);
7961                 if (bp->hwrm_spec_code >= 0x10201) {
7962                         netdev_warn(bp->dev, "Module part number %s\n",
7963                                     resp->phy_vendor_partnumber);
7964                 }
7965                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
7966                         netdev_warn(bp->dev, "TX is disabled\n");
7967                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
7968                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
7969         }
7970 }
7971
7972 static void
7973 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
7974 {
7975         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
7976                 if (bp->hwrm_spec_code >= 0x10201)
7977                         req->auto_pause =
7978                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
7979                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7980                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
7981                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
7982                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
7983                 req->enables |=
7984                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7985         } else {
7986                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7987                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
7988                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
7989                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
7990                 req->enables |=
7991                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
7992                 if (bp->hwrm_spec_code >= 0x10201) {
7993                         req->auto_pause = req->force_pause;
7994                         req->enables |= cpu_to_le32(
7995                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7996                 }
7997         }
7998 }
7999
8000 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
8001                                       struct hwrm_port_phy_cfg_input *req)
8002 {
8003         u8 autoneg = bp->link_info.autoneg;
8004         u16 fw_link_speed = bp->link_info.req_link_speed;
8005         u16 advertising = bp->link_info.advertising;
8006
8007         if (autoneg & BNXT_AUTONEG_SPEED) {
8008                 req->auto_mode |=
8009                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
8010
8011                 req->enables |= cpu_to_le32(
8012                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8013                 req->auto_link_speed_mask = cpu_to_le16(advertising);
8014
8015                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8016                 req->flags |=
8017                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8018         } else {
8019                 req->force_link_speed = cpu_to_le16(fw_link_speed);
8020                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8021         }
8022
8023         /* tell chimp that the setting takes effect immediately */
8024         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8025 }
8026
8027 int bnxt_hwrm_set_pause(struct bnxt *bp)
8028 {
8029         struct hwrm_port_phy_cfg_input req = {0};
8030         int rc;
8031
8032         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8033         bnxt_hwrm_set_pause_common(bp, &req);
8034
8035         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8036             bp->link_info.force_link_chng)
8037                 bnxt_hwrm_set_link_common(bp, &req);
8038
8039         mutex_lock(&bp->hwrm_cmd_lock);
8040         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8041         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8042                 /* since changing of pause setting doesn't trigger any link
8043                  * change event, the driver needs to update the current pause
8044                  * result upon successfully return of the phy_cfg command
8045                  */
8046                 bp->link_info.pause =
8047                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8048                 bp->link_info.auto_pause_setting = 0;
8049                 if (!bp->link_info.force_link_chng)
8050                         bnxt_report_link(bp);
8051         }
8052         bp->link_info.force_link_chng = false;
8053         mutex_unlock(&bp->hwrm_cmd_lock);
8054         return rc;
8055 }
8056
8057 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8058                               struct hwrm_port_phy_cfg_input *req)
8059 {
8060         struct ethtool_eee *eee = &bp->eee;
8061
8062         if (eee->eee_enabled) {
8063                 u16 eee_speeds;
8064                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8065
8066                 if (eee->tx_lpi_enabled)
8067                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8068                 else
8069                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8070
8071                 req->flags |= cpu_to_le32(flags);
8072                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8073                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8074                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8075         } else {
8076                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8077         }
8078 }
8079
8080 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8081 {
8082         struct hwrm_port_phy_cfg_input req = {0};
8083
8084         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8085         if (set_pause)
8086                 bnxt_hwrm_set_pause_common(bp, &req);
8087
8088         bnxt_hwrm_set_link_common(bp, &req);
8089
8090         if (set_eee)
8091                 bnxt_hwrm_set_eee(bp, &req);
8092         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8093 }
8094
8095 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8096 {
8097         struct hwrm_port_phy_cfg_input req = {0};
8098
8099         if (!BNXT_SINGLE_PF(bp))
8100                 return 0;
8101
8102         if (pci_num_vf(bp->pdev))
8103                 return 0;
8104
8105         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8106         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8107         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8108 }
8109
8110 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8111 {
8112         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8113         struct hwrm_func_drv_if_change_input req = {0};
8114         bool resc_reinit = false;
8115         int rc;
8116
8117         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8118                 return 0;
8119
8120         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8121         if (up)
8122                 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8123         mutex_lock(&bp->hwrm_cmd_lock);
8124         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8125         if (!rc && (resp->flags &
8126                     cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8127                 resc_reinit = true;
8128         mutex_unlock(&bp->hwrm_cmd_lock);
8129
8130         if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8131                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8132
8133                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8134                 hw_resc->resv_cp_rings = 0;
8135                 hw_resc->resv_stat_ctxs = 0;
8136                 hw_resc->resv_irqs = 0;
8137                 hw_resc->resv_tx_rings = 0;
8138                 hw_resc->resv_rx_rings = 0;
8139                 hw_resc->resv_hw_ring_grps = 0;
8140                 hw_resc->resv_vnics = 0;
8141                 bp->tx_nr_rings = 0;
8142                 bp->rx_nr_rings = 0;
8143         }
8144         return rc;
8145 }
8146
8147 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8148 {
8149         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8150         struct hwrm_port_led_qcaps_input req = {0};
8151         struct bnxt_pf_info *pf = &bp->pf;
8152         int rc;
8153
8154         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8155                 return 0;
8156
8157         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8158         req.port_id = cpu_to_le16(pf->port_id);
8159         mutex_lock(&bp->hwrm_cmd_lock);
8160         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8161         if (rc) {
8162                 mutex_unlock(&bp->hwrm_cmd_lock);
8163                 return rc;
8164         }
8165         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8166                 int i;
8167
8168                 bp->num_leds = resp->num_leds;
8169                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8170                                                  bp->num_leds);
8171                 for (i = 0; i < bp->num_leds; i++) {
8172                         struct bnxt_led_info *led = &bp->leds[i];
8173                         __le16 caps = led->led_state_caps;
8174
8175                         if (!led->led_group_id ||
8176                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
8177                                 bp->num_leds = 0;
8178                                 break;
8179                         }
8180                 }
8181         }
8182         mutex_unlock(&bp->hwrm_cmd_lock);
8183         return 0;
8184 }
8185
8186 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8187 {
8188         struct hwrm_wol_filter_alloc_input req = {0};
8189         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8190         int rc;
8191
8192         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8193         req.port_id = cpu_to_le16(bp->pf.port_id);
8194         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8195         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8196         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8197         mutex_lock(&bp->hwrm_cmd_lock);
8198         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8199         if (!rc)
8200                 bp->wol_filter_id = resp->wol_filter_id;
8201         mutex_unlock(&bp->hwrm_cmd_lock);
8202         return rc;
8203 }
8204
8205 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8206 {
8207         struct hwrm_wol_filter_free_input req = {0};
8208         int rc;
8209
8210         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8211         req.port_id = cpu_to_le16(bp->pf.port_id);
8212         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8213         req.wol_filter_id = bp->wol_filter_id;
8214         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8215         return rc;
8216 }
8217
8218 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8219 {
8220         struct hwrm_wol_filter_qcfg_input req = {0};
8221         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8222         u16 next_handle = 0;
8223         int rc;
8224
8225         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8226         req.port_id = cpu_to_le16(bp->pf.port_id);
8227         req.handle = cpu_to_le16(handle);
8228         mutex_lock(&bp->hwrm_cmd_lock);
8229         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8230         if (!rc) {
8231                 next_handle = le16_to_cpu(resp->next_handle);
8232                 if (next_handle != 0) {
8233                         if (resp->wol_type ==
8234                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8235                                 bp->wol = 1;
8236                                 bp->wol_filter_id = resp->wol_filter_id;
8237                         }
8238                 }
8239         }
8240         mutex_unlock(&bp->hwrm_cmd_lock);
8241         return next_handle;
8242 }
8243
8244 static void bnxt_get_wol_settings(struct bnxt *bp)
8245 {
8246         u16 handle = 0;
8247
8248         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8249                 return;
8250
8251         do {
8252                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8253         } while (handle && handle != 0xffff);
8254 }
8255
8256 #ifdef CONFIG_BNXT_HWMON
8257 static ssize_t bnxt_show_temp(struct device *dev,
8258                               struct device_attribute *devattr, char *buf)
8259 {
8260         struct hwrm_temp_monitor_query_input req = {0};
8261         struct hwrm_temp_monitor_query_output *resp;
8262         struct bnxt *bp = dev_get_drvdata(dev);
8263         u32 temp = 0;
8264
8265         resp = bp->hwrm_cmd_resp_addr;
8266         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8267         mutex_lock(&bp->hwrm_cmd_lock);
8268         if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8269                 temp = resp->temp * 1000; /* display millidegree */
8270         mutex_unlock(&bp->hwrm_cmd_lock);
8271
8272         return sprintf(buf, "%u\n", temp);
8273 }
8274 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8275
8276 static struct attribute *bnxt_attrs[] = {
8277         &sensor_dev_attr_temp1_input.dev_attr.attr,
8278         NULL
8279 };
8280 ATTRIBUTE_GROUPS(bnxt);
8281
8282 static void bnxt_hwmon_close(struct bnxt *bp)
8283 {
8284         if (bp->hwmon_dev) {
8285                 hwmon_device_unregister(bp->hwmon_dev);
8286                 bp->hwmon_dev = NULL;
8287         }
8288 }
8289
8290 static void bnxt_hwmon_open(struct bnxt *bp)
8291 {
8292         struct pci_dev *pdev = bp->pdev;
8293
8294         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8295                                                           DRV_MODULE_NAME, bp,
8296                                                           bnxt_groups);
8297         if (IS_ERR(bp->hwmon_dev)) {
8298                 bp->hwmon_dev = NULL;
8299                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8300         }
8301 }
8302 #else
8303 static void bnxt_hwmon_close(struct bnxt *bp)
8304 {
8305 }
8306
8307 static void bnxt_hwmon_open(struct bnxt *bp)
8308 {
8309 }
8310 #endif
8311
8312 static bool bnxt_eee_config_ok(struct bnxt *bp)
8313 {
8314         struct ethtool_eee *eee = &bp->eee;
8315         struct bnxt_link_info *link_info = &bp->link_info;
8316
8317         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8318                 return true;
8319
8320         if (eee->eee_enabled) {
8321                 u32 advertising =
8322                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8323
8324                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8325                         eee->eee_enabled = 0;
8326                         return false;
8327                 }
8328                 if (eee->advertised & ~advertising) {
8329                         eee->advertised = advertising & eee->supported;
8330                         return false;
8331                 }
8332         }
8333         return true;
8334 }
8335
8336 static int bnxt_update_phy_setting(struct bnxt *bp)
8337 {
8338         int rc;
8339         bool update_link = false;
8340         bool update_pause = false;
8341         bool update_eee = false;
8342         struct bnxt_link_info *link_info = &bp->link_info;
8343
8344         rc = bnxt_update_link(bp, true);
8345         if (rc) {
8346                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8347                            rc);
8348                 return rc;
8349         }
8350         if (!BNXT_SINGLE_PF(bp))
8351                 return 0;
8352
8353         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8354             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8355             link_info->req_flow_ctrl)
8356                 update_pause = true;
8357         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8358             link_info->force_pause_setting != link_info->req_flow_ctrl)
8359                 update_pause = true;
8360         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8361                 if (BNXT_AUTO_MODE(link_info->auto_mode))
8362                         update_link = true;
8363                 if (link_info->req_link_speed != link_info->force_link_speed)
8364                         update_link = true;
8365                 if (link_info->req_duplex != link_info->duplex_setting)
8366                         update_link = true;
8367         } else {
8368                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8369                         update_link = true;
8370                 if (link_info->advertising != link_info->auto_link_speeds)
8371                         update_link = true;
8372         }
8373
8374         /* The last close may have shutdown the link, so need to call
8375          * PHY_CFG to bring it back up.
8376          */
8377         if (!netif_carrier_ok(bp->dev))
8378                 update_link = true;
8379
8380         if (!bnxt_eee_config_ok(bp))
8381                 update_eee = true;
8382
8383         if (update_link)
8384                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8385         else if (update_pause)
8386                 rc = bnxt_hwrm_set_pause(bp);
8387         if (rc) {
8388                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8389                            rc);
8390                 return rc;
8391         }
8392
8393         return rc;
8394 }
8395
8396 /* Common routine to pre-map certain register block to different GRC window.
8397  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8398  * in PF and 3 windows in VF that can be customized to map in different
8399  * register blocks.
8400  */
8401 static void bnxt_preset_reg_win(struct bnxt *bp)
8402 {
8403         if (BNXT_PF(bp)) {
8404                 /* CAG registers map to GRC window #4 */
8405                 writel(BNXT_CAG_REG_BASE,
8406                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8407         }
8408 }
8409
8410 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8411
8412 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8413 {
8414         int rc = 0;
8415
8416         bnxt_preset_reg_win(bp);
8417         netif_carrier_off(bp->dev);
8418         if (irq_re_init) {
8419                 /* Reserve rings now if none were reserved at driver probe. */
8420                 rc = bnxt_init_dflt_ring_mode(bp);
8421                 if (rc) {
8422                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8423                         return rc;
8424                 }
8425         }
8426         rc = bnxt_reserve_rings(bp);
8427         if (rc)
8428                 return rc;
8429         if ((bp->flags & BNXT_FLAG_RFS) &&
8430             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8431                 /* disable RFS if falling back to INTA */
8432                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8433                 bp->flags &= ~BNXT_FLAG_RFS;
8434         }
8435
8436         rc = bnxt_alloc_mem(bp, irq_re_init);
8437         if (rc) {
8438                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8439                 goto open_err_free_mem;
8440         }
8441
8442         if (irq_re_init) {
8443                 bnxt_init_napi(bp);
8444                 rc = bnxt_request_irq(bp);
8445                 if (rc) {
8446                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8447                         goto open_err_irq;
8448                 }
8449         }
8450
8451         bnxt_enable_napi(bp);
8452         bnxt_debug_dev_init(bp);
8453
8454         rc = bnxt_init_nic(bp, irq_re_init);
8455         if (rc) {
8456                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8457                 goto open_err;
8458         }
8459
8460         if (link_re_init) {
8461                 mutex_lock(&bp->link_lock);
8462                 rc = bnxt_update_phy_setting(bp);
8463                 mutex_unlock(&bp->link_lock);
8464                 if (rc) {
8465                         netdev_warn(bp->dev, "failed to update phy settings\n");
8466                         if (BNXT_SINGLE_PF(bp)) {
8467                                 bp->link_info.phy_retry = true;
8468                                 bp->link_info.phy_retry_expires =
8469                                         jiffies + 5 * HZ;
8470                         }
8471                 }
8472         }
8473
8474         if (irq_re_init)
8475                 udp_tunnel_get_rx_info(bp->dev);
8476
8477         set_bit(BNXT_STATE_OPEN, &bp->state);
8478         bnxt_enable_int(bp);
8479         /* Enable TX queues */
8480         bnxt_tx_enable(bp);
8481         mod_timer(&bp->timer, jiffies + bp->current_interval);
8482         /* Poll link status and check for SFP+ module status */
8483         bnxt_get_port_module_status(bp);
8484
8485         /* VF-reps may need to be re-opened after the PF is re-opened */
8486         if (BNXT_PF(bp))
8487                 bnxt_vf_reps_open(bp);
8488         return 0;
8489
8490 open_err:
8491         bnxt_debug_dev_exit(bp);
8492         bnxt_disable_napi(bp);
8493
8494 open_err_irq:
8495         bnxt_del_napi(bp);
8496
8497 open_err_free_mem:
8498         bnxt_free_skbs(bp);
8499         bnxt_free_irq(bp);
8500         bnxt_free_mem(bp, true);
8501         return rc;
8502 }
8503
8504 /* rtnl_lock held */
8505 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8506 {
8507         int rc = 0;
8508
8509         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8510         if (rc) {
8511                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8512                 dev_close(bp->dev);
8513         }
8514         return rc;
8515 }
8516
8517 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8518  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
8519  * self tests.
8520  */
8521 int bnxt_half_open_nic(struct bnxt *bp)
8522 {
8523         int rc = 0;
8524
8525         rc = bnxt_alloc_mem(bp, false);
8526         if (rc) {
8527                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8528                 goto half_open_err;
8529         }
8530         rc = bnxt_init_nic(bp, false);
8531         if (rc) {
8532                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8533                 goto half_open_err;
8534         }
8535         return 0;
8536
8537 half_open_err:
8538         bnxt_free_skbs(bp);
8539         bnxt_free_mem(bp, false);
8540         dev_close(bp->dev);
8541         return rc;
8542 }
8543
8544 /* rtnl_lock held, this call can only be made after a previous successful
8545  * call to bnxt_half_open_nic().
8546  */
8547 void bnxt_half_close_nic(struct bnxt *bp)
8548 {
8549         bnxt_hwrm_resource_free(bp, false, false);
8550         bnxt_free_skbs(bp);
8551         bnxt_free_mem(bp, false);
8552 }
8553
8554 static int bnxt_open(struct net_device *dev)
8555 {
8556         struct bnxt *bp = netdev_priv(dev);
8557         int rc;
8558
8559         bnxt_hwrm_if_change(bp, true);
8560         rc = __bnxt_open_nic(bp, true, true);
8561         if (rc)
8562                 bnxt_hwrm_if_change(bp, false);
8563
8564         bnxt_hwmon_open(bp);
8565
8566         return rc;
8567 }
8568
8569 static bool bnxt_drv_busy(struct bnxt *bp)
8570 {
8571         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8572                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8573 }
8574
8575 static void bnxt_get_ring_stats(struct bnxt *bp,
8576                                 struct rtnl_link_stats64 *stats);
8577
8578 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8579                              bool link_re_init)
8580 {
8581         /* Close the VF-reps before closing PF */
8582         if (BNXT_PF(bp))
8583                 bnxt_vf_reps_close(bp);
8584
8585         /* Change device state to avoid TX queue wake up's */
8586         bnxt_tx_disable(bp);
8587
8588         clear_bit(BNXT_STATE_OPEN, &bp->state);
8589         smp_mb__after_atomic();
8590         while (bnxt_drv_busy(bp))
8591                 msleep(20);
8592
8593         /* Flush rings and and disable interrupts */
8594         bnxt_shutdown_nic(bp, irq_re_init);
8595
8596         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8597
8598         bnxt_debug_dev_exit(bp);
8599         bnxt_disable_napi(bp);
8600         del_timer_sync(&bp->timer);
8601         bnxt_free_skbs(bp);
8602
8603         /* Save ring stats before shutdown */
8604         if (bp->bnapi)
8605                 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8606         if (irq_re_init) {
8607                 bnxt_free_irq(bp);
8608                 bnxt_del_napi(bp);
8609         }
8610         bnxt_free_mem(bp, irq_re_init);
8611 }
8612
8613 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8614 {
8615         int rc = 0;
8616
8617 #ifdef CONFIG_BNXT_SRIOV
8618         if (bp->sriov_cfg) {
8619                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8620                                                       !bp->sriov_cfg,
8621                                                       BNXT_SRIOV_CFG_WAIT_TMO);
8622                 if (rc)
8623                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8624         }
8625 #endif
8626         __bnxt_close_nic(bp, irq_re_init, link_re_init);
8627         return rc;
8628 }
8629
8630 static int bnxt_close(struct net_device *dev)
8631 {
8632         struct bnxt *bp = netdev_priv(dev);
8633
8634         bnxt_hwmon_close(bp);
8635         bnxt_close_nic(bp, true, true);
8636         bnxt_hwrm_shutdown_link(bp);
8637         bnxt_hwrm_if_change(bp, false);
8638         return 0;
8639 }
8640
8641 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
8642                                    u16 *val)
8643 {
8644         struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
8645         struct hwrm_port_phy_mdio_read_input req = {0};
8646         int rc;
8647
8648         if (bp->hwrm_spec_code < 0x10a00)
8649                 return -EOPNOTSUPP;
8650
8651         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
8652         req.port_id = cpu_to_le16(bp->pf.port_id);
8653         req.phy_addr = phy_addr;
8654         req.reg_addr = cpu_to_le16(reg & 0x1f);
8655         if (bp->link_info.support_speeds & BNXT_LINK_SPEED_MSK_10GB) {
8656                 req.cl45_mdio = 1;
8657                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8658                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8659                 req.reg_addr = cpu_to_le16(reg);
8660         }
8661
8662         mutex_lock(&bp->hwrm_cmd_lock);
8663         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8664         if (!rc)
8665                 *val = le16_to_cpu(resp->reg_data);
8666         mutex_unlock(&bp->hwrm_cmd_lock);
8667         return rc;
8668 }
8669
8670 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
8671                                     u16 val)
8672 {
8673         struct hwrm_port_phy_mdio_write_input req = {0};
8674
8675         if (bp->hwrm_spec_code < 0x10a00)
8676                 return -EOPNOTSUPP;
8677
8678         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
8679         req.port_id = cpu_to_le16(bp->pf.port_id);
8680         req.phy_addr = phy_addr;
8681         req.reg_addr = cpu_to_le16(reg & 0x1f);
8682         if (bp->link_info.support_speeds & BNXT_LINK_SPEED_MSK_10GB) {
8683                 req.cl45_mdio = 1;
8684                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8685                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8686                 req.reg_addr = cpu_to_le16(reg);
8687         }
8688         req.reg_data = cpu_to_le16(val);
8689
8690         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8691 }
8692
8693 /* rtnl_lock held */
8694 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8695 {
8696         struct mii_ioctl_data *mdio = if_mii(ifr);
8697         struct bnxt *bp = netdev_priv(dev);
8698         int rc;
8699
8700         switch (cmd) {
8701         case SIOCGMIIPHY:
8702                 mdio->phy_id = bp->link_info.phy_addr;
8703
8704                 /* fallthru */
8705         case SIOCGMIIREG: {
8706                 u16 mii_regval = 0;
8707
8708                 if (!netif_running(dev))
8709                         return -EAGAIN;
8710
8711                 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
8712                                              &mii_regval);
8713                 mdio->val_out = mii_regval;
8714                 return rc;
8715         }
8716
8717         case SIOCSMIIREG:
8718                 if (!netif_running(dev))
8719                         return -EAGAIN;
8720
8721                 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
8722                                                 mdio->val_in);
8723
8724         default:
8725                 /* do nothing */
8726                 break;
8727         }
8728         return -EOPNOTSUPP;
8729 }
8730
8731 static void bnxt_get_ring_stats(struct bnxt *bp,
8732                                 struct rtnl_link_stats64 *stats)
8733 {
8734         int i;
8735
8736
8737         for (i = 0; i < bp->cp_nr_rings; i++) {
8738                 struct bnxt_napi *bnapi = bp->bnapi[i];
8739                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8740                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8741
8742                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8743                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8744                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8745
8746                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8747                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8748                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8749
8750                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8751                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8752                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8753
8754                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8755                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8756                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8757
8758                 stats->rx_missed_errors +=
8759                         le64_to_cpu(hw_stats->rx_discard_pkts);
8760
8761                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8762
8763                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8764         }
8765 }
8766
8767 static void bnxt_add_prev_stats(struct bnxt *bp,
8768                                 struct rtnl_link_stats64 *stats)
8769 {
8770         struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8771
8772         stats->rx_packets += prev_stats->rx_packets;
8773         stats->tx_packets += prev_stats->tx_packets;
8774         stats->rx_bytes += prev_stats->rx_bytes;
8775         stats->tx_bytes += prev_stats->tx_bytes;
8776         stats->rx_missed_errors += prev_stats->rx_missed_errors;
8777         stats->multicast += prev_stats->multicast;
8778         stats->tx_dropped += prev_stats->tx_dropped;
8779 }
8780
8781 static void
8782 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8783 {
8784         struct bnxt *bp = netdev_priv(dev);
8785
8786         set_bit(BNXT_STATE_READ_STATS, &bp->state);
8787         /* Make sure bnxt_close_nic() sees that we are reading stats before
8788          * we check the BNXT_STATE_OPEN flag.
8789          */
8790         smp_mb__after_atomic();
8791         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8792                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8793                 *stats = bp->net_stats_prev;
8794                 return;
8795         }
8796
8797         bnxt_get_ring_stats(bp, stats);
8798         bnxt_add_prev_stats(bp, stats);
8799
8800         if (bp->flags & BNXT_FLAG_PORT_STATS) {
8801                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8802                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8803
8804                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8805                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8806                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8807                                           le64_to_cpu(rx->rx_ovrsz_frames) +
8808                                           le64_to_cpu(rx->rx_runt_frames);
8809                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8810                                    le64_to_cpu(rx->rx_jbr_frames);
8811                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8812                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8813                 stats->tx_errors = le64_to_cpu(tx->tx_err);
8814         }
8815         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8816 }
8817
8818 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8819 {
8820         struct net_device *dev = bp->dev;
8821         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8822         struct netdev_hw_addr *ha;
8823         u8 *haddr;
8824         int mc_count = 0;
8825         bool update = false;
8826         int off = 0;
8827
8828         netdev_for_each_mc_addr(ha, dev) {
8829                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
8830                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8831                         vnic->mc_list_count = 0;
8832                         return false;
8833                 }
8834                 haddr = ha->addr;
8835                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
8836                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
8837                         update = true;
8838                 }
8839                 off += ETH_ALEN;
8840                 mc_count++;
8841         }
8842         if (mc_count)
8843                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
8844
8845         if (mc_count != vnic->mc_list_count) {
8846                 vnic->mc_list_count = mc_count;
8847                 update = true;
8848         }
8849         return update;
8850 }
8851
8852 static bool bnxt_uc_list_updated(struct bnxt *bp)
8853 {
8854         struct net_device *dev = bp->dev;
8855         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8856         struct netdev_hw_addr *ha;
8857         int off = 0;
8858
8859         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
8860                 return true;
8861
8862         netdev_for_each_uc_addr(ha, dev) {
8863                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
8864                         return true;
8865
8866                 off += ETH_ALEN;
8867         }
8868         return false;
8869 }
8870
8871 static void bnxt_set_rx_mode(struct net_device *dev)
8872 {
8873         struct bnxt *bp = netdev_priv(dev);
8874         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8875         u32 mask = vnic->rx_mask;
8876         bool mc_update = false;
8877         bool uc_update;
8878
8879         if (!netif_running(dev))
8880                 return;
8881
8882         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
8883                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
8884                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
8885                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
8886
8887         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
8888                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8889
8890         uc_update = bnxt_uc_list_updated(bp);
8891
8892         if (dev->flags & IFF_BROADCAST)
8893                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8894         if (dev->flags & IFF_ALLMULTI) {
8895                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8896                 vnic->mc_list_count = 0;
8897         } else {
8898                 mc_update = bnxt_mc_list_updated(bp, &mask);
8899         }
8900
8901         if (mask != vnic->rx_mask || uc_update || mc_update) {
8902                 vnic->rx_mask = mask;
8903
8904                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
8905                 bnxt_queue_sp_work(bp);
8906         }
8907 }
8908
8909 static int bnxt_cfg_rx_mode(struct bnxt *bp)
8910 {
8911         struct net_device *dev = bp->dev;
8912         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8913         struct netdev_hw_addr *ha;
8914         int i, off = 0, rc;
8915         bool uc_update;
8916
8917         netif_addr_lock_bh(dev);
8918         uc_update = bnxt_uc_list_updated(bp);
8919         netif_addr_unlock_bh(dev);
8920
8921         if (!uc_update)
8922                 goto skip_uc;
8923
8924         mutex_lock(&bp->hwrm_cmd_lock);
8925         for (i = 1; i < vnic->uc_filter_count; i++) {
8926                 struct hwrm_cfa_l2_filter_free_input req = {0};
8927
8928                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
8929                                        -1);
8930
8931                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
8932
8933                 rc = _hwrm_send_message(bp, &req, sizeof(req),
8934                                         HWRM_CMD_TIMEOUT);
8935         }
8936         mutex_unlock(&bp->hwrm_cmd_lock);
8937
8938         vnic->uc_filter_count = 1;
8939
8940         netif_addr_lock_bh(dev);
8941         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
8942                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8943         } else {
8944                 netdev_for_each_uc_addr(ha, dev) {
8945                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
8946                         off += ETH_ALEN;
8947                         vnic->uc_filter_count++;
8948                 }
8949         }
8950         netif_addr_unlock_bh(dev);
8951
8952         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
8953                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
8954                 if (rc) {
8955                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
8956                                    rc);
8957                         vnic->uc_filter_count = i;
8958                         return rc;
8959                 }
8960         }
8961
8962 skip_uc:
8963         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
8964         if (rc)
8965                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
8966                            rc);
8967
8968         return rc;
8969 }
8970
8971 static bool bnxt_can_reserve_rings(struct bnxt *bp)
8972 {
8973 #ifdef CONFIG_BNXT_SRIOV
8974         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
8975                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8976
8977                 /* No minimum rings were provisioned by the PF.  Don't
8978                  * reserve rings by default when device is down.
8979                  */
8980                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
8981                         return true;
8982
8983                 if (!netif_running(bp->dev))
8984                         return false;
8985         }
8986 #endif
8987         return true;
8988 }
8989
8990 /* If the chip and firmware supports RFS */
8991 static bool bnxt_rfs_supported(struct bnxt *bp)
8992 {
8993         if (bp->flags & BNXT_FLAG_CHIP_P5)
8994                 return false;
8995         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
8996                 return true;
8997         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8998                 return true;
8999         return false;
9000 }
9001
9002 /* If runtime conditions support RFS */
9003 static bool bnxt_rfs_capable(struct bnxt *bp)
9004 {
9005 #ifdef CONFIG_RFS_ACCEL
9006         int vnics, max_vnics, max_rss_ctxs;
9007
9008         if (bp->flags & BNXT_FLAG_CHIP_P5)
9009                 return false;
9010         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
9011                 return false;
9012
9013         vnics = 1 + bp->rx_nr_rings;
9014         max_vnics = bnxt_get_max_func_vnics(bp);
9015         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9016
9017         /* RSS contexts not a limiting factor */
9018         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9019                 max_rss_ctxs = max_vnics;
9020         if (vnics > max_vnics || vnics > max_rss_ctxs) {
9021                 if (bp->rx_nr_rings > 1)
9022                         netdev_warn(bp->dev,
9023                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9024                                     min(max_rss_ctxs - 1, max_vnics - 1));
9025                 return false;
9026         }
9027
9028         if (!BNXT_NEW_RM(bp))
9029                 return true;
9030
9031         if (vnics == bp->hw_resc.resv_vnics)
9032                 return true;
9033
9034         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9035         if (vnics <= bp->hw_resc.resv_vnics)
9036                 return true;
9037
9038         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9039         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9040         return false;
9041 #else
9042         return false;
9043 #endif
9044 }
9045
9046 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9047                                            netdev_features_t features)
9048 {
9049         struct bnxt *bp = netdev_priv(dev);
9050
9051         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9052                 features &= ~NETIF_F_NTUPLE;
9053
9054         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9055                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9056
9057         if (!(features & NETIF_F_GRO))
9058                 features &= ~NETIF_F_GRO_HW;
9059
9060         if (features & NETIF_F_GRO_HW)
9061                 features &= ~NETIF_F_LRO;
9062
9063         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
9064          * turned on or off together.
9065          */
9066         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
9067             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
9068                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9069                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9070                                       NETIF_F_HW_VLAN_STAG_RX);
9071                 else
9072                         features |= NETIF_F_HW_VLAN_CTAG_RX |
9073                                     NETIF_F_HW_VLAN_STAG_RX;
9074         }
9075 #ifdef CONFIG_BNXT_SRIOV
9076         if (BNXT_VF(bp)) {
9077                 if (bp->vf.vlan) {
9078                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9079                                       NETIF_F_HW_VLAN_STAG_RX);
9080                 }
9081         }
9082 #endif
9083         return features;
9084 }
9085
9086 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9087 {
9088         struct bnxt *bp = netdev_priv(dev);
9089         u32 flags = bp->flags;
9090         u32 changes;
9091         int rc = 0;
9092         bool re_init = false;
9093         bool update_tpa = false;
9094
9095         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9096         if (features & NETIF_F_GRO_HW)
9097                 flags |= BNXT_FLAG_GRO;
9098         else if (features & NETIF_F_LRO)
9099                 flags |= BNXT_FLAG_LRO;
9100
9101         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9102                 flags &= ~BNXT_FLAG_TPA;
9103
9104         if (features & NETIF_F_HW_VLAN_CTAG_RX)
9105                 flags |= BNXT_FLAG_STRIP_VLAN;
9106
9107         if (features & NETIF_F_NTUPLE)
9108                 flags |= BNXT_FLAG_RFS;
9109
9110         changes = flags ^ bp->flags;
9111         if (changes & BNXT_FLAG_TPA) {
9112                 update_tpa = true;
9113                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9114                     (flags & BNXT_FLAG_TPA) == 0)
9115                         re_init = true;
9116         }
9117
9118         if (changes & ~BNXT_FLAG_TPA)
9119                 re_init = true;
9120
9121         if (flags != bp->flags) {
9122                 u32 old_flags = bp->flags;
9123
9124                 bp->flags = flags;
9125
9126                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9127                         if (update_tpa)
9128                                 bnxt_set_ring_params(bp);
9129                         return rc;
9130                 }
9131
9132                 if (re_init) {
9133                         bnxt_close_nic(bp, false, false);
9134                         if (update_tpa)
9135                                 bnxt_set_ring_params(bp);
9136
9137                         return bnxt_open_nic(bp, false, false);
9138                 }
9139                 if (update_tpa) {
9140                         rc = bnxt_set_tpa(bp,
9141                                           (flags & BNXT_FLAG_TPA) ?
9142                                           true : false);
9143                         if (rc)
9144                                 bp->flags = old_flags;
9145                 }
9146         }
9147         return rc;
9148 }
9149
9150 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9151                                        u32 ring_id, u32 *prod, u32 *cons)
9152 {
9153         struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9154         struct hwrm_dbg_ring_info_get_input req = {0};
9155         int rc;
9156
9157         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9158         req.ring_type = ring_type;
9159         req.fw_ring_id = cpu_to_le32(ring_id);
9160         mutex_lock(&bp->hwrm_cmd_lock);
9161         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9162         if (!rc) {
9163                 *prod = le32_to_cpu(resp->producer_index);
9164                 *cons = le32_to_cpu(resp->consumer_index);
9165         }
9166         mutex_unlock(&bp->hwrm_cmd_lock);
9167         return rc;
9168 }
9169
9170 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9171 {
9172         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9173         int i = bnapi->index;
9174
9175         if (!txr)
9176                 return;
9177
9178         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9179                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9180                     txr->tx_cons);
9181 }
9182
9183 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9184 {
9185         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9186         int i = bnapi->index;
9187
9188         if (!rxr)
9189                 return;
9190
9191         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9192                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9193                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9194                     rxr->rx_sw_agg_prod);
9195 }
9196
9197 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9198 {
9199         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9200         int i = bnapi->index;
9201
9202         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9203                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9204 }
9205
9206 static void bnxt_dbg_dump_states(struct bnxt *bp)
9207 {
9208         int i;
9209         struct bnxt_napi *bnapi;
9210
9211         for (i = 0; i < bp->cp_nr_rings; i++) {
9212                 bnapi = bp->bnapi[i];
9213                 if (netif_msg_drv(bp)) {
9214                         bnxt_dump_tx_sw_state(bnapi);
9215                         bnxt_dump_rx_sw_state(bnapi);
9216                         bnxt_dump_cp_sw_state(bnapi);
9217                 }
9218         }
9219 }
9220
9221 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9222 {
9223         if (!silent)
9224                 bnxt_dbg_dump_states(bp);
9225         if (netif_running(bp->dev)) {
9226                 int rc;
9227
9228                 if (!silent)
9229                         bnxt_ulp_stop(bp);
9230                 bnxt_close_nic(bp, false, false);
9231                 rc = bnxt_open_nic(bp, false, false);
9232                 if (!silent && !rc)
9233                         bnxt_ulp_start(bp);
9234         }
9235 }
9236
9237 static void bnxt_tx_timeout(struct net_device *dev)
9238 {
9239         struct bnxt *bp = netdev_priv(dev);
9240
9241         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
9242         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9243         bnxt_queue_sp_work(bp);
9244 }
9245
9246 static void bnxt_timer(struct timer_list *t)
9247 {
9248         struct bnxt *bp = from_timer(bp, t, timer);
9249         struct net_device *dev = bp->dev;
9250
9251         if (!netif_running(dev))
9252                 return;
9253
9254         if (atomic_read(&bp->intr_sem) != 0)
9255                 goto bnxt_restart_timer;
9256
9257         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9258             bp->stats_coal_ticks) {
9259                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9260                 bnxt_queue_sp_work(bp);
9261         }
9262
9263         if (bnxt_tc_flower_enabled(bp)) {
9264                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9265                 bnxt_queue_sp_work(bp);
9266         }
9267
9268         if (bp->link_info.phy_retry) {
9269                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9270                         bp->link_info.phy_retry = 0;
9271                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9272                 } else {
9273                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9274                         bnxt_queue_sp_work(bp);
9275                 }
9276         }
9277
9278         if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9279                 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9280                 bnxt_queue_sp_work(bp);
9281         }
9282 bnxt_restart_timer:
9283         mod_timer(&bp->timer, jiffies + bp->current_interval);
9284 }
9285
9286 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9287 {
9288         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9289          * set.  If the device is being closed, bnxt_close() may be holding
9290          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
9291          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9292          */
9293         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9294         rtnl_lock();
9295 }
9296
9297 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9298 {
9299         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9300         rtnl_unlock();
9301 }
9302
9303 /* Only called from bnxt_sp_task() */
9304 static void bnxt_reset(struct bnxt *bp, bool silent)
9305 {
9306         bnxt_rtnl_lock_sp(bp);
9307         if (test_bit(BNXT_STATE_OPEN, &bp->state))
9308                 bnxt_reset_task(bp, silent);
9309         bnxt_rtnl_unlock_sp(bp);
9310 }
9311
9312 static void bnxt_chk_missed_irq(struct bnxt *bp)
9313 {
9314         int i;
9315
9316         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9317                 return;
9318
9319         for (i = 0; i < bp->cp_nr_rings; i++) {
9320                 struct bnxt_napi *bnapi = bp->bnapi[i];
9321                 struct bnxt_cp_ring_info *cpr;
9322                 u32 fw_ring_id;
9323                 int j;
9324
9325                 if (!bnapi)
9326                         continue;
9327
9328                 cpr = &bnapi->cp_ring;
9329                 for (j = 0; j < 2; j++) {
9330                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9331                         u32 val[2];
9332
9333                         if (!cpr2 || cpr2->has_more_work ||
9334                             !bnxt_has_work(bp, cpr2))
9335                                 continue;
9336
9337                         if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9338                                 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9339                                 continue;
9340                         }
9341                         fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9342                         bnxt_dbg_hwrm_ring_info_get(bp,
9343                                 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9344                                 fw_ring_id, &val[0], &val[1]);
9345                         cpr->missed_irqs++;
9346                 }
9347         }
9348 }
9349
9350 static void bnxt_cfg_ntp_filters(struct bnxt *);
9351
9352 static void bnxt_sp_task(struct work_struct *work)
9353 {
9354         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9355
9356         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9357         smp_mb__after_atomic();
9358         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9359                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9360                 return;
9361         }
9362
9363         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9364                 bnxt_cfg_rx_mode(bp);
9365
9366         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9367                 bnxt_cfg_ntp_filters(bp);
9368         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9369                 bnxt_hwrm_exec_fwd_req(bp);
9370         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9371                 bnxt_hwrm_tunnel_dst_port_alloc(
9372                         bp, bp->vxlan_port,
9373                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9374         }
9375         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9376                 bnxt_hwrm_tunnel_dst_port_free(
9377                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9378         }
9379         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9380                 bnxt_hwrm_tunnel_dst_port_alloc(
9381                         bp, bp->nge_port,
9382                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9383         }
9384         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9385                 bnxt_hwrm_tunnel_dst_port_free(
9386                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9387         }
9388         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9389                 bnxt_hwrm_port_qstats(bp);
9390                 bnxt_hwrm_port_qstats_ext(bp);
9391         }
9392
9393         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9394                 int rc;
9395
9396                 mutex_lock(&bp->link_lock);
9397                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9398                                        &bp->sp_event))
9399                         bnxt_hwrm_phy_qcaps(bp);
9400
9401                 rc = bnxt_update_link(bp, true);
9402                 mutex_unlock(&bp->link_lock);
9403                 if (rc)
9404                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9405                                    rc);
9406         }
9407         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9408                 int rc;
9409
9410                 mutex_lock(&bp->link_lock);
9411                 rc = bnxt_update_phy_setting(bp);
9412                 mutex_unlock(&bp->link_lock);
9413                 if (rc) {
9414                         netdev_warn(bp->dev, "update phy settings retry failed\n");
9415                 } else {
9416                         bp->link_info.phy_retry = false;
9417                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
9418                 }
9419         }
9420         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9421                 mutex_lock(&bp->link_lock);
9422                 bnxt_get_port_module_status(bp);
9423                 mutex_unlock(&bp->link_lock);
9424         }
9425
9426         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9427                 bnxt_tc_flow_stats_work(bp);
9428
9429         if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9430                 bnxt_chk_missed_irq(bp);
9431
9432         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
9433          * must be the last functions to be called before exiting.
9434          */
9435         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9436                 bnxt_reset(bp, false);
9437
9438         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9439                 bnxt_reset(bp, true);
9440
9441         smp_mb__before_atomic();
9442         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9443 }
9444
9445 /* Under rtnl_lock */
9446 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9447                      int tx_xdp)
9448 {
9449         int max_rx, max_tx, tx_sets = 1;
9450         int tx_rings_needed, stats;
9451         int rx_rings = rx;
9452         int cp, vnics, rc;
9453
9454         if (tcs)
9455                 tx_sets = tcs;
9456
9457         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9458         if (rc)
9459                 return rc;
9460
9461         if (max_rx < rx)
9462                 return -ENOMEM;
9463
9464         tx_rings_needed = tx * tx_sets + tx_xdp;
9465         if (max_tx < tx_rings_needed)
9466                 return -ENOMEM;
9467
9468         vnics = 1;
9469         if (bp->flags & BNXT_FLAG_RFS)
9470                 vnics += rx_rings;
9471
9472         if (bp->flags & BNXT_FLAG_AGG_RINGS)
9473                 rx_rings <<= 1;
9474         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9475         stats = cp;
9476         if (BNXT_NEW_RM(bp)) {
9477                 cp += bnxt_get_ulp_msix_num(bp);
9478                 stats += bnxt_get_ulp_stat_ctxs(bp);
9479         }
9480         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9481                                      stats, vnics);
9482 }
9483
9484 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9485 {
9486         if (bp->bar2) {
9487                 pci_iounmap(pdev, bp->bar2);
9488                 bp->bar2 = NULL;
9489         }
9490
9491         if (bp->bar1) {
9492                 pci_iounmap(pdev, bp->bar1);
9493                 bp->bar1 = NULL;
9494         }
9495
9496         if (bp->bar0) {
9497                 pci_iounmap(pdev, bp->bar0);
9498                 bp->bar0 = NULL;
9499         }
9500 }
9501
9502 static void bnxt_cleanup_pci(struct bnxt *bp)
9503 {
9504         bnxt_unmap_bars(bp, bp->pdev);
9505         pci_release_regions(bp->pdev);
9506         pci_disable_device(bp->pdev);
9507 }
9508
9509 static void bnxt_init_dflt_coal(struct bnxt *bp)
9510 {
9511         struct bnxt_coal *coal;
9512
9513         /* Tick values in micro seconds.
9514          * 1 coal_buf x bufs_per_record = 1 completion record.
9515          */
9516         coal = &bp->rx_coal;
9517         coal->coal_ticks = 10;
9518         coal->coal_bufs = 30;
9519         coal->coal_ticks_irq = 1;
9520         coal->coal_bufs_irq = 2;
9521         coal->idle_thresh = 50;
9522         coal->bufs_per_record = 2;
9523         coal->budget = 64;              /* NAPI budget */
9524
9525         coal = &bp->tx_coal;
9526         coal->coal_ticks = 28;
9527         coal->coal_bufs = 30;
9528         coal->coal_ticks_irq = 2;
9529         coal->coal_bufs_irq = 2;
9530         coal->bufs_per_record = 1;
9531
9532         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9533 }
9534
9535 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9536 {
9537         int rc;
9538         struct bnxt *bp = netdev_priv(dev);
9539
9540         SET_NETDEV_DEV(dev, &pdev->dev);
9541
9542         /* enable device (incl. PCI PM wakeup), and bus-mastering */
9543         rc = pci_enable_device(pdev);
9544         if (rc) {
9545                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9546                 goto init_err;
9547         }
9548
9549         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9550                 dev_err(&pdev->dev,
9551                         "Cannot find PCI device base address, aborting\n");
9552                 rc = -ENODEV;
9553                 goto init_err_disable;
9554         }
9555
9556         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9557         if (rc) {
9558                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9559                 goto init_err_disable;
9560         }
9561
9562         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9563             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9564                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9565                 goto init_err_disable;
9566         }
9567
9568         pci_set_master(pdev);
9569
9570         bp->dev = dev;
9571         bp->pdev = pdev;
9572
9573         bp->bar0 = pci_ioremap_bar(pdev, 0);
9574         if (!bp->bar0) {
9575                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9576                 rc = -ENOMEM;
9577                 goto init_err_release;
9578         }
9579
9580         bp->bar1 = pci_ioremap_bar(pdev, 2);
9581         if (!bp->bar1) {
9582                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9583                 rc = -ENOMEM;
9584                 goto init_err_release;
9585         }
9586
9587         bp->bar2 = pci_ioremap_bar(pdev, 4);
9588         if (!bp->bar2) {
9589                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9590                 rc = -ENOMEM;
9591                 goto init_err_release;
9592         }
9593
9594         pci_enable_pcie_error_reporting(pdev);
9595
9596         INIT_WORK(&bp->sp_task, bnxt_sp_task);
9597
9598         spin_lock_init(&bp->ntp_fltr_lock);
9599 #if BITS_PER_LONG == 32
9600         spin_lock_init(&bp->db_lock);
9601 #endif
9602
9603         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9604         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9605
9606         bnxt_init_dflt_coal(bp);
9607
9608         timer_setup(&bp->timer, bnxt_timer, 0);
9609         bp->current_interval = BNXT_TIMER_INTERVAL;
9610
9611         clear_bit(BNXT_STATE_OPEN, &bp->state);
9612         return 0;
9613
9614 init_err_release:
9615         bnxt_unmap_bars(bp, pdev);
9616         pci_release_regions(pdev);
9617
9618 init_err_disable:
9619         pci_disable_device(pdev);
9620
9621 init_err:
9622         return rc;
9623 }
9624
9625 /* rtnl_lock held */
9626 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9627 {
9628         struct sockaddr *addr = p;
9629         struct bnxt *bp = netdev_priv(dev);
9630         int rc = 0;
9631
9632         if (!is_valid_ether_addr(addr->sa_data))
9633                 return -EADDRNOTAVAIL;
9634
9635         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9636                 return 0;
9637
9638         rc = bnxt_approve_mac(bp, addr->sa_data, true);
9639         if (rc)
9640                 return rc;
9641
9642         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9643         if (netif_running(dev)) {
9644                 bnxt_close_nic(bp, false, false);
9645                 rc = bnxt_open_nic(bp, false, false);
9646         }
9647
9648         return rc;
9649 }
9650
9651 /* rtnl_lock held */
9652 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9653 {
9654         struct bnxt *bp = netdev_priv(dev);
9655
9656         if (netif_running(dev))
9657                 bnxt_close_nic(bp, false, false);
9658
9659         dev->mtu = new_mtu;
9660         bnxt_set_ring_params(bp);
9661
9662         if (netif_running(dev))
9663                 return bnxt_open_nic(bp, false, false);
9664
9665         return 0;
9666 }
9667
9668 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9669 {
9670         struct bnxt *bp = netdev_priv(dev);
9671         bool sh = false;
9672         int rc;
9673
9674         if (tc > bp->max_tc) {
9675                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9676                            tc, bp->max_tc);
9677                 return -EINVAL;
9678         }
9679
9680         if (netdev_get_num_tc(dev) == tc)
9681                 return 0;
9682
9683         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9684                 sh = true;
9685
9686         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9687                               sh, tc, bp->tx_nr_rings_xdp);
9688         if (rc)
9689                 return rc;
9690
9691         /* Needs to close the device and do hw resource re-allocations */
9692         if (netif_running(bp->dev))
9693                 bnxt_close_nic(bp, true, false);
9694
9695         if (tc) {
9696                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9697                 netdev_set_num_tc(dev, tc);
9698         } else {
9699                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9700                 netdev_reset_tc(dev);
9701         }
9702         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9703         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9704                                bp->tx_nr_rings + bp->rx_nr_rings;
9705
9706         if (netif_running(bp->dev))
9707                 return bnxt_open_nic(bp, true, false);
9708
9709         return 0;
9710 }
9711
9712 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9713                                   void *cb_priv)
9714 {
9715         struct bnxt *bp = cb_priv;
9716
9717         if (!bnxt_tc_flower_enabled(bp) ||
9718             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9719                 return -EOPNOTSUPP;
9720
9721         switch (type) {
9722         case TC_SETUP_CLSFLOWER:
9723                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9724         default:
9725                 return -EOPNOTSUPP;
9726         }
9727 }
9728
9729 static int bnxt_setup_tc_block(struct net_device *dev,
9730                                struct tc_block_offload *f)
9731 {
9732         struct bnxt *bp = netdev_priv(dev);
9733
9734         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9735                 return -EOPNOTSUPP;
9736
9737         switch (f->command) {
9738         case TC_BLOCK_BIND:
9739                 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
9740                                              bp, bp, f->extack);
9741         case TC_BLOCK_UNBIND:
9742                 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
9743                 return 0;
9744         default:
9745                 return -EOPNOTSUPP;
9746         }
9747 }
9748
9749 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9750                          void *type_data)
9751 {
9752         switch (type) {
9753         case TC_SETUP_BLOCK:
9754                 return bnxt_setup_tc_block(dev, type_data);
9755         case TC_SETUP_QDISC_MQPRIO: {
9756                 struct tc_mqprio_qopt *mqprio = type_data;
9757
9758                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9759
9760                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9761         }
9762         default:
9763                 return -EOPNOTSUPP;
9764         }
9765 }
9766
9767 #ifdef CONFIG_RFS_ACCEL
9768 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9769                             struct bnxt_ntuple_filter *f2)
9770 {
9771         struct flow_keys *keys1 = &f1->fkeys;
9772         struct flow_keys *keys2 = &f2->fkeys;
9773
9774         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9775             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9776             keys1->ports.ports == keys2->ports.ports &&
9777             keys1->basic.ip_proto == keys2->basic.ip_proto &&
9778             keys1->basic.n_proto == keys2->basic.n_proto &&
9779             keys1->control.flags == keys2->control.flags &&
9780             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9781             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9782                 return true;
9783
9784         return false;
9785 }
9786
9787 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9788                               u16 rxq_index, u32 flow_id)
9789 {
9790         struct bnxt *bp = netdev_priv(dev);
9791         struct bnxt_ntuple_filter *fltr, *new_fltr;
9792         struct flow_keys *fkeys;
9793         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9794         int rc = 0, idx, bit_id, l2_idx = 0;
9795         struct hlist_head *head;
9796
9797         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9798                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9799                 int off = 0, j;
9800
9801                 netif_addr_lock_bh(dev);
9802                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9803                         if (ether_addr_equal(eth->h_dest,
9804                                              vnic->uc_list + off)) {
9805                                 l2_idx = j + 1;
9806                                 break;
9807                         }
9808                 }
9809                 netif_addr_unlock_bh(dev);
9810                 if (!l2_idx)
9811                         return -EINVAL;
9812         }
9813         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9814         if (!new_fltr)
9815                 return -ENOMEM;
9816
9817         fkeys = &new_fltr->fkeys;
9818         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
9819                 rc = -EPROTONOSUPPORT;
9820                 goto err_free;
9821         }
9822
9823         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
9824              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
9825             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
9826              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
9827                 rc = -EPROTONOSUPPORT;
9828                 goto err_free;
9829         }
9830         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
9831             bp->hwrm_spec_code < 0x10601) {
9832                 rc = -EPROTONOSUPPORT;
9833                 goto err_free;
9834         }
9835         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
9836             bp->hwrm_spec_code < 0x10601) {
9837                 rc = -EPROTONOSUPPORT;
9838                 goto err_free;
9839         }
9840
9841         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
9842         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
9843
9844         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
9845         head = &bp->ntp_fltr_hash_tbl[idx];
9846         rcu_read_lock();
9847         hlist_for_each_entry_rcu(fltr, head, hash) {
9848                 if (bnxt_fltr_match(fltr, new_fltr)) {
9849                         rcu_read_unlock();
9850                         rc = 0;
9851                         goto err_free;
9852                 }
9853         }
9854         rcu_read_unlock();
9855
9856         spin_lock_bh(&bp->ntp_fltr_lock);
9857         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
9858                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
9859         if (bit_id < 0) {
9860                 spin_unlock_bh(&bp->ntp_fltr_lock);
9861                 rc = -ENOMEM;
9862                 goto err_free;
9863         }
9864
9865         new_fltr->sw_id = (u16)bit_id;
9866         new_fltr->flow_id = flow_id;
9867         new_fltr->l2_fltr_idx = l2_idx;
9868         new_fltr->rxq = rxq_index;
9869         hlist_add_head_rcu(&new_fltr->hash, head);
9870         bp->ntp_fltr_count++;
9871         spin_unlock_bh(&bp->ntp_fltr_lock);
9872
9873         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
9874         bnxt_queue_sp_work(bp);
9875
9876         return new_fltr->sw_id;
9877
9878 err_free:
9879         kfree(new_fltr);
9880         return rc;
9881 }
9882
9883 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9884 {
9885         int i;
9886
9887         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
9888                 struct hlist_head *head;
9889                 struct hlist_node *tmp;
9890                 struct bnxt_ntuple_filter *fltr;
9891                 int rc;
9892
9893                 head = &bp->ntp_fltr_hash_tbl[i];
9894                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
9895                         bool del = false;
9896
9897                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
9898                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
9899                                                         fltr->flow_id,
9900                                                         fltr->sw_id)) {
9901                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
9902                                                                          fltr);
9903                                         del = true;
9904                                 }
9905                         } else {
9906                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
9907                                                                        fltr);
9908                                 if (rc)
9909                                         del = true;
9910                                 else
9911                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
9912                         }
9913
9914                         if (del) {
9915                                 spin_lock_bh(&bp->ntp_fltr_lock);
9916                                 hlist_del_rcu(&fltr->hash);
9917                                 bp->ntp_fltr_count--;
9918                                 spin_unlock_bh(&bp->ntp_fltr_lock);
9919                                 synchronize_rcu();
9920                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
9921                                 kfree(fltr);
9922                         }
9923                 }
9924         }
9925         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
9926                 netdev_info(bp->dev, "Receive PF driver unload event!");
9927 }
9928
9929 #else
9930
9931 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9932 {
9933 }
9934
9935 #endif /* CONFIG_RFS_ACCEL */
9936
9937 static void bnxt_udp_tunnel_add(struct net_device *dev,
9938                                 struct udp_tunnel_info *ti)
9939 {
9940         struct bnxt *bp = netdev_priv(dev);
9941
9942         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
9943                 return;
9944
9945         if (!netif_running(dev))
9946                 return;
9947
9948         switch (ti->type) {
9949         case UDP_TUNNEL_TYPE_VXLAN:
9950                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
9951                         return;
9952
9953                 bp->vxlan_port_cnt++;
9954                 if (bp->vxlan_port_cnt == 1) {
9955                         bp->vxlan_port = ti->port;
9956                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
9957                         bnxt_queue_sp_work(bp);
9958                 }
9959                 break;
9960         case UDP_TUNNEL_TYPE_GENEVE:
9961                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
9962                         return;
9963
9964                 bp->nge_port_cnt++;
9965                 if (bp->nge_port_cnt == 1) {
9966                         bp->nge_port = ti->port;
9967                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
9968                 }
9969                 break;
9970         default:
9971                 return;
9972         }
9973
9974         bnxt_queue_sp_work(bp);
9975 }
9976
9977 static void bnxt_udp_tunnel_del(struct net_device *dev,
9978                                 struct udp_tunnel_info *ti)
9979 {
9980         struct bnxt *bp = netdev_priv(dev);
9981
9982         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
9983                 return;
9984
9985         if (!netif_running(dev))
9986                 return;
9987
9988         switch (ti->type) {
9989         case UDP_TUNNEL_TYPE_VXLAN:
9990                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
9991                         return;
9992                 bp->vxlan_port_cnt--;
9993
9994                 if (bp->vxlan_port_cnt != 0)
9995                         return;
9996
9997                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
9998                 break;
9999         case UDP_TUNNEL_TYPE_GENEVE:
10000                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
10001                         return;
10002                 bp->nge_port_cnt--;
10003
10004                 if (bp->nge_port_cnt != 0)
10005                         return;
10006
10007                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
10008                 break;
10009         default:
10010                 return;
10011         }
10012
10013         bnxt_queue_sp_work(bp);
10014 }
10015
10016 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10017                                struct net_device *dev, u32 filter_mask,
10018                                int nlflags)
10019 {
10020         struct bnxt *bp = netdev_priv(dev);
10021
10022         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
10023                                        nlflags, filter_mask, NULL);
10024 }
10025
10026 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
10027                                u16 flags, struct netlink_ext_ack *extack)
10028 {
10029         struct bnxt *bp = netdev_priv(dev);
10030         struct nlattr *attr, *br_spec;
10031         int rem, rc = 0;
10032
10033         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
10034                 return -EOPNOTSUPP;
10035
10036         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10037         if (!br_spec)
10038                 return -EINVAL;
10039
10040         nla_for_each_nested(attr, br_spec, rem) {
10041                 u16 mode;
10042
10043                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
10044                         continue;
10045
10046                 if (nla_len(attr) < sizeof(mode))
10047                         return -EINVAL;
10048
10049                 mode = nla_get_u16(attr);
10050                 if (mode == bp->br_mode)
10051                         break;
10052
10053                 rc = bnxt_hwrm_set_br_mode(bp, mode);
10054                 if (!rc)
10055                         bp->br_mode = mode;
10056                 break;
10057         }
10058         return rc;
10059 }
10060
10061 int bnxt_get_port_parent_id(struct net_device *dev,
10062                             struct netdev_phys_item_id *ppid)
10063 {
10064         struct bnxt *bp = netdev_priv(dev);
10065
10066         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
10067                 return -EOPNOTSUPP;
10068
10069         /* The PF and it's VF-reps only support the switchdev framework */
10070         if (!BNXT_PF(bp))
10071                 return -EOPNOTSUPP;
10072
10073         ppid->id_len = sizeof(bp->switch_id);
10074         memcpy(ppid->id, bp->switch_id, ppid->id_len);
10075
10076         return 0;
10077 }
10078
10079 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
10080 {
10081         struct bnxt *bp = netdev_priv(dev);
10082
10083         return &bp->dl_port;
10084 }
10085
10086 static const struct net_device_ops bnxt_netdev_ops = {
10087         .ndo_open               = bnxt_open,
10088         .ndo_start_xmit         = bnxt_start_xmit,
10089         .ndo_stop               = bnxt_close,
10090         .ndo_get_stats64        = bnxt_get_stats64,
10091         .ndo_set_rx_mode        = bnxt_set_rx_mode,
10092         .ndo_do_ioctl           = bnxt_ioctl,
10093         .ndo_validate_addr      = eth_validate_addr,
10094         .ndo_set_mac_address    = bnxt_change_mac_addr,
10095         .ndo_change_mtu         = bnxt_change_mtu,
10096         .ndo_fix_features       = bnxt_fix_features,
10097         .ndo_set_features       = bnxt_set_features,
10098         .ndo_tx_timeout         = bnxt_tx_timeout,
10099 #ifdef CONFIG_BNXT_SRIOV
10100         .ndo_get_vf_config      = bnxt_get_vf_config,
10101         .ndo_set_vf_mac         = bnxt_set_vf_mac,
10102         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
10103         .ndo_set_vf_rate        = bnxt_set_vf_bw,
10104         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
10105         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
10106         .ndo_set_vf_trust       = bnxt_set_vf_trust,
10107 #endif
10108         .ndo_setup_tc           = bnxt_setup_tc,
10109 #ifdef CONFIG_RFS_ACCEL
10110         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
10111 #endif
10112         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
10113         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
10114         .ndo_bpf                = bnxt_xdp,
10115         .ndo_bridge_getlink     = bnxt_bridge_getlink,
10116         .ndo_bridge_setlink     = bnxt_bridge_setlink,
10117         .ndo_get_devlink_port   = bnxt_get_devlink_port,
10118 };
10119
10120 static void bnxt_remove_one(struct pci_dev *pdev)
10121 {
10122         struct net_device *dev = pci_get_drvdata(pdev);
10123         struct bnxt *bp = netdev_priv(dev);
10124
10125         if (BNXT_PF(bp)) {
10126                 bnxt_sriov_disable(bp);
10127                 bnxt_dl_unregister(bp);
10128         }
10129
10130         pci_disable_pcie_error_reporting(pdev);
10131         unregister_netdev(dev);
10132         bnxt_shutdown_tc(bp);
10133         bnxt_cancel_sp_work(bp);
10134         bp->sp_event = 0;
10135
10136         bnxt_clear_int_mode(bp);
10137         bnxt_hwrm_func_drv_unrgtr(bp);
10138         bnxt_free_hwrm_resources(bp);
10139         bnxt_free_hwrm_short_cmd_req(bp);
10140         bnxt_ethtool_free(bp);
10141         bnxt_dcb_free(bp);
10142         kfree(bp->edev);
10143         bp->edev = NULL;
10144         bnxt_free_ctx_mem(bp);
10145         kfree(bp->ctx);
10146         bp->ctx = NULL;
10147         bnxt_cleanup_pci(bp);
10148         bnxt_free_port_stats(bp);
10149         free_netdev(dev);
10150 }
10151
10152 static int bnxt_probe_phy(struct bnxt *bp)
10153 {
10154         int rc = 0;
10155         struct bnxt_link_info *link_info = &bp->link_info;
10156
10157         rc = bnxt_hwrm_phy_qcaps(bp);
10158         if (rc) {
10159                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10160                            rc);
10161                 return rc;
10162         }
10163         mutex_init(&bp->link_lock);
10164
10165         rc = bnxt_update_link(bp, false);
10166         if (rc) {
10167                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10168                            rc);
10169                 return rc;
10170         }
10171
10172         /* Older firmware does not have supported_auto_speeds, so assume
10173          * that all supported speeds can be autonegotiated.
10174          */
10175         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10176                 link_info->support_auto_speeds = link_info->support_speeds;
10177
10178         /*initialize the ethool setting copy with NVM settings */
10179         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10180                 link_info->autoneg = BNXT_AUTONEG_SPEED;
10181                 if (bp->hwrm_spec_code >= 0x10201) {
10182                         if (link_info->auto_pause_setting &
10183                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10184                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10185                 } else {
10186                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10187                 }
10188                 link_info->advertising = link_info->auto_link_speeds;
10189         } else {
10190                 link_info->req_link_speed = link_info->force_link_speed;
10191                 link_info->req_duplex = link_info->duplex_setting;
10192         }
10193         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10194                 link_info->req_flow_ctrl =
10195                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10196         else
10197                 link_info->req_flow_ctrl = link_info->force_pause_setting;
10198         return rc;
10199 }
10200
10201 static int bnxt_get_max_irq(struct pci_dev *pdev)
10202 {
10203         u16 ctrl;
10204
10205         if (!pdev->msix_cap)
10206                 return 1;
10207
10208         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10209         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10210 }
10211
10212 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10213                                 int *max_cp)
10214 {
10215         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10216         int max_ring_grps = 0, max_irq;
10217
10218         *max_tx = hw_resc->max_tx_rings;
10219         *max_rx = hw_resc->max_rx_rings;
10220         *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10221         max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10222                         bnxt_get_ulp_msix_num(bp),
10223                         hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10224         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10225                 *max_cp = min_t(int, *max_cp, max_irq);
10226         max_ring_grps = hw_resc->max_hw_ring_grps;
10227         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10228                 *max_cp -= 1;
10229                 *max_rx -= 2;
10230         }
10231         if (bp->flags & BNXT_FLAG_AGG_RINGS)
10232                 *max_rx >>= 1;
10233         if (bp->flags & BNXT_FLAG_CHIP_P5) {
10234                 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10235                 /* On P5 chips, max_cp output param should be available NQs */
10236                 *max_cp = max_irq;
10237         }
10238         *max_rx = min_t(int, *max_rx, max_ring_grps);
10239 }
10240
10241 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10242 {
10243         int rx, tx, cp;
10244
10245         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10246         *max_rx = rx;
10247         *max_tx = tx;
10248         if (!rx || !tx || !cp)
10249                 return -ENOMEM;
10250
10251         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10252 }
10253
10254 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10255                                bool shared)
10256 {
10257         int rc;
10258
10259         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10260         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10261                 /* Not enough rings, try disabling agg rings. */
10262                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10263                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10264                 if (rc) {
10265                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
10266                         bp->flags |= BNXT_FLAG_AGG_RINGS;
10267                         return rc;
10268                 }
10269                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10270                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10271                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10272                 bnxt_set_ring_params(bp);
10273         }
10274
10275         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10276                 int max_cp, max_stat, max_irq;
10277
10278                 /* Reserve minimum resources for RoCE */
10279                 max_cp = bnxt_get_max_func_cp_rings(bp);
10280                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10281                 max_irq = bnxt_get_max_func_irqs(bp);
10282                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10283                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10284                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10285                         return 0;
10286
10287                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10288                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10289                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10290                 max_cp = min_t(int, max_cp, max_irq);
10291                 max_cp = min_t(int, max_cp, max_stat);
10292                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10293                 if (rc)
10294                         rc = 0;
10295         }
10296         return rc;
10297 }
10298
10299 /* In initial default shared ring setting, each shared ring must have a
10300  * RX/TX ring pair.
10301  */
10302 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10303 {
10304         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10305         bp->rx_nr_rings = bp->cp_nr_rings;
10306         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10307         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10308 }
10309
10310 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10311 {
10312         int dflt_rings, max_rx_rings, max_tx_rings, rc;
10313
10314         if (!bnxt_can_reserve_rings(bp))
10315                 return 0;
10316
10317         if (sh)
10318                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10319         dflt_rings = netif_get_num_default_rss_queues();
10320         /* Reduce default rings on multi-port cards so that total default
10321          * rings do not exceed CPU count.
10322          */
10323         if (bp->port_count > 1) {
10324                 int max_rings =
10325                         max_t(int, num_online_cpus() / bp->port_count, 1);
10326
10327                 dflt_rings = min_t(int, dflt_rings, max_rings);
10328         }
10329         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10330         if (rc)
10331                 return rc;
10332         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10333         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10334         if (sh)
10335                 bnxt_trim_dflt_sh_rings(bp);
10336         else
10337                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10338         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10339
10340         rc = __bnxt_reserve_rings(bp);
10341         if (rc)
10342                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10343         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10344         if (sh)
10345                 bnxt_trim_dflt_sh_rings(bp);
10346
10347         /* Rings may have been trimmed, re-reserve the trimmed rings. */
10348         if (bnxt_need_reserve_rings(bp)) {
10349                 rc = __bnxt_reserve_rings(bp);
10350                 if (rc)
10351                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10352                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10353         }
10354         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10355                 bp->rx_nr_rings++;
10356                 bp->cp_nr_rings++;
10357         }
10358         return rc;
10359 }
10360
10361 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10362 {
10363         int rc;
10364
10365         if (bp->tx_nr_rings)
10366                 return 0;
10367
10368         bnxt_ulp_irq_stop(bp);
10369         bnxt_clear_int_mode(bp);
10370         rc = bnxt_set_dflt_rings(bp, true);
10371         if (rc) {
10372                 netdev_err(bp->dev, "Not enough rings available.\n");
10373                 goto init_dflt_ring_err;
10374         }
10375         rc = bnxt_init_int_mode(bp);
10376         if (rc)
10377                 goto init_dflt_ring_err;
10378
10379         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10380         if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10381                 bp->flags |= BNXT_FLAG_RFS;
10382                 bp->dev->features |= NETIF_F_NTUPLE;
10383         }
10384 init_dflt_ring_err:
10385         bnxt_ulp_irq_restart(bp, rc);
10386         return rc;
10387 }
10388
10389 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10390 {
10391         int rc;
10392
10393         ASSERT_RTNL();
10394         bnxt_hwrm_func_qcaps(bp);
10395
10396         if (netif_running(bp->dev))
10397                 __bnxt_close_nic(bp, true, false);
10398
10399         bnxt_ulp_irq_stop(bp);
10400         bnxt_clear_int_mode(bp);
10401         rc = bnxt_init_int_mode(bp);
10402         bnxt_ulp_irq_restart(bp, rc);
10403
10404         if (netif_running(bp->dev)) {
10405                 if (rc)
10406                         dev_close(bp->dev);
10407                 else
10408                         rc = bnxt_open_nic(bp, true, false);
10409         }
10410
10411         return rc;
10412 }
10413
10414 static int bnxt_init_mac_addr(struct bnxt *bp)
10415 {
10416         int rc = 0;
10417
10418         if (BNXT_PF(bp)) {
10419                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10420         } else {
10421 #ifdef CONFIG_BNXT_SRIOV
10422                 struct bnxt_vf_info *vf = &bp->vf;
10423                 bool strict_approval = true;
10424
10425                 if (is_valid_ether_addr(vf->mac_addr)) {
10426                         /* overwrite netdev dev_addr with admin VF MAC */
10427                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10428                         /* Older PF driver or firmware may not approve this
10429                          * correctly.
10430                          */
10431                         strict_approval = false;
10432                 } else {
10433                         eth_hw_addr_random(bp->dev);
10434                 }
10435                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10436 #endif
10437         }
10438         return rc;
10439 }
10440
10441 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
10442 {
10443         struct pci_dev *pdev = bp->pdev;
10444         int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
10445         u32 dw;
10446
10447         if (!pos) {
10448                 netdev_info(bp->dev, "Unable do read adapter's DSN");
10449                 return -EOPNOTSUPP;
10450         }
10451
10452         /* DSN (two dw) is at an offset of 4 from the cap pos */
10453         pos += 4;
10454         pci_read_config_dword(pdev, pos, &dw);
10455         put_unaligned_le32(dw, &dsn[0]);
10456         pci_read_config_dword(pdev, pos + 4, &dw);
10457         put_unaligned_le32(dw, &dsn[4]);
10458         return 0;
10459 }
10460
10461 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10462 {
10463         static int version_printed;
10464         struct net_device *dev;
10465         struct bnxt *bp;
10466         int rc, max_irqs;
10467
10468         if (pci_is_bridge(pdev))
10469                 return -ENODEV;
10470
10471         if (version_printed++ == 0)
10472                 pr_info("%s", version);
10473
10474         max_irqs = bnxt_get_max_irq(pdev);
10475         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10476         if (!dev)
10477                 return -ENOMEM;
10478
10479         bp = netdev_priv(dev);
10480         bnxt_set_max_func_irqs(bp, max_irqs);
10481
10482         if (bnxt_vf_pciid(ent->driver_data))
10483                 bp->flags |= BNXT_FLAG_VF;
10484
10485         if (pdev->msix_cap)
10486                 bp->flags |= BNXT_FLAG_MSIX_CAP;
10487
10488         rc = bnxt_init_board(pdev, dev);
10489         if (rc < 0)
10490                 goto init_err_free;
10491
10492         dev->netdev_ops = &bnxt_netdev_ops;
10493         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10494         dev->ethtool_ops = &bnxt_ethtool_ops;
10495         pci_set_drvdata(pdev, dev);
10496
10497         rc = bnxt_alloc_hwrm_resources(bp);
10498         if (rc)
10499                 goto init_err_pci_clean;
10500
10501         mutex_init(&bp->hwrm_cmd_lock);
10502         rc = bnxt_hwrm_ver_get(bp);
10503         if (rc)
10504                 goto init_err_pci_clean;
10505
10506         if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10507                 rc = bnxt_alloc_kong_hwrm_resources(bp);
10508                 if (rc)
10509                         bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10510         }
10511
10512         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10513             bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10514                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10515                 if (rc)
10516                         goto init_err_pci_clean;
10517         }
10518
10519         if (BNXT_CHIP_P5(bp))
10520                 bp->flags |= BNXT_FLAG_CHIP_P5;
10521
10522         rc = bnxt_hwrm_func_reset(bp);
10523         if (rc)
10524                 goto init_err_pci_clean;
10525
10526         bnxt_hwrm_fw_set_time(bp);
10527
10528         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10529                            NETIF_F_TSO | NETIF_F_TSO6 |
10530                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10531                            NETIF_F_GSO_IPXIP4 |
10532                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10533                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10534                            NETIF_F_RXCSUM | NETIF_F_GRO;
10535
10536         if (BNXT_SUPPORTS_TPA(bp))
10537                 dev->hw_features |= NETIF_F_LRO;
10538
10539         dev->hw_enc_features =
10540                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10541                         NETIF_F_TSO | NETIF_F_TSO6 |
10542                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10543                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10544                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10545         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10546                                     NETIF_F_GSO_GRE_CSUM;
10547         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10548         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10549                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10550         if (BNXT_SUPPORTS_TPA(bp))
10551                 dev->hw_features |= NETIF_F_GRO_HW;
10552         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10553         if (dev->features & NETIF_F_GRO_HW)
10554                 dev->features &= ~NETIF_F_LRO;
10555         dev->priv_flags |= IFF_UNICAST_FLT;
10556
10557 #ifdef CONFIG_BNXT_SRIOV
10558         init_waitqueue_head(&bp->sriov_cfg_wait);
10559         mutex_init(&bp->sriov_lock);
10560 #endif
10561         if (BNXT_SUPPORTS_TPA(bp)) {
10562                 bp->gro_func = bnxt_gro_func_5730x;
10563                 if (BNXT_CHIP_P4(bp))
10564                         bp->gro_func = bnxt_gro_func_5731x;
10565         }
10566         if (!BNXT_CHIP_P4_PLUS(bp))
10567                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10568
10569         rc = bnxt_hwrm_func_drv_rgtr(bp);
10570         if (rc)
10571                 goto init_err_pci_clean;
10572
10573         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10574         if (rc)
10575                 goto init_err_pci_clean;
10576
10577         bp->ulp_probe = bnxt_ulp_probe;
10578
10579         rc = bnxt_hwrm_queue_qportcfg(bp);
10580         if (rc) {
10581                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10582                            rc);
10583                 rc = -1;
10584                 goto init_err_pci_clean;
10585         }
10586         /* Get the MAX capabilities for this function */
10587         rc = bnxt_hwrm_func_qcaps(bp);
10588         if (rc) {
10589                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10590                            rc);
10591                 rc = -1;
10592                 goto init_err_pci_clean;
10593         }
10594         rc = bnxt_init_mac_addr(bp);
10595         if (rc) {
10596                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10597                 rc = -EADDRNOTAVAIL;
10598                 goto init_err_pci_clean;
10599         }
10600
10601         /* Read the adapter's DSN to use as the eswitch switch_id */
10602         rc = bnxt_pcie_dsn_get(bp, bp->switch_id);
10603         if (rc)
10604                 goto init_err_pci_clean;
10605
10606         bnxt_hwrm_func_qcfg(bp);
10607         bnxt_hwrm_vnic_qcaps(bp);
10608         bnxt_hwrm_port_led_qcaps(bp);
10609         bnxt_ethtool_init(bp);
10610         bnxt_dcb_init(bp);
10611
10612         /* MTU range: 60 - FW defined max */
10613         dev->min_mtu = ETH_ZLEN;
10614         dev->max_mtu = bp->max_mtu;
10615
10616         rc = bnxt_probe_phy(bp);
10617         if (rc)
10618                 goto init_err_pci_clean;
10619
10620         bnxt_set_rx_skb_mode(bp, false);
10621         bnxt_set_tpa_flags(bp);
10622         bnxt_set_ring_params(bp);
10623         rc = bnxt_set_dflt_rings(bp, true);
10624         if (rc) {
10625                 netdev_err(bp->dev, "Not enough rings available.\n");
10626                 rc = -ENOMEM;
10627                 goto init_err_pci_clean;
10628         }
10629
10630         /* Default RSS hash cfg. */
10631         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10632                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10633                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10634                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10635         if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10636                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10637                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10638                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10639         }
10640
10641         if (bnxt_rfs_supported(bp)) {
10642                 dev->hw_features |= NETIF_F_NTUPLE;
10643                 if (bnxt_rfs_capable(bp)) {
10644                         bp->flags |= BNXT_FLAG_RFS;
10645                         dev->features |= NETIF_F_NTUPLE;
10646                 }
10647         }
10648
10649         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10650                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10651
10652         rc = bnxt_init_int_mode(bp);
10653         if (rc)
10654                 goto init_err_pci_clean;
10655
10656         /* No TC has been set yet and rings may have been trimmed due to
10657          * limited MSIX, so we re-initialize the TX rings per TC.
10658          */
10659         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10660
10661         bnxt_get_wol_settings(bp);
10662         if (bp->flags & BNXT_FLAG_WOL_CAP)
10663                 device_set_wakeup_enable(&pdev->dev, bp->wol);
10664         else
10665                 device_set_wakeup_capable(&pdev->dev, false);
10666
10667         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10668
10669         bnxt_hwrm_coal_params_qcaps(bp);
10670
10671         if (BNXT_PF(bp)) {
10672                 if (!bnxt_pf_wq) {
10673                         bnxt_pf_wq =
10674                                 create_singlethread_workqueue("bnxt_pf_wq");
10675                         if (!bnxt_pf_wq) {
10676                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10677                                 goto init_err_pci_clean;
10678                         }
10679                 }
10680                 bnxt_init_tc(bp);
10681         }
10682
10683         rc = register_netdev(dev);
10684         if (rc)
10685                 goto init_err_cleanup_tc;
10686
10687         if (BNXT_PF(bp))
10688                 bnxt_dl_register(bp);
10689
10690         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10691                     board_info[ent->driver_data].name,
10692                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
10693         pcie_print_link_status(pdev);
10694
10695         return 0;
10696
10697 init_err_cleanup_tc:
10698         bnxt_shutdown_tc(bp);
10699         bnxt_clear_int_mode(bp);
10700
10701 init_err_pci_clean:
10702         bnxt_free_hwrm_resources(bp);
10703         bnxt_free_ctx_mem(bp);
10704         kfree(bp->ctx);
10705         bp->ctx = NULL;
10706         bnxt_cleanup_pci(bp);
10707
10708 init_err_free:
10709         free_netdev(dev);
10710         return rc;
10711 }
10712
10713 static void bnxt_shutdown(struct pci_dev *pdev)
10714 {
10715         struct net_device *dev = pci_get_drvdata(pdev);
10716         struct bnxt *bp;
10717
10718         if (!dev)
10719                 return;
10720
10721         rtnl_lock();
10722         bp = netdev_priv(dev);
10723         if (!bp)
10724                 goto shutdown_exit;
10725
10726         if (netif_running(dev))
10727                 dev_close(dev);
10728
10729         bnxt_ulp_shutdown(bp);
10730
10731         if (system_state == SYSTEM_POWER_OFF) {
10732                 bnxt_clear_int_mode(bp);
10733                 pci_wake_from_d3(pdev, bp->wol);
10734                 pci_set_power_state(pdev, PCI_D3hot);
10735         }
10736
10737 shutdown_exit:
10738         rtnl_unlock();
10739 }
10740
10741 #ifdef CONFIG_PM_SLEEP
10742 static int bnxt_suspend(struct device *device)
10743 {
10744         struct pci_dev *pdev = to_pci_dev(device);
10745         struct net_device *dev = pci_get_drvdata(pdev);
10746         struct bnxt *bp = netdev_priv(dev);
10747         int rc = 0;
10748
10749         rtnl_lock();
10750         if (netif_running(dev)) {
10751                 netif_device_detach(dev);
10752                 rc = bnxt_close(dev);
10753         }
10754         bnxt_hwrm_func_drv_unrgtr(bp);
10755         rtnl_unlock();
10756         return rc;
10757 }
10758
10759 static int bnxt_resume(struct device *device)
10760 {
10761         struct pci_dev *pdev = to_pci_dev(device);
10762         struct net_device *dev = pci_get_drvdata(pdev);
10763         struct bnxt *bp = netdev_priv(dev);
10764         int rc = 0;
10765
10766         rtnl_lock();
10767         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10768                 rc = -ENODEV;
10769                 goto resume_exit;
10770         }
10771         rc = bnxt_hwrm_func_reset(bp);
10772         if (rc) {
10773                 rc = -EBUSY;
10774                 goto resume_exit;
10775         }
10776         bnxt_get_wol_settings(bp);
10777         if (netif_running(dev)) {
10778                 rc = bnxt_open(dev);
10779                 if (!rc)
10780                         netif_device_attach(dev);
10781         }
10782
10783 resume_exit:
10784         rtnl_unlock();
10785         return rc;
10786 }
10787
10788 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10789 #define BNXT_PM_OPS (&bnxt_pm_ops)
10790
10791 #else
10792
10793 #define BNXT_PM_OPS NULL
10794
10795 #endif /* CONFIG_PM_SLEEP */
10796
10797 /**
10798  * bnxt_io_error_detected - called when PCI error is detected
10799  * @pdev: Pointer to PCI device
10800  * @state: The current pci connection state
10801  *
10802  * This function is called after a PCI bus error affecting
10803  * this device has been detected.
10804  */
10805 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10806                                                pci_channel_state_t state)
10807 {
10808         struct net_device *netdev = pci_get_drvdata(pdev);
10809         struct bnxt *bp = netdev_priv(netdev);
10810
10811         netdev_info(netdev, "PCI I/O error detected\n");
10812
10813         rtnl_lock();
10814         netif_device_detach(netdev);
10815
10816         bnxt_ulp_stop(bp);
10817
10818         if (state == pci_channel_io_perm_failure) {
10819                 rtnl_unlock();
10820                 return PCI_ERS_RESULT_DISCONNECT;
10821         }
10822
10823         if (netif_running(netdev))
10824                 bnxt_close(netdev);
10825
10826         pci_disable_device(pdev);
10827         rtnl_unlock();
10828
10829         /* Request a slot slot reset. */
10830         return PCI_ERS_RESULT_NEED_RESET;
10831 }
10832
10833 /**
10834  * bnxt_io_slot_reset - called after the pci bus has been reset.
10835  * @pdev: Pointer to PCI device
10836  *
10837  * Restart the card from scratch, as if from a cold-boot.
10838  * At this point, the card has exprienced a hard reset,
10839  * followed by fixups by BIOS, and has its config space
10840  * set up identically to what it was at cold boot.
10841  */
10842 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
10843 {
10844         struct net_device *netdev = pci_get_drvdata(pdev);
10845         struct bnxt *bp = netdev_priv(netdev);
10846         int err = 0;
10847         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
10848
10849         netdev_info(bp->dev, "PCI Slot Reset\n");
10850
10851         rtnl_lock();
10852
10853         if (pci_enable_device(pdev)) {
10854                 dev_err(&pdev->dev,
10855                         "Cannot re-enable PCI device after reset.\n");
10856         } else {
10857                 pci_set_master(pdev);
10858
10859                 err = bnxt_hwrm_func_reset(bp);
10860                 if (!err && netif_running(netdev))
10861                         err = bnxt_open(netdev);
10862
10863                 if (!err) {
10864                         result = PCI_ERS_RESULT_RECOVERED;
10865                         bnxt_ulp_start(bp);
10866                 }
10867         }
10868
10869         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
10870                 dev_close(netdev);
10871
10872         rtnl_unlock();
10873
10874         return PCI_ERS_RESULT_RECOVERED;
10875 }
10876
10877 /**
10878  * bnxt_io_resume - called when traffic can start flowing again.
10879  * @pdev: Pointer to PCI device
10880  *
10881  * This callback is called when the error recovery driver tells
10882  * us that its OK to resume normal operation.
10883  */
10884 static void bnxt_io_resume(struct pci_dev *pdev)
10885 {
10886         struct net_device *netdev = pci_get_drvdata(pdev);
10887
10888         rtnl_lock();
10889
10890         netif_device_attach(netdev);
10891
10892         rtnl_unlock();
10893 }
10894
10895 static const struct pci_error_handlers bnxt_err_handler = {
10896         .error_detected = bnxt_io_error_detected,
10897         .slot_reset     = bnxt_io_slot_reset,
10898         .resume         = bnxt_io_resume
10899 };
10900
10901 static struct pci_driver bnxt_pci_driver = {
10902         .name           = DRV_MODULE_NAME,
10903         .id_table       = bnxt_pci_tbl,
10904         .probe          = bnxt_init_one,
10905         .remove         = bnxt_remove_one,
10906         .shutdown       = bnxt_shutdown,
10907         .driver.pm      = BNXT_PM_OPS,
10908         .err_handler    = &bnxt_err_handler,
10909 #if defined(CONFIG_BNXT_SRIOV)
10910         .sriov_configure = bnxt_sriov_configure,
10911 #endif
10912 };
10913
10914 static int __init bnxt_init(void)
10915 {
10916         bnxt_debug_init();
10917         return pci_register_driver(&bnxt_pci_driver);
10918 }
10919
10920 static void __exit bnxt_exit(void)
10921 {
10922         pci_unregister_driver(&bnxt_pci_driver);
10923         if (bnxt_pf_wq)
10924                 destroy_workqueue(bnxt_pf_wq);
10925         bnxt_debug_exit();
10926 }
10927
10928 module_init(bnxt_init);
10929 module_exit(bnxt_exit);