1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
35 #include <linux/rtc.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <net/udp_tunnel.h>
42 #ifdef CONFIG_NET_RX_BUSY_POLL
43 #include <net/busy_poll.h>
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
55 #include "bnxt_sriov.h"
56 #include "bnxt_ethtool.h"
58 #define BNXT_TX_TIMEOUT (5 * HZ)
60 static const char version[] =
61 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63 MODULE_LICENSE("GPL");
64 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
65 MODULE_VERSION(DRV_MODULE_VERSION);
67 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
68 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
69 #define BNXT_RX_COPY_THRESH 256
71 #define BNXT_TX_PUSH_THRESH 164
104 /* indexed by enum above */
105 static const struct {
108 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
109 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
110 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
111 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
112 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
113 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
114 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
115 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
116 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
117 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
118 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
119 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
120 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
121 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
122 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
123 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
124 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
125 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
126 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
127 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
128 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
129 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
130 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
131 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
132 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
133 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
134 { "Broadcom NetXtreme-E Ethernet Virtual Function" },
135 { "Broadcom NetXtreme-C Ethernet Virtual Function" },
138 static const struct pci_device_id bnxt_pci_tbl[] = {
139 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
140 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
141 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
142 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
143 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
144 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
145 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
146 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
147 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
148 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
149 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
150 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
151 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
152 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
153 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
154 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
155 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
156 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
157 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
158 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
159 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
160 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
161 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
162 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
163 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
164 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
165 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
166 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
167 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
168 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
169 #ifdef CONFIG_BNXT_SRIOV
170 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
171 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
172 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
173 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
174 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
175 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
180 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
182 static const u16 bnxt_vf_req_snif[] = {
185 HWRM_CFA_L2_FILTER_ALLOC,
188 static const u16 bnxt_async_events_arr[] = {
189 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
190 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
191 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
192 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
193 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
196 static bool bnxt_vf_pciid(enum board_idx idx)
198 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
201 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
202 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
203 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
205 #define BNXT_CP_DB_REARM(db, raw_cons) \
206 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
208 #define BNXT_CP_DB(db, raw_cons) \
209 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
211 #define BNXT_CP_DB_IRQ_DIS(db) \
212 writel(DB_CP_IRQ_DIS_FLAGS, db)
214 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
216 /* Tell compiler to fetch tx indices from memory. */
219 return bp->tx_ring_size -
220 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
223 static const u16 bnxt_lhint_arr[] = {
224 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
225 TX_BD_FLAGS_LHINT_512_TO_1023,
226 TX_BD_FLAGS_LHINT_1024_TO_2047,
227 TX_BD_FLAGS_LHINT_1024_TO_2047,
228 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
229 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
230 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
231 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
232 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
233 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
234 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
235 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
236 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
237 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
238 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
239 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
240 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
241 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
242 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
245 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
247 struct bnxt *bp = netdev_priv(dev);
249 struct tx_bd_ext *txbd1;
250 struct netdev_queue *txq;
253 unsigned int length, pad = 0;
254 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
256 struct pci_dev *pdev = bp->pdev;
257 struct bnxt_tx_ring_info *txr;
258 struct bnxt_sw_tx_bd *tx_buf;
260 i = skb_get_queue_mapping(skb);
261 if (unlikely(i >= bp->tx_nr_rings)) {
262 dev_kfree_skb_any(skb);
266 txr = &bp->tx_ring[i];
267 txq = netdev_get_tx_queue(dev, i);
270 free_size = bnxt_tx_avail(bp, txr);
271 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
272 netif_tx_stop_queue(txq);
273 return NETDEV_TX_BUSY;
277 len = skb_headlen(skb);
278 last_frag = skb_shinfo(skb)->nr_frags;
280 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
282 txbd->tx_bd_opaque = prod;
284 tx_buf = &txr->tx_buf_ring[prod];
286 tx_buf->nr_frags = last_frag;
290 if (skb_vlan_tag_present(skb)) {
291 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
292 skb_vlan_tag_get(skb);
293 /* Currently supports 8021Q, 8021AD vlan offloads
294 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
296 if (skb->vlan_proto == htons(ETH_P_8021Q))
297 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
300 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
301 struct tx_push_buffer *tx_push_buf = txr->tx_push;
302 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
303 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
304 void *pdata = tx_push_buf->data;
308 /* Set COAL_NOW to be ready quickly for the next push */
309 tx_push->tx_bd_len_flags_type =
310 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
311 TX_BD_TYPE_LONG_TX_BD |
312 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
313 TX_BD_FLAGS_COAL_NOW |
314 TX_BD_FLAGS_PACKET_END |
315 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
317 if (skb->ip_summed == CHECKSUM_PARTIAL)
318 tx_push1->tx_bd_hsize_lflags =
319 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
321 tx_push1->tx_bd_hsize_lflags = 0;
323 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
324 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
326 end = pdata + length;
327 end = PTR_ALIGN(end, 8) - 1;
330 skb_copy_from_linear_data(skb, pdata, len);
332 for (j = 0; j < last_frag; j++) {
333 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
336 fptr = skb_frag_address_safe(frag);
340 memcpy(pdata, fptr, skb_frag_size(frag));
341 pdata += skb_frag_size(frag);
344 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
345 txbd->tx_bd_haddr = txr->data_mapping;
346 prod = NEXT_TX(prod);
347 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
348 memcpy(txbd, tx_push1, sizeof(*txbd));
349 prod = NEXT_TX(prod);
351 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
355 netdev_tx_sent_queue(txq, skb->len);
356 wmb(); /* Sync is_push and byte queue before pushing data */
358 push_len = (length + sizeof(*tx_push) + 7) / 8;
360 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
361 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
362 (push_len - 16) << 1);
364 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
372 if (length < BNXT_MIN_PKT_SIZE) {
373 pad = BNXT_MIN_PKT_SIZE - length;
374 if (skb_pad(skb, pad)) {
375 /* SKB already freed. */
379 length = BNXT_MIN_PKT_SIZE;
382 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
384 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
385 dev_kfree_skb_any(skb);
390 dma_unmap_addr_set(tx_buf, mapping, mapping);
391 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
392 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
394 txbd->tx_bd_haddr = cpu_to_le64(mapping);
396 prod = NEXT_TX(prod);
397 txbd1 = (struct tx_bd_ext *)
398 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
400 txbd1->tx_bd_hsize_lflags = 0;
401 if (skb_is_gso(skb)) {
404 if (skb->encapsulation)
405 hdr_len = skb_inner_network_offset(skb) +
406 skb_inner_network_header_len(skb) +
407 inner_tcp_hdrlen(skb);
409 hdr_len = skb_transport_offset(skb) +
412 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
414 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
415 length = skb_shinfo(skb)->gso_size;
416 txbd1->tx_bd_mss = cpu_to_le32(length);
418 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
419 txbd1->tx_bd_hsize_lflags =
420 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
421 txbd1->tx_bd_mss = 0;
425 flags |= bnxt_lhint_arr[length];
426 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
428 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
429 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
430 for (i = 0; i < last_frag; i++) {
431 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
433 prod = NEXT_TX(prod);
434 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
436 len = skb_frag_size(frag);
437 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
440 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
443 tx_buf = &txr->tx_buf_ring[prod];
444 dma_unmap_addr_set(tx_buf, mapping, mapping);
446 txbd->tx_bd_haddr = cpu_to_le64(mapping);
448 flags = len << TX_BD_LEN_SHIFT;
449 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
453 txbd->tx_bd_len_flags_type =
454 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
455 TX_BD_FLAGS_PACKET_END);
457 netdev_tx_sent_queue(txq, skb->len);
459 /* Sync BD data before updating doorbell */
462 prod = NEXT_TX(prod);
465 writel(DB_KEY_TX | prod, txr->tx_doorbell);
466 writel(DB_KEY_TX | prod, txr->tx_doorbell);
472 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
473 netif_tx_stop_queue(txq);
475 /* netif_tx_stop_queue() must be done before checking
476 * tx index in bnxt_tx_avail() below, because in
477 * bnxt_tx_int(), we update tx index before checking for
478 * netif_tx_queue_stopped().
481 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
482 netif_tx_wake_queue(txq);
489 /* start back at beginning and unmap skb */
491 tx_buf = &txr->tx_buf_ring[prod];
493 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
494 skb_headlen(skb), PCI_DMA_TODEVICE);
495 prod = NEXT_TX(prod);
497 /* unmap remaining mapped pages */
498 for (i = 0; i < last_frag; i++) {
499 prod = NEXT_TX(prod);
500 tx_buf = &txr->tx_buf_ring[prod];
501 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
502 skb_frag_size(&skb_shinfo(skb)->frags[i]),
506 dev_kfree_skb_any(skb);
510 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
512 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
513 int index = txr - &bp->tx_ring[0];
514 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
515 u16 cons = txr->tx_cons;
516 struct pci_dev *pdev = bp->pdev;
518 unsigned int tx_bytes = 0;
520 for (i = 0; i < nr_pkts; i++) {
521 struct bnxt_sw_tx_bd *tx_buf;
525 tx_buf = &txr->tx_buf_ring[cons];
526 cons = NEXT_TX(cons);
530 if (tx_buf->is_push) {
535 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
536 skb_headlen(skb), PCI_DMA_TODEVICE);
537 last = tx_buf->nr_frags;
539 for (j = 0; j < last; j++) {
540 cons = NEXT_TX(cons);
541 tx_buf = &txr->tx_buf_ring[cons];
544 dma_unmap_addr(tx_buf, mapping),
545 skb_frag_size(&skb_shinfo(skb)->frags[j]),
550 cons = NEXT_TX(cons);
552 tx_bytes += skb->len;
553 dev_kfree_skb_any(skb);
556 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
559 /* Need to make the tx_cons update visible to bnxt_start_xmit()
560 * before checking for netif_tx_queue_stopped(). Without the
561 * memory barrier, there is a small possibility that bnxt_start_xmit()
562 * will miss it and cause the queue to be stopped forever.
566 if (unlikely(netif_tx_queue_stopped(txq)) &&
567 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
568 __netif_tx_lock(txq, smp_processor_id());
569 if (netif_tx_queue_stopped(txq) &&
570 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
571 txr->dev_state != BNXT_DEV_STATE_CLOSING)
572 netif_tx_wake_queue(txq);
573 __netif_tx_unlock(txq);
577 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
581 struct pci_dev *pdev = bp->pdev;
583 data = kmalloc(bp->rx_buf_size, gfp);
587 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
588 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
590 if (dma_mapping_error(&pdev->dev, *mapping)) {
597 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
598 struct bnxt_rx_ring_info *rxr,
601 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
602 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
606 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
611 dma_unmap_addr_set(rx_buf, mapping, mapping);
613 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
618 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
621 u16 prod = rxr->rx_prod;
622 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
623 struct rx_bd *cons_bd, *prod_bd;
625 prod_rx_buf = &rxr->rx_buf_ring[prod];
626 cons_rx_buf = &rxr->rx_buf_ring[cons];
628 prod_rx_buf->data = data;
630 dma_unmap_addr_set(prod_rx_buf, mapping,
631 dma_unmap_addr(cons_rx_buf, mapping));
633 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
634 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
636 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
639 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
641 u16 next, max = rxr->rx_agg_bmap_size;
643 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
645 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
649 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
650 struct bnxt_rx_ring_info *rxr,
654 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
655 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
656 struct pci_dev *pdev = bp->pdev;
659 u16 sw_prod = rxr->rx_sw_agg_prod;
660 unsigned int offset = 0;
662 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
665 page = alloc_page(gfp);
669 rxr->rx_page_offset = 0;
671 offset = rxr->rx_page_offset;
672 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
673 if (rxr->rx_page_offset == PAGE_SIZE)
678 page = alloc_page(gfp);
683 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
685 if (dma_mapping_error(&pdev->dev, mapping)) {
690 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
691 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
693 __set_bit(sw_prod, rxr->rx_agg_bmap);
694 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
695 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
697 rx_agg_buf->page = page;
698 rx_agg_buf->offset = offset;
699 rx_agg_buf->mapping = mapping;
700 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
701 rxbd->rx_bd_opaque = sw_prod;
705 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
708 struct bnxt *bp = bnapi->bp;
709 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
710 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
711 u16 prod = rxr->rx_agg_prod;
712 u16 sw_prod = rxr->rx_sw_agg_prod;
715 for (i = 0; i < agg_bufs; i++) {
717 struct rx_agg_cmp *agg;
718 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
719 struct rx_bd *prod_bd;
722 agg = (struct rx_agg_cmp *)
723 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
724 cons = agg->rx_agg_cmp_opaque;
725 __clear_bit(cons, rxr->rx_agg_bmap);
727 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
728 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
730 __set_bit(sw_prod, rxr->rx_agg_bmap);
731 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
732 cons_rx_buf = &rxr->rx_agg_ring[cons];
734 /* It is possible for sw_prod to be equal to cons, so
735 * set cons_rx_buf->page to NULL first.
737 page = cons_rx_buf->page;
738 cons_rx_buf->page = NULL;
739 prod_rx_buf->page = page;
740 prod_rx_buf->offset = cons_rx_buf->offset;
742 prod_rx_buf->mapping = cons_rx_buf->mapping;
744 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
746 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
747 prod_bd->rx_bd_opaque = sw_prod;
749 prod = NEXT_RX_AGG(prod);
750 sw_prod = NEXT_RX_AGG(sw_prod);
751 cp_cons = NEXT_CMP(cp_cons);
753 rxr->rx_agg_prod = prod;
754 rxr->rx_sw_agg_prod = sw_prod;
757 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
758 struct bnxt_rx_ring_info *rxr, u16 cons,
759 u16 prod, u8 *data, dma_addr_t dma_addr,
765 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
767 bnxt_reuse_rx_data(rxr, cons, data);
771 skb = build_skb(data, 0);
772 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
779 skb_reserve(skb, BNXT_RX_OFFSET);
784 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
785 struct sk_buff *skb, u16 cp_cons,
788 struct pci_dev *pdev = bp->pdev;
789 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
790 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
791 u16 prod = rxr->rx_agg_prod;
794 for (i = 0; i < agg_bufs; i++) {
796 struct rx_agg_cmp *agg;
797 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
801 agg = (struct rx_agg_cmp *)
802 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
803 cons = agg->rx_agg_cmp_opaque;
804 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
805 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
807 cons_rx_buf = &rxr->rx_agg_ring[cons];
808 skb_fill_page_desc(skb, i, cons_rx_buf->page,
809 cons_rx_buf->offset, frag_len);
810 __clear_bit(cons, rxr->rx_agg_bmap);
812 /* It is possible for bnxt_alloc_rx_page() to allocate
813 * a sw_prod index that equals the cons index, so we
814 * need to clear the cons entry now.
816 mapping = dma_unmap_addr(cons_rx_buf, mapping);
817 page = cons_rx_buf->page;
818 cons_rx_buf->page = NULL;
820 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
821 struct skb_shared_info *shinfo;
822 unsigned int nr_frags;
824 shinfo = skb_shinfo(skb);
825 nr_frags = --shinfo->nr_frags;
826 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
830 cons_rx_buf->page = page;
832 /* Update prod since possibly some pages have been
835 rxr->rx_agg_prod = prod;
836 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
840 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
843 skb->data_len += frag_len;
844 skb->len += frag_len;
845 skb->truesize += PAGE_SIZE;
847 prod = NEXT_RX_AGG(prod);
848 cp_cons = NEXT_CMP(cp_cons);
850 rxr->rx_agg_prod = prod;
854 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
855 u8 agg_bufs, u32 *raw_cons)
858 struct rx_agg_cmp *agg;
860 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
861 last = RING_CMP(*raw_cons);
862 agg = (struct rx_agg_cmp *)
863 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
864 return RX_AGG_CMP_VALID(agg, *raw_cons);
867 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
871 struct bnxt *bp = bnapi->bp;
872 struct pci_dev *pdev = bp->pdev;
875 skb = napi_alloc_skb(&bnapi->napi, len);
879 dma_sync_single_for_cpu(&pdev->dev, mapping,
880 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
882 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
884 dma_sync_single_for_device(&pdev->dev, mapping,
892 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
893 u32 *raw_cons, void *cmp)
895 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
896 struct rx_cmp *rxcmp = cmp;
897 u32 tmp_raw_cons = *raw_cons;
898 u8 cmp_type, agg_bufs = 0;
900 cmp_type = RX_CMP_TYPE(rxcmp);
902 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
903 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
905 RX_CMP_AGG_BUFS_SHIFT;
906 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
907 struct rx_tpa_end_cmp *tpa_end = cmp;
909 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
910 RX_TPA_END_CMP_AGG_BUFS) >>
911 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
915 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
918 *raw_cons = tmp_raw_cons;
922 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
924 if (!rxr->bnapi->in_reset) {
925 rxr->bnapi->in_reset = true;
926 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
927 schedule_work(&bp->sp_task);
929 rxr->rx_next_cons = 0xffff;
932 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
933 struct rx_tpa_start_cmp *tpa_start,
934 struct rx_tpa_start_cmp_ext *tpa_start1)
936 u8 agg_id = TPA_START_AGG_ID(tpa_start);
938 struct bnxt_tpa_info *tpa_info;
939 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
940 struct rx_bd *prod_bd;
943 cons = tpa_start->rx_tpa_start_cmp_opaque;
945 cons_rx_buf = &rxr->rx_buf_ring[cons];
946 prod_rx_buf = &rxr->rx_buf_ring[prod];
947 tpa_info = &rxr->rx_tpa[agg_id];
949 if (unlikely(cons != rxr->rx_next_cons)) {
950 bnxt_sched_reset(bp, rxr);
954 prod_rx_buf->data = tpa_info->data;
956 mapping = tpa_info->mapping;
957 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
959 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
961 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
963 tpa_info->data = cons_rx_buf->data;
964 cons_rx_buf->data = NULL;
965 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
968 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
969 RX_TPA_START_CMP_LEN_SHIFT;
970 if (likely(TPA_START_HASH_VALID(tpa_start))) {
971 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
973 tpa_info->hash_type = PKT_HASH_TYPE_L4;
974 tpa_info->gso_type = SKB_GSO_TCPV4;
975 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
977 tpa_info->gso_type = SKB_GSO_TCPV6;
979 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
981 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
982 tpa_info->gso_type = 0;
983 if (netif_msg_rx_err(bp))
984 netdev_warn(bp->dev, "TPA packet without valid hash\n");
986 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
987 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
988 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
990 rxr->rx_prod = NEXT_RX(prod);
991 cons = NEXT_RX(cons);
992 rxr->rx_next_cons = NEXT_RX(cons);
993 cons_rx_buf = &rxr->rx_buf_ring[cons];
995 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
996 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
997 cons_rx_buf->data = NULL;
1000 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1001 u16 cp_cons, u32 agg_bufs)
1004 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1007 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1008 int payload_off, int tcp_ts,
1009 struct sk_buff *skb)
1014 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1015 u32 hdr_info = tpa_info->hdr_info;
1016 bool loopback = false;
1018 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1019 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1020 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1022 /* If the packet is an internal loopback packet, the offsets will
1023 * have an extra 4 bytes.
1025 if (inner_mac_off == 4) {
1027 } else if (inner_mac_off > 4) {
1028 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1031 /* We only support inner iPv4/ipv6. If we don't see the
1032 * correct protocol ID, it must be a loopback packet where
1033 * the offsets are off by 4.
1035 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1039 /* internal loopback packet, subtract all offsets by 4 */
1045 nw_off = inner_ip_off - ETH_HLEN;
1046 skb_set_network_header(skb, nw_off);
1047 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1048 struct ipv6hdr *iph = ipv6_hdr(skb);
1050 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1051 len = skb->len - skb_transport_offset(skb);
1053 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1055 struct iphdr *iph = ip_hdr(skb);
1057 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1058 len = skb->len - skb_transport_offset(skb);
1060 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1063 if (inner_mac_off) { /* tunnel */
1064 struct udphdr *uh = NULL;
1065 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1068 if (proto == htons(ETH_P_IP)) {
1069 struct iphdr *iph = (struct iphdr *)skb->data;
1071 if (iph->protocol == IPPROTO_UDP)
1072 uh = (struct udphdr *)(iph + 1);
1074 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1076 if (iph->nexthdr == IPPROTO_UDP)
1077 uh = (struct udphdr *)(iph + 1);
1081 skb_shinfo(skb)->gso_type |=
1082 SKB_GSO_UDP_TUNNEL_CSUM;
1084 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1091 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1092 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1094 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1095 int payload_off, int tcp_ts,
1096 struct sk_buff *skb)
1100 int len, nw_off, tcp_opt_len;
1105 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1108 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1110 skb_set_network_header(skb, nw_off);
1112 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1113 len = skb->len - skb_transport_offset(skb);
1115 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1116 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1117 struct ipv6hdr *iph;
1119 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1121 skb_set_network_header(skb, nw_off);
1122 iph = ipv6_hdr(skb);
1123 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1124 len = skb->len - skb_transport_offset(skb);
1126 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1128 dev_kfree_skb_any(skb);
1131 tcp_gro_complete(skb);
1133 if (nw_off) { /* tunnel */
1134 struct udphdr *uh = NULL;
1136 if (skb->protocol == htons(ETH_P_IP)) {
1137 struct iphdr *iph = (struct iphdr *)skb->data;
1139 if (iph->protocol == IPPROTO_UDP)
1140 uh = (struct udphdr *)(iph + 1);
1142 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1144 if (iph->nexthdr == IPPROTO_UDP)
1145 uh = (struct udphdr *)(iph + 1);
1149 skb_shinfo(skb)->gso_type |=
1150 SKB_GSO_UDP_TUNNEL_CSUM;
1152 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1159 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1160 struct bnxt_tpa_info *tpa_info,
1161 struct rx_tpa_end_cmp *tpa_end,
1162 struct rx_tpa_end_cmp_ext *tpa_end1,
1163 struct sk_buff *skb)
1169 segs = TPA_END_TPA_SEGS(tpa_end);
1173 NAPI_GRO_CB(skb)->count = segs;
1174 skb_shinfo(skb)->gso_size =
1175 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1176 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1177 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1178 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1179 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1180 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1185 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1186 struct bnxt_napi *bnapi,
1188 struct rx_tpa_end_cmp *tpa_end,
1189 struct rx_tpa_end_cmp_ext *tpa_end1,
1192 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1193 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1194 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1196 u16 cp_cons = RING_CMP(*raw_cons);
1198 struct bnxt_tpa_info *tpa_info;
1200 struct sk_buff *skb;
1202 if (unlikely(bnapi->in_reset)) {
1203 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1206 return ERR_PTR(-EBUSY);
1210 tpa_info = &rxr->rx_tpa[agg_id];
1211 data = tpa_info->data;
1213 len = tpa_info->len;
1214 mapping = tpa_info->mapping;
1216 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1217 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1220 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1221 return ERR_PTR(-EBUSY);
1224 cp_cons = NEXT_CMP(cp_cons);
1227 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1228 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1229 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1230 agg_bufs, (int)MAX_SKB_FRAGS);
1234 if (len <= bp->rx_copy_thresh) {
1235 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1237 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1242 dma_addr_t new_mapping;
1244 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1246 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1250 tpa_info->data = new_data;
1251 tpa_info->mapping = new_mapping;
1253 skb = build_skb(data, 0);
1254 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1255 PCI_DMA_FROMDEVICE);
1259 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1262 skb_reserve(skb, BNXT_RX_OFFSET);
1267 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1269 /* Page reuse already handled by bnxt_rx_pages(). */
1273 skb->protocol = eth_type_trans(skb, bp->dev);
1275 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1276 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1278 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1279 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1280 u16 vlan_proto = tpa_info->metadata >>
1281 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1282 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1284 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1287 skb_checksum_none_assert(skb);
1288 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1289 skb->ip_summed = CHECKSUM_UNNECESSARY;
1291 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1294 if (TPA_END_GRO(tpa_end))
1295 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1300 /* returns the following:
1301 * 1 - 1 packet successfully received
1302 * 0 - successful TPA_START, packet not completed yet
1303 * -EBUSY - completion ring does not have all the agg buffers yet
1304 * -ENOMEM - packet aborted due to out of memory
1305 * -EIO - packet aborted due to hw error indicated in BD
1307 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1310 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1311 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1312 struct net_device *dev = bp->dev;
1313 struct rx_cmp *rxcmp;
1314 struct rx_cmp_ext *rxcmp1;
1315 u32 tmp_raw_cons = *raw_cons;
1316 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1317 struct bnxt_sw_rx_bd *rx_buf;
1319 u8 *data, agg_bufs, cmp_type;
1320 dma_addr_t dma_addr;
1321 struct sk_buff *skb;
1324 rxcmp = (struct rx_cmp *)
1325 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1327 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1328 cp_cons = RING_CMP(tmp_raw_cons);
1329 rxcmp1 = (struct rx_cmp_ext *)
1330 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1332 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1335 cmp_type = RX_CMP_TYPE(rxcmp);
1337 prod = rxr->rx_prod;
1339 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1340 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1341 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1343 goto next_rx_no_prod;
1345 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1346 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1347 (struct rx_tpa_end_cmp *)rxcmp,
1348 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1351 if (unlikely(IS_ERR(skb)))
1356 skb_record_rx_queue(skb, bnapi->index);
1357 skb_mark_napi_id(skb, &bnapi->napi);
1358 if (bnxt_busy_polling(bnapi))
1359 netif_receive_skb(skb);
1361 napi_gro_receive(&bnapi->napi, skb);
1364 goto next_rx_no_prod;
1367 cons = rxcmp->rx_cmp_opaque;
1368 rx_buf = &rxr->rx_buf_ring[cons];
1369 data = rx_buf->data;
1370 if (unlikely(cons != rxr->rx_next_cons)) {
1371 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1373 bnxt_sched_reset(bp, rxr);
1378 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1379 RX_CMP_AGG_BUFS_SHIFT;
1382 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1385 cp_cons = NEXT_CMP(cp_cons);
1389 rx_buf->data = NULL;
1390 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1391 bnxt_reuse_rx_data(rxr, cons, data);
1393 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1399 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1400 dma_addr = dma_unmap_addr(rx_buf, mapping);
1402 if (len <= bp->rx_copy_thresh) {
1403 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1404 bnxt_reuse_rx_data(rxr, cons, data);
1410 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1418 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1425 if (RX_CMP_HASH_VALID(rxcmp)) {
1426 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1427 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1429 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1430 if (hash_type != 1 && hash_type != 3)
1431 type = PKT_HASH_TYPE_L3;
1432 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1435 skb->protocol = eth_type_trans(skb, dev);
1437 if ((rxcmp1->rx_cmp_flags2 &
1438 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1439 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1440 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1441 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1442 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1444 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1447 skb_checksum_none_assert(skb);
1448 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1449 if (dev->features & NETIF_F_RXCSUM) {
1450 skb->ip_summed = CHECKSUM_UNNECESSARY;
1451 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1454 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1455 if (dev->features & NETIF_F_RXCSUM)
1456 cpr->rx_l4_csum_errors++;
1460 skb_record_rx_queue(skb, bnapi->index);
1461 skb_mark_napi_id(skb, &bnapi->napi);
1462 if (bnxt_busy_polling(bnapi))
1463 netif_receive_skb(skb);
1465 napi_gro_receive(&bnapi->napi, skb);
1469 rxr->rx_prod = NEXT_RX(prod);
1470 rxr->rx_next_cons = NEXT_RX(cons);
1473 *raw_cons = tmp_raw_cons;
1478 #define BNXT_GET_EVENT_PORT(data) \
1480 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1482 static int bnxt_async_event_process(struct bnxt *bp,
1483 struct hwrm_async_event_cmpl *cmpl)
1485 u16 event_id = le16_to_cpu(cmpl->event_id);
1487 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1489 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1490 u32 data1 = le32_to_cpu(cmpl->event_data1);
1491 struct bnxt_link_info *link_info = &bp->link_info;
1494 goto async_event_process_exit;
1495 if (data1 & 0x20000) {
1496 u16 fw_speed = link_info->force_link_speed;
1497 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1499 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1504 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1505 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1507 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1508 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1510 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1511 u32 data1 = le32_to_cpu(cmpl->event_data1);
1512 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1517 if (bp->pf.port_id != port_id)
1520 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1523 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1525 goto async_event_process_exit;
1526 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1529 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1531 goto async_event_process_exit;
1533 schedule_work(&bp->sp_task);
1534 async_event_process_exit:
1538 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1540 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1541 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1542 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1543 (struct hwrm_fwd_req_cmpl *)txcmp;
1545 switch (cmpl_type) {
1546 case CMPL_BASE_TYPE_HWRM_DONE:
1547 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1548 if (seq_id == bp->hwrm_intr_seq_id)
1549 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1551 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1554 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1555 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1557 if ((vf_id < bp->pf.first_vf_id) ||
1558 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1559 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1564 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1565 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1566 schedule_work(&bp->sp_task);
1569 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1570 bnxt_async_event_process(bp,
1571 (struct hwrm_async_event_cmpl *)txcmp);
1580 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1582 struct bnxt_napi *bnapi = dev_instance;
1583 struct bnxt *bp = bnapi->bp;
1584 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1585 u32 cons = RING_CMP(cpr->cp_raw_cons);
1587 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1588 napi_schedule(&bnapi->napi);
1592 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1594 u32 raw_cons = cpr->cp_raw_cons;
1595 u16 cons = RING_CMP(raw_cons);
1596 struct tx_cmp *txcmp;
1598 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1600 return TX_CMP_VALID(txcmp, raw_cons);
1603 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1605 struct bnxt_napi *bnapi = dev_instance;
1606 struct bnxt *bp = bnapi->bp;
1607 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1608 u32 cons = RING_CMP(cpr->cp_raw_cons);
1611 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1613 if (!bnxt_has_work(bp, cpr)) {
1614 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1615 /* return if erroneous interrupt */
1616 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1620 /* disable ring IRQ */
1621 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1623 /* Return here if interrupt is shared and is disabled. */
1624 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1627 napi_schedule(&bnapi->napi);
1631 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1633 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1634 u32 raw_cons = cpr->cp_raw_cons;
1638 bool rx_event = false;
1639 bool agg_event = false;
1640 struct tx_cmp *txcmp;
1645 cons = RING_CMP(raw_cons);
1646 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1648 if (!TX_CMP_VALID(txcmp, raw_cons))
1651 /* The valid test of the entry must be done first before
1652 * reading any further.
1655 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1657 /* return full budget so NAPI will complete. */
1658 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1660 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1661 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1662 if (likely(rc >= 0))
1664 else if (rc == -EBUSY) /* partial completion */
1667 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1668 CMPL_BASE_TYPE_HWRM_DONE) ||
1669 (TX_CMP_TYPE(txcmp) ==
1670 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1671 (TX_CMP_TYPE(txcmp) ==
1672 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1673 bnxt_hwrm_handler(bp, txcmp);
1675 raw_cons = NEXT_RAW_CMP(raw_cons);
1677 if (rx_pkts == budget)
1681 cpr->cp_raw_cons = raw_cons;
1682 /* ACK completion ring before freeing tx ring and producing new
1683 * buffers in rx/agg rings to prevent overflowing the completion
1686 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1689 bnxt_tx_int(bp, bnapi, tx_pkts);
1692 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1694 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1695 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1697 writel(DB_KEY_RX | rxr->rx_agg_prod,
1698 rxr->rx_agg_doorbell);
1699 writel(DB_KEY_RX | rxr->rx_agg_prod,
1700 rxr->rx_agg_doorbell);
1706 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1708 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1709 struct bnxt *bp = bnapi->bp;
1710 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1711 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1712 struct tx_cmp *txcmp;
1713 struct rx_cmp_ext *rxcmp1;
1714 u32 cp_cons, tmp_raw_cons;
1715 u32 raw_cons = cpr->cp_raw_cons;
1717 bool agg_event = false;
1722 cp_cons = RING_CMP(raw_cons);
1723 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1725 if (!TX_CMP_VALID(txcmp, raw_cons))
1728 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1729 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1730 cp_cons = RING_CMP(tmp_raw_cons);
1731 rxcmp1 = (struct rx_cmp_ext *)
1732 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1734 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1737 /* force an error to recycle the buffer */
1738 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1739 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1741 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1742 if (likely(rc == -EIO))
1744 else if (rc == -EBUSY) /* partial completion */
1746 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1747 CMPL_BASE_TYPE_HWRM_DONE)) {
1748 bnxt_hwrm_handler(bp, txcmp);
1751 "Invalid completion received on special ring\n");
1753 raw_cons = NEXT_RAW_CMP(raw_cons);
1755 if (rx_pkts == budget)
1759 cpr->cp_raw_cons = raw_cons;
1760 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1761 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1762 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1765 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1766 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1769 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1770 napi_complete(napi);
1771 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1776 static int bnxt_poll(struct napi_struct *napi, int budget)
1778 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1779 struct bnxt *bp = bnapi->bp;
1780 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1783 if (!bnxt_lock_napi(bnapi))
1787 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1789 if (work_done >= budget)
1792 if (!bnxt_has_work(bp, cpr)) {
1793 napi_complete(napi);
1794 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1799 bnxt_unlock_napi(bnapi);
1803 #ifdef CONFIG_NET_RX_BUSY_POLL
1804 static int bnxt_busy_poll(struct napi_struct *napi)
1806 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1807 struct bnxt *bp = bnapi->bp;
1808 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1809 int rx_work, budget = 4;
1811 if (atomic_read(&bp->intr_sem) != 0)
1812 return LL_FLUSH_FAILED;
1814 if (!bnxt_lock_poll(bnapi))
1815 return LL_FLUSH_BUSY;
1817 rx_work = bnxt_poll_work(bp, bnapi, budget);
1819 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1821 bnxt_unlock_poll(bnapi);
1826 static void bnxt_free_tx_skbs(struct bnxt *bp)
1829 struct pci_dev *pdev = bp->pdev;
1834 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1835 for (i = 0; i < bp->tx_nr_rings; i++) {
1836 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1839 for (j = 0; j < max_idx;) {
1840 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1841 struct sk_buff *skb = tx_buf->skb;
1851 if (tx_buf->is_push) {
1857 dma_unmap_single(&pdev->dev,
1858 dma_unmap_addr(tx_buf, mapping),
1862 last = tx_buf->nr_frags;
1864 for (k = 0; k < last; k++, j++) {
1865 int ring_idx = j & bp->tx_ring_mask;
1866 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1868 tx_buf = &txr->tx_buf_ring[ring_idx];
1871 dma_unmap_addr(tx_buf, mapping),
1872 skb_frag_size(frag), PCI_DMA_TODEVICE);
1876 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1880 static void bnxt_free_rx_skbs(struct bnxt *bp)
1882 int i, max_idx, max_agg_idx;
1883 struct pci_dev *pdev = bp->pdev;
1888 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1889 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1890 for (i = 0; i < bp->rx_nr_rings; i++) {
1891 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1895 for (j = 0; j < MAX_TPA; j++) {
1896 struct bnxt_tpa_info *tpa_info =
1898 u8 *data = tpa_info->data;
1905 dma_unmap_addr(tpa_info, mapping),
1906 bp->rx_buf_use_size,
1907 PCI_DMA_FROMDEVICE);
1909 tpa_info->data = NULL;
1915 for (j = 0; j < max_idx; j++) {
1916 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1917 u8 *data = rx_buf->data;
1922 dma_unmap_single(&pdev->dev,
1923 dma_unmap_addr(rx_buf, mapping),
1924 bp->rx_buf_use_size,
1925 PCI_DMA_FROMDEVICE);
1927 rx_buf->data = NULL;
1932 for (j = 0; j < max_agg_idx; j++) {
1933 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1934 &rxr->rx_agg_ring[j];
1935 struct page *page = rx_agg_buf->page;
1940 dma_unmap_page(&pdev->dev,
1941 dma_unmap_addr(rx_agg_buf, mapping),
1942 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
1944 rx_agg_buf->page = NULL;
1945 __clear_bit(j, rxr->rx_agg_bmap);
1950 __free_page(rxr->rx_page);
1951 rxr->rx_page = NULL;
1956 static void bnxt_free_skbs(struct bnxt *bp)
1958 bnxt_free_tx_skbs(bp);
1959 bnxt_free_rx_skbs(bp);
1962 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1964 struct pci_dev *pdev = bp->pdev;
1967 for (i = 0; i < ring->nr_pages; i++) {
1968 if (!ring->pg_arr[i])
1971 dma_free_coherent(&pdev->dev, ring->page_size,
1972 ring->pg_arr[i], ring->dma_arr[i]);
1974 ring->pg_arr[i] = NULL;
1977 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1978 ring->pg_tbl, ring->pg_tbl_map);
1979 ring->pg_tbl = NULL;
1981 if (ring->vmem_size && *ring->vmem) {
1987 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1990 struct pci_dev *pdev = bp->pdev;
1992 if (ring->nr_pages > 1) {
1993 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2001 for (i = 0; i < ring->nr_pages; i++) {
2002 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2006 if (!ring->pg_arr[i])
2009 if (ring->nr_pages > 1)
2010 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2013 if (ring->vmem_size) {
2014 *ring->vmem = vzalloc(ring->vmem_size);
2021 static void bnxt_free_rx_rings(struct bnxt *bp)
2028 for (i = 0; i < bp->rx_nr_rings; i++) {
2029 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2030 struct bnxt_ring_struct *ring;
2035 kfree(rxr->rx_agg_bmap);
2036 rxr->rx_agg_bmap = NULL;
2038 ring = &rxr->rx_ring_struct;
2039 bnxt_free_ring(bp, ring);
2041 ring = &rxr->rx_agg_ring_struct;
2042 bnxt_free_ring(bp, ring);
2046 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2048 int i, rc, agg_rings = 0, tpa_rings = 0;
2053 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2056 if (bp->flags & BNXT_FLAG_TPA)
2059 for (i = 0; i < bp->rx_nr_rings; i++) {
2060 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2061 struct bnxt_ring_struct *ring;
2063 ring = &rxr->rx_ring_struct;
2065 rc = bnxt_alloc_ring(bp, ring);
2072 ring = &rxr->rx_agg_ring_struct;
2073 rc = bnxt_alloc_ring(bp, ring);
2077 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2078 mem_size = rxr->rx_agg_bmap_size / 8;
2079 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2080 if (!rxr->rx_agg_bmap)
2084 rxr->rx_tpa = kcalloc(MAX_TPA,
2085 sizeof(struct bnxt_tpa_info),
2095 static void bnxt_free_tx_rings(struct bnxt *bp)
2098 struct pci_dev *pdev = bp->pdev;
2103 for (i = 0; i < bp->tx_nr_rings; i++) {
2104 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2105 struct bnxt_ring_struct *ring;
2108 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2109 txr->tx_push, txr->tx_push_mapping);
2110 txr->tx_push = NULL;
2113 ring = &txr->tx_ring_struct;
2115 bnxt_free_ring(bp, ring);
2119 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2122 struct pci_dev *pdev = bp->pdev;
2124 bp->tx_push_size = 0;
2125 if (bp->tx_push_thresh) {
2128 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2129 bp->tx_push_thresh);
2131 if (push_size > 256) {
2133 bp->tx_push_thresh = 0;
2136 bp->tx_push_size = push_size;
2139 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2140 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2141 struct bnxt_ring_struct *ring;
2143 ring = &txr->tx_ring_struct;
2145 rc = bnxt_alloc_ring(bp, ring);
2149 if (bp->tx_push_size) {
2152 /* One pre-allocated DMA buffer to backup
2155 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2157 &txr->tx_push_mapping,
2163 mapping = txr->tx_push_mapping +
2164 sizeof(struct tx_push_bd);
2165 txr->data_mapping = cpu_to_le64(mapping);
2167 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2169 ring->queue_id = bp->q_info[j].queue_id;
2170 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2176 static void bnxt_free_cp_rings(struct bnxt *bp)
2183 for (i = 0; i < bp->cp_nr_rings; i++) {
2184 struct bnxt_napi *bnapi = bp->bnapi[i];
2185 struct bnxt_cp_ring_info *cpr;
2186 struct bnxt_ring_struct *ring;
2191 cpr = &bnapi->cp_ring;
2192 ring = &cpr->cp_ring_struct;
2194 bnxt_free_ring(bp, ring);
2198 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2202 for (i = 0; i < bp->cp_nr_rings; i++) {
2203 struct bnxt_napi *bnapi = bp->bnapi[i];
2204 struct bnxt_cp_ring_info *cpr;
2205 struct bnxt_ring_struct *ring;
2210 cpr = &bnapi->cp_ring;
2211 ring = &cpr->cp_ring_struct;
2213 rc = bnxt_alloc_ring(bp, ring);
2220 static void bnxt_init_ring_struct(struct bnxt *bp)
2224 for (i = 0; i < bp->cp_nr_rings; i++) {
2225 struct bnxt_napi *bnapi = bp->bnapi[i];
2226 struct bnxt_cp_ring_info *cpr;
2227 struct bnxt_rx_ring_info *rxr;
2228 struct bnxt_tx_ring_info *txr;
2229 struct bnxt_ring_struct *ring;
2234 cpr = &bnapi->cp_ring;
2235 ring = &cpr->cp_ring_struct;
2236 ring->nr_pages = bp->cp_nr_pages;
2237 ring->page_size = HW_CMPD_RING_SIZE;
2238 ring->pg_arr = (void **)cpr->cp_desc_ring;
2239 ring->dma_arr = cpr->cp_desc_mapping;
2240 ring->vmem_size = 0;
2242 rxr = bnapi->rx_ring;
2246 ring = &rxr->rx_ring_struct;
2247 ring->nr_pages = bp->rx_nr_pages;
2248 ring->page_size = HW_RXBD_RING_SIZE;
2249 ring->pg_arr = (void **)rxr->rx_desc_ring;
2250 ring->dma_arr = rxr->rx_desc_mapping;
2251 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2252 ring->vmem = (void **)&rxr->rx_buf_ring;
2254 ring = &rxr->rx_agg_ring_struct;
2255 ring->nr_pages = bp->rx_agg_nr_pages;
2256 ring->page_size = HW_RXBD_RING_SIZE;
2257 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2258 ring->dma_arr = rxr->rx_agg_desc_mapping;
2259 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2260 ring->vmem = (void **)&rxr->rx_agg_ring;
2263 txr = bnapi->tx_ring;
2267 ring = &txr->tx_ring_struct;
2268 ring->nr_pages = bp->tx_nr_pages;
2269 ring->page_size = HW_RXBD_RING_SIZE;
2270 ring->pg_arr = (void **)txr->tx_desc_ring;
2271 ring->dma_arr = txr->tx_desc_mapping;
2272 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2273 ring->vmem = (void **)&txr->tx_buf_ring;
2277 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2281 struct rx_bd **rx_buf_ring;
2283 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2284 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2288 rxbd = rx_buf_ring[i];
2292 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2293 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2294 rxbd->rx_bd_opaque = prod;
2299 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2301 struct net_device *dev = bp->dev;
2302 struct bnxt_rx_ring_info *rxr;
2303 struct bnxt_ring_struct *ring;
2307 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2308 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2310 if (NET_IP_ALIGN == 2)
2311 type |= RX_BD_FLAGS_SOP;
2313 rxr = &bp->rx_ring[ring_nr];
2314 ring = &rxr->rx_ring_struct;
2315 bnxt_init_rxbd_pages(ring, type);
2317 prod = rxr->rx_prod;
2318 for (i = 0; i < bp->rx_ring_size; i++) {
2319 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2320 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2321 ring_nr, i, bp->rx_ring_size);
2324 prod = NEXT_RX(prod);
2326 rxr->rx_prod = prod;
2327 ring->fw_ring_id = INVALID_HW_RING_ID;
2329 ring = &rxr->rx_agg_ring_struct;
2330 ring->fw_ring_id = INVALID_HW_RING_ID;
2332 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2335 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2336 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2338 bnxt_init_rxbd_pages(ring, type);
2340 prod = rxr->rx_agg_prod;
2341 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2342 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2343 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2344 ring_nr, i, bp->rx_ring_size);
2347 prod = NEXT_RX_AGG(prod);
2349 rxr->rx_agg_prod = prod;
2351 if (bp->flags & BNXT_FLAG_TPA) {
2356 for (i = 0; i < MAX_TPA; i++) {
2357 data = __bnxt_alloc_rx_data(bp, &mapping,
2362 rxr->rx_tpa[i].data = data;
2363 rxr->rx_tpa[i].mapping = mapping;
2366 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2374 static int bnxt_init_rx_rings(struct bnxt *bp)
2378 for (i = 0; i < bp->rx_nr_rings; i++) {
2379 rc = bnxt_init_one_rx_ring(bp, i);
2387 static int bnxt_init_tx_rings(struct bnxt *bp)
2391 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2394 for (i = 0; i < bp->tx_nr_rings; i++) {
2395 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2396 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2398 ring->fw_ring_id = INVALID_HW_RING_ID;
2404 static void bnxt_free_ring_grps(struct bnxt *bp)
2406 kfree(bp->grp_info);
2407 bp->grp_info = NULL;
2410 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2415 bp->grp_info = kcalloc(bp->cp_nr_rings,
2416 sizeof(struct bnxt_ring_grp_info),
2421 for (i = 0; i < bp->cp_nr_rings; i++) {
2423 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2424 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2425 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2426 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2427 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2432 static void bnxt_free_vnics(struct bnxt *bp)
2434 kfree(bp->vnic_info);
2435 bp->vnic_info = NULL;
2439 static int bnxt_alloc_vnics(struct bnxt *bp)
2443 #ifdef CONFIG_RFS_ACCEL
2444 if (bp->flags & BNXT_FLAG_RFS)
2445 num_vnics += bp->rx_nr_rings;
2448 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2451 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2456 bp->nr_vnics = num_vnics;
2460 static void bnxt_init_vnics(struct bnxt *bp)
2464 for (i = 0; i < bp->nr_vnics; i++) {
2465 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2467 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2468 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2469 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2470 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2472 if (bp->vnic_info[i].rss_hash_key) {
2474 prandom_bytes(vnic->rss_hash_key,
2477 memcpy(vnic->rss_hash_key,
2478 bp->vnic_info[0].rss_hash_key,
2484 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2488 pages = ring_size / desc_per_pg;
2495 while (pages & (pages - 1))
2501 static void bnxt_set_tpa_flags(struct bnxt *bp)
2503 bp->flags &= ~BNXT_FLAG_TPA;
2504 if (bp->dev->features & NETIF_F_LRO)
2505 bp->flags |= BNXT_FLAG_LRO;
2506 if (bp->dev->features & NETIF_F_GRO)
2507 bp->flags |= BNXT_FLAG_GRO;
2510 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2513 void bnxt_set_ring_params(struct bnxt *bp)
2515 u32 ring_size, rx_size, rx_space;
2516 u32 agg_factor = 0, agg_ring_size = 0;
2518 /* 8 for CRC and VLAN */
2519 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2521 rx_space = rx_size + NET_SKB_PAD +
2522 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2524 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2525 ring_size = bp->rx_ring_size;
2526 bp->rx_agg_ring_size = 0;
2527 bp->rx_agg_nr_pages = 0;
2529 if (bp->flags & BNXT_FLAG_TPA)
2530 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2532 bp->flags &= ~BNXT_FLAG_JUMBO;
2533 if (rx_space > PAGE_SIZE) {
2536 bp->flags |= BNXT_FLAG_JUMBO;
2537 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2538 if (jumbo_factor > agg_factor)
2539 agg_factor = jumbo_factor;
2541 agg_ring_size = ring_size * agg_factor;
2543 if (agg_ring_size) {
2544 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2546 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2547 u32 tmp = agg_ring_size;
2549 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2550 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2551 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2552 tmp, agg_ring_size);
2554 bp->rx_agg_ring_size = agg_ring_size;
2555 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2556 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2557 rx_space = rx_size + NET_SKB_PAD +
2558 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2561 bp->rx_buf_use_size = rx_size;
2562 bp->rx_buf_size = rx_space;
2564 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2565 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2567 ring_size = bp->tx_ring_size;
2568 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2569 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2571 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2572 bp->cp_ring_size = ring_size;
2574 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2575 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2576 bp->cp_nr_pages = MAX_CP_PAGES;
2577 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2578 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2579 ring_size, bp->cp_ring_size);
2581 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2582 bp->cp_ring_mask = bp->cp_bit - 1;
2585 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2588 struct bnxt_vnic_info *vnic;
2589 struct pci_dev *pdev = bp->pdev;
2594 for (i = 0; i < bp->nr_vnics; i++) {
2595 vnic = &bp->vnic_info[i];
2597 kfree(vnic->fw_grp_ids);
2598 vnic->fw_grp_ids = NULL;
2600 kfree(vnic->uc_list);
2601 vnic->uc_list = NULL;
2603 if (vnic->mc_list) {
2604 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2605 vnic->mc_list, vnic->mc_list_mapping);
2606 vnic->mc_list = NULL;
2609 if (vnic->rss_table) {
2610 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2612 vnic->rss_table_dma_addr);
2613 vnic->rss_table = NULL;
2616 vnic->rss_hash_key = NULL;
2621 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2623 int i, rc = 0, size;
2624 struct bnxt_vnic_info *vnic;
2625 struct pci_dev *pdev = bp->pdev;
2628 for (i = 0; i < bp->nr_vnics; i++) {
2629 vnic = &bp->vnic_info[i];
2631 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2632 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2635 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2636 if (!vnic->uc_list) {
2643 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2644 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2646 dma_alloc_coherent(&pdev->dev,
2648 &vnic->mc_list_mapping,
2650 if (!vnic->mc_list) {
2656 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2657 max_rings = bp->rx_nr_rings;
2661 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2662 if (!vnic->fw_grp_ids) {
2667 /* Allocate rss table and hash key */
2668 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2669 &vnic->rss_table_dma_addr,
2671 if (!vnic->rss_table) {
2676 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2678 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2679 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2687 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2689 struct pci_dev *pdev = bp->pdev;
2691 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2692 bp->hwrm_cmd_resp_dma_addr);
2694 bp->hwrm_cmd_resp_addr = NULL;
2695 if (bp->hwrm_dbg_resp_addr) {
2696 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2697 bp->hwrm_dbg_resp_addr,
2698 bp->hwrm_dbg_resp_dma_addr);
2700 bp->hwrm_dbg_resp_addr = NULL;
2704 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2706 struct pci_dev *pdev = bp->pdev;
2708 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2709 &bp->hwrm_cmd_resp_dma_addr,
2711 if (!bp->hwrm_cmd_resp_addr)
2713 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2714 HWRM_DBG_REG_BUF_SIZE,
2715 &bp->hwrm_dbg_resp_dma_addr,
2717 if (!bp->hwrm_dbg_resp_addr)
2718 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2723 static void bnxt_free_stats(struct bnxt *bp)
2726 struct pci_dev *pdev = bp->pdev;
2728 if (bp->hw_rx_port_stats) {
2729 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2730 bp->hw_rx_port_stats,
2731 bp->hw_rx_port_stats_map);
2732 bp->hw_rx_port_stats = NULL;
2733 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2739 size = sizeof(struct ctx_hw_stats);
2741 for (i = 0; i < bp->cp_nr_rings; i++) {
2742 struct bnxt_napi *bnapi = bp->bnapi[i];
2743 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2745 if (cpr->hw_stats) {
2746 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2748 cpr->hw_stats = NULL;
2753 static int bnxt_alloc_stats(struct bnxt *bp)
2756 struct pci_dev *pdev = bp->pdev;
2758 size = sizeof(struct ctx_hw_stats);
2760 for (i = 0; i < bp->cp_nr_rings; i++) {
2761 struct bnxt_napi *bnapi = bp->bnapi[i];
2762 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2764 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2770 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2773 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
2774 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2775 sizeof(struct tx_port_stats) + 1024;
2777 bp->hw_rx_port_stats =
2778 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2779 &bp->hw_rx_port_stats_map,
2781 if (!bp->hw_rx_port_stats)
2784 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2786 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2787 sizeof(struct rx_port_stats) + 512;
2788 bp->flags |= BNXT_FLAG_PORT_STATS;
2793 static void bnxt_clear_ring_indices(struct bnxt *bp)
2800 for (i = 0; i < bp->cp_nr_rings; i++) {
2801 struct bnxt_napi *bnapi = bp->bnapi[i];
2802 struct bnxt_cp_ring_info *cpr;
2803 struct bnxt_rx_ring_info *rxr;
2804 struct bnxt_tx_ring_info *txr;
2809 cpr = &bnapi->cp_ring;
2810 cpr->cp_raw_cons = 0;
2812 txr = bnapi->tx_ring;
2818 rxr = bnapi->rx_ring;
2821 rxr->rx_agg_prod = 0;
2822 rxr->rx_sw_agg_prod = 0;
2823 rxr->rx_next_cons = 0;
2828 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2830 #ifdef CONFIG_RFS_ACCEL
2833 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2834 * safe to delete the hash table.
2836 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2837 struct hlist_head *head;
2838 struct hlist_node *tmp;
2839 struct bnxt_ntuple_filter *fltr;
2841 head = &bp->ntp_fltr_hash_tbl[i];
2842 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2843 hlist_del(&fltr->hash);
2848 kfree(bp->ntp_fltr_bmap);
2849 bp->ntp_fltr_bmap = NULL;
2851 bp->ntp_fltr_count = 0;
2855 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2857 #ifdef CONFIG_RFS_ACCEL
2860 if (!(bp->flags & BNXT_FLAG_RFS))
2863 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2864 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2866 bp->ntp_fltr_count = 0;
2867 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2870 if (!bp->ntp_fltr_bmap)
2879 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2881 bnxt_free_vnic_attributes(bp);
2882 bnxt_free_tx_rings(bp);
2883 bnxt_free_rx_rings(bp);
2884 bnxt_free_cp_rings(bp);
2885 bnxt_free_ntp_fltrs(bp, irq_re_init);
2887 bnxt_free_stats(bp);
2888 bnxt_free_ring_grps(bp);
2889 bnxt_free_vnics(bp);
2897 bnxt_clear_ring_indices(bp);
2901 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2903 int i, j, rc, size, arr_size;
2907 /* Allocate bnapi mem pointer array and mem block for
2910 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2912 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2913 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2919 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2920 bp->bnapi[i] = bnapi;
2921 bp->bnapi[i]->index = i;
2922 bp->bnapi[i]->bp = bp;
2925 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2926 sizeof(struct bnxt_rx_ring_info),
2931 for (i = 0; i < bp->rx_nr_rings; i++) {
2932 bp->rx_ring[i].bnapi = bp->bnapi[i];
2933 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2936 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2937 sizeof(struct bnxt_tx_ring_info),
2942 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2945 j = bp->rx_nr_rings;
2947 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2948 bp->tx_ring[i].bnapi = bp->bnapi[j];
2949 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2952 rc = bnxt_alloc_stats(bp);
2956 rc = bnxt_alloc_ntp_fltrs(bp);
2960 rc = bnxt_alloc_vnics(bp);
2965 bnxt_init_ring_struct(bp);
2967 rc = bnxt_alloc_rx_rings(bp);
2971 rc = bnxt_alloc_tx_rings(bp);
2975 rc = bnxt_alloc_cp_rings(bp);
2979 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2980 BNXT_VNIC_UCAST_FLAG;
2981 rc = bnxt_alloc_vnic_attributes(bp);
2987 bnxt_free_mem(bp, true);
2991 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2992 u16 cmpl_ring, u16 target_id)
2994 struct input *req = request;
2996 req->req_type = cpu_to_le16(req_type);
2997 req->cmpl_ring = cpu_to_le16(cmpl_ring);
2998 req->target_id = cpu_to_le16(target_id);
2999 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3002 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3003 int timeout, bool silent)
3005 int i, intr_process, rc, tmo_count;
3006 struct input *req = msg;
3008 __le32 *resp_len, *valid;
3009 u16 cp_ring_id, len = 0;
3010 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3012 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3013 memset(resp, 0, PAGE_SIZE);
3014 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3015 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3017 /* Write request msg to hwrm channel */
3018 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3020 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
3021 writel(0, bp->bar0 + i);
3023 /* currently supports only one outstanding message */
3025 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3027 /* Ring channel doorbell */
3028 writel(1, bp->bar0 + 0x100);
3031 timeout = DFLT_HWRM_CMD_TIMEOUT;
3034 tmo_count = timeout * 40;
3036 /* Wait until hwrm response cmpl interrupt is processed */
3037 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3039 usleep_range(25, 40);
3042 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3043 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3044 le16_to_cpu(req->req_type));
3048 /* Check if response len is updated */
3049 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3050 for (i = 0; i < tmo_count; i++) {
3051 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3055 usleep_range(25, 40);
3058 if (i >= tmo_count) {
3059 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3060 timeout, le16_to_cpu(req->req_type),
3061 le16_to_cpu(req->seq_id), len);
3065 /* Last word of resp contains valid bit */
3066 valid = bp->hwrm_cmd_resp_addr + len - 4;
3067 for (i = 0; i < 5; i++) {
3068 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3074 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3075 timeout, le16_to_cpu(req->req_type),
3076 le16_to_cpu(req->seq_id), len, *valid);
3081 rc = le16_to_cpu(resp->error_code);
3083 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3084 le16_to_cpu(resp->req_type),
3085 le16_to_cpu(resp->seq_id), rc);
3089 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3091 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3094 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3098 mutex_lock(&bp->hwrm_cmd_lock);
3099 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3100 mutex_unlock(&bp->hwrm_cmd_lock);
3104 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3109 mutex_lock(&bp->hwrm_cmd_lock);
3110 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3111 mutex_unlock(&bp->hwrm_cmd_lock);
3115 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3117 struct hwrm_func_drv_rgtr_input req = {0};
3119 DECLARE_BITMAP(async_events_bmap, 256);
3120 u32 *events = (u32 *)async_events_bmap;
3122 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3125 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3126 FUNC_DRV_RGTR_REQ_ENABLES_VER |
3127 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3129 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3130 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3131 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3133 for (i = 0; i < 8; i++)
3134 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3136 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3137 req.ver_maj = DRV_VER_MAJ;
3138 req.ver_min = DRV_VER_MIN;
3139 req.ver_upd = DRV_VER_UPD;
3142 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3143 u32 *data = (u32 *)vf_req_snif_bmap;
3145 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3146 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3147 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3149 for (i = 0; i < 8; i++)
3150 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3153 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3156 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3159 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3161 struct hwrm_func_drv_unrgtr_input req = {0};
3163 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3164 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3167 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3170 struct hwrm_tunnel_dst_port_free_input req = {0};
3172 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3173 req.tunnel_type = tunnel_type;
3175 switch (tunnel_type) {
3176 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3177 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3179 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3180 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3186 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3188 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3193 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3197 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3198 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3200 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3202 req.tunnel_type = tunnel_type;
3203 req.tunnel_dst_port_val = port;
3205 mutex_lock(&bp->hwrm_cmd_lock);
3206 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3208 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3213 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
3214 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3216 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
3217 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3219 mutex_unlock(&bp->hwrm_cmd_lock);
3223 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3225 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3226 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3228 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3229 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3231 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3232 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3233 req.mask = cpu_to_le32(vnic->rx_mask);
3234 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3237 #ifdef CONFIG_RFS_ACCEL
3238 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3239 struct bnxt_ntuple_filter *fltr)
3241 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3243 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3244 req.ntuple_filter_id = fltr->filter_id;
3245 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3248 #define BNXT_NTP_FLTR_FLAGS \
3249 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3250 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3251 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3252 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3253 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3254 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3255 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3256 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3257 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3258 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3259 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3260 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3261 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3262 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3264 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3265 struct bnxt_ntuple_filter *fltr)
3268 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3269 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3270 bp->hwrm_cmd_resp_addr;
3271 struct flow_keys *keys = &fltr->fkeys;
3272 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3274 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3275 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3277 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3279 req.ethertype = htons(ETH_P_IP);
3280 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3281 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3282 req.ip_protocol = keys->basic.ip_proto;
3284 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3285 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3286 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3287 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3289 req.src_port = keys->ports.src;
3290 req.src_port_mask = cpu_to_be16(0xffff);
3291 req.dst_port = keys->ports.dst;
3292 req.dst_port_mask = cpu_to_be16(0xffff);
3294 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3295 mutex_lock(&bp->hwrm_cmd_lock);
3296 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3298 fltr->filter_id = resp->ntuple_filter_id;
3299 mutex_unlock(&bp->hwrm_cmd_lock);
3304 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3308 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3309 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3311 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3312 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3313 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3315 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3316 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3318 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3319 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3320 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3321 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3322 req.l2_addr_mask[0] = 0xff;
3323 req.l2_addr_mask[1] = 0xff;
3324 req.l2_addr_mask[2] = 0xff;
3325 req.l2_addr_mask[3] = 0xff;
3326 req.l2_addr_mask[4] = 0xff;
3327 req.l2_addr_mask[5] = 0xff;
3329 mutex_lock(&bp->hwrm_cmd_lock);
3330 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3332 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3334 mutex_unlock(&bp->hwrm_cmd_lock);
3338 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3340 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3343 /* Any associated ntuple filters will also be cleared by firmware. */
3344 mutex_lock(&bp->hwrm_cmd_lock);
3345 for (i = 0; i < num_of_vnics; i++) {
3346 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3348 for (j = 0; j < vnic->uc_filter_count; j++) {
3349 struct hwrm_cfa_l2_filter_free_input req = {0};
3351 bnxt_hwrm_cmd_hdr_init(bp, &req,
3352 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3354 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3356 rc = _hwrm_send_message(bp, &req, sizeof(req),
3359 vnic->uc_filter_count = 0;
3361 mutex_unlock(&bp->hwrm_cmd_lock);
3366 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3368 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3369 struct hwrm_vnic_tpa_cfg_input req = {0};
3371 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3374 u16 mss = bp->dev->mtu - 40;
3375 u32 nsegs, n, segs = 0, flags;
3377 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3378 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3379 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3380 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3381 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3382 if (tpa_flags & BNXT_FLAG_GRO)
3383 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3385 req.flags = cpu_to_le32(flags);
3388 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3389 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3390 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3392 /* Number of segs are log2 units, and first packet is not
3393 * included as part of this units.
3395 if (mss <= BNXT_RX_PAGE_SIZE) {
3396 n = BNXT_RX_PAGE_SIZE / mss;
3397 nsegs = (MAX_SKB_FRAGS - 1) * n;
3399 n = mss / BNXT_RX_PAGE_SIZE;
3400 if (mss & (BNXT_RX_PAGE_SIZE - 1))
3402 nsegs = (MAX_SKB_FRAGS - n) / n;
3405 segs = ilog2(nsegs);
3406 req.max_agg_segs = cpu_to_le16(segs);
3407 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3409 req.min_agg_len = cpu_to_le32(512);
3411 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3413 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3416 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3418 u32 i, j, max_rings;
3419 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3420 struct hwrm_vnic_rss_cfg_input req = {0};
3422 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3425 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3427 vnic->hash_type = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
3428 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
3429 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
3430 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
3432 req.hash_type = cpu_to_le32(vnic->hash_type);
3434 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3435 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3436 max_rings = bp->rx_nr_rings - 1;
3438 max_rings = bp->rx_nr_rings;
3443 /* Fill the RSS indirection table with ring group ids */
3444 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3447 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3450 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3451 req.hash_key_tbl_addr =
3452 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3454 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3455 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3458 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3460 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3461 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3463 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3464 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3465 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3466 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3468 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3469 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3470 /* thresholds not implemented in firmware yet */
3471 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3472 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3473 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3474 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3477 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3480 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3482 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3483 req.rss_cos_lb_ctx_id =
3484 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3486 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3487 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3490 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3494 for (i = 0; i < bp->nr_vnics; i++) {
3495 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3497 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3498 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3499 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3502 bp->rsscos_nr_ctxs = 0;
3505 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3508 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3509 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3510 bp->hwrm_cmd_resp_addr;
3512 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3515 mutex_lock(&bp->hwrm_cmd_lock);
3516 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3518 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3519 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3520 mutex_unlock(&bp->hwrm_cmd_lock);
3525 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3527 unsigned int ring = 0, grp_idx;
3528 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3529 struct hwrm_vnic_cfg_input req = {0};
3532 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3534 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
3535 /* Only RSS support for now TBD: COS & LB */
3536 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3537 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3538 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3539 VNIC_CFG_REQ_ENABLES_MRU);
3541 req.rss_rule = cpu_to_le16(0xffff);
3544 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3545 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
3546 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3547 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3549 req.cos_rule = cpu_to_le16(0xffff);
3552 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3554 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3556 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3557 ring = bp->rx_nr_rings - 1;
3559 grp_idx = bp->rx_ring[ring].bnapi->index;
3560 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3561 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3563 req.lb_rule = cpu_to_le16(0xffff);
3564 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3567 #ifdef CONFIG_BNXT_SRIOV
3569 def_vlan = bp->vf.vlan;
3571 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3572 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3574 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3577 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3581 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3582 struct hwrm_vnic_free_input req = {0};
3584 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3586 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3588 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3591 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3596 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3600 for (i = 0; i < bp->nr_vnics; i++)
3601 bnxt_hwrm_vnic_free_one(bp, i);
3604 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3605 unsigned int start_rx_ring_idx,
3606 unsigned int nr_rings)
3609 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3610 struct hwrm_vnic_alloc_input req = {0};
3611 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3613 /* map ring groups to this vnic */
3614 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3615 grp_idx = bp->rx_ring[i].bnapi->index;
3616 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3617 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3621 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3622 bp->grp_info[grp_idx].fw_grp_id;
3625 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3626 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
3628 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3630 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3632 mutex_lock(&bp->hwrm_cmd_lock);
3633 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3635 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3636 mutex_unlock(&bp->hwrm_cmd_lock);
3640 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3645 mutex_lock(&bp->hwrm_cmd_lock);
3646 for (i = 0; i < bp->rx_nr_rings; i++) {
3647 struct hwrm_ring_grp_alloc_input req = {0};
3648 struct hwrm_ring_grp_alloc_output *resp =
3649 bp->hwrm_cmd_resp_addr;
3650 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3652 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3654 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3655 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3656 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3657 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3659 rc = _hwrm_send_message(bp, &req, sizeof(req),
3664 bp->grp_info[grp_idx].fw_grp_id =
3665 le32_to_cpu(resp->ring_group_id);
3667 mutex_unlock(&bp->hwrm_cmd_lock);
3671 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3675 struct hwrm_ring_grp_free_input req = {0};
3680 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3682 mutex_lock(&bp->hwrm_cmd_lock);
3683 for (i = 0; i < bp->cp_nr_rings; i++) {
3684 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3687 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3689 rc = _hwrm_send_message(bp, &req, sizeof(req),
3693 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3695 mutex_unlock(&bp->hwrm_cmd_lock);
3699 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3700 struct bnxt_ring_struct *ring,
3701 u32 ring_type, u32 map_index,
3704 int rc = 0, err = 0;
3705 struct hwrm_ring_alloc_input req = {0};
3706 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3709 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3712 if (ring->nr_pages > 1) {
3713 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3714 /* Page size is in log2 units */
3715 req.page_size = BNXT_PAGE_SHIFT;
3716 req.page_tbl_depth = 1;
3718 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3721 /* Association of ring index with doorbell index and MSIX number */
3722 req.logical_id = cpu_to_le16(map_index);
3724 switch (ring_type) {
3725 case HWRM_RING_ALLOC_TX:
3726 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3727 /* Association of transmit ring with completion ring */
3729 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3730 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3731 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3732 req.queue_id = cpu_to_le16(ring->queue_id);
3734 case HWRM_RING_ALLOC_RX:
3735 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3736 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3738 case HWRM_RING_ALLOC_AGG:
3739 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3740 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3742 case HWRM_RING_ALLOC_CMPL:
3743 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3744 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3745 if (bp->flags & BNXT_FLAG_USING_MSIX)
3746 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3749 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3754 mutex_lock(&bp->hwrm_cmd_lock);
3755 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3756 err = le16_to_cpu(resp->error_code);
3757 ring_id = le16_to_cpu(resp->ring_id);
3758 mutex_unlock(&bp->hwrm_cmd_lock);
3761 switch (ring_type) {
3762 case RING_FREE_REQ_RING_TYPE_CMPL:
3763 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3767 case RING_FREE_REQ_RING_TYPE_RX:
3768 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3772 case RING_FREE_REQ_RING_TYPE_TX:
3773 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3778 netdev_err(bp->dev, "Invalid ring\n");
3782 ring->fw_ring_id = ring_id;
3786 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3790 for (i = 0; i < bp->cp_nr_rings; i++) {
3791 struct bnxt_napi *bnapi = bp->bnapi[i];
3792 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3793 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3795 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3796 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3797 INVALID_STATS_CTX_ID);
3800 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3801 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3804 for (i = 0; i < bp->tx_nr_rings; i++) {
3805 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3806 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3807 u32 map_idx = txr->bnapi->index;
3808 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3810 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3811 map_idx, fw_stats_ctx);
3814 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3817 for (i = 0; i < bp->rx_nr_rings; i++) {
3818 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3819 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3820 u32 map_idx = rxr->bnapi->index;
3822 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3823 map_idx, INVALID_STATS_CTX_ID);
3826 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3827 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3828 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3831 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3832 for (i = 0; i < bp->rx_nr_rings; i++) {
3833 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3834 struct bnxt_ring_struct *ring =
3835 &rxr->rx_agg_ring_struct;
3836 u32 grp_idx = rxr->bnapi->index;
3837 u32 map_idx = grp_idx + bp->rx_nr_rings;
3839 rc = hwrm_ring_alloc_send_msg(bp, ring,
3840 HWRM_RING_ALLOC_AGG,
3842 INVALID_STATS_CTX_ID);
3846 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3847 writel(DB_KEY_RX | rxr->rx_agg_prod,
3848 rxr->rx_agg_doorbell);
3849 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3856 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3857 struct bnxt_ring_struct *ring,
3858 u32 ring_type, int cmpl_ring_id)
3861 struct hwrm_ring_free_input req = {0};
3862 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3865 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3866 req.ring_type = ring_type;
3867 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3869 mutex_lock(&bp->hwrm_cmd_lock);
3870 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3871 error_code = le16_to_cpu(resp->error_code);
3872 mutex_unlock(&bp->hwrm_cmd_lock);
3874 if (rc || error_code) {
3875 switch (ring_type) {
3876 case RING_FREE_REQ_RING_TYPE_CMPL:
3877 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3880 case RING_FREE_REQ_RING_TYPE_RX:
3881 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3884 case RING_FREE_REQ_RING_TYPE_TX:
3885 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3889 netdev_err(bp->dev, "Invalid ring\n");
3896 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3903 for (i = 0; i < bp->tx_nr_rings; i++) {
3904 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3905 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3906 u32 grp_idx = txr->bnapi->index;
3907 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3909 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3910 hwrm_ring_free_send_msg(bp, ring,
3911 RING_FREE_REQ_RING_TYPE_TX,
3912 close_path ? cmpl_ring_id :
3913 INVALID_HW_RING_ID);
3914 ring->fw_ring_id = INVALID_HW_RING_ID;
3918 for (i = 0; i < bp->rx_nr_rings; i++) {
3919 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3920 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3921 u32 grp_idx = rxr->bnapi->index;
3922 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3924 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3925 hwrm_ring_free_send_msg(bp, ring,
3926 RING_FREE_REQ_RING_TYPE_RX,
3927 close_path ? cmpl_ring_id :
3928 INVALID_HW_RING_ID);
3929 ring->fw_ring_id = INVALID_HW_RING_ID;
3930 bp->grp_info[grp_idx].rx_fw_ring_id =
3935 for (i = 0; i < bp->rx_nr_rings; i++) {
3936 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3937 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3938 u32 grp_idx = rxr->bnapi->index;
3939 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3941 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3942 hwrm_ring_free_send_msg(bp, ring,
3943 RING_FREE_REQ_RING_TYPE_RX,
3944 close_path ? cmpl_ring_id :
3945 INVALID_HW_RING_ID);
3946 ring->fw_ring_id = INVALID_HW_RING_ID;
3947 bp->grp_info[grp_idx].agg_fw_ring_id =
3952 for (i = 0; i < bp->cp_nr_rings; i++) {
3953 struct bnxt_napi *bnapi = bp->bnapi[i];
3954 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3955 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3957 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3958 hwrm_ring_free_send_msg(bp, ring,
3959 RING_FREE_REQ_RING_TYPE_CMPL,
3960 INVALID_HW_RING_ID);
3961 ring->fw_ring_id = INVALID_HW_RING_ID;
3962 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3967 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3968 u32 buf_tmrs, u16 flags,
3969 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3971 req->flags = cpu_to_le16(flags);
3972 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3973 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3974 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3975 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3976 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3977 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3978 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3979 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3982 int bnxt_hwrm_set_coal(struct bnxt *bp)
3985 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3987 u16 max_buf, max_buf_irq;
3988 u16 buf_tmr, buf_tmr_irq;
3991 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3992 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3993 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3994 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3996 /* Each rx completion (2 records) should be DMAed immediately.
3997 * DMA 1/4 of the completion buffers at a time.
3999 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
4000 /* max_buf must not be zero */
4001 max_buf = clamp_t(u16, max_buf, 1, 63);
4002 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4003 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4004 /* buf timer set to 1/4 of interrupt timer */
4005 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4006 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4007 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4009 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4011 /* RING_IDLE generates more IRQs for lower latency. Enable it only
4012 * if coal_ticks is less than 25 us.
4014 if (bp->rx_coal_ticks < 25)
4015 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4017 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4018 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4020 /* max_buf must not be zero */
4021 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4022 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4023 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4024 /* buf timer set to 1/4 of interrupt timer */
4025 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4026 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4027 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4029 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4030 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4031 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
4033 mutex_lock(&bp->hwrm_cmd_lock);
4034 for (i = 0; i < bp->cp_nr_rings; i++) {
4035 struct bnxt_napi *bnapi = bp->bnapi[i];
4038 if (!bnapi->rx_ring)
4040 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4042 rc = _hwrm_send_message(bp, req, sizeof(*req),
4047 mutex_unlock(&bp->hwrm_cmd_lock);
4051 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4054 struct hwrm_stat_ctx_free_input req = {0};
4059 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4062 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4064 mutex_lock(&bp->hwrm_cmd_lock);
4065 for (i = 0; i < bp->cp_nr_rings; i++) {
4066 struct bnxt_napi *bnapi = bp->bnapi[i];
4067 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4069 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4070 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4072 rc = _hwrm_send_message(bp, &req, sizeof(req),
4077 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4080 mutex_unlock(&bp->hwrm_cmd_lock);
4084 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4087 struct hwrm_stat_ctx_alloc_input req = {0};
4088 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4090 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4093 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4095 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4097 mutex_lock(&bp->hwrm_cmd_lock);
4098 for (i = 0; i < bp->cp_nr_rings; i++) {
4099 struct bnxt_napi *bnapi = bp->bnapi[i];
4100 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4102 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4104 rc = _hwrm_send_message(bp, &req, sizeof(req),
4109 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4111 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4113 mutex_unlock(&bp->hwrm_cmd_lock);
4117 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4119 struct hwrm_func_qcfg_input req = {0};
4120 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4123 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4124 req.fid = cpu_to_le16(0xffff);
4125 mutex_lock(&bp->hwrm_cmd_lock);
4126 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4128 goto func_qcfg_exit;
4130 #ifdef CONFIG_BNXT_SRIOV
4132 struct bnxt_vf_info *vf = &bp->vf;
4134 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4137 switch (resp->port_partition_type) {
4138 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4139 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4140 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4141 bp->port_partition_type = resp->port_partition_type;
4146 mutex_unlock(&bp->hwrm_cmd_lock);
4150 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4153 struct hwrm_func_qcaps_input req = {0};
4154 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4156 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4157 req.fid = cpu_to_le16(0xffff);
4159 mutex_lock(&bp->hwrm_cmd_lock);
4160 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4162 goto hwrm_func_qcaps_exit;
4164 bp->tx_push_thresh = 0;
4166 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4167 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4170 struct bnxt_pf_info *pf = &bp->pf;
4172 pf->fw_fid = le16_to_cpu(resp->fid);
4173 pf->port_id = le16_to_cpu(resp->port_id);
4174 bp->dev->dev_port = pf->port_id;
4175 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4176 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4177 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4178 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4179 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4180 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4181 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4182 if (!pf->max_hw_ring_grps)
4183 pf->max_hw_ring_grps = pf->max_tx_rings;
4184 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4185 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4186 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4187 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4188 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4189 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4190 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4191 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4192 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4193 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4194 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4196 #ifdef CONFIG_BNXT_SRIOV
4197 struct bnxt_vf_info *vf = &bp->vf;
4199 vf->fw_fid = le16_to_cpu(resp->fid);
4201 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4202 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4203 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4204 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4205 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4206 if (!vf->max_hw_ring_grps)
4207 vf->max_hw_ring_grps = vf->max_tx_rings;
4208 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4209 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4210 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4212 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4213 mutex_unlock(&bp->hwrm_cmd_lock);
4215 if (is_valid_ether_addr(vf->mac_addr)) {
4216 /* overwrite netdev dev_adr with admin VF MAC */
4217 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4219 random_ether_addr(bp->dev->dev_addr);
4220 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4226 hwrm_func_qcaps_exit:
4227 mutex_unlock(&bp->hwrm_cmd_lock);
4231 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4233 struct hwrm_func_reset_input req = {0};
4235 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4238 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4241 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4244 struct hwrm_queue_qportcfg_input req = {0};
4245 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4248 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4250 mutex_lock(&bp->hwrm_cmd_lock);
4251 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4255 if (!resp->max_configurable_queues) {
4259 bp->max_tc = resp->max_configurable_queues;
4260 if (bp->max_tc > BNXT_MAX_QUEUE)
4261 bp->max_tc = BNXT_MAX_QUEUE;
4263 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4266 qptr = &resp->queue_id0;
4267 for (i = 0; i < bp->max_tc; i++) {
4268 bp->q_info[i].queue_id = *qptr++;
4269 bp->q_info[i].queue_profile = *qptr++;
4273 mutex_unlock(&bp->hwrm_cmd_lock);
4277 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4280 struct hwrm_ver_get_input req = {0};
4281 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4283 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4284 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4285 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4286 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4287 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4288 mutex_lock(&bp->hwrm_cmd_lock);
4289 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4291 goto hwrm_ver_get_exit;
4293 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4295 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4296 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4297 if (resp->hwrm_intf_maj < 1) {
4298 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4299 resp->hwrm_intf_maj, resp->hwrm_intf_min,
4300 resp->hwrm_intf_upd);
4301 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4303 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4304 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4305 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4307 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4308 if (!bp->hwrm_cmd_timeout)
4309 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4311 if (resp->hwrm_intf_maj >= 1)
4312 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4314 bp->chip_num = le16_to_cpu(resp->chip_num);
4315 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4317 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4320 mutex_unlock(&bp->hwrm_cmd_lock);
4324 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4326 #if IS_ENABLED(CONFIG_RTC_LIB)
4327 struct hwrm_fw_set_time_input req = {0};
4331 if (bp->hwrm_spec_code < 0x10400)
4334 do_gettimeofday(&tv);
4335 rtc_time_to_tm(tv.tv_sec, &tm);
4336 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4337 req.year = cpu_to_le16(1900 + tm.tm_year);
4338 req.month = 1 + tm.tm_mon;
4339 req.day = tm.tm_mday;
4340 req.hour = tm.tm_hour;
4341 req.minute = tm.tm_min;
4342 req.second = tm.tm_sec;
4343 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4349 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4352 struct bnxt_pf_info *pf = &bp->pf;
4353 struct hwrm_port_qstats_input req = {0};
4355 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4358 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4359 req.port_id = cpu_to_le16(pf->port_id);
4360 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4361 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4362 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4366 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4368 if (bp->vxlan_port_cnt) {
4369 bnxt_hwrm_tunnel_dst_port_free(
4370 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4372 bp->vxlan_port_cnt = 0;
4373 if (bp->nge_port_cnt) {
4374 bnxt_hwrm_tunnel_dst_port_free(
4375 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4377 bp->nge_port_cnt = 0;
4380 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4386 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4387 for (i = 0; i < bp->nr_vnics; i++) {
4388 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4390 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4398 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4402 for (i = 0; i < bp->nr_vnics; i++)
4403 bnxt_hwrm_vnic_set_rss(bp, i, false);
4406 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4409 if (bp->vnic_info) {
4410 bnxt_hwrm_clear_vnic_filter(bp);
4411 /* clear all RSS setting before free vnic ctx */
4412 bnxt_hwrm_clear_vnic_rss(bp);
4413 bnxt_hwrm_vnic_ctx_free(bp);
4414 /* before free the vnic, undo the vnic tpa settings */
4415 if (bp->flags & BNXT_FLAG_TPA)
4416 bnxt_set_tpa(bp, false);
4417 bnxt_hwrm_vnic_free(bp);
4419 bnxt_hwrm_ring_free(bp, close_path);
4420 bnxt_hwrm_ring_grp_free(bp);
4422 bnxt_hwrm_stat_ctx_free(bp);
4423 bnxt_hwrm_free_tunnel_ports(bp);
4427 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4431 /* allocate context for vnic */
4432 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
4434 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4436 goto vnic_setup_err;
4438 bp->rsscos_nr_ctxs++;
4440 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4441 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4443 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4445 goto vnic_setup_err;
4447 bp->rsscos_nr_ctxs++;
4450 /* configure default vnic, ring grp */
4451 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4453 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4455 goto vnic_setup_err;
4458 /* Enable RSS hashing on vnic */
4459 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4461 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4463 goto vnic_setup_err;
4466 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4467 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4469 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4478 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4480 #ifdef CONFIG_RFS_ACCEL
4483 for (i = 0; i < bp->rx_nr_rings; i++) {
4484 u16 vnic_id = i + 1;
4487 if (vnic_id >= bp->nr_vnics)
4490 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
4491 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4493 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4497 rc = bnxt_setup_vnic(bp, vnic_id);
4507 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4508 static bool bnxt_promisc_ok(struct bnxt *bp)
4510 #ifdef CONFIG_BNXT_SRIOV
4511 if (BNXT_VF(bp) && !bp->vf.vlan)
4517 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4519 unsigned int rc = 0;
4521 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4523 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4528 rc = bnxt_hwrm_vnic_cfg(bp, 1);
4530 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4537 static int bnxt_cfg_rx_mode(struct bnxt *);
4538 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4540 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4542 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4544 unsigned int rx_nr_rings = bp->rx_nr_rings;
4547 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4549 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4555 rc = bnxt_hwrm_ring_alloc(bp);
4557 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4561 rc = bnxt_hwrm_ring_grp_alloc(bp);
4563 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4567 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4570 /* default vnic 0 */
4571 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
4573 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4577 rc = bnxt_setup_vnic(bp, 0);
4581 if (bp->flags & BNXT_FLAG_RFS) {
4582 rc = bnxt_alloc_rfs_vnics(bp);
4587 if (bp->flags & BNXT_FLAG_TPA) {
4588 rc = bnxt_set_tpa(bp, true);
4594 bnxt_update_vf_mac(bp);
4596 /* Filter for default vnic 0 */
4597 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4599 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4602 vnic->uc_filter_count = 1;
4604 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4606 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
4607 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4609 if (bp->dev->flags & IFF_ALLMULTI) {
4610 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4611 vnic->mc_list_count = 0;
4615 bnxt_mc_list_updated(bp, &mask);
4616 vnic->rx_mask |= mask;
4619 rc = bnxt_cfg_rx_mode(bp);
4623 rc = bnxt_hwrm_set_coal(bp);
4625 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4628 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4629 rc = bnxt_setup_nitroa0_vnic(bp);
4631 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
4636 bnxt_hwrm_func_qcfg(bp);
4637 netdev_update_features(bp->dev);
4643 bnxt_hwrm_resource_free(bp, 0, true);
4648 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4650 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4654 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4656 bnxt_init_rx_rings(bp);
4657 bnxt_init_tx_rings(bp);
4658 bnxt_init_ring_grps(bp, irq_re_init);
4659 bnxt_init_vnics(bp);
4661 return bnxt_init_chip(bp, irq_re_init);
4664 static void bnxt_disable_int(struct bnxt *bp)
4671 for (i = 0; i < bp->cp_nr_rings; i++) {
4672 struct bnxt_napi *bnapi = bp->bnapi[i];
4673 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4675 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4679 static void bnxt_enable_int(struct bnxt *bp)
4683 atomic_set(&bp->intr_sem, 0);
4684 for (i = 0; i < bp->cp_nr_rings; i++) {
4685 struct bnxt_napi *bnapi = bp->bnapi[i];
4686 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4688 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4692 static int bnxt_set_real_num_queues(struct bnxt *bp)
4695 struct net_device *dev = bp->dev;
4697 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4701 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4705 #ifdef CONFIG_RFS_ACCEL
4706 if (bp->flags & BNXT_FLAG_RFS)
4707 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4713 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4716 int _rx = *rx, _tx = *tx;
4719 *rx = min_t(int, _rx, max);
4720 *tx = min_t(int, _tx, max);
4725 while (_rx + _tx > max) {
4726 if (_rx > _tx && _rx > 1)
4737 static int bnxt_setup_msix(struct bnxt *bp)
4739 struct msix_entry *msix_ent;
4740 struct net_device *dev = bp->dev;
4741 int i, total_vecs, rc = 0, min = 1;
4742 const int len = sizeof(bp->irq_tbl[0].name);
4744 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4745 total_vecs = bp->cp_nr_rings;
4747 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4751 for (i = 0; i < total_vecs; i++) {
4752 msix_ent[i].entry = i;
4753 msix_ent[i].vector = 0;
4756 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4759 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4760 if (total_vecs < 0) {
4762 goto msix_setup_exit;
4765 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4769 /* Trim rings based upon num of vectors allocated */
4770 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4771 total_vecs, min == 1);
4773 goto msix_setup_exit;
4775 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4776 tcs = netdev_get_num_tc(dev);
4778 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4779 if (bp->tx_nr_rings_per_tc == 0) {
4780 netdev_reset_tc(dev);
4781 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4785 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4786 for (i = 0; i < tcs; i++) {
4787 count = bp->tx_nr_rings_per_tc;
4789 netdev_set_tc_queue(dev, i, count, off);
4793 bp->cp_nr_rings = total_vecs;
4795 for (i = 0; i < bp->cp_nr_rings; i++) {
4798 bp->irq_tbl[i].vector = msix_ent[i].vector;
4799 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4801 else if (i < bp->rx_nr_rings)
4806 snprintf(bp->irq_tbl[i].name, len,
4807 "%s-%s-%d", dev->name, attr, i);
4808 bp->irq_tbl[i].handler = bnxt_msix;
4810 rc = bnxt_set_real_num_queues(bp);
4812 goto msix_setup_exit;
4815 goto msix_setup_exit;
4817 bp->flags |= BNXT_FLAG_USING_MSIX;
4822 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4823 pci_disable_msix(bp->pdev);
4828 static int bnxt_setup_inta(struct bnxt *bp)
4831 const int len = sizeof(bp->irq_tbl[0].name);
4833 if (netdev_get_num_tc(bp->dev))
4834 netdev_reset_tc(bp->dev);
4836 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4841 bp->rx_nr_rings = 1;
4842 bp->tx_nr_rings = 1;
4843 bp->cp_nr_rings = 1;
4844 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4845 bp->flags |= BNXT_FLAG_SHARED_RINGS;
4846 bp->irq_tbl[0].vector = bp->pdev->irq;
4847 snprintf(bp->irq_tbl[0].name, len,
4848 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4849 bp->irq_tbl[0].handler = bnxt_inta;
4850 rc = bnxt_set_real_num_queues(bp);
4854 static int bnxt_setup_int_mode(struct bnxt *bp)
4858 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4859 rc = bnxt_setup_msix(bp);
4861 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
4862 /* fallback to INTA */
4863 rc = bnxt_setup_inta(bp);
4868 static void bnxt_free_irq(struct bnxt *bp)
4870 struct bnxt_irq *irq;
4873 #ifdef CONFIG_RFS_ACCEL
4874 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4875 bp->dev->rx_cpu_rmap = NULL;
4880 for (i = 0; i < bp->cp_nr_rings; i++) {
4881 irq = &bp->irq_tbl[i];
4883 free_irq(irq->vector, bp->bnapi[i]);
4886 if (bp->flags & BNXT_FLAG_USING_MSIX)
4887 pci_disable_msix(bp->pdev);
4892 static int bnxt_request_irq(struct bnxt *bp)
4895 unsigned long flags = 0;
4896 #ifdef CONFIG_RFS_ACCEL
4897 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4900 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4901 flags = IRQF_SHARED;
4903 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4904 struct bnxt_irq *irq = &bp->irq_tbl[i];
4905 #ifdef CONFIG_RFS_ACCEL
4906 if (rmap && bp->bnapi[i]->rx_ring) {
4907 rc = irq_cpu_rmap_add(rmap, irq->vector);
4909 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4914 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4924 static void bnxt_del_napi(struct bnxt *bp)
4931 for (i = 0; i < bp->cp_nr_rings; i++) {
4932 struct bnxt_napi *bnapi = bp->bnapi[i];
4934 napi_hash_del(&bnapi->napi);
4935 netif_napi_del(&bnapi->napi);
4939 static void bnxt_init_napi(struct bnxt *bp)
4942 unsigned int cp_nr_rings = bp->cp_nr_rings;
4943 struct bnxt_napi *bnapi;
4945 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4946 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4948 for (i = 0; i < cp_nr_rings; i++) {
4949 bnapi = bp->bnapi[i];
4950 netif_napi_add(bp->dev, &bnapi->napi,
4953 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4954 bnapi = bp->bnapi[cp_nr_rings];
4955 netif_napi_add(bp->dev, &bnapi->napi,
4956 bnxt_poll_nitroa0, 64);
4957 napi_hash_add(&bnapi->napi);
4960 bnapi = bp->bnapi[0];
4961 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4965 static void bnxt_disable_napi(struct bnxt *bp)
4972 for (i = 0; i < bp->cp_nr_rings; i++) {
4973 napi_disable(&bp->bnapi[i]->napi);
4974 bnxt_disable_poll(bp->bnapi[i]);
4978 static void bnxt_enable_napi(struct bnxt *bp)
4982 for (i = 0; i < bp->cp_nr_rings; i++) {
4983 bp->bnapi[i]->in_reset = false;
4984 bnxt_enable_poll(bp->bnapi[i]);
4985 napi_enable(&bp->bnapi[i]->napi);
4989 static void bnxt_tx_disable(struct bnxt *bp)
4992 struct bnxt_tx_ring_info *txr;
4993 struct netdev_queue *txq;
4996 for (i = 0; i < bp->tx_nr_rings; i++) {
4997 txr = &bp->tx_ring[i];
4998 txq = netdev_get_tx_queue(bp->dev, i);
4999 txr->dev_state = BNXT_DEV_STATE_CLOSING;
5002 /* Stop all TX queues */
5003 netif_tx_disable(bp->dev);
5004 netif_carrier_off(bp->dev);
5007 static void bnxt_tx_enable(struct bnxt *bp)
5010 struct bnxt_tx_ring_info *txr;
5011 struct netdev_queue *txq;
5013 for (i = 0; i < bp->tx_nr_rings; i++) {
5014 txr = &bp->tx_ring[i];
5015 txq = netdev_get_tx_queue(bp->dev, i);
5018 netif_tx_wake_all_queues(bp->dev);
5019 if (bp->link_info.link_up)
5020 netif_carrier_on(bp->dev);
5023 static void bnxt_report_link(struct bnxt *bp)
5025 if (bp->link_info.link_up) {
5027 const char *flow_ctrl;
5030 netif_carrier_on(bp->dev);
5031 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5035 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5036 flow_ctrl = "ON - receive & transmit";
5037 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5038 flow_ctrl = "ON - transmit";
5039 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5040 flow_ctrl = "ON - receive";
5043 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5044 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5045 speed, duplex, flow_ctrl);
5046 if (bp->flags & BNXT_FLAG_EEE_CAP)
5047 netdev_info(bp->dev, "EEE is %s\n",
5048 bp->eee.eee_active ? "active" :
5051 netif_carrier_off(bp->dev);
5052 netdev_err(bp->dev, "NIC Link is Down\n");
5056 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5059 struct hwrm_port_phy_qcaps_input req = {0};
5060 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5061 struct bnxt_link_info *link_info = &bp->link_info;
5063 if (bp->hwrm_spec_code < 0x10201)
5066 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5068 mutex_lock(&bp->hwrm_cmd_lock);
5069 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5071 goto hwrm_phy_qcaps_exit;
5073 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5074 struct ethtool_eee *eee = &bp->eee;
5075 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5077 bp->flags |= BNXT_FLAG_EEE_CAP;
5078 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5079 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5080 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5081 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5082 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5084 link_info->support_auto_speeds =
5085 le16_to_cpu(resp->supported_speeds_auto_mode);
5087 hwrm_phy_qcaps_exit:
5088 mutex_unlock(&bp->hwrm_cmd_lock);
5092 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5095 struct bnxt_link_info *link_info = &bp->link_info;
5096 struct hwrm_port_phy_qcfg_input req = {0};
5097 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5098 u8 link_up = link_info->link_up;
5100 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5102 mutex_lock(&bp->hwrm_cmd_lock);
5103 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5105 mutex_unlock(&bp->hwrm_cmd_lock);
5109 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5110 link_info->phy_link_status = resp->link;
5111 link_info->duplex = resp->duplex;
5112 link_info->pause = resp->pause;
5113 link_info->auto_mode = resp->auto_mode;
5114 link_info->auto_pause_setting = resp->auto_pause;
5115 link_info->lp_pause = resp->link_partner_adv_pause;
5116 link_info->force_pause_setting = resp->force_pause;
5117 link_info->duplex_setting = resp->duplex;
5118 if (link_info->phy_link_status == BNXT_LINK_LINK)
5119 link_info->link_speed = le16_to_cpu(resp->link_speed);
5121 link_info->link_speed = 0;
5122 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5123 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5124 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5125 link_info->lp_auto_link_speeds =
5126 le16_to_cpu(resp->link_partner_adv_speeds);
5127 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5128 link_info->phy_ver[0] = resp->phy_maj;
5129 link_info->phy_ver[1] = resp->phy_min;
5130 link_info->phy_ver[2] = resp->phy_bld;
5131 link_info->media_type = resp->media_type;
5132 link_info->phy_type = resp->phy_type;
5133 link_info->transceiver = resp->xcvr_pkg_type;
5134 link_info->phy_addr = resp->eee_config_phy_addr &
5135 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5136 link_info->module_status = resp->module_status;
5138 if (bp->flags & BNXT_FLAG_EEE_CAP) {
5139 struct ethtool_eee *eee = &bp->eee;
5142 eee->eee_active = 0;
5143 if (resp->eee_config_phy_addr &
5144 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5145 eee->eee_active = 1;
5146 fw_speeds = le16_to_cpu(
5147 resp->link_partner_adv_eee_link_speed_mask);
5148 eee->lp_advertised =
5149 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5152 /* Pull initial EEE config */
5153 if (!chng_link_state) {
5154 if (resp->eee_config_phy_addr &
5155 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5156 eee->eee_enabled = 1;
5158 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5160 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5162 if (resp->eee_config_phy_addr &
5163 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5166 eee->tx_lpi_enabled = 1;
5167 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5168 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5169 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5173 /* TODO: need to add more logic to report VF link */
5174 if (chng_link_state) {
5175 if (link_info->phy_link_status == BNXT_LINK_LINK)
5176 link_info->link_up = 1;
5178 link_info->link_up = 0;
5179 if (link_up != link_info->link_up)
5180 bnxt_report_link(bp);
5182 /* alwasy link down if not require to update link state */
5183 link_info->link_up = 0;
5185 mutex_unlock(&bp->hwrm_cmd_lock);
5189 static void bnxt_get_port_module_status(struct bnxt *bp)
5191 struct bnxt_link_info *link_info = &bp->link_info;
5192 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5195 if (bnxt_update_link(bp, true))
5198 module_status = link_info->module_status;
5199 switch (module_status) {
5200 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5201 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5202 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5203 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5205 if (bp->hwrm_spec_code >= 0x10201) {
5206 netdev_warn(bp->dev, "Module part number %s\n",
5207 resp->phy_vendor_partnumber);
5209 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5210 netdev_warn(bp->dev, "TX is disabled\n");
5211 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5212 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5217 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5219 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
5220 if (bp->hwrm_spec_code >= 0x10201)
5222 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
5223 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5224 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5225 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5226 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
5228 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5230 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5231 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5232 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5233 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5235 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5236 if (bp->hwrm_spec_code >= 0x10201) {
5237 req->auto_pause = req->force_pause;
5238 req->enables |= cpu_to_le32(
5239 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5244 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5245 struct hwrm_port_phy_cfg_input *req)
5247 u8 autoneg = bp->link_info.autoneg;
5248 u16 fw_link_speed = bp->link_info.req_link_speed;
5249 u32 advertising = bp->link_info.advertising;
5251 if (autoneg & BNXT_AUTONEG_SPEED) {
5253 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5255 req->enables |= cpu_to_le32(
5256 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5257 req->auto_link_speed_mask = cpu_to_le16(advertising);
5259 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5261 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5263 req->force_link_speed = cpu_to_le16(fw_link_speed);
5264 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5267 /* tell chimp that the setting takes effect immediately */
5268 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5271 int bnxt_hwrm_set_pause(struct bnxt *bp)
5273 struct hwrm_port_phy_cfg_input req = {0};
5276 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5277 bnxt_hwrm_set_pause_common(bp, &req);
5279 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5280 bp->link_info.force_link_chng)
5281 bnxt_hwrm_set_link_common(bp, &req);
5283 mutex_lock(&bp->hwrm_cmd_lock);
5284 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5285 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5286 /* since changing of pause setting doesn't trigger any link
5287 * change event, the driver needs to update the current pause
5288 * result upon successfully return of the phy_cfg command
5290 bp->link_info.pause =
5291 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5292 bp->link_info.auto_pause_setting = 0;
5293 if (!bp->link_info.force_link_chng)
5294 bnxt_report_link(bp);
5296 bp->link_info.force_link_chng = false;
5297 mutex_unlock(&bp->hwrm_cmd_lock);
5301 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5302 struct hwrm_port_phy_cfg_input *req)
5304 struct ethtool_eee *eee = &bp->eee;
5306 if (eee->eee_enabled) {
5308 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5310 if (eee->tx_lpi_enabled)
5311 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5313 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5315 req->flags |= cpu_to_le32(flags);
5316 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5317 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5318 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5320 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5324 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5326 struct hwrm_port_phy_cfg_input req = {0};
5328 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5330 bnxt_hwrm_set_pause_common(bp, &req);
5332 bnxt_hwrm_set_link_common(bp, &req);
5335 bnxt_hwrm_set_eee(bp, &req);
5336 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5339 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5341 struct hwrm_port_phy_cfg_input req = {0};
5343 if (!BNXT_SINGLE_PF(bp))
5346 if (pci_num_vf(bp->pdev))
5349 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5350 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN);
5351 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5354 static bool bnxt_eee_config_ok(struct bnxt *bp)
5356 struct ethtool_eee *eee = &bp->eee;
5357 struct bnxt_link_info *link_info = &bp->link_info;
5359 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5362 if (eee->eee_enabled) {
5364 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5366 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5367 eee->eee_enabled = 0;
5370 if (eee->advertised & ~advertising) {
5371 eee->advertised = advertising & eee->supported;
5378 static int bnxt_update_phy_setting(struct bnxt *bp)
5381 bool update_link = false;
5382 bool update_pause = false;
5383 bool update_eee = false;
5384 struct bnxt_link_info *link_info = &bp->link_info;
5386 rc = bnxt_update_link(bp, true);
5388 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5392 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5393 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5394 link_info->req_flow_ctrl)
5395 update_pause = true;
5396 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5397 link_info->force_pause_setting != link_info->req_flow_ctrl)
5398 update_pause = true;
5399 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5400 if (BNXT_AUTO_MODE(link_info->auto_mode))
5402 if (link_info->req_link_speed != link_info->force_link_speed)
5404 if (link_info->req_duplex != link_info->duplex_setting)
5407 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5409 if (link_info->advertising != link_info->auto_link_speeds)
5413 if (!bnxt_eee_config_ok(bp))
5417 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
5418 else if (update_pause)
5419 rc = bnxt_hwrm_set_pause(bp);
5421 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5429 /* Common routine to pre-map certain register block to different GRC window.
5430 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5431 * in PF and 3 windows in VF that can be customized to map in different
5434 static void bnxt_preset_reg_win(struct bnxt *bp)
5437 /* CAG registers map to GRC window #4 */
5438 writel(BNXT_CAG_REG_BASE,
5439 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5443 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5447 bnxt_preset_reg_win(bp);
5448 netif_carrier_off(bp->dev);
5450 rc = bnxt_setup_int_mode(bp);
5452 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5457 if ((bp->flags & BNXT_FLAG_RFS) &&
5458 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5459 /* disable RFS if falling back to INTA */
5460 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5461 bp->flags &= ~BNXT_FLAG_RFS;
5464 rc = bnxt_alloc_mem(bp, irq_re_init);
5466 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5467 goto open_err_free_mem;
5472 rc = bnxt_request_irq(bp);
5474 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5479 bnxt_enable_napi(bp);
5481 rc = bnxt_init_nic(bp, irq_re_init);
5483 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5488 rc = bnxt_update_phy_setting(bp);
5490 netdev_warn(bp->dev, "failed to update phy settings\n");
5494 udp_tunnel_get_rx_info(bp->dev);
5496 set_bit(BNXT_STATE_OPEN, &bp->state);
5497 bnxt_enable_int(bp);
5498 /* Enable TX queues */
5500 mod_timer(&bp->timer, jiffies + bp->current_interval);
5501 /* Poll link status and check for SFP+ module status */
5502 bnxt_get_port_module_status(bp);
5507 bnxt_disable_napi(bp);
5513 bnxt_free_mem(bp, true);
5517 /* rtnl_lock held */
5518 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5522 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5524 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5530 static int bnxt_open(struct net_device *dev)
5532 struct bnxt *bp = netdev_priv(dev);
5535 if (!test_bit(BNXT_STATE_FN_RST_DONE, &bp->state)) {
5536 rc = bnxt_hwrm_func_reset(bp);
5538 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
5543 /* Do func_reset during the 1st PF open only to prevent killing
5544 * the VFs when the PF is brought down and up.
5547 set_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
5549 return __bnxt_open_nic(bp, true, true);
5552 static void bnxt_disable_int_sync(struct bnxt *bp)
5556 atomic_inc(&bp->intr_sem);
5557 if (!netif_running(bp->dev))
5560 bnxt_disable_int(bp);
5561 for (i = 0; i < bp->cp_nr_rings; i++)
5562 synchronize_irq(bp->irq_tbl[i].vector);
5565 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5569 #ifdef CONFIG_BNXT_SRIOV
5570 if (bp->sriov_cfg) {
5571 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5573 BNXT_SRIOV_CFG_WAIT_TMO);
5575 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5578 /* Change device state to avoid TX queue wake up's */
5579 bnxt_tx_disable(bp);
5581 clear_bit(BNXT_STATE_OPEN, &bp->state);
5582 smp_mb__after_atomic();
5583 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5586 /* Flush rings before disabling interrupts */
5587 bnxt_shutdown_nic(bp, irq_re_init);
5589 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5591 bnxt_disable_napi(bp);
5592 bnxt_disable_int_sync(bp);
5593 del_timer_sync(&bp->timer);
5600 bnxt_free_mem(bp, irq_re_init);
5604 static int bnxt_close(struct net_device *dev)
5606 struct bnxt *bp = netdev_priv(dev);
5608 bnxt_close_nic(bp, true, true);
5609 bnxt_hwrm_shutdown_link(bp);
5613 /* rtnl_lock held */
5614 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5620 if (!netif_running(dev))
5627 if (!netif_running(dev))
5639 static struct rtnl_link_stats64 *
5640 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5643 struct bnxt *bp = netdev_priv(dev);
5645 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5650 /* TODO check if we need to synchronize with bnxt_close path */
5651 for (i = 0; i < bp->cp_nr_rings; i++) {
5652 struct bnxt_napi *bnapi = bp->bnapi[i];
5653 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5654 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5656 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5657 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5658 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5660 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5661 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5662 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5664 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5665 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5666 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5668 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5669 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5670 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5672 stats->rx_missed_errors +=
5673 le64_to_cpu(hw_stats->rx_discard_pkts);
5675 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5677 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5680 if (bp->flags & BNXT_FLAG_PORT_STATS) {
5681 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5682 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5684 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5685 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5686 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5687 le64_to_cpu(rx->rx_ovrsz_frames) +
5688 le64_to_cpu(rx->rx_runt_frames);
5689 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5690 le64_to_cpu(rx->rx_jbr_frames);
5691 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5692 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5693 stats->tx_errors = le64_to_cpu(tx->tx_err);
5699 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5701 struct net_device *dev = bp->dev;
5702 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5703 struct netdev_hw_addr *ha;
5706 bool update = false;
5709 netdev_for_each_mc_addr(ha, dev) {
5710 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5711 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5712 vnic->mc_list_count = 0;
5716 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5717 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5724 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5726 if (mc_count != vnic->mc_list_count) {
5727 vnic->mc_list_count = mc_count;
5733 static bool bnxt_uc_list_updated(struct bnxt *bp)
5735 struct net_device *dev = bp->dev;
5736 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5737 struct netdev_hw_addr *ha;
5740 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5743 netdev_for_each_uc_addr(ha, dev) {
5744 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5752 static void bnxt_set_rx_mode(struct net_device *dev)
5754 struct bnxt *bp = netdev_priv(dev);
5755 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5756 u32 mask = vnic->rx_mask;
5757 bool mc_update = false;
5760 if (!netif_running(dev))
5763 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5764 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5765 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5767 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5768 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5770 uc_update = bnxt_uc_list_updated(bp);
5772 if (dev->flags & IFF_ALLMULTI) {
5773 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5774 vnic->mc_list_count = 0;
5776 mc_update = bnxt_mc_list_updated(bp, &mask);
5779 if (mask != vnic->rx_mask || uc_update || mc_update) {
5780 vnic->rx_mask = mask;
5782 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5783 schedule_work(&bp->sp_task);
5787 static int bnxt_cfg_rx_mode(struct bnxt *bp)
5789 struct net_device *dev = bp->dev;
5790 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5791 struct netdev_hw_addr *ha;
5795 netif_addr_lock_bh(dev);
5796 uc_update = bnxt_uc_list_updated(bp);
5797 netif_addr_unlock_bh(dev);
5802 mutex_lock(&bp->hwrm_cmd_lock);
5803 for (i = 1; i < vnic->uc_filter_count; i++) {
5804 struct hwrm_cfa_l2_filter_free_input req = {0};
5806 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5809 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5811 rc = _hwrm_send_message(bp, &req, sizeof(req),
5814 mutex_unlock(&bp->hwrm_cmd_lock);
5816 vnic->uc_filter_count = 1;
5818 netif_addr_lock_bh(dev);
5819 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5820 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5822 netdev_for_each_uc_addr(ha, dev) {
5823 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5825 vnic->uc_filter_count++;
5828 netif_addr_unlock_bh(dev);
5830 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5831 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5833 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5835 vnic->uc_filter_count = i;
5841 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5843 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5849 static bool bnxt_rfs_capable(struct bnxt *bp)
5851 #ifdef CONFIG_RFS_ACCEL
5852 struct bnxt_pf_info *pf = &bp->pf;
5855 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5858 vnics = 1 + bp->rx_nr_rings;
5859 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics) {
5860 netdev_warn(bp->dev,
5861 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
5862 min(pf->max_rsscos_ctxs - 1, pf->max_vnics - 1));
5872 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5873 netdev_features_t features)
5875 struct bnxt *bp = netdev_priv(dev);
5877 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
5878 features &= ~NETIF_F_NTUPLE;
5880 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5881 * turned on or off together.
5883 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
5884 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
5885 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
5886 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5887 NETIF_F_HW_VLAN_STAG_RX);
5889 features |= NETIF_F_HW_VLAN_CTAG_RX |
5890 NETIF_F_HW_VLAN_STAG_RX;
5892 #ifdef CONFIG_BNXT_SRIOV
5895 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5896 NETIF_F_HW_VLAN_STAG_RX);
5903 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5905 struct bnxt *bp = netdev_priv(dev);
5906 u32 flags = bp->flags;
5909 bool re_init = false;
5910 bool update_tpa = false;
5912 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5913 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
5914 flags |= BNXT_FLAG_GRO;
5915 if (features & NETIF_F_LRO)
5916 flags |= BNXT_FLAG_LRO;
5918 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5919 flags |= BNXT_FLAG_STRIP_VLAN;
5921 if (features & NETIF_F_NTUPLE)
5922 flags |= BNXT_FLAG_RFS;
5924 changes = flags ^ bp->flags;
5925 if (changes & BNXT_FLAG_TPA) {
5927 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5928 (flags & BNXT_FLAG_TPA) == 0)
5932 if (changes & ~BNXT_FLAG_TPA)
5935 if (flags != bp->flags) {
5936 u32 old_flags = bp->flags;
5940 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5942 bnxt_set_ring_params(bp);
5947 bnxt_close_nic(bp, false, false);
5949 bnxt_set_ring_params(bp);
5951 return bnxt_open_nic(bp, false, false);
5954 rc = bnxt_set_tpa(bp,
5955 (flags & BNXT_FLAG_TPA) ?
5958 bp->flags = old_flags;
5964 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5966 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5967 int i = bnapi->index;
5972 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5973 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5977 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5979 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5980 int i = bnapi->index;
5985 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5986 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5987 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5988 rxr->rx_sw_agg_prod);
5991 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5993 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5994 int i = bnapi->index;
5996 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5997 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6000 static void bnxt_dbg_dump_states(struct bnxt *bp)
6003 struct bnxt_napi *bnapi;
6005 for (i = 0; i < bp->cp_nr_rings; i++) {
6006 bnapi = bp->bnapi[i];
6007 if (netif_msg_drv(bp)) {
6008 bnxt_dump_tx_sw_state(bnapi);
6009 bnxt_dump_rx_sw_state(bnapi);
6010 bnxt_dump_cp_sw_state(bnapi);
6015 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6018 bnxt_dbg_dump_states(bp);
6019 if (netif_running(bp->dev)) {
6020 bnxt_close_nic(bp, false, false);
6021 bnxt_open_nic(bp, false, false);
6025 static void bnxt_tx_timeout(struct net_device *dev)
6027 struct bnxt *bp = netdev_priv(dev);
6029 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
6030 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6031 schedule_work(&bp->sp_task);
6034 #ifdef CONFIG_NET_POLL_CONTROLLER
6035 static void bnxt_poll_controller(struct net_device *dev)
6037 struct bnxt *bp = netdev_priv(dev);
6040 for (i = 0; i < bp->cp_nr_rings; i++) {
6041 struct bnxt_irq *irq = &bp->irq_tbl[i];
6043 disable_irq(irq->vector);
6044 irq->handler(irq->vector, bp->bnapi[i]);
6045 enable_irq(irq->vector);
6050 static void bnxt_timer(unsigned long data)
6052 struct bnxt *bp = (struct bnxt *)data;
6053 struct net_device *dev = bp->dev;
6055 if (!netif_running(dev))
6058 if (atomic_read(&bp->intr_sem) != 0)
6059 goto bnxt_restart_timer;
6061 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6062 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6063 schedule_work(&bp->sp_task);
6066 mod_timer(&bp->timer, jiffies + bp->current_interval);
6069 /* Only called from bnxt_sp_task() */
6070 static void bnxt_reset(struct bnxt *bp, bool silent)
6072 /* bnxt_reset_task() calls bnxt_close_nic() which waits
6073 * for BNXT_STATE_IN_SP_TASK to clear.
6074 * If there is a parallel dev_close(), bnxt_close() may be holding
6075 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6076 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6078 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6080 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6081 bnxt_reset_task(bp, silent);
6082 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6086 static void bnxt_cfg_ntp_filters(struct bnxt *);
6088 static void bnxt_sp_task(struct work_struct *work)
6090 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
6093 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6094 smp_mb__after_atomic();
6095 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6096 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6100 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6101 bnxt_cfg_rx_mode(bp);
6103 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6104 bnxt_cfg_ntp_filters(bp);
6105 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6106 rc = bnxt_update_link(bp, true);
6108 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6111 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6112 bnxt_hwrm_exec_fwd_req(bp);
6113 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6114 bnxt_hwrm_tunnel_dst_port_alloc(
6116 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6118 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6119 bnxt_hwrm_tunnel_dst_port_free(
6120 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6122 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6123 bnxt_hwrm_tunnel_dst_port_alloc(
6125 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6127 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6128 bnxt_hwrm_tunnel_dst_port_free(
6129 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6131 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6132 bnxt_reset(bp, false);
6134 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6135 bnxt_reset(bp, true);
6137 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event))
6138 bnxt_get_port_module_status(bp);
6140 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6141 bnxt_hwrm_port_qstats(bp);
6143 smp_mb__before_atomic();
6144 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6147 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6150 struct bnxt *bp = netdev_priv(dev);
6152 SET_NETDEV_DEV(dev, &pdev->dev);
6154 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6155 rc = pci_enable_device(pdev);
6157 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6161 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6163 "Cannot find PCI device base address, aborting\n");
6165 goto init_err_disable;
6168 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6170 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6171 goto init_err_disable;
6174 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6175 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6176 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6177 goto init_err_disable;
6180 pci_set_master(pdev);
6185 bp->bar0 = pci_ioremap_bar(pdev, 0);
6187 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6189 goto init_err_release;
6192 bp->bar1 = pci_ioremap_bar(pdev, 2);
6194 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6196 goto init_err_release;
6199 bp->bar2 = pci_ioremap_bar(pdev, 4);
6201 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6203 goto init_err_release;
6206 pci_enable_pcie_error_reporting(pdev);
6208 INIT_WORK(&bp->sp_task, bnxt_sp_task);
6210 spin_lock_init(&bp->ntp_fltr_lock);
6212 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6213 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6215 /* tick values in micro seconds */
6216 bp->rx_coal_ticks = 12;
6217 bp->rx_coal_bufs = 30;
6218 bp->rx_coal_ticks_irq = 1;
6219 bp->rx_coal_bufs_irq = 2;
6221 bp->tx_coal_ticks = 25;
6222 bp->tx_coal_bufs = 30;
6223 bp->tx_coal_ticks_irq = 2;
6224 bp->tx_coal_bufs_irq = 2;
6226 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6228 init_timer(&bp->timer);
6229 bp->timer.data = (unsigned long)bp;
6230 bp->timer.function = bnxt_timer;
6231 bp->current_interval = BNXT_TIMER_INTERVAL;
6233 clear_bit(BNXT_STATE_OPEN, &bp->state);
6239 pci_iounmap(pdev, bp->bar2);
6244 pci_iounmap(pdev, bp->bar1);
6249 pci_iounmap(pdev, bp->bar0);
6253 pci_release_regions(pdev);
6256 pci_disable_device(pdev);
6262 /* rtnl_lock held */
6263 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6265 struct sockaddr *addr = p;
6266 struct bnxt *bp = netdev_priv(dev);
6269 if (!is_valid_ether_addr(addr->sa_data))
6270 return -EADDRNOTAVAIL;
6272 rc = bnxt_approve_mac(bp, addr->sa_data);
6276 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6279 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6280 if (netif_running(dev)) {
6281 bnxt_close_nic(bp, false, false);
6282 rc = bnxt_open_nic(bp, false, false);
6288 /* rtnl_lock held */
6289 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6291 struct bnxt *bp = netdev_priv(dev);
6293 if (new_mtu < 60 || new_mtu > 9500)
6296 if (netif_running(dev))
6297 bnxt_close_nic(bp, false, false);
6300 bnxt_set_ring_params(bp);
6302 if (netif_running(dev))
6303 return bnxt_open_nic(bp, false, false);
6308 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6309 struct tc_to_netdev *ntc)
6311 struct bnxt *bp = netdev_priv(dev);
6314 if (ntc->type != TC_SETUP_MQPRIO)
6319 if (tc > bp->max_tc) {
6320 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6325 if (netdev_get_num_tc(dev) == tc)
6329 int max_rx_rings, max_tx_rings, rc;
6332 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6335 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6336 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
6340 /* Needs to close the device and do hw resource re-allocations */
6341 if (netif_running(bp->dev))
6342 bnxt_close_nic(bp, true, false);
6345 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6346 netdev_set_num_tc(dev, tc);
6348 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6349 netdev_reset_tc(dev);
6351 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
6352 bp->num_stat_ctxs = bp->cp_nr_rings;
6354 if (netif_running(bp->dev))
6355 return bnxt_open_nic(bp, true, false);
6360 #ifdef CONFIG_RFS_ACCEL
6361 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6362 struct bnxt_ntuple_filter *f2)
6364 struct flow_keys *keys1 = &f1->fkeys;
6365 struct flow_keys *keys2 = &f2->fkeys;
6367 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6368 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6369 keys1->ports.ports == keys2->ports.ports &&
6370 keys1->basic.ip_proto == keys2->basic.ip_proto &&
6371 keys1->basic.n_proto == keys2->basic.n_proto &&
6372 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
6373 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
6379 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6380 u16 rxq_index, u32 flow_id)
6382 struct bnxt *bp = netdev_priv(dev);
6383 struct bnxt_ntuple_filter *fltr, *new_fltr;
6384 struct flow_keys *fkeys;
6385 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
6386 int rc = 0, idx, bit_id, l2_idx = 0;
6387 struct hlist_head *head;
6389 if (skb->encapsulation)
6390 return -EPROTONOSUPPORT;
6392 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
6393 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6396 netif_addr_lock_bh(dev);
6397 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
6398 if (ether_addr_equal(eth->h_dest,
6399 vnic->uc_list + off)) {
6404 netif_addr_unlock_bh(dev);
6408 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6412 fkeys = &new_fltr->fkeys;
6413 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6414 rc = -EPROTONOSUPPORT;
6418 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
6419 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6420 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6421 rc = -EPROTONOSUPPORT;
6425 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
6426 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6428 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6429 head = &bp->ntp_fltr_hash_tbl[idx];
6431 hlist_for_each_entry_rcu(fltr, head, hash) {
6432 if (bnxt_fltr_match(fltr, new_fltr)) {
6440 spin_lock_bh(&bp->ntp_fltr_lock);
6441 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6442 BNXT_NTP_FLTR_MAX_FLTR, 0);
6444 spin_unlock_bh(&bp->ntp_fltr_lock);
6449 new_fltr->sw_id = (u16)bit_id;
6450 new_fltr->flow_id = flow_id;
6451 new_fltr->l2_fltr_idx = l2_idx;
6452 new_fltr->rxq = rxq_index;
6453 hlist_add_head_rcu(&new_fltr->hash, head);
6454 bp->ntp_fltr_count++;
6455 spin_unlock_bh(&bp->ntp_fltr_lock);
6457 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6458 schedule_work(&bp->sp_task);
6460 return new_fltr->sw_id;
6467 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6471 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6472 struct hlist_head *head;
6473 struct hlist_node *tmp;
6474 struct bnxt_ntuple_filter *fltr;
6477 head = &bp->ntp_fltr_hash_tbl[i];
6478 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6481 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6482 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6485 bnxt_hwrm_cfa_ntuple_filter_free(bp,
6490 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6495 set_bit(BNXT_FLTR_VALID, &fltr->state);
6499 spin_lock_bh(&bp->ntp_fltr_lock);
6500 hlist_del_rcu(&fltr->hash);
6501 bp->ntp_fltr_count--;
6502 spin_unlock_bh(&bp->ntp_fltr_lock);
6504 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6509 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6510 netdev_info(bp->dev, "Receive PF driver unload event!");
6515 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6519 #endif /* CONFIG_RFS_ACCEL */
6521 static void bnxt_udp_tunnel_add(struct net_device *dev,
6522 struct udp_tunnel_info *ti)
6524 struct bnxt *bp = netdev_priv(dev);
6526 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
6529 if (!netif_running(dev))
6533 case UDP_TUNNEL_TYPE_VXLAN:
6534 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
6537 bp->vxlan_port_cnt++;
6538 if (bp->vxlan_port_cnt == 1) {
6539 bp->vxlan_port = ti->port;
6540 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
6541 schedule_work(&bp->sp_task);
6544 case UDP_TUNNEL_TYPE_GENEVE:
6545 if (bp->nge_port_cnt && bp->nge_port != ti->port)
6549 if (bp->nge_port_cnt == 1) {
6550 bp->nge_port = ti->port;
6551 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
6558 schedule_work(&bp->sp_task);
6561 static void bnxt_udp_tunnel_del(struct net_device *dev,
6562 struct udp_tunnel_info *ti)
6564 struct bnxt *bp = netdev_priv(dev);
6566 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
6569 if (!netif_running(dev))
6573 case UDP_TUNNEL_TYPE_VXLAN:
6574 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
6576 bp->vxlan_port_cnt--;
6578 if (bp->vxlan_port_cnt != 0)
6581 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
6583 case UDP_TUNNEL_TYPE_GENEVE:
6584 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
6588 if (bp->nge_port_cnt != 0)
6591 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
6597 schedule_work(&bp->sp_task);
6600 static const struct net_device_ops bnxt_netdev_ops = {
6601 .ndo_open = bnxt_open,
6602 .ndo_start_xmit = bnxt_start_xmit,
6603 .ndo_stop = bnxt_close,
6604 .ndo_get_stats64 = bnxt_get_stats64,
6605 .ndo_set_rx_mode = bnxt_set_rx_mode,
6606 .ndo_do_ioctl = bnxt_ioctl,
6607 .ndo_validate_addr = eth_validate_addr,
6608 .ndo_set_mac_address = bnxt_change_mac_addr,
6609 .ndo_change_mtu = bnxt_change_mtu,
6610 .ndo_fix_features = bnxt_fix_features,
6611 .ndo_set_features = bnxt_set_features,
6612 .ndo_tx_timeout = bnxt_tx_timeout,
6613 #ifdef CONFIG_BNXT_SRIOV
6614 .ndo_get_vf_config = bnxt_get_vf_config,
6615 .ndo_set_vf_mac = bnxt_set_vf_mac,
6616 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
6617 .ndo_set_vf_rate = bnxt_set_vf_bw,
6618 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
6619 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
6621 #ifdef CONFIG_NET_POLL_CONTROLLER
6622 .ndo_poll_controller = bnxt_poll_controller,
6624 .ndo_setup_tc = bnxt_setup_tc,
6625 #ifdef CONFIG_RFS_ACCEL
6626 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
6628 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
6629 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
6630 #ifdef CONFIG_NET_RX_BUSY_POLL
6631 .ndo_busy_poll = bnxt_busy_poll,
6635 static void bnxt_remove_one(struct pci_dev *pdev)
6637 struct net_device *dev = pci_get_drvdata(pdev);
6638 struct bnxt *bp = netdev_priv(dev);
6641 bnxt_sriov_disable(bp);
6643 pci_disable_pcie_error_reporting(pdev);
6644 unregister_netdev(dev);
6645 cancel_work_sync(&bp->sp_task);
6648 bnxt_hwrm_func_drv_unrgtr(bp);
6649 bnxt_free_hwrm_resources(bp);
6650 pci_iounmap(pdev, bp->bar2);
6651 pci_iounmap(pdev, bp->bar1);
6652 pci_iounmap(pdev, bp->bar0);
6655 pci_release_regions(pdev);
6656 pci_disable_device(pdev);
6659 static int bnxt_probe_phy(struct bnxt *bp)
6662 struct bnxt_link_info *link_info = &bp->link_info;
6664 rc = bnxt_hwrm_phy_qcaps(bp);
6666 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6671 rc = bnxt_update_link(bp, false);
6673 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
6678 /* Older firmware does not have supported_auto_speeds, so assume
6679 * that all supported speeds can be autonegotiated.
6681 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
6682 link_info->support_auto_speeds = link_info->support_speeds;
6684 /*initialize the ethool setting copy with NVM settings */
6685 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
6686 link_info->autoneg = BNXT_AUTONEG_SPEED;
6687 if (bp->hwrm_spec_code >= 0x10201) {
6688 if (link_info->auto_pause_setting &
6689 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
6690 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6692 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6694 link_info->advertising = link_info->auto_link_speeds;
6696 link_info->req_link_speed = link_info->force_link_speed;
6697 link_info->req_duplex = link_info->duplex_setting;
6699 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
6700 link_info->req_flow_ctrl =
6701 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
6703 link_info->req_flow_ctrl = link_info->force_pause_setting;
6707 static int bnxt_get_max_irq(struct pci_dev *pdev)
6711 if (!pdev->msix_cap)
6714 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
6715 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
6718 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6721 int max_ring_grps = 0;
6723 #ifdef CONFIG_BNXT_SRIOV
6725 *max_tx = bp->vf.max_tx_rings;
6726 *max_rx = bp->vf.max_rx_rings;
6727 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
6728 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
6729 max_ring_grps = bp->vf.max_hw_ring_grps;
6733 *max_tx = bp->pf.max_tx_rings;
6734 *max_rx = bp->pf.max_rx_rings;
6735 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
6736 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
6737 max_ring_grps = bp->pf.max_hw_ring_grps;
6739 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
6743 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6745 *max_rx = min_t(int, *max_rx, max_ring_grps);
6748 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
6752 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
6753 if (!rx || !tx || !cp)
6758 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
6761 static int bnxt_set_dflt_rings(struct bnxt *bp)
6763 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6767 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6768 dflt_rings = netif_get_num_default_rss_queues();
6769 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6772 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
6773 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
6774 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6775 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6776 bp->tx_nr_rings + bp->rx_nr_rings;
6777 bp->num_stat_ctxs = bp->cp_nr_rings;
6778 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6785 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
6787 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
6788 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
6790 if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
6791 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
6792 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
6794 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
6795 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
6796 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
6797 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
6801 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6803 static int version_printed;
6804 struct net_device *dev;
6808 if (pdev->device == 0x16cd && pci_is_bridge(pdev))
6811 if (version_printed++ == 0)
6812 pr_info("%s", version);
6814 max_irqs = bnxt_get_max_irq(pdev);
6815 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
6819 bp = netdev_priv(dev);
6821 if (bnxt_vf_pciid(ent->driver_data))
6822 bp->flags |= BNXT_FLAG_VF;
6825 bp->flags |= BNXT_FLAG_MSIX_CAP;
6827 rc = bnxt_init_board(pdev, dev);
6831 dev->netdev_ops = &bnxt_netdev_ops;
6832 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
6833 dev->ethtool_ops = &bnxt_ethtool_ops;
6835 pci_set_drvdata(pdev, dev);
6837 rc = bnxt_alloc_hwrm_resources(bp);
6841 mutex_init(&bp->hwrm_cmd_lock);
6842 rc = bnxt_hwrm_ver_get(bp);
6846 bnxt_hwrm_fw_set_time(bp);
6848 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6849 NETIF_F_TSO | NETIF_F_TSO6 |
6850 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6851 NETIF_F_GSO_IPXIP4 |
6852 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6853 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
6854 NETIF_F_RXCSUM | NETIF_F_GRO;
6856 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
6857 dev->hw_features |= NETIF_F_LRO;
6859 dev->hw_enc_features =
6860 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6861 NETIF_F_TSO | NETIF_F_TSO6 |
6862 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6863 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6864 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
6865 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
6866 NETIF_F_GSO_GRE_CSUM;
6867 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
6868 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6869 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
6870 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
6871 dev->priv_flags |= IFF_UNICAST_FLT;
6873 #ifdef CONFIG_BNXT_SRIOV
6874 init_waitqueue_head(&bp->sriov_cfg_wait);
6876 bp->gro_func = bnxt_gro_func_5730x;
6877 if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
6878 bp->gro_func = bnxt_gro_func_5731x;
6880 rc = bnxt_hwrm_func_drv_rgtr(bp);
6884 /* Get the MAX capabilities for this function */
6885 rc = bnxt_hwrm_func_qcaps(bp);
6887 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6893 rc = bnxt_hwrm_queue_qportcfg(bp);
6895 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6901 bnxt_hwrm_func_qcfg(bp);
6903 bnxt_set_tpa_flags(bp);
6904 bnxt_set_ring_params(bp);
6906 bp->pf.max_irqs = max_irqs;
6907 #if defined(CONFIG_BNXT_SRIOV)
6909 bp->vf.max_irqs = max_irqs;
6911 bnxt_set_dflt_rings(bp);
6913 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6914 dev->hw_features |= NETIF_F_NTUPLE;
6915 if (bnxt_rfs_capable(bp)) {
6916 bp->flags |= BNXT_FLAG_RFS;
6917 dev->features |= NETIF_F_NTUPLE;
6921 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6922 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6924 rc = bnxt_probe_phy(bp);
6928 rc = register_netdev(dev);
6932 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6933 board_info[ent->driver_data].name,
6934 (long)pci_resource_start(pdev, 0), dev->dev_addr);
6936 bnxt_parse_log_pcie_link(bp);
6941 pci_iounmap(pdev, bp->bar0);
6942 pci_release_regions(pdev);
6943 pci_disable_device(pdev);
6951 * bnxt_io_error_detected - called when PCI error is detected
6952 * @pdev: Pointer to PCI device
6953 * @state: The current pci connection state
6955 * This function is called after a PCI bus error affecting
6956 * this device has been detected.
6958 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6959 pci_channel_state_t state)
6961 struct net_device *netdev = pci_get_drvdata(pdev);
6962 struct bnxt *bp = netdev_priv(netdev);
6964 netdev_info(netdev, "PCI I/O error detected\n");
6967 netif_device_detach(netdev);
6969 if (state == pci_channel_io_perm_failure) {
6971 return PCI_ERS_RESULT_DISCONNECT;
6974 if (netif_running(netdev))
6977 /* So that func_reset will be done during slot_reset */
6978 clear_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
6979 pci_disable_device(pdev);
6982 /* Request a slot slot reset. */
6983 return PCI_ERS_RESULT_NEED_RESET;
6987 * bnxt_io_slot_reset - called after the pci bus has been reset.
6988 * @pdev: Pointer to PCI device
6990 * Restart the card from scratch, as if from a cold-boot.
6991 * At this point, the card has exprienced a hard reset,
6992 * followed by fixups by BIOS, and has its config space
6993 * set up identically to what it was at cold boot.
6995 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
6997 struct net_device *netdev = pci_get_drvdata(pdev);
6998 struct bnxt *bp = netdev_priv(netdev);
7000 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7002 netdev_info(bp->dev, "PCI Slot Reset\n");
7006 if (pci_enable_device(pdev)) {
7008 "Cannot re-enable PCI device after reset.\n");
7010 pci_set_master(pdev);
7012 if (netif_running(netdev))
7013 err = bnxt_open(netdev);
7016 result = PCI_ERS_RESULT_RECOVERED;
7019 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7024 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7027 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7028 err); /* non-fatal, continue */
7031 return PCI_ERS_RESULT_RECOVERED;
7035 * bnxt_io_resume - called when traffic can start flowing again.
7036 * @pdev: Pointer to PCI device
7038 * This callback is called when the error recovery driver tells
7039 * us that its OK to resume normal operation.
7041 static void bnxt_io_resume(struct pci_dev *pdev)
7043 struct net_device *netdev = pci_get_drvdata(pdev);
7047 netif_device_attach(netdev);
7052 static const struct pci_error_handlers bnxt_err_handler = {
7053 .error_detected = bnxt_io_error_detected,
7054 .slot_reset = bnxt_io_slot_reset,
7055 .resume = bnxt_io_resume
7058 static struct pci_driver bnxt_pci_driver = {
7059 .name = DRV_MODULE_NAME,
7060 .id_table = bnxt_pci_tbl,
7061 .probe = bnxt_init_one,
7062 .remove = bnxt_remove_one,
7063 .err_handler = &bnxt_err_handler,
7064 #if defined(CONFIG_BNXT_SRIOV)
7065 .sriov_configure = bnxt_sriov_configure,
7069 module_pci_driver(bnxt_pci_driver);