drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2019 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/mdio.h>
  35 #include <linux/if.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/if_bridge.h>
  38 #include <linux/rtc.h>
  39 #include <linux/bpf.h>
  40 #include <net/ip.h>
  41 #include <net/tcp.h>
  42 #include <net/udp.h>
  43 #include <net/checksum.h>
  44 #include <net/ip6_checksum.h>
  45 #include <net/udp_tunnel.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53 #include <linux/cpumask.h>
  54 #include <net/pkt_cls.h>
  55 #include <linux/hwmon.h>
  56 #include <linux/hwmon-sysfs.h>
  57
  58 #include "bnxt_hsi.h"
  59 #include "bnxt.h"
  60 #include "bnxt_ulp.h"
  61 #include "bnxt_sriov.h"
  62 #include "bnxt_ethtool.h"
  63 #include "bnxt_dcb.h"
  64 #include "bnxt_xdp.h"
  65 #include "bnxt_vfr.h"
  66 #include "bnxt_tc.h"
  67 #include "bnxt_devlink.h"
  68 #include "bnxt_debugfs.h"
  69
  70 #define BNXT_TX_TIMEOUT         (5 * HZ)
  71
  72 static const char version[] =
  73         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  74
  75 MODULE_LICENSE("GPL");
  76 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  77 MODULE_VERSION(DRV_MODULE_VERSION);
  78
  79 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  80 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  81 #define BNXT_RX_COPY_THRESH 256
  82
  83 #define BNXT_TX_PUSH_THRESH 164
  84
  85 enum board_idx {
  86         BCM57301,
  87         BCM57302,
  88         BCM57304,
  89         BCM57417_NPAR,
  90         BCM58700,
  91         BCM57311,
  92         BCM57312,
  93         BCM57402,
  94         BCM57404,
  95         BCM57406,
  96         BCM57402_NPAR,
  97         BCM57407,
  98         BCM57412,
  99         BCM57414,
 100         BCM57416,
 101         BCM57417,
 102         BCM57412_NPAR,
 103         BCM57314,
 104         BCM57417_SFP,
 105         BCM57416_SFP,
 106         BCM57404_NPAR,
 107         BCM57406_NPAR,
 108         BCM57407_SFP,
 109         BCM57407_NPAR,
 110         BCM57414_NPAR,
 111         BCM57416_NPAR,
 112         BCM57452,
 113         BCM57454,
 114         BCM5745x_NPAR,
 115         BCM57508,
 116         BCM57504,
 117         BCM58802,
 118         BCM58804,
 119         BCM58808,
 120         NETXTREME_E_VF,
 121         NETXTREME_C_VF,
 122         NETXTREME_S_VF,
 123         NETXTREME_E_P5_VF,
 124 };
 125
 126 /* indexed by enum above */
 127 static const struct {
 128         char *name;
 129 } board_info[] = {
 130         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 131         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 132         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 133         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 134         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 135         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 136         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 137         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 138         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 139         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 140         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 141         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 142         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 143         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 144         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 145         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 146         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 147         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 148         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 149         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 150         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 151         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 152         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 153         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 154         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 155         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 156         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 157         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 158         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 159         [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 160         [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 161         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 162         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 163         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 164         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 165         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 166         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 167         [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
 168 };
 169
 170 static const struct pci_device_id bnxt_pci_tbl[] = {
 171         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 173         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 174         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 175         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 176         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 177         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 178         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 179         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 180         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 181         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 182         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 183         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 184         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 185         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 186         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 187         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 188         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 189         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 190         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 191         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 192         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 193         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 194         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 195         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 196         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 197         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 198         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 199         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 200         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 201         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 202         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 203         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 204         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 205         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 206         { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
 207         { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
 208         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 209         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 210 #ifdef CONFIG_BNXT_SRIOV
 211         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 212         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 213         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 214         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 215         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 216         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 217         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 218         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 219         { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
 220         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 221 #endif
 222         { 0 }
 223 };
 224
 225 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 226
 227 static const u16 bnxt_vf_req_snif[] = {
 228         HWRM_FUNC_CFG,
 229         HWRM_FUNC_VF_CFG,
 230         HWRM_PORT_PHY_QCFG,
 231         HWRM_CFA_L2_FILTER_ALLOC,
 232 };
 233
 234 static const u16 bnxt_async_events_arr[] = {
 235         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 236         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 237         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 238         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 239         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 240 };
 241
 242 static struct workqueue_struct *bnxt_pf_wq;
 243
 244 static bool bnxt_vf_pciid(enum board_idx idx)
 245 {
 246         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 247                 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
 248 }
 249
 250 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 251 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 252 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 253
 254 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 255                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 256
 257 #define BNXT_DB_CQ(db, idx)                                             \
 258         writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
 259
 260 #define BNXT_DB_NQ_P5(db, idx)                                          \
 261         writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
 262
 263 #define BNXT_DB_CQ_ARM(db, idx)                                         \
 264         writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
 265
 266 #define BNXT_DB_NQ_ARM_P5(db, idx)                                      \
 267         writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
 268
 269 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 270 {
 271         if (bp->flags & BNXT_FLAG_CHIP_P5)
 272                 BNXT_DB_NQ_P5(db, idx);
 273         else
 274                 BNXT_DB_CQ(db, idx);
 275 }
 276
 277 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 278 {
 279         if (bp->flags & BNXT_FLAG_CHIP_P5)
 280                 BNXT_DB_NQ_ARM_P5(db, idx);
 281         else
 282                 BNXT_DB_CQ_ARM(db, idx);
 283 }
 284
 285 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 286 {
 287         if (bp->flags & BNXT_FLAG_CHIP_P5)
 288                 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
 289                        db->doorbell);
 290         else
 291                 BNXT_DB_CQ(db, idx);
 292 }
 293
 294 const u16 bnxt_lhint_arr[] = {
 295         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 296         TX_BD_FLAGS_LHINT_512_TO_1023,
 297         TX_BD_FLAGS_LHINT_1024_TO_2047,
 298         TX_BD_FLAGS_LHINT_1024_TO_2047,
 299         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 300         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 301         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 302         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 303         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 304         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 305         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 306         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 307         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 308         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 309         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 310         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 311         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 312         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 313         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 314 };
 315
 316 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 317 {
 318         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 319
 320         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 321                 return 0;
 322
 323         return md_dst->u.port_info.port_id;
 324 }
 325
 326 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 327 {
 328         struct bnxt *bp = netdev_priv(dev);
 329         struct tx_bd *txbd;
 330         struct tx_bd_ext *txbd1;
 331         struct netdev_queue *txq;
 332         int i;
 333         dma_addr_t mapping;
 334         unsigned int length, pad = 0;
 335         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 336         u16 prod, last_frag;
 337         struct pci_dev *pdev = bp->pdev;
 338         struct bnxt_tx_ring_info *txr;
 339         struct bnxt_sw_tx_bd *tx_buf;
 340
 341         i = skb_get_queue_mapping(skb);
 342         if (unlikely(i >= bp->tx_nr_rings)) {
 343                 dev_kfree_skb_any(skb);
 344                 return NETDEV_TX_OK;
 345         }
 346
 347         txq = netdev_get_tx_queue(dev, i);
 348         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 349         prod = txr->tx_prod;
 350
 351         free_size = bnxt_tx_avail(bp, txr);
 352         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 353                 netif_tx_stop_queue(txq);
 354                 return NETDEV_TX_BUSY;
 355         }
 356
 357         length = skb->len;
 358         len = skb_headlen(skb);
 359         last_frag = skb_shinfo(skb)->nr_frags;
 360
 361         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 362
 363         txbd->tx_bd_opaque = prod;
 364
 365         tx_buf = &txr->tx_buf_ring[prod];
 366         tx_buf->skb = skb;
 367         tx_buf->nr_frags = last_frag;
 368
 369         vlan_tag_flags = 0;
 370         cfa_action = bnxt_xmit_get_cfa_action(skb);
 371         if (skb_vlan_tag_present(skb)) {
 372                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 373                                  skb_vlan_tag_get(skb);
 374                 /* Currently supports 8021Q, 8021AD vlan offloads
 375                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 376                  */
 377                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 378                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 379         }
 380
 381         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 382                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 383                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 384                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 385                 void __iomem *db = txr->tx_db.doorbell;
 386                 void *pdata = tx_push_buf->data;
 387                 u64 *end;
 388                 int j, push_len;
 389
 390                 /* Set COAL_NOW to be ready quickly for the next push */
 391                 tx_push->tx_bd_len_flags_type =
 392                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 393                                         TX_BD_TYPE_LONG_TX_BD |
 394                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 395                                         TX_BD_FLAGS_COAL_NOW |
 396                                         TX_BD_FLAGS_PACKET_END |
 397                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 398
 399                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 400                         tx_push1->tx_bd_hsize_lflags =
 401                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 402                 else
 403                         tx_push1->tx_bd_hsize_lflags = 0;
 404
 405                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 406                 tx_push1->tx_bd_cfa_action =
 407                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 408
 409                 end = pdata + length;
 410                 end = PTR_ALIGN(end, 8) - 1;
 411                 *end = 0;
 412
 413                 skb_copy_from_linear_data(skb, pdata, len);
 414                 pdata += len;
 415                 for (j = 0; j < last_frag; j++) {
 416                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 417                         void *fptr;
 418
 419                         fptr = skb_frag_address_safe(frag);
 420                         if (!fptr)
 421                                 goto normal_tx;
 422
 423                         memcpy(pdata, fptr, skb_frag_size(frag));
 424                         pdata += skb_frag_size(frag);
 425                 }
 426
 427                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 428                 txbd->tx_bd_haddr = txr->data_mapping;
 429                 prod = NEXT_TX(prod);
 430                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 431                 memcpy(txbd, tx_push1, sizeof(*txbd));
 432                 prod = NEXT_TX(prod);
 433                 tx_push->doorbell =
 434                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 435                 txr->tx_prod = prod;
 436
 437                 tx_buf->is_push = 1;
 438                 netdev_tx_sent_queue(txq, skb->len);
 439                 wmb();  /* Sync is_push and byte queue before pushing data */
 440
 441                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 442                 if (push_len > 16) {
 443                         __iowrite64_copy(db, tx_push_buf, 16);
 444                         __iowrite32_copy(db + 4, tx_push_buf + 1,
 445                                          (push_len - 16) << 1);
 446                 } else {
 447                         __iowrite64_copy(db, tx_push_buf, push_len);
 448                 }
 449
 450                 goto tx_done;
 451         }
 452
 453 normal_tx:
 454         if (length < BNXT_MIN_PKT_SIZE) {
 455                 pad = BNXT_MIN_PKT_SIZE - length;
 456                 if (skb_pad(skb, pad)) {
 457                         /* SKB already freed. */
 458                         tx_buf->skb = NULL;
 459                         return NETDEV_TX_OK;
 460                 }
 461                 length = BNXT_MIN_PKT_SIZE;
 462         }
 463
 464         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 465
 466         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 467                 dev_kfree_skb_any(skb);
 468                 tx_buf->skb = NULL;
 469                 return NETDEV_TX_OK;
 470         }
 471
 472         dma_unmap_addr_set(tx_buf, mapping, mapping);
 473         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 474                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 475
 476         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 477
 478         prod = NEXT_TX(prod);
 479         txbd1 = (struct tx_bd_ext *)
 480                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 481
 482         txbd1->tx_bd_hsize_lflags = 0;
 483         if (skb_is_gso(skb)) {
 484                 u32 hdr_len;
 485
 486                 if (skb->encapsulation)
 487                         hdr_len = skb_inner_network_offset(skb) +
 488                                 skb_inner_network_header_len(skb) +
 489                                 inner_tcp_hdrlen(skb);
 490                 else
 491                         hdr_len = skb_transport_offset(skb) +
 492                                 tcp_hdrlen(skb);
 493
 494                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 495                                         TX_BD_FLAGS_T_IPID |
 496                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 497                 length = skb_shinfo(skb)->gso_size;
 498                 txbd1->tx_bd_mss = cpu_to_le32(length);
 499                 length += hdr_len;
 500         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 501                 txbd1->tx_bd_hsize_lflags =
 502                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 503                 txbd1->tx_bd_mss = 0;
 504         }
 505
 506         length >>= 9;
 507         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 508                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 509                                      skb->len);
 510                 i = 0;
 511                 goto tx_dma_error;
 512         }
 513         flags |= bnxt_lhint_arr[length];
 514         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 515
 516         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 517         txbd1->tx_bd_cfa_action =
 518                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 519         for (i = 0; i < last_frag; i++) {
 520                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 521
 522                 prod = NEXT_TX(prod);
 523                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 524
 525                 len = skb_frag_size(frag);
 526                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 527                                            DMA_TO_DEVICE);
 528
 529                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 530                         goto tx_dma_error;
 531
 532                 tx_buf = &txr->tx_buf_ring[prod];
 533                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 534
 535                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 536
 537                 flags = len << TX_BD_LEN_SHIFT;
 538                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 539         }
 540
 541         flags &= ~TX_BD_LEN;
 542         txbd->tx_bd_len_flags_type =
 543                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 544                             TX_BD_FLAGS_PACKET_END);
 545
 546         netdev_tx_sent_queue(txq, skb->len);
 547
 548         /* Sync BD data before updating doorbell */
 549         wmb();
 550
 551         prod = NEXT_TX(prod);
 552         txr->tx_prod = prod;
 553
 554         if (!skb->xmit_more || netif_xmit_stopped(txq))
 555                 bnxt_db_write(bp, &txr->tx_db, prod);
 556
 557 tx_done:
 558
 559         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 560                 if (skb->xmit_more && !tx_buf->is_push)
 561                         bnxt_db_write(bp, &txr->tx_db, prod);
 562
 563                 netif_tx_stop_queue(txq);
 564
 565                 /* netif_tx_stop_queue() must be done before checking
 566                  * tx index in bnxt_tx_avail() below, because in
 567                  * bnxt_tx_int(), we update tx index before checking for
 568                  * netif_tx_queue_stopped().
 569                  */
 570                 smp_mb();
 571                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 572                         netif_tx_wake_queue(txq);
 573         }
 574         return NETDEV_TX_OK;
 575
 576 tx_dma_error:
 577         last_frag = i;
 578
 579         /* start back at beginning and unmap skb */
 580         prod = txr->tx_prod;
 581         tx_buf = &txr->tx_buf_ring[prod];
 582         tx_buf->skb = NULL;
 583         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 584                          skb_headlen(skb), PCI_DMA_TODEVICE);
 585         prod = NEXT_TX(prod);
 586
 587         /* unmap remaining mapped pages */
 588         for (i = 0; i < last_frag; i++) {
 589                 prod = NEXT_TX(prod);
 590                 tx_buf = &txr->tx_buf_ring[prod];
 591                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 592                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 593                                PCI_DMA_TODEVICE);
 594         }
 595
 596         dev_kfree_skb_any(skb);
 597         return NETDEV_TX_OK;
 598 }
 599
 600 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 601 {
 602         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 603         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 604         u16 cons = txr->tx_cons;
 605         struct pci_dev *pdev = bp->pdev;
 606         int i;
 607         unsigned int tx_bytes = 0;
 608
 609         for (i = 0; i < nr_pkts; i++) {
 610                 struct bnxt_sw_tx_bd *tx_buf;
 611                 struct sk_buff *skb;
 612                 int j, last;
 613
 614                 tx_buf = &txr->tx_buf_ring[cons];
 615                 cons = NEXT_TX(cons);
 616                 skb = tx_buf->skb;
 617                 tx_buf->skb = NULL;
 618
 619                 if (tx_buf->is_push) {
 620                         tx_buf->is_push = 0;
 621                         goto next_tx_int;
 622                 }
 623
 624                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 625                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 626                 last = tx_buf->nr_frags;
 627
 628                 for (j = 0; j < last; j++) {
 629                         cons = NEXT_TX(cons);
 630                         tx_buf = &txr->tx_buf_ring[cons];
 631                         dma_unmap_page(
 632                                 &pdev->dev,
 633                                 dma_unmap_addr(tx_buf, mapping),
 634                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 635                                 PCI_DMA_TODEVICE);
 636                 }
 637
 638 next_tx_int:
 639                 cons = NEXT_TX(cons);
 640
 641                 tx_bytes += skb->len;
 642                 dev_kfree_skb_any(skb);
 643         }
 644
 645         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 646         txr->tx_cons = cons;
 647
 648         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 649          * before checking for netif_tx_queue_stopped().  Without the
 650          * memory barrier, there is a small possibility that bnxt_start_xmit()
 651          * will miss it and cause the queue to be stopped forever.
 652          */
 653         smp_mb();
 654
 655         if (unlikely(netif_tx_queue_stopped(txq)) &&
 656             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 657                 __netif_tx_lock(txq, smp_processor_id());
 658                 if (netif_tx_queue_stopped(txq) &&
 659                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 660                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 661                         netif_tx_wake_queue(txq);
 662                 __netif_tx_unlock(txq);
 663         }
 664 }
 665
 666 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 667                                          gfp_t gfp)
 668 {
 669         struct device *dev = &bp->pdev->dev;
 670         struct page *page;
 671
 672         page = alloc_page(gfp);
 673         if (!page)
 674                 return NULL;
 675
 676         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 677                                       DMA_ATTR_WEAK_ORDERING);
 678         if (dma_mapping_error(dev, *mapping)) {
 679                 __free_page(page);
 680                 return NULL;
 681         }
 682         *mapping += bp->rx_dma_offset;
 683         return page;
 684 }
 685
 686 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 687                                        gfp_t gfp)
 688 {
 689         u8 *data;
 690         struct pci_dev *pdev = bp->pdev;
 691
 692         data = kmalloc(bp->rx_buf_size, gfp);
 693         if (!data)
 694                 return NULL;
 695
 696         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 697                                         bp->rx_buf_use_size, bp->rx_dir,
 698                                         DMA_ATTR_WEAK_ORDERING);
 699
 700         if (dma_mapping_error(&pdev->dev, *mapping)) {
 701                 kfree(data);
 702                 data = NULL;
 703         }
 704         return data;
 705 }
 706
 707 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 708                        u16 prod, gfp_t gfp)
 709 {
 710         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 711         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 712         dma_addr_t mapping;
 713
 714         if (BNXT_RX_PAGE_MODE(bp)) {
 715                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 716
 717                 if (!page)
 718                         return -ENOMEM;
 719
 720                 rx_buf->data = page;
 721                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 722         } else {
 723                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 724
 725                 if (!data)
 726                         return -ENOMEM;
 727
 728                 rx_buf->data = data;
 729                 rx_buf->data_ptr = data + bp->rx_offset;
 730         }
 731         rx_buf->mapping = mapping;
 732
 733         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 734         return 0;
 735 }
 736
 737 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 738 {
 739         u16 prod = rxr->rx_prod;
 740         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 741         struct rx_bd *cons_bd, *prod_bd;
 742
 743         prod_rx_buf = &rxr->rx_buf_ring[prod];
 744         cons_rx_buf = &rxr->rx_buf_ring[cons];
 745
 746         prod_rx_buf->data = data;
 747         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 748
 749         prod_rx_buf->mapping = cons_rx_buf->mapping;
 750
 751         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 752         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 753
 754         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 755 }
 756
 757 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 758 {
 759         u16 next, max = rxr->rx_agg_bmap_size;
 760
 761         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 762         if (next >= max)
 763                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 764         return next;
 765 }
 766
 767 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 768                                      struct bnxt_rx_ring_info *rxr,
 769                                      u16 prod, gfp_t gfp)
 770 {
 771         struct rx_bd *rxbd =
 772                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 773         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 774         struct pci_dev *pdev = bp->pdev;
 775         struct page *page;
 776         dma_addr_t mapping;
 777         u16 sw_prod = rxr->rx_sw_agg_prod;
 778         unsigned int offset = 0;
 779
 780         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 781                 page = rxr->rx_page;
 782                 if (!page) {
 783                         page = alloc_page(gfp);
 784                         if (!page)
 785                                 return -ENOMEM;
 786                         rxr->rx_page = page;
 787                         rxr->rx_page_offset = 0;
 788                 }
 789                 offset = rxr->rx_page_offset;
 790                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 791                 if (rxr->rx_page_offset == PAGE_SIZE)
 792                         rxr->rx_page = NULL;
 793                 else
 794                         get_page(page);
 795         } else {
 796                 page = alloc_page(gfp);
 797                 if (!page)
 798                         return -ENOMEM;
 799         }
 800
 801         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 802                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 803                                      DMA_ATTR_WEAK_ORDERING);
 804         if (dma_mapping_error(&pdev->dev, mapping)) {
 805                 __free_page(page);
 806                 return -EIO;
 807         }
 808
 809         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 810                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 811
 812         __set_bit(sw_prod, rxr->rx_agg_bmap);
 813         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 814         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 815
 816         rx_agg_buf->page = page;
 817         rx_agg_buf->offset = offset;
 818         rx_agg_buf->mapping = mapping;
 819         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 820         rxbd->rx_bd_opaque = sw_prod;
 821         return 0;
 822 }
 823
 824 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
 825                                    u32 agg_bufs)
 826 {
 827         struct bnxt_napi *bnapi = cpr->bnapi;
 828         struct bnxt *bp = bnapi->bp;
 829         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 830         u16 prod = rxr->rx_agg_prod;
 831         u16 sw_prod = rxr->rx_sw_agg_prod;
 832         u32 i;
 833
 834         for (i = 0; i < agg_bufs; i++) {
 835                 u16 cons;
 836                 struct rx_agg_cmp *agg;
 837                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 838                 struct rx_bd *prod_bd;
 839                 struct page *page;
 840
 841                 agg = (struct rx_agg_cmp *)
 842                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 843                 cons = agg->rx_agg_cmp_opaque;
 844                 __clear_bit(cons, rxr->rx_agg_bmap);
 845
 846                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 847                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 848
 849                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 850                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 851                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 852
 853                 /* It is possible for sw_prod to be equal to cons, so
 854                  * set cons_rx_buf->page to NULL first.
 855                  */
 856                 page = cons_rx_buf->page;
 857                 cons_rx_buf->page = NULL;
 858                 prod_rx_buf->page = page;
 859                 prod_rx_buf->offset = cons_rx_buf->offset;
 860
 861                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 862
 863                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 864
 865                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 866                 prod_bd->rx_bd_opaque = sw_prod;
 867
 868                 prod = NEXT_RX_AGG(prod);
 869                 sw_prod = NEXT_RX_AGG(sw_prod);
 870                 cp_cons = NEXT_CMP(cp_cons);
 871         }
 872         rxr->rx_agg_prod = prod;
 873         rxr->rx_sw_agg_prod = sw_prod;
 874 }
 875
 876 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 877                                         struct bnxt_rx_ring_info *rxr,
 878                                         u16 cons, void *data, u8 *data_ptr,
 879                                         dma_addr_t dma_addr,
 880                                         unsigned int offset_and_len)
 881 {
 882         unsigned int payload = offset_and_len >> 16;
 883         unsigned int len = offset_and_len & 0xffff;
 884         struct skb_frag_struct *frag;
 885         struct page *page = data;
 886         u16 prod = rxr->rx_prod;
 887         struct sk_buff *skb;
 888         int off, err;
 889
 890         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 891         if (unlikely(err)) {
 892                 bnxt_reuse_rx_data(rxr, cons, data);
 893                 return NULL;
 894         }
 895         dma_addr -= bp->rx_dma_offset;
 896         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 897                              DMA_ATTR_WEAK_ORDERING);
 898
 899         if (unlikely(!payload))
 900                 payload = eth_get_headlen(data_ptr, len);
 901
 902         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 903         if (!skb) {
 904                 __free_page(page);
 905                 return NULL;
 906         }
 907
 908         off = (void *)data_ptr - page_address(page);
 909         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 910         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 911                payload + NET_IP_ALIGN);
 912
 913         frag = &skb_shinfo(skb)->frags[0];
 914         skb_frag_size_sub(frag, payload);
 915         frag->page_offset += payload;
 916         skb->data_len -= payload;
 917         skb->tail += payload;
 918
 919         return skb;
 920 }
 921
 922 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 923                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 924                                    void *data, u8 *data_ptr,
 925                                    dma_addr_t dma_addr,
 926                                    unsigned int offset_and_len)
 927 {
 928         u16 prod = rxr->rx_prod;
 929         struct sk_buff *skb;
 930         int err;
 931
 932         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 933         if (unlikely(err)) {
 934                 bnxt_reuse_rx_data(rxr, cons, data);
 935                 return NULL;
 936         }
 937
 938         skb = build_skb(data, 0);
 939         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 940                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 941         if (!skb) {
 942                 kfree(data);
 943                 return NULL;
 944         }
 945
 946         skb_reserve(skb, bp->rx_offset);
 947         skb_put(skb, offset_and_len & 0xffff);
 948         return skb;
 949 }
 950
 951 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
 952                                      struct bnxt_cp_ring_info *cpr,
 953                                      struct sk_buff *skb, u16 cp_cons,
 954                                      u32 agg_bufs)
 955 {
 956         struct bnxt_napi *bnapi = cpr->bnapi;
 957         struct pci_dev *pdev = bp->pdev;
 958         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 959         u16 prod = rxr->rx_agg_prod;
 960         u32 i;
 961
 962         for (i = 0; i < agg_bufs; i++) {
 963                 u16 cons, frag_len;
 964                 struct rx_agg_cmp *agg;
 965                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 966                 struct page *page;
 967                 dma_addr_t mapping;
 968
 969                 agg = (struct rx_agg_cmp *)
 970                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 971                 cons = agg->rx_agg_cmp_opaque;
 972                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 973                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 974
 975                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 976                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 977                                    cons_rx_buf->offset, frag_len);
 978                 __clear_bit(cons, rxr->rx_agg_bmap);
 979
 980                 /* It is possible for bnxt_alloc_rx_page() to allocate
 981                  * a sw_prod index that equals the cons index, so we
 982                  * need to clear the cons entry now.
 983                  */
 984                 mapping = cons_rx_buf->mapping;
 985                 page = cons_rx_buf->page;
 986                 cons_rx_buf->page = NULL;
 987
 988                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 989                         struct skb_shared_info *shinfo;
 990                         unsigned int nr_frags;
 991
 992                         shinfo = skb_shinfo(skb);
 993                         nr_frags = --shinfo->nr_frags;
 994                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 995
 996                         dev_kfree_skb(skb);
 997
 998                         cons_rx_buf->page = page;
 999
1000                         /* Update prod since possibly some pages have been
1001                          * allocated already.
1002                          */
1003                         rxr->rx_agg_prod = prod;
1004                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1005                         return NULL;
1006                 }
1007
1008                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1009                                      PCI_DMA_FROMDEVICE,
1010                                      DMA_ATTR_WEAK_ORDERING);
1011
1012                 skb->data_len += frag_len;
1013                 skb->len += frag_len;
1014                 skb->truesize += PAGE_SIZE;
1015
1016                 prod = NEXT_RX_AGG(prod);
1017                 cp_cons = NEXT_CMP(cp_cons);
1018         }
1019         rxr->rx_agg_prod = prod;
1020         return skb;
1021 }
1022
1023 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1024                                u8 agg_bufs, u32 *raw_cons)
1025 {
1026         u16 last;
1027         struct rx_agg_cmp *agg;
1028
1029         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1030         last = RING_CMP(*raw_cons);
1031         agg = (struct rx_agg_cmp *)
1032                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1033         return RX_AGG_CMP_VALID(agg, *raw_cons);
1034 }
1035
1036 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1037                                             unsigned int len,
1038                                             dma_addr_t mapping)
1039 {
1040         struct bnxt *bp = bnapi->bp;
1041         struct pci_dev *pdev = bp->pdev;
1042         struct sk_buff *skb;
1043
1044         skb = napi_alloc_skb(&bnapi->napi, len);
1045         if (!skb)
1046                 return NULL;
1047
1048         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1049                                 bp->rx_dir);
1050
1051         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1052                len + NET_IP_ALIGN);
1053
1054         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1055                                    bp->rx_dir);
1056
1057         skb_put(skb, len);
1058         return skb;
1059 }
1060
1061 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1062                            u32 *raw_cons, void *cmp)
1063 {
1064         struct rx_cmp *rxcmp = cmp;
1065         u32 tmp_raw_cons = *raw_cons;
1066         u8 cmp_type, agg_bufs = 0;
1067
1068         cmp_type = RX_CMP_TYPE(rxcmp);
1069
1070         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1071                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1072                             RX_CMP_AGG_BUFS) >>
1073                            RX_CMP_AGG_BUFS_SHIFT;
1074         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1075                 struct rx_tpa_end_cmp *tpa_end = cmp;
1076
1077                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1078                             RX_TPA_END_CMP_AGG_BUFS) >>
1079                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1080         }
1081
1082         if (agg_bufs) {
1083                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1084                         return -EBUSY;
1085         }
1086         *raw_cons = tmp_raw_cons;
1087         return 0;
1088 }
1089
1090 static void bnxt_queue_sp_work(struct bnxt *bp)
1091 {
1092         if (BNXT_PF(bp))
1093                 queue_work(bnxt_pf_wq, &bp->sp_task);
1094         else
1095                 schedule_work(&bp->sp_task);
1096 }
1097
1098 static void bnxt_cancel_sp_work(struct bnxt *bp)
1099 {
1100         if (BNXT_PF(bp))
1101                 flush_workqueue(bnxt_pf_wq);
1102         else
1103                 cancel_work_sync(&bp->sp_task);
1104 }
1105
1106 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1107 {
1108         if (!rxr->bnapi->in_reset) {
1109                 rxr->bnapi->in_reset = true;
1110                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1111                 bnxt_queue_sp_work(bp);
1112         }
1113         rxr->rx_next_cons = 0xffff;
1114 }
1115
1116 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1117                            struct rx_tpa_start_cmp *tpa_start,
1118                            struct rx_tpa_start_cmp_ext *tpa_start1)
1119 {
1120         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1121         u16 cons, prod;
1122         struct bnxt_tpa_info *tpa_info;
1123         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1124         struct rx_bd *prod_bd;
1125         dma_addr_t mapping;
1126
1127         cons = tpa_start->rx_tpa_start_cmp_opaque;
1128         prod = rxr->rx_prod;
1129         cons_rx_buf = &rxr->rx_buf_ring[cons];
1130         prod_rx_buf = &rxr->rx_buf_ring[prod];
1131         tpa_info = &rxr->rx_tpa[agg_id];
1132
1133         if (unlikely(cons != rxr->rx_next_cons)) {
1134                 bnxt_sched_reset(bp, rxr);
1135                 return;
1136         }
1137         /* Store cfa_code in tpa_info to use in tpa_end
1138          * completion processing.
1139          */
1140         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1141         prod_rx_buf->data = tpa_info->data;
1142         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1143
1144         mapping = tpa_info->mapping;
1145         prod_rx_buf->mapping = mapping;
1146
1147         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1148
1149         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1150
1151         tpa_info->data = cons_rx_buf->data;
1152         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1153         cons_rx_buf->data = NULL;
1154         tpa_info->mapping = cons_rx_buf->mapping;
1155
1156         tpa_info->len =
1157                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1158                                 RX_TPA_START_CMP_LEN_SHIFT;
1159         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1160                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1161
1162                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1163                 tpa_info->gso_type = SKB_GSO_TCPV4;
1164                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1165                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1166                         tpa_info->gso_type = SKB_GSO_TCPV6;
1167                 tpa_info->rss_hash =
1168                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1169         } else {
1170                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1171                 tpa_info->gso_type = 0;
1172                 if (netif_msg_rx_err(bp))
1173                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1174         }
1175         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1176         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1177         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1178
1179         rxr->rx_prod = NEXT_RX(prod);
1180         cons = NEXT_RX(cons);
1181         rxr->rx_next_cons = NEXT_RX(cons);
1182         cons_rx_buf = &rxr->rx_buf_ring[cons];
1183
1184         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1185         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1186         cons_rx_buf->data = NULL;
1187 }
1188
1189 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1190                            u32 agg_bufs)
1191 {
1192         if (agg_bufs)
1193                 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1194 }
1195
1196 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1197                                            int payload_off, int tcp_ts,
1198                                            struct sk_buff *skb)
1199 {
1200 #ifdef CONFIG_INET
1201         struct tcphdr *th;
1202         int len, nw_off;
1203         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1204         u32 hdr_info = tpa_info->hdr_info;
1205         bool loopback = false;
1206
1207         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1208         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1209         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1210
1211         /* If the packet is an internal loopback packet, the offsets will
1212          * have an extra 4 bytes.
1213          */
1214         if (inner_mac_off == 4) {
1215                 loopback = true;
1216         } else if (inner_mac_off > 4) {
1217                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1218                                             ETH_HLEN - 2));
1219
1220                 /* We only support inner iPv4/ipv6.  If we don't see the
1221                  * correct protocol ID, it must be a loopback packet where
1222                  * the offsets are off by 4.
1223                  */
1224                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1225                         loopback = true;
1226         }
1227         if (loopback) {
1228                 /* internal loopback packet, subtract all offsets by 4 */
1229                 inner_ip_off -= 4;
1230                 inner_mac_off -= 4;
1231                 outer_ip_off -= 4;
1232         }
1233
1234         nw_off = inner_ip_off - ETH_HLEN;
1235         skb_set_network_header(skb, nw_off);
1236         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1237                 struct ipv6hdr *iph = ipv6_hdr(skb);
1238
1239                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1240                 len = skb->len - skb_transport_offset(skb);
1241                 th = tcp_hdr(skb);
1242                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1243         } else {
1244                 struct iphdr *iph = ip_hdr(skb);
1245
1246                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1247                 len = skb->len - skb_transport_offset(skb);
1248                 th = tcp_hdr(skb);
1249                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1250         }
1251
1252         if (inner_mac_off) { /* tunnel */
1253                 struct udphdr *uh = NULL;
1254                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1255                                             ETH_HLEN - 2));
1256
1257                 if (proto == htons(ETH_P_IP)) {
1258                         struct iphdr *iph = (struct iphdr *)skb->data;
1259
1260                         if (iph->protocol == IPPROTO_UDP)
1261                                 uh = (struct udphdr *)(iph + 1);
1262                 } else {
1263                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1264
1265                         if (iph->nexthdr == IPPROTO_UDP)
1266                                 uh = (struct udphdr *)(iph + 1);
1267                 }
1268                 if (uh) {
1269                         if (uh->check)
1270                                 skb_shinfo(skb)->gso_type |=
1271                                         SKB_GSO_UDP_TUNNEL_CSUM;
1272                         else
1273                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1274                 }
1275         }
1276 #endif
1277         return skb;
1278 }
1279
1280 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1281 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1282
1283 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1284                                            int payload_off, int tcp_ts,
1285                                            struct sk_buff *skb)
1286 {
1287 #ifdef CONFIG_INET
1288         struct tcphdr *th;
1289         int len, nw_off, tcp_opt_len = 0;
1290
1291         if (tcp_ts)
1292                 tcp_opt_len = 12;
1293
1294         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1295                 struct iphdr *iph;
1296
1297                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1298                          ETH_HLEN;
1299                 skb_set_network_header(skb, nw_off);
1300                 iph = ip_hdr(skb);
1301                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1302                 len = skb->len - skb_transport_offset(skb);
1303                 th = tcp_hdr(skb);
1304                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1305         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1306                 struct ipv6hdr *iph;
1307
1308                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1309                          ETH_HLEN;
1310                 skb_set_network_header(skb, nw_off);
1311                 iph = ipv6_hdr(skb);
1312                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1313                 len = skb->len - skb_transport_offset(skb);
1314                 th = tcp_hdr(skb);
1315                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1316         } else {
1317                 dev_kfree_skb_any(skb);
1318                 return NULL;
1319         }
1320
1321         if (nw_off) { /* tunnel */
1322                 struct udphdr *uh = NULL;
1323
1324                 if (skb->protocol == htons(ETH_P_IP)) {
1325                         struct iphdr *iph = (struct iphdr *)skb->data;
1326
1327                         if (iph->protocol == IPPROTO_UDP)
1328                                 uh = (struct udphdr *)(iph + 1);
1329                 } else {
1330                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1331
1332                         if (iph->nexthdr == IPPROTO_UDP)
1333                                 uh = (struct udphdr *)(iph + 1);
1334                 }
1335                 if (uh) {
1336                         if (uh->check)
1337                                 skb_shinfo(skb)->gso_type |=
1338                                         SKB_GSO_UDP_TUNNEL_CSUM;
1339                         else
1340                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1341                 }
1342         }
1343 #endif
1344         return skb;
1345 }
1346
1347 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1348                                            struct bnxt_tpa_info *tpa_info,
1349                                            struct rx_tpa_end_cmp *tpa_end,
1350                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1351                                            struct sk_buff *skb)
1352 {
1353 #ifdef CONFIG_INET
1354         int payload_off;
1355         u16 segs;
1356
1357         segs = TPA_END_TPA_SEGS(tpa_end);
1358         if (segs == 1)
1359                 return skb;
1360
1361         NAPI_GRO_CB(skb)->count = segs;
1362         skb_shinfo(skb)->gso_size =
1363                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1364         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1365         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1366                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1367                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1368         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1369         if (likely(skb))
1370                 tcp_gro_complete(skb);
1371 #endif
1372         return skb;
1373 }
1374
1375 /* Given the cfa_code of a received packet determine which
1376  * netdev (vf-rep or PF) the packet is destined to.
1377  */
1378 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1379 {
1380         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1381
1382         /* if vf-rep dev is NULL, the must belongs to the PF */
1383         return dev ? dev : bp->dev;
1384 }
1385
1386 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1387                                            struct bnxt_cp_ring_info *cpr,
1388                                            u32 *raw_cons,
1389                                            struct rx_tpa_end_cmp *tpa_end,
1390                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1391                                            u8 *event)
1392 {
1393         struct bnxt_napi *bnapi = cpr->bnapi;
1394         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1395         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1396         u8 *data_ptr, agg_bufs;
1397         u16 cp_cons = RING_CMP(*raw_cons);
1398         unsigned int len;
1399         struct bnxt_tpa_info *tpa_info;
1400         dma_addr_t mapping;
1401         struct sk_buff *skb;
1402         void *data;
1403
1404         if (unlikely(bnapi->in_reset)) {
1405                 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1406
1407                 if (rc < 0)
1408                         return ERR_PTR(-EBUSY);
1409                 return NULL;
1410         }
1411
1412         tpa_info = &rxr->rx_tpa[agg_id];
1413         data = tpa_info->data;
1414         data_ptr = tpa_info->data_ptr;
1415         prefetch(data_ptr);
1416         len = tpa_info->len;
1417         mapping = tpa_info->mapping;
1418
1419         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1420                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1421
1422         if (agg_bufs) {
1423                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1424                         return ERR_PTR(-EBUSY);
1425
1426                 *event |= BNXT_AGG_EVENT;
1427                 cp_cons = NEXT_CMP(cp_cons);
1428         }
1429
1430         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1431                 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1432                 if (agg_bufs > MAX_SKB_FRAGS)
1433                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1434                                     agg_bufs, (int)MAX_SKB_FRAGS);
1435                 return NULL;
1436         }
1437
1438         if (len <= bp->rx_copy_thresh) {
1439                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1440                 if (!skb) {
1441                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1442                         return NULL;
1443                 }
1444         } else {
1445                 u8 *new_data;
1446                 dma_addr_t new_mapping;
1447
1448                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1449                 if (!new_data) {
1450                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1451                         return NULL;
1452                 }
1453
1454                 tpa_info->data = new_data;
1455                 tpa_info->data_ptr = new_data + bp->rx_offset;
1456                 tpa_info->mapping = new_mapping;
1457
1458                 skb = build_skb(data, 0);
1459                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1460                                        bp->rx_buf_use_size, bp->rx_dir,
1461                                        DMA_ATTR_WEAK_ORDERING);
1462
1463                 if (!skb) {
1464                         kfree(data);
1465                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1466                         return NULL;
1467                 }
1468                 skb_reserve(skb, bp->rx_offset);
1469                 skb_put(skb, len);
1470         }
1471
1472         if (agg_bufs) {
1473                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1474                 if (!skb) {
1475                         /* Page reuse already handled by bnxt_rx_pages(). */
1476                         return NULL;
1477                 }
1478         }
1479
1480         skb->protocol =
1481                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1482
1483         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1484                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1485
1486         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1487             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1488                 u16 vlan_proto = tpa_info->metadata >>
1489                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1490                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1491
1492                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1493         }
1494
1495         skb_checksum_none_assert(skb);
1496         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1497                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1498                 skb->csum_level =
1499                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1500         }
1501
1502         if (TPA_END_GRO(tpa_end))
1503                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1504
1505         return skb;
1506 }
1507
1508 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1509                              struct sk_buff *skb)
1510 {
1511         if (skb->dev != bp->dev) {
1512                 /* this packet belongs to a vf-rep */
1513                 bnxt_vf_rep_rx(bp, skb);
1514                 return;
1515         }
1516         skb_record_rx_queue(skb, bnapi->index);
1517         napi_gro_receive(&bnapi->napi, skb);
1518 }
1519
1520 /* returns the following:
1521  * 1       - 1 packet successfully received
1522  * 0       - successful TPA_START, packet not completed yet
1523  * -EBUSY  - completion ring does not have all the agg buffers yet
1524  * -ENOMEM - packet aborted due to out of memory
1525  * -EIO    - packet aborted due to hw error indicated in BD
1526  */
1527 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1528                        u32 *raw_cons, u8 *event)
1529 {
1530         struct bnxt_napi *bnapi = cpr->bnapi;
1531         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1532         struct net_device *dev = bp->dev;
1533         struct rx_cmp *rxcmp;
1534         struct rx_cmp_ext *rxcmp1;
1535         u32 tmp_raw_cons = *raw_cons;
1536         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1537         struct bnxt_sw_rx_bd *rx_buf;
1538         unsigned int len;
1539         u8 *data_ptr, agg_bufs, cmp_type;
1540         dma_addr_t dma_addr;
1541         struct sk_buff *skb;
1542         void *data;
1543         int rc = 0;
1544         u32 misc;
1545
1546         rxcmp = (struct rx_cmp *)
1547                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1548
1549         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1550         cp_cons = RING_CMP(tmp_raw_cons);
1551         rxcmp1 = (struct rx_cmp_ext *)
1552                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1553
1554         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1555                 return -EBUSY;
1556
1557         cmp_type = RX_CMP_TYPE(rxcmp);
1558
1559         prod = rxr->rx_prod;
1560
1561         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1562                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1563                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1564
1565                 *event |= BNXT_RX_EVENT;
1566                 goto next_rx_no_prod_no_len;
1567
1568         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1569                 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1570                                    (struct rx_tpa_end_cmp *)rxcmp,
1571                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1572
1573                 if (IS_ERR(skb))
1574                         return -EBUSY;
1575
1576                 rc = -ENOMEM;
1577                 if (likely(skb)) {
1578                         bnxt_deliver_skb(bp, bnapi, skb);
1579                         rc = 1;
1580                 }
1581                 *event |= BNXT_RX_EVENT;
1582                 goto next_rx_no_prod_no_len;
1583         }
1584
1585         cons = rxcmp->rx_cmp_opaque;
1586         rx_buf = &rxr->rx_buf_ring[cons];
1587         data = rx_buf->data;
1588         data_ptr = rx_buf->data_ptr;
1589         if (unlikely(cons != rxr->rx_next_cons)) {
1590                 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1591
1592                 bnxt_sched_reset(bp, rxr);
1593                 return rc1;
1594         }
1595         prefetch(data_ptr);
1596
1597         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1598         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1599
1600         if (agg_bufs) {
1601                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1602                         return -EBUSY;
1603
1604                 cp_cons = NEXT_CMP(cp_cons);
1605                 *event |= BNXT_AGG_EVENT;
1606         }
1607         *event |= BNXT_RX_EVENT;
1608
1609         rx_buf->data = NULL;
1610         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1611                 bnxt_reuse_rx_data(rxr, cons, data);
1612                 if (agg_bufs)
1613                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1614
1615                 rc = -EIO;
1616                 goto next_rx;
1617         }
1618
1619         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1620         dma_addr = rx_buf->mapping;
1621
1622         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1623                 rc = 1;
1624                 goto next_rx;
1625         }
1626
1627         if (len <= bp->rx_copy_thresh) {
1628                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1629                 bnxt_reuse_rx_data(rxr, cons, data);
1630                 if (!skb) {
1631                         rc = -ENOMEM;
1632                         goto next_rx;
1633                 }
1634         } else {
1635                 u32 payload;
1636
1637                 if (rx_buf->data_ptr == data_ptr)
1638                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1639                 else
1640                         payload = 0;
1641                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1642                                       payload | len);
1643                 if (!skb) {
1644                         rc = -ENOMEM;
1645                         goto next_rx;
1646                 }
1647         }
1648
1649         if (agg_bufs) {
1650                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1651                 if (!skb) {
1652                         rc = -ENOMEM;
1653                         goto next_rx;
1654                 }
1655         }
1656
1657         if (RX_CMP_HASH_VALID(rxcmp)) {
1658                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1659                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1660
1661                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1662                 if (hash_type != 1 && hash_type != 3)
1663                         type = PKT_HASH_TYPE_L3;
1664                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1665         }
1666
1667         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1668         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1669
1670         if ((rxcmp1->rx_cmp_flags2 &
1671              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1672             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1673                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1674                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1675                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1676
1677                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1678         }
1679
1680         skb_checksum_none_assert(skb);
1681         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1682                 if (dev->features & NETIF_F_RXCSUM) {
1683                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1684                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1685                 }
1686         } else {
1687                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1688                         if (dev->features & NETIF_F_RXCSUM)
1689                                 bnapi->cp_ring.rx_l4_csum_errors++;
1690                 }
1691         }
1692
1693         bnxt_deliver_skb(bp, bnapi, skb);
1694         rc = 1;
1695
1696 next_rx:
1697         rxr->rx_prod = NEXT_RX(prod);
1698         rxr->rx_next_cons = NEXT_RX(cons);
1699
1700         cpr->rx_packets += 1;
1701         cpr->rx_bytes += len;
1702
1703 next_rx_no_prod_no_len:
1704         *raw_cons = tmp_raw_cons;
1705
1706         return rc;
1707 }
1708
1709 /* In netpoll mode, if we are using a combined completion ring, we need to
1710  * discard the rx packets and recycle the buffers.
1711  */
1712 static int bnxt_force_rx_discard(struct bnxt *bp,
1713                                  struct bnxt_cp_ring_info *cpr,
1714                                  u32 *raw_cons, u8 *event)
1715 {
1716         u32 tmp_raw_cons = *raw_cons;
1717         struct rx_cmp_ext *rxcmp1;
1718         struct rx_cmp *rxcmp;
1719         u16 cp_cons;
1720         u8 cmp_type;
1721
1722         cp_cons = RING_CMP(tmp_raw_cons);
1723         rxcmp = (struct rx_cmp *)
1724                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1725
1726         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1727         cp_cons = RING_CMP(tmp_raw_cons);
1728         rxcmp1 = (struct rx_cmp_ext *)
1729                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1730
1731         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1732                 return -EBUSY;
1733
1734         cmp_type = RX_CMP_TYPE(rxcmp);
1735         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1736                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1737                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1738         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1739                 struct rx_tpa_end_cmp_ext *tpa_end1;
1740
1741                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1742                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1743                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1744         }
1745         return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1746 }
1747
1748 #define BNXT_GET_EVENT_PORT(data)       \
1749         ((data) &                       \
1750          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1751
1752 static int bnxt_async_event_process(struct bnxt *bp,
1753                                     struct hwrm_async_event_cmpl *cmpl)
1754 {
1755         u16 event_id = le16_to_cpu(cmpl->event_id);
1756
1757         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1758         switch (event_id) {
1759         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1760                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1761                 struct bnxt_link_info *link_info = &bp->link_info;
1762
1763                 if (BNXT_VF(bp))
1764                         goto async_event_process_exit;
1765
1766                 /* print unsupported speed warning in forced speed mode only */
1767                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1768                     (data1 & 0x20000)) {
1769                         u16 fw_speed = link_info->force_link_speed;
1770                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1771
1772                         if (speed != SPEED_UNKNOWN)
1773                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1774                                             speed);
1775                 }
1776                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1777         }
1778         /* fall through */
1779         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1780                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1781                 break;
1782         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1783                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1784                 break;
1785         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1786                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1787                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1788
1789                 if (BNXT_VF(bp))
1790                         break;
1791
1792                 if (bp->pf.port_id != port_id)
1793                         break;
1794
1795                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1796                 break;
1797         }
1798         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1799                 if (BNXT_PF(bp))
1800                         goto async_event_process_exit;
1801                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1802                 break;
1803         default:
1804                 goto async_event_process_exit;
1805         }
1806         bnxt_queue_sp_work(bp);
1807 async_event_process_exit:
1808         bnxt_ulp_async_events(bp, cmpl);
1809         return 0;
1810 }
1811
1812 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1813 {
1814         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1815         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1816         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1817                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1818
1819         switch (cmpl_type) {
1820         case CMPL_BASE_TYPE_HWRM_DONE:
1821                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1822                 if (seq_id == bp->hwrm_intr_seq_id)
1823                         bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1824                 else
1825                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1826                 break;
1827
1828         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1829                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1830
1831                 if ((vf_id < bp->pf.first_vf_id) ||
1832                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1833                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1834                                    vf_id);
1835                         return -EINVAL;
1836                 }
1837
1838                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1839                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1840                 bnxt_queue_sp_work(bp);
1841                 break;
1842
1843         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1844                 bnxt_async_event_process(bp,
1845                                          (struct hwrm_async_event_cmpl *)txcmp);
1846
1847         default:
1848                 break;
1849         }
1850
1851         return 0;
1852 }
1853
1854 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1855 {
1856         struct bnxt_napi *bnapi = dev_instance;
1857         struct bnxt *bp = bnapi->bp;
1858         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1859         u32 cons = RING_CMP(cpr->cp_raw_cons);
1860
1861         cpr->event_ctr++;
1862         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1863         napi_schedule(&bnapi->napi);
1864         return IRQ_HANDLED;
1865 }
1866
1867 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1868 {
1869         u32 raw_cons = cpr->cp_raw_cons;
1870         u16 cons = RING_CMP(raw_cons);
1871         struct tx_cmp *txcmp;
1872
1873         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1874
1875         return TX_CMP_VALID(txcmp, raw_cons);
1876 }
1877
1878 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1879 {
1880         struct bnxt_napi *bnapi = dev_instance;
1881         struct bnxt *bp = bnapi->bp;
1882         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1883         u32 cons = RING_CMP(cpr->cp_raw_cons);
1884         u32 int_status;
1885
1886         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1887
1888         if (!bnxt_has_work(bp, cpr)) {
1889                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1890                 /* return if erroneous interrupt */
1891                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1892                         return IRQ_NONE;
1893         }
1894
1895         /* disable ring IRQ */
1896         BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1897
1898         /* Return here if interrupt is shared and is disabled. */
1899         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1900                 return IRQ_HANDLED;
1901
1902         napi_schedule(&bnapi->napi);
1903         return IRQ_HANDLED;
1904 }
1905
1906 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1907                             int budget)
1908 {
1909         struct bnxt_napi *bnapi = cpr->bnapi;
1910         u32 raw_cons = cpr->cp_raw_cons;
1911         u32 cons;
1912         int tx_pkts = 0;
1913         int rx_pkts = 0;
1914         u8 event = 0;
1915         struct tx_cmp *txcmp;
1916
1917         cpr->has_more_work = 0;
1918         while (1) {
1919                 int rc;
1920
1921                 cons = RING_CMP(raw_cons);
1922                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1923
1924                 if (!TX_CMP_VALID(txcmp, raw_cons))
1925                         break;
1926
1927                 /* The valid test of the entry must be done first before
1928                  * reading any further.
1929                  */
1930                 dma_rmb();
1931                 cpr->had_work_done = 1;
1932                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1933                         tx_pkts++;
1934                         /* return full budget so NAPI will complete. */
1935                         if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1936                                 rx_pkts = budget;
1937                                 raw_cons = NEXT_RAW_CMP(raw_cons);
1938                                 if (budget)
1939                                         cpr->has_more_work = 1;
1940                                 break;
1941                         }
1942                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1943                         if (likely(budget))
1944                                 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1945                         else
1946                                 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1947                                                            &event);
1948                         if (likely(rc >= 0))
1949                                 rx_pkts += rc;
1950                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1951                          * the NAPI budget.  Otherwise, we may potentially loop
1952                          * here forever if we consistently cannot allocate
1953                          * buffers.
1954                          */
1955                         else if (rc == -ENOMEM && budget)
1956                                 rx_pkts++;
1957                         else if (rc == -EBUSY)  /* partial completion */
1958                                 break;
1959                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1960                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1961                                     (TX_CMP_TYPE(txcmp) ==
1962                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1963                                     (TX_CMP_TYPE(txcmp) ==
1964                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1965                         bnxt_hwrm_handler(bp, txcmp);
1966                 }
1967                 raw_cons = NEXT_RAW_CMP(raw_cons);
1968
1969                 if (rx_pkts && rx_pkts == budget) {
1970                         cpr->has_more_work = 1;
1971                         break;
1972                 }
1973         }
1974
1975         if (event & BNXT_TX_EVENT) {
1976                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1977                 u16 prod = txr->tx_prod;
1978
1979                 /* Sync BD data before updating doorbell */
1980                 wmb();
1981
1982                 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
1983         }
1984
1985         cpr->cp_raw_cons = raw_cons;
1986         bnapi->tx_pkts += tx_pkts;
1987         bnapi->events |= event;
1988         return rx_pkts;
1989 }
1990
1991 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
1992 {
1993         if (bnapi->tx_pkts) {
1994                 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
1995                 bnapi->tx_pkts = 0;
1996         }
1997
1998         if (bnapi->events & BNXT_RX_EVENT) {
1999                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2000
2001                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2002                 if (bnapi->events & BNXT_AGG_EVENT)
2003                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2004         }
2005         bnapi->events = 0;
2006 }
2007
2008 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2009                           int budget)
2010 {
2011         struct bnxt_napi *bnapi = cpr->bnapi;
2012         int rx_pkts;
2013
2014         rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2015
2016         /* ACK completion ring before freeing tx ring and producing new
2017          * buffers in rx/agg rings to prevent overflowing the completion
2018          * ring.
2019          */
2020         bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2021
2022         __bnxt_poll_work_done(bp, bnapi);
2023         return rx_pkts;
2024 }
2025
2026 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2027 {
2028         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2029         struct bnxt *bp = bnapi->bp;
2030         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2031         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2032         struct tx_cmp *txcmp;
2033         struct rx_cmp_ext *rxcmp1;
2034         u32 cp_cons, tmp_raw_cons;
2035         u32 raw_cons = cpr->cp_raw_cons;
2036         u32 rx_pkts = 0;
2037         u8 event = 0;
2038
2039         while (1) {
2040                 int rc;
2041
2042                 cp_cons = RING_CMP(raw_cons);
2043                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2044
2045                 if (!TX_CMP_VALID(txcmp, raw_cons))
2046                         break;
2047
2048                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2049                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2050                         cp_cons = RING_CMP(tmp_raw_cons);
2051                         rxcmp1 = (struct rx_cmp_ext *)
2052                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2053
2054                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2055                                 break;
2056
2057                         /* force an error to recycle the buffer */
2058                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2059                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2060
2061                         rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2062                         if (likely(rc == -EIO) && budget)
2063                                 rx_pkts++;
2064                         else if (rc == -EBUSY)  /* partial completion */
2065                                 break;
2066                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2067                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2068                         bnxt_hwrm_handler(bp, txcmp);
2069                 } else {
2070                         netdev_err(bp->dev,
2071                                    "Invalid completion received on special ring\n");
2072                 }
2073                 raw_cons = NEXT_RAW_CMP(raw_cons);
2074
2075                 if (rx_pkts == budget)
2076                         break;
2077         }
2078
2079         cpr->cp_raw_cons = raw_cons;
2080         BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2081         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2082
2083         if (event & BNXT_AGG_EVENT)
2084                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2085
2086         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2087                 napi_complete_done(napi, rx_pkts);
2088                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2089         }
2090         return rx_pkts;
2091 }
2092
2093 static int bnxt_poll(struct napi_struct *napi, int budget)
2094 {
2095         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2096         struct bnxt *bp = bnapi->bp;
2097         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2098         int work_done = 0;
2099
2100         while (1) {
2101                 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2102
2103                 if (work_done >= budget) {
2104                         if (!budget)
2105                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2106                         break;
2107                 }
2108
2109                 if (!bnxt_has_work(bp, cpr)) {
2110                         if (napi_complete_done(napi, work_done))
2111                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2112                         break;
2113                 }
2114         }
2115         if (bp->flags & BNXT_FLAG_DIM) {
2116                 struct net_dim_sample dim_sample;
2117
2118                 net_dim_sample(cpr->event_ctr,
2119                                cpr->rx_packets,
2120                                cpr->rx_bytes,
2121                                &dim_sample);
2122                 net_dim(&cpr->dim, dim_sample);
2123         }
2124         return work_done;
2125 }
2126
2127 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2128 {
2129         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2130         int i, work_done = 0;
2131
2132         for (i = 0; i < 2; i++) {
2133                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2134
2135                 if (cpr2) {
2136                         work_done += __bnxt_poll_work(bp, cpr2,
2137                                                       budget - work_done);
2138                         cpr->has_more_work |= cpr2->has_more_work;
2139                 }
2140         }
2141         return work_done;
2142 }
2143
2144 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2145                                  u64 dbr_type, bool all)
2146 {
2147         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2148         int i;
2149
2150         for (i = 0; i < 2; i++) {
2151                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2152                 struct bnxt_db_info *db;
2153
2154                 if (cpr2 && (all || cpr2->had_work_done)) {
2155                         db = &cpr2->cp_db;
2156                         writeq(db->db_key64 | dbr_type |
2157                                RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2158                         cpr2->had_work_done = 0;
2159                 }
2160         }
2161         __bnxt_poll_work_done(bp, bnapi);
2162 }
2163
2164 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2165 {
2166         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2167         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2168         u32 raw_cons = cpr->cp_raw_cons;
2169         struct bnxt *bp = bnapi->bp;
2170         struct nqe_cn *nqcmp;
2171         int work_done = 0;
2172         u32 cons;
2173
2174         if (cpr->has_more_work) {
2175                 cpr->has_more_work = 0;
2176                 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2177                 if (cpr->has_more_work) {
2178                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2179                         return work_done;
2180                 }
2181                 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2182                 if (napi_complete_done(napi, work_done))
2183                         BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2184                 return work_done;
2185         }
2186         while (1) {
2187                 cons = RING_CMP(raw_cons);
2188                 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2189
2190                 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2191                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2192                                              false);
2193                         cpr->cp_raw_cons = raw_cons;
2194                         if (napi_complete_done(napi, work_done))
2195                                 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2196                                                   cpr->cp_raw_cons);
2197                         return work_done;
2198                 }
2199
2200                 /* The valid test of the entry must be done first before
2201                  * reading any further.
2202                  */
2203                 dma_rmb();
2204
2205                 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2206                         u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2207                         struct bnxt_cp_ring_info *cpr2;
2208
2209                         cpr2 = cpr->cp_ring_arr[idx];
2210                         work_done += __bnxt_poll_work(bp, cpr2,
2211                                                       budget - work_done);
2212                         cpr->has_more_work = cpr2->has_more_work;
2213                 } else {
2214                         bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2215                 }
2216                 raw_cons = NEXT_RAW_CMP(raw_cons);
2217                 if (cpr->has_more_work)
2218                         break;
2219         }
2220         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2221         cpr->cp_raw_cons = raw_cons;
2222         return work_done;
2223 }
2224
2225 static void bnxt_free_tx_skbs(struct bnxt *bp)
2226 {
2227         int i, max_idx;
2228         struct pci_dev *pdev = bp->pdev;
2229
2230         if (!bp->tx_ring)
2231                 return;
2232
2233         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2234         for (i = 0; i < bp->tx_nr_rings; i++) {
2235                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2236                 int j;
2237
2238                 for (j = 0; j < max_idx;) {
2239                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2240                         struct sk_buff *skb = tx_buf->skb;
2241                         int k, last;
2242
2243                         if (!skb) {
2244                                 j++;
2245                                 continue;
2246                         }
2247
2248                         tx_buf->skb = NULL;
2249
2250                         if (tx_buf->is_push) {
2251                                 dev_kfree_skb(skb);
2252                                 j += 2;
2253                                 continue;
2254                         }
2255
2256                         dma_unmap_single(&pdev->dev,
2257                                          dma_unmap_addr(tx_buf, mapping),
2258                                          skb_headlen(skb),
2259                                          PCI_DMA_TODEVICE);
2260
2261                         last = tx_buf->nr_frags;
2262                         j += 2;
2263                         for (k = 0; k < last; k++, j++) {
2264                                 int ring_idx = j & bp->tx_ring_mask;
2265                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2266
2267                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2268                                 dma_unmap_page(
2269                                         &pdev->dev,
2270                                         dma_unmap_addr(tx_buf, mapping),
2271                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2272                         }
2273                         dev_kfree_skb(skb);
2274                 }
2275                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2276         }
2277 }
2278
2279 static void bnxt_free_rx_skbs(struct bnxt *bp)
2280 {
2281         int i, max_idx, max_agg_idx;
2282         struct pci_dev *pdev = bp->pdev;
2283
2284         if (!bp->rx_ring)
2285                 return;
2286
2287         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2288         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2289         for (i = 0; i < bp->rx_nr_rings; i++) {
2290                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2291                 int j;
2292
2293                 if (rxr->rx_tpa) {
2294                         for (j = 0; j < MAX_TPA; j++) {
2295                                 struct bnxt_tpa_info *tpa_info =
2296                                                         &rxr->rx_tpa[j];
2297                                 u8 *data = tpa_info->data;
2298
2299                                 if (!data)
2300                                         continue;
2301
2302                                 dma_unmap_single_attrs(&pdev->dev,
2303                                                        tpa_info->mapping,
2304                                                        bp->rx_buf_use_size,
2305                                                        bp->rx_dir,
2306                                                        DMA_ATTR_WEAK_ORDERING);
2307
2308                                 tpa_info->data = NULL;
2309
2310                                 kfree(data);
2311                         }
2312                 }
2313
2314                 for (j = 0; j < max_idx; j++) {
2315                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2316                         dma_addr_t mapping = rx_buf->mapping;
2317                         void *data = rx_buf->data;
2318
2319                         if (!data)
2320                                 continue;
2321
2322                         rx_buf->data = NULL;
2323
2324                         if (BNXT_RX_PAGE_MODE(bp)) {
2325                                 mapping -= bp->rx_dma_offset;
2326                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2327                                                      PAGE_SIZE, bp->rx_dir,
2328                                                      DMA_ATTR_WEAK_ORDERING);
2329                                 __free_page(data);
2330                         } else {
2331                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2332                                                        bp->rx_buf_use_size,
2333                                                        bp->rx_dir,
2334                                                        DMA_ATTR_WEAK_ORDERING);
2335                                 kfree(data);
2336                         }
2337                 }
2338
2339                 for (j = 0; j < max_agg_idx; j++) {
2340                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2341                                 &rxr->rx_agg_ring[j];
2342                         struct page *page = rx_agg_buf->page;
2343
2344                         if (!page)
2345                                 continue;
2346
2347                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2348                                              BNXT_RX_PAGE_SIZE,
2349                                              PCI_DMA_FROMDEVICE,
2350                                              DMA_ATTR_WEAK_ORDERING);
2351
2352                         rx_agg_buf->page = NULL;
2353                         __clear_bit(j, rxr->rx_agg_bmap);
2354
2355                         __free_page(page);
2356                 }
2357                 if (rxr->rx_page) {
2358                         __free_page(rxr->rx_page);
2359                         rxr->rx_page = NULL;
2360                 }
2361         }
2362 }
2363
2364 static void bnxt_free_skbs(struct bnxt *bp)
2365 {
2366         bnxt_free_tx_skbs(bp);
2367         bnxt_free_rx_skbs(bp);
2368 }
2369
2370 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2371 {
2372         struct pci_dev *pdev = bp->pdev;
2373         int i;
2374
2375         for (i = 0; i < rmem->nr_pages; i++) {
2376                 if (!rmem->pg_arr[i])
2377                         continue;
2378
2379                 dma_free_coherent(&pdev->dev, rmem->page_size,
2380                                   rmem->pg_arr[i], rmem->dma_arr[i]);
2381
2382                 rmem->pg_arr[i] = NULL;
2383         }
2384         if (rmem->pg_tbl) {
2385                 size_t pg_tbl_size = rmem->nr_pages * 8;
2386
2387                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2388                         pg_tbl_size = rmem->page_size;
2389                 dma_free_coherent(&pdev->dev, pg_tbl_size,
2390                                   rmem->pg_tbl, rmem->pg_tbl_map);
2391                 rmem->pg_tbl = NULL;
2392         }
2393         if (rmem->vmem_size && *rmem->vmem) {
2394                 vfree(*rmem->vmem);
2395                 *rmem->vmem = NULL;
2396         }
2397 }
2398
2399 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2400 {
2401         struct pci_dev *pdev = bp->pdev;
2402         u64 valid_bit = 0;
2403         int i;
2404
2405         if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2406                 valid_bit = PTU_PTE_VALID;
2407         if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2408                 size_t pg_tbl_size = rmem->nr_pages * 8;
2409
2410                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2411                         pg_tbl_size = rmem->page_size;
2412                 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2413                                                   &rmem->pg_tbl_map,
2414                                                   GFP_KERNEL);
2415                 if (!rmem->pg_tbl)
2416                         return -ENOMEM;
2417         }
2418
2419         for (i = 0; i < rmem->nr_pages; i++) {
2420                 u64 extra_bits = valid_bit;
2421
2422                 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2423                                                      rmem->page_size,
2424                                                      &rmem->dma_arr[i],
2425                                                      GFP_KERNEL);
2426                 if (!rmem->pg_arr[i])
2427                         return -ENOMEM;
2428
2429                 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2430                         if (i == rmem->nr_pages - 2 &&
2431                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2432                                 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2433                         else if (i == rmem->nr_pages - 1 &&
2434                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2435                                 extra_bits |= PTU_PTE_LAST;
2436                         rmem->pg_tbl[i] =
2437                                 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2438                 }
2439         }
2440
2441         if (rmem->vmem_size) {
2442                 *rmem->vmem = vzalloc(rmem->vmem_size);
2443                 if (!(*rmem->vmem))
2444                         return -ENOMEM;
2445         }
2446         return 0;
2447 }
2448
2449 static void bnxt_free_rx_rings(struct bnxt *bp)
2450 {
2451         int i;
2452
2453         if (!bp->rx_ring)
2454                 return;
2455
2456         for (i = 0; i < bp->rx_nr_rings; i++) {
2457                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2458                 struct bnxt_ring_struct *ring;
2459
2460                 if (rxr->xdp_prog)
2461                         bpf_prog_put(rxr->xdp_prog);
2462
2463                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2464                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2465
2466                 kfree(rxr->rx_tpa);
2467                 rxr->rx_tpa = NULL;
2468
2469                 kfree(rxr->rx_agg_bmap);
2470                 rxr->rx_agg_bmap = NULL;
2471
2472                 ring = &rxr->rx_ring_struct;
2473                 bnxt_free_ring(bp, &ring->ring_mem);
2474
2475                 ring = &rxr->rx_agg_ring_struct;
2476                 bnxt_free_ring(bp, &ring->ring_mem);
2477         }
2478 }
2479
2480 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2481 {
2482         int i, rc, agg_rings = 0, tpa_rings = 0;
2483
2484         if (!bp->rx_ring)
2485                 return -ENOMEM;
2486
2487         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2488                 agg_rings = 1;
2489
2490         if (bp->flags & BNXT_FLAG_TPA)
2491                 tpa_rings = 1;
2492
2493         for (i = 0; i < bp->rx_nr_rings; i++) {
2494                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2495                 struct bnxt_ring_struct *ring;
2496
2497                 ring = &rxr->rx_ring_struct;
2498
2499                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2500                 if (rc < 0)
2501                         return rc;
2502
2503                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2504                 if (rc)
2505                         return rc;
2506
2507                 ring->grp_idx = i;
2508                 if (agg_rings) {
2509                         u16 mem_size;
2510
2511                         ring = &rxr->rx_agg_ring_struct;
2512                         rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2513                         if (rc)
2514                                 return rc;
2515
2516                         ring->grp_idx = i;
2517                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2518                         mem_size = rxr->rx_agg_bmap_size / 8;
2519                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2520                         if (!rxr->rx_agg_bmap)
2521                                 return -ENOMEM;
2522
2523                         if (tpa_rings) {
2524                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2525                                                 sizeof(struct bnxt_tpa_info),
2526                                                 GFP_KERNEL);
2527                                 if (!rxr->rx_tpa)
2528                                         return -ENOMEM;
2529                         }
2530                 }
2531         }
2532         return 0;
2533 }
2534
2535 static void bnxt_free_tx_rings(struct bnxt *bp)
2536 {
2537         int i;
2538         struct pci_dev *pdev = bp->pdev;
2539
2540         if (!bp->tx_ring)
2541                 return;
2542
2543         for (i = 0; i < bp->tx_nr_rings; i++) {
2544                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2545                 struct bnxt_ring_struct *ring;
2546
2547                 if (txr->tx_push) {
2548                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2549                                           txr->tx_push, txr->tx_push_mapping);
2550                         txr->tx_push = NULL;
2551                 }
2552
2553                 ring = &txr->tx_ring_struct;
2554
2555                 bnxt_free_ring(bp, &ring->ring_mem);
2556         }
2557 }
2558
2559 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2560 {
2561         int i, j, rc;
2562         struct pci_dev *pdev = bp->pdev;
2563
2564         bp->tx_push_size = 0;
2565         if (bp->tx_push_thresh) {
2566                 int push_size;
2567
2568                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2569                                         bp->tx_push_thresh);
2570
2571                 if (push_size > 256) {
2572                         push_size = 0;
2573                         bp->tx_push_thresh = 0;
2574                 }
2575
2576                 bp->tx_push_size = push_size;
2577         }
2578
2579         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2580                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2581                 struct bnxt_ring_struct *ring;
2582                 u8 qidx;
2583
2584                 ring = &txr->tx_ring_struct;
2585
2586                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2587                 if (rc)
2588                         return rc;
2589
2590                 ring->grp_idx = txr->bnapi->index;
2591                 if (bp->tx_push_size) {
2592                         dma_addr_t mapping;
2593
2594                         /* One pre-allocated DMA buffer to backup
2595                          * TX push operation
2596                          */
2597                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2598                                                 bp->tx_push_size,
2599                                                 &txr->tx_push_mapping,
2600                                                 GFP_KERNEL);
2601
2602                         if (!txr->tx_push)
2603                                 return -ENOMEM;
2604
2605                         mapping = txr->tx_push_mapping +
2606                                 sizeof(struct tx_push_bd);
2607                         txr->data_mapping = cpu_to_le64(mapping);
2608
2609                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2610                 }
2611                 qidx = bp->tc_to_qidx[j];
2612                 ring->queue_id = bp->q_info[qidx].queue_id;
2613                 if (i < bp->tx_nr_rings_xdp)
2614                         continue;
2615                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2616                         j++;
2617         }
2618         return 0;
2619 }
2620
2621 static void bnxt_free_cp_rings(struct bnxt *bp)
2622 {
2623         int i;
2624
2625         if (!bp->bnapi)
2626                 return;
2627
2628         for (i = 0; i < bp->cp_nr_rings; i++) {
2629                 struct bnxt_napi *bnapi = bp->bnapi[i];
2630                 struct bnxt_cp_ring_info *cpr;
2631                 struct bnxt_ring_struct *ring;
2632                 int j;
2633
2634                 if (!bnapi)
2635                         continue;
2636
2637                 cpr = &bnapi->cp_ring;
2638                 ring = &cpr->cp_ring_struct;
2639
2640                 bnxt_free_ring(bp, &ring->ring_mem);
2641
2642                 for (j = 0; j < 2; j++) {
2643                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2644
2645                         if (cpr2) {
2646                                 ring = &cpr2->cp_ring_struct;
2647                                 bnxt_free_ring(bp, &ring->ring_mem);
2648                                 kfree(cpr2);
2649                                 cpr->cp_ring_arr[j] = NULL;
2650                         }
2651                 }
2652         }
2653 }
2654
2655 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2656 {
2657         struct bnxt_ring_mem_info *rmem;
2658         struct bnxt_ring_struct *ring;
2659         struct bnxt_cp_ring_info *cpr;
2660         int rc;
2661
2662         cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2663         if (!cpr)
2664                 return NULL;
2665
2666         ring = &cpr->cp_ring_struct;
2667         rmem = &ring->ring_mem;
2668         rmem->nr_pages = bp->cp_nr_pages;
2669         rmem->page_size = HW_CMPD_RING_SIZE;
2670         rmem->pg_arr = (void **)cpr->cp_desc_ring;
2671         rmem->dma_arr = cpr->cp_desc_mapping;
2672         rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2673         rc = bnxt_alloc_ring(bp, rmem);
2674         if (rc) {
2675                 bnxt_free_ring(bp, rmem);
2676                 kfree(cpr);
2677                 cpr = NULL;
2678         }
2679         return cpr;
2680 }
2681
2682 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2683 {
2684         bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2685         int i, rc, ulp_base_vec, ulp_msix;
2686
2687         ulp_msix = bnxt_get_ulp_msix_num(bp);
2688         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2689         for (i = 0; i < bp->cp_nr_rings; i++) {
2690                 struct bnxt_napi *bnapi = bp->bnapi[i];
2691                 struct bnxt_cp_ring_info *cpr;
2692                 struct bnxt_ring_struct *ring;
2693
2694                 if (!bnapi)
2695                         continue;
2696
2697                 cpr = &bnapi->cp_ring;
2698                 cpr->bnapi = bnapi;
2699                 ring = &cpr->cp_ring_struct;
2700
2701                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2702                 if (rc)
2703                         return rc;
2704
2705                 if (ulp_msix && i >= ulp_base_vec)
2706                         ring->map_idx = i + ulp_msix;
2707                 else
2708                         ring->map_idx = i;
2709
2710                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2711                         continue;
2712
2713                 if (i < bp->rx_nr_rings) {
2714                         struct bnxt_cp_ring_info *cpr2 =
2715                                 bnxt_alloc_cp_sub_ring(bp);
2716
2717                         cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2718                         if (!cpr2)
2719                                 return -ENOMEM;
2720                         cpr2->bnapi = bnapi;
2721                 }
2722                 if ((sh && i < bp->tx_nr_rings) ||
2723                     (!sh && i >= bp->rx_nr_rings)) {
2724                         struct bnxt_cp_ring_info *cpr2 =
2725                                 bnxt_alloc_cp_sub_ring(bp);
2726
2727                         cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2728                         if (!cpr2)
2729                                 return -ENOMEM;
2730                         cpr2->bnapi = bnapi;
2731                 }
2732         }
2733         return 0;
2734 }
2735
2736 static void bnxt_init_ring_struct(struct bnxt *bp)
2737 {
2738         int i;
2739
2740         for (i = 0; i < bp->cp_nr_rings; i++) {
2741                 struct bnxt_napi *bnapi = bp->bnapi[i];
2742                 struct bnxt_ring_mem_info *rmem;
2743                 struct bnxt_cp_ring_info *cpr;
2744                 struct bnxt_rx_ring_info *rxr;
2745                 struct bnxt_tx_ring_info *txr;
2746                 struct bnxt_ring_struct *ring;
2747
2748                 if (!bnapi)
2749                         continue;
2750
2751                 cpr = &bnapi->cp_ring;
2752                 ring = &cpr->cp_ring_struct;
2753                 rmem = &ring->ring_mem;
2754                 rmem->nr_pages = bp->cp_nr_pages;
2755                 rmem->page_size = HW_CMPD_RING_SIZE;
2756                 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2757                 rmem->dma_arr = cpr->cp_desc_mapping;
2758                 rmem->vmem_size = 0;
2759
2760                 rxr = bnapi->rx_ring;
2761                 if (!rxr)
2762                         goto skip_rx;
2763
2764                 ring = &rxr->rx_ring_struct;
2765                 rmem = &ring->ring_mem;
2766                 rmem->nr_pages = bp->rx_nr_pages;
2767                 rmem->page_size = HW_RXBD_RING_SIZE;
2768                 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2769                 rmem->dma_arr = rxr->rx_desc_mapping;
2770                 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2771                 rmem->vmem = (void **)&rxr->rx_buf_ring;
2772
2773                 ring = &rxr->rx_agg_ring_struct;
2774                 rmem = &ring->ring_mem;
2775                 rmem->nr_pages = bp->rx_agg_nr_pages;
2776                 rmem->page_size = HW_RXBD_RING_SIZE;
2777                 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2778                 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2779                 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2780                 rmem->vmem = (void **)&rxr->rx_agg_ring;
2781
2782 skip_rx:
2783                 txr = bnapi->tx_ring;
2784                 if (!txr)
2785                         continue;
2786
2787                 ring = &txr->tx_ring_struct;
2788                 rmem = &ring->ring_mem;
2789                 rmem->nr_pages = bp->tx_nr_pages;
2790                 rmem->page_size = HW_RXBD_RING_SIZE;
2791                 rmem->pg_arr = (void **)txr->tx_desc_ring;
2792                 rmem->dma_arr = txr->tx_desc_mapping;
2793                 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2794                 rmem->vmem = (void **)&txr->tx_buf_ring;
2795         }
2796 }
2797
2798 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2799 {
2800         int i;
2801         u32 prod;
2802         struct rx_bd **rx_buf_ring;
2803
2804         rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2805         for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2806                 int j;
2807                 struct rx_bd *rxbd;
2808
2809                 rxbd = rx_buf_ring[i];
2810                 if (!rxbd)
2811                         continue;
2812
2813                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2814                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2815                         rxbd->rx_bd_opaque = prod;
2816                 }
2817         }
2818 }
2819
2820 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2821 {
2822         struct net_device *dev = bp->dev;
2823         struct bnxt_rx_ring_info *rxr;
2824         struct bnxt_ring_struct *ring;
2825         u32 prod, type;
2826         int i;
2827
2828         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2829                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2830
2831         if (NET_IP_ALIGN == 2)
2832                 type |= RX_BD_FLAGS_SOP;
2833
2834         rxr = &bp->rx_ring[ring_nr];
2835         ring = &rxr->rx_ring_struct;
2836         bnxt_init_rxbd_pages(ring, type);
2837
2838         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2839                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2840                 if (IS_ERR(rxr->xdp_prog)) {
2841                         int rc = PTR_ERR(rxr->xdp_prog);
2842
2843                         rxr->xdp_prog = NULL;
2844                         return rc;
2845                 }
2846         }
2847         prod = rxr->rx_prod;
2848         for (i = 0; i < bp->rx_ring_size; i++) {
2849                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2850                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2851                                     ring_nr, i, bp->rx_ring_size);
2852                         break;
2853                 }
2854                 prod = NEXT_RX(prod);
2855         }
2856         rxr->rx_prod = prod;
2857         ring->fw_ring_id = INVALID_HW_RING_ID;
2858
2859         ring = &rxr->rx_agg_ring_struct;
2860         ring->fw_ring_id = INVALID_HW_RING_ID;
2861
2862         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2863                 return 0;
2864
2865         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2866                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2867
2868         bnxt_init_rxbd_pages(ring, type);
2869
2870         prod = rxr->rx_agg_prod;
2871         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2872                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2873                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2874                                     ring_nr, i, bp->rx_ring_size);
2875                         break;
2876                 }
2877                 prod = NEXT_RX_AGG(prod);
2878         }
2879         rxr->rx_agg_prod = prod;
2880
2881         if (bp->flags & BNXT_FLAG_TPA) {
2882                 if (rxr->rx_tpa) {
2883                         u8 *data;
2884                         dma_addr_t mapping;
2885
2886                         for (i = 0; i < MAX_TPA; i++) {
2887                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2888                                                             GFP_KERNEL);
2889                                 if (!data)
2890                                         return -ENOMEM;
2891
2892                                 rxr->rx_tpa[i].data = data;
2893                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2894                                 rxr->rx_tpa[i].mapping = mapping;
2895                         }
2896                 } else {
2897                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2898                         return -ENOMEM;
2899                 }
2900         }
2901
2902         return 0;
2903 }
2904
2905 static void bnxt_init_cp_rings(struct bnxt *bp)
2906 {
2907         int i, j;
2908
2909         for (i = 0; i < bp->cp_nr_rings; i++) {
2910                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2911                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2912
2913                 ring->fw_ring_id = INVALID_HW_RING_ID;
2914                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2915                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2916                 for (j = 0; j < 2; j++) {
2917                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2918
2919                         if (!cpr2)
2920                                 continue;
2921
2922                         ring = &cpr2->cp_ring_struct;
2923                         ring->fw_ring_id = INVALID_HW_RING_ID;
2924                         cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2925                         cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2926                 }
2927         }
2928 }
2929
2930 static int bnxt_init_rx_rings(struct bnxt *bp)
2931 {
2932         int i, rc = 0;
2933
2934         if (BNXT_RX_PAGE_MODE(bp)) {
2935                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2936                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2937         } else {
2938                 bp->rx_offset = BNXT_RX_OFFSET;
2939                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2940         }
2941
2942         for (i = 0; i < bp->rx_nr_rings; i++) {
2943                 rc = bnxt_init_one_rx_ring(bp, i);
2944                 if (rc)
2945                         break;
2946         }
2947
2948         return rc;
2949 }
2950
2951 static int bnxt_init_tx_rings(struct bnxt *bp)
2952 {
2953         u16 i;
2954
2955         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2956                                    MAX_SKB_FRAGS + 1);
2957
2958         for (i = 0; i < bp->tx_nr_rings; i++) {
2959                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2960                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2961
2962                 ring->fw_ring_id = INVALID_HW_RING_ID;
2963         }
2964
2965         return 0;
2966 }
2967
2968 static void bnxt_free_ring_grps(struct bnxt *bp)
2969 {
2970         kfree(bp->grp_info);
2971         bp->grp_info = NULL;
2972 }
2973
2974 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2975 {
2976         int i;
2977
2978         if (irq_re_init) {
2979                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2980                                        sizeof(struct bnxt_ring_grp_info),
2981                                        GFP_KERNEL);
2982                 if (!bp->grp_info)
2983                         return -ENOMEM;
2984         }
2985         for (i = 0; i < bp->cp_nr_rings; i++) {
2986                 if (irq_re_init)
2987                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2988                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2989                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2990                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2991                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2992         }
2993         return 0;
2994 }
2995
2996 static void bnxt_free_vnics(struct bnxt *bp)
2997 {
2998         kfree(bp->vnic_info);
2999         bp->vnic_info = NULL;
3000         bp->nr_vnics = 0;
3001 }
3002
3003 static int bnxt_alloc_vnics(struct bnxt *bp)
3004 {
3005         int num_vnics = 1;
3006
3007 #ifdef CONFIG_RFS_ACCEL
3008         if (bp->flags & BNXT_FLAG_RFS)
3009                 num_vnics += bp->rx_nr_rings;
3010 #endif
3011
3012         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3013                 num_vnics++;
3014
3015         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3016                                 GFP_KERNEL);
3017         if (!bp->vnic_info)
3018                 return -ENOMEM;
3019
3020         bp->nr_vnics = num_vnics;
3021         return 0;
3022 }
3023
3024 static void bnxt_init_vnics(struct bnxt *bp)
3025 {
3026         int i;
3027
3028         for (i = 0; i < bp->nr_vnics; i++) {
3029                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3030                 int j;
3031
3032                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3033                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3034                         vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3035
3036                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3037
3038                 if (bp->vnic_info[i].rss_hash_key) {
3039                         if (i == 0)
3040                                 prandom_bytes(vnic->rss_hash_key,
3041                                               HW_HASH_KEY_SIZE);
3042                         else
3043                                 memcpy(vnic->rss_hash_key,
3044                                        bp->vnic_info[0].rss_hash_key,
3045                                        HW_HASH_KEY_SIZE);
3046                 }
3047         }
3048 }
3049
3050 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3051 {
3052         int pages;
3053
3054         pages = ring_size / desc_per_pg;
3055
3056         if (!pages)
3057                 return 1;
3058
3059         pages++;
3060
3061         while (pages & (pages - 1))
3062                 pages++;
3063
3064         return pages;
3065 }
3066
3067 void bnxt_set_tpa_flags(struct bnxt *bp)
3068 {
3069         bp->flags &= ~BNXT_FLAG_TPA;
3070         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3071                 return;
3072         if (bp->dev->features & NETIF_F_LRO)
3073                 bp->flags |= BNXT_FLAG_LRO;
3074         else if (bp->dev->features & NETIF_F_GRO_HW)
3075                 bp->flags |= BNXT_FLAG_GRO;
3076 }
3077
3078 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3079  * be set on entry.
3080  */
3081 void bnxt_set_ring_params(struct bnxt *bp)
3082 {
3083         u32 ring_size, rx_size, rx_space;
3084         u32 agg_factor = 0, agg_ring_size = 0;
3085
3086         /* 8 for CRC and VLAN */
3087         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3088
3089         rx_space = rx_size + NET_SKB_PAD +
3090                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3091
3092         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3093         ring_size = bp->rx_ring_size;
3094         bp->rx_agg_ring_size = 0;
3095         bp->rx_agg_nr_pages = 0;
3096
3097         if (bp->flags & BNXT_FLAG_TPA)
3098                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3099
3100         bp->flags &= ~BNXT_FLAG_JUMBO;
3101         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3102                 u32 jumbo_factor;
3103
3104                 bp->flags |= BNXT_FLAG_JUMBO;
3105                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3106                 if (jumbo_factor > agg_factor)
3107                         agg_factor = jumbo_factor;
3108         }
3109         agg_ring_size = ring_size * agg_factor;
3110
3111         if (agg_ring_size) {
3112                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3113                                                         RX_DESC_CNT);
3114                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3115                         u32 tmp = agg_ring_size;
3116
3117                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3118                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3119                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3120                                     tmp, agg_ring_size);
3121                 }
3122                 bp->rx_agg_ring_size = agg_ring_size;
3123                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3124                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3125                 rx_space = rx_size + NET_SKB_PAD +
3126                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3127         }
3128
3129         bp->rx_buf_use_size = rx_size;
3130         bp->rx_buf_size = rx_space;
3131
3132         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3133         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3134
3135         ring_size = bp->tx_ring_size;
3136         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3137         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3138
3139         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3140         bp->cp_ring_size = ring_size;
3141
3142         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3143         if (bp->cp_nr_pages > MAX_CP_PAGES) {
3144                 bp->cp_nr_pages = MAX_CP_PAGES;
3145                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3146                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3147                             ring_size, bp->cp_ring_size);
3148         }
3149         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3150         bp->cp_ring_mask = bp->cp_bit - 1;
3151 }
3152
3153 /* Changing allocation mode of RX rings.
3154  * TODO: Update when extending xdp_rxq_info to support allocation modes.
3155  */
3156 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3157 {
3158         if (page_mode) {
3159                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3160                         return -EOPNOTSUPP;
3161                 bp->dev->max_mtu =
3162                         min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3163                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3164                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3165                 bp->rx_dir = DMA_BIDIRECTIONAL;
3166                 bp->rx_skb_func = bnxt_rx_page_skb;
3167                 /* Disable LRO or GRO_HW */
3168                 netdev_update_features(bp->dev);
3169         } else {
3170                 bp->dev->max_mtu = bp->max_mtu;
3171                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3172                 bp->rx_dir = DMA_FROM_DEVICE;
3173                 bp->rx_skb_func = bnxt_rx_skb;
3174         }
3175         return 0;
3176 }
3177
3178 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3179 {
3180         int i;
3181         struct bnxt_vnic_info *vnic;
3182         struct pci_dev *pdev = bp->pdev;
3183
3184         if (!bp->vnic_info)
3185                 return;
3186
3187         for (i = 0; i < bp->nr_vnics; i++) {
3188                 vnic = &bp->vnic_info[i];
3189
3190                 kfree(vnic->fw_grp_ids);
3191                 vnic->fw_grp_ids = NULL;
3192
3193                 kfree(vnic->uc_list);
3194                 vnic->uc_list = NULL;
3195
3196                 if (vnic->mc_list) {
3197                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3198                                           vnic->mc_list, vnic->mc_list_mapping);
3199                         vnic->mc_list = NULL;
3200                 }
3201
3202                 if (vnic->rss_table) {
3203                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
3204                                           vnic->rss_table,
3205                                           vnic->rss_table_dma_addr);
3206                         vnic->rss_table = NULL;
3207                 }
3208
3209                 vnic->rss_hash_key = NULL;
3210                 vnic->flags = 0;
3211         }
3212 }
3213
3214 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3215 {
3216         int i, rc = 0, size;
3217         struct bnxt_vnic_info *vnic;
3218         struct pci_dev *pdev = bp->pdev;
3219         int max_rings;
3220
3221         for (i = 0; i < bp->nr_vnics; i++) {
3222                 vnic = &bp->vnic_info[i];
3223
3224                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3225                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3226
3227                         if (mem_size > 0) {
3228                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3229                                 if (!vnic->uc_list) {
3230                                         rc = -ENOMEM;
3231                                         goto out;
3232                                 }
3233                         }
3234                 }
3235
3236                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3237                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3238                         vnic->mc_list =
3239                                 dma_alloc_coherent(&pdev->dev,
3240                                                    vnic->mc_list_size,
3241                                                    &vnic->mc_list_mapping,
3242                                                    GFP_KERNEL);
3243                         if (!vnic->mc_list) {
3244                                 rc = -ENOMEM;
3245                                 goto out;
3246                         }
3247                 }
3248
3249                 if (bp->flags & BNXT_FLAG_CHIP_P5)
3250                         goto vnic_skip_grps;
3251
3252                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3253                         max_rings = bp->rx_nr_rings;
3254                 else
3255                         max_rings = 1;
3256
3257                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3258                 if (!vnic->fw_grp_ids) {
3259                         rc = -ENOMEM;
3260                         goto out;
3261                 }
3262 vnic_skip_grps:
3263                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3264                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3265                         continue;
3266
3267                 /* Allocate rss table and hash key */
3268                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3269                                                      &vnic->rss_table_dma_addr,
3270                                                      GFP_KERNEL);
3271                 if (!vnic->rss_table) {
3272                         rc = -ENOMEM;
3273                         goto out;
3274                 }
3275
3276                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3277
3278                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3279                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3280         }
3281         return 0;
3282
3283 out:
3284         return rc;
3285 }
3286
3287 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3288 {
3289         struct pci_dev *pdev = bp->pdev;
3290
3291         if (bp->hwrm_cmd_resp_addr) {
3292                 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3293                                   bp->hwrm_cmd_resp_dma_addr);
3294                 bp->hwrm_cmd_resp_addr = NULL;
3295         }
3296
3297         if (bp->hwrm_cmd_kong_resp_addr) {
3298                 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3299                                   bp->hwrm_cmd_kong_resp_addr,
3300                                   bp->hwrm_cmd_kong_resp_dma_addr);
3301                 bp->hwrm_cmd_kong_resp_addr = NULL;
3302         }
3303 }
3304
3305 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3306 {
3307         struct pci_dev *pdev = bp->pdev;
3308
3309         bp->hwrm_cmd_kong_resp_addr =
3310                 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3311                                    &bp->hwrm_cmd_kong_resp_dma_addr,
3312                                    GFP_KERNEL);
3313         if (!bp->hwrm_cmd_kong_resp_addr)
3314                 return -ENOMEM;
3315
3316         return 0;
3317 }
3318
3319 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3320 {
3321         struct pci_dev *pdev = bp->pdev;
3322
3323         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3324                                                    &bp->hwrm_cmd_resp_dma_addr,
3325                                                    GFP_KERNEL);
3326         if (!bp->hwrm_cmd_resp_addr)
3327                 return -ENOMEM;
3328
3329         return 0;
3330 }
3331
3332 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3333 {
3334         if (bp->hwrm_short_cmd_req_addr) {
3335                 struct pci_dev *pdev = bp->pdev;
3336
3337                 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3338                                   bp->hwrm_short_cmd_req_addr,
3339                                   bp->hwrm_short_cmd_req_dma_addr);
3340                 bp->hwrm_short_cmd_req_addr = NULL;
3341         }
3342 }
3343
3344 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3345 {
3346         struct pci_dev *pdev = bp->pdev;
3347
3348         bp->hwrm_short_cmd_req_addr =
3349                 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3350                                    &bp->hwrm_short_cmd_req_dma_addr,
3351                                    GFP_KERNEL);
3352         if (!bp->hwrm_short_cmd_req_addr)
3353                 return -ENOMEM;
3354
3355         return 0;
3356 }
3357
3358 static void bnxt_free_port_stats(struct bnxt *bp)
3359 {
3360         struct pci_dev *pdev = bp->pdev;
3361
3362         bp->flags &= ~BNXT_FLAG_PORT_STATS;
3363         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3364
3365         if (bp->hw_rx_port_stats) {
3366                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3367                                   bp->hw_rx_port_stats,
3368                                   bp->hw_rx_port_stats_map);
3369                 bp->hw_rx_port_stats = NULL;
3370         }
3371
3372         if (bp->hw_tx_port_stats_ext) {
3373                 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3374                                   bp->hw_tx_port_stats_ext,
3375                                   bp->hw_tx_port_stats_ext_map);
3376                 bp->hw_tx_port_stats_ext = NULL;
3377         }
3378
3379         if (bp->hw_rx_port_stats_ext) {
3380                 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3381                                   bp->hw_rx_port_stats_ext,
3382                                   bp->hw_rx_port_stats_ext_map);
3383                 bp->hw_rx_port_stats_ext = NULL;
3384         }
3385 }
3386
3387 static void bnxt_free_ring_stats(struct bnxt *bp)
3388 {
3389         struct pci_dev *pdev = bp->pdev;
3390         int size, i;
3391
3392         if (!bp->bnapi)
3393                 return;
3394
3395         size = sizeof(struct ctx_hw_stats);
3396
3397         for (i = 0; i < bp->cp_nr_rings; i++) {
3398                 struct bnxt_napi *bnapi = bp->bnapi[i];
3399                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3400
3401                 if (cpr->hw_stats) {
3402                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3403                                           cpr->hw_stats_map);
3404                         cpr->hw_stats = NULL;
3405                 }
3406         }
3407 }
3408
3409 static int bnxt_alloc_stats(struct bnxt *bp)
3410 {
3411         u32 size, i;
3412         struct pci_dev *pdev = bp->pdev;
3413
3414         size = sizeof(struct ctx_hw_stats);
3415
3416         for (i = 0; i < bp->cp_nr_rings; i++) {
3417                 struct bnxt_napi *bnapi = bp->bnapi[i];
3418                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3419
3420                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3421                                                    &cpr->hw_stats_map,
3422                                                    GFP_KERNEL);
3423                 if (!cpr->hw_stats)
3424                         return -ENOMEM;
3425
3426                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3427         }
3428
3429         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3430                 if (bp->hw_rx_port_stats)
3431                         goto alloc_ext_stats;
3432
3433                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3434                                          sizeof(struct tx_port_stats) + 1024;
3435
3436                 bp->hw_rx_port_stats =
3437                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3438                                            &bp->hw_rx_port_stats_map,
3439                                            GFP_KERNEL);
3440                 if (!bp->hw_rx_port_stats)
3441                         return -ENOMEM;
3442
3443                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3444                                        512;
3445                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3446                                            sizeof(struct rx_port_stats) + 512;
3447                 bp->flags |= BNXT_FLAG_PORT_STATS;
3448
3449 alloc_ext_stats:
3450                 /* Display extended statistics only if FW supports it */
3451                 if (bp->hwrm_spec_code < 0x10804 ||
3452                     bp->hwrm_spec_code == 0x10900)
3453                         return 0;
3454
3455                 if (bp->hw_rx_port_stats_ext)
3456                         goto alloc_tx_ext_stats;
3457
3458                 bp->hw_rx_port_stats_ext =
3459                         dma_alloc_coherent(&pdev->dev,
3460                                            sizeof(struct rx_port_stats_ext),
3461                                            &bp->hw_rx_port_stats_ext_map,
3462                                            GFP_KERNEL);
3463                 if (!bp->hw_rx_port_stats_ext)
3464                         return 0;
3465
3466 alloc_tx_ext_stats:
3467                 if (bp->hw_tx_port_stats_ext)
3468                         return 0;
3469
3470                 if (bp->hwrm_spec_code >= 0x10902) {
3471                         bp->hw_tx_port_stats_ext =
3472                                 dma_alloc_coherent(&pdev->dev,
3473                                                    sizeof(struct tx_port_stats_ext),
3474                                                    &bp->hw_tx_port_stats_ext_map,
3475                                                    GFP_KERNEL);
3476                 }
3477                 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3478         }
3479         return 0;
3480 }
3481
3482 static void bnxt_clear_ring_indices(struct bnxt *bp)
3483 {
3484         int i;
3485
3486         if (!bp->bnapi)
3487                 return;
3488
3489         for (i = 0; i < bp->cp_nr_rings; i++) {
3490                 struct bnxt_napi *bnapi = bp->bnapi[i];
3491                 struct bnxt_cp_ring_info *cpr;
3492                 struct bnxt_rx_ring_info *rxr;
3493                 struct bnxt_tx_ring_info *txr;
3494
3495                 if (!bnapi)
3496                         continue;
3497
3498                 cpr = &bnapi->cp_ring;
3499                 cpr->cp_raw_cons = 0;
3500
3501                 txr = bnapi->tx_ring;
3502                 if (txr) {
3503                         txr->tx_prod = 0;
3504                         txr->tx_cons = 0;
3505                 }
3506
3507                 rxr = bnapi->rx_ring;
3508                 if (rxr) {
3509                         rxr->rx_prod = 0;
3510                         rxr->rx_agg_prod = 0;
3511                         rxr->rx_sw_agg_prod = 0;
3512                         rxr->rx_next_cons = 0;
3513                 }
3514         }
3515 }
3516
3517 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3518 {
3519 #ifdef CONFIG_RFS_ACCEL
3520         int i;
3521
3522         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3523          * safe to delete the hash table.
3524          */
3525         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3526                 struct hlist_head *head;
3527                 struct hlist_node *tmp;
3528                 struct bnxt_ntuple_filter *fltr;
3529
3530                 head = &bp->ntp_fltr_hash_tbl[i];
3531                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3532                         hlist_del(&fltr->hash);
3533                         kfree(fltr);
3534                 }
3535         }
3536         if (irq_reinit) {
3537                 kfree(bp->ntp_fltr_bmap);
3538                 bp->ntp_fltr_bmap = NULL;
3539         }
3540         bp->ntp_fltr_count = 0;
3541 #endif
3542 }
3543
3544 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3545 {
3546 #ifdef CONFIG_RFS_ACCEL
3547         int i, rc = 0;
3548
3549         if (!(bp->flags & BNXT_FLAG_RFS))
3550                 return 0;
3551
3552         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3553                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3554
3555         bp->ntp_fltr_count = 0;
3556         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3557                                     sizeof(long),
3558                                     GFP_KERNEL);
3559
3560         if (!bp->ntp_fltr_bmap)
3561                 rc = -ENOMEM;
3562
3563         return rc;
3564 #else
3565         return 0;
3566 #endif
3567 }
3568
3569 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3570 {
3571         bnxt_free_vnic_attributes(bp);
3572         bnxt_free_tx_rings(bp);
3573         bnxt_free_rx_rings(bp);
3574         bnxt_free_cp_rings(bp);
3575         bnxt_free_ntp_fltrs(bp, irq_re_init);
3576         if (irq_re_init) {
3577                 bnxt_free_ring_stats(bp);
3578                 bnxt_free_ring_grps(bp);
3579                 bnxt_free_vnics(bp);
3580                 kfree(bp->tx_ring_map);
3581                 bp->tx_ring_map = NULL;
3582                 kfree(bp->tx_ring);
3583                 bp->tx_ring = NULL;
3584                 kfree(bp->rx_ring);
3585                 bp->rx_ring = NULL;
3586                 kfree(bp->bnapi);
3587                 bp->bnapi = NULL;
3588         } else {
3589                 bnxt_clear_ring_indices(bp);
3590         }
3591 }
3592
3593 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3594 {
3595         int i, j, rc, size, arr_size;
3596         void *bnapi;
3597
3598         if (irq_re_init) {
3599                 /* Allocate bnapi mem pointer array and mem block for
3600                  * all queues
3601                  */
3602                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3603                                 bp->cp_nr_rings);
3604                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3605                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3606                 if (!bnapi)
3607                         return -ENOMEM;
3608
3609                 bp->bnapi = bnapi;
3610                 bnapi += arr_size;
3611                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3612                         bp->bnapi[i] = bnapi;
3613                         bp->bnapi[i]->index = i;
3614                         bp->bnapi[i]->bp = bp;
3615                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3616                                 struct bnxt_cp_ring_info *cpr =
3617                                         &bp->bnapi[i]->cp_ring;
3618
3619                                 cpr->cp_ring_struct.ring_mem.flags =
3620                                         BNXT_RMEM_RING_PTE_FLAG;
3621                         }
3622                 }
3623
3624                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3625                                       sizeof(struct bnxt_rx_ring_info),
3626                                       GFP_KERNEL);
3627                 if (!bp->rx_ring)
3628                         return -ENOMEM;
3629
3630                 for (i = 0; i < bp->rx_nr_rings; i++) {
3631                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3632
3633                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3634                                 rxr->rx_ring_struct.ring_mem.flags =
3635                                         BNXT_RMEM_RING_PTE_FLAG;
3636                                 rxr->rx_agg_ring_struct.ring_mem.flags =
3637                                         BNXT_RMEM_RING_PTE_FLAG;
3638                         }
3639                         rxr->bnapi = bp->bnapi[i];
3640                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3641                 }
3642
3643                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3644                                       sizeof(struct bnxt_tx_ring_info),
3645                                       GFP_KERNEL);
3646                 if (!bp->tx_ring)
3647                         return -ENOMEM;
3648
3649                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3650                                           GFP_KERNEL);
3651
3652                 if (!bp->tx_ring_map)
3653                         return -ENOMEM;
3654
3655                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3656                         j = 0;
3657                 else
3658                         j = bp->rx_nr_rings;
3659
3660                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3661                         struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3662
3663                         if (bp->flags & BNXT_FLAG_CHIP_P5)
3664                                 txr->tx_ring_struct.ring_mem.flags =
3665                                         BNXT_RMEM_RING_PTE_FLAG;
3666                         txr->bnapi = bp->bnapi[j];
3667                         bp->bnapi[j]->tx_ring = txr;
3668                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3669                         if (i >= bp->tx_nr_rings_xdp) {
3670                                 txr->txq_index = i - bp->tx_nr_rings_xdp;
3671                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3672                         } else {
3673                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3674                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3675                         }
3676                 }
3677
3678                 rc = bnxt_alloc_stats(bp);
3679                 if (rc)
3680                         goto alloc_mem_err;
3681
3682                 rc = bnxt_alloc_ntp_fltrs(bp);
3683                 if (rc)
3684                         goto alloc_mem_err;
3685
3686                 rc = bnxt_alloc_vnics(bp);
3687                 if (rc)
3688                         goto alloc_mem_err;
3689         }
3690
3691         bnxt_init_ring_struct(bp);
3692
3693         rc = bnxt_alloc_rx_rings(bp);
3694         if (rc)
3695                 goto alloc_mem_err;
3696
3697         rc = bnxt_alloc_tx_rings(bp);
3698         if (rc)
3699                 goto alloc_mem_err;
3700
3701         rc = bnxt_alloc_cp_rings(bp);
3702         if (rc)
3703                 goto alloc_mem_err;
3704
3705         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3706                                   BNXT_VNIC_UCAST_FLAG;
3707         rc = bnxt_alloc_vnic_attributes(bp);
3708         if (rc)
3709                 goto alloc_mem_err;
3710         return 0;
3711
3712 alloc_mem_err:
3713         bnxt_free_mem(bp, true);
3714         return rc;
3715 }
3716
3717 static void bnxt_disable_int(struct bnxt *bp)
3718 {
3719         int i;
3720
3721         if (!bp->bnapi)
3722                 return;
3723
3724         for (i = 0; i < bp->cp_nr_rings; i++) {
3725                 struct bnxt_napi *bnapi = bp->bnapi[i];
3726                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3727                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3728
3729                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3730                         bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3731         }
3732 }
3733
3734 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3735 {
3736         struct bnxt_napi *bnapi = bp->bnapi[n];
3737         struct bnxt_cp_ring_info *cpr;
3738
3739         cpr = &bnapi->cp_ring;
3740         return cpr->cp_ring_struct.map_idx;
3741 }
3742
3743 static void bnxt_disable_int_sync(struct bnxt *bp)
3744 {
3745         int i;
3746
3747         atomic_inc(&bp->intr_sem);
3748
3749         bnxt_disable_int(bp);
3750         for (i = 0; i < bp->cp_nr_rings; i++) {
3751                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3752
3753                 synchronize_irq(bp->irq_tbl[map_idx].vector);
3754         }
3755 }
3756
3757 static void bnxt_enable_int(struct bnxt *bp)
3758 {
3759         int i;
3760
3761         atomic_set(&bp->intr_sem, 0);
3762         for (i = 0; i < bp->cp_nr_rings; i++) {
3763                 struct bnxt_napi *bnapi = bp->bnapi[i];
3764                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3765
3766                 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3767         }
3768 }
3769
3770 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3771                             u16 cmpl_ring, u16 target_id)
3772 {
3773         struct input *req = request;
3774
3775         req->req_type = cpu_to_le16(req_type);
3776         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3777         req->target_id = cpu_to_le16(target_id);
3778         if (bnxt_kong_hwrm_message(bp, req))
3779                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3780         else
3781                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3782 }
3783
3784 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3785                                  int timeout, bool silent)
3786 {
3787         int i, intr_process, rc, tmo_count;
3788         struct input *req = msg;
3789         u32 *data = msg;
3790         __le32 *resp_len;
3791         u8 *valid;
3792         u16 cp_ring_id, len = 0;
3793         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3794         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3795         struct hwrm_short_input short_input = {0};
3796         u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3797         u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3798         u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3799         u16 dst = BNXT_HWRM_CHNL_CHIMP;
3800
3801         if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3802                 if (msg_len > bp->hwrm_max_ext_req_len ||
3803                     !bp->hwrm_short_cmd_req_addr)
3804                         return -EINVAL;
3805         }
3806
3807         if (bnxt_hwrm_kong_chnl(bp, req)) {
3808                 dst = BNXT_HWRM_CHNL_KONG;
3809                 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3810                 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3811                 resp = bp->hwrm_cmd_kong_resp_addr;
3812                 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3813         }
3814
3815         memset(resp, 0, PAGE_SIZE);
3816         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3817         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3818
3819         req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3820         /* currently supports only one outstanding message */
3821         if (intr_process)
3822                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3823
3824         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3825             msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3826                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3827                 u16 max_msg_len;
3828
3829                 /* Set boundary for maximum extended request length for short
3830                  * cmd format. If passed up from device use the max supported
3831                  * internal req length.
3832                  */
3833                 max_msg_len = bp->hwrm_max_ext_req_len;
3834
3835                 memcpy(short_cmd_req, req, msg_len);
3836                 if (msg_len < max_msg_len)
3837                         memset(short_cmd_req + msg_len, 0,
3838                                max_msg_len - msg_len);
3839
3840                 short_input.req_type = req->req_type;
3841                 short_input.signature =
3842                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3843                 short_input.size = cpu_to_le16(msg_len);
3844                 short_input.req_addr =
3845                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3846
3847                 data = (u32 *)&short_input;
3848                 msg_len = sizeof(short_input);
3849
3850                 /* Sync memory write before updating doorbell */
3851                 wmb();
3852
3853                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3854         }
3855
3856         /* Write request msg to hwrm channel */
3857         __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3858
3859         for (i = msg_len; i < max_req_len; i += 4)
3860                 writel(0, bp->bar0 + bar_offset + i);
3861
3862         /* Ring channel doorbell */
3863         writel(1, bp->bar0 + doorbell_offset);
3864
3865         if (!timeout)
3866                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3867         /* convert timeout to usec */
3868         timeout *= 1000;
3869
3870         i = 0;
3871         /* Short timeout for the first few iterations:
3872          * number of loops = number of loops for short timeout +
3873          * number of loops for standard timeout.
3874          */
3875         tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3876         timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3877         tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3878         resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3879
3880         if (intr_process) {
3881                 u16 seq_id = bp->hwrm_intr_seq_id;
3882
3883                 /* Wait until hwrm response cmpl interrupt is processed */
3884                 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3885                        i++ < tmo_count) {
3886                         /* on first few passes, just barely sleep */
3887                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3888                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3889                                              HWRM_SHORT_MAX_TIMEOUT);
3890                         else
3891                                 usleep_range(HWRM_MIN_TIMEOUT,
3892                                              HWRM_MAX_TIMEOUT);
3893                 }
3894
3895                 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3896                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3897                                    le16_to_cpu(req->req_type));
3898                         return -1;
3899                 }
3900                 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3901                       HWRM_RESP_LEN_SFT;
3902                 valid = resp_addr + len - 1;
3903         } else {
3904                 int j;
3905
3906                 /* Check if response len is updated */
3907                 for (i = 0; i < tmo_count; i++) {
3908                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3909                               HWRM_RESP_LEN_SFT;
3910                         if (len)
3911                                 break;
3912                         /* on first few passes, just barely sleep */
3913                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3914                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3915                                              HWRM_SHORT_MAX_TIMEOUT);
3916                         else
3917                                 usleep_range(HWRM_MIN_TIMEOUT,
3918                                              HWRM_MAX_TIMEOUT);
3919                 }
3920
3921                 if (i >= tmo_count) {
3922                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3923                                    HWRM_TOTAL_TIMEOUT(i),
3924                                    le16_to_cpu(req->req_type),
3925                                    le16_to_cpu(req->seq_id), len);
3926                         return -1;
3927                 }
3928
3929                 /* Last byte of resp contains valid bit */
3930                 valid = resp_addr + len - 1;
3931                 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3932                         /* make sure we read from updated DMA memory */
3933                         dma_rmb();
3934                         if (*valid)
3935                                 break;
3936                         usleep_range(1, 5);
3937                 }
3938
3939                 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3940                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3941                                    HWRM_TOTAL_TIMEOUT(i),
3942                                    le16_to_cpu(req->req_type),
3943                                    le16_to_cpu(req->seq_id), len, *valid);
3944                         return -1;
3945                 }
3946         }
3947
3948         /* Zero valid bit for compatibility.  Valid bit in an older spec
3949          * may become a new field in a newer spec.  We must make sure that
3950          * a new field not implemented by old spec will read zero.
3951          */
3952         *valid = 0;
3953         rc = le16_to_cpu(resp->error_code);
3954         if (rc && !silent)
3955                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3956                            le16_to_cpu(resp->req_type),
3957                            le16_to_cpu(resp->seq_id), rc);
3958         return rc;
3959 }
3960
3961 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3962 {
3963         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3964 }
3965
3966 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3967                               int timeout)
3968 {
3969         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3970 }
3971
3972 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3973 {
3974         int rc;
3975
3976         mutex_lock(&bp->hwrm_cmd_lock);
3977         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3978         mutex_unlock(&bp->hwrm_cmd_lock);
3979         return rc;
3980 }
3981
3982 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3983                              int timeout)
3984 {
3985         int rc;
3986
3987         mutex_lock(&bp->hwrm_cmd_lock);
3988         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3989         mutex_unlock(&bp->hwrm_cmd_lock);
3990         return rc;
3991 }
3992
3993 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3994                                      int bmap_size)
3995 {
3996         struct hwrm_func_drv_rgtr_input req = {0};
3997         DECLARE_BITMAP(async_events_bmap, 256);
3998         u32 *events = (u32 *)async_events_bmap;
3999         int i;
4000
4001         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4002
4003         req.enables =
4004                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4005
4006         memset(async_events_bmap, 0, sizeof(async_events_bmap));
4007         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4008                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4009
4010         if (bmap && bmap_size) {
4011                 for (i = 0; i < bmap_size; i++) {
4012                         if (test_bit(i, bmap))
4013                                 __set_bit(i, async_events_bmap);
4014                 }
4015         }
4016
4017         for (i = 0; i < 8; i++)
4018                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4019
4020         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4021 }
4022
4023 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4024 {
4025         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4026         struct hwrm_func_drv_rgtr_input req = {0};
4027         int rc;
4028
4029         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4030
4031         req.enables =
4032                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4033                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
4034
4035         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4036         req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4037         req.ver_maj_8b = DRV_VER_MAJ;
4038         req.ver_min_8b = DRV_VER_MIN;
4039         req.ver_upd_8b = DRV_VER_UPD;
4040         req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4041         req.ver_min = cpu_to_le16(DRV_VER_MIN);
4042         req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4043
4044         if (BNXT_PF(bp)) {
4045                 u32 data[8];
4046                 int i;
4047
4048                 memset(data, 0, sizeof(data));
4049                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4050                         u16 cmd = bnxt_vf_req_snif[i];
4051                         unsigned int bit, idx;
4052
4053                         idx = cmd / 32;
4054                         bit = cmd % 32;
4055                         data[idx] |= 1 << bit;
4056                 }
4057
4058                 for (i = 0; i < 8; i++)
4059                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4060
4061                 req.enables |=
4062                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4063         }
4064
4065         if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4066                 req.flags |= cpu_to_le32(
4067                         FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4068
4069         mutex_lock(&bp->hwrm_cmd_lock);
4070         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4071         if (rc)
4072                 rc = -EIO;
4073         else if (resp->flags &
4074                  cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4075                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4076         mutex_unlock(&bp->hwrm_cmd_lock);
4077         return rc;
4078 }
4079
4080 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4081 {
4082         struct hwrm_func_drv_unrgtr_input req = {0};
4083
4084         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4085         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4086 }
4087
4088 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4089 {
4090         u32 rc = 0;
4091         struct hwrm_tunnel_dst_port_free_input req = {0};
4092
4093         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4094         req.tunnel_type = tunnel_type;
4095
4096         switch (tunnel_type) {
4097         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4098                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4099                 break;
4100         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4101                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4102                 break;
4103         default:
4104                 break;
4105         }
4106
4107         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4108         if (rc)
4109                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4110                            rc);
4111         return rc;
4112 }
4113
4114 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4115                                            u8 tunnel_type)
4116 {
4117         u32 rc = 0;
4118         struct hwrm_tunnel_dst_port_alloc_input req = {0};
4119         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4120
4121         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4122
4123         req.tunnel_type = tunnel_type;
4124         req.tunnel_dst_port_val = port;
4125
4126         mutex_lock(&bp->hwrm_cmd_lock);
4127         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4128         if (rc) {
4129                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4130                            rc);
4131                 goto err_out;
4132         }
4133
4134         switch (tunnel_type) {
4135         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4136                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4137                 break;
4138         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4139                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4140                 break;
4141         default:
4142                 break;
4143         }
4144
4145 err_out:
4146         mutex_unlock(&bp->hwrm_cmd_lock);
4147         return rc;
4148 }
4149
4150 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4151 {
4152         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4153         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4154
4155         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4156         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4157
4158         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4159         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4160         req.mask = cpu_to_le32(vnic->rx_mask);
4161         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4162 }
4163
4164 #ifdef CONFIG_RFS_ACCEL
4165 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4166                                             struct bnxt_ntuple_filter *fltr)
4167 {
4168         struct hwrm_cfa_ntuple_filter_free_input req = {0};
4169
4170         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4171         req.ntuple_filter_id = fltr->filter_id;
4172         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4173 }
4174
4175 #define BNXT_NTP_FLTR_FLAGS                                     \
4176         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
4177          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
4178          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
4179          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
4180          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
4181          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
4182          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
4183          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
4184          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
4185          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
4186          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
4187          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
4188          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
4189          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4190
4191 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
4192                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4193
4194 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4195                                              struct bnxt_ntuple_filter *fltr)
4196 {
4197         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
4198         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4199         struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4200         struct flow_keys *keys = &fltr->fkeys;
4201         int rc = 0;
4202
4203         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4204         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4205
4206         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4207
4208         req.ethertype = htons(ETH_P_IP);
4209         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4210         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4211         req.ip_protocol = keys->basic.ip_proto;
4212
4213         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4214                 int i;
4215
4216                 req.ethertype = htons(ETH_P_IPV6);
4217                 req.ip_addr_type =
4218                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4219                 *(struct in6_addr *)&req.src_ipaddr[0] =
4220                         keys->addrs.v6addrs.src;
4221                 *(struct in6_addr *)&req.dst_ipaddr[0] =
4222                         keys->addrs.v6addrs.dst;
4223                 for (i = 0; i < 4; i++) {
4224                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4225                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4226                 }
4227         } else {
4228                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4229                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4230                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4231                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4232         }
4233         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4234                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4235                 req.tunnel_type =
4236                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4237         }
4238
4239         req.src_port = keys->ports.src;
4240         req.src_port_mask = cpu_to_be16(0xffff);
4241         req.dst_port = keys->ports.dst;
4242         req.dst_port_mask = cpu_to_be16(0xffff);
4243
4244         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4245         mutex_lock(&bp->hwrm_cmd_lock);
4246         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4247         if (!rc) {
4248                 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4249                 fltr->filter_id = resp->ntuple_filter_id;
4250         }
4251         mutex_unlock(&bp->hwrm_cmd_lock);
4252         return rc;
4253 }
4254 #endif
4255
4256 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4257                                      u8 *mac_addr)
4258 {
4259         u32 rc = 0;
4260         struct hwrm_cfa_l2_filter_alloc_input req = {0};
4261         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4262
4263         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4264         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4265         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4266                 req.flags |=
4267                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4268         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4269         req.enables =
4270                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4271                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4272                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4273         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4274         req.l2_addr_mask[0] = 0xff;
4275         req.l2_addr_mask[1] = 0xff;
4276         req.l2_addr_mask[2] = 0xff;
4277         req.l2_addr_mask[3] = 0xff;
4278         req.l2_addr_mask[4] = 0xff;
4279         req.l2_addr_mask[5] = 0xff;
4280
4281         mutex_lock(&bp->hwrm_cmd_lock);
4282         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4283         if (!rc)
4284                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4285                                                         resp->l2_filter_id;
4286         mutex_unlock(&bp->hwrm_cmd_lock);
4287         return rc;
4288 }
4289
4290 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4291 {
4292         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4293         int rc = 0;
4294
4295         /* Any associated ntuple filters will also be cleared by firmware. */
4296         mutex_lock(&bp->hwrm_cmd_lock);
4297         for (i = 0; i < num_of_vnics; i++) {
4298                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4299
4300                 for (j = 0; j < vnic->uc_filter_count; j++) {
4301                         struct hwrm_cfa_l2_filter_free_input req = {0};
4302
4303                         bnxt_hwrm_cmd_hdr_init(bp, &req,
4304                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
4305
4306                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
4307
4308                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4309                                                 HWRM_CMD_TIMEOUT);
4310                 }
4311                 vnic->uc_filter_count = 0;
4312         }
4313         mutex_unlock(&bp->hwrm_cmd_lock);
4314
4315         return rc;
4316 }
4317
4318 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4319 {
4320         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4321         struct hwrm_vnic_tpa_cfg_input req = {0};
4322
4323         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4324                 return 0;
4325
4326         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4327
4328         if (tpa_flags) {
4329                 u16 mss = bp->dev->mtu - 40;
4330                 u32 nsegs, n, segs = 0, flags;
4331
4332                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4333                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4334                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4335                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4336                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4337                 if (tpa_flags & BNXT_FLAG_GRO)
4338                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4339
4340                 req.flags = cpu_to_le32(flags);
4341
4342                 req.enables =
4343                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4344                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4345                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4346
4347                 /* Number of segs are log2 units, and first packet is not
4348                  * included as part of this units.
4349                  */
4350                 if (mss <= BNXT_RX_PAGE_SIZE) {
4351                         n = BNXT_RX_PAGE_SIZE / mss;
4352                         nsegs = (MAX_SKB_FRAGS - 1) * n;
4353                 } else {
4354                         n = mss / BNXT_RX_PAGE_SIZE;
4355                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
4356                                 n++;
4357                         nsegs = (MAX_SKB_FRAGS - n) / n;
4358                 }
4359
4360                 segs = ilog2(nsegs);
4361                 req.max_agg_segs = cpu_to_le16(segs);
4362                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4363
4364                 req.min_agg_len = cpu_to_le32(512);
4365         }
4366         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4367
4368         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4369 }
4370
4371 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4372 {
4373         struct bnxt_ring_grp_info *grp_info;
4374
4375         grp_info = &bp->grp_info[ring->grp_idx];
4376         return grp_info->cp_fw_ring_id;
4377 }
4378
4379 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4380 {
4381         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4382                 struct bnxt_napi *bnapi = rxr->bnapi;
4383                 struct bnxt_cp_ring_info *cpr;
4384
4385                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4386                 return cpr->cp_ring_struct.fw_ring_id;
4387         } else {
4388                 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4389         }
4390 }
4391
4392 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4393 {
4394         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4395                 struct bnxt_napi *bnapi = txr->bnapi;
4396                 struct bnxt_cp_ring_info *cpr;
4397
4398                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4399                 return cpr->cp_ring_struct.fw_ring_id;
4400         } else {
4401                 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4402         }
4403 }
4404
4405 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4406 {
4407         u32 i, j, max_rings;
4408         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4409         struct hwrm_vnic_rss_cfg_input req = {0};
4410
4411         if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4412             vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4413                 return 0;
4414
4415         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4416         if (set_rss) {
4417                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4418                 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4419                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4420                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4421                                 max_rings = bp->rx_nr_rings - 1;
4422                         else
4423                                 max_rings = bp->rx_nr_rings;
4424                 } else {
4425                         max_rings = 1;
4426                 }
4427
4428                 /* Fill the RSS indirection table with ring group ids */
4429                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4430                         if (j == max_rings)
4431                                 j = 0;
4432                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4433                 }
4434
4435                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4436                 req.hash_key_tbl_addr =
4437                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
4438         }
4439         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4440         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4441 }
4442
4443 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4444 {
4445         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4446         u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4447         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4448         struct hwrm_vnic_rss_cfg_input req = {0};
4449
4450         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4451         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4452         if (!set_rss) {
4453                 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4454                 return 0;
4455         }
4456         req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4457         req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4458         req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4459         req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4460         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4461         for (i = 0, k = 0; i < nr_ctxs; i++) {
4462                 __le16 *ring_tbl = vnic->rss_table;
4463                 int rc;
4464
4465                 req.ring_table_pair_index = i;
4466                 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4467                 for (j = 0; j < 64; j++) {
4468                         u16 ring_id;
4469
4470                         ring_id = rxr->rx_ring_struct.fw_ring_id;
4471                         *ring_tbl++ = cpu_to_le16(ring_id);
4472                         ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4473                         *ring_tbl++ = cpu_to_le16(ring_id);
4474                         rxr++;
4475                         k++;
4476                         if (k == max_rings) {
4477                                 k = 0;
4478                                 rxr = &bp->rx_ring[0];
4479                         }
4480                 }
4481                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4482                 if (rc)
4483                         return -EIO;
4484         }
4485         return 0;
4486 }
4487
4488 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4489 {
4490         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4491         struct hwrm_vnic_plcmodes_cfg_input req = {0};
4492
4493         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4494         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4495                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4496                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4497         req.enables =
4498                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4499                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4500         /* thresholds not implemented in firmware yet */
4501         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4502         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4503         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4504         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4505 }
4506
4507 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4508                                         u16 ctx_idx)
4509 {
4510         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4511
4512         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4513         req.rss_cos_lb_ctx_id =
4514                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4515
4516         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4517         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4518 }
4519
4520 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4521 {
4522         int i, j;
4523
4524         for (i = 0; i < bp->nr_vnics; i++) {
4525                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4526
4527                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4528                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4529                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4530                 }
4531         }
4532         bp->rsscos_nr_ctxs = 0;
4533 }
4534
4535 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4536 {
4537         int rc;
4538         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4539         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4540                                                 bp->hwrm_cmd_resp_addr;
4541
4542         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4543                                -1);
4544
4545         mutex_lock(&bp->hwrm_cmd_lock);
4546         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4547         if (!rc)
4548                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4549                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
4550         mutex_unlock(&bp->hwrm_cmd_lock);
4551
4552         return rc;
4553 }
4554
4555 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4556 {
4557         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4558                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4559         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4560 }
4561
4562 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4563 {
4564         unsigned int ring = 0, grp_idx;
4565         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4566         struct hwrm_vnic_cfg_input req = {0};
4567         u16 def_vlan = 0;
4568
4569         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4570
4571         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4572                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4573
4574                 req.default_rx_ring_id =
4575                         cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4576                 req.default_cmpl_ring_id =
4577                         cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4578                 req.enables =
4579                         cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4580                                     VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4581                 goto vnic_mru;
4582         }
4583         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4584         /* Only RSS support for now TBD: COS & LB */
4585         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4586                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4587                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4588                                            VNIC_CFG_REQ_ENABLES_MRU);
4589         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4590                 req.rss_rule =
4591                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4592                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4593                                            VNIC_CFG_REQ_ENABLES_MRU);
4594                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4595         } else {
4596                 req.rss_rule = cpu_to_le16(0xffff);
4597         }
4598
4599         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4600             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4601                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4602                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4603         } else {
4604                 req.cos_rule = cpu_to_le16(0xffff);
4605         }
4606
4607         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4608                 ring = 0;
4609         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4610                 ring = vnic_id - 1;
4611         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4612                 ring = bp->rx_nr_rings - 1;
4613
4614         grp_idx = bp->rx_ring[ring].bnapi->index;
4615         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4616         req.lb_rule = cpu_to_le16(0xffff);
4617 vnic_mru:
4618         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4619                               VLAN_HLEN);
4620
4621         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4622 #ifdef CONFIG_BNXT_SRIOV
4623         if (BNXT_VF(bp))
4624                 def_vlan = bp->vf.vlan;
4625 #endif
4626         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4627                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4628         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4629                 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4630
4631         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4632 }
4633
4634 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4635 {
4636         u32 rc = 0;
4637
4638         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4639                 struct hwrm_vnic_free_input req = {0};
4640
4641                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4642                 req.vnic_id =
4643                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4644
4645                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4646                 if (rc)
4647                         return rc;
4648                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4649         }
4650         return rc;
4651 }
4652
4653 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4654 {
4655         u16 i;
4656
4657         for (i = 0; i < bp->nr_vnics; i++)
4658                 bnxt_hwrm_vnic_free_one(bp, i);
4659 }
4660
4661 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4662                                 unsigned int start_rx_ring_idx,
4663                                 unsigned int nr_rings)
4664 {
4665         int rc = 0;
4666         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4667         struct hwrm_vnic_alloc_input req = {0};
4668         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4669         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4670
4671         if (bp->flags & BNXT_FLAG_CHIP_P5)
4672                 goto vnic_no_ring_grps;
4673
4674         /* map ring groups to this vnic */
4675         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4676                 grp_idx = bp->rx_ring[i].bnapi->index;
4677                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4678                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4679                                    j, nr_rings);
4680                         break;
4681                 }
4682                 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4683         }
4684
4685 vnic_no_ring_grps:
4686         for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4687                 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4688         if (vnic_id == 0)
4689                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4690
4691         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4692
4693         mutex_lock(&bp->hwrm_cmd_lock);
4694         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4695         if (!rc)
4696                 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4697         mutex_unlock(&bp->hwrm_cmd_lock);
4698         return rc;
4699 }
4700
4701 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4702 {
4703         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4704         struct hwrm_vnic_qcaps_input req = {0};
4705         int rc;
4706
4707         if (bp->hwrm_spec_code < 0x10600)
4708                 return 0;
4709
4710         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4711         mutex_lock(&bp->hwrm_cmd_lock);
4712         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4713         if (!rc) {
4714                 u32 flags = le32_to_cpu(resp->flags);
4715
4716                 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4717                     (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4718                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4719                 if (flags &
4720                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4721                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4722         }
4723         mutex_unlock(&bp->hwrm_cmd_lock);
4724         return rc;
4725 }
4726
4727 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4728 {
4729         u16 i;
4730         u32 rc = 0;
4731
4732         if (bp->flags & BNXT_FLAG_CHIP_P5)
4733                 return 0;
4734
4735         mutex_lock(&bp->hwrm_cmd_lock);
4736         for (i = 0; i < bp->rx_nr_rings; i++) {
4737                 struct hwrm_ring_grp_alloc_input req = {0};
4738                 struct hwrm_ring_grp_alloc_output *resp =
4739                                         bp->hwrm_cmd_resp_addr;
4740                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4741
4742                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4743
4744                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4745                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4746                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4747                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4748
4749                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4750                                         HWRM_CMD_TIMEOUT);
4751                 if (rc)
4752                         break;
4753
4754                 bp->grp_info[grp_idx].fw_grp_id =
4755                         le32_to_cpu(resp->ring_group_id);
4756         }
4757         mutex_unlock(&bp->hwrm_cmd_lock);
4758         return rc;
4759 }
4760
4761 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4762 {
4763         u16 i;
4764         u32 rc = 0;
4765         struct hwrm_ring_grp_free_input req = {0};
4766
4767         if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4768                 return 0;
4769
4770         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4771
4772         mutex_lock(&bp->hwrm_cmd_lock);
4773         for (i = 0; i < bp->cp_nr_rings; i++) {
4774                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4775                         continue;
4776                 req.ring_group_id =
4777                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4778
4779                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4780                                         HWRM_CMD_TIMEOUT);
4781                 if (rc)
4782                         break;
4783                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4784         }
4785         mutex_unlock(&bp->hwrm_cmd_lock);
4786         return rc;
4787 }
4788
4789 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4790                                     struct bnxt_ring_struct *ring,
4791                                     u32 ring_type, u32 map_index)
4792 {
4793         int rc = 0, err = 0;
4794         struct hwrm_ring_alloc_input req = {0};
4795         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4796         struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4797         struct bnxt_ring_grp_info *grp_info;
4798         u16 ring_id;
4799
4800         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4801
4802         req.enables = 0;
4803         if (rmem->nr_pages > 1) {
4804                 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4805                 /* Page size is in log2 units */
4806                 req.page_size = BNXT_PAGE_SHIFT;
4807                 req.page_tbl_depth = 1;
4808         } else {
4809                 req.page_tbl_addr =  cpu_to_le64(rmem->dma_arr[0]);
4810         }
4811         req.fbo = 0;
4812         /* Association of ring index with doorbell index and MSIX number */
4813         req.logical_id = cpu_to_le16(map_index);
4814
4815         switch (ring_type) {
4816         case HWRM_RING_ALLOC_TX: {
4817                 struct bnxt_tx_ring_info *txr;
4818
4819                 txr = container_of(ring, struct bnxt_tx_ring_info,
4820                                    tx_ring_struct);
4821                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4822                 /* Association of transmit ring with completion ring */
4823                 grp_info = &bp->grp_info[ring->grp_idx];
4824                 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4825                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4826                 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4827                 req.queue_id = cpu_to_le16(ring->queue_id);
4828                 break;
4829         }
4830         case HWRM_RING_ALLOC_RX:
4831                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4832                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4833                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4834                         u16 flags = 0;
4835
4836                         /* Association of rx ring with stats context */
4837                         grp_info = &bp->grp_info[ring->grp_idx];
4838                         req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4839                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4840                         req.enables |= cpu_to_le32(
4841                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4842                         if (NET_IP_ALIGN == 2)
4843                                 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4844                         req.flags = cpu_to_le16(flags);
4845                 }
4846                 break;
4847         case HWRM_RING_ALLOC_AGG:
4848                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4849                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4850                         /* Association of agg ring with rx ring */
4851                         grp_info = &bp->grp_info[ring->grp_idx];
4852                         req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4853                         req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4854                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4855                         req.enables |= cpu_to_le32(
4856                                 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4857                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4858                 } else {
4859                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4860                 }
4861                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4862                 break;
4863         case HWRM_RING_ALLOC_CMPL:
4864                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4865                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4866                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4867                         /* Association of cp ring with nq */
4868                         grp_info = &bp->grp_info[map_index];
4869                         req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4870                         req.cq_handle = cpu_to_le64(ring->handle);
4871                         req.enables |= cpu_to_le32(
4872                                 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4873                 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4874                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4875                 }
4876                 break;
4877         case HWRM_RING_ALLOC_NQ:
4878                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4879                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4880                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4881                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4882                 break;
4883         default:
4884                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4885                            ring_type);
4886                 return -1;
4887         }
4888
4889         mutex_lock(&bp->hwrm_cmd_lock);
4890         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4891         err = le16_to_cpu(resp->error_code);
4892         ring_id = le16_to_cpu(resp->ring_id);
4893         mutex_unlock(&bp->hwrm_cmd_lock);
4894
4895         if (rc || err) {
4896                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4897                            ring_type, rc, err);
4898                 return -EIO;
4899         }
4900         ring->fw_ring_id = ring_id;
4901         return rc;
4902 }
4903
4904 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4905 {
4906         int rc;
4907
4908         if (BNXT_PF(bp)) {
4909                 struct hwrm_func_cfg_input req = {0};
4910
4911                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4912                 req.fid = cpu_to_le16(0xffff);
4913                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4914                 req.async_event_cr = cpu_to_le16(idx);
4915                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4916         } else {
4917                 struct hwrm_func_vf_cfg_input req = {0};
4918
4919                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4920                 req.enables =
4921                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4922                 req.async_event_cr = cpu_to_le16(idx);
4923                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4924         }
4925         return rc;
4926 }
4927
4928 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
4929                         u32 map_idx, u32 xid)
4930 {
4931         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4932                 if (BNXT_PF(bp))
4933                         db->doorbell = bp->bar1 + 0x10000;
4934                 else
4935                         db->doorbell = bp->bar1 + 0x4000;
4936                 switch (ring_type) {
4937                 case HWRM_RING_ALLOC_TX:
4938                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
4939                         break;
4940                 case HWRM_RING_ALLOC_RX:
4941                 case HWRM_RING_ALLOC_AGG:
4942                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
4943                         break;
4944                 case HWRM_RING_ALLOC_CMPL:
4945                         db->db_key64 = DBR_PATH_L2;
4946                         break;
4947                 case HWRM_RING_ALLOC_NQ:
4948                         db->db_key64 = DBR_PATH_L2;
4949                         break;
4950                 }
4951                 db->db_key64 |= (u64)xid << DBR_XID_SFT;
4952         } else {
4953                 db->doorbell = bp->bar1 + map_idx * 0x80;
4954                 switch (ring_type) {
4955                 case HWRM_RING_ALLOC_TX:
4956                         db->db_key32 = DB_KEY_TX;
4957                         break;
4958                 case HWRM_RING_ALLOC_RX:
4959                 case HWRM_RING_ALLOC_AGG:
4960                         db->db_key32 = DB_KEY_RX;
4961                         break;
4962                 case HWRM_RING_ALLOC_CMPL:
4963                         db->db_key32 = DB_KEY_CP;
4964                         break;
4965                 }
4966         }
4967 }
4968
4969 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4970 {
4971         int i, rc = 0;
4972         u32 type;
4973
4974         if (bp->flags & BNXT_FLAG_CHIP_P5)
4975                 type = HWRM_RING_ALLOC_NQ;
4976         else
4977                 type = HWRM_RING_ALLOC_CMPL;
4978         for (i = 0; i < bp->cp_nr_rings; i++) {
4979                 struct bnxt_napi *bnapi = bp->bnapi[i];
4980                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4981                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4982                 u32 map_idx = ring->map_idx;
4983                 unsigned int vector;
4984
4985                 vector = bp->irq_tbl[map_idx].vector;
4986                 disable_irq_nosync(vector);
4987                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
4988                 if (rc) {
4989                         enable_irq(vector);
4990                         goto err_out;
4991                 }
4992                 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
4993                 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4994                 enable_irq(vector);
4995                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4996
4997                 if (!i) {
4998                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4999                         if (rc)
5000                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5001                 }
5002         }
5003
5004         type = HWRM_RING_ALLOC_TX;
5005         for (i = 0; i < bp->tx_nr_rings; i++) {
5006                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5007                 struct bnxt_ring_struct *ring;
5008                 u32 map_idx;
5009
5010                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5011                         struct bnxt_napi *bnapi = txr->bnapi;
5012                         struct bnxt_cp_ring_info *cpr, *cpr2;
5013                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5014
5015                         cpr = &bnapi->cp_ring;
5016                         cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5017                         ring = &cpr2->cp_ring_struct;
5018                         ring->handle = BNXT_TX_HDL;
5019                         map_idx = bnapi->index;
5020                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5021                         if (rc)
5022                                 goto err_out;
5023                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5024                                     ring->fw_ring_id);
5025                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5026                 }
5027                 ring = &txr->tx_ring_struct;
5028                 map_idx = i;
5029                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5030                 if (rc)
5031                         goto err_out;
5032                 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5033         }
5034
5035         type = HWRM_RING_ALLOC_RX;
5036         for (i = 0; i < bp->rx_nr_rings; i++) {
5037                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5038                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5039                 struct bnxt_napi *bnapi = rxr->bnapi;
5040                 u32 map_idx = bnapi->index;
5041
5042                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5043                 if (rc)
5044                         goto err_out;
5045                 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5046                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5047                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5048                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5049                         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5050                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5051                         struct bnxt_cp_ring_info *cpr2;
5052
5053                         cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5054                         ring = &cpr2->cp_ring_struct;
5055                         ring->handle = BNXT_RX_HDL;
5056                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5057                         if (rc)
5058                                 goto err_out;
5059                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5060                                     ring->fw_ring_id);
5061                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5062                 }
5063         }
5064
5065         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5066                 type = HWRM_RING_ALLOC_AGG;
5067                 for (i = 0; i < bp->rx_nr_rings; i++) {
5068                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5069                         struct bnxt_ring_struct *ring =
5070                                                 &rxr->rx_agg_ring_struct;
5071                         u32 grp_idx = ring->grp_idx;
5072                         u32 map_idx = grp_idx + bp->rx_nr_rings;
5073
5074                         rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5075                         if (rc)
5076                                 goto err_out;
5077
5078                         bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5079                                     ring->fw_ring_id);
5080                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5081                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5082                 }
5083         }
5084 err_out:
5085         return rc;
5086 }
5087
5088 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5089                                    struct bnxt_ring_struct *ring,
5090                                    u32 ring_type, int cmpl_ring_id)
5091 {
5092         int rc;
5093         struct hwrm_ring_free_input req = {0};
5094         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5095         u16 error_code;
5096
5097         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5098         req.ring_type = ring_type;
5099         req.ring_id = cpu_to_le16(ring->fw_ring_id);
5100
5101         mutex_lock(&bp->hwrm_cmd_lock);
5102         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5103         error_code = le16_to_cpu(resp->error_code);
5104         mutex_unlock(&bp->hwrm_cmd_lock);
5105
5106         if (rc || error_code) {
5107                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5108                            ring_type, rc, error_code);
5109                 return -EIO;
5110         }
5111         return 0;
5112 }
5113
5114 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5115 {
5116         u32 type;
5117         int i;
5118
5119         if (!bp->bnapi)
5120                 return;
5121
5122         for (i = 0; i < bp->tx_nr_rings; i++) {
5123                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5124                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5125                 u32 cmpl_ring_id;
5126
5127                 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5128                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5129                         hwrm_ring_free_send_msg(bp, ring,
5130                                                 RING_FREE_REQ_RING_TYPE_TX,
5131                                                 close_path ? cmpl_ring_id :
5132                                                 INVALID_HW_RING_ID);
5133                         ring->fw_ring_id = INVALID_HW_RING_ID;
5134                 }
5135         }
5136
5137         for (i = 0; i < bp->rx_nr_rings; i++) {
5138                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5139                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5140                 u32 grp_idx = rxr->bnapi->index;
5141                 u32 cmpl_ring_id;
5142
5143                 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5144                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5145                         hwrm_ring_free_send_msg(bp, ring,
5146                                                 RING_FREE_REQ_RING_TYPE_RX,
5147                                                 close_path ? cmpl_ring_id :
5148                                                 INVALID_HW_RING_ID);
5149                         ring->fw_ring_id = INVALID_HW_RING_ID;
5150                         bp->grp_info[grp_idx].rx_fw_ring_id =
5151                                 INVALID_HW_RING_ID;
5152                 }
5153         }
5154
5155         if (bp->flags & BNXT_FLAG_CHIP_P5)
5156                 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5157         else
5158                 type = RING_FREE_REQ_RING_TYPE_RX;
5159         for (i = 0; i < bp->rx_nr_rings; i++) {
5160                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5161                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5162                 u32 grp_idx = rxr->bnapi->index;
5163                 u32 cmpl_ring_id;
5164
5165                 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5166                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5167                         hwrm_ring_free_send_msg(bp, ring, type,
5168                                                 close_path ? cmpl_ring_id :
5169                                                 INVALID_HW_RING_ID);
5170                         ring->fw_ring_id = INVALID_HW_RING_ID;
5171                         bp->grp_info[grp_idx].agg_fw_ring_id =
5172                                 INVALID_HW_RING_ID;
5173                 }
5174         }
5175
5176         /* The completion rings are about to be freed.  After that the
5177          * IRQ doorbell will not work anymore.  So we need to disable
5178          * IRQ here.
5179          */
5180         bnxt_disable_int_sync(bp);
5181
5182         if (bp->flags & BNXT_FLAG_CHIP_P5)
5183                 type = RING_FREE_REQ_RING_TYPE_NQ;
5184         else
5185                 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5186         for (i = 0; i < bp->cp_nr_rings; i++) {
5187                 struct bnxt_napi *bnapi = bp->bnapi[i];
5188                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5189                 struct bnxt_ring_struct *ring;
5190                 int j;
5191
5192                 for (j = 0; j < 2; j++) {
5193                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5194
5195                         if (cpr2) {
5196                                 ring = &cpr2->cp_ring_struct;
5197                                 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5198                                         continue;
5199                                 hwrm_ring_free_send_msg(bp, ring,
5200                                         RING_FREE_REQ_RING_TYPE_L2_CMPL,
5201                                         INVALID_HW_RING_ID);
5202                                 ring->fw_ring_id = INVALID_HW_RING_ID;
5203                         }
5204                 }
5205                 ring = &cpr->cp_ring_struct;
5206                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5207                         hwrm_ring_free_send_msg(bp, ring, type,
5208                                                 INVALID_HW_RING_ID);
5209                         ring->fw_ring_id = INVALID_HW_RING_ID;
5210                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5211                 }
5212         }
5213 }
5214
5215 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5216                            bool shared);
5217
5218 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5219 {
5220         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5221         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5222         struct hwrm_func_qcfg_input req = {0};
5223         int rc;
5224
5225         if (bp->hwrm_spec_code < 0x10601)
5226                 return 0;
5227
5228         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5229         req.fid = cpu_to_le16(0xffff);
5230         mutex_lock(&bp->hwrm_cmd_lock);
5231         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5232         if (rc) {
5233                 mutex_unlock(&bp->hwrm_cmd_lock);
5234                 return -EIO;
5235         }
5236
5237         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5238         if (BNXT_NEW_RM(bp)) {
5239                 u16 cp, stats;
5240
5241                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5242                 hw_resc->resv_hw_ring_grps =
5243                         le32_to_cpu(resp->alloc_hw_ring_grps);
5244                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5245                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5246                 stats = le16_to_cpu(resp->alloc_stat_ctx);
5247                 hw_resc->resv_irqs = cp;
5248                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5249                         int rx = hw_resc->resv_rx_rings;
5250                         int tx = hw_resc->resv_tx_rings;
5251
5252                         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5253                                 rx >>= 1;
5254                         if (cp < (rx + tx)) {
5255                                 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5256                                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5257                                         rx <<= 1;
5258                                 hw_resc->resv_rx_rings = rx;
5259                                 hw_resc->resv_tx_rings = tx;
5260                         }
5261                         hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5262                         hw_resc->resv_hw_ring_grps = rx;
5263                 }
5264                 hw_resc->resv_cp_rings = cp;
5265                 hw_resc->resv_stat_ctxs = stats;
5266         }
5267         mutex_unlock(&bp->hwrm_cmd_lock);
5268         return 0;
5269 }
5270
5271 /* Caller must hold bp->hwrm_cmd_lock */
5272 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5273 {
5274         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5275         struct hwrm_func_qcfg_input req = {0};
5276         int rc;
5277
5278         if (bp->hwrm_spec_code < 0x10601)
5279                 return 0;
5280
5281         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5282         req.fid = cpu_to_le16(fid);
5283         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5284         if (!rc)
5285                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5286
5287         return rc;
5288 }
5289
5290 static bool bnxt_rfs_supported(struct bnxt *bp);
5291
5292 static void
5293 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5294                              int tx_rings, int rx_rings, int ring_grps,
5295                              int cp_rings, int stats, int vnics)
5296 {
5297         u32 enables = 0;
5298
5299         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5300         req->fid = cpu_to_le16(0xffff);
5301         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5302         req->num_tx_rings = cpu_to_le16(tx_rings);
5303         if (BNXT_NEW_RM(bp)) {
5304                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5305                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5306                         enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5307                         enables |= tx_rings + ring_grps ?
5308                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5309                                    FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5310                         enables |= rx_rings ?
5311                                 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5312                 } else {
5313                         enables |= cp_rings ?
5314                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5315                                    FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5316                         enables |= ring_grps ?
5317                                    FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5318                                    FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5319                 }
5320                 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5321
5322                 req->num_rx_rings = cpu_to_le16(rx_rings);
5323                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5324                         req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5325                         req->num_msix = cpu_to_le16(cp_rings);
5326                         req->num_rsscos_ctxs =
5327                                 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5328                 } else {
5329                         req->num_cmpl_rings = cpu_to_le16(cp_rings);
5330                         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5331                         req->num_rsscos_ctxs = cpu_to_le16(1);
5332                         if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5333                             bnxt_rfs_supported(bp))
5334                                 req->num_rsscos_ctxs =
5335                                         cpu_to_le16(ring_grps + 1);
5336                 }
5337                 req->num_stat_ctxs = cpu_to_le16(stats);
5338                 req->num_vnics = cpu_to_le16(vnics);
5339         }
5340         req->enables = cpu_to_le32(enables);
5341 }
5342
5343 static void
5344 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5345                              struct hwrm_func_vf_cfg_input *req, int tx_rings,
5346                              int rx_rings, int ring_grps, int cp_rings,
5347                              int stats, int vnics)
5348 {
5349         u32 enables = 0;
5350
5351         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5352         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5353         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5354                               FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5355         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5356                 enables |= tx_rings + ring_grps ?
5357                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5358                            FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5359         } else {
5360                 enables |= cp_rings ?
5361                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5362                            FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5363                 enables |= ring_grps ?
5364                            FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5365         }
5366         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5367         enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5368
5369         req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5370         req->num_tx_rings = cpu_to_le16(tx_rings);
5371         req->num_rx_rings = cpu_to_le16(rx_rings);
5372         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5373                 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5374                 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5375         } else {
5376                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5377                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5378                 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5379         }
5380         req->num_stat_ctxs = cpu_to_le16(stats);
5381         req->num_vnics = cpu_to_le16(vnics);
5382
5383         req->enables = cpu_to_le32(enables);
5384 }
5385
5386 static int
5387 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5388                            int ring_grps, int cp_rings, int stats, int vnics)
5389 {
5390         struct hwrm_func_cfg_input req = {0};
5391         int rc;
5392
5393         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5394                                      cp_rings, stats, vnics);
5395         if (!req.enables)
5396                 return 0;
5397
5398         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5399         if (rc)
5400                 return -ENOMEM;
5401
5402         if (bp->hwrm_spec_code < 0x10601)
5403                 bp->hw_resc.resv_tx_rings = tx_rings;
5404
5405         rc = bnxt_hwrm_get_rings(bp);
5406         return rc;
5407 }
5408
5409 static int
5410 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5411                            int ring_grps, int cp_rings, int stats, int vnics)
5412 {
5413         struct hwrm_func_vf_cfg_input req = {0};
5414         int rc;
5415
5416         if (!BNXT_NEW_RM(bp)) {
5417                 bp->hw_resc.resv_tx_rings = tx_rings;
5418                 return 0;
5419         }
5420
5421         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5422                                      cp_rings, stats, vnics);
5423         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5424         if (rc)
5425                 return -ENOMEM;
5426
5427         rc = bnxt_hwrm_get_rings(bp);
5428         return rc;
5429 }
5430
5431 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5432                                    int cp, int stat, int vnic)
5433 {
5434         if (BNXT_PF(bp))
5435                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5436                                                   vnic);
5437         else
5438                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5439                                                   vnic);
5440 }
5441
5442 int bnxt_nq_rings_in_use(struct bnxt *bp)
5443 {
5444         int cp = bp->cp_nr_rings;
5445         int ulp_msix, ulp_base;
5446
5447         ulp_msix = bnxt_get_ulp_msix_num(bp);
5448         if (ulp_msix) {
5449                 ulp_base = bnxt_get_ulp_msix_base(bp);
5450                 cp += ulp_msix;
5451                 if ((ulp_base + ulp_msix) > cp)
5452                         cp = ulp_base + ulp_msix;
5453         }
5454         return cp;
5455 }
5456
5457 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5458 {
5459         int cp;
5460
5461         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5462                 return bnxt_nq_rings_in_use(bp);
5463
5464         cp = bp->tx_nr_rings + bp->rx_nr_rings;
5465         return cp;
5466 }
5467
5468 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5469 {
5470         return bp->cp_nr_rings + bnxt_get_ulp_stat_ctxs(bp);
5471 }
5472
5473 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5474 {
5475         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5476         int cp = bnxt_cp_rings_in_use(bp);
5477         int nq = bnxt_nq_rings_in_use(bp);
5478         int rx = bp->rx_nr_rings, stat;
5479         int vnic = 1, grp = rx;
5480
5481         if (bp->hwrm_spec_code < 0x10601)
5482                 return false;
5483
5484         if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5485                 return true;
5486
5487         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5488                 vnic = rx + 1;
5489         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5490                 rx <<= 1;
5491         stat = bnxt_get_func_stat_ctxs(bp);
5492         if (BNXT_NEW_RM(bp) &&
5493             (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5494              hw_resc->resv_irqs < nq || hw_resc->resv_vnics != vnic ||
5495              hw_resc->resv_stat_ctxs != stat ||
5496              (hw_resc->resv_hw_ring_grps != grp &&
5497               !(bp->flags & BNXT_FLAG_CHIP_P5))))
5498                 return true;
5499         return false;
5500 }
5501
5502 static int __bnxt_reserve_rings(struct bnxt *bp)
5503 {
5504         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5505         int cp = bnxt_nq_rings_in_use(bp);
5506         int tx = bp->tx_nr_rings;
5507         int rx = bp->rx_nr_rings;
5508         int grp, rx_rings, rc;
5509         int vnic = 1, stat;
5510         bool sh = false;
5511
5512         if (!bnxt_need_reserve_rings(bp))
5513                 return 0;
5514
5515         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5516                 sh = true;
5517         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5518                 vnic = rx + 1;
5519         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5520                 rx <<= 1;
5521         grp = bp->rx_nr_rings;
5522         stat = bnxt_get_func_stat_ctxs(bp);
5523
5524         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5525         if (rc)
5526                 return rc;
5527
5528         tx = hw_resc->resv_tx_rings;
5529         if (BNXT_NEW_RM(bp)) {
5530                 rx = hw_resc->resv_rx_rings;
5531                 cp = hw_resc->resv_irqs;
5532                 grp = hw_resc->resv_hw_ring_grps;
5533                 vnic = hw_resc->resv_vnics;
5534                 stat = hw_resc->resv_stat_ctxs;
5535         }
5536
5537         rx_rings = rx;
5538         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5539                 if (rx >= 2) {
5540                         rx_rings = rx >> 1;
5541                 } else {
5542                         if (netif_running(bp->dev))
5543                                 return -ENOMEM;
5544
5545                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5546                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5547                         bp->dev->hw_features &= ~NETIF_F_LRO;
5548                         bp->dev->features &= ~NETIF_F_LRO;
5549                         bnxt_set_ring_params(bp);
5550                 }
5551         }
5552         rx_rings = min_t(int, rx_rings, grp);
5553         cp = min_t(int, cp, bp->cp_nr_rings);
5554         if (stat > bnxt_get_ulp_stat_ctxs(bp))
5555                 stat -= bnxt_get_ulp_stat_ctxs(bp);
5556         cp = min_t(int, cp, stat);
5557         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5558         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5559                 rx = rx_rings << 1;
5560         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5561         bp->tx_nr_rings = tx;
5562         bp->rx_nr_rings = rx_rings;
5563         bp->cp_nr_rings = cp;
5564
5565         if (!tx || !rx || !cp || !grp || !vnic || !stat)
5566                 return -ENOMEM;
5567
5568         return rc;
5569 }
5570
5571 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5572                                     int ring_grps, int cp_rings, int stats,
5573                                     int vnics)
5574 {
5575         struct hwrm_func_vf_cfg_input req = {0};
5576         u32 flags;
5577         int rc;
5578
5579         if (!BNXT_NEW_RM(bp))
5580                 return 0;
5581
5582         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5583                                      cp_rings, stats, vnics);
5584         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5585                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5586                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5587                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5588                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5589                 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5590         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5591                 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5592
5593         req.flags = cpu_to_le32(flags);
5594         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5595         if (rc)
5596                 return -ENOMEM;
5597         return 0;
5598 }
5599
5600 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5601                                     int ring_grps, int cp_rings, int stats,
5602                                     int vnics)
5603 {
5604         struct hwrm_func_cfg_input req = {0};
5605         u32 flags;
5606         int rc;
5607
5608         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5609                                      cp_rings, stats, vnics);
5610         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5611         if (BNXT_NEW_RM(bp)) {
5612                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5613                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5614                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5615                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5616                 if (bp->flags & BNXT_FLAG_CHIP_P5)
5617                         flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
5618                                  FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
5619                 else
5620                         flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5621         }
5622
5623         req.flags = cpu_to_le32(flags);
5624         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5625         if (rc)
5626                 return -ENOMEM;
5627         return 0;
5628 }
5629
5630 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5631                                  int ring_grps, int cp_rings, int stats,
5632                                  int vnics)
5633 {
5634         if (bp->hwrm_spec_code < 0x10801)
5635                 return 0;
5636
5637         if (BNXT_PF(bp))
5638                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5639                                                 ring_grps, cp_rings, stats,
5640                                                 vnics);
5641
5642         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5643                                         cp_rings, stats, vnics);
5644 }
5645
5646 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5647 {
5648         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5649         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5650         struct hwrm_ring_aggint_qcaps_input req = {0};
5651         int rc;
5652
5653         coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5654         coal_cap->num_cmpl_dma_aggr_max = 63;
5655         coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5656         coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5657         coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5658         coal_cap->int_lat_tmr_min_max = 65535;
5659         coal_cap->int_lat_tmr_max_max = 65535;
5660         coal_cap->num_cmpl_aggr_int_max = 65535;
5661         coal_cap->timer_units = 80;
5662
5663         if (bp->hwrm_spec_code < 0x10902)
5664                 return;
5665
5666         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5667         mutex_lock(&bp->hwrm_cmd_lock);
5668         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5669         if (!rc) {
5670                 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5671                 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5672                 coal_cap->num_cmpl_dma_aggr_max =
5673                         le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5674                 coal_cap->num_cmpl_dma_aggr_during_int_max =
5675                         le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5676                 coal_cap->cmpl_aggr_dma_tmr_max =
5677                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5678                 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5679                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5680                 coal_cap->int_lat_tmr_min_max =
5681                         le16_to_cpu(resp->int_lat_tmr_min_max);
5682                 coal_cap->int_lat_tmr_max_max =
5683                         le16_to_cpu(resp->int_lat_tmr_max_max);
5684                 coal_cap->num_cmpl_aggr_int_max =
5685                         le16_to_cpu(resp->num_cmpl_aggr_int_max);
5686                 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5687         }
5688         mutex_unlock(&bp->hwrm_cmd_lock);
5689 }
5690
5691 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5692 {
5693         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5694
5695         return usec * 1000 / coal_cap->timer_units;
5696 }
5697
5698 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5699         struct bnxt_coal *hw_coal,
5700         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5701 {
5702         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5703         u32 cmpl_params = coal_cap->cmpl_params;
5704         u16 val, tmr, max, flags = 0;
5705
5706         max = hw_coal->bufs_per_record * 128;
5707         if (hw_coal->budget)
5708                 max = hw_coal->bufs_per_record * hw_coal->budget;
5709         max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5710
5711         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5712         req->num_cmpl_aggr_int = cpu_to_le16(val);
5713
5714         val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5715         req->num_cmpl_dma_aggr = cpu_to_le16(val);
5716
5717         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5718                       coal_cap->num_cmpl_dma_aggr_during_int_max);
5719         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5720
5721         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5722         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5723         req->int_lat_tmr_max = cpu_to_le16(tmr);
5724
5725         /* min timer set to 1/2 of interrupt timer */
5726         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5727                 val = tmr / 2;
5728                 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5729                 req->int_lat_tmr_min = cpu_to_le16(val);
5730                 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5731         }
5732
5733         /* buf timer set to 1/4 of interrupt timer */
5734         val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5735         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5736
5737         if (cmpl_params &
5738             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5739                 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5740                 val = clamp_t(u16, tmr, 1,
5741                               coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5742                 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5743                 req->enables |=
5744                         cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5745         }
5746
5747         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5748                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5749         if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5750             hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5751                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5752         req->flags = cpu_to_le16(flags);
5753         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5754 }
5755
5756 /* Caller holds bp->hwrm_cmd_lock */
5757 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5758                                    struct bnxt_coal *hw_coal)
5759 {
5760         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5761         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5762         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5763         u32 nq_params = coal_cap->nq_params;
5764         u16 tmr;
5765
5766         if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5767                 return 0;
5768
5769         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5770                                -1, -1);
5771         req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5772         req.flags =
5773                 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5774
5775         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5776         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5777         req.int_lat_tmr_min = cpu_to_le16(tmr);
5778         req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5779         return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5780 }
5781
5782 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5783 {
5784         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5785         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5786         struct bnxt_coal coal;
5787
5788         /* Tick values in micro seconds.
5789          * 1 coal_buf x bufs_per_record = 1 completion record.
5790          */
5791         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5792
5793         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5794         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5795
5796         if (!bnapi->rx_ring)
5797                 return -ENODEV;
5798
5799         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5800                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5801
5802         bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5803
5804         req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5805
5806         return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5807                                  HWRM_CMD_TIMEOUT);
5808 }
5809
5810 int bnxt_hwrm_set_coal(struct bnxt *bp)
5811 {
5812         int i, rc = 0;
5813         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5814                                                            req_tx = {0}, *req;
5815
5816         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5817                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5818         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5819                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5820
5821         bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5822         bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5823
5824         mutex_lock(&bp->hwrm_cmd_lock);
5825         for (i = 0; i < bp->cp_nr_rings; i++) {
5826                 struct bnxt_napi *bnapi = bp->bnapi[i];
5827                 struct bnxt_coal *hw_coal;
5828                 u16 ring_id;
5829
5830                 req = &req_rx;
5831                 if (!bnapi->rx_ring) {
5832                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5833                         req = &req_tx;
5834                 } else {
5835                         ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5836                 }
5837                 req->ring_id = cpu_to_le16(ring_id);
5838
5839                 rc = _hwrm_send_message(bp, req, sizeof(*req),
5840                                         HWRM_CMD_TIMEOUT);
5841                 if (rc)
5842                         break;
5843
5844                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5845                         continue;
5846
5847                 if (bnapi->rx_ring && bnapi->tx_ring) {
5848                         req = &req_tx;
5849                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5850                         req->ring_id = cpu_to_le16(ring_id);
5851                         rc = _hwrm_send_message(bp, req, sizeof(*req),
5852                                                 HWRM_CMD_TIMEOUT);
5853                         if (rc)
5854                                 break;
5855                 }
5856                 if (bnapi->rx_ring)
5857                         hw_coal = &bp->rx_coal;
5858                 else
5859                         hw_coal = &bp->tx_coal;
5860                 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5861         }
5862         mutex_unlock(&bp->hwrm_cmd_lock);
5863         return rc;
5864 }
5865
5866 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5867 {
5868         int rc = 0, i;
5869         struct hwrm_stat_ctx_free_input req = {0};
5870
5871         if (!bp->bnapi)
5872                 return 0;
5873
5874         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5875                 return 0;
5876
5877         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5878
5879         mutex_lock(&bp->hwrm_cmd_lock);
5880         for (i = 0; i < bp->cp_nr_rings; i++) {
5881                 struct bnxt_napi *bnapi = bp->bnapi[i];
5882                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5883
5884                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5885                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5886
5887                         rc = _hwrm_send_message(bp, &req, sizeof(req),
5888                                                 HWRM_CMD_TIMEOUT);
5889                         if (rc)
5890                                 break;
5891
5892                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5893                 }
5894         }
5895         mutex_unlock(&bp->hwrm_cmd_lock);
5896         return rc;
5897 }
5898
5899 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5900 {
5901         int rc = 0, i;
5902         struct hwrm_stat_ctx_alloc_input req = {0};
5903         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5904
5905         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5906                 return 0;
5907
5908         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5909
5910         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5911
5912         mutex_lock(&bp->hwrm_cmd_lock);
5913         for (i = 0; i < bp->cp_nr_rings; i++) {
5914                 struct bnxt_napi *bnapi = bp->bnapi[i];
5915                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5916
5917                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5918
5919                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5920                                         HWRM_CMD_TIMEOUT);
5921                 if (rc)
5922                         break;
5923
5924                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5925
5926                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5927         }
5928         mutex_unlock(&bp->hwrm_cmd_lock);
5929         return rc;
5930 }
5931
5932 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5933 {
5934         struct hwrm_func_qcfg_input req = {0};
5935         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5936         u16 flags;
5937         int rc;
5938
5939         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5940         req.fid = cpu_to_le16(0xffff);
5941         mutex_lock(&bp->hwrm_cmd_lock);
5942         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5943         if (rc)
5944                 goto func_qcfg_exit;
5945
5946 #ifdef CONFIG_BNXT_SRIOV
5947         if (BNXT_VF(bp)) {
5948                 struct bnxt_vf_info *vf = &bp->vf;
5949
5950                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5951         }
5952 #endif
5953         flags = le16_to_cpu(resp->flags);
5954         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5955                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5956                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5957                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5958                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
5959         }
5960         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5961                 bp->flags |= BNXT_FLAG_MULTI_HOST;
5962
5963         switch (resp->port_partition_type) {
5964         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5965         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5966         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5967                 bp->port_partition_type = resp->port_partition_type;
5968                 break;
5969         }
5970         if (bp->hwrm_spec_code < 0x10707 ||
5971             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5972                 bp->br_mode = BRIDGE_MODE_VEB;
5973         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5974                 bp->br_mode = BRIDGE_MODE_VEPA;
5975         else
5976                 bp->br_mode = BRIDGE_MODE_UNDEF;
5977
5978         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5979         if (!bp->max_mtu)
5980                 bp->max_mtu = BNXT_MAX_MTU;
5981
5982 func_qcfg_exit:
5983         mutex_unlock(&bp->hwrm_cmd_lock);
5984         return rc;
5985 }
5986
5987 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5988 {
5989         struct hwrm_func_backing_store_qcaps_input req = {0};
5990         struct hwrm_func_backing_store_qcaps_output *resp =
5991                 bp->hwrm_cmd_resp_addr;
5992         int rc;
5993
5994         if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
5995                 return 0;
5996
5997         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
5998         mutex_lock(&bp->hwrm_cmd_lock);
5999         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6000         if (!rc) {
6001                 struct bnxt_ctx_pg_info *ctx_pg;
6002                 struct bnxt_ctx_mem_info *ctx;
6003                 int i;
6004
6005                 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6006                 if (!ctx) {
6007                         rc = -ENOMEM;
6008                         goto ctx_err;
6009                 }
6010                 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6011                 if (!ctx_pg) {
6012                         kfree(ctx);
6013                         rc = -ENOMEM;
6014                         goto ctx_err;
6015                 }
6016                 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6017                         ctx->tqm_mem[i] = ctx_pg;
6018
6019                 bp->ctx = ctx;
6020                 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6021                 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6022                 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6023                 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6024                 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6025                 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6026                 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6027                 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6028                 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6029                 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6030                 ctx->vnic_max_vnic_entries =
6031                         le16_to_cpu(resp->vnic_max_vnic_entries);
6032                 ctx->vnic_max_ring_table_entries =
6033                         le16_to_cpu(resp->vnic_max_ring_table_entries);
6034                 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6035                 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6036                 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6037                 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6038                 ctx->tqm_min_entries_per_ring =
6039                         le32_to_cpu(resp->tqm_min_entries_per_ring);
6040                 ctx->tqm_max_entries_per_ring =
6041                         le32_to_cpu(resp->tqm_max_entries_per_ring);
6042                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6043                 if (!ctx->tqm_entries_multiple)
6044                         ctx->tqm_entries_multiple = 1;
6045                 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6046                 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6047                 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6048                 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6049         } else {
6050                 rc = 0;
6051         }
6052 ctx_err:
6053         mutex_unlock(&bp->hwrm_cmd_lock);
6054         return rc;
6055 }
6056
6057 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6058                                   __le64 *pg_dir)
6059 {
6060         u8 pg_size = 0;
6061
6062         if (BNXT_PAGE_SHIFT == 13)
6063                 pg_size = 1 << 4;
6064         else if (BNXT_PAGE_SIZE == 16)
6065                 pg_size = 2 << 4;
6066
6067         *pg_attr = pg_size;
6068         if (rmem->depth >= 1) {
6069                 if (rmem->depth == 2)
6070                         *pg_attr |= 2;
6071                 else
6072                         *pg_attr |= 1;
6073                 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6074         } else {
6075                 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6076         }
6077 }
6078
6079 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES                 \
6080         (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP |                \
6081          FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ |               \
6082          FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ |                \
6083          FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC |              \
6084          FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6085
6086 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6087 {
6088         struct hwrm_func_backing_store_cfg_input req = {0};
6089         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6090         struct bnxt_ctx_pg_info *ctx_pg;
6091         __le32 *num_entries;
6092         __le64 *pg_dir;
6093         u8 *pg_attr;
6094         int i, rc;
6095         u32 ena;
6096
6097         if (!ctx)
6098                 return 0;
6099
6100         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6101         req.enables = cpu_to_le32(enables);
6102
6103         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6104                 ctx_pg = &ctx->qp_mem;
6105                 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6106                 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6107                 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6108                 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6109                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6110                                       &req.qpc_pg_size_qpc_lvl,
6111                                       &req.qpc_page_dir);
6112         }
6113         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6114                 ctx_pg = &ctx->srq_mem;
6115                 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6116                 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6117                 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6118                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6119                                       &req.srq_pg_size_srq_lvl,
6120                                       &req.srq_page_dir);
6121         }
6122         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6123                 ctx_pg = &ctx->cq_mem;
6124                 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6125                 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6126                 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6127                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6128                                       &req.cq_page_dir);
6129         }
6130         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6131                 ctx_pg = &ctx->vnic_mem;
6132                 req.vnic_num_vnic_entries =
6133                         cpu_to_le16(ctx->vnic_max_vnic_entries);
6134                 req.vnic_num_ring_table_entries =
6135                         cpu_to_le16(ctx->vnic_max_ring_table_entries);
6136                 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6137                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6138                                       &req.vnic_pg_size_vnic_lvl,
6139                                       &req.vnic_page_dir);
6140         }
6141         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6142                 ctx_pg = &ctx->stat_mem;
6143                 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6144                 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6145                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6146                                       &req.stat_pg_size_stat_lvl,
6147                                       &req.stat_page_dir);
6148         }
6149         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6150                 ctx_pg = &ctx->mrav_mem;
6151                 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6152                 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6153                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6154                                       &req.mrav_pg_size_mrav_lvl,
6155                                       &req.mrav_page_dir);
6156         }
6157         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6158                 ctx_pg = &ctx->tim_mem;
6159                 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6160                 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6161                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6162                                       &req.tim_pg_size_tim_lvl,
6163                                       &req.tim_page_dir);
6164         }
6165         for (i = 0, num_entries = &req.tqm_sp_num_entries,
6166              pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6167              pg_dir = &req.tqm_sp_page_dir,
6168              ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6169              i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6170                 if (!(enables & ena))
6171                         continue;
6172
6173                 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6174                 ctx_pg = ctx->tqm_mem[i];
6175                 *num_entries = cpu_to_le32(ctx_pg->entries);
6176                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6177         }
6178         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6179         if (rc)
6180                 rc = -EIO;
6181         return rc;
6182 }
6183
6184 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6185                                   struct bnxt_ctx_pg_info *ctx_pg)
6186 {
6187         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6188
6189         rmem->page_size = BNXT_PAGE_SIZE;
6190         rmem->pg_arr = ctx_pg->ctx_pg_arr;
6191         rmem->dma_arr = ctx_pg->ctx_dma_arr;
6192         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6193         if (rmem->depth >= 1)
6194                 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6195         return bnxt_alloc_ring(bp, rmem);
6196 }
6197
6198 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6199                                   struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6200                                   u8 depth)
6201 {
6202         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6203         int rc;
6204
6205         if (!mem_size)
6206                 return 0;
6207
6208         ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6209         if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6210                 ctx_pg->nr_pages = 0;
6211                 return -EINVAL;
6212         }
6213         if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6214                 int nr_tbls, i;
6215
6216                 rmem->depth = 2;
6217                 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6218                                              GFP_KERNEL);
6219                 if (!ctx_pg->ctx_pg_tbl)
6220                         return -ENOMEM;
6221                 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6222                 rmem->nr_pages = nr_tbls;
6223                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6224                 if (rc)
6225                         return rc;
6226                 for (i = 0; i < nr_tbls; i++) {
6227                         struct bnxt_ctx_pg_info *pg_tbl;
6228
6229                         pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6230                         if (!pg_tbl)
6231                                 return -ENOMEM;
6232                         ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6233                         rmem = &pg_tbl->ring_mem;
6234                         rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6235                         rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6236                         rmem->depth = 1;
6237                         rmem->nr_pages = MAX_CTX_PAGES;
6238                         if (i == (nr_tbls - 1)) {
6239                                 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6240
6241                                 if (rem)
6242                                         rmem->nr_pages = rem;
6243                         }
6244                         rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6245                         if (rc)
6246                                 break;
6247                 }
6248         } else {
6249                 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6250                 if (rmem->nr_pages > 1 || depth)
6251                         rmem->depth = 1;
6252                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6253         }
6254         return rc;
6255 }
6256
6257 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6258                                   struct bnxt_ctx_pg_info *ctx_pg)
6259 {
6260         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6261
6262         if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6263             ctx_pg->ctx_pg_tbl) {
6264                 int i, nr_tbls = rmem->nr_pages;
6265
6266                 for (i = 0; i < nr_tbls; i++) {
6267                         struct bnxt_ctx_pg_info *pg_tbl;
6268                         struct bnxt_ring_mem_info *rmem2;
6269
6270                         pg_tbl = ctx_pg->ctx_pg_tbl[i];
6271                         if (!pg_tbl)
6272                                 continue;
6273                         rmem2 = &pg_tbl->ring_mem;
6274                         bnxt_free_ring(bp, rmem2);
6275                         ctx_pg->ctx_pg_arr[i] = NULL;
6276                         kfree(pg_tbl);
6277                         ctx_pg->ctx_pg_tbl[i] = NULL;
6278                 }
6279                 kfree(ctx_pg->ctx_pg_tbl);
6280                 ctx_pg->ctx_pg_tbl = NULL;
6281         }
6282         bnxt_free_ring(bp, rmem);
6283         ctx_pg->nr_pages = 0;
6284 }
6285
6286 static void bnxt_free_ctx_mem(struct bnxt *bp)
6287 {
6288         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6289         int i;
6290
6291         if (!ctx)
6292                 return;
6293
6294         if (ctx->tqm_mem[0]) {
6295                 for (i = 0; i < bp->max_q + 1; i++)
6296                         bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6297                 kfree(ctx->tqm_mem[0]);
6298                 ctx->tqm_mem[0] = NULL;
6299         }
6300
6301         bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6302         bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6303         bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6304         bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6305         bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6306         bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6307         bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6308         ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6309 }
6310
6311 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6312 {
6313         struct bnxt_ctx_pg_info *ctx_pg;
6314         struct bnxt_ctx_mem_info *ctx;
6315         u32 mem_size, ena, entries;
6316         u32 extra_srqs = 0;
6317         u32 extra_qps = 0;
6318         u8 pg_lvl = 1;
6319         int i, rc;
6320
6321         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6322         if (rc) {
6323                 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6324                            rc);
6325                 return rc;
6326         }
6327         ctx = bp->ctx;
6328         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6329                 return 0;
6330
6331         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
6332                 pg_lvl = 2;
6333                 extra_qps = 65536;
6334                 extra_srqs = 8192;
6335         }
6336
6337         ctx_pg = &ctx->qp_mem;
6338         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6339                           extra_qps;
6340         mem_size = ctx->qp_entry_size * ctx_pg->entries;
6341         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6342         if (rc)
6343                 return rc;
6344
6345         ctx_pg = &ctx->srq_mem;
6346         ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6347         mem_size = ctx->srq_entry_size * ctx_pg->entries;
6348         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6349         if (rc)
6350                 return rc;
6351
6352         ctx_pg = &ctx->cq_mem;
6353         ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6354         mem_size = ctx->cq_entry_size * ctx_pg->entries;
6355         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6356         if (rc)
6357                 return rc;
6358
6359         ctx_pg = &ctx->vnic_mem;
6360         ctx_pg->entries = ctx->vnic_max_vnic_entries +
6361                           ctx->vnic_max_ring_table_entries;
6362         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6363         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6364         if (rc)
6365                 return rc;
6366
6367         ctx_pg = &ctx->stat_mem;
6368         ctx_pg->entries = ctx->stat_max_entries;
6369         mem_size = ctx->stat_entry_size * ctx_pg->entries;
6370         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6371         if (rc)
6372                 return rc;
6373
6374         ena = 0;
6375         if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6376                 goto skip_rdma;
6377
6378         ctx_pg = &ctx->mrav_mem;
6379         ctx_pg->entries = extra_qps * 4;
6380         mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6381         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6382         if (rc)
6383                 return rc;
6384         ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6385
6386         ctx_pg = &ctx->tim_mem;
6387         ctx_pg->entries = ctx->qp_mem.entries;
6388         mem_size = ctx->tim_entry_size * ctx_pg->entries;
6389         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6390         if (rc)
6391                 return rc;
6392         ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6393
6394 skip_rdma:
6395         entries = ctx->qp_max_l2_entries + extra_qps;
6396         entries = roundup(entries, ctx->tqm_entries_multiple);
6397         entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6398                           ctx->tqm_max_entries_per_ring);
6399         for (i = 0; i < bp->max_q + 1; i++) {
6400                 ctx_pg = ctx->tqm_mem[i];
6401                 ctx_pg->entries = entries;
6402                 mem_size = ctx->tqm_entry_size * entries;
6403                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6404                 if (rc)
6405                         return rc;
6406                 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6407         }
6408         ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6409         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6410         if (rc)
6411                 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6412                            rc);
6413         else
6414                 ctx->flags |= BNXT_CTX_FLAG_INITED;
6415
6416         return 0;
6417 }
6418
6419 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6420 {
6421         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6422         struct hwrm_func_resource_qcaps_input req = {0};
6423         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6424         int rc;
6425
6426         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6427         req.fid = cpu_to_le16(0xffff);
6428
6429         mutex_lock(&bp->hwrm_cmd_lock);
6430         rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6431                                        HWRM_CMD_TIMEOUT);
6432         if (rc) {
6433                 rc = -EIO;
6434                 goto hwrm_func_resc_qcaps_exit;
6435         }
6436
6437         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6438         if (!all)
6439                 goto hwrm_func_resc_qcaps_exit;
6440
6441         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6442         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6443         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6444         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6445         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6446         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6447         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6448         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6449         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6450         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6451         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6452         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6453         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6454         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6455         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6456         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6457
6458         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6459                 u16 max_msix = le16_to_cpu(resp->max_msix);
6460
6461                 hw_resc->max_nqs = max_msix;
6462                 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6463         }
6464
6465         if (BNXT_PF(bp)) {
6466                 struct bnxt_pf_info *pf = &bp->pf;
6467
6468                 pf->vf_resv_strategy =
6469                         le16_to_cpu(resp->vf_reservation_strategy);
6470                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6471                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6472         }
6473 hwrm_func_resc_qcaps_exit:
6474         mutex_unlock(&bp->hwrm_cmd_lock);
6475         return rc;
6476 }
6477
6478 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6479 {
6480         int rc = 0;
6481         struct hwrm_func_qcaps_input req = {0};
6482         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6483         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6484         u32 flags;
6485
6486         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6487         req.fid = cpu_to_le16(0xffff);
6488
6489         mutex_lock(&bp->hwrm_cmd_lock);
6490         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6491         if (rc)
6492                 goto hwrm_func_qcaps_exit;
6493
6494         flags = le32_to_cpu(resp->flags);
6495         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6496                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6497         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6498                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6499
6500         bp->tx_push_thresh = 0;
6501         if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6502                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6503
6504         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6505         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6506         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6507         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6508         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6509         if (!hw_resc->max_hw_ring_grps)
6510                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6511         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6512         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6513         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6514
6515         if (BNXT_PF(bp)) {
6516                 struct bnxt_pf_info *pf = &bp->pf;
6517
6518                 pf->fw_fid = le16_to_cpu(resp->fid);
6519                 pf->port_id = le16_to_cpu(resp->port_id);
6520                 bp->dev->dev_port = pf->port_id;
6521                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6522                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6523                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6524                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6525                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6526                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6527                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6528                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6529                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6530                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6531                         bp->flags |= BNXT_FLAG_WOL_CAP;
6532         } else {
6533 #ifdef CONFIG_BNXT_SRIOV
6534                 struct bnxt_vf_info *vf = &bp->vf;
6535
6536                 vf->fw_fid = le16_to_cpu(resp->fid);
6537                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6538 #endif
6539         }
6540
6541 hwrm_func_qcaps_exit:
6542         mutex_unlock(&bp->hwrm_cmd_lock);
6543         return rc;
6544 }
6545
6546 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6547
6548 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6549 {
6550         int rc;
6551
6552         rc = __bnxt_hwrm_func_qcaps(bp);
6553         if (rc)
6554                 return rc;
6555         rc = bnxt_hwrm_queue_qportcfg(bp);
6556         if (rc) {
6557                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6558                 return rc;
6559         }
6560         if (bp->hwrm_spec_code >= 0x10803) {
6561                 rc = bnxt_alloc_ctx_mem(bp);
6562                 if (rc)
6563                         return rc;
6564                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6565                 if (!rc)
6566                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6567         }
6568         return 0;
6569 }
6570
6571 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6572 {
6573         struct hwrm_func_reset_input req = {0};
6574
6575         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6576         req.enables = 0;
6577
6578         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6579 }
6580
6581 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6582 {
6583         int rc = 0;
6584         struct hwrm_queue_qportcfg_input req = {0};
6585         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6586         u8 i, j, *qptr;
6587         bool no_rdma;
6588
6589         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6590
6591         mutex_lock(&bp->hwrm_cmd_lock);
6592         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6593         if (rc)
6594                 goto qportcfg_exit;
6595
6596         if (!resp->max_configurable_queues) {
6597                 rc = -EINVAL;
6598                 goto qportcfg_exit;
6599         }
6600         bp->max_tc = resp->max_configurable_queues;
6601         bp->max_lltc = resp->max_configurable_lossless_queues;
6602         if (bp->max_tc > BNXT_MAX_QUEUE)
6603                 bp->max_tc = BNXT_MAX_QUEUE;
6604
6605         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6606         qptr = &resp->queue_id0;
6607         for (i = 0, j = 0; i < bp->max_tc; i++) {
6608                 bp->q_info[j].queue_id = *qptr;
6609                 bp->q_ids[i] = *qptr++;
6610                 bp->q_info[j].queue_profile = *qptr++;
6611                 bp->tc_to_qidx[j] = j;
6612                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6613                     (no_rdma && BNXT_PF(bp)))
6614                         j++;
6615         }
6616         bp->max_q = bp->max_tc;
6617         bp->max_tc = max_t(u8, j, 1);
6618
6619         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6620                 bp->max_tc = 1;
6621
6622         if (bp->max_lltc > bp->max_tc)
6623                 bp->max_lltc = bp->max_tc;
6624
6625 qportcfg_exit:
6626         mutex_unlock(&bp->hwrm_cmd_lock);
6627         return rc;
6628 }
6629
6630 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6631 {
6632         int rc;
6633         struct hwrm_ver_get_input req = {0};
6634         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6635         u32 dev_caps_cfg;
6636
6637         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6638         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6639         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6640         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6641         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6642         mutex_lock(&bp->hwrm_cmd_lock);
6643         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6644         if (rc)
6645                 goto hwrm_ver_get_exit;
6646
6647         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6648
6649         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6650                              resp->hwrm_intf_min_8b << 8 |
6651                              resp->hwrm_intf_upd_8b;
6652         if (resp->hwrm_intf_maj_8b < 1) {
6653                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6654                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6655                             resp->hwrm_intf_upd_8b);
6656                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6657         }
6658         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6659                  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6660                  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6661
6662         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6663         if (!bp->hwrm_cmd_timeout)
6664                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6665
6666         if (resp->hwrm_intf_maj_8b >= 1) {
6667                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6668                 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6669         }
6670         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6671                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6672
6673         bp->chip_num = le16_to_cpu(resp->chip_num);
6674         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6675             !resp->chip_metal)
6676                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6677
6678         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6679         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6680             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6681                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6682
6683         if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6684                 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6685
6686         if (dev_caps_cfg &
6687             VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6688                 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6689
6690         if (dev_caps_cfg &
6691             VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
6692                 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
6693
6694 hwrm_ver_get_exit:
6695         mutex_unlock(&bp->hwrm_cmd_lock);
6696         return rc;
6697 }
6698
6699 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6700 {
6701         struct hwrm_fw_set_time_input req = {0};
6702         struct tm tm;
6703         time64_t now = ktime_get_real_seconds();
6704
6705         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6706             bp->hwrm_spec_code < 0x10400)
6707                 return -EOPNOTSUPP;
6708
6709         time64_to_tm(now, 0, &tm);
6710         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6711         req.year = cpu_to_le16(1900 + tm.tm_year);
6712         req.month = 1 + tm.tm_mon;
6713         req.day = tm.tm_mday;
6714         req.hour = tm.tm_hour;
6715         req.minute = tm.tm_min;
6716         req.second = tm.tm_sec;
6717         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6718 }
6719
6720 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6721 {
6722         int rc;
6723         struct bnxt_pf_info *pf = &bp->pf;
6724         struct hwrm_port_qstats_input req = {0};
6725
6726         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6727                 return 0;
6728
6729         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6730         req.port_id = cpu_to_le16(pf->port_id);
6731         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6732         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6733         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6734         return rc;
6735 }
6736
6737 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6738 {
6739         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6740         struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6741         struct hwrm_port_qstats_ext_input req = {0};
6742         struct bnxt_pf_info *pf = &bp->pf;
6743         int rc;
6744
6745         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6746                 return 0;
6747
6748         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6749         req.port_id = cpu_to_le16(pf->port_id);
6750         req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6751         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6752         req.tx_stat_size = cpu_to_le16(sizeof(struct tx_port_stats_ext));
6753         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6754         mutex_lock(&bp->hwrm_cmd_lock);
6755         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6756         if (!rc) {
6757                 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6758                 bp->fw_tx_stats_ext_size = le16_to_cpu(resp->tx_stat_size) / 8;
6759         } else {
6760                 bp->fw_rx_stats_ext_size = 0;
6761                 bp->fw_tx_stats_ext_size = 0;
6762         }
6763         if (bp->fw_tx_stats_ext_size <=
6764             offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6765                 mutex_unlock(&bp->hwrm_cmd_lock);
6766                 bp->pri2cos_valid = 0;
6767                 return rc;
6768         }
6769
6770         bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6771         req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6772
6773         rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6774         if (!rc) {
6775                 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6776                 u8 *pri2cos;
6777                 int i, j;
6778
6779                 resp2 = bp->hwrm_cmd_resp_addr;
6780                 pri2cos = &resp2->pri0_cos_queue_id;
6781                 for (i = 0; i < 8; i++) {
6782                         u8 queue_id = pri2cos[i];
6783
6784                         for (j = 0; j < bp->max_q; j++) {
6785                                 if (bp->q_ids[j] == queue_id)
6786                                         bp->pri2cos[i] = j;
6787                         }
6788                 }
6789                 bp->pri2cos_valid = 1;
6790         }
6791         mutex_unlock(&bp->hwrm_cmd_lock);
6792         return rc;
6793 }
6794
6795 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6796 {
6797         if (bp->vxlan_port_cnt) {
6798                 bnxt_hwrm_tunnel_dst_port_free(
6799                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6800         }
6801         bp->vxlan_port_cnt = 0;
6802         if (bp->nge_port_cnt) {
6803                 bnxt_hwrm_tunnel_dst_port_free(
6804                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6805         }
6806         bp->nge_port_cnt = 0;
6807 }
6808
6809 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6810 {
6811         int rc, i;
6812         u32 tpa_flags = 0;
6813
6814         if (set_tpa)
6815                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
6816         for (i = 0; i < bp->nr_vnics; i++) {
6817                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
6818                 if (rc) {
6819                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
6820                                    i, rc);
6821                         return rc;
6822                 }
6823         }
6824         return 0;
6825 }
6826
6827 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
6828 {
6829         int i;
6830
6831         for (i = 0; i < bp->nr_vnics; i++)
6832                 bnxt_hwrm_vnic_set_rss(bp, i, false);
6833 }
6834
6835 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
6836                                     bool irq_re_init)
6837 {
6838         if (bp->vnic_info) {
6839                 bnxt_hwrm_clear_vnic_filter(bp);
6840                 /* clear all RSS setting before free vnic ctx */
6841                 bnxt_hwrm_clear_vnic_rss(bp);
6842                 bnxt_hwrm_vnic_ctx_free(bp);
6843                 /* before free the vnic, undo the vnic tpa settings */
6844                 if (bp->flags & BNXT_FLAG_TPA)
6845                         bnxt_set_tpa(bp, false);
6846                 bnxt_hwrm_vnic_free(bp);
6847         }
6848         bnxt_hwrm_ring_free(bp, close_path);
6849         bnxt_hwrm_ring_grp_free(bp);
6850         if (irq_re_init) {
6851                 bnxt_hwrm_stat_ctx_free(bp);
6852                 bnxt_hwrm_free_tunnel_ports(bp);
6853         }
6854 }
6855
6856 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
6857 {
6858         struct hwrm_func_cfg_input req = {0};
6859         int rc;
6860
6861         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6862         req.fid = cpu_to_le16(0xffff);
6863         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
6864         if (br_mode == BRIDGE_MODE_VEB)
6865                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
6866         else if (br_mode == BRIDGE_MODE_VEPA)
6867                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
6868         else
6869                 return -EINVAL;
6870         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6871         if (rc)
6872                 rc = -EIO;
6873         return rc;
6874 }
6875
6876 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
6877 {
6878         struct hwrm_func_cfg_input req = {0};
6879         int rc;
6880
6881         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
6882                 return 0;
6883
6884         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6885         req.fid = cpu_to_le16(0xffff);
6886         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
6887         req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
6888         if (size == 128)
6889                 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
6890
6891         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6892         if (rc)
6893                 rc = -EIO;
6894         return rc;
6895 }
6896
6897 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
6898 {
6899         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
6900         int rc;
6901
6902         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
6903                 goto skip_rss_ctx;
6904
6905         /* allocate context for vnic */
6906         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
6907         if (rc) {
6908                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
6909                            vnic_id, rc);
6910                 goto vnic_setup_err;
6911         }
6912         bp->rsscos_nr_ctxs++;
6913
6914         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6915                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
6916                 if (rc) {
6917                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
6918                                    vnic_id, rc);
6919                         goto vnic_setup_err;
6920                 }
6921                 bp->rsscos_nr_ctxs++;
6922         }
6923
6924 skip_rss_ctx:
6925         /* configure default vnic, ring grp */
6926         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6927         if (rc) {
6928                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6929                            vnic_id, rc);
6930                 goto vnic_setup_err;
6931         }
6932
6933         /* Enable RSS hashing on vnic */
6934         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
6935         if (rc) {
6936                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
6937                            vnic_id, rc);
6938                 goto vnic_setup_err;
6939         }
6940
6941         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6942                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6943                 if (rc) {
6944                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6945                                    vnic_id, rc);
6946                 }
6947         }
6948
6949 vnic_setup_err:
6950         return rc;
6951 }
6952
6953 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
6954 {
6955         int rc, i, nr_ctxs;
6956
6957         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
6958         for (i = 0; i < nr_ctxs; i++) {
6959                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
6960                 if (rc) {
6961                         netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
6962                                    vnic_id, i, rc);
6963                         break;
6964                 }
6965                 bp->rsscos_nr_ctxs++;
6966         }
6967         if (i < nr_ctxs)
6968                 return -ENOMEM;
6969
6970         rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
6971         if (rc) {
6972                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
6973                            vnic_id, rc);
6974                 return rc;
6975         }
6976         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6977         if (rc) {
6978                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6979                            vnic_id, rc);
6980                 return rc;
6981         }
6982         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6983                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6984                 if (rc) {
6985                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6986                                    vnic_id, rc);
6987                 }
6988         }
6989         return rc;
6990 }
6991
6992 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
6993 {
6994         if (bp->flags & BNXT_FLAG_CHIP_P5)
6995                 return __bnxt_setup_vnic_p5(bp, vnic_id);
6996         else
6997                 return __bnxt_setup_vnic(bp, vnic_id);
6998 }
6999
7000 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7001 {
7002 #ifdef CONFIG_RFS_ACCEL
7003         int i, rc = 0;
7004
7005         for (i = 0; i < bp->rx_nr_rings; i++) {
7006                 struct bnxt_vnic_info *vnic;
7007                 u16 vnic_id = i + 1;
7008                 u16 ring_id = i;
7009
7010                 if (vnic_id >= bp->nr_vnics)
7011                         break;
7012
7013                 vnic = &bp->vnic_info[vnic_id];
7014                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7015                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7016                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7017                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7018                 if (rc) {
7019                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7020                                    vnic_id, rc);
7021                         break;
7022                 }
7023                 rc = bnxt_setup_vnic(bp, vnic_id);
7024                 if (rc)
7025                         break;
7026         }
7027         return rc;
7028 #else
7029         return 0;
7030 #endif
7031 }
7032
7033 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7034 static bool bnxt_promisc_ok(struct bnxt *bp)
7035 {
7036 #ifdef CONFIG_BNXT_SRIOV
7037         if (BNXT_VF(bp) && !bp->vf.vlan)
7038                 return false;
7039 #endif
7040         return true;
7041 }
7042
7043 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7044 {
7045         unsigned int rc = 0;
7046
7047         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7048         if (rc) {
7049                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7050                            rc);
7051                 return rc;
7052         }
7053
7054         rc = bnxt_hwrm_vnic_cfg(bp, 1);
7055         if (rc) {
7056                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7057                            rc);
7058                 return rc;
7059         }
7060         return rc;
7061 }
7062
7063 static int bnxt_cfg_rx_mode(struct bnxt *);
7064 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7065
7066 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7067 {
7068         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7069         int rc = 0;
7070         unsigned int rx_nr_rings = bp->rx_nr_rings;
7071
7072         if (irq_re_init) {
7073                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7074                 if (rc) {
7075                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7076                                    rc);
7077                         goto err_out;
7078                 }
7079         }
7080
7081         rc = bnxt_hwrm_ring_alloc(bp);
7082         if (rc) {
7083                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7084                 goto err_out;
7085         }
7086
7087         rc = bnxt_hwrm_ring_grp_alloc(bp);
7088         if (rc) {
7089                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7090                 goto err_out;
7091         }
7092
7093         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7094                 rx_nr_rings--;
7095
7096         /* default vnic 0 */
7097         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7098         if (rc) {
7099                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7100                 goto err_out;
7101         }
7102
7103         rc = bnxt_setup_vnic(bp, 0);
7104         if (rc)
7105                 goto err_out;
7106
7107         if (bp->flags & BNXT_FLAG_RFS) {
7108                 rc = bnxt_alloc_rfs_vnics(bp);
7109                 if (rc)
7110                         goto err_out;
7111         }
7112
7113         if (bp->flags & BNXT_FLAG_TPA) {
7114                 rc = bnxt_set_tpa(bp, true);
7115                 if (rc)
7116                         goto err_out;
7117         }
7118
7119         if (BNXT_VF(bp))
7120                 bnxt_update_vf_mac(bp);
7121
7122         /* Filter for default vnic 0 */
7123         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7124         if (rc) {
7125                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7126                 goto err_out;
7127         }
7128         vnic->uc_filter_count = 1;
7129
7130         vnic->rx_mask = 0;
7131         if (bp->dev->flags & IFF_BROADCAST)
7132                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7133
7134         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7135                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7136
7137         if (bp->dev->flags & IFF_ALLMULTI) {
7138                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7139                 vnic->mc_list_count = 0;
7140         } else {
7141                 u32 mask = 0;
7142
7143                 bnxt_mc_list_updated(bp, &mask);
7144                 vnic->rx_mask |= mask;
7145         }
7146
7147         rc = bnxt_cfg_rx_mode(bp);
7148         if (rc)
7149                 goto err_out;
7150
7151         rc = bnxt_hwrm_set_coal(bp);
7152         if (rc)
7153                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7154                                 rc);
7155
7156         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7157                 rc = bnxt_setup_nitroa0_vnic(bp);
7158                 if (rc)
7159                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7160                                    rc);
7161         }
7162
7163         if (BNXT_VF(bp)) {
7164                 bnxt_hwrm_func_qcfg(bp);
7165                 netdev_update_features(bp->dev);
7166         }
7167
7168         return 0;
7169
7170 err_out:
7171         bnxt_hwrm_resource_free(bp, 0, true);
7172
7173         return rc;
7174 }
7175
7176 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7177 {
7178         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7179         return 0;
7180 }
7181
7182 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7183 {
7184         bnxt_init_cp_rings(bp);
7185         bnxt_init_rx_rings(bp);
7186         bnxt_init_tx_rings(bp);
7187         bnxt_init_ring_grps(bp, irq_re_init);
7188         bnxt_init_vnics(bp);
7189
7190         return bnxt_init_chip(bp, irq_re_init);
7191 }
7192
7193 static int bnxt_set_real_num_queues(struct bnxt *bp)
7194 {
7195         int rc;
7196         struct net_device *dev = bp->dev;
7197
7198         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7199                                           bp->tx_nr_rings_xdp);
7200         if (rc)
7201                 return rc;
7202
7203         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7204         if (rc)
7205                 return rc;
7206
7207 #ifdef CONFIG_RFS_ACCEL
7208         if (bp->flags & BNXT_FLAG_RFS)
7209                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7210 #endif
7211
7212         return rc;
7213 }
7214
7215 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7216                            bool shared)
7217 {
7218         int _rx = *rx, _tx = *tx;
7219
7220         if (shared) {
7221                 *rx = min_t(int, _rx, max);
7222                 *tx = min_t(int, _tx, max);
7223         } else {
7224                 if (max < 2)
7225                         return -ENOMEM;
7226
7227                 while (_rx + _tx > max) {
7228                         if (_rx > _tx && _rx > 1)
7229                                 _rx--;
7230                         else if (_tx > 1)
7231                                 _tx--;
7232                 }
7233                 *rx = _rx;
7234                 *tx = _tx;
7235         }
7236         return 0;
7237 }
7238
7239 static void bnxt_setup_msix(struct bnxt *bp)
7240 {
7241         const int len = sizeof(bp->irq_tbl[0].name);
7242         struct net_device *dev = bp->dev;
7243         int tcs, i;
7244
7245         tcs = netdev_get_num_tc(dev);
7246         if (tcs > 1) {
7247                 int i, off, count;
7248
7249                 for (i = 0; i < tcs; i++) {
7250                         count = bp->tx_nr_rings_per_tc;
7251                         off = i * count;
7252                         netdev_set_tc_queue(dev, i, count, off);
7253                 }
7254         }
7255
7256         for (i = 0; i < bp->cp_nr_rings; i++) {
7257                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7258                 char *attr;
7259
7260                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7261                         attr = "TxRx";
7262                 else if (i < bp->rx_nr_rings)
7263                         attr = "rx";
7264                 else
7265                         attr = "tx";
7266
7267                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7268                          attr, i);
7269                 bp->irq_tbl[map_idx].handler = bnxt_msix;
7270         }
7271 }
7272
7273 static void bnxt_setup_inta(struct bnxt *bp)
7274 {
7275         const int len = sizeof(bp->irq_tbl[0].name);
7276
7277         if (netdev_get_num_tc(bp->dev))
7278                 netdev_reset_tc(bp->dev);
7279
7280         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7281                  0);
7282         bp->irq_tbl[0].handler = bnxt_inta;
7283 }
7284
7285 static int bnxt_setup_int_mode(struct bnxt *bp)
7286 {
7287         int rc;
7288
7289         if (bp->flags & BNXT_FLAG_USING_MSIX)
7290                 bnxt_setup_msix(bp);
7291         else
7292                 bnxt_setup_inta(bp);
7293
7294         rc = bnxt_set_real_num_queues(bp);
7295         return rc;
7296 }
7297
7298 #ifdef CONFIG_RFS_ACCEL
7299 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7300 {
7301         return bp->hw_resc.max_rsscos_ctxs;
7302 }
7303
7304 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7305 {
7306         return bp->hw_resc.max_vnics;
7307 }
7308 #endif
7309
7310 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7311 {
7312         return bp->hw_resc.max_stat_ctxs;
7313 }
7314
7315 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7316 {
7317         return bp->hw_resc.max_cp_rings;
7318 }
7319
7320 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7321 {
7322         unsigned int cp = bp->hw_resc.max_cp_rings;
7323
7324         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7325                 cp -= bnxt_get_ulp_msix_num(bp);
7326
7327         return cp;
7328 }
7329
7330 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7331 {
7332         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7333
7334         if (bp->flags & BNXT_FLAG_CHIP_P5)
7335                 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7336
7337         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7338 }
7339
7340 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7341 {
7342         bp->hw_resc.max_irqs = max_irqs;
7343 }
7344
7345 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7346 {
7347         unsigned int cp;
7348
7349         cp = bnxt_get_max_func_cp_rings_for_en(bp);
7350         if (bp->flags & BNXT_FLAG_CHIP_P5)
7351                 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7352         else
7353                 return cp - bp->cp_nr_rings;
7354 }
7355
7356 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7357 {
7358         unsigned int stat;
7359
7360         stat = bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_ulp_stat_ctxs(bp);
7361         stat -= bp->cp_nr_rings;
7362         return stat;
7363 }
7364
7365 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7366 {
7367         int max_cp = bnxt_get_max_func_cp_rings(bp);
7368         int max_irq = bnxt_get_max_func_irqs(bp);
7369         int total_req = bp->cp_nr_rings + num;
7370         int max_idx, avail_msix;
7371
7372         max_idx = bp->total_irqs;
7373         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7374                 max_idx = min_t(int, bp->total_irqs, max_cp);
7375         avail_msix = max_idx - bp->cp_nr_rings;
7376         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7377                 return avail_msix;
7378
7379         if (max_irq < total_req) {
7380                 num = max_irq - bp->cp_nr_rings;
7381                 if (num <= 0)
7382                         return 0;
7383         }
7384         return num;
7385 }
7386
7387 static int bnxt_get_num_msix(struct bnxt *bp)
7388 {
7389         if (!BNXT_NEW_RM(bp))
7390                 return bnxt_get_max_func_irqs(bp);
7391
7392         return bnxt_nq_rings_in_use(bp);
7393 }
7394
7395 static int bnxt_init_msix(struct bnxt *bp)
7396 {
7397         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7398         struct msix_entry *msix_ent;
7399
7400         total_vecs = bnxt_get_num_msix(bp);
7401         max = bnxt_get_max_func_irqs(bp);
7402         if (total_vecs > max)
7403                 total_vecs = max;
7404
7405         if (!total_vecs)
7406                 return 0;
7407
7408         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7409         if (!msix_ent)
7410                 return -ENOMEM;
7411
7412         for (i = 0; i < total_vecs; i++) {
7413                 msix_ent[i].entry = i;
7414                 msix_ent[i].vector = 0;
7415         }
7416
7417         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7418                 min = 2;
7419
7420         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7421         ulp_msix = bnxt_get_ulp_msix_num(bp);
7422         if (total_vecs < 0 || total_vecs < ulp_msix) {
7423                 rc = -ENODEV;
7424                 goto msix_setup_exit;
7425         }
7426
7427         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7428         if (bp->irq_tbl) {
7429                 for (i = 0; i < total_vecs; i++)
7430                         bp->irq_tbl[i].vector = msix_ent[i].vector;
7431
7432                 bp->total_irqs = total_vecs;
7433                 /* Trim rings based upon num of vectors allocated */
7434                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7435                                      total_vecs - ulp_msix, min == 1);
7436                 if (rc)
7437                         goto msix_setup_exit;
7438
7439                 bp->cp_nr_rings = (min == 1) ?
7440                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7441                                   bp->tx_nr_rings + bp->rx_nr_rings;
7442
7443         } else {
7444                 rc = -ENOMEM;
7445                 goto msix_setup_exit;
7446         }
7447         bp->flags |= BNXT_FLAG_USING_MSIX;
7448         kfree(msix_ent);
7449         return 0;
7450
7451 msix_setup_exit:
7452         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7453         kfree(bp->irq_tbl);
7454         bp->irq_tbl = NULL;
7455         pci_disable_msix(bp->pdev);
7456         kfree(msix_ent);
7457         return rc;
7458 }
7459
7460 static int bnxt_init_inta(struct bnxt *bp)
7461 {
7462         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7463         if (!bp->irq_tbl)
7464                 return -ENOMEM;
7465
7466         bp->total_irqs = 1;
7467         bp->rx_nr_rings = 1;
7468         bp->tx_nr_rings = 1;
7469         bp->cp_nr_rings = 1;
7470         bp->flags |= BNXT_FLAG_SHARED_RINGS;
7471         bp->irq_tbl[0].vector = bp->pdev->irq;
7472         return 0;
7473 }
7474
7475 static int bnxt_init_int_mode(struct bnxt *bp)
7476 {
7477         int rc = 0;
7478
7479         if (bp->flags & BNXT_FLAG_MSIX_CAP)
7480                 rc = bnxt_init_msix(bp);
7481
7482         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7483                 /* fallback to INTA */
7484                 rc = bnxt_init_inta(bp);
7485         }
7486         return rc;
7487 }
7488
7489 static void bnxt_clear_int_mode(struct bnxt *bp)
7490 {
7491         if (bp->flags & BNXT_FLAG_USING_MSIX)
7492                 pci_disable_msix(bp->pdev);
7493
7494         kfree(bp->irq_tbl);
7495         bp->irq_tbl = NULL;
7496         bp->flags &= ~BNXT_FLAG_USING_MSIX;
7497 }
7498
7499 int bnxt_reserve_rings(struct bnxt *bp)
7500 {
7501         int tcs = netdev_get_num_tc(bp->dev);
7502         bool reinit_irq = false;
7503         int rc;
7504
7505         if (!bnxt_need_reserve_rings(bp))
7506                 return 0;
7507
7508         if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
7509                 bnxt_ulp_irq_stop(bp);
7510                 bnxt_clear_int_mode(bp);
7511                 reinit_irq = true;
7512         }
7513         rc = __bnxt_reserve_rings(bp);
7514         if (reinit_irq) {
7515                 if (!rc)
7516                         rc = bnxt_init_int_mode(bp);
7517                 bnxt_ulp_irq_restart(bp, rc);
7518         }
7519         if (rc) {
7520                 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7521                 return rc;
7522         }
7523         if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7524                 netdev_err(bp->dev, "tx ring reservation failure\n");
7525                 netdev_reset_tc(bp->dev);
7526                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7527                 return -ENOMEM;
7528         }
7529         return 0;
7530 }
7531
7532 static void bnxt_free_irq(struct bnxt *bp)
7533 {
7534         struct bnxt_irq *irq;
7535         int i;
7536
7537 #ifdef CONFIG_RFS_ACCEL
7538         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7539         bp->dev->rx_cpu_rmap = NULL;
7540 #endif
7541         if (!bp->irq_tbl || !bp->bnapi)
7542                 return;
7543
7544         for (i = 0; i < bp->cp_nr_rings; i++) {
7545                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7546
7547                 irq = &bp->irq_tbl[map_idx];
7548                 if (irq->requested) {
7549                         if (irq->have_cpumask) {
7550                                 irq_set_affinity_hint(irq->vector, NULL);
7551                                 free_cpumask_var(irq->cpu_mask);
7552                                 irq->have_cpumask = 0;
7553                         }
7554                         free_irq(irq->vector, bp->bnapi[i]);
7555                 }
7556
7557                 irq->requested = 0;
7558         }
7559 }
7560
7561 static int bnxt_request_irq(struct bnxt *bp)
7562 {
7563         int i, j, rc = 0;
7564         unsigned long flags = 0;
7565 #ifdef CONFIG_RFS_ACCEL
7566         struct cpu_rmap *rmap;
7567 #endif
7568
7569         rc = bnxt_setup_int_mode(bp);
7570         if (rc) {
7571                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7572                            rc);
7573                 return rc;
7574         }
7575 #ifdef CONFIG_RFS_ACCEL
7576         rmap = bp->dev->rx_cpu_rmap;
7577 #endif
7578         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7579                 flags = IRQF_SHARED;
7580
7581         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7582                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7583                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7584
7585 #ifdef CONFIG_RFS_ACCEL
7586                 if (rmap && bp->bnapi[i]->rx_ring) {
7587                         rc = irq_cpu_rmap_add(rmap, irq->vector);
7588                         if (rc)
7589                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7590                                             j);
7591                         j++;
7592                 }
7593 #endif
7594                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7595                                  bp->bnapi[i]);
7596                 if (rc)
7597                         break;
7598
7599                 irq->requested = 1;
7600
7601                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7602                         int numa_node = dev_to_node(&bp->pdev->dev);
7603
7604                         irq->have_cpumask = 1;
7605                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7606                                         irq->cpu_mask);
7607                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7608                         if (rc) {
7609                                 netdev_warn(bp->dev,
7610                                             "Set affinity failed, IRQ = %d\n",
7611                                             irq->vector);
7612                                 break;
7613                         }
7614                 }
7615         }
7616         return rc;
7617 }
7618
7619 static void bnxt_del_napi(struct bnxt *bp)
7620 {
7621         int i;
7622
7623         if (!bp->bnapi)
7624                 return;
7625
7626         for (i = 0; i < bp->cp_nr_rings; i++) {
7627                 struct bnxt_napi *bnapi = bp->bnapi[i];
7628
7629                 napi_hash_del(&bnapi->napi);
7630                 netif_napi_del(&bnapi->napi);
7631         }
7632         /* We called napi_hash_del() before netif_napi_del(), we need
7633          * to respect an RCU grace period before freeing napi structures.
7634          */
7635         synchronize_net();
7636 }
7637
7638 static void bnxt_init_napi(struct bnxt *bp)
7639 {
7640         int i;
7641         unsigned int cp_nr_rings = bp->cp_nr_rings;
7642         struct bnxt_napi *bnapi;
7643
7644         if (bp->flags & BNXT_FLAG_USING_MSIX) {
7645                 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7646
7647                 if (bp->flags & BNXT_FLAG_CHIP_P5)
7648                         poll_fn = bnxt_poll_p5;
7649                 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7650                         cp_nr_rings--;
7651                 for (i = 0; i < cp_nr_rings; i++) {
7652                         bnapi = bp->bnapi[i];
7653                         netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7654                 }
7655                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7656                         bnapi = bp->bnapi[cp_nr_rings];
7657                         netif_napi_add(bp->dev, &bnapi->napi,
7658                                        bnxt_poll_nitroa0, 64);
7659                 }
7660         } else {
7661                 bnapi = bp->bnapi[0];
7662                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7663         }
7664 }
7665
7666 static void bnxt_disable_napi(struct bnxt *bp)
7667 {
7668         int i;
7669
7670         if (!bp->bnapi)
7671                 return;
7672
7673         for (i = 0; i < bp->cp_nr_rings; i++) {
7674                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7675
7676                 if (bp->bnapi[i]->rx_ring)
7677                         cancel_work_sync(&cpr->dim.work);
7678
7679                 napi_disable(&bp->bnapi[i]->napi);
7680         }
7681 }
7682
7683 static void bnxt_enable_napi(struct bnxt *bp)
7684 {
7685         int i;
7686
7687         for (i = 0; i < bp->cp_nr_rings; i++) {
7688                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7689                 bp->bnapi[i]->in_reset = false;
7690
7691                 if (bp->bnapi[i]->rx_ring) {
7692                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7693                         cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7694                 }
7695                 napi_enable(&bp->bnapi[i]->napi);
7696         }
7697 }
7698
7699 void bnxt_tx_disable(struct bnxt *bp)
7700 {
7701         int i;
7702         struct bnxt_tx_ring_info *txr;
7703
7704         if (bp->tx_ring) {
7705                 for (i = 0; i < bp->tx_nr_rings; i++) {
7706                         txr = &bp->tx_ring[i];
7707                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
7708                 }
7709         }
7710         /* Stop all TX queues */
7711         netif_tx_disable(bp->dev);
7712         netif_carrier_off(bp->dev);
7713 }
7714
7715 void bnxt_tx_enable(struct bnxt *bp)
7716 {
7717         int i;
7718         struct bnxt_tx_ring_info *txr;
7719
7720         for (i = 0; i < bp->tx_nr_rings; i++) {
7721                 txr = &bp->tx_ring[i];
7722                 txr->dev_state = 0;
7723         }
7724         netif_tx_wake_all_queues(bp->dev);
7725         if (bp->link_info.link_up)
7726                 netif_carrier_on(bp->dev);
7727 }
7728
7729 static void bnxt_report_link(struct bnxt *bp)
7730 {
7731         if (bp->link_info.link_up) {
7732                 const char *duplex;
7733                 const char *flow_ctrl;
7734                 u32 speed;
7735                 u16 fec;
7736
7737                 netif_carrier_on(bp->dev);
7738                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7739                         duplex = "full";
7740                 else
7741                         duplex = "half";
7742                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7743                         flow_ctrl = "ON - receive & transmit";
7744                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7745                         flow_ctrl = "ON - transmit";
7746                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7747                         flow_ctrl = "ON - receive";
7748                 else
7749                         flow_ctrl = "none";
7750                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7751                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7752                             speed, duplex, flow_ctrl);
7753                 if (bp->flags & BNXT_FLAG_EEE_CAP)
7754                         netdev_info(bp->dev, "EEE is %s\n",
7755                                     bp->eee.eee_active ? "active" :
7756                                                          "not active");
7757                 fec = bp->link_info.fec_cfg;
7758                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7759                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7760                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7761                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7762                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7763         } else {
7764                 netif_carrier_off(bp->dev);
7765                 netdev_err(bp->dev, "NIC Link is Down\n");
7766         }
7767 }
7768
7769 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7770 {
7771         int rc = 0;
7772         struct hwrm_port_phy_qcaps_input req = {0};
7773         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7774         struct bnxt_link_info *link_info = &bp->link_info;
7775
7776         if (bp->hwrm_spec_code < 0x10201)
7777                 return 0;
7778
7779         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7780
7781         mutex_lock(&bp->hwrm_cmd_lock);
7782         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7783         if (rc)
7784                 goto hwrm_phy_qcaps_exit;
7785
7786         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7787                 struct ethtool_eee *eee = &bp->eee;
7788                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7789
7790                 bp->flags |= BNXT_FLAG_EEE_CAP;
7791                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7792                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7793                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7794                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7795                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7796         }
7797         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7798                 if (bp->test_info)
7799                         bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7800         }
7801         if (resp->supported_speeds_auto_mode)
7802                 link_info->support_auto_speeds =
7803                         le16_to_cpu(resp->supported_speeds_auto_mode);
7804
7805         bp->port_count = resp->port_cnt;
7806
7807 hwrm_phy_qcaps_exit:
7808         mutex_unlock(&bp->hwrm_cmd_lock);
7809         return rc;
7810 }
7811
7812 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7813 {
7814         int rc = 0;
7815         struct bnxt_link_info *link_info = &bp->link_info;
7816         struct hwrm_port_phy_qcfg_input req = {0};
7817         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7818         u8 link_up = link_info->link_up;
7819         u16 diff;
7820
7821         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
7822
7823         mutex_lock(&bp->hwrm_cmd_lock);
7824         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7825         if (rc) {
7826                 mutex_unlock(&bp->hwrm_cmd_lock);
7827                 return rc;
7828         }
7829
7830         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
7831         link_info->phy_link_status = resp->link;
7832         link_info->duplex = resp->duplex_cfg;
7833         if (bp->hwrm_spec_code >= 0x10800)
7834                 link_info->duplex = resp->duplex_state;
7835         link_info->pause = resp->pause;
7836         link_info->auto_mode = resp->auto_mode;
7837         link_info->auto_pause_setting = resp->auto_pause;
7838         link_info->lp_pause = resp->link_partner_adv_pause;
7839         link_info->force_pause_setting = resp->force_pause;
7840         link_info->duplex_setting = resp->duplex_cfg;
7841         if (link_info->phy_link_status == BNXT_LINK_LINK)
7842                 link_info->link_speed = le16_to_cpu(resp->link_speed);
7843         else
7844                 link_info->link_speed = 0;
7845         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
7846         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
7847         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
7848         link_info->lp_auto_link_speeds =
7849                 le16_to_cpu(resp->link_partner_adv_speeds);
7850         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
7851         link_info->phy_ver[0] = resp->phy_maj;
7852         link_info->phy_ver[1] = resp->phy_min;
7853         link_info->phy_ver[2] = resp->phy_bld;
7854         link_info->media_type = resp->media_type;
7855         link_info->phy_type = resp->phy_type;
7856         link_info->transceiver = resp->xcvr_pkg_type;
7857         link_info->phy_addr = resp->eee_config_phy_addr &
7858                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
7859         link_info->module_status = resp->module_status;
7860
7861         if (bp->flags & BNXT_FLAG_EEE_CAP) {
7862                 struct ethtool_eee *eee = &bp->eee;
7863                 u16 fw_speeds;
7864
7865                 eee->eee_active = 0;
7866                 if (resp->eee_config_phy_addr &
7867                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
7868                         eee->eee_active = 1;
7869                         fw_speeds = le16_to_cpu(
7870                                 resp->link_partner_adv_eee_link_speed_mask);
7871                         eee->lp_advertised =
7872                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7873                 }
7874
7875                 /* Pull initial EEE config */
7876                 if (!chng_link_state) {
7877                         if (resp->eee_config_phy_addr &
7878                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
7879                                 eee->eee_enabled = 1;
7880
7881                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
7882                         eee->advertised =
7883                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7884
7885                         if (resp->eee_config_phy_addr &
7886                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
7887                                 __le32 tmr;
7888
7889                                 eee->tx_lpi_enabled = 1;
7890                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
7891                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
7892                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
7893                         }
7894                 }
7895         }
7896
7897         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
7898         if (bp->hwrm_spec_code >= 0x10504)
7899                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
7900
7901         /* TODO: need to add more logic to report VF link */
7902         if (chng_link_state) {
7903                 if (link_info->phy_link_status == BNXT_LINK_LINK)
7904                         link_info->link_up = 1;
7905                 else
7906                         link_info->link_up = 0;
7907                 if (link_up != link_info->link_up)
7908                         bnxt_report_link(bp);
7909         } else {
7910                 /* alwasy link down if not require to update link state */
7911                 link_info->link_up = 0;
7912         }
7913         mutex_unlock(&bp->hwrm_cmd_lock);
7914
7915         if (!BNXT_SINGLE_PF(bp))
7916                 return 0;
7917
7918         diff = link_info->support_auto_speeds ^ link_info->advertising;
7919         if ((link_info->support_auto_speeds | diff) !=
7920             link_info->support_auto_speeds) {
7921                 /* An advertised speed is no longer supported, so we need to
7922                  * update the advertisement settings.  Caller holds RTNL
7923                  * so we can modify link settings.
7924                  */
7925                 link_info->advertising = link_info->support_auto_speeds;
7926                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
7927                         bnxt_hwrm_set_link_setting(bp, true, false);
7928         }
7929         return 0;
7930 }
7931
7932 static void bnxt_get_port_module_status(struct bnxt *bp)
7933 {
7934         struct bnxt_link_info *link_info = &bp->link_info;
7935         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
7936         u8 module_status;
7937
7938         if (bnxt_update_link(bp, true))
7939                 return;
7940
7941         module_status = link_info->module_status;
7942         switch (module_status) {
7943         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
7944         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
7945         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
7946                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
7947                             bp->pf.port_id);
7948                 if (bp->hwrm_spec_code >= 0x10201) {
7949                         netdev_warn(bp->dev, "Module part number %s\n",
7950                                     resp->phy_vendor_partnumber);
7951                 }
7952                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
7953                         netdev_warn(bp->dev, "TX is disabled\n");
7954                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
7955                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
7956         }
7957 }
7958
7959 static void
7960 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
7961 {
7962         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
7963                 if (bp->hwrm_spec_code >= 0x10201)
7964                         req->auto_pause =
7965                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
7966                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7967                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
7968                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
7969                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
7970                 req->enables |=
7971                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7972         } else {
7973                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7974                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
7975                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
7976                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
7977                 req->enables |=
7978                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
7979                 if (bp->hwrm_spec_code >= 0x10201) {
7980                         req->auto_pause = req->force_pause;
7981                         req->enables |= cpu_to_le32(
7982                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7983                 }
7984         }
7985 }
7986
7987 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
7988                                       struct hwrm_port_phy_cfg_input *req)
7989 {
7990         u8 autoneg = bp->link_info.autoneg;
7991         u16 fw_link_speed = bp->link_info.req_link_speed;
7992         u16 advertising = bp->link_info.advertising;
7993
7994         if (autoneg & BNXT_AUTONEG_SPEED) {
7995                 req->auto_mode |=
7996                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
7997
7998                 req->enables |= cpu_to_le32(
7999                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8000                 req->auto_link_speed_mask = cpu_to_le16(advertising);
8001
8002                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8003                 req->flags |=
8004                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8005         } else {
8006                 req->force_link_speed = cpu_to_le16(fw_link_speed);
8007                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8008         }
8009
8010         /* tell chimp that the setting takes effect immediately */
8011         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8012 }
8013
8014 int bnxt_hwrm_set_pause(struct bnxt *bp)
8015 {
8016         struct hwrm_port_phy_cfg_input req = {0};
8017         int rc;
8018
8019         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8020         bnxt_hwrm_set_pause_common(bp, &req);
8021
8022         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8023             bp->link_info.force_link_chng)
8024                 bnxt_hwrm_set_link_common(bp, &req);
8025
8026         mutex_lock(&bp->hwrm_cmd_lock);
8027         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8028         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8029                 /* since changing of pause setting doesn't trigger any link
8030                  * change event, the driver needs to update the current pause
8031                  * result upon successfully return of the phy_cfg command
8032                  */
8033                 bp->link_info.pause =
8034                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8035                 bp->link_info.auto_pause_setting = 0;
8036                 if (!bp->link_info.force_link_chng)
8037                         bnxt_report_link(bp);
8038         }
8039         bp->link_info.force_link_chng = false;
8040         mutex_unlock(&bp->hwrm_cmd_lock);
8041         return rc;
8042 }
8043
8044 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8045                               struct hwrm_port_phy_cfg_input *req)
8046 {
8047         struct ethtool_eee *eee = &bp->eee;
8048
8049         if (eee->eee_enabled) {
8050                 u16 eee_speeds;
8051                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8052
8053                 if (eee->tx_lpi_enabled)
8054                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8055                 else
8056                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8057
8058                 req->flags |= cpu_to_le32(flags);
8059                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8060                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8061                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8062         } else {
8063                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8064         }
8065 }
8066
8067 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8068 {
8069         struct hwrm_port_phy_cfg_input req = {0};
8070
8071         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8072         if (set_pause)
8073                 bnxt_hwrm_set_pause_common(bp, &req);
8074
8075         bnxt_hwrm_set_link_common(bp, &req);
8076
8077         if (set_eee)
8078                 bnxt_hwrm_set_eee(bp, &req);
8079         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8080 }
8081
8082 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8083 {
8084         struct hwrm_port_phy_cfg_input req = {0};
8085
8086         if (!BNXT_SINGLE_PF(bp))
8087                 return 0;
8088
8089         if (pci_num_vf(bp->pdev))
8090                 return 0;
8091
8092         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8093         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8094         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8095 }
8096
8097 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8098 {
8099         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8100         struct hwrm_func_drv_if_change_input req = {0};
8101         bool resc_reinit = false;
8102         int rc;
8103
8104         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8105                 return 0;
8106
8107         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8108         if (up)
8109                 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8110         mutex_lock(&bp->hwrm_cmd_lock);
8111         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8112         if (!rc && (resp->flags &
8113                     cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8114                 resc_reinit = true;
8115         mutex_unlock(&bp->hwrm_cmd_lock);
8116
8117         if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8118                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8119
8120                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8121                 hw_resc->resv_cp_rings = 0;
8122                 hw_resc->resv_stat_ctxs = 0;
8123                 hw_resc->resv_irqs = 0;
8124                 hw_resc->resv_tx_rings = 0;
8125                 hw_resc->resv_rx_rings = 0;
8126                 hw_resc->resv_hw_ring_grps = 0;
8127                 hw_resc->resv_vnics = 0;
8128                 bp->tx_nr_rings = 0;
8129                 bp->rx_nr_rings = 0;
8130         }
8131         return rc;
8132 }
8133
8134 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8135 {
8136         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8137         struct hwrm_port_led_qcaps_input req = {0};
8138         struct bnxt_pf_info *pf = &bp->pf;
8139         int rc;
8140
8141         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8142                 return 0;
8143
8144         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8145         req.port_id = cpu_to_le16(pf->port_id);
8146         mutex_lock(&bp->hwrm_cmd_lock);
8147         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8148         if (rc) {
8149                 mutex_unlock(&bp->hwrm_cmd_lock);
8150                 return rc;
8151         }
8152         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8153                 int i;
8154
8155                 bp->num_leds = resp->num_leds;
8156                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8157                                                  bp->num_leds);
8158                 for (i = 0; i < bp->num_leds; i++) {
8159                         struct bnxt_led_info *led = &bp->leds[i];
8160                         __le16 caps = led->led_state_caps;
8161
8162                         if (!led->led_group_id ||
8163                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
8164                                 bp->num_leds = 0;
8165                                 break;
8166                         }
8167                 }
8168         }
8169         mutex_unlock(&bp->hwrm_cmd_lock);
8170         return 0;
8171 }
8172
8173 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8174 {
8175         struct hwrm_wol_filter_alloc_input req = {0};
8176         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8177         int rc;
8178
8179         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8180         req.port_id = cpu_to_le16(bp->pf.port_id);
8181         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8182         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8183         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8184         mutex_lock(&bp->hwrm_cmd_lock);
8185         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8186         if (!rc)
8187                 bp->wol_filter_id = resp->wol_filter_id;
8188         mutex_unlock(&bp->hwrm_cmd_lock);
8189         return rc;
8190 }
8191
8192 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8193 {
8194         struct hwrm_wol_filter_free_input req = {0};
8195         int rc;
8196
8197         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8198         req.port_id = cpu_to_le16(bp->pf.port_id);
8199         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8200         req.wol_filter_id = bp->wol_filter_id;
8201         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8202         return rc;
8203 }
8204
8205 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8206 {
8207         struct hwrm_wol_filter_qcfg_input req = {0};
8208         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8209         u16 next_handle = 0;
8210         int rc;
8211
8212         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8213         req.port_id = cpu_to_le16(bp->pf.port_id);
8214         req.handle = cpu_to_le16(handle);
8215         mutex_lock(&bp->hwrm_cmd_lock);
8216         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8217         if (!rc) {
8218                 next_handle = le16_to_cpu(resp->next_handle);
8219                 if (next_handle != 0) {
8220                         if (resp->wol_type ==
8221                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8222                                 bp->wol = 1;
8223                                 bp->wol_filter_id = resp->wol_filter_id;
8224                         }
8225                 }
8226         }
8227         mutex_unlock(&bp->hwrm_cmd_lock);
8228         return next_handle;
8229 }
8230
8231 static void bnxt_get_wol_settings(struct bnxt *bp)
8232 {
8233         u16 handle = 0;
8234
8235         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8236                 return;
8237
8238         do {
8239                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8240         } while (handle && handle != 0xffff);
8241 }
8242
8243 #ifdef CONFIG_BNXT_HWMON
8244 static ssize_t bnxt_show_temp(struct device *dev,
8245                               struct device_attribute *devattr, char *buf)
8246 {
8247         struct hwrm_temp_monitor_query_input req = {0};
8248         struct hwrm_temp_monitor_query_output *resp;
8249         struct bnxt *bp = dev_get_drvdata(dev);
8250         u32 temp = 0;
8251
8252         resp = bp->hwrm_cmd_resp_addr;
8253         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8254         mutex_lock(&bp->hwrm_cmd_lock);
8255         if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8256                 temp = resp->temp * 1000; /* display millidegree */
8257         mutex_unlock(&bp->hwrm_cmd_lock);
8258
8259         return sprintf(buf, "%u\n", temp);
8260 }
8261 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8262
8263 static struct attribute *bnxt_attrs[] = {
8264         &sensor_dev_attr_temp1_input.dev_attr.attr,
8265         NULL
8266 };
8267 ATTRIBUTE_GROUPS(bnxt);
8268
8269 static void bnxt_hwmon_close(struct bnxt *bp)
8270 {
8271         if (bp->hwmon_dev) {
8272                 hwmon_device_unregister(bp->hwmon_dev);
8273                 bp->hwmon_dev = NULL;
8274         }
8275 }
8276
8277 static void bnxt_hwmon_open(struct bnxt *bp)
8278 {
8279         struct pci_dev *pdev = bp->pdev;
8280
8281         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8282                                                           DRV_MODULE_NAME, bp,
8283                                                           bnxt_groups);
8284         if (IS_ERR(bp->hwmon_dev)) {
8285                 bp->hwmon_dev = NULL;
8286                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8287         }
8288 }
8289 #else
8290 static void bnxt_hwmon_close(struct bnxt *bp)
8291 {
8292 }
8293
8294 static void bnxt_hwmon_open(struct bnxt *bp)
8295 {
8296 }
8297 #endif
8298
8299 static bool bnxt_eee_config_ok(struct bnxt *bp)
8300 {
8301         struct ethtool_eee *eee = &bp->eee;
8302         struct bnxt_link_info *link_info = &bp->link_info;
8303
8304         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8305                 return true;
8306
8307         if (eee->eee_enabled) {
8308                 u32 advertising =
8309                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8310
8311                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8312                         eee->eee_enabled = 0;
8313                         return false;
8314                 }
8315                 if (eee->advertised & ~advertising) {
8316                         eee->advertised = advertising & eee->supported;
8317                         return false;
8318                 }
8319         }
8320         return true;
8321 }
8322
8323 static int bnxt_update_phy_setting(struct bnxt *bp)
8324 {
8325         int rc;
8326         bool update_link = false;
8327         bool update_pause = false;
8328         bool update_eee = false;
8329         struct bnxt_link_info *link_info = &bp->link_info;
8330
8331         rc = bnxt_update_link(bp, true);
8332         if (rc) {
8333                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8334                            rc);
8335                 return rc;
8336         }
8337         if (!BNXT_SINGLE_PF(bp))
8338                 return 0;
8339
8340         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8341             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8342             link_info->req_flow_ctrl)
8343                 update_pause = true;
8344         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8345             link_info->force_pause_setting != link_info->req_flow_ctrl)
8346                 update_pause = true;
8347         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8348                 if (BNXT_AUTO_MODE(link_info->auto_mode))
8349                         update_link = true;
8350                 if (link_info->req_link_speed != link_info->force_link_speed)
8351                         update_link = true;
8352                 if (link_info->req_duplex != link_info->duplex_setting)
8353                         update_link = true;
8354         } else {
8355                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8356                         update_link = true;
8357                 if (link_info->advertising != link_info->auto_link_speeds)
8358                         update_link = true;
8359         }
8360
8361         /* The last close may have shutdown the link, so need to call
8362          * PHY_CFG to bring it back up.
8363          */
8364         if (!netif_carrier_ok(bp->dev))
8365                 update_link = true;
8366
8367         if (!bnxt_eee_config_ok(bp))
8368                 update_eee = true;
8369
8370         if (update_link)
8371                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8372         else if (update_pause)
8373                 rc = bnxt_hwrm_set_pause(bp);
8374         if (rc) {
8375                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8376                            rc);
8377                 return rc;
8378         }
8379
8380         return rc;
8381 }
8382
8383 /* Common routine to pre-map certain register block to different GRC window.
8384  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8385  * in PF and 3 windows in VF that can be customized to map in different
8386  * register blocks.
8387  */
8388 static void bnxt_preset_reg_win(struct bnxt *bp)
8389 {
8390         if (BNXT_PF(bp)) {
8391                 /* CAG registers map to GRC window #4 */
8392                 writel(BNXT_CAG_REG_BASE,
8393                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8394         }
8395 }
8396
8397 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8398
8399 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8400 {
8401         int rc = 0;
8402
8403         bnxt_preset_reg_win(bp);
8404         netif_carrier_off(bp->dev);
8405         if (irq_re_init) {
8406                 /* Reserve rings now if none were reserved at driver probe. */
8407                 rc = bnxt_init_dflt_ring_mode(bp);
8408                 if (rc) {
8409                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8410                         return rc;
8411                 }
8412         }
8413         rc = bnxt_reserve_rings(bp);
8414         if (rc)
8415                 return rc;
8416         if ((bp->flags & BNXT_FLAG_RFS) &&
8417             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8418                 /* disable RFS if falling back to INTA */
8419                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8420                 bp->flags &= ~BNXT_FLAG_RFS;
8421         }
8422
8423         rc = bnxt_alloc_mem(bp, irq_re_init);
8424         if (rc) {
8425                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8426                 goto open_err_free_mem;
8427         }
8428
8429         if (irq_re_init) {
8430                 bnxt_init_napi(bp);
8431                 rc = bnxt_request_irq(bp);
8432                 if (rc) {
8433                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8434                         goto open_err_irq;
8435                 }
8436         }
8437
8438         bnxt_enable_napi(bp);
8439         bnxt_debug_dev_init(bp);
8440
8441         rc = bnxt_init_nic(bp, irq_re_init);
8442         if (rc) {
8443                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8444                 goto open_err;
8445         }
8446
8447         if (link_re_init) {
8448                 mutex_lock(&bp->link_lock);
8449                 rc = bnxt_update_phy_setting(bp);
8450                 mutex_unlock(&bp->link_lock);
8451                 if (rc) {
8452                         netdev_warn(bp->dev, "failed to update phy settings\n");
8453                         if (BNXT_SINGLE_PF(bp)) {
8454                                 bp->link_info.phy_retry = true;
8455                                 bp->link_info.phy_retry_expires =
8456                                         jiffies + 5 * HZ;
8457                         }
8458                 }
8459         }
8460
8461         if (irq_re_init)
8462                 udp_tunnel_get_rx_info(bp->dev);
8463
8464         set_bit(BNXT_STATE_OPEN, &bp->state);
8465         bnxt_enable_int(bp);
8466         /* Enable TX queues */
8467         bnxt_tx_enable(bp);
8468         mod_timer(&bp->timer, jiffies + bp->current_interval);
8469         /* Poll link status and check for SFP+ module status */
8470         bnxt_get_port_module_status(bp);
8471
8472         /* VF-reps may need to be re-opened after the PF is re-opened */
8473         if (BNXT_PF(bp))
8474                 bnxt_vf_reps_open(bp);
8475         return 0;
8476
8477 open_err:
8478         bnxt_debug_dev_exit(bp);
8479         bnxt_disable_napi(bp);
8480
8481 open_err_irq:
8482         bnxt_del_napi(bp);
8483
8484 open_err_free_mem:
8485         bnxt_free_skbs(bp);
8486         bnxt_free_irq(bp);
8487         bnxt_free_mem(bp, true);
8488         return rc;
8489 }
8490
8491 /* rtnl_lock held */
8492 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8493 {
8494         int rc = 0;
8495
8496         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8497         if (rc) {
8498                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8499                 dev_close(bp->dev);
8500         }
8501         return rc;
8502 }
8503
8504 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8505  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
8506  * self tests.
8507  */
8508 int bnxt_half_open_nic(struct bnxt *bp)
8509 {
8510         int rc = 0;
8511
8512         rc = bnxt_alloc_mem(bp, false);
8513         if (rc) {
8514                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8515                 goto half_open_err;
8516         }
8517         rc = bnxt_init_nic(bp, false);
8518         if (rc) {
8519                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8520                 goto half_open_err;
8521         }
8522         return 0;
8523
8524 half_open_err:
8525         bnxt_free_skbs(bp);
8526         bnxt_free_mem(bp, false);
8527         dev_close(bp->dev);
8528         return rc;
8529 }
8530
8531 /* rtnl_lock held, this call can only be made after a previous successful
8532  * call to bnxt_half_open_nic().
8533  */
8534 void bnxt_half_close_nic(struct bnxt *bp)
8535 {
8536         bnxt_hwrm_resource_free(bp, false, false);
8537         bnxt_free_skbs(bp);
8538         bnxt_free_mem(bp, false);
8539 }
8540
8541 static int bnxt_open(struct net_device *dev)
8542 {
8543         struct bnxt *bp = netdev_priv(dev);
8544         int rc;
8545
8546         bnxt_hwrm_if_change(bp, true);
8547         rc = __bnxt_open_nic(bp, true, true);
8548         if (rc)
8549                 bnxt_hwrm_if_change(bp, false);
8550
8551         bnxt_hwmon_open(bp);
8552
8553         return rc;
8554 }
8555
8556 static bool bnxt_drv_busy(struct bnxt *bp)
8557 {
8558         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8559                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8560 }
8561
8562 static void bnxt_get_ring_stats(struct bnxt *bp,
8563                                 struct rtnl_link_stats64 *stats);
8564
8565 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8566                              bool link_re_init)
8567 {
8568         /* Close the VF-reps before closing PF */
8569         if (BNXT_PF(bp))
8570                 bnxt_vf_reps_close(bp);
8571
8572         /* Change device state to avoid TX queue wake up's */
8573         bnxt_tx_disable(bp);
8574
8575         clear_bit(BNXT_STATE_OPEN, &bp->state);
8576         smp_mb__after_atomic();
8577         while (bnxt_drv_busy(bp))
8578                 msleep(20);
8579
8580         /* Flush rings and and disable interrupts */
8581         bnxt_shutdown_nic(bp, irq_re_init);
8582
8583         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8584
8585         bnxt_debug_dev_exit(bp);
8586         bnxt_disable_napi(bp);
8587         del_timer_sync(&bp->timer);
8588         bnxt_free_skbs(bp);
8589
8590         /* Save ring stats before shutdown */
8591         if (bp->bnapi)
8592                 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8593         if (irq_re_init) {
8594                 bnxt_free_irq(bp);
8595                 bnxt_del_napi(bp);
8596         }
8597         bnxt_free_mem(bp, irq_re_init);
8598 }
8599
8600 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8601 {
8602         int rc = 0;
8603
8604 #ifdef CONFIG_BNXT_SRIOV
8605         if (bp->sriov_cfg) {
8606                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8607                                                       !bp->sriov_cfg,
8608                                                       BNXT_SRIOV_CFG_WAIT_TMO);
8609                 if (rc)
8610                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8611         }
8612 #endif
8613         __bnxt_close_nic(bp, irq_re_init, link_re_init);
8614         return rc;
8615 }
8616
8617 static int bnxt_close(struct net_device *dev)
8618 {
8619         struct bnxt *bp = netdev_priv(dev);
8620
8621         bnxt_hwmon_close(bp);
8622         bnxt_close_nic(bp, true, true);
8623         bnxt_hwrm_shutdown_link(bp);
8624         bnxt_hwrm_if_change(bp, false);
8625         return 0;
8626 }
8627
8628 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
8629                                    u16 *val)
8630 {
8631         struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
8632         struct hwrm_port_phy_mdio_read_input req = {0};
8633         int rc;
8634
8635         if (bp->hwrm_spec_code < 0x10a00)
8636                 return -EOPNOTSUPP;
8637
8638         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
8639         req.port_id = cpu_to_le16(bp->pf.port_id);
8640         req.phy_addr = phy_addr;
8641         req.reg_addr = cpu_to_le16(reg & 0x1f);
8642         if (bp->link_info.support_speeds & BNXT_LINK_SPEED_MSK_10GB) {
8643                 req.cl45_mdio = 1;
8644                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8645                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8646                 req.reg_addr = cpu_to_le16(reg);
8647         }
8648
8649         mutex_lock(&bp->hwrm_cmd_lock);
8650         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8651         if (!rc)
8652                 *val = le16_to_cpu(resp->reg_data);
8653         mutex_unlock(&bp->hwrm_cmd_lock);
8654         return rc;
8655 }
8656
8657 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
8658                                     u16 val)
8659 {
8660         struct hwrm_port_phy_mdio_write_input req = {0};
8661
8662         if (bp->hwrm_spec_code < 0x10a00)
8663                 return -EOPNOTSUPP;
8664
8665         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
8666         req.port_id = cpu_to_le16(bp->pf.port_id);
8667         req.phy_addr = phy_addr;
8668         req.reg_addr = cpu_to_le16(reg & 0x1f);
8669         if (bp->link_info.support_speeds & BNXT_LINK_SPEED_MSK_10GB) {
8670                 req.cl45_mdio = 1;
8671                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8672                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8673                 req.reg_addr = cpu_to_le16(reg);
8674         }
8675         req.reg_data = cpu_to_le16(val);
8676
8677         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8678 }
8679
8680 /* rtnl_lock held */
8681 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8682 {
8683         struct mii_ioctl_data *mdio = if_mii(ifr);
8684         struct bnxt *bp = netdev_priv(dev);
8685         int rc;
8686
8687         switch (cmd) {
8688         case SIOCGMIIPHY:
8689                 mdio->phy_id = bp->link_info.phy_addr;
8690
8691                 /* fallthru */
8692         case SIOCGMIIREG: {
8693                 u16 mii_regval = 0;
8694
8695                 if (!netif_running(dev))
8696                         return -EAGAIN;
8697
8698                 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
8699                                              &mii_regval);
8700                 mdio->val_out = mii_regval;
8701                 return rc;
8702         }
8703
8704         case SIOCSMIIREG:
8705                 if (!netif_running(dev))
8706                         return -EAGAIN;
8707
8708                 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
8709                                                 mdio->val_in);
8710
8711         default:
8712                 /* do nothing */
8713                 break;
8714         }
8715         return -EOPNOTSUPP;
8716 }
8717
8718 static void bnxt_get_ring_stats(struct bnxt *bp,
8719                                 struct rtnl_link_stats64 *stats)
8720 {
8721         int i;
8722
8723
8724         for (i = 0; i < bp->cp_nr_rings; i++) {
8725                 struct bnxt_napi *bnapi = bp->bnapi[i];
8726                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8727                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8728
8729                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8730                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8731                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8732
8733                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8734                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8735                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8736
8737                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8738                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8739                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8740
8741                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8742                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8743                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8744
8745                 stats->rx_missed_errors +=
8746                         le64_to_cpu(hw_stats->rx_discard_pkts);
8747
8748                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8749
8750                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8751         }
8752 }
8753
8754 static void bnxt_add_prev_stats(struct bnxt *bp,
8755                                 struct rtnl_link_stats64 *stats)
8756 {
8757         struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8758
8759         stats->rx_packets += prev_stats->rx_packets;
8760         stats->tx_packets += prev_stats->tx_packets;
8761         stats->rx_bytes += prev_stats->rx_bytes;
8762         stats->tx_bytes += prev_stats->tx_bytes;
8763         stats->rx_missed_errors += prev_stats->rx_missed_errors;
8764         stats->multicast += prev_stats->multicast;
8765         stats->tx_dropped += prev_stats->tx_dropped;
8766 }
8767
8768 static void
8769 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8770 {
8771         struct bnxt *bp = netdev_priv(dev);
8772
8773         set_bit(BNXT_STATE_READ_STATS, &bp->state);
8774         /* Make sure bnxt_close_nic() sees that we are reading stats before
8775          * we check the BNXT_STATE_OPEN flag.
8776          */
8777         smp_mb__after_atomic();
8778         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8779                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8780                 *stats = bp->net_stats_prev;
8781                 return;
8782         }
8783
8784         bnxt_get_ring_stats(bp, stats);
8785         bnxt_add_prev_stats(bp, stats);
8786
8787         if (bp->flags & BNXT_FLAG_PORT_STATS) {
8788                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8789                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8790
8791                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8792                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8793                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8794                                           le64_to_cpu(rx->rx_ovrsz_frames) +
8795                                           le64_to_cpu(rx->rx_runt_frames);
8796                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8797                                    le64_to_cpu(rx->rx_jbr_frames);
8798                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8799                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8800                 stats->tx_errors = le64_to_cpu(tx->tx_err);
8801         }
8802         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8803 }
8804
8805 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8806 {
8807         struct net_device *dev = bp->dev;
8808         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8809         struct netdev_hw_addr *ha;
8810         u8 *haddr;
8811         int mc_count = 0;
8812         bool update = false;
8813         int off = 0;
8814
8815         netdev_for_each_mc_addr(ha, dev) {
8816                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
8817                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8818                         vnic->mc_list_count = 0;
8819                         return false;
8820                 }
8821                 haddr = ha->addr;
8822                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
8823                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
8824                         update = true;
8825                 }
8826                 off += ETH_ALEN;
8827                 mc_count++;
8828         }
8829         if (mc_count)
8830                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
8831
8832         if (mc_count != vnic->mc_list_count) {
8833                 vnic->mc_list_count = mc_count;
8834                 update = true;
8835         }
8836         return update;
8837 }
8838
8839 static bool bnxt_uc_list_updated(struct bnxt *bp)
8840 {
8841         struct net_device *dev = bp->dev;
8842         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8843         struct netdev_hw_addr *ha;
8844         int off = 0;
8845
8846         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
8847                 return true;
8848
8849         netdev_for_each_uc_addr(ha, dev) {
8850                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
8851                         return true;
8852
8853                 off += ETH_ALEN;
8854         }
8855         return false;
8856 }
8857
8858 static void bnxt_set_rx_mode(struct net_device *dev)
8859 {
8860         struct bnxt *bp = netdev_priv(dev);
8861         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8862         u32 mask = vnic->rx_mask;
8863         bool mc_update = false;
8864         bool uc_update;
8865
8866         if (!netif_running(dev))
8867                 return;
8868
8869         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
8870                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
8871                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
8872                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
8873
8874         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
8875                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8876
8877         uc_update = bnxt_uc_list_updated(bp);
8878
8879         if (dev->flags & IFF_BROADCAST)
8880                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8881         if (dev->flags & IFF_ALLMULTI) {
8882                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8883                 vnic->mc_list_count = 0;
8884         } else {
8885                 mc_update = bnxt_mc_list_updated(bp, &mask);
8886         }
8887
8888         if (mask != vnic->rx_mask || uc_update || mc_update) {
8889                 vnic->rx_mask = mask;
8890
8891                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
8892                 bnxt_queue_sp_work(bp);
8893         }
8894 }
8895
8896 static int bnxt_cfg_rx_mode(struct bnxt *bp)
8897 {
8898         struct net_device *dev = bp->dev;
8899         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8900         struct netdev_hw_addr *ha;
8901         int i, off = 0, rc;
8902         bool uc_update;
8903
8904         netif_addr_lock_bh(dev);
8905         uc_update = bnxt_uc_list_updated(bp);
8906         netif_addr_unlock_bh(dev);
8907
8908         if (!uc_update)
8909                 goto skip_uc;
8910
8911         mutex_lock(&bp->hwrm_cmd_lock);
8912         for (i = 1; i < vnic->uc_filter_count; i++) {
8913                 struct hwrm_cfa_l2_filter_free_input req = {0};
8914
8915                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
8916                                        -1);
8917
8918                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
8919
8920                 rc = _hwrm_send_message(bp, &req, sizeof(req),
8921                                         HWRM_CMD_TIMEOUT);
8922         }
8923         mutex_unlock(&bp->hwrm_cmd_lock);
8924
8925         vnic->uc_filter_count = 1;
8926
8927         netif_addr_lock_bh(dev);
8928         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
8929                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8930         } else {
8931                 netdev_for_each_uc_addr(ha, dev) {
8932                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
8933                         off += ETH_ALEN;
8934                         vnic->uc_filter_count++;
8935                 }
8936         }
8937         netif_addr_unlock_bh(dev);
8938
8939         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
8940                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
8941                 if (rc) {
8942                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
8943                                    rc);
8944                         vnic->uc_filter_count = i;
8945                         return rc;
8946                 }
8947         }
8948
8949 skip_uc:
8950         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
8951         if (rc)
8952                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
8953                            rc);
8954
8955         return rc;
8956 }
8957
8958 static bool bnxt_can_reserve_rings(struct bnxt *bp)
8959 {
8960 #ifdef CONFIG_BNXT_SRIOV
8961         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
8962                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8963
8964                 /* No minimum rings were provisioned by the PF.  Don't
8965                  * reserve rings by default when device is down.
8966                  */
8967                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
8968                         return true;
8969
8970                 if (!netif_running(bp->dev))
8971                         return false;
8972         }
8973 #endif
8974         return true;
8975 }
8976
8977 /* If the chip and firmware supports RFS */
8978 static bool bnxt_rfs_supported(struct bnxt *bp)
8979 {
8980         if (bp->flags & BNXT_FLAG_CHIP_P5)
8981                 return false;
8982         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
8983                 return true;
8984         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8985                 return true;
8986         return false;
8987 }
8988
8989 /* If runtime conditions support RFS */
8990 static bool bnxt_rfs_capable(struct bnxt *bp)
8991 {
8992 #ifdef CONFIG_RFS_ACCEL
8993         int vnics, max_vnics, max_rss_ctxs;
8994
8995         if (bp->flags & BNXT_FLAG_CHIP_P5)
8996                 return false;
8997         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
8998                 return false;
8999
9000         vnics = 1 + bp->rx_nr_rings;
9001         max_vnics = bnxt_get_max_func_vnics(bp);
9002         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9003
9004         /* RSS contexts not a limiting factor */
9005         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9006                 max_rss_ctxs = max_vnics;
9007         if (vnics > max_vnics || vnics > max_rss_ctxs) {
9008                 if (bp->rx_nr_rings > 1)
9009                         netdev_warn(bp->dev,
9010                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9011                                     min(max_rss_ctxs - 1, max_vnics - 1));
9012                 return false;
9013         }
9014
9015         if (!BNXT_NEW_RM(bp))
9016                 return true;
9017
9018         if (vnics == bp->hw_resc.resv_vnics)
9019                 return true;
9020
9021         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9022         if (vnics <= bp->hw_resc.resv_vnics)
9023                 return true;
9024
9025         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9026         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9027         return false;
9028 #else
9029         return false;
9030 #endif
9031 }
9032
9033 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9034                                            netdev_features_t features)
9035 {
9036         struct bnxt *bp = netdev_priv(dev);
9037
9038         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9039                 features &= ~NETIF_F_NTUPLE;
9040
9041         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9042                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9043
9044         if (!(features & NETIF_F_GRO))
9045                 features &= ~NETIF_F_GRO_HW;
9046
9047         if (features & NETIF_F_GRO_HW)
9048                 features &= ~NETIF_F_LRO;
9049
9050         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
9051          * turned on or off together.
9052          */
9053         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
9054             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
9055                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9056                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9057                                       NETIF_F_HW_VLAN_STAG_RX);
9058                 else
9059                         features |= NETIF_F_HW_VLAN_CTAG_RX |
9060                                     NETIF_F_HW_VLAN_STAG_RX;
9061         }
9062 #ifdef CONFIG_BNXT_SRIOV
9063         if (BNXT_VF(bp)) {
9064                 if (bp->vf.vlan) {
9065                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9066                                       NETIF_F_HW_VLAN_STAG_RX);
9067                 }
9068         }
9069 #endif
9070         return features;
9071 }
9072
9073 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9074 {
9075         struct bnxt *bp = netdev_priv(dev);
9076         u32 flags = bp->flags;
9077         u32 changes;
9078         int rc = 0;
9079         bool re_init = false;
9080         bool update_tpa = false;
9081
9082         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9083         if (features & NETIF_F_GRO_HW)
9084                 flags |= BNXT_FLAG_GRO;
9085         else if (features & NETIF_F_LRO)
9086                 flags |= BNXT_FLAG_LRO;
9087
9088         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9089                 flags &= ~BNXT_FLAG_TPA;
9090
9091         if (features & NETIF_F_HW_VLAN_CTAG_RX)
9092                 flags |= BNXT_FLAG_STRIP_VLAN;
9093
9094         if (features & NETIF_F_NTUPLE)
9095                 flags |= BNXT_FLAG_RFS;
9096
9097         changes = flags ^ bp->flags;
9098         if (changes & BNXT_FLAG_TPA) {
9099                 update_tpa = true;
9100                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9101                     (flags & BNXT_FLAG_TPA) == 0)
9102                         re_init = true;
9103         }
9104
9105         if (changes & ~BNXT_FLAG_TPA)
9106                 re_init = true;
9107
9108         if (flags != bp->flags) {
9109                 u32 old_flags = bp->flags;
9110
9111                 bp->flags = flags;
9112
9113                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9114                         if (update_tpa)
9115                                 bnxt_set_ring_params(bp);
9116                         return rc;
9117                 }
9118
9119                 if (re_init) {
9120                         bnxt_close_nic(bp, false, false);
9121                         if (update_tpa)
9122                                 bnxt_set_ring_params(bp);
9123
9124                         return bnxt_open_nic(bp, false, false);
9125                 }
9126                 if (update_tpa) {
9127                         rc = bnxt_set_tpa(bp,
9128                                           (flags & BNXT_FLAG_TPA) ?
9129                                           true : false);
9130                         if (rc)
9131                                 bp->flags = old_flags;
9132                 }
9133         }
9134         return rc;
9135 }
9136
9137 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9138                                        u32 ring_id, u32 *prod, u32 *cons)
9139 {
9140         struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9141         struct hwrm_dbg_ring_info_get_input req = {0};
9142         int rc;
9143
9144         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9145         req.ring_type = ring_type;
9146         req.fw_ring_id = cpu_to_le32(ring_id);
9147         mutex_lock(&bp->hwrm_cmd_lock);
9148         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9149         if (!rc) {
9150                 *prod = le32_to_cpu(resp->producer_index);
9151                 *cons = le32_to_cpu(resp->consumer_index);
9152         }
9153         mutex_unlock(&bp->hwrm_cmd_lock);
9154         return rc;
9155 }
9156
9157 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9158 {
9159         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9160         int i = bnapi->index;
9161
9162         if (!txr)
9163                 return;
9164
9165         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9166                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9167                     txr->tx_cons);
9168 }
9169
9170 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9171 {
9172         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9173         int i = bnapi->index;
9174
9175         if (!rxr)
9176                 return;
9177
9178         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9179                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9180                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9181                     rxr->rx_sw_agg_prod);
9182 }
9183
9184 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9185 {
9186         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9187         int i = bnapi->index;
9188
9189         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9190                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9191 }
9192
9193 static void bnxt_dbg_dump_states(struct bnxt *bp)
9194 {
9195         int i;
9196         struct bnxt_napi *bnapi;
9197
9198         for (i = 0; i < bp->cp_nr_rings; i++) {
9199                 bnapi = bp->bnapi[i];
9200                 if (netif_msg_drv(bp)) {
9201                         bnxt_dump_tx_sw_state(bnapi);
9202                         bnxt_dump_rx_sw_state(bnapi);
9203                         bnxt_dump_cp_sw_state(bnapi);
9204                 }
9205         }
9206 }
9207
9208 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9209 {
9210         if (!silent)
9211                 bnxt_dbg_dump_states(bp);
9212         if (netif_running(bp->dev)) {
9213                 int rc;
9214
9215                 if (!silent)
9216                         bnxt_ulp_stop(bp);
9217                 bnxt_close_nic(bp, false, false);
9218                 rc = bnxt_open_nic(bp, false, false);
9219                 if (!silent && !rc)
9220                         bnxt_ulp_start(bp);
9221         }
9222 }
9223
9224 static void bnxt_tx_timeout(struct net_device *dev)
9225 {
9226         struct bnxt *bp = netdev_priv(dev);
9227
9228         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
9229         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9230         bnxt_queue_sp_work(bp);
9231 }
9232
9233 static void bnxt_timer(struct timer_list *t)
9234 {
9235         struct bnxt *bp = from_timer(bp, t, timer);
9236         struct net_device *dev = bp->dev;
9237
9238         if (!netif_running(dev))
9239                 return;
9240
9241         if (atomic_read(&bp->intr_sem) != 0)
9242                 goto bnxt_restart_timer;
9243
9244         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9245             bp->stats_coal_ticks) {
9246                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9247                 bnxt_queue_sp_work(bp);
9248         }
9249
9250         if (bnxt_tc_flower_enabled(bp)) {
9251                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9252                 bnxt_queue_sp_work(bp);
9253         }
9254
9255         if (bp->link_info.phy_retry) {
9256                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9257                         bp->link_info.phy_retry = 0;
9258                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9259                 } else {
9260                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9261                         bnxt_queue_sp_work(bp);
9262                 }
9263         }
9264
9265         if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9266                 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9267                 bnxt_queue_sp_work(bp);
9268         }
9269 bnxt_restart_timer:
9270         mod_timer(&bp->timer, jiffies + bp->current_interval);
9271 }
9272
9273 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9274 {
9275         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9276          * set.  If the device is being closed, bnxt_close() may be holding
9277          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
9278          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9279          */
9280         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9281         rtnl_lock();
9282 }
9283
9284 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9285 {
9286         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9287         rtnl_unlock();
9288 }
9289
9290 /* Only called from bnxt_sp_task() */
9291 static void bnxt_reset(struct bnxt *bp, bool silent)
9292 {
9293         bnxt_rtnl_lock_sp(bp);
9294         if (test_bit(BNXT_STATE_OPEN, &bp->state))
9295                 bnxt_reset_task(bp, silent);
9296         bnxt_rtnl_unlock_sp(bp);
9297 }
9298
9299 static void bnxt_chk_missed_irq(struct bnxt *bp)
9300 {
9301         int i;
9302
9303         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9304                 return;
9305
9306         for (i = 0; i < bp->cp_nr_rings; i++) {
9307                 struct bnxt_napi *bnapi = bp->bnapi[i];
9308                 struct bnxt_cp_ring_info *cpr;
9309                 u32 fw_ring_id;
9310                 int j;
9311
9312                 if (!bnapi)
9313                         continue;
9314
9315                 cpr = &bnapi->cp_ring;
9316                 for (j = 0; j < 2; j++) {
9317                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9318                         u32 val[2];
9319
9320                         if (!cpr2 || cpr2->has_more_work ||
9321                             !bnxt_has_work(bp, cpr2))
9322                                 continue;
9323
9324                         if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9325                                 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9326                                 continue;
9327                         }
9328                         fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9329                         bnxt_dbg_hwrm_ring_info_get(bp,
9330                                 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9331                                 fw_ring_id, &val[0], &val[1]);
9332                         cpr->missed_irqs++;
9333                 }
9334         }
9335 }
9336
9337 static void bnxt_cfg_ntp_filters(struct bnxt *);
9338
9339 static void bnxt_sp_task(struct work_struct *work)
9340 {
9341         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9342
9343         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9344         smp_mb__after_atomic();
9345         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9346                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9347                 return;
9348         }
9349
9350         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9351                 bnxt_cfg_rx_mode(bp);
9352
9353         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9354                 bnxt_cfg_ntp_filters(bp);
9355         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9356                 bnxt_hwrm_exec_fwd_req(bp);
9357         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9358                 bnxt_hwrm_tunnel_dst_port_alloc(
9359                         bp, bp->vxlan_port,
9360                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9361         }
9362         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9363                 bnxt_hwrm_tunnel_dst_port_free(
9364                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9365         }
9366         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9367                 bnxt_hwrm_tunnel_dst_port_alloc(
9368                         bp, bp->nge_port,
9369                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9370         }
9371         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9372                 bnxt_hwrm_tunnel_dst_port_free(
9373                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9374         }
9375         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9376                 bnxt_hwrm_port_qstats(bp);
9377                 bnxt_hwrm_port_qstats_ext(bp);
9378         }
9379
9380         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9381                 int rc;
9382
9383                 mutex_lock(&bp->link_lock);
9384                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9385                                        &bp->sp_event))
9386                         bnxt_hwrm_phy_qcaps(bp);
9387
9388                 rc = bnxt_update_link(bp, true);
9389                 mutex_unlock(&bp->link_lock);
9390                 if (rc)
9391                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9392                                    rc);
9393         }
9394         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9395                 int rc;
9396
9397                 mutex_lock(&bp->link_lock);
9398                 rc = bnxt_update_phy_setting(bp);
9399                 mutex_unlock(&bp->link_lock);
9400                 if (rc) {
9401                         netdev_warn(bp->dev, "update phy settings retry failed\n");
9402                 } else {
9403                         bp->link_info.phy_retry = false;
9404                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
9405                 }
9406         }
9407         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9408                 mutex_lock(&bp->link_lock);
9409                 bnxt_get_port_module_status(bp);
9410                 mutex_unlock(&bp->link_lock);
9411         }
9412
9413         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9414                 bnxt_tc_flow_stats_work(bp);
9415
9416         if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9417                 bnxt_chk_missed_irq(bp);
9418
9419         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
9420          * must be the last functions to be called before exiting.
9421          */
9422         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9423                 bnxt_reset(bp, false);
9424
9425         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9426                 bnxt_reset(bp, true);
9427
9428         smp_mb__before_atomic();
9429         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9430 }
9431
9432 /* Under rtnl_lock */
9433 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9434                      int tx_xdp)
9435 {
9436         int max_rx, max_tx, tx_sets = 1;
9437         int tx_rings_needed, stats;
9438         int rx_rings = rx;
9439         int cp, vnics, rc;
9440
9441         if (tcs)
9442                 tx_sets = tcs;
9443
9444         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9445         if (rc)
9446                 return rc;
9447
9448         if (max_rx < rx)
9449                 return -ENOMEM;
9450
9451         tx_rings_needed = tx * tx_sets + tx_xdp;
9452         if (max_tx < tx_rings_needed)
9453                 return -ENOMEM;
9454
9455         vnics = 1;
9456         if (bp->flags & BNXT_FLAG_RFS)
9457                 vnics += rx_rings;
9458
9459         if (bp->flags & BNXT_FLAG_AGG_RINGS)
9460                 rx_rings <<= 1;
9461         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9462         stats = cp;
9463         if (BNXT_NEW_RM(bp)) {
9464                 cp += bnxt_get_ulp_msix_num(bp);
9465                 stats += bnxt_get_ulp_stat_ctxs(bp);
9466         }
9467         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9468                                      stats, vnics);
9469 }
9470
9471 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9472 {
9473         if (bp->bar2) {
9474                 pci_iounmap(pdev, bp->bar2);
9475                 bp->bar2 = NULL;
9476         }
9477
9478         if (bp->bar1) {
9479                 pci_iounmap(pdev, bp->bar1);
9480                 bp->bar1 = NULL;
9481         }
9482
9483         if (bp->bar0) {
9484                 pci_iounmap(pdev, bp->bar0);
9485                 bp->bar0 = NULL;
9486         }
9487 }
9488
9489 static void bnxt_cleanup_pci(struct bnxt *bp)
9490 {
9491         bnxt_unmap_bars(bp, bp->pdev);
9492         pci_release_regions(bp->pdev);
9493         pci_disable_device(bp->pdev);
9494 }
9495
9496 static void bnxt_init_dflt_coal(struct bnxt *bp)
9497 {
9498         struct bnxt_coal *coal;
9499
9500         /* Tick values in micro seconds.
9501          * 1 coal_buf x bufs_per_record = 1 completion record.
9502          */
9503         coal = &bp->rx_coal;
9504         coal->coal_ticks = 10;
9505         coal->coal_bufs = 30;
9506         coal->coal_ticks_irq = 1;
9507         coal->coal_bufs_irq = 2;
9508         coal->idle_thresh = 50;
9509         coal->bufs_per_record = 2;
9510         coal->budget = 64;              /* NAPI budget */
9511
9512         coal = &bp->tx_coal;
9513         coal->coal_ticks = 28;
9514         coal->coal_bufs = 30;
9515         coal->coal_ticks_irq = 2;
9516         coal->coal_bufs_irq = 2;
9517         coal->bufs_per_record = 1;
9518
9519         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9520 }
9521
9522 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9523 {
9524         int rc;
9525         struct bnxt *bp = netdev_priv(dev);
9526
9527         SET_NETDEV_DEV(dev, &pdev->dev);
9528
9529         /* enable device (incl. PCI PM wakeup), and bus-mastering */
9530         rc = pci_enable_device(pdev);
9531         if (rc) {
9532                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9533                 goto init_err;
9534         }
9535
9536         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9537                 dev_err(&pdev->dev,
9538                         "Cannot find PCI device base address, aborting\n");
9539                 rc = -ENODEV;
9540                 goto init_err_disable;
9541         }
9542
9543         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9544         if (rc) {
9545                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9546                 goto init_err_disable;
9547         }
9548
9549         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9550             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9551                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9552                 goto init_err_disable;
9553         }
9554
9555         pci_set_master(pdev);
9556
9557         bp->dev = dev;
9558         bp->pdev = pdev;
9559
9560         bp->bar0 = pci_ioremap_bar(pdev, 0);
9561         if (!bp->bar0) {
9562                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9563                 rc = -ENOMEM;
9564                 goto init_err_release;
9565         }
9566
9567         bp->bar1 = pci_ioremap_bar(pdev, 2);
9568         if (!bp->bar1) {
9569                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9570                 rc = -ENOMEM;
9571                 goto init_err_release;
9572         }
9573
9574         bp->bar2 = pci_ioremap_bar(pdev, 4);
9575         if (!bp->bar2) {
9576                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9577                 rc = -ENOMEM;
9578                 goto init_err_release;
9579         }
9580
9581         pci_enable_pcie_error_reporting(pdev);
9582
9583         INIT_WORK(&bp->sp_task, bnxt_sp_task);
9584
9585         spin_lock_init(&bp->ntp_fltr_lock);
9586 #if BITS_PER_LONG == 32
9587         spin_lock_init(&bp->db_lock);
9588 #endif
9589
9590         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9591         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9592
9593         bnxt_init_dflt_coal(bp);
9594
9595         timer_setup(&bp->timer, bnxt_timer, 0);
9596         bp->current_interval = BNXT_TIMER_INTERVAL;
9597
9598         clear_bit(BNXT_STATE_OPEN, &bp->state);
9599         return 0;
9600
9601 init_err_release:
9602         bnxt_unmap_bars(bp, pdev);
9603         pci_release_regions(pdev);
9604
9605 init_err_disable:
9606         pci_disable_device(pdev);
9607
9608 init_err:
9609         return rc;
9610 }
9611
9612 /* rtnl_lock held */
9613 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9614 {
9615         struct sockaddr *addr = p;
9616         struct bnxt *bp = netdev_priv(dev);
9617         int rc = 0;
9618
9619         if (!is_valid_ether_addr(addr->sa_data))
9620                 return -EADDRNOTAVAIL;
9621
9622         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9623                 return 0;
9624
9625         rc = bnxt_approve_mac(bp, addr->sa_data, true);
9626         if (rc)
9627                 return rc;
9628
9629         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9630         if (netif_running(dev)) {
9631                 bnxt_close_nic(bp, false, false);
9632                 rc = bnxt_open_nic(bp, false, false);
9633         }
9634
9635         return rc;
9636 }
9637
9638 /* rtnl_lock held */
9639 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9640 {
9641         struct bnxt *bp = netdev_priv(dev);
9642
9643         if (netif_running(dev))
9644                 bnxt_close_nic(bp, false, false);
9645
9646         dev->mtu = new_mtu;
9647         bnxt_set_ring_params(bp);
9648
9649         if (netif_running(dev))
9650                 return bnxt_open_nic(bp, false, false);
9651
9652         return 0;
9653 }
9654
9655 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9656 {
9657         struct bnxt *bp = netdev_priv(dev);
9658         bool sh = false;
9659         int rc;
9660
9661         if (tc > bp->max_tc) {
9662                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9663                            tc, bp->max_tc);
9664                 return -EINVAL;
9665         }
9666
9667         if (netdev_get_num_tc(dev) == tc)
9668                 return 0;
9669
9670         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9671                 sh = true;
9672
9673         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9674                               sh, tc, bp->tx_nr_rings_xdp);
9675         if (rc)
9676                 return rc;
9677
9678         /* Needs to close the device and do hw resource re-allocations */
9679         if (netif_running(bp->dev))
9680                 bnxt_close_nic(bp, true, false);
9681
9682         if (tc) {
9683                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9684                 netdev_set_num_tc(dev, tc);
9685         } else {
9686                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9687                 netdev_reset_tc(dev);
9688         }
9689         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9690         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9691                                bp->tx_nr_rings + bp->rx_nr_rings;
9692
9693         if (netif_running(bp->dev))
9694                 return bnxt_open_nic(bp, true, false);
9695
9696         return 0;
9697 }
9698
9699 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9700                                   void *cb_priv)
9701 {
9702         struct bnxt *bp = cb_priv;
9703
9704         if (!bnxt_tc_flower_enabled(bp) ||
9705             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9706                 return -EOPNOTSUPP;
9707
9708         switch (type) {
9709         case TC_SETUP_CLSFLOWER:
9710                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9711         default:
9712                 return -EOPNOTSUPP;
9713         }
9714 }
9715
9716 static int bnxt_setup_tc_block(struct net_device *dev,
9717                                struct tc_block_offload *f)
9718 {
9719         struct bnxt *bp = netdev_priv(dev);
9720
9721         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9722                 return -EOPNOTSUPP;
9723
9724         switch (f->command) {
9725         case TC_BLOCK_BIND:
9726                 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
9727                                              bp, bp, f->extack);
9728         case TC_BLOCK_UNBIND:
9729                 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
9730                 return 0;
9731         default:
9732                 return -EOPNOTSUPP;
9733         }
9734 }
9735
9736 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9737                          void *type_data)
9738 {
9739         switch (type) {
9740         case TC_SETUP_BLOCK:
9741                 return bnxt_setup_tc_block(dev, type_data);
9742         case TC_SETUP_QDISC_MQPRIO: {
9743                 struct tc_mqprio_qopt *mqprio = type_data;
9744
9745                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9746
9747                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9748         }
9749         default:
9750                 return -EOPNOTSUPP;
9751         }
9752 }
9753
9754 #ifdef CONFIG_RFS_ACCEL
9755 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9756                             struct bnxt_ntuple_filter *f2)
9757 {
9758         struct flow_keys *keys1 = &f1->fkeys;
9759         struct flow_keys *keys2 = &f2->fkeys;
9760
9761         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9762             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9763             keys1->ports.ports == keys2->ports.ports &&
9764             keys1->basic.ip_proto == keys2->basic.ip_proto &&
9765             keys1->basic.n_proto == keys2->basic.n_proto &&
9766             keys1->control.flags == keys2->control.flags &&
9767             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9768             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9769                 return true;
9770
9771         return false;
9772 }
9773
9774 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9775                               u16 rxq_index, u32 flow_id)
9776 {
9777         struct bnxt *bp = netdev_priv(dev);
9778         struct bnxt_ntuple_filter *fltr, *new_fltr;
9779         struct flow_keys *fkeys;
9780         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9781         int rc = 0, idx, bit_id, l2_idx = 0;
9782         struct hlist_head *head;
9783
9784         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9785                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9786                 int off = 0, j;
9787
9788                 netif_addr_lock_bh(dev);
9789                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9790                         if (ether_addr_equal(eth->h_dest,
9791                                              vnic->uc_list + off)) {
9792                                 l2_idx = j + 1;
9793                                 break;
9794                         }
9795                 }
9796                 netif_addr_unlock_bh(dev);
9797                 if (!l2_idx)
9798                         return -EINVAL;
9799         }
9800         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9801         if (!new_fltr)
9802                 return -ENOMEM;
9803
9804         fkeys = &new_fltr->fkeys;
9805         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
9806                 rc = -EPROTONOSUPPORT;
9807                 goto err_free;
9808         }
9809
9810         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
9811              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
9812             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
9813              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
9814                 rc = -EPROTONOSUPPORT;
9815                 goto err_free;
9816         }
9817         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
9818             bp->hwrm_spec_code < 0x10601) {
9819                 rc = -EPROTONOSUPPORT;
9820                 goto err_free;
9821         }
9822         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
9823             bp->hwrm_spec_code < 0x10601) {
9824                 rc = -EPROTONOSUPPORT;
9825                 goto err_free;
9826         }
9827
9828         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
9829         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
9830
9831         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
9832         head = &bp->ntp_fltr_hash_tbl[idx];
9833         rcu_read_lock();
9834         hlist_for_each_entry_rcu(fltr, head, hash) {
9835                 if (bnxt_fltr_match(fltr, new_fltr)) {
9836                         rcu_read_unlock();
9837                         rc = 0;
9838                         goto err_free;
9839                 }
9840         }
9841         rcu_read_unlock();
9842
9843         spin_lock_bh(&bp->ntp_fltr_lock);
9844         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
9845                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
9846         if (bit_id < 0) {
9847                 spin_unlock_bh(&bp->ntp_fltr_lock);
9848                 rc = -ENOMEM;
9849                 goto err_free;
9850         }
9851
9852         new_fltr->sw_id = (u16)bit_id;
9853         new_fltr->flow_id = flow_id;
9854         new_fltr->l2_fltr_idx = l2_idx;
9855         new_fltr->rxq = rxq_index;
9856         hlist_add_head_rcu(&new_fltr->hash, head);
9857         bp->ntp_fltr_count++;
9858         spin_unlock_bh(&bp->ntp_fltr_lock);
9859
9860         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
9861         bnxt_queue_sp_work(bp);
9862
9863         return new_fltr->sw_id;
9864
9865 err_free:
9866         kfree(new_fltr);
9867         return rc;
9868 }
9869
9870 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9871 {
9872         int i;
9873
9874         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
9875                 struct hlist_head *head;
9876                 struct hlist_node *tmp;
9877                 struct bnxt_ntuple_filter *fltr;
9878                 int rc;
9879
9880                 head = &bp->ntp_fltr_hash_tbl[i];
9881                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
9882                         bool del = false;
9883
9884                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
9885                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
9886                                                         fltr->flow_id,
9887                                                         fltr->sw_id)) {
9888                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
9889                                                                          fltr);
9890                                         del = true;
9891                                 }
9892                         } else {
9893                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
9894                                                                        fltr);
9895                                 if (rc)
9896                                         del = true;
9897                                 else
9898                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
9899                         }
9900
9901                         if (del) {
9902                                 spin_lock_bh(&bp->ntp_fltr_lock);
9903                                 hlist_del_rcu(&fltr->hash);
9904                                 bp->ntp_fltr_count--;
9905                                 spin_unlock_bh(&bp->ntp_fltr_lock);
9906                                 synchronize_rcu();
9907                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
9908                                 kfree(fltr);
9909                         }
9910                 }
9911         }
9912         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
9913                 netdev_info(bp->dev, "Receive PF driver unload event!");
9914 }
9915
9916 #else
9917
9918 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9919 {
9920 }
9921
9922 #endif /* CONFIG_RFS_ACCEL */
9923
9924 static void bnxt_udp_tunnel_add(struct net_device *dev,
9925                                 struct udp_tunnel_info *ti)
9926 {
9927         struct bnxt *bp = netdev_priv(dev);
9928
9929         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
9930                 return;
9931
9932         if (!netif_running(dev))
9933                 return;
9934
9935         switch (ti->type) {
9936         case UDP_TUNNEL_TYPE_VXLAN:
9937                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
9938                         return;
9939
9940                 bp->vxlan_port_cnt++;
9941                 if (bp->vxlan_port_cnt == 1) {
9942                         bp->vxlan_port = ti->port;
9943                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
9944                         bnxt_queue_sp_work(bp);
9945                 }
9946                 break;
9947         case UDP_TUNNEL_TYPE_GENEVE:
9948                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
9949                         return;
9950
9951                 bp->nge_port_cnt++;
9952                 if (bp->nge_port_cnt == 1) {
9953                         bp->nge_port = ti->port;
9954                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
9955                 }
9956                 break;
9957         default:
9958                 return;
9959         }
9960
9961         bnxt_queue_sp_work(bp);
9962 }
9963
9964 static void bnxt_udp_tunnel_del(struct net_device *dev,
9965                                 struct udp_tunnel_info *ti)
9966 {
9967         struct bnxt *bp = netdev_priv(dev);
9968
9969         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
9970                 return;
9971
9972         if (!netif_running(dev))
9973                 return;
9974
9975         switch (ti->type) {
9976         case UDP_TUNNEL_TYPE_VXLAN:
9977                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
9978                         return;
9979                 bp->vxlan_port_cnt--;
9980
9981                 if (bp->vxlan_port_cnt != 0)
9982                         return;
9983
9984                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
9985                 break;
9986         case UDP_TUNNEL_TYPE_GENEVE:
9987                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
9988                         return;
9989                 bp->nge_port_cnt--;
9990
9991                 if (bp->nge_port_cnt != 0)
9992                         return;
9993
9994                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
9995                 break;
9996         default:
9997                 return;
9998         }
9999
10000         bnxt_queue_sp_work(bp);
10001 }
10002
10003 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10004                                struct net_device *dev, u32 filter_mask,
10005                                int nlflags)
10006 {
10007         struct bnxt *bp = netdev_priv(dev);
10008
10009         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
10010                                        nlflags, filter_mask, NULL);
10011 }
10012
10013 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
10014                                u16 flags, struct netlink_ext_ack *extack)
10015 {
10016         struct bnxt *bp = netdev_priv(dev);
10017         struct nlattr *attr, *br_spec;
10018         int rem, rc = 0;
10019
10020         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
10021                 return -EOPNOTSUPP;
10022
10023         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10024         if (!br_spec)
10025                 return -EINVAL;
10026
10027         nla_for_each_nested(attr, br_spec, rem) {
10028                 u16 mode;
10029
10030                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
10031                         continue;
10032
10033                 if (nla_len(attr) < sizeof(mode))
10034                         return -EINVAL;
10035
10036                 mode = nla_get_u16(attr);
10037                 if (mode == bp->br_mode)
10038                         break;
10039
10040                 rc = bnxt_hwrm_set_br_mode(bp, mode);
10041                 if (!rc)
10042                         bp->br_mode = mode;
10043                 break;
10044         }
10045         return rc;
10046 }
10047
10048 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
10049                                    size_t len)
10050 {
10051         struct bnxt *bp = netdev_priv(dev);
10052         int rc;
10053
10054         /* The PF and it's VF-reps only support the switchdev framework */
10055         if (!BNXT_PF(bp))
10056                 return -EOPNOTSUPP;
10057
10058         rc = snprintf(buf, len, "p%d", bp->pf.port_id);
10059
10060         if (rc >= len)
10061                 return -EOPNOTSUPP;
10062         return 0;
10063 }
10064
10065 int bnxt_get_port_parent_id(struct net_device *dev,
10066                             struct netdev_phys_item_id *ppid)
10067 {
10068         struct bnxt *bp = netdev_priv(dev);
10069
10070         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
10071                 return -EOPNOTSUPP;
10072
10073         /* The PF and it's VF-reps only support the switchdev framework */
10074         if (!BNXT_PF(bp))
10075                 return -EOPNOTSUPP;
10076
10077         ppid->id_len = sizeof(bp->switch_id);
10078         memcpy(ppid->id, bp->switch_id, ppid->id_len);
10079
10080         return 0;
10081 }
10082
10083 static const struct net_device_ops bnxt_netdev_ops = {
10084         .ndo_open               = bnxt_open,
10085         .ndo_start_xmit         = bnxt_start_xmit,
10086         .ndo_stop               = bnxt_close,
10087         .ndo_get_stats64        = bnxt_get_stats64,
10088         .ndo_set_rx_mode        = bnxt_set_rx_mode,
10089         .ndo_do_ioctl           = bnxt_ioctl,
10090         .ndo_validate_addr      = eth_validate_addr,
10091         .ndo_set_mac_address    = bnxt_change_mac_addr,
10092         .ndo_change_mtu         = bnxt_change_mtu,
10093         .ndo_fix_features       = bnxt_fix_features,
10094         .ndo_set_features       = bnxt_set_features,
10095         .ndo_tx_timeout         = bnxt_tx_timeout,
10096 #ifdef CONFIG_BNXT_SRIOV
10097         .ndo_get_vf_config      = bnxt_get_vf_config,
10098         .ndo_set_vf_mac         = bnxt_set_vf_mac,
10099         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
10100         .ndo_set_vf_rate        = bnxt_set_vf_bw,
10101         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
10102         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
10103         .ndo_set_vf_trust       = bnxt_set_vf_trust,
10104 #endif
10105         .ndo_setup_tc           = bnxt_setup_tc,
10106 #ifdef CONFIG_RFS_ACCEL
10107         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
10108 #endif
10109         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
10110         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
10111         .ndo_bpf                = bnxt_xdp,
10112         .ndo_bridge_getlink     = bnxt_bridge_getlink,
10113         .ndo_bridge_setlink     = bnxt_bridge_setlink,
10114         .ndo_get_port_parent_id = bnxt_get_port_parent_id,
10115         .ndo_get_phys_port_name = bnxt_get_phys_port_name
10116 };
10117
10118 static void bnxt_remove_one(struct pci_dev *pdev)
10119 {
10120         struct net_device *dev = pci_get_drvdata(pdev);
10121         struct bnxt *bp = netdev_priv(dev);
10122
10123         if (BNXT_PF(bp)) {
10124                 bnxt_sriov_disable(bp);
10125                 bnxt_dl_unregister(bp);
10126         }
10127
10128         pci_disable_pcie_error_reporting(pdev);
10129         unregister_netdev(dev);
10130         bnxt_shutdown_tc(bp);
10131         bnxt_cancel_sp_work(bp);
10132         bp->sp_event = 0;
10133
10134         bnxt_clear_int_mode(bp);
10135         bnxt_hwrm_func_drv_unrgtr(bp);
10136         bnxt_free_hwrm_resources(bp);
10137         bnxt_free_hwrm_short_cmd_req(bp);
10138         bnxt_ethtool_free(bp);
10139         bnxt_dcb_free(bp);
10140         kfree(bp->edev);
10141         bp->edev = NULL;
10142         bnxt_free_ctx_mem(bp);
10143         kfree(bp->ctx);
10144         bp->ctx = NULL;
10145         bnxt_cleanup_pci(bp);
10146         bnxt_free_port_stats(bp);
10147         free_netdev(dev);
10148 }
10149
10150 static int bnxt_probe_phy(struct bnxt *bp)
10151 {
10152         int rc = 0;
10153         struct bnxt_link_info *link_info = &bp->link_info;
10154
10155         rc = bnxt_hwrm_phy_qcaps(bp);
10156         if (rc) {
10157                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10158                            rc);
10159                 return rc;
10160         }
10161         mutex_init(&bp->link_lock);
10162
10163         rc = bnxt_update_link(bp, false);
10164         if (rc) {
10165                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10166                            rc);
10167                 return rc;
10168         }
10169
10170         /* Older firmware does not have supported_auto_speeds, so assume
10171          * that all supported speeds can be autonegotiated.
10172          */
10173         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10174                 link_info->support_auto_speeds = link_info->support_speeds;
10175
10176         /*initialize the ethool setting copy with NVM settings */
10177         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10178                 link_info->autoneg = BNXT_AUTONEG_SPEED;
10179                 if (bp->hwrm_spec_code >= 0x10201) {
10180                         if (link_info->auto_pause_setting &
10181                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10182                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10183                 } else {
10184                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10185                 }
10186                 link_info->advertising = link_info->auto_link_speeds;
10187         } else {
10188                 link_info->req_link_speed = link_info->force_link_speed;
10189                 link_info->req_duplex = link_info->duplex_setting;
10190         }
10191         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10192                 link_info->req_flow_ctrl =
10193                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10194         else
10195                 link_info->req_flow_ctrl = link_info->force_pause_setting;
10196         return rc;
10197 }
10198
10199 static int bnxt_get_max_irq(struct pci_dev *pdev)
10200 {
10201         u16 ctrl;
10202
10203         if (!pdev->msix_cap)
10204                 return 1;
10205
10206         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10207         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10208 }
10209
10210 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10211                                 int *max_cp)
10212 {
10213         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10214         int max_ring_grps = 0, max_irq;
10215
10216         *max_tx = hw_resc->max_tx_rings;
10217         *max_rx = hw_resc->max_rx_rings;
10218         *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10219         max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10220                         bnxt_get_ulp_msix_num(bp),
10221                         hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10222         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10223                 *max_cp = min_t(int, *max_cp, max_irq);
10224         max_ring_grps = hw_resc->max_hw_ring_grps;
10225         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10226                 *max_cp -= 1;
10227                 *max_rx -= 2;
10228         }
10229         if (bp->flags & BNXT_FLAG_AGG_RINGS)
10230                 *max_rx >>= 1;
10231         if (bp->flags & BNXT_FLAG_CHIP_P5) {
10232                 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10233                 /* On P5 chips, max_cp output param should be available NQs */
10234                 *max_cp = max_irq;
10235         }
10236         *max_rx = min_t(int, *max_rx, max_ring_grps);
10237 }
10238
10239 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10240 {
10241         int rx, tx, cp;
10242
10243         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10244         *max_rx = rx;
10245         *max_tx = tx;
10246         if (!rx || !tx || !cp)
10247                 return -ENOMEM;
10248
10249         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10250 }
10251
10252 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10253                                bool shared)
10254 {
10255         int rc;
10256
10257         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10258         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10259                 /* Not enough rings, try disabling agg rings. */
10260                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10261                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10262                 if (rc) {
10263                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
10264                         bp->flags |= BNXT_FLAG_AGG_RINGS;
10265                         return rc;
10266                 }
10267                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10268                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10269                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10270                 bnxt_set_ring_params(bp);
10271         }
10272
10273         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10274                 int max_cp, max_stat, max_irq;
10275
10276                 /* Reserve minimum resources for RoCE */
10277                 max_cp = bnxt_get_max_func_cp_rings(bp);
10278                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10279                 max_irq = bnxt_get_max_func_irqs(bp);
10280                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10281                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10282                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10283                         return 0;
10284
10285                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10286                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10287                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10288                 max_cp = min_t(int, max_cp, max_irq);
10289                 max_cp = min_t(int, max_cp, max_stat);
10290                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10291                 if (rc)
10292                         rc = 0;
10293         }
10294         return rc;
10295 }
10296
10297 /* In initial default shared ring setting, each shared ring must have a
10298  * RX/TX ring pair.
10299  */
10300 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10301 {
10302         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10303         bp->rx_nr_rings = bp->cp_nr_rings;
10304         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10305         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10306 }
10307
10308 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10309 {
10310         int dflt_rings, max_rx_rings, max_tx_rings, rc;
10311
10312         if (!bnxt_can_reserve_rings(bp))
10313                 return 0;
10314
10315         if (sh)
10316                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10317         dflt_rings = netif_get_num_default_rss_queues();
10318         /* Reduce default rings on multi-port cards so that total default
10319          * rings do not exceed CPU count.
10320          */
10321         if (bp->port_count > 1) {
10322                 int max_rings =
10323                         max_t(int, num_online_cpus() / bp->port_count, 1);
10324
10325                 dflt_rings = min_t(int, dflt_rings, max_rings);
10326         }
10327         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10328         if (rc)
10329                 return rc;
10330         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10331         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10332         if (sh)
10333                 bnxt_trim_dflt_sh_rings(bp);
10334         else
10335                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10336         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10337
10338         rc = __bnxt_reserve_rings(bp);
10339         if (rc)
10340                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10341         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10342         if (sh)
10343                 bnxt_trim_dflt_sh_rings(bp);
10344
10345         /* Rings may have been trimmed, re-reserve the trimmed rings. */
10346         if (bnxt_need_reserve_rings(bp)) {
10347                 rc = __bnxt_reserve_rings(bp);
10348                 if (rc)
10349                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10350                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10351         }
10352         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10353                 bp->rx_nr_rings++;
10354                 bp->cp_nr_rings++;
10355         }
10356         return rc;
10357 }
10358
10359 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10360 {
10361         int rc;
10362
10363         if (bp->tx_nr_rings)
10364                 return 0;
10365
10366         bnxt_ulp_irq_stop(bp);
10367         bnxt_clear_int_mode(bp);
10368         rc = bnxt_set_dflt_rings(bp, true);
10369         if (rc) {
10370                 netdev_err(bp->dev, "Not enough rings available.\n");
10371                 goto init_dflt_ring_err;
10372         }
10373         rc = bnxt_init_int_mode(bp);
10374         if (rc)
10375                 goto init_dflt_ring_err;
10376
10377         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10378         if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10379                 bp->flags |= BNXT_FLAG_RFS;
10380                 bp->dev->features |= NETIF_F_NTUPLE;
10381         }
10382 init_dflt_ring_err:
10383         bnxt_ulp_irq_restart(bp, rc);
10384         return rc;
10385 }
10386
10387 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10388 {
10389         int rc;
10390
10391         ASSERT_RTNL();
10392         bnxt_hwrm_func_qcaps(bp);
10393
10394         if (netif_running(bp->dev))
10395                 __bnxt_close_nic(bp, true, false);
10396
10397         bnxt_ulp_irq_stop(bp);
10398         bnxt_clear_int_mode(bp);
10399         rc = bnxt_init_int_mode(bp);
10400         bnxt_ulp_irq_restart(bp, rc);
10401
10402         if (netif_running(bp->dev)) {
10403                 if (rc)
10404                         dev_close(bp->dev);
10405                 else
10406                         rc = bnxt_open_nic(bp, true, false);
10407         }
10408
10409         return rc;
10410 }
10411
10412 static int bnxt_init_mac_addr(struct bnxt *bp)
10413 {
10414         int rc = 0;
10415
10416         if (BNXT_PF(bp)) {
10417                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10418         } else {
10419 #ifdef CONFIG_BNXT_SRIOV
10420                 struct bnxt_vf_info *vf = &bp->vf;
10421                 bool strict_approval = true;
10422
10423                 if (is_valid_ether_addr(vf->mac_addr)) {
10424                         /* overwrite netdev dev_addr with admin VF MAC */
10425                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10426                         /* Older PF driver or firmware may not approve this
10427                          * correctly.
10428                          */
10429                         strict_approval = false;
10430                 } else {
10431                         eth_hw_addr_random(bp->dev);
10432                 }
10433                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10434 #endif
10435         }
10436         return rc;
10437 }
10438
10439 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10440 {
10441         static int version_printed;
10442         struct net_device *dev;
10443         struct bnxt *bp;
10444         int rc, max_irqs;
10445
10446         if (pci_is_bridge(pdev))
10447                 return -ENODEV;
10448
10449         if (version_printed++ == 0)
10450                 pr_info("%s", version);
10451
10452         max_irqs = bnxt_get_max_irq(pdev);
10453         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10454         if (!dev)
10455                 return -ENOMEM;
10456
10457         bp = netdev_priv(dev);
10458         bnxt_set_max_func_irqs(bp, max_irqs);
10459
10460         if (bnxt_vf_pciid(ent->driver_data))
10461                 bp->flags |= BNXT_FLAG_VF;
10462
10463         if (pdev->msix_cap)
10464                 bp->flags |= BNXT_FLAG_MSIX_CAP;
10465
10466         rc = bnxt_init_board(pdev, dev);
10467         if (rc < 0)
10468                 goto init_err_free;
10469
10470         dev->netdev_ops = &bnxt_netdev_ops;
10471         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10472         dev->ethtool_ops = &bnxt_ethtool_ops;
10473         pci_set_drvdata(pdev, dev);
10474
10475         rc = bnxt_alloc_hwrm_resources(bp);
10476         if (rc)
10477                 goto init_err_pci_clean;
10478
10479         mutex_init(&bp->hwrm_cmd_lock);
10480         rc = bnxt_hwrm_ver_get(bp);
10481         if (rc)
10482                 goto init_err_pci_clean;
10483
10484         if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10485                 rc = bnxt_alloc_kong_hwrm_resources(bp);
10486                 if (rc)
10487                         bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10488         }
10489
10490         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10491             bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10492                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10493                 if (rc)
10494                         goto init_err_pci_clean;
10495         }
10496
10497         if (BNXT_CHIP_P5(bp))
10498                 bp->flags |= BNXT_FLAG_CHIP_P5;
10499
10500         rc = bnxt_hwrm_func_reset(bp);
10501         if (rc)
10502                 goto init_err_pci_clean;
10503
10504         bnxt_hwrm_fw_set_time(bp);
10505
10506         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10507                            NETIF_F_TSO | NETIF_F_TSO6 |
10508                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10509                            NETIF_F_GSO_IPXIP4 |
10510                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10511                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10512                            NETIF_F_RXCSUM | NETIF_F_GRO;
10513
10514         if (BNXT_SUPPORTS_TPA(bp))
10515                 dev->hw_features |= NETIF_F_LRO;
10516
10517         dev->hw_enc_features =
10518                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10519                         NETIF_F_TSO | NETIF_F_TSO6 |
10520                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10521                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10522                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10523         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10524                                     NETIF_F_GSO_GRE_CSUM;
10525         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10526         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10527                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10528         if (BNXT_SUPPORTS_TPA(bp))
10529                 dev->hw_features |= NETIF_F_GRO_HW;
10530         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10531         if (dev->features & NETIF_F_GRO_HW)
10532                 dev->features &= ~NETIF_F_LRO;
10533         dev->priv_flags |= IFF_UNICAST_FLT;
10534
10535 #ifdef CONFIG_BNXT_SRIOV
10536         init_waitqueue_head(&bp->sriov_cfg_wait);
10537         mutex_init(&bp->sriov_lock);
10538 #endif
10539         if (BNXT_SUPPORTS_TPA(bp)) {
10540                 bp->gro_func = bnxt_gro_func_5730x;
10541                 if (BNXT_CHIP_P4(bp))
10542                         bp->gro_func = bnxt_gro_func_5731x;
10543         }
10544         if (!BNXT_CHIP_P4_PLUS(bp))
10545                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10546
10547         rc = bnxt_hwrm_func_drv_rgtr(bp);
10548         if (rc)
10549                 goto init_err_pci_clean;
10550
10551         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10552         if (rc)
10553                 goto init_err_pci_clean;
10554
10555         bp->ulp_probe = bnxt_ulp_probe;
10556
10557         rc = bnxt_hwrm_queue_qportcfg(bp);
10558         if (rc) {
10559                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10560                            rc);
10561                 rc = -1;
10562                 goto init_err_pci_clean;
10563         }
10564         /* Get the MAX capabilities for this function */
10565         rc = bnxt_hwrm_func_qcaps(bp);
10566         if (rc) {
10567                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10568                            rc);
10569                 rc = -1;
10570                 goto init_err_pci_clean;
10571         }
10572         rc = bnxt_init_mac_addr(bp);
10573         if (rc) {
10574                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10575                 rc = -EADDRNOTAVAIL;
10576                 goto init_err_pci_clean;
10577         }
10578
10579         bnxt_hwrm_func_qcfg(bp);
10580         bnxt_hwrm_vnic_qcaps(bp);
10581         bnxt_hwrm_port_led_qcaps(bp);
10582         bnxt_ethtool_init(bp);
10583         bnxt_dcb_init(bp);
10584
10585         /* MTU range: 60 - FW defined max */
10586         dev->min_mtu = ETH_ZLEN;
10587         dev->max_mtu = bp->max_mtu;
10588
10589         rc = bnxt_probe_phy(bp);
10590         if (rc)
10591                 goto init_err_pci_clean;
10592
10593         bnxt_set_rx_skb_mode(bp, false);
10594         bnxt_set_tpa_flags(bp);
10595         bnxt_set_ring_params(bp);
10596         rc = bnxt_set_dflt_rings(bp, true);
10597         if (rc) {
10598                 netdev_err(bp->dev, "Not enough rings available.\n");
10599                 rc = -ENOMEM;
10600                 goto init_err_pci_clean;
10601         }
10602
10603         /* Default RSS hash cfg. */
10604         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10605                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10606                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10607                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10608         if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10609                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10610                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10611                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10612         }
10613
10614         if (bnxt_rfs_supported(bp)) {
10615                 dev->hw_features |= NETIF_F_NTUPLE;
10616                 if (bnxt_rfs_capable(bp)) {
10617                         bp->flags |= BNXT_FLAG_RFS;
10618                         dev->features |= NETIF_F_NTUPLE;
10619                 }
10620         }
10621
10622         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10623                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10624
10625         rc = bnxt_init_int_mode(bp);
10626         if (rc)
10627                 goto init_err_pci_clean;
10628
10629         /* No TC has been set yet and rings may have been trimmed due to
10630          * limited MSIX, so we re-initialize the TX rings per TC.
10631          */
10632         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10633
10634         bnxt_get_wol_settings(bp);
10635         if (bp->flags & BNXT_FLAG_WOL_CAP)
10636                 device_set_wakeup_enable(&pdev->dev, bp->wol);
10637         else
10638                 device_set_wakeup_capable(&pdev->dev, false);
10639
10640         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10641
10642         bnxt_hwrm_coal_params_qcaps(bp);
10643
10644         if (BNXT_PF(bp)) {
10645                 if (!bnxt_pf_wq) {
10646                         bnxt_pf_wq =
10647                                 create_singlethread_workqueue("bnxt_pf_wq");
10648                         if (!bnxt_pf_wq) {
10649                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10650                                 goto init_err_pci_clean;
10651                         }
10652                 }
10653                 bnxt_init_tc(bp);
10654         }
10655
10656         rc = register_netdev(dev);
10657         if (rc)
10658                 goto init_err_cleanup_tc;
10659
10660         if (BNXT_PF(bp))
10661                 bnxt_dl_register(bp);
10662
10663         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10664                     board_info[ent->driver_data].name,
10665                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
10666         pcie_print_link_status(pdev);
10667
10668         return 0;
10669
10670 init_err_cleanup_tc:
10671         bnxt_shutdown_tc(bp);
10672         bnxt_clear_int_mode(bp);
10673
10674 init_err_pci_clean:
10675         bnxt_free_hwrm_resources(bp);
10676         bnxt_free_ctx_mem(bp);
10677         kfree(bp->ctx);
10678         bp->ctx = NULL;
10679         bnxt_cleanup_pci(bp);
10680
10681 init_err_free:
10682         free_netdev(dev);
10683         return rc;
10684 }
10685
10686 static void bnxt_shutdown(struct pci_dev *pdev)
10687 {
10688         struct net_device *dev = pci_get_drvdata(pdev);
10689         struct bnxt *bp;
10690
10691         if (!dev)
10692                 return;
10693
10694         rtnl_lock();
10695         bp = netdev_priv(dev);
10696         if (!bp)
10697                 goto shutdown_exit;
10698
10699         if (netif_running(dev))
10700                 dev_close(dev);
10701
10702         bnxt_ulp_shutdown(bp);
10703
10704         if (system_state == SYSTEM_POWER_OFF) {
10705                 bnxt_clear_int_mode(bp);
10706                 pci_wake_from_d3(pdev, bp->wol);
10707                 pci_set_power_state(pdev, PCI_D3hot);
10708         }
10709
10710 shutdown_exit:
10711         rtnl_unlock();
10712 }
10713
10714 #ifdef CONFIG_PM_SLEEP
10715 static int bnxt_suspend(struct device *device)
10716 {
10717         struct pci_dev *pdev = to_pci_dev(device);
10718         struct net_device *dev = pci_get_drvdata(pdev);
10719         struct bnxt *bp = netdev_priv(dev);
10720         int rc = 0;
10721
10722         rtnl_lock();
10723         if (netif_running(dev)) {
10724                 netif_device_detach(dev);
10725                 rc = bnxt_close(dev);
10726         }
10727         bnxt_hwrm_func_drv_unrgtr(bp);
10728         rtnl_unlock();
10729         return rc;
10730 }
10731
10732 static int bnxt_resume(struct device *device)
10733 {
10734         struct pci_dev *pdev = to_pci_dev(device);
10735         struct net_device *dev = pci_get_drvdata(pdev);
10736         struct bnxt *bp = netdev_priv(dev);
10737         int rc = 0;
10738
10739         rtnl_lock();
10740         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10741                 rc = -ENODEV;
10742                 goto resume_exit;
10743         }
10744         rc = bnxt_hwrm_func_reset(bp);
10745         if (rc) {
10746                 rc = -EBUSY;
10747                 goto resume_exit;
10748         }
10749         bnxt_get_wol_settings(bp);
10750         if (netif_running(dev)) {
10751                 rc = bnxt_open(dev);
10752                 if (!rc)
10753                         netif_device_attach(dev);
10754         }
10755
10756 resume_exit:
10757         rtnl_unlock();
10758         return rc;
10759 }
10760
10761 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10762 #define BNXT_PM_OPS (&bnxt_pm_ops)
10763
10764 #else
10765
10766 #define BNXT_PM_OPS NULL
10767
10768 #endif /* CONFIG_PM_SLEEP */
10769
10770 /**
10771  * bnxt_io_error_detected - called when PCI error is detected
10772  * @pdev: Pointer to PCI device
10773  * @state: The current pci connection state
10774  *
10775  * This function is called after a PCI bus error affecting
10776  * this device has been detected.
10777  */
10778 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10779                                                pci_channel_state_t state)
10780 {
10781         struct net_device *netdev = pci_get_drvdata(pdev);
10782         struct bnxt *bp = netdev_priv(netdev);
10783
10784         netdev_info(netdev, "PCI I/O error detected\n");
10785
10786         rtnl_lock();
10787         netif_device_detach(netdev);
10788
10789         bnxt_ulp_stop(bp);
10790
10791         if (state == pci_channel_io_perm_failure) {
10792                 rtnl_unlock();
10793                 return PCI_ERS_RESULT_DISCONNECT;
10794         }
10795
10796         if (netif_running(netdev))
10797                 bnxt_close(netdev);
10798
10799         pci_disable_device(pdev);
10800         rtnl_unlock();
10801
10802         /* Request a slot slot reset. */
10803         return PCI_ERS_RESULT_NEED_RESET;
10804 }
10805
10806 /**
10807  * bnxt_io_slot_reset - called after the pci bus has been reset.
10808  * @pdev: Pointer to PCI device
10809  *
10810  * Restart the card from scratch, as if from a cold-boot.
10811  * At this point, the card has exprienced a hard reset,
10812  * followed by fixups by BIOS, and has its config space
10813  * set up identically to what it was at cold boot.
10814  */
10815 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
10816 {
10817         struct net_device *netdev = pci_get_drvdata(pdev);
10818         struct bnxt *bp = netdev_priv(netdev);
10819         int err = 0;
10820         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
10821
10822         netdev_info(bp->dev, "PCI Slot Reset\n");
10823
10824         rtnl_lock();
10825
10826         if (pci_enable_device(pdev)) {
10827                 dev_err(&pdev->dev,
10828                         "Cannot re-enable PCI device after reset.\n");
10829         } else {
10830                 pci_set_master(pdev);
10831
10832                 err = bnxt_hwrm_func_reset(bp);
10833                 if (!err && netif_running(netdev))
10834                         err = bnxt_open(netdev);
10835
10836                 if (!err) {
10837                         result = PCI_ERS_RESULT_RECOVERED;
10838                         bnxt_ulp_start(bp);
10839                 }
10840         }
10841
10842         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
10843                 dev_close(netdev);
10844
10845         rtnl_unlock();
10846
10847         return PCI_ERS_RESULT_RECOVERED;
10848 }
10849
10850 /**
10851  * bnxt_io_resume - called when traffic can start flowing again.
10852  * @pdev: Pointer to PCI device
10853  *
10854  * This callback is called when the error recovery driver tells
10855  * us that its OK to resume normal operation.
10856  */
10857 static void bnxt_io_resume(struct pci_dev *pdev)
10858 {
10859         struct net_device *netdev = pci_get_drvdata(pdev);
10860
10861         rtnl_lock();
10862
10863         netif_device_attach(netdev);
10864
10865         rtnl_unlock();
10866 }
10867
10868 static const struct pci_error_handlers bnxt_err_handler = {
10869         .error_detected = bnxt_io_error_detected,
10870         .slot_reset     = bnxt_io_slot_reset,
10871         .resume         = bnxt_io_resume
10872 };
10873
10874 static struct pci_driver bnxt_pci_driver = {
10875         .name           = DRV_MODULE_NAME,
10876         .id_table       = bnxt_pci_tbl,
10877         .probe          = bnxt_init_one,
10878         .remove         = bnxt_remove_one,
10879         .shutdown       = bnxt_shutdown,
10880         .driver.pm      = BNXT_PM_OPS,
10881         .err_handler    = &bnxt_err_handler,
10882 #if defined(CONFIG_BNXT_SRIOV)
10883         .sriov_configure = bnxt_sriov_configure,
10884 #endif
10885 };
10886
10887 static int __init bnxt_init(void)
10888 {
10889         bnxt_debug_init();
10890         return pci_register_driver(&bnxt_pci_driver);
10891 }
10892
10893 static void __exit bnxt_exit(void)
10894 {
10895         pci_unregister_driver(&bnxt_pci_driver);
10896         if (bnxt_pf_wq)
10897                 destroy_workqueue(bnxt_pf_wq);
10898         bnxt_debug_exit();
10899 }
10900
10901 module_init(bnxt_init);
10902 module_exit(bnxt_exit);