drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2017 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/if.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/rtc.h>
  37 #include <linux/bpf.h>
  38 #include <net/ip.h>
  39 #include <net/tcp.h>
  40 #include <net/udp.h>
  41 #include <net/checksum.h>
  42 #include <net/ip6_checksum.h>
  43 #include <net/udp_tunnel.h>
  44 #include <linux/workqueue.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/cache.h>
  47 #include <linux/log2.h>
  48 #include <linux/aer.h>
  49 #include <linux/bitmap.h>
  50 #include <linux/cpu_rmap.h>
  51
  52 #include "bnxt_hsi.h"
  53 #include "bnxt.h"
  54 #include "bnxt_ulp.h"
  55 #include "bnxt_sriov.h"
  56 #include "bnxt_ethtool.h"
  57 #include "bnxt_dcb.h"
  58 #include "bnxt_xdp.h"
  59
  60 #define BNXT_TX_TIMEOUT         (5 * HZ)
  61
  62 static const char version[] =
  63         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  64
  65 MODULE_LICENSE("GPL");
  66 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  67 MODULE_VERSION(DRV_MODULE_VERSION);
  68
  69 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  70 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  71 #define BNXT_RX_COPY_THRESH 256
  72
  73 #define BNXT_TX_PUSH_THRESH 164
  74
  75 enum board_idx {
  76         BCM57301,
  77         BCM57302,
  78         BCM57304,
  79         BCM57417_NPAR,
  80         BCM58700,
  81         BCM57311,
  82         BCM57312,
  83         BCM57402,
  84         BCM57404,
  85         BCM57406,
  86         BCM57402_NPAR,
  87         BCM57407,
  88         BCM57412,
  89         BCM57414,
  90         BCM57416,
  91         BCM57417,
  92         BCM57412_NPAR,
  93         BCM57314,
  94         BCM57417_SFP,
  95         BCM57416_SFP,
  96         BCM57404_NPAR,
  97         BCM57406_NPAR,
  98         BCM57407_SFP,
  99         BCM57407_NPAR,
 100         BCM57414_NPAR,
 101         BCM57416_NPAR,
 102         BCM57452,
 103         BCM57454,
 104         NETXTREME_E_VF,
 105         NETXTREME_C_VF,
 106 };
 107
 108 /* indexed by enum above */
 109 static const struct {
 110         char *name;
 111 } board_info[] = {
 112         { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 113         { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 114         { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 115         { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 116         { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 117         { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 118         { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 119         { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 120         { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 121         { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 122         { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 123         { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 124         { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 125         { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 126         { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 127         { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 128         { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 129         { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 130         { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 131         { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 132         { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 133         { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 134         { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 135         { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 136         { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 137         { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 138         { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 139         { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 140         { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 141         { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 142 };
 143
 144 static const struct pci_device_id bnxt_pci_tbl[] = {
 145         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 146         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 147         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 148         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 149         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 150         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 151         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 152         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 153         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 154         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 155         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 156         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 157         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 158         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 159         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 160         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 161         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 162         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 163         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 164         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 165         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 166         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 167         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 169         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 170         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 171         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 173         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 174         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 175         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 176         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 177 #ifdef CONFIG_BNXT_SRIOV
 178         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 179         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 180         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 181         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 182         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 183         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 184         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 185         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 186 #endif
 187         { 0 }
 188 };
 189
 190 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 191
 192 static const u16 bnxt_vf_req_snif[] = {
 193         HWRM_FUNC_CFG,
 194         HWRM_PORT_PHY_QCFG,
 195         HWRM_CFA_L2_FILTER_ALLOC,
 196 };
 197
 198 static const u16 bnxt_async_events_arr[] = {
 199         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 200         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 201         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 202         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 203         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 204 };
 205
 206 static bool bnxt_vf_pciid(enum board_idx idx)
 207 {
 208         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
 209 }
 210
 211 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 212 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 213 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 214
 215 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 216                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 217
 218 #define BNXT_CP_DB(db, raw_cons)                                        \
 219                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 220
 221 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 222                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 223
 224 const u16 bnxt_lhint_arr[] = {
 225         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 226         TX_BD_FLAGS_LHINT_512_TO_1023,
 227         TX_BD_FLAGS_LHINT_1024_TO_2047,
 228         TX_BD_FLAGS_LHINT_1024_TO_2047,
 229         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 230         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 231         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 232         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 233         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 234         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 235         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 236         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 237         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 238         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 239         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 240         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 241         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 242         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 243         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 244 };
 245
 246 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 247 {
 248         struct bnxt *bp = netdev_priv(dev);
 249         struct tx_bd *txbd;
 250         struct tx_bd_ext *txbd1;
 251         struct netdev_queue *txq;
 252         int i;
 253         dma_addr_t mapping;
 254         unsigned int length, pad = 0;
 255         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 256         u16 prod, last_frag;
 257         struct pci_dev *pdev = bp->pdev;
 258         struct bnxt_tx_ring_info *txr;
 259         struct bnxt_sw_tx_bd *tx_buf;
 260
 261         i = skb_get_queue_mapping(skb);
 262         if (unlikely(i >= bp->tx_nr_rings)) {
 263                 dev_kfree_skb_any(skb);
 264                 return NETDEV_TX_OK;
 265         }
 266
 267         txq = netdev_get_tx_queue(dev, i);
 268         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 269         prod = txr->tx_prod;
 270
 271         free_size = bnxt_tx_avail(bp, txr);
 272         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 273                 netif_tx_stop_queue(txq);
 274                 return NETDEV_TX_BUSY;
 275         }
 276
 277         length = skb->len;
 278         len = skb_headlen(skb);
 279         last_frag = skb_shinfo(skb)->nr_frags;
 280
 281         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 282
 283         txbd->tx_bd_opaque = prod;
 284
 285         tx_buf = &txr->tx_buf_ring[prod];
 286         tx_buf->skb = skb;
 287         tx_buf->nr_frags = last_frag;
 288
 289         vlan_tag_flags = 0;
 290         cfa_action = 0;
 291         if (skb_vlan_tag_present(skb)) {
 292                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 293                                  skb_vlan_tag_get(skb);
 294                 /* Currently supports 8021Q, 8021AD vlan offloads
 295                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 296                  */
 297                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 298                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 299         }
 300
 301         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 302                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 303                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 304                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 305                 void *pdata = tx_push_buf->data;
 306                 u64 *end;
 307                 int j, push_len;
 308
 309                 /* Set COAL_NOW to be ready quickly for the next push */
 310                 tx_push->tx_bd_len_flags_type =
 311                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 312                                         TX_BD_TYPE_LONG_TX_BD |
 313                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 314                                         TX_BD_FLAGS_COAL_NOW |
 315                                         TX_BD_FLAGS_PACKET_END |
 316                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 317
 318                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 319                         tx_push1->tx_bd_hsize_lflags =
 320                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 321                 else
 322                         tx_push1->tx_bd_hsize_lflags = 0;
 323
 324                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 325                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 326
 327                 end = pdata + length;
 328                 end = PTR_ALIGN(end, 8) - 1;
 329                 *end = 0;
 330
 331                 skb_copy_from_linear_data(skb, pdata, len);
 332                 pdata += len;
 333                 for (j = 0; j < last_frag; j++) {
 334                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 335                         void *fptr;
 336
 337                         fptr = skb_frag_address_safe(frag);
 338                         if (!fptr)
 339                                 goto normal_tx;
 340
 341                         memcpy(pdata, fptr, skb_frag_size(frag));
 342                         pdata += skb_frag_size(frag);
 343                 }
 344
 345                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 346                 txbd->tx_bd_haddr = txr->data_mapping;
 347                 prod = NEXT_TX(prod);
 348                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 349                 memcpy(txbd, tx_push1, sizeof(*txbd));
 350                 prod = NEXT_TX(prod);
 351                 tx_push->doorbell =
 352                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 353                 txr->tx_prod = prod;
 354
 355                 tx_buf->is_push = 1;
 356                 netdev_tx_sent_queue(txq, skb->len);
 357                 wmb();  /* Sync is_push and byte queue before pushing data */
 358
 359                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 360                 if (push_len > 16) {
 361                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 362                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 363                                          (push_len - 16) << 1);
 364                 } else {
 365                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 366                                          push_len);
 367                 }
 368
 369                 goto tx_done;
 370         }
 371
 372 normal_tx:
 373         if (length < BNXT_MIN_PKT_SIZE) {
 374                 pad = BNXT_MIN_PKT_SIZE - length;
 375                 if (skb_pad(skb, pad)) {
 376                         /* SKB already freed. */
 377                         tx_buf->skb = NULL;
 378                         return NETDEV_TX_OK;
 379                 }
 380                 length = BNXT_MIN_PKT_SIZE;
 381         }
 382
 383         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 384
 385         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 386                 dev_kfree_skb_any(skb);
 387                 tx_buf->skb = NULL;
 388                 return NETDEV_TX_OK;
 389         }
 390
 391         dma_unmap_addr_set(tx_buf, mapping, mapping);
 392         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 393                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 394
 395         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 396
 397         prod = NEXT_TX(prod);
 398         txbd1 = (struct tx_bd_ext *)
 399                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 400
 401         txbd1->tx_bd_hsize_lflags = 0;
 402         if (skb_is_gso(skb)) {
 403                 u32 hdr_len;
 404
 405                 if (skb->encapsulation)
 406                         hdr_len = skb_inner_network_offset(skb) +
 407                                 skb_inner_network_header_len(skb) +
 408                                 inner_tcp_hdrlen(skb);
 409                 else
 410                         hdr_len = skb_transport_offset(skb) +
 411                                 tcp_hdrlen(skb);
 412
 413                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 414                                         TX_BD_FLAGS_T_IPID |
 415                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 416                 length = skb_shinfo(skb)->gso_size;
 417                 txbd1->tx_bd_mss = cpu_to_le32(length);
 418                 length += hdr_len;
 419         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 420                 txbd1->tx_bd_hsize_lflags =
 421                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 422                 txbd1->tx_bd_mss = 0;
 423         }
 424
 425         length >>= 9;
 426         flags |= bnxt_lhint_arr[length];
 427         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 428
 429         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 430         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 431         for (i = 0; i < last_frag; i++) {
 432                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 433
 434                 prod = NEXT_TX(prod);
 435                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 436
 437                 len = skb_frag_size(frag);
 438                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 439                                            DMA_TO_DEVICE);
 440
 441                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 442                         goto tx_dma_error;
 443
 444                 tx_buf = &txr->tx_buf_ring[prod];
 445                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 446
 447                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 448
 449                 flags = len << TX_BD_LEN_SHIFT;
 450                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 451         }
 452
 453         flags &= ~TX_BD_LEN;
 454         txbd->tx_bd_len_flags_type =
 455                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 456                             TX_BD_FLAGS_PACKET_END);
 457
 458         netdev_tx_sent_queue(txq, skb->len);
 459
 460         /* Sync BD data before updating doorbell */
 461         wmb();
 462
 463         prod = NEXT_TX(prod);
 464         txr->tx_prod = prod;
 465
 466         if (!skb->xmit_more || netif_xmit_stopped(txq))
 467                 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 468
 469 tx_done:
 470
 471         mmiowb();
 472
 473         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 474                 if (skb->xmit_more && !tx_buf->is_push)
 475                         bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 476
 477                 netif_tx_stop_queue(txq);
 478
 479                 /* netif_tx_stop_queue() must be done before checking
 480                  * tx index in bnxt_tx_avail() below, because in
 481                  * bnxt_tx_int(), we update tx index before checking for
 482                  * netif_tx_queue_stopped().
 483                  */
 484                 smp_mb();
 485                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 486                         netif_tx_wake_queue(txq);
 487         }
 488         return NETDEV_TX_OK;
 489
 490 tx_dma_error:
 491         last_frag = i;
 492
 493         /* start back at beginning and unmap skb */
 494         prod = txr->tx_prod;
 495         tx_buf = &txr->tx_buf_ring[prod];
 496         tx_buf->skb = NULL;
 497         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 498                          skb_headlen(skb), PCI_DMA_TODEVICE);
 499         prod = NEXT_TX(prod);
 500
 501         /* unmap remaining mapped pages */
 502         for (i = 0; i < last_frag; i++) {
 503                 prod = NEXT_TX(prod);
 504                 tx_buf = &txr->tx_buf_ring[prod];
 505                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 506                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 507                                PCI_DMA_TODEVICE);
 508         }
 509
 510         dev_kfree_skb_any(skb);
 511         return NETDEV_TX_OK;
 512 }
 513
 514 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 515 {
 516         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 517         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 518         u16 cons = txr->tx_cons;
 519         struct pci_dev *pdev = bp->pdev;
 520         int i;
 521         unsigned int tx_bytes = 0;
 522
 523         for (i = 0; i < nr_pkts; i++) {
 524                 struct bnxt_sw_tx_bd *tx_buf;
 525                 struct sk_buff *skb;
 526                 int j, last;
 527
 528                 tx_buf = &txr->tx_buf_ring[cons];
 529                 cons = NEXT_TX(cons);
 530                 skb = tx_buf->skb;
 531                 tx_buf->skb = NULL;
 532
 533                 if (tx_buf->is_push) {
 534                         tx_buf->is_push = 0;
 535                         goto next_tx_int;
 536                 }
 537
 538                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 539                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 540                 last = tx_buf->nr_frags;
 541
 542                 for (j = 0; j < last; j++) {
 543                         cons = NEXT_TX(cons);
 544                         tx_buf = &txr->tx_buf_ring[cons];
 545                         dma_unmap_page(
 546                                 &pdev->dev,
 547                                 dma_unmap_addr(tx_buf, mapping),
 548                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 549                                 PCI_DMA_TODEVICE);
 550                 }
 551
 552 next_tx_int:
 553                 cons = NEXT_TX(cons);
 554
 555                 tx_bytes += skb->len;
 556                 dev_kfree_skb_any(skb);
 557         }
 558
 559         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 560         txr->tx_cons = cons;
 561
 562         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 563          * before checking for netif_tx_queue_stopped().  Without the
 564          * memory barrier, there is a small possibility that bnxt_start_xmit()
 565          * will miss it and cause the queue to be stopped forever.
 566          */
 567         smp_mb();
 568
 569         if (unlikely(netif_tx_queue_stopped(txq)) &&
 570             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 571                 __netif_tx_lock(txq, smp_processor_id());
 572                 if (netif_tx_queue_stopped(txq) &&
 573                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 574                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 575                         netif_tx_wake_queue(txq);
 576                 __netif_tx_unlock(txq);
 577         }
 578 }
 579
 580 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 581                                          gfp_t gfp)
 582 {
 583         struct device *dev = &bp->pdev->dev;
 584         struct page *page;
 585
 586         page = alloc_page(gfp);
 587         if (!page)
 588                 return NULL;
 589
 590         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 591                                       DMA_ATTR_WEAK_ORDERING);
 592         if (dma_mapping_error(dev, *mapping)) {
 593                 __free_page(page);
 594                 return NULL;
 595         }
 596         *mapping += bp->rx_dma_offset;
 597         return page;
 598 }
 599
 600 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 601                                        gfp_t gfp)
 602 {
 603         u8 *data;
 604         struct pci_dev *pdev = bp->pdev;
 605
 606         data = kmalloc(bp->rx_buf_size, gfp);
 607         if (!data)
 608                 return NULL;
 609
 610         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 611                                         bp->rx_buf_use_size, bp->rx_dir,
 612                                         DMA_ATTR_WEAK_ORDERING);
 613
 614         if (dma_mapping_error(&pdev->dev, *mapping)) {
 615                 kfree(data);
 616                 data = NULL;
 617         }
 618         return data;
 619 }
 620
 621 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 622                        u16 prod, gfp_t gfp)
 623 {
 624         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 625         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 626         dma_addr_t mapping;
 627
 628         if (BNXT_RX_PAGE_MODE(bp)) {
 629                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 630
 631                 if (!page)
 632                         return -ENOMEM;
 633
 634                 rx_buf->data = page;
 635                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 636         } else {
 637                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 638
 639                 if (!data)
 640                         return -ENOMEM;
 641
 642                 rx_buf->data = data;
 643                 rx_buf->data_ptr = data + bp->rx_offset;
 644         }
 645         rx_buf->mapping = mapping;
 646
 647         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 648         return 0;
 649 }
 650
 651 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 652 {
 653         u16 prod = rxr->rx_prod;
 654         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 655         struct rx_bd *cons_bd, *prod_bd;
 656
 657         prod_rx_buf = &rxr->rx_buf_ring[prod];
 658         cons_rx_buf = &rxr->rx_buf_ring[cons];
 659
 660         prod_rx_buf->data = data;
 661         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 662
 663         prod_rx_buf->mapping = cons_rx_buf->mapping;
 664
 665         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 666         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 667
 668         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 669 }
 670
 671 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 672 {
 673         u16 next, max = rxr->rx_agg_bmap_size;
 674
 675         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 676         if (next >= max)
 677                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 678         return next;
 679 }
 680
 681 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 682                                      struct bnxt_rx_ring_info *rxr,
 683                                      u16 prod, gfp_t gfp)
 684 {
 685         struct rx_bd *rxbd =
 686                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 687         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 688         struct pci_dev *pdev = bp->pdev;
 689         struct page *page;
 690         dma_addr_t mapping;
 691         u16 sw_prod = rxr->rx_sw_agg_prod;
 692         unsigned int offset = 0;
 693
 694         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 695                 page = rxr->rx_page;
 696                 if (!page) {
 697                         page = alloc_page(gfp);
 698                         if (!page)
 699                                 return -ENOMEM;
 700                         rxr->rx_page = page;
 701                         rxr->rx_page_offset = 0;
 702                 }
 703                 offset = rxr->rx_page_offset;
 704                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 705                 if (rxr->rx_page_offset == PAGE_SIZE)
 706                         rxr->rx_page = NULL;
 707                 else
 708                         get_page(page);
 709         } else {
 710                 page = alloc_page(gfp);
 711                 if (!page)
 712                         return -ENOMEM;
 713         }
 714
 715         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 716                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 717                                      DMA_ATTR_WEAK_ORDERING);
 718         if (dma_mapping_error(&pdev->dev, mapping)) {
 719                 __free_page(page);
 720                 return -EIO;
 721         }
 722
 723         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 724                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 725
 726         __set_bit(sw_prod, rxr->rx_agg_bmap);
 727         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 728         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 729
 730         rx_agg_buf->page = page;
 731         rx_agg_buf->offset = offset;
 732         rx_agg_buf->mapping = mapping;
 733         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 734         rxbd->rx_bd_opaque = sw_prod;
 735         return 0;
 736 }
 737
 738 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 739                                    u32 agg_bufs)
 740 {
 741         struct bnxt *bp = bnapi->bp;
 742         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 743         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 744         u16 prod = rxr->rx_agg_prod;
 745         u16 sw_prod = rxr->rx_sw_agg_prod;
 746         u32 i;
 747
 748         for (i = 0; i < agg_bufs; i++) {
 749                 u16 cons;
 750                 struct rx_agg_cmp *agg;
 751                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 752                 struct rx_bd *prod_bd;
 753                 struct page *page;
 754
 755                 agg = (struct rx_agg_cmp *)
 756                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 757                 cons = agg->rx_agg_cmp_opaque;
 758                 __clear_bit(cons, rxr->rx_agg_bmap);
 759
 760                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 761                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 762
 763                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 764                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 765                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 766
 767                 /* It is possible for sw_prod to be equal to cons, so
 768                  * set cons_rx_buf->page to NULL first.
 769                  */
 770                 page = cons_rx_buf->page;
 771                 cons_rx_buf->page = NULL;
 772                 prod_rx_buf->page = page;
 773                 prod_rx_buf->offset = cons_rx_buf->offset;
 774
 775                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 776
 777                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 778
 779                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 780                 prod_bd->rx_bd_opaque = sw_prod;
 781
 782                 prod = NEXT_RX_AGG(prod);
 783                 sw_prod = NEXT_RX_AGG(sw_prod);
 784                 cp_cons = NEXT_CMP(cp_cons);
 785         }
 786         rxr->rx_agg_prod = prod;
 787         rxr->rx_sw_agg_prod = sw_prod;
 788 }
 789
 790 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 791                                         struct bnxt_rx_ring_info *rxr,
 792                                         u16 cons, void *data, u8 *data_ptr,
 793                                         dma_addr_t dma_addr,
 794                                         unsigned int offset_and_len)
 795 {
 796         unsigned int payload = offset_and_len >> 16;
 797         unsigned int len = offset_and_len & 0xffff;
 798         struct skb_frag_struct *frag;
 799         struct page *page = data;
 800         u16 prod = rxr->rx_prod;
 801         struct sk_buff *skb;
 802         int off, err;
 803
 804         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 805         if (unlikely(err)) {
 806                 bnxt_reuse_rx_data(rxr, cons, data);
 807                 return NULL;
 808         }
 809         dma_addr -= bp->rx_dma_offset;
 810         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 811                              DMA_ATTR_WEAK_ORDERING);
 812
 813         if (unlikely(!payload))
 814                 payload = eth_get_headlen(data_ptr, len);
 815
 816         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 817         if (!skb) {
 818                 __free_page(page);
 819                 return NULL;
 820         }
 821
 822         off = (void *)data_ptr - page_address(page);
 823         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 824         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 825                payload + NET_IP_ALIGN);
 826
 827         frag = &skb_shinfo(skb)->frags[0];
 828         skb_frag_size_sub(frag, payload);
 829         frag->page_offset += payload;
 830         skb->data_len -= payload;
 831         skb->tail += payload;
 832
 833         return skb;
 834 }
 835
 836 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 837                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 838                                    void *data, u8 *data_ptr,
 839                                    dma_addr_t dma_addr,
 840                                    unsigned int offset_and_len)
 841 {
 842         u16 prod = rxr->rx_prod;
 843         struct sk_buff *skb;
 844         int err;
 845
 846         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 847         if (unlikely(err)) {
 848                 bnxt_reuse_rx_data(rxr, cons, data);
 849                 return NULL;
 850         }
 851
 852         skb = build_skb(data, 0);
 853         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 854                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 855         if (!skb) {
 856                 kfree(data);
 857                 return NULL;
 858         }
 859
 860         skb_reserve(skb, bp->rx_offset);
 861         skb_put(skb, offset_and_len & 0xffff);
 862         return skb;
 863 }
 864
 865 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 866                                      struct sk_buff *skb, u16 cp_cons,
 867                                      u32 agg_bufs)
 868 {
 869         struct pci_dev *pdev = bp->pdev;
 870         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 871         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 872         u16 prod = rxr->rx_agg_prod;
 873         u32 i;
 874
 875         for (i = 0; i < agg_bufs; i++) {
 876                 u16 cons, frag_len;
 877                 struct rx_agg_cmp *agg;
 878                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 879                 struct page *page;
 880                 dma_addr_t mapping;
 881
 882                 agg = (struct rx_agg_cmp *)
 883                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 884                 cons = agg->rx_agg_cmp_opaque;
 885                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 886                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 887
 888                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 889                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 890                                    cons_rx_buf->offset, frag_len);
 891                 __clear_bit(cons, rxr->rx_agg_bmap);
 892
 893                 /* It is possible for bnxt_alloc_rx_page() to allocate
 894                  * a sw_prod index that equals the cons index, so we
 895                  * need to clear the cons entry now.
 896                  */
 897                 mapping = cons_rx_buf->mapping;
 898                 page = cons_rx_buf->page;
 899                 cons_rx_buf->page = NULL;
 900
 901                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 902                         struct skb_shared_info *shinfo;
 903                         unsigned int nr_frags;
 904
 905                         shinfo = skb_shinfo(skb);
 906                         nr_frags = --shinfo->nr_frags;
 907                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 908
 909                         dev_kfree_skb(skb);
 910
 911                         cons_rx_buf->page = page;
 912
 913                         /* Update prod since possibly some pages have been
 914                          * allocated already.
 915                          */
 916                         rxr->rx_agg_prod = prod;
 917                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 918                         return NULL;
 919                 }
 920
 921                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 922                                      PCI_DMA_FROMDEVICE,
 923                                      DMA_ATTR_WEAK_ORDERING);
 924
 925                 skb->data_len += frag_len;
 926                 skb->len += frag_len;
 927                 skb->truesize += PAGE_SIZE;
 928
 929                 prod = NEXT_RX_AGG(prod);
 930                 cp_cons = NEXT_CMP(cp_cons);
 931         }
 932         rxr->rx_agg_prod = prod;
 933         return skb;
 934 }
 935
 936 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 937                                u8 agg_bufs, u32 *raw_cons)
 938 {
 939         u16 last;
 940         struct rx_agg_cmp *agg;
 941
 942         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 943         last = RING_CMP(*raw_cons);
 944         agg = (struct rx_agg_cmp *)
 945                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 946         return RX_AGG_CMP_VALID(agg, *raw_cons);
 947 }
 948
 949 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 950                                             unsigned int len,
 951                                             dma_addr_t mapping)
 952 {
 953         struct bnxt *bp = bnapi->bp;
 954         struct pci_dev *pdev = bp->pdev;
 955         struct sk_buff *skb;
 956
 957         skb = napi_alloc_skb(&bnapi->napi, len);
 958         if (!skb)
 959                 return NULL;
 960
 961         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
 962                                 bp->rx_dir);
 963
 964         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
 965                len + NET_IP_ALIGN);
 966
 967         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
 968                                    bp->rx_dir);
 969
 970         skb_put(skb, len);
 971         return skb;
 972 }
 973
 974 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
 975                            u32 *raw_cons, void *cmp)
 976 {
 977         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 978         struct rx_cmp *rxcmp = cmp;
 979         u32 tmp_raw_cons = *raw_cons;
 980         u8 cmp_type, agg_bufs = 0;
 981
 982         cmp_type = RX_CMP_TYPE(rxcmp);
 983
 984         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
 985                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
 986                             RX_CMP_AGG_BUFS) >>
 987                            RX_CMP_AGG_BUFS_SHIFT;
 988         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
 989                 struct rx_tpa_end_cmp *tpa_end = cmp;
 990
 991                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 992                             RX_TPA_END_CMP_AGG_BUFS) >>
 993                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 994         }
 995
 996         if (agg_bufs) {
 997                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
 998                         return -EBUSY;
 999         }
1000         *raw_cons = tmp_raw_cons;
1001         return 0;
1002 }
1003
1004 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1005 {
1006         if (!rxr->bnapi->in_reset) {
1007                 rxr->bnapi->in_reset = true;
1008                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1009                 schedule_work(&bp->sp_task);
1010         }
1011         rxr->rx_next_cons = 0xffff;
1012 }
1013
1014 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1015                            struct rx_tpa_start_cmp *tpa_start,
1016                            struct rx_tpa_start_cmp_ext *tpa_start1)
1017 {
1018         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1019         u16 cons, prod;
1020         struct bnxt_tpa_info *tpa_info;
1021         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1022         struct rx_bd *prod_bd;
1023         dma_addr_t mapping;
1024
1025         cons = tpa_start->rx_tpa_start_cmp_opaque;
1026         prod = rxr->rx_prod;
1027         cons_rx_buf = &rxr->rx_buf_ring[cons];
1028         prod_rx_buf = &rxr->rx_buf_ring[prod];
1029         tpa_info = &rxr->rx_tpa[agg_id];
1030
1031         if (unlikely(cons != rxr->rx_next_cons)) {
1032                 bnxt_sched_reset(bp, rxr);
1033                 return;
1034         }
1035
1036         prod_rx_buf->data = tpa_info->data;
1037         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1038
1039         mapping = tpa_info->mapping;
1040         prod_rx_buf->mapping = mapping;
1041
1042         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1043
1044         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1045
1046         tpa_info->data = cons_rx_buf->data;
1047         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1048         cons_rx_buf->data = NULL;
1049         tpa_info->mapping = cons_rx_buf->mapping;
1050
1051         tpa_info->len =
1052                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1053                                 RX_TPA_START_CMP_LEN_SHIFT;
1054         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1055                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1056
1057                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1058                 tpa_info->gso_type = SKB_GSO_TCPV4;
1059                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1060                 if (hash_type == 3)
1061                         tpa_info->gso_type = SKB_GSO_TCPV6;
1062                 tpa_info->rss_hash =
1063                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1064         } else {
1065                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1066                 tpa_info->gso_type = 0;
1067                 if (netif_msg_rx_err(bp))
1068                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1069         }
1070         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1071         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1072         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1073
1074         rxr->rx_prod = NEXT_RX(prod);
1075         cons = NEXT_RX(cons);
1076         rxr->rx_next_cons = NEXT_RX(cons);
1077         cons_rx_buf = &rxr->rx_buf_ring[cons];
1078
1079         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1080         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1081         cons_rx_buf->data = NULL;
1082 }
1083
1084 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1085                            u16 cp_cons, u32 agg_bufs)
1086 {
1087         if (agg_bufs)
1088                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1089 }
1090
1091 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1092                                            int payload_off, int tcp_ts,
1093                                            struct sk_buff *skb)
1094 {
1095 #ifdef CONFIG_INET
1096         struct tcphdr *th;
1097         int len, nw_off;
1098         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1099         u32 hdr_info = tpa_info->hdr_info;
1100         bool loopback = false;
1101
1102         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1103         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1104         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1105
1106         /* If the packet is an internal loopback packet, the offsets will
1107          * have an extra 4 bytes.
1108          */
1109         if (inner_mac_off == 4) {
1110                 loopback = true;
1111         } else if (inner_mac_off > 4) {
1112                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1113                                             ETH_HLEN - 2));
1114
1115                 /* We only support inner iPv4/ipv6.  If we don't see the
1116                  * correct protocol ID, it must be a loopback packet where
1117                  * the offsets are off by 4.
1118                  */
1119                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1120                         loopback = true;
1121         }
1122         if (loopback) {
1123                 /* internal loopback packet, subtract all offsets by 4 */
1124                 inner_ip_off -= 4;
1125                 inner_mac_off -= 4;
1126                 outer_ip_off -= 4;
1127         }
1128
1129         nw_off = inner_ip_off - ETH_HLEN;
1130         skb_set_network_header(skb, nw_off);
1131         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1132                 struct ipv6hdr *iph = ipv6_hdr(skb);
1133
1134                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1135                 len = skb->len - skb_transport_offset(skb);
1136                 th = tcp_hdr(skb);
1137                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1138         } else {
1139                 struct iphdr *iph = ip_hdr(skb);
1140
1141                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1142                 len = skb->len - skb_transport_offset(skb);
1143                 th = tcp_hdr(skb);
1144                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1145         }
1146
1147         if (inner_mac_off) { /* tunnel */
1148                 struct udphdr *uh = NULL;
1149                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1150                                             ETH_HLEN - 2));
1151
1152                 if (proto == htons(ETH_P_IP)) {
1153                         struct iphdr *iph = (struct iphdr *)skb->data;
1154
1155                         if (iph->protocol == IPPROTO_UDP)
1156                                 uh = (struct udphdr *)(iph + 1);
1157                 } else {
1158                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1159
1160                         if (iph->nexthdr == IPPROTO_UDP)
1161                                 uh = (struct udphdr *)(iph + 1);
1162                 }
1163                 if (uh) {
1164                         if (uh->check)
1165                                 skb_shinfo(skb)->gso_type |=
1166                                         SKB_GSO_UDP_TUNNEL_CSUM;
1167                         else
1168                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1169                 }
1170         }
1171 #endif
1172         return skb;
1173 }
1174
1175 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1176 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1177
1178 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1179                                            int payload_off, int tcp_ts,
1180                                            struct sk_buff *skb)
1181 {
1182 #ifdef CONFIG_INET
1183         struct tcphdr *th;
1184         int len, nw_off, tcp_opt_len = 0;
1185
1186         if (tcp_ts)
1187                 tcp_opt_len = 12;
1188
1189         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1190                 struct iphdr *iph;
1191
1192                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1193                          ETH_HLEN;
1194                 skb_set_network_header(skb, nw_off);
1195                 iph = ip_hdr(skb);
1196                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1197                 len = skb->len - skb_transport_offset(skb);
1198                 th = tcp_hdr(skb);
1199                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1200         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1201                 struct ipv6hdr *iph;
1202
1203                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1204                          ETH_HLEN;
1205                 skb_set_network_header(skb, nw_off);
1206                 iph = ipv6_hdr(skb);
1207                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1208                 len = skb->len - skb_transport_offset(skb);
1209                 th = tcp_hdr(skb);
1210                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1211         } else {
1212                 dev_kfree_skb_any(skb);
1213                 return NULL;
1214         }
1215
1216         if (nw_off) { /* tunnel */
1217                 struct udphdr *uh = NULL;
1218
1219                 if (skb->protocol == htons(ETH_P_IP)) {
1220                         struct iphdr *iph = (struct iphdr *)skb->data;
1221
1222                         if (iph->protocol == IPPROTO_UDP)
1223                                 uh = (struct udphdr *)(iph + 1);
1224                 } else {
1225                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1226
1227                         if (iph->nexthdr == IPPROTO_UDP)
1228                                 uh = (struct udphdr *)(iph + 1);
1229                 }
1230                 if (uh) {
1231                         if (uh->check)
1232                                 skb_shinfo(skb)->gso_type |=
1233                                         SKB_GSO_UDP_TUNNEL_CSUM;
1234                         else
1235                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1236                 }
1237         }
1238 #endif
1239         return skb;
1240 }
1241
1242 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1243                                            struct bnxt_tpa_info *tpa_info,
1244                                            struct rx_tpa_end_cmp *tpa_end,
1245                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1246                                            struct sk_buff *skb)
1247 {
1248 #ifdef CONFIG_INET
1249         int payload_off;
1250         u16 segs;
1251
1252         segs = TPA_END_TPA_SEGS(tpa_end);
1253         if (segs == 1)
1254                 return skb;
1255
1256         NAPI_GRO_CB(skb)->count = segs;
1257         skb_shinfo(skb)->gso_size =
1258                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1259         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1260         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1261                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1262                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1263         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1264         if (likely(skb))
1265                 tcp_gro_complete(skb);
1266 #endif
1267         return skb;
1268 }
1269
1270 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1271                                            struct bnxt_napi *bnapi,
1272                                            u32 *raw_cons,
1273                                            struct rx_tpa_end_cmp *tpa_end,
1274                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1275                                            u8 *event)
1276 {
1277         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1278         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1279         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1280         u8 *data_ptr, agg_bufs;
1281         u16 cp_cons = RING_CMP(*raw_cons);
1282         unsigned int len;
1283         struct bnxt_tpa_info *tpa_info;
1284         dma_addr_t mapping;
1285         struct sk_buff *skb;
1286         void *data;
1287
1288         if (unlikely(bnapi->in_reset)) {
1289                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1290
1291                 if (rc < 0)
1292                         return ERR_PTR(-EBUSY);
1293                 return NULL;
1294         }
1295
1296         tpa_info = &rxr->rx_tpa[agg_id];
1297         data = tpa_info->data;
1298         data_ptr = tpa_info->data_ptr;
1299         prefetch(data_ptr);
1300         len = tpa_info->len;
1301         mapping = tpa_info->mapping;
1302
1303         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1304                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1305
1306         if (agg_bufs) {
1307                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1308                         return ERR_PTR(-EBUSY);
1309
1310                 *event |= BNXT_AGG_EVENT;
1311                 cp_cons = NEXT_CMP(cp_cons);
1312         }
1313
1314         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1315                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1316                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1317                             agg_bufs, (int)MAX_SKB_FRAGS);
1318                 return NULL;
1319         }
1320
1321         if (len <= bp->rx_copy_thresh) {
1322                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1323                 if (!skb) {
1324                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1325                         return NULL;
1326                 }
1327         } else {
1328                 u8 *new_data;
1329                 dma_addr_t new_mapping;
1330
1331                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1332                 if (!new_data) {
1333                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1334                         return NULL;
1335                 }
1336
1337                 tpa_info->data = new_data;
1338                 tpa_info->data_ptr = new_data + bp->rx_offset;
1339                 tpa_info->mapping = new_mapping;
1340
1341                 skb = build_skb(data, 0);
1342                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1343                                        bp->rx_buf_use_size, bp->rx_dir,
1344                                        DMA_ATTR_WEAK_ORDERING);
1345
1346                 if (!skb) {
1347                         kfree(data);
1348                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1349                         return NULL;
1350                 }
1351                 skb_reserve(skb, bp->rx_offset);
1352                 skb_put(skb, len);
1353         }
1354
1355         if (agg_bufs) {
1356                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1357                 if (!skb) {
1358                         /* Page reuse already handled by bnxt_rx_pages(). */
1359                         return NULL;
1360                 }
1361         }
1362         skb->protocol = eth_type_trans(skb, bp->dev);
1363
1364         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1365                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1366
1367         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1368             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1369                 u16 vlan_proto = tpa_info->metadata >>
1370                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1371                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1372
1373                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1374         }
1375
1376         skb_checksum_none_assert(skb);
1377         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1378                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1379                 skb->csum_level =
1380                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1381         }
1382
1383         if (TPA_END_GRO(tpa_end))
1384                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1385
1386         return skb;
1387 }
1388
1389 /* returns the following:
1390  * 1       - 1 packet successfully received
1391  * 0       - successful TPA_START, packet not completed yet
1392  * -EBUSY  - completion ring does not have all the agg buffers yet
1393  * -ENOMEM - packet aborted due to out of memory
1394  * -EIO    - packet aborted due to hw error indicated in BD
1395  */
1396 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1397                        u8 *event)
1398 {
1399         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1400         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1401         struct net_device *dev = bp->dev;
1402         struct rx_cmp *rxcmp;
1403         struct rx_cmp_ext *rxcmp1;
1404         u32 tmp_raw_cons = *raw_cons;
1405         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1406         struct bnxt_sw_rx_bd *rx_buf;
1407         unsigned int len;
1408         u8 *data_ptr, agg_bufs, cmp_type;
1409         dma_addr_t dma_addr;
1410         struct sk_buff *skb;
1411         void *data;
1412         int rc = 0;
1413         u32 misc;
1414
1415         rxcmp = (struct rx_cmp *)
1416                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1417
1418         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1419         cp_cons = RING_CMP(tmp_raw_cons);
1420         rxcmp1 = (struct rx_cmp_ext *)
1421                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1422
1423         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1424                 return -EBUSY;
1425
1426         cmp_type = RX_CMP_TYPE(rxcmp);
1427
1428         prod = rxr->rx_prod;
1429
1430         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1431                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1432                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1433
1434                 *event |= BNXT_RX_EVENT;
1435                 goto next_rx_no_prod;
1436
1437         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1438                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1439                                    (struct rx_tpa_end_cmp *)rxcmp,
1440                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1441
1442                 if (unlikely(IS_ERR(skb)))
1443                         return -EBUSY;
1444
1445                 rc = -ENOMEM;
1446                 if (likely(skb)) {
1447                         skb_record_rx_queue(skb, bnapi->index);
1448                         napi_gro_receive(&bnapi->napi, skb);
1449                         rc = 1;
1450                 }
1451                 *event |= BNXT_RX_EVENT;
1452                 goto next_rx_no_prod;
1453         }
1454
1455         cons = rxcmp->rx_cmp_opaque;
1456         rx_buf = &rxr->rx_buf_ring[cons];
1457         data = rx_buf->data;
1458         data_ptr = rx_buf->data_ptr;
1459         if (unlikely(cons != rxr->rx_next_cons)) {
1460                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1461
1462                 bnxt_sched_reset(bp, rxr);
1463                 return rc1;
1464         }
1465         prefetch(data_ptr);
1466
1467         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1468         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1469
1470         if (agg_bufs) {
1471                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1472                         return -EBUSY;
1473
1474                 cp_cons = NEXT_CMP(cp_cons);
1475                 *event |= BNXT_AGG_EVENT;
1476         }
1477         *event |= BNXT_RX_EVENT;
1478
1479         rx_buf->data = NULL;
1480         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1481                 bnxt_reuse_rx_data(rxr, cons, data);
1482                 if (agg_bufs)
1483                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1484
1485                 rc = -EIO;
1486                 goto next_rx;
1487         }
1488
1489         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1490         dma_addr = rx_buf->mapping;
1491
1492         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1493                 rc = 1;
1494                 goto next_rx;
1495         }
1496
1497         if (len <= bp->rx_copy_thresh) {
1498                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1499                 bnxt_reuse_rx_data(rxr, cons, data);
1500                 if (!skb) {
1501                         rc = -ENOMEM;
1502                         goto next_rx;
1503                 }
1504         } else {
1505                 u32 payload;
1506
1507                 if (rx_buf->data_ptr == data_ptr)
1508                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1509                 else
1510                         payload = 0;
1511                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1512                                       payload | len);
1513                 if (!skb) {
1514                         rc = -ENOMEM;
1515                         goto next_rx;
1516                 }
1517         }
1518
1519         if (agg_bufs) {
1520                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1521                 if (!skb) {
1522                         rc = -ENOMEM;
1523                         goto next_rx;
1524                 }
1525         }
1526
1527         if (RX_CMP_HASH_VALID(rxcmp)) {
1528                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1529                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1530
1531                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1532                 if (hash_type != 1 && hash_type != 3)
1533                         type = PKT_HASH_TYPE_L3;
1534                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1535         }
1536
1537         skb->protocol = eth_type_trans(skb, dev);
1538
1539         if ((rxcmp1->rx_cmp_flags2 &
1540              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1541             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1542                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1543                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1544                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1545
1546                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1547         }
1548
1549         skb_checksum_none_assert(skb);
1550         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1551                 if (dev->features & NETIF_F_RXCSUM) {
1552                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1553                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1554                 }
1555         } else {
1556                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1557                         if (dev->features & NETIF_F_RXCSUM)
1558                                 cpr->rx_l4_csum_errors++;
1559                 }
1560         }
1561
1562         skb_record_rx_queue(skb, bnapi->index);
1563         napi_gro_receive(&bnapi->napi, skb);
1564         rc = 1;
1565
1566 next_rx:
1567         rxr->rx_prod = NEXT_RX(prod);
1568         rxr->rx_next_cons = NEXT_RX(cons);
1569
1570 next_rx_no_prod:
1571         *raw_cons = tmp_raw_cons;
1572
1573         return rc;
1574 }
1575
1576 #define BNXT_GET_EVENT_PORT(data)       \
1577         ((data) &                       \
1578          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1579
1580 static int bnxt_async_event_process(struct bnxt *bp,
1581                                     struct hwrm_async_event_cmpl *cmpl)
1582 {
1583         u16 event_id = le16_to_cpu(cmpl->event_id);
1584
1585         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1586         switch (event_id) {
1587         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1588                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1589                 struct bnxt_link_info *link_info = &bp->link_info;
1590
1591                 if (BNXT_VF(bp))
1592                         goto async_event_process_exit;
1593                 if (data1 & 0x20000) {
1594                         u16 fw_speed = link_info->force_link_speed;
1595                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1596
1597                         netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1598                                     speed);
1599                 }
1600                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1601                 /* fall thru */
1602         }
1603         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1604                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1605                 break;
1606         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1607                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1608                 break;
1609         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1610                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1611                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1612
1613                 if (BNXT_VF(bp))
1614                         break;
1615
1616                 if (bp->pf.port_id != port_id)
1617                         break;
1618
1619                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1620                 break;
1621         }
1622         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1623                 if (BNXT_PF(bp))
1624                         goto async_event_process_exit;
1625                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1626                 break;
1627         default:
1628                 goto async_event_process_exit;
1629         }
1630         schedule_work(&bp->sp_task);
1631 async_event_process_exit:
1632         bnxt_ulp_async_events(bp, cmpl);
1633         return 0;
1634 }
1635
1636 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1637 {
1638         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1639         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1640         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1641                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1642
1643         switch (cmpl_type) {
1644         case CMPL_BASE_TYPE_HWRM_DONE:
1645                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1646                 if (seq_id == bp->hwrm_intr_seq_id)
1647                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1648                 else
1649                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1650                 break;
1651
1652         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1653                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1654
1655                 if ((vf_id < bp->pf.first_vf_id) ||
1656                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1657                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1658                                    vf_id);
1659                         return -EINVAL;
1660                 }
1661
1662                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1663                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1664                 schedule_work(&bp->sp_task);
1665                 break;
1666
1667         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1668                 bnxt_async_event_process(bp,
1669                                          (struct hwrm_async_event_cmpl *)txcmp);
1670
1671         default:
1672                 break;
1673         }
1674
1675         return 0;
1676 }
1677
1678 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1679 {
1680         struct bnxt_napi *bnapi = dev_instance;
1681         struct bnxt *bp = bnapi->bp;
1682         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1683         u32 cons = RING_CMP(cpr->cp_raw_cons);
1684
1685         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1686         napi_schedule(&bnapi->napi);
1687         return IRQ_HANDLED;
1688 }
1689
1690 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1691 {
1692         u32 raw_cons = cpr->cp_raw_cons;
1693         u16 cons = RING_CMP(raw_cons);
1694         struct tx_cmp *txcmp;
1695
1696         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1697
1698         return TX_CMP_VALID(txcmp, raw_cons);
1699 }
1700
1701 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1702 {
1703         struct bnxt_napi *bnapi = dev_instance;
1704         struct bnxt *bp = bnapi->bp;
1705         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1706         u32 cons = RING_CMP(cpr->cp_raw_cons);
1707         u32 int_status;
1708
1709         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1710
1711         if (!bnxt_has_work(bp, cpr)) {
1712                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1713                 /* return if erroneous interrupt */
1714                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1715                         return IRQ_NONE;
1716         }
1717
1718         /* disable ring IRQ */
1719         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1720
1721         /* Return here if interrupt is shared and is disabled. */
1722         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1723                 return IRQ_HANDLED;
1724
1725         napi_schedule(&bnapi->napi);
1726         return IRQ_HANDLED;
1727 }
1728
1729 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1730 {
1731         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1732         u32 raw_cons = cpr->cp_raw_cons;
1733         u32 cons;
1734         int tx_pkts = 0;
1735         int rx_pkts = 0;
1736         u8 event = 0;
1737         struct tx_cmp *txcmp;
1738
1739         while (1) {
1740                 int rc;
1741
1742                 cons = RING_CMP(raw_cons);
1743                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1744
1745                 if (!TX_CMP_VALID(txcmp, raw_cons))
1746                         break;
1747
1748                 /* The valid test of the entry must be done first before
1749                  * reading any further.
1750                  */
1751                 dma_rmb();
1752                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1753                         tx_pkts++;
1754                         /* return full budget so NAPI will complete. */
1755                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1756                                 rx_pkts = budget;
1757                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1758                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1759                         if (likely(rc >= 0))
1760                                 rx_pkts += rc;
1761                         else if (rc == -EBUSY)  /* partial completion */
1762                                 break;
1763                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1764                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1765                                     (TX_CMP_TYPE(txcmp) ==
1766                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1767                                     (TX_CMP_TYPE(txcmp) ==
1768                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1769                         bnxt_hwrm_handler(bp, txcmp);
1770                 }
1771                 raw_cons = NEXT_RAW_CMP(raw_cons);
1772
1773                 if (rx_pkts == budget)
1774                         break;
1775         }
1776
1777         if (event & BNXT_TX_EVENT) {
1778                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1779                 void __iomem *db = txr->tx_doorbell;
1780                 u16 prod = txr->tx_prod;
1781
1782                 /* Sync BD data before updating doorbell */
1783                 wmb();
1784
1785                 bnxt_db_write(bp, db, DB_KEY_TX | prod);
1786         }
1787
1788         cpr->cp_raw_cons = raw_cons;
1789         /* ACK completion ring before freeing tx ring and producing new
1790          * buffers in rx/agg rings to prevent overflowing the completion
1791          * ring.
1792          */
1793         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1794
1795         if (tx_pkts)
1796                 bnapi->tx_int(bp, bnapi, tx_pkts);
1797
1798         if (event & BNXT_RX_EVENT) {
1799                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1800
1801                 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1802                 if (event & BNXT_AGG_EVENT)
1803                         bnxt_db_write(bp, rxr->rx_agg_doorbell,
1804                                       DB_KEY_RX | rxr->rx_agg_prod);
1805         }
1806         return rx_pkts;
1807 }
1808
1809 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1810 {
1811         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1812         struct bnxt *bp = bnapi->bp;
1813         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1814         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1815         struct tx_cmp *txcmp;
1816         struct rx_cmp_ext *rxcmp1;
1817         u32 cp_cons, tmp_raw_cons;
1818         u32 raw_cons = cpr->cp_raw_cons;
1819         u32 rx_pkts = 0;
1820         u8 event = 0;
1821
1822         while (1) {
1823                 int rc;
1824
1825                 cp_cons = RING_CMP(raw_cons);
1826                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1827
1828                 if (!TX_CMP_VALID(txcmp, raw_cons))
1829                         break;
1830
1831                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1832                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1833                         cp_cons = RING_CMP(tmp_raw_cons);
1834                         rxcmp1 = (struct rx_cmp_ext *)
1835                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1836
1837                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1838                                 break;
1839
1840                         /* force an error to recycle the buffer */
1841                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1842                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1843
1844                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1845                         if (likely(rc == -EIO))
1846                                 rx_pkts++;
1847                         else if (rc == -EBUSY)  /* partial completion */
1848                                 break;
1849                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1850                                     CMPL_BASE_TYPE_HWRM_DONE)) {
1851                         bnxt_hwrm_handler(bp, txcmp);
1852                 } else {
1853                         netdev_err(bp->dev,
1854                                    "Invalid completion received on special ring\n");
1855                 }
1856                 raw_cons = NEXT_RAW_CMP(raw_cons);
1857
1858                 if (rx_pkts == budget)
1859                         break;
1860         }
1861
1862         cpr->cp_raw_cons = raw_cons;
1863         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1864         bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1865
1866         if (event & BNXT_AGG_EVENT)
1867                 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1868                               DB_KEY_RX | rxr->rx_agg_prod);
1869
1870         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1871                 napi_complete_done(napi, rx_pkts);
1872                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1873         }
1874         return rx_pkts;
1875 }
1876
1877 static int bnxt_poll(struct napi_struct *napi, int budget)
1878 {
1879         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1880         struct bnxt *bp = bnapi->bp;
1881         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1882         int work_done = 0;
1883
1884         while (1) {
1885                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1886
1887                 if (work_done >= budget)
1888                         break;
1889
1890                 if (!bnxt_has_work(bp, cpr)) {
1891                         if (napi_complete_done(napi, work_done))
1892                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
1893                                                  cpr->cp_raw_cons);
1894                         break;
1895                 }
1896         }
1897         mmiowb();
1898         return work_done;
1899 }
1900
1901 static void bnxt_free_tx_skbs(struct bnxt *bp)
1902 {
1903         int i, max_idx;
1904         struct pci_dev *pdev = bp->pdev;
1905
1906         if (!bp->tx_ring)
1907                 return;
1908
1909         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1910         for (i = 0; i < bp->tx_nr_rings; i++) {
1911                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1912                 int j;
1913
1914                 for (j = 0; j < max_idx;) {
1915                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1916                         struct sk_buff *skb = tx_buf->skb;
1917                         int k, last;
1918
1919                         if (!skb) {
1920                                 j++;
1921                                 continue;
1922                         }
1923
1924                         tx_buf->skb = NULL;
1925
1926                         if (tx_buf->is_push) {
1927                                 dev_kfree_skb(skb);
1928                                 j += 2;
1929                                 continue;
1930                         }
1931
1932                         dma_unmap_single(&pdev->dev,
1933                                          dma_unmap_addr(tx_buf, mapping),
1934                                          skb_headlen(skb),
1935                                          PCI_DMA_TODEVICE);
1936
1937                         last = tx_buf->nr_frags;
1938                         j += 2;
1939                         for (k = 0; k < last; k++, j++) {
1940                                 int ring_idx = j & bp->tx_ring_mask;
1941                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1942
1943                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1944                                 dma_unmap_page(
1945                                         &pdev->dev,
1946                                         dma_unmap_addr(tx_buf, mapping),
1947                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1948                         }
1949                         dev_kfree_skb(skb);
1950                 }
1951                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1952         }
1953 }
1954
1955 static void bnxt_free_rx_skbs(struct bnxt *bp)
1956 {
1957         int i, max_idx, max_agg_idx;
1958         struct pci_dev *pdev = bp->pdev;
1959
1960         if (!bp->rx_ring)
1961                 return;
1962
1963         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1964         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1965         for (i = 0; i < bp->rx_nr_rings; i++) {
1966                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1967                 int j;
1968
1969                 if (rxr->rx_tpa) {
1970                         for (j = 0; j < MAX_TPA; j++) {
1971                                 struct bnxt_tpa_info *tpa_info =
1972                                                         &rxr->rx_tpa[j];
1973                                 u8 *data = tpa_info->data;
1974
1975                                 if (!data)
1976                                         continue;
1977
1978                                 dma_unmap_single_attrs(&pdev->dev,
1979                                                        tpa_info->mapping,
1980                                                        bp->rx_buf_use_size,
1981                                                        bp->rx_dir,
1982                                                        DMA_ATTR_WEAK_ORDERING);
1983
1984                                 tpa_info->data = NULL;
1985
1986                                 kfree(data);
1987                         }
1988                 }
1989
1990                 for (j = 0; j < max_idx; j++) {
1991                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1992                         dma_addr_t mapping = rx_buf->mapping;
1993                         void *data = rx_buf->data;
1994
1995                         if (!data)
1996                                 continue;
1997
1998                         rx_buf->data = NULL;
1999
2000                         if (BNXT_RX_PAGE_MODE(bp)) {
2001                                 mapping -= bp->rx_dma_offset;
2002                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2003                                                      PAGE_SIZE, bp->rx_dir,
2004                                                      DMA_ATTR_WEAK_ORDERING);
2005                                 __free_page(data);
2006                         } else {
2007                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2008                                                        bp->rx_buf_use_size,
2009                                                        bp->rx_dir,
2010                                                        DMA_ATTR_WEAK_ORDERING);
2011                                 kfree(data);
2012                         }
2013                 }
2014
2015                 for (j = 0; j < max_agg_idx; j++) {
2016                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2017                                 &rxr->rx_agg_ring[j];
2018                         struct page *page = rx_agg_buf->page;
2019
2020                         if (!page)
2021                                 continue;
2022
2023                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2024                                              BNXT_RX_PAGE_SIZE,
2025                                              PCI_DMA_FROMDEVICE,
2026                                              DMA_ATTR_WEAK_ORDERING);
2027
2028                         rx_agg_buf->page = NULL;
2029                         __clear_bit(j, rxr->rx_agg_bmap);
2030
2031                         __free_page(page);
2032                 }
2033                 if (rxr->rx_page) {
2034                         __free_page(rxr->rx_page);
2035                         rxr->rx_page = NULL;
2036                 }
2037         }
2038 }
2039
2040 static void bnxt_free_skbs(struct bnxt *bp)
2041 {
2042         bnxt_free_tx_skbs(bp);
2043         bnxt_free_rx_skbs(bp);
2044 }
2045
2046 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2047 {
2048         struct pci_dev *pdev = bp->pdev;
2049         int i;
2050
2051         for (i = 0; i < ring->nr_pages; i++) {
2052                 if (!ring->pg_arr[i])
2053                         continue;
2054
2055                 dma_free_coherent(&pdev->dev, ring->page_size,
2056                                   ring->pg_arr[i], ring->dma_arr[i]);
2057
2058                 ring->pg_arr[i] = NULL;
2059         }
2060         if (ring->pg_tbl) {
2061                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2062                                   ring->pg_tbl, ring->pg_tbl_map);
2063                 ring->pg_tbl = NULL;
2064         }
2065         if (ring->vmem_size && *ring->vmem) {
2066                 vfree(*ring->vmem);
2067                 *ring->vmem = NULL;
2068         }
2069 }
2070
2071 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2072 {
2073         int i;
2074         struct pci_dev *pdev = bp->pdev;
2075
2076         if (ring->nr_pages > 1) {
2077                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2078                                                   ring->nr_pages * 8,
2079                                                   &ring->pg_tbl_map,
2080                                                   GFP_KERNEL);
2081                 if (!ring->pg_tbl)
2082                         return -ENOMEM;
2083         }
2084
2085         for (i = 0; i < ring->nr_pages; i++) {
2086                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2087                                                      ring->page_size,
2088                                                      &ring->dma_arr[i],
2089                                                      GFP_KERNEL);
2090                 if (!ring->pg_arr[i])
2091                         return -ENOMEM;
2092
2093                 if (ring->nr_pages > 1)
2094                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2095         }
2096
2097         if (ring->vmem_size) {
2098                 *ring->vmem = vzalloc(ring->vmem_size);
2099                 if (!(*ring->vmem))
2100                         return -ENOMEM;
2101         }
2102         return 0;
2103 }
2104
2105 static void bnxt_free_rx_rings(struct bnxt *bp)
2106 {
2107         int i;
2108
2109         if (!bp->rx_ring)
2110                 return;
2111
2112         for (i = 0; i < bp->rx_nr_rings; i++) {
2113                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2114                 struct bnxt_ring_struct *ring;
2115
2116                 if (rxr->xdp_prog)
2117                         bpf_prog_put(rxr->xdp_prog);
2118
2119                 kfree(rxr->rx_tpa);
2120                 rxr->rx_tpa = NULL;
2121
2122                 kfree(rxr->rx_agg_bmap);
2123                 rxr->rx_agg_bmap = NULL;
2124
2125                 ring = &rxr->rx_ring_struct;
2126                 bnxt_free_ring(bp, ring);
2127
2128                 ring = &rxr->rx_agg_ring_struct;
2129                 bnxt_free_ring(bp, ring);
2130         }
2131 }
2132
2133 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2134 {
2135         int i, rc, agg_rings = 0, tpa_rings = 0;
2136
2137         if (!bp->rx_ring)
2138                 return -ENOMEM;
2139
2140         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2141                 agg_rings = 1;
2142
2143         if (bp->flags & BNXT_FLAG_TPA)
2144                 tpa_rings = 1;
2145
2146         for (i = 0; i < bp->rx_nr_rings; i++) {
2147                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2148                 struct bnxt_ring_struct *ring;
2149
2150                 ring = &rxr->rx_ring_struct;
2151
2152                 rc = bnxt_alloc_ring(bp, ring);
2153                 if (rc)
2154                         return rc;
2155
2156                 if (agg_rings) {
2157                         u16 mem_size;
2158
2159                         ring = &rxr->rx_agg_ring_struct;
2160                         rc = bnxt_alloc_ring(bp, ring);
2161                         if (rc)
2162                                 return rc;
2163
2164                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2165                         mem_size = rxr->rx_agg_bmap_size / 8;
2166                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2167                         if (!rxr->rx_agg_bmap)
2168                                 return -ENOMEM;
2169
2170                         if (tpa_rings) {
2171                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2172                                                 sizeof(struct bnxt_tpa_info),
2173                                                 GFP_KERNEL);
2174                                 if (!rxr->rx_tpa)
2175                                         return -ENOMEM;
2176                         }
2177                 }
2178         }
2179         return 0;
2180 }
2181
2182 static void bnxt_free_tx_rings(struct bnxt *bp)
2183 {
2184         int i;
2185         struct pci_dev *pdev = bp->pdev;
2186
2187         if (!bp->tx_ring)
2188                 return;
2189
2190         for (i = 0; i < bp->tx_nr_rings; i++) {
2191                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2192                 struct bnxt_ring_struct *ring;
2193
2194                 if (txr->tx_push) {
2195                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2196                                           txr->tx_push, txr->tx_push_mapping);
2197                         txr->tx_push = NULL;
2198                 }
2199
2200                 ring = &txr->tx_ring_struct;
2201
2202                 bnxt_free_ring(bp, ring);
2203         }
2204 }
2205
2206 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2207 {
2208         int i, j, rc;
2209         struct pci_dev *pdev = bp->pdev;
2210
2211         bp->tx_push_size = 0;
2212         if (bp->tx_push_thresh) {
2213                 int push_size;
2214
2215                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2216                                         bp->tx_push_thresh);
2217
2218                 if (push_size > 256) {
2219                         push_size = 0;
2220                         bp->tx_push_thresh = 0;
2221                 }
2222
2223                 bp->tx_push_size = push_size;
2224         }
2225
2226         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2227                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2228                 struct bnxt_ring_struct *ring;
2229
2230                 ring = &txr->tx_ring_struct;
2231
2232                 rc = bnxt_alloc_ring(bp, ring);
2233                 if (rc)
2234                         return rc;
2235
2236                 if (bp->tx_push_size) {
2237                         dma_addr_t mapping;
2238
2239                         /* One pre-allocated DMA buffer to backup
2240                          * TX push operation
2241                          */
2242                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2243                                                 bp->tx_push_size,
2244                                                 &txr->tx_push_mapping,
2245                                                 GFP_KERNEL);
2246
2247                         if (!txr->tx_push)
2248                                 return -ENOMEM;
2249
2250                         mapping = txr->tx_push_mapping +
2251                                 sizeof(struct tx_push_bd);
2252                         txr->data_mapping = cpu_to_le64(mapping);
2253
2254                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2255                 }
2256                 ring->queue_id = bp->q_info[j].queue_id;
2257                 if (i < bp->tx_nr_rings_xdp)
2258                         continue;
2259                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2260                         j++;
2261         }
2262         return 0;
2263 }
2264
2265 static void bnxt_free_cp_rings(struct bnxt *bp)
2266 {
2267         int i;
2268
2269         if (!bp->bnapi)
2270                 return;
2271
2272         for (i = 0; i < bp->cp_nr_rings; i++) {
2273                 struct bnxt_napi *bnapi = bp->bnapi[i];
2274                 struct bnxt_cp_ring_info *cpr;
2275                 struct bnxt_ring_struct *ring;
2276
2277                 if (!bnapi)
2278                         continue;
2279
2280                 cpr = &bnapi->cp_ring;
2281                 ring = &cpr->cp_ring_struct;
2282
2283                 bnxt_free_ring(bp, ring);
2284         }
2285 }
2286
2287 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2288 {
2289         int i, rc;
2290
2291         for (i = 0; i < bp->cp_nr_rings; i++) {
2292                 struct bnxt_napi *bnapi = bp->bnapi[i];
2293                 struct bnxt_cp_ring_info *cpr;
2294                 struct bnxt_ring_struct *ring;
2295
2296                 if (!bnapi)
2297                         continue;
2298
2299                 cpr = &bnapi->cp_ring;
2300                 ring = &cpr->cp_ring_struct;
2301
2302                 rc = bnxt_alloc_ring(bp, ring);
2303                 if (rc)
2304                         return rc;
2305         }
2306         return 0;
2307 }
2308
2309 static void bnxt_init_ring_struct(struct bnxt *bp)
2310 {
2311         int i;
2312
2313         for (i = 0; i < bp->cp_nr_rings; i++) {
2314                 struct bnxt_napi *bnapi = bp->bnapi[i];
2315                 struct bnxt_cp_ring_info *cpr;
2316                 struct bnxt_rx_ring_info *rxr;
2317                 struct bnxt_tx_ring_info *txr;
2318                 struct bnxt_ring_struct *ring;
2319
2320                 if (!bnapi)
2321                         continue;
2322
2323                 cpr = &bnapi->cp_ring;
2324                 ring = &cpr->cp_ring_struct;
2325                 ring->nr_pages = bp->cp_nr_pages;
2326                 ring->page_size = HW_CMPD_RING_SIZE;
2327                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2328                 ring->dma_arr = cpr->cp_desc_mapping;
2329                 ring->vmem_size = 0;
2330
2331                 rxr = bnapi->rx_ring;
2332                 if (!rxr)
2333                         goto skip_rx;
2334
2335                 ring = &rxr->rx_ring_struct;
2336                 ring->nr_pages = bp->rx_nr_pages;
2337                 ring->page_size = HW_RXBD_RING_SIZE;
2338                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2339                 ring->dma_arr = rxr->rx_desc_mapping;
2340                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2341                 ring->vmem = (void **)&rxr->rx_buf_ring;
2342
2343                 ring = &rxr->rx_agg_ring_struct;
2344                 ring->nr_pages = bp->rx_agg_nr_pages;
2345                 ring->page_size = HW_RXBD_RING_SIZE;
2346                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2347                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2348                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2349                 ring->vmem = (void **)&rxr->rx_agg_ring;
2350
2351 skip_rx:
2352                 txr = bnapi->tx_ring;
2353                 if (!txr)
2354                         continue;
2355
2356                 ring = &txr->tx_ring_struct;
2357                 ring->nr_pages = bp->tx_nr_pages;
2358                 ring->page_size = HW_RXBD_RING_SIZE;
2359                 ring->pg_arr = (void **)txr->tx_desc_ring;
2360                 ring->dma_arr = txr->tx_desc_mapping;
2361                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2362                 ring->vmem = (void **)&txr->tx_buf_ring;
2363         }
2364 }
2365
2366 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2367 {
2368         int i;
2369         u32 prod;
2370         struct rx_bd **rx_buf_ring;
2371
2372         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2373         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2374                 int j;
2375                 struct rx_bd *rxbd;
2376
2377                 rxbd = rx_buf_ring[i];
2378                 if (!rxbd)
2379                         continue;
2380
2381                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2382                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2383                         rxbd->rx_bd_opaque = prod;
2384                 }
2385         }
2386 }
2387
2388 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2389 {
2390         struct net_device *dev = bp->dev;
2391         struct bnxt_rx_ring_info *rxr;
2392         struct bnxt_ring_struct *ring;
2393         u32 prod, type;
2394         int i;
2395
2396         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2397                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2398
2399         if (NET_IP_ALIGN == 2)
2400                 type |= RX_BD_FLAGS_SOP;
2401
2402         rxr = &bp->rx_ring[ring_nr];
2403         ring = &rxr->rx_ring_struct;
2404         bnxt_init_rxbd_pages(ring, type);
2405
2406         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2407                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2408                 if (IS_ERR(rxr->xdp_prog)) {
2409                         int rc = PTR_ERR(rxr->xdp_prog);
2410
2411                         rxr->xdp_prog = NULL;
2412                         return rc;
2413                 }
2414         }
2415         prod = rxr->rx_prod;
2416         for (i = 0; i < bp->rx_ring_size; i++) {
2417                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2418                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2419                                     ring_nr, i, bp->rx_ring_size);
2420                         break;
2421                 }
2422                 prod = NEXT_RX(prod);
2423         }
2424         rxr->rx_prod = prod;
2425         ring->fw_ring_id = INVALID_HW_RING_ID;
2426
2427         ring = &rxr->rx_agg_ring_struct;
2428         ring->fw_ring_id = INVALID_HW_RING_ID;
2429
2430         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2431                 return 0;
2432
2433         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2434                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2435
2436         bnxt_init_rxbd_pages(ring, type);
2437
2438         prod = rxr->rx_agg_prod;
2439         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2440                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2441                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2442                                     ring_nr, i, bp->rx_ring_size);
2443                         break;
2444                 }
2445                 prod = NEXT_RX_AGG(prod);
2446         }
2447         rxr->rx_agg_prod = prod;
2448
2449         if (bp->flags & BNXT_FLAG_TPA) {
2450                 if (rxr->rx_tpa) {
2451                         u8 *data;
2452                         dma_addr_t mapping;
2453
2454                         for (i = 0; i < MAX_TPA; i++) {
2455                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2456                                                             GFP_KERNEL);
2457                                 if (!data)
2458                                         return -ENOMEM;
2459
2460                                 rxr->rx_tpa[i].data = data;
2461                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2462                                 rxr->rx_tpa[i].mapping = mapping;
2463                         }
2464                 } else {
2465                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2466                         return -ENOMEM;
2467                 }
2468         }
2469
2470         return 0;
2471 }
2472
2473 static void bnxt_init_cp_rings(struct bnxt *bp)
2474 {
2475         int i;
2476
2477         for (i = 0; i < bp->cp_nr_rings; i++) {
2478                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2479                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2480
2481                 ring->fw_ring_id = INVALID_HW_RING_ID;
2482         }
2483 }
2484
2485 static int bnxt_init_rx_rings(struct bnxt *bp)
2486 {
2487         int i, rc = 0;
2488
2489         if (BNXT_RX_PAGE_MODE(bp)) {
2490                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2491                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2492         } else {
2493                 bp->rx_offset = BNXT_RX_OFFSET;
2494                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2495         }
2496
2497         for (i = 0; i < bp->rx_nr_rings; i++) {
2498                 rc = bnxt_init_one_rx_ring(bp, i);
2499                 if (rc)
2500                         break;
2501         }
2502
2503         return rc;
2504 }
2505
2506 static int bnxt_init_tx_rings(struct bnxt *bp)
2507 {
2508         u16 i;
2509
2510         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2511                                    MAX_SKB_FRAGS + 1);
2512
2513         for (i = 0; i < bp->tx_nr_rings; i++) {
2514                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2515                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2516
2517                 ring->fw_ring_id = INVALID_HW_RING_ID;
2518         }
2519
2520         return 0;
2521 }
2522
2523 static void bnxt_free_ring_grps(struct bnxt *bp)
2524 {
2525         kfree(bp->grp_info);
2526         bp->grp_info = NULL;
2527 }
2528
2529 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2530 {
2531         int i;
2532
2533         if (irq_re_init) {
2534                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2535                                        sizeof(struct bnxt_ring_grp_info),
2536                                        GFP_KERNEL);
2537                 if (!bp->grp_info)
2538                         return -ENOMEM;
2539         }
2540         for (i = 0; i < bp->cp_nr_rings; i++) {
2541                 if (irq_re_init)
2542                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2543                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2544                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2545                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2546                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2547         }
2548         return 0;
2549 }
2550
2551 static void bnxt_free_vnics(struct bnxt *bp)
2552 {
2553         kfree(bp->vnic_info);
2554         bp->vnic_info = NULL;
2555         bp->nr_vnics = 0;
2556 }
2557
2558 static int bnxt_alloc_vnics(struct bnxt *bp)
2559 {
2560         int num_vnics = 1;
2561
2562 #ifdef CONFIG_RFS_ACCEL
2563         if (bp->flags & BNXT_FLAG_RFS)
2564                 num_vnics += bp->rx_nr_rings;
2565 #endif
2566
2567         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2568                 num_vnics++;
2569
2570         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2571                                 GFP_KERNEL);
2572         if (!bp->vnic_info)
2573                 return -ENOMEM;
2574
2575         bp->nr_vnics = num_vnics;
2576         return 0;
2577 }
2578
2579 static void bnxt_init_vnics(struct bnxt *bp)
2580 {
2581         int i;
2582
2583         for (i = 0; i < bp->nr_vnics; i++) {
2584                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2585
2586                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2587                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2588                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2589                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2590
2591                 if (bp->vnic_info[i].rss_hash_key) {
2592                         if (i == 0)
2593                                 prandom_bytes(vnic->rss_hash_key,
2594                                               HW_HASH_KEY_SIZE);
2595                         else
2596                                 memcpy(vnic->rss_hash_key,
2597                                        bp->vnic_info[0].rss_hash_key,
2598                                        HW_HASH_KEY_SIZE);
2599                 }
2600         }
2601 }
2602
2603 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2604 {
2605         int pages;
2606
2607         pages = ring_size / desc_per_pg;
2608
2609         if (!pages)
2610                 return 1;
2611
2612         pages++;
2613
2614         while (pages & (pages - 1))
2615                 pages++;
2616
2617         return pages;
2618 }
2619
2620 void bnxt_set_tpa_flags(struct bnxt *bp)
2621 {
2622         bp->flags &= ~BNXT_FLAG_TPA;
2623         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2624                 return;
2625         if (bp->dev->features & NETIF_F_LRO)
2626                 bp->flags |= BNXT_FLAG_LRO;
2627         if (bp->dev->features & NETIF_F_GRO)
2628                 bp->flags |= BNXT_FLAG_GRO;
2629 }
2630
2631 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2632  * be set on entry.
2633  */
2634 void bnxt_set_ring_params(struct bnxt *bp)
2635 {
2636         u32 ring_size, rx_size, rx_space;
2637         u32 agg_factor = 0, agg_ring_size = 0;
2638
2639         /* 8 for CRC and VLAN */
2640         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2641
2642         rx_space = rx_size + NET_SKB_PAD +
2643                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2644
2645         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2646         ring_size = bp->rx_ring_size;
2647         bp->rx_agg_ring_size = 0;
2648         bp->rx_agg_nr_pages = 0;
2649
2650         if (bp->flags & BNXT_FLAG_TPA)
2651                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2652
2653         bp->flags &= ~BNXT_FLAG_JUMBO;
2654         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2655                 u32 jumbo_factor;
2656
2657                 bp->flags |= BNXT_FLAG_JUMBO;
2658                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2659                 if (jumbo_factor > agg_factor)
2660                         agg_factor = jumbo_factor;
2661         }
2662         agg_ring_size = ring_size * agg_factor;
2663
2664         if (agg_ring_size) {
2665                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2666                                                         RX_DESC_CNT);
2667                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2668                         u32 tmp = agg_ring_size;
2669
2670                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2671                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2672                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2673                                     tmp, agg_ring_size);
2674                 }
2675                 bp->rx_agg_ring_size = agg_ring_size;
2676                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2677                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2678                 rx_space = rx_size + NET_SKB_PAD +
2679                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2680         }
2681
2682         bp->rx_buf_use_size = rx_size;
2683         bp->rx_buf_size = rx_space;
2684
2685         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2686         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2687
2688         ring_size = bp->tx_ring_size;
2689         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2690         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2691
2692         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2693         bp->cp_ring_size = ring_size;
2694
2695         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2696         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2697                 bp->cp_nr_pages = MAX_CP_PAGES;
2698                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2699                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2700                             ring_size, bp->cp_ring_size);
2701         }
2702         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2703         bp->cp_ring_mask = bp->cp_bit - 1;
2704 }
2705
2706 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2707 {
2708         if (page_mode) {
2709                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2710                         return -EOPNOTSUPP;
2711                 bp->dev->max_mtu = BNXT_MAX_PAGE_MODE_MTU;
2712                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2713                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2714                 bp->dev->hw_features &= ~NETIF_F_LRO;
2715                 bp->dev->features &= ~NETIF_F_LRO;
2716                 bp->rx_dir = DMA_BIDIRECTIONAL;
2717                 bp->rx_skb_func = bnxt_rx_page_skb;
2718         } else {
2719                 bp->dev->max_mtu = BNXT_MAX_MTU;
2720                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2721                 bp->rx_dir = DMA_FROM_DEVICE;
2722                 bp->rx_skb_func = bnxt_rx_skb;
2723         }
2724         return 0;
2725 }
2726
2727 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2728 {
2729         int i;
2730         struct bnxt_vnic_info *vnic;
2731         struct pci_dev *pdev = bp->pdev;
2732
2733         if (!bp->vnic_info)
2734                 return;
2735
2736         for (i = 0; i < bp->nr_vnics; i++) {
2737                 vnic = &bp->vnic_info[i];
2738
2739                 kfree(vnic->fw_grp_ids);
2740                 vnic->fw_grp_ids = NULL;
2741
2742                 kfree(vnic->uc_list);
2743                 vnic->uc_list = NULL;
2744
2745                 if (vnic->mc_list) {
2746                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2747                                           vnic->mc_list, vnic->mc_list_mapping);
2748                         vnic->mc_list = NULL;
2749                 }
2750
2751                 if (vnic->rss_table) {
2752                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2753                                           vnic->rss_table,
2754                                           vnic->rss_table_dma_addr);
2755                         vnic->rss_table = NULL;
2756                 }
2757
2758                 vnic->rss_hash_key = NULL;
2759                 vnic->flags = 0;
2760         }
2761 }
2762
2763 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2764 {
2765         int i, rc = 0, size;
2766         struct bnxt_vnic_info *vnic;
2767         struct pci_dev *pdev = bp->pdev;
2768         int max_rings;
2769
2770         for (i = 0; i < bp->nr_vnics; i++) {
2771                 vnic = &bp->vnic_info[i];
2772
2773                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2774                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2775
2776                         if (mem_size > 0) {
2777                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2778                                 if (!vnic->uc_list) {
2779                                         rc = -ENOMEM;
2780                                         goto out;
2781                                 }
2782                         }
2783                 }
2784
2785                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2786                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2787                         vnic->mc_list =
2788                                 dma_alloc_coherent(&pdev->dev,
2789                                                    vnic->mc_list_size,
2790                                                    &vnic->mc_list_mapping,
2791                                                    GFP_KERNEL);
2792                         if (!vnic->mc_list) {
2793                                 rc = -ENOMEM;
2794                                 goto out;
2795                         }
2796                 }
2797
2798                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2799                         max_rings = bp->rx_nr_rings;
2800                 else
2801                         max_rings = 1;
2802
2803                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2804                 if (!vnic->fw_grp_ids) {
2805                         rc = -ENOMEM;
2806                         goto out;
2807                 }
2808
2809                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2810                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2811                         continue;
2812
2813                 /* Allocate rss table and hash key */
2814                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2815                                                      &vnic->rss_table_dma_addr,
2816                                                      GFP_KERNEL);
2817                 if (!vnic->rss_table) {
2818                         rc = -ENOMEM;
2819                         goto out;
2820                 }
2821
2822                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2823
2824                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2825                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2826         }
2827         return 0;
2828
2829 out:
2830         return rc;
2831 }
2832
2833 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2834 {
2835         struct pci_dev *pdev = bp->pdev;
2836
2837         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2838                           bp->hwrm_cmd_resp_dma_addr);
2839
2840         bp->hwrm_cmd_resp_addr = NULL;
2841         if (bp->hwrm_dbg_resp_addr) {
2842                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2843                                   bp->hwrm_dbg_resp_addr,
2844                                   bp->hwrm_dbg_resp_dma_addr);
2845
2846                 bp->hwrm_dbg_resp_addr = NULL;
2847         }
2848 }
2849
2850 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2851 {
2852         struct pci_dev *pdev = bp->pdev;
2853
2854         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2855                                                    &bp->hwrm_cmd_resp_dma_addr,
2856                                                    GFP_KERNEL);
2857         if (!bp->hwrm_cmd_resp_addr)
2858                 return -ENOMEM;
2859         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2860                                                     HWRM_DBG_REG_BUF_SIZE,
2861                                                     &bp->hwrm_dbg_resp_dma_addr,
2862                                                     GFP_KERNEL);
2863         if (!bp->hwrm_dbg_resp_addr)
2864                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2865
2866         return 0;
2867 }
2868
2869 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
2870 {
2871         if (bp->hwrm_short_cmd_req_addr) {
2872                 struct pci_dev *pdev = bp->pdev;
2873
2874                 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
2875                                   bp->hwrm_short_cmd_req_addr,
2876                                   bp->hwrm_short_cmd_req_dma_addr);
2877                 bp->hwrm_short_cmd_req_addr = NULL;
2878         }
2879 }
2880
2881 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
2882 {
2883         struct pci_dev *pdev = bp->pdev;
2884
2885         bp->hwrm_short_cmd_req_addr =
2886                 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
2887                                    &bp->hwrm_short_cmd_req_dma_addr,
2888                                    GFP_KERNEL);
2889         if (!bp->hwrm_short_cmd_req_addr)
2890                 return -ENOMEM;
2891
2892         return 0;
2893 }
2894
2895 static void bnxt_free_stats(struct bnxt *bp)
2896 {
2897         u32 size, i;
2898         struct pci_dev *pdev = bp->pdev;
2899
2900         if (bp->hw_rx_port_stats) {
2901                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2902                                   bp->hw_rx_port_stats,
2903                                   bp->hw_rx_port_stats_map);
2904                 bp->hw_rx_port_stats = NULL;
2905                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2906         }
2907
2908         if (!bp->bnapi)
2909                 return;
2910
2911         size = sizeof(struct ctx_hw_stats);
2912
2913         for (i = 0; i < bp->cp_nr_rings; i++) {
2914                 struct bnxt_napi *bnapi = bp->bnapi[i];
2915                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2916
2917                 if (cpr->hw_stats) {
2918                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2919                                           cpr->hw_stats_map);
2920                         cpr->hw_stats = NULL;
2921                 }
2922         }
2923 }
2924
2925 static int bnxt_alloc_stats(struct bnxt *bp)
2926 {
2927         u32 size, i;
2928         struct pci_dev *pdev = bp->pdev;
2929
2930         size = sizeof(struct ctx_hw_stats);
2931
2932         for (i = 0; i < bp->cp_nr_rings; i++) {
2933                 struct bnxt_napi *bnapi = bp->bnapi[i];
2934                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2935
2936                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2937                                                    &cpr->hw_stats_map,
2938                                                    GFP_KERNEL);
2939                 if (!cpr->hw_stats)
2940                         return -ENOMEM;
2941
2942                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2943         }
2944
2945         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
2946                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2947                                          sizeof(struct tx_port_stats) + 1024;
2948
2949                 bp->hw_rx_port_stats =
2950                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2951                                            &bp->hw_rx_port_stats_map,
2952                                            GFP_KERNEL);
2953                 if (!bp->hw_rx_port_stats)
2954                         return -ENOMEM;
2955
2956                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2957                                        512;
2958                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2959                                            sizeof(struct rx_port_stats) + 512;
2960                 bp->flags |= BNXT_FLAG_PORT_STATS;
2961         }
2962         return 0;
2963 }
2964
2965 static void bnxt_clear_ring_indices(struct bnxt *bp)
2966 {
2967         int i;
2968
2969         if (!bp->bnapi)
2970                 return;
2971
2972         for (i = 0; i < bp->cp_nr_rings; i++) {
2973                 struct bnxt_napi *bnapi = bp->bnapi[i];
2974                 struct bnxt_cp_ring_info *cpr;
2975                 struct bnxt_rx_ring_info *rxr;
2976                 struct bnxt_tx_ring_info *txr;
2977
2978                 if (!bnapi)
2979                         continue;
2980
2981                 cpr = &bnapi->cp_ring;
2982                 cpr->cp_raw_cons = 0;
2983
2984                 txr = bnapi->tx_ring;
2985                 if (txr) {
2986                         txr->tx_prod = 0;
2987                         txr->tx_cons = 0;
2988                 }
2989
2990                 rxr = bnapi->rx_ring;
2991                 if (rxr) {
2992                         rxr->rx_prod = 0;
2993                         rxr->rx_agg_prod = 0;
2994                         rxr->rx_sw_agg_prod = 0;
2995                         rxr->rx_next_cons = 0;
2996                 }
2997         }
2998 }
2999
3000 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3001 {
3002 #ifdef CONFIG_RFS_ACCEL
3003         int i;
3004
3005         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3006          * safe to delete the hash table.
3007          */
3008         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3009                 struct hlist_head *head;
3010                 struct hlist_node *tmp;
3011                 struct bnxt_ntuple_filter *fltr;
3012
3013                 head = &bp->ntp_fltr_hash_tbl[i];
3014                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3015                         hlist_del(&fltr->hash);
3016                         kfree(fltr);
3017                 }
3018         }
3019         if (irq_reinit) {
3020                 kfree(bp->ntp_fltr_bmap);
3021                 bp->ntp_fltr_bmap = NULL;
3022         }
3023         bp->ntp_fltr_count = 0;
3024 #endif
3025 }
3026
3027 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3028 {
3029 #ifdef CONFIG_RFS_ACCEL
3030         int i, rc = 0;
3031
3032         if (!(bp->flags & BNXT_FLAG_RFS))
3033                 return 0;
3034
3035         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3036                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3037
3038         bp->ntp_fltr_count = 0;
3039         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3040                                     sizeof(long),
3041                                     GFP_KERNEL);
3042
3043         if (!bp->ntp_fltr_bmap)
3044                 rc = -ENOMEM;
3045
3046         return rc;
3047 #else
3048         return 0;
3049 #endif
3050 }
3051
3052 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3053 {
3054         bnxt_free_vnic_attributes(bp);
3055         bnxt_free_tx_rings(bp);
3056         bnxt_free_rx_rings(bp);
3057         bnxt_free_cp_rings(bp);
3058         bnxt_free_ntp_fltrs(bp, irq_re_init);
3059         if (irq_re_init) {
3060                 bnxt_free_stats(bp);
3061                 bnxt_free_ring_grps(bp);
3062                 bnxt_free_vnics(bp);
3063                 kfree(bp->tx_ring_map);
3064                 bp->tx_ring_map = NULL;
3065                 kfree(bp->tx_ring);
3066                 bp->tx_ring = NULL;
3067                 kfree(bp->rx_ring);
3068                 bp->rx_ring = NULL;
3069                 kfree(bp->bnapi);
3070                 bp->bnapi = NULL;
3071         } else {
3072                 bnxt_clear_ring_indices(bp);
3073         }
3074 }
3075
3076 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3077 {
3078         int i, j, rc, size, arr_size;
3079         void *bnapi;
3080
3081         if (irq_re_init) {
3082                 /* Allocate bnapi mem pointer array and mem block for
3083                  * all queues
3084                  */
3085                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3086                                 bp->cp_nr_rings);
3087                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3088                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3089                 if (!bnapi)
3090                         return -ENOMEM;
3091
3092                 bp->bnapi = bnapi;
3093                 bnapi += arr_size;
3094                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3095                         bp->bnapi[i] = bnapi;
3096                         bp->bnapi[i]->index = i;
3097                         bp->bnapi[i]->bp = bp;
3098                 }
3099
3100                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3101                                       sizeof(struct bnxt_rx_ring_info),
3102                                       GFP_KERNEL);
3103                 if (!bp->rx_ring)
3104                         return -ENOMEM;
3105
3106                 for (i = 0; i < bp->rx_nr_rings; i++) {
3107                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3108                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3109                 }
3110
3111                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3112                                       sizeof(struct bnxt_tx_ring_info),
3113                                       GFP_KERNEL);
3114                 if (!bp->tx_ring)
3115                         return -ENOMEM;
3116
3117                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3118                                           GFP_KERNEL);
3119
3120                 if (!bp->tx_ring_map)
3121                         return -ENOMEM;
3122
3123                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3124                         j = 0;
3125                 else
3126                         j = bp->rx_nr_rings;
3127
3128                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3129                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3130                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3131                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3132                         if (i >= bp->tx_nr_rings_xdp) {
3133                                 bp->tx_ring[i].txq_index = i -
3134                                         bp->tx_nr_rings_xdp;
3135                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3136                         } else {
3137                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3138                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3139                         }
3140                 }
3141
3142                 rc = bnxt_alloc_stats(bp);
3143                 if (rc)
3144                         goto alloc_mem_err;
3145
3146                 rc = bnxt_alloc_ntp_fltrs(bp);
3147                 if (rc)
3148                         goto alloc_mem_err;
3149
3150                 rc = bnxt_alloc_vnics(bp);
3151                 if (rc)
3152                         goto alloc_mem_err;
3153         }
3154
3155         bnxt_init_ring_struct(bp);
3156
3157         rc = bnxt_alloc_rx_rings(bp);
3158         if (rc)
3159                 goto alloc_mem_err;
3160
3161         rc = bnxt_alloc_tx_rings(bp);
3162         if (rc)
3163                 goto alloc_mem_err;
3164
3165         rc = bnxt_alloc_cp_rings(bp);
3166         if (rc)
3167                 goto alloc_mem_err;
3168
3169         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3170                                   BNXT_VNIC_UCAST_FLAG;
3171         rc = bnxt_alloc_vnic_attributes(bp);
3172         if (rc)
3173                 goto alloc_mem_err;
3174         return 0;
3175
3176 alloc_mem_err:
3177         bnxt_free_mem(bp, true);
3178         return rc;
3179 }
3180
3181 static void bnxt_disable_int(struct bnxt *bp)
3182 {
3183         int i;
3184
3185         if (!bp->bnapi)
3186                 return;
3187
3188         for (i = 0; i < bp->cp_nr_rings; i++) {
3189                 struct bnxt_napi *bnapi = bp->bnapi[i];
3190                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3191                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3192
3193                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3194                         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3195         }
3196 }
3197
3198 static void bnxt_disable_int_sync(struct bnxt *bp)
3199 {
3200         int i;
3201
3202         atomic_inc(&bp->intr_sem);
3203
3204         bnxt_disable_int(bp);
3205         for (i = 0; i < bp->cp_nr_rings; i++)
3206                 synchronize_irq(bp->irq_tbl[i].vector);
3207 }
3208
3209 static void bnxt_enable_int(struct bnxt *bp)
3210 {
3211         int i;
3212
3213         atomic_set(&bp->intr_sem, 0);
3214         for (i = 0; i < bp->cp_nr_rings; i++) {
3215                 struct bnxt_napi *bnapi = bp->bnapi[i];
3216                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3217
3218                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3219         }
3220 }
3221
3222 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3223                             u16 cmpl_ring, u16 target_id)
3224 {
3225         struct input *req = request;
3226
3227         req->req_type = cpu_to_le16(req_type);
3228         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3229         req->target_id = cpu_to_le16(target_id);
3230         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3231 }
3232
3233 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3234                                  int timeout, bool silent)
3235 {
3236         int i, intr_process, rc, tmo_count;
3237         struct input *req = msg;
3238         u32 *data = msg;
3239         __le32 *resp_len, *valid;
3240         u16 cp_ring_id, len = 0;
3241         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3242         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3243
3244         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3245         memset(resp, 0, PAGE_SIZE);
3246         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3247         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3248
3249         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3250                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3251                 struct hwrm_short_input short_input = {0};
3252
3253                 memcpy(short_cmd_req, req, msg_len);
3254                 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3255                                                    msg_len);
3256
3257                 short_input.req_type = req->req_type;
3258                 short_input.signature =
3259                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3260                 short_input.size = cpu_to_le16(msg_len);
3261                 short_input.req_addr =
3262                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3263
3264                 data = (u32 *)&short_input;
3265                 msg_len = sizeof(short_input);
3266
3267                 /* Sync memory write before updating doorbell */
3268                 wmb();
3269
3270                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3271         }
3272
3273         /* Write request msg to hwrm channel */
3274         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3275
3276         for (i = msg_len; i < max_req_len; i += 4)
3277                 writel(0, bp->bar0 + i);
3278
3279         /* currently supports only one outstanding message */
3280         if (intr_process)
3281                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3282
3283         /* Ring channel doorbell */
3284         writel(1, bp->bar0 + 0x100);
3285
3286         if (!timeout)
3287                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3288
3289         i = 0;
3290         tmo_count = timeout * 40;
3291         if (intr_process) {
3292                 /* Wait until hwrm response cmpl interrupt is processed */
3293                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3294                        i++ < tmo_count) {
3295                         usleep_range(25, 40);
3296                 }
3297
3298                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3299                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3300                                    le16_to_cpu(req->req_type));
3301                         return -1;
3302                 }
3303         } else {
3304                 /* Check if response len is updated */
3305                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3306                 for (i = 0; i < tmo_count; i++) {
3307                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3308                               HWRM_RESP_LEN_SFT;
3309                         if (len)
3310                                 break;
3311                         usleep_range(25, 40);
3312                 }
3313
3314                 if (i >= tmo_count) {
3315                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3316                                    timeout, le16_to_cpu(req->req_type),
3317                                    le16_to_cpu(req->seq_id), len);
3318                         return -1;
3319                 }
3320
3321                 /* Last word of resp contains valid bit */
3322                 valid = bp->hwrm_cmd_resp_addr + len - 4;
3323                 for (i = 0; i < 5; i++) {
3324                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3325                                 break;
3326                         udelay(1);
3327                 }
3328
3329                 if (i >= 5) {
3330                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3331                                    timeout, le16_to_cpu(req->req_type),
3332                                    le16_to_cpu(req->seq_id), len, *valid);
3333                         return -1;
3334                 }
3335         }
3336
3337         rc = le16_to_cpu(resp->error_code);
3338         if (rc && !silent)
3339                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3340                            le16_to_cpu(resp->req_type),
3341                            le16_to_cpu(resp->seq_id), rc);
3342         return rc;
3343 }
3344
3345 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3346 {
3347         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3348 }
3349
3350 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3351 {
3352         int rc;
3353
3354         mutex_lock(&bp->hwrm_cmd_lock);
3355         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3356         mutex_unlock(&bp->hwrm_cmd_lock);
3357         return rc;
3358 }
3359
3360 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3361                              int timeout)
3362 {
3363         int rc;
3364
3365         mutex_lock(&bp->hwrm_cmd_lock);
3366         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3367         mutex_unlock(&bp->hwrm_cmd_lock);
3368         return rc;
3369 }
3370
3371 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3372                                      int bmap_size)
3373 {
3374         struct hwrm_func_drv_rgtr_input req = {0};
3375         DECLARE_BITMAP(async_events_bmap, 256);
3376         u32 *events = (u32 *)async_events_bmap;
3377         int i;
3378
3379         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3380
3381         req.enables =
3382                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3383
3384         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3385         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3386                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3387
3388         if (bmap && bmap_size) {
3389                 for (i = 0; i < bmap_size; i++) {
3390                         if (test_bit(i, bmap))
3391                                 __set_bit(i, async_events_bmap);
3392                 }
3393         }
3394
3395         for (i = 0; i < 8; i++)
3396                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3397
3398         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3399 }
3400
3401 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3402 {
3403         struct hwrm_func_drv_rgtr_input req = {0};
3404
3405         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3406
3407         req.enables =
3408                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3409                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3410
3411         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3412         req.ver_maj = DRV_VER_MAJ;
3413         req.ver_min = DRV_VER_MIN;
3414         req.ver_upd = DRV_VER_UPD;
3415
3416         if (BNXT_PF(bp)) {
3417                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3418                 u32 *data = (u32 *)vf_req_snif_bmap;
3419                 int i;
3420
3421                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3422                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3423                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3424
3425                 for (i = 0; i < 8; i++)
3426                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3427
3428                 req.enables |=
3429                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3430         }
3431
3432         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3433 }
3434
3435 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3436 {
3437         struct hwrm_func_drv_unrgtr_input req = {0};
3438
3439         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3440         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3441 }
3442
3443 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3444 {
3445         u32 rc = 0;
3446         struct hwrm_tunnel_dst_port_free_input req = {0};
3447
3448         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3449         req.tunnel_type = tunnel_type;
3450
3451         switch (tunnel_type) {
3452         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3453                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3454                 break;
3455         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3456                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3457                 break;
3458         default:
3459                 break;
3460         }
3461
3462         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3463         if (rc)
3464                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3465                            rc);
3466         return rc;
3467 }
3468
3469 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3470                                            u8 tunnel_type)
3471 {
3472         u32 rc = 0;
3473         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3474         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3475
3476         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3477
3478         req.tunnel_type = tunnel_type;
3479         req.tunnel_dst_port_val = port;
3480
3481         mutex_lock(&bp->hwrm_cmd_lock);
3482         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3483         if (rc) {
3484                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3485                            rc);
3486                 goto err_out;
3487         }
3488
3489         switch (tunnel_type) {
3490         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3491                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3492                 break;
3493         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3494                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3495                 break;
3496         default:
3497                 break;
3498         }
3499
3500 err_out:
3501         mutex_unlock(&bp->hwrm_cmd_lock);
3502         return rc;
3503 }
3504
3505 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3506 {
3507         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3508         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3509
3510         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3511         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3512
3513         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3514         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3515         req.mask = cpu_to_le32(vnic->rx_mask);
3516         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3517 }
3518
3519 #ifdef CONFIG_RFS_ACCEL
3520 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3521                                             struct bnxt_ntuple_filter *fltr)
3522 {
3523         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3524
3525         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3526         req.ntuple_filter_id = fltr->filter_id;
3527         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3528 }
3529
3530 #define BNXT_NTP_FLTR_FLAGS                                     \
3531         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3532          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3533          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3534          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3535          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3536          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3537          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3538          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3539          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3540          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3541          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3542          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3543          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3544          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3545
3546 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
3547                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3548
3549 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3550                                              struct bnxt_ntuple_filter *fltr)
3551 {
3552         int rc = 0;
3553         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3554         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3555                 bp->hwrm_cmd_resp_addr;
3556         struct flow_keys *keys = &fltr->fkeys;
3557         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3558
3559         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3560         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3561
3562         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3563
3564         req.ethertype = htons(ETH_P_IP);
3565         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3566         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3567         req.ip_protocol = keys->basic.ip_proto;
3568
3569         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3570                 int i;
3571
3572                 req.ethertype = htons(ETH_P_IPV6);
3573                 req.ip_addr_type =
3574                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3575                 *(struct in6_addr *)&req.src_ipaddr[0] =
3576                         keys->addrs.v6addrs.src;
3577                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3578                         keys->addrs.v6addrs.dst;
3579                 for (i = 0; i < 4; i++) {
3580                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3581                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3582                 }
3583         } else {
3584                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3585                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3586                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3587                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3588         }
3589         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3590                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3591                 req.tunnel_type =
3592                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3593         }
3594
3595         req.src_port = keys->ports.src;
3596         req.src_port_mask = cpu_to_be16(0xffff);
3597         req.dst_port = keys->ports.dst;
3598         req.dst_port_mask = cpu_to_be16(0xffff);
3599
3600         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3601         mutex_lock(&bp->hwrm_cmd_lock);
3602         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3603         if (!rc)
3604                 fltr->filter_id = resp->ntuple_filter_id;
3605         mutex_unlock(&bp->hwrm_cmd_lock);
3606         return rc;
3607 }
3608 #endif
3609
3610 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3611                                      u8 *mac_addr)
3612 {
3613         u32 rc = 0;
3614         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3615         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3616
3617         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3618         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3619         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3620                 req.flags |=
3621                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3622         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3623         req.enables =
3624                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3625                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3626                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3627         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3628         req.l2_addr_mask[0] = 0xff;
3629         req.l2_addr_mask[1] = 0xff;
3630         req.l2_addr_mask[2] = 0xff;
3631         req.l2_addr_mask[3] = 0xff;
3632         req.l2_addr_mask[4] = 0xff;
3633         req.l2_addr_mask[5] = 0xff;
3634
3635         mutex_lock(&bp->hwrm_cmd_lock);
3636         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3637         if (!rc)
3638                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3639                                                         resp->l2_filter_id;
3640         mutex_unlock(&bp->hwrm_cmd_lock);
3641         return rc;
3642 }
3643
3644 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3645 {
3646         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3647         int rc = 0;
3648
3649         /* Any associated ntuple filters will also be cleared by firmware. */
3650         mutex_lock(&bp->hwrm_cmd_lock);
3651         for (i = 0; i < num_of_vnics; i++) {
3652                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3653
3654                 for (j = 0; j < vnic->uc_filter_count; j++) {
3655                         struct hwrm_cfa_l2_filter_free_input req = {0};
3656
3657                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3658                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3659
3660                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3661
3662                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3663                                                 HWRM_CMD_TIMEOUT);
3664                 }
3665                 vnic->uc_filter_count = 0;
3666         }
3667         mutex_unlock(&bp->hwrm_cmd_lock);
3668
3669         return rc;
3670 }
3671
3672 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3673 {
3674         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3675         struct hwrm_vnic_tpa_cfg_input req = {0};
3676
3677         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3678
3679         if (tpa_flags) {
3680                 u16 mss = bp->dev->mtu - 40;
3681                 u32 nsegs, n, segs = 0, flags;
3682
3683                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3684                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3685                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3686                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3687                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3688                 if (tpa_flags & BNXT_FLAG_GRO)
3689                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3690
3691                 req.flags = cpu_to_le32(flags);
3692
3693                 req.enables =
3694                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3695                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3696                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3697
3698                 /* Number of segs are log2 units, and first packet is not
3699                  * included as part of this units.
3700                  */
3701                 if (mss <= BNXT_RX_PAGE_SIZE) {
3702                         n = BNXT_RX_PAGE_SIZE / mss;
3703                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3704                 } else {
3705                         n = mss / BNXT_RX_PAGE_SIZE;
3706                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3707                                 n++;
3708                         nsegs = (MAX_SKB_FRAGS - n) / n;
3709                 }
3710
3711                 segs = ilog2(nsegs);
3712                 req.max_agg_segs = cpu_to_le16(segs);
3713                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3714
3715                 req.min_agg_len = cpu_to_le32(512);
3716         }
3717         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3718
3719         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3720 }
3721
3722 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3723 {
3724         u32 i, j, max_rings;
3725         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3726         struct hwrm_vnic_rss_cfg_input req = {0};
3727
3728         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3729                 return 0;
3730
3731         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3732         if (set_rss) {
3733                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3734                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3735                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3736                                 max_rings = bp->rx_nr_rings - 1;
3737                         else
3738                                 max_rings = bp->rx_nr_rings;
3739                 } else {
3740                         max_rings = 1;
3741                 }
3742
3743                 /* Fill the RSS indirection table with ring group ids */
3744                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3745                         if (j == max_rings)
3746                                 j = 0;
3747                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3748                 }
3749
3750                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3751                 req.hash_key_tbl_addr =
3752                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3753         }
3754         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3755         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3756 }
3757
3758 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3759 {
3760         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3761         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3762
3763         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3764         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3765                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3766                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3767         req.enables =
3768                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3769                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3770         /* thresholds not implemented in firmware yet */
3771         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3772         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3773         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3774         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3775 }
3776
3777 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3778                                         u16 ctx_idx)
3779 {
3780         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3781
3782         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3783         req.rss_cos_lb_ctx_id =
3784                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3785
3786         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3787         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3788 }
3789
3790 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3791 {
3792         int i, j;
3793
3794         for (i = 0; i < bp->nr_vnics; i++) {
3795                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3796
3797                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3798                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3799                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3800                 }
3801         }
3802         bp->rsscos_nr_ctxs = 0;
3803 }
3804
3805 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3806 {
3807         int rc;
3808         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3809         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3810                                                 bp->hwrm_cmd_resp_addr;
3811
3812         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3813                                -1);
3814
3815         mutex_lock(&bp->hwrm_cmd_lock);
3816         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3817         if (!rc)
3818                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3819                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3820         mutex_unlock(&bp->hwrm_cmd_lock);
3821
3822         return rc;
3823 }
3824
3825 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3826 {
3827         unsigned int ring = 0, grp_idx;
3828         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3829         struct hwrm_vnic_cfg_input req = {0};
3830         u16 def_vlan = 0;
3831
3832         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3833
3834         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
3835         /* Only RSS support for now TBD: COS & LB */
3836         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3837                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3838                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3839                                            VNIC_CFG_REQ_ENABLES_MRU);
3840         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3841                 req.rss_rule =
3842                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3843                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3844                                            VNIC_CFG_REQ_ENABLES_MRU);
3845                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
3846         } else {
3847                 req.rss_rule = cpu_to_le16(0xffff);
3848         }
3849
3850         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3851             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
3852                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3853                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3854         } else {
3855                 req.cos_rule = cpu_to_le16(0xffff);
3856         }
3857
3858         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3859                 ring = 0;
3860         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3861                 ring = vnic_id - 1;
3862         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3863                 ring = bp->rx_nr_rings - 1;
3864
3865         grp_idx = bp->rx_ring[ring].bnapi->index;
3866         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3867         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3868
3869         req.lb_rule = cpu_to_le16(0xffff);
3870         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3871                               VLAN_HLEN);
3872
3873 #ifdef CONFIG_BNXT_SRIOV
3874         if (BNXT_VF(bp))
3875                 def_vlan = bp->vf.vlan;
3876 #endif
3877         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3878                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3879         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
3880                 req.flags |=
3881                         cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
3882
3883         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3884 }
3885
3886 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3887 {
3888         u32 rc = 0;
3889
3890         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3891                 struct hwrm_vnic_free_input req = {0};
3892
3893                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3894                 req.vnic_id =
3895                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3896
3897                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3898                 if (rc)
3899                         return rc;
3900                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3901         }
3902         return rc;
3903 }
3904
3905 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3906 {
3907         u16 i;
3908
3909         for (i = 0; i < bp->nr_vnics; i++)
3910                 bnxt_hwrm_vnic_free_one(bp, i);
3911 }
3912
3913 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3914                                 unsigned int start_rx_ring_idx,
3915                                 unsigned int nr_rings)
3916 {
3917         int rc = 0;
3918         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3919         struct hwrm_vnic_alloc_input req = {0};
3920         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3921
3922         /* map ring groups to this vnic */
3923         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3924                 grp_idx = bp->rx_ring[i].bnapi->index;
3925                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3926                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3927                                    j, nr_rings);
3928                         break;
3929                 }
3930                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3931                                         bp->grp_info[grp_idx].fw_grp_id;
3932         }
3933
3934         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3935         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
3936         if (vnic_id == 0)
3937                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3938
3939         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3940
3941         mutex_lock(&bp->hwrm_cmd_lock);
3942         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3943         if (!rc)
3944                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3945         mutex_unlock(&bp->hwrm_cmd_lock);
3946         return rc;
3947 }
3948
3949 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
3950 {
3951         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3952         struct hwrm_vnic_qcaps_input req = {0};
3953         int rc;
3954
3955         if (bp->hwrm_spec_code < 0x10600)
3956                 return 0;
3957
3958         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
3959         mutex_lock(&bp->hwrm_cmd_lock);
3960         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3961         if (!rc) {
3962                 if (resp->flags &
3963                     cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
3964                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
3965         }
3966         mutex_unlock(&bp->hwrm_cmd_lock);
3967         return rc;
3968 }
3969
3970 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3971 {
3972         u16 i;
3973         u32 rc = 0;
3974
3975         mutex_lock(&bp->hwrm_cmd_lock);
3976         for (i = 0; i < bp->rx_nr_rings; i++) {
3977                 struct hwrm_ring_grp_alloc_input req = {0};
3978                 struct hwrm_ring_grp_alloc_output *resp =
3979                                         bp->hwrm_cmd_resp_addr;
3980                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3981
3982                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3983
3984                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3985                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3986                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3987                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3988
3989                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3990                                         HWRM_CMD_TIMEOUT);
3991                 if (rc)
3992                         break;
3993
3994                 bp->grp_info[grp_idx].fw_grp_id =
3995                         le32_to_cpu(resp->ring_group_id);
3996         }
3997         mutex_unlock(&bp->hwrm_cmd_lock);
3998         return rc;
3999 }
4000
4001 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4002 {
4003         u16 i;
4004         u32 rc = 0;
4005         struct hwrm_ring_grp_free_input req = {0};
4006
4007         if (!bp->grp_info)
4008                 return 0;
4009
4010         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4011
4012         mutex_lock(&bp->hwrm_cmd_lock);
4013         for (i = 0; i < bp->cp_nr_rings; i++) {
4014                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4015                         continue;
4016                 req.ring_group_id =
4017                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4018
4019                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4020                                         HWRM_CMD_TIMEOUT);
4021                 if (rc)
4022                         break;
4023                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4024         }
4025         mutex_unlock(&bp->hwrm_cmd_lock);
4026         return rc;
4027 }
4028
4029 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4030                                     struct bnxt_ring_struct *ring,
4031                                     u32 ring_type, u32 map_index,
4032                                     u32 stats_ctx_id)
4033 {
4034         int rc = 0, err = 0;
4035         struct hwrm_ring_alloc_input req = {0};
4036         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4037         u16 ring_id;
4038
4039         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4040
4041         req.enables = 0;
4042         if (ring->nr_pages > 1) {
4043                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4044                 /* Page size is in log2 units */
4045                 req.page_size = BNXT_PAGE_SHIFT;
4046                 req.page_tbl_depth = 1;
4047         } else {
4048                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
4049         }
4050         req.fbo = 0;
4051         /* Association of ring index with doorbell index and MSIX number */
4052         req.logical_id = cpu_to_le16(map_index);
4053
4054         switch (ring_type) {
4055         case HWRM_RING_ALLOC_TX:
4056                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4057                 /* Association of transmit ring with completion ring */
4058                 req.cmpl_ring_id =
4059                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
4060                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4061                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4062                 req.queue_id = cpu_to_le16(ring->queue_id);
4063                 break;
4064         case HWRM_RING_ALLOC_RX:
4065                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4066                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4067                 break;
4068         case HWRM_RING_ALLOC_AGG:
4069                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4070                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4071                 break;
4072         case HWRM_RING_ALLOC_CMPL:
4073                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4074                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4075                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4076                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4077                 break;
4078         default:
4079                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4080                            ring_type);
4081                 return -1;
4082         }
4083
4084         mutex_lock(&bp->hwrm_cmd_lock);
4085         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4086         err = le16_to_cpu(resp->error_code);
4087         ring_id = le16_to_cpu(resp->ring_id);
4088         mutex_unlock(&bp->hwrm_cmd_lock);
4089
4090         if (rc || err) {
4091                 switch (ring_type) {
4092                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4093                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4094                                    rc, err);
4095                         return -1;
4096
4097                 case RING_FREE_REQ_RING_TYPE_RX:
4098                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4099                                    rc, err);
4100                         return -1;
4101
4102                 case RING_FREE_REQ_RING_TYPE_TX:
4103                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4104                                    rc, err);
4105                         return -1;
4106
4107                 default:
4108                         netdev_err(bp->dev, "Invalid ring\n");
4109                         return -1;
4110                 }
4111         }
4112         ring->fw_ring_id = ring_id;
4113         return rc;
4114 }
4115
4116 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4117 {
4118         int rc;
4119
4120         if (BNXT_PF(bp)) {
4121                 struct hwrm_func_cfg_input req = {0};
4122
4123                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4124                 req.fid = cpu_to_le16(0xffff);
4125                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4126                 req.async_event_cr = cpu_to_le16(idx);
4127                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4128         } else {
4129                 struct hwrm_func_vf_cfg_input req = {0};
4130
4131                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4132                 req.enables =
4133                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4134                 req.async_event_cr = cpu_to_le16(idx);
4135                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4136         }
4137         return rc;
4138 }
4139
4140 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4141 {
4142         int i, rc = 0;
4143
4144         for (i = 0; i < bp->cp_nr_rings; i++) {
4145                 struct bnxt_napi *bnapi = bp->bnapi[i];
4146                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4147                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4148
4149                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
4150                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4151                                               INVALID_STATS_CTX_ID);
4152                 if (rc)
4153                         goto err_out;
4154                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4155                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4156
4157                 if (!i) {
4158                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4159                         if (rc)
4160                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4161                 }
4162         }
4163
4164         for (i = 0; i < bp->tx_nr_rings; i++) {
4165                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4166                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4167                 u32 map_idx = txr->bnapi->index;
4168                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
4169
4170                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4171                                               map_idx, fw_stats_ctx);
4172                 if (rc)
4173                         goto err_out;
4174                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4175         }
4176
4177         for (i = 0; i < bp->rx_nr_rings; i++) {
4178                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4179                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4180                 u32 map_idx = rxr->bnapi->index;
4181
4182                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4183                                               map_idx, INVALID_STATS_CTX_ID);
4184                 if (rc)
4185                         goto err_out;
4186                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4187                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4188                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4189         }
4190
4191         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4192                 for (i = 0; i < bp->rx_nr_rings; i++) {
4193                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4194                         struct bnxt_ring_struct *ring =
4195                                                 &rxr->rx_agg_ring_struct;
4196                         u32 grp_idx = rxr->bnapi->index;
4197                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4198
4199                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4200                                                       HWRM_RING_ALLOC_AGG,
4201                                                       map_idx,
4202                                                       INVALID_STATS_CTX_ID);
4203                         if (rc)
4204                                 goto err_out;
4205
4206                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4207                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4208                                rxr->rx_agg_doorbell);
4209                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4210                 }
4211         }
4212 err_out:
4213         return rc;
4214 }
4215
4216 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4217                                    struct bnxt_ring_struct *ring,
4218                                    u32 ring_type, int cmpl_ring_id)
4219 {
4220         int rc;
4221         struct hwrm_ring_free_input req = {0};
4222         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4223         u16 error_code;
4224
4225         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4226         req.ring_type = ring_type;
4227         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4228
4229         mutex_lock(&bp->hwrm_cmd_lock);
4230         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4231         error_code = le16_to_cpu(resp->error_code);
4232         mutex_unlock(&bp->hwrm_cmd_lock);
4233
4234         if (rc || error_code) {
4235                 switch (ring_type) {
4236                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4237                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4238                                    rc);
4239                         return rc;
4240                 case RING_FREE_REQ_RING_TYPE_RX:
4241                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4242                                    rc);
4243                         return rc;
4244                 case RING_FREE_REQ_RING_TYPE_TX:
4245                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4246                                    rc);
4247                         return rc;
4248                 default:
4249                         netdev_err(bp->dev, "Invalid ring\n");
4250                         return -1;
4251                 }
4252         }
4253         return 0;
4254 }
4255
4256 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4257 {
4258         int i;
4259
4260         if (!bp->bnapi)
4261                 return;
4262
4263         for (i = 0; i < bp->tx_nr_rings; i++) {
4264                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4265                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4266                 u32 grp_idx = txr->bnapi->index;
4267                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4268
4269                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4270                         hwrm_ring_free_send_msg(bp, ring,
4271                                                 RING_FREE_REQ_RING_TYPE_TX,
4272                                                 close_path ? cmpl_ring_id :
4273                                                 INVALID_HW_RING_ID);
4274                         ring->fw_ring_id = INVALID_HW_RING_ID;
4275                 }
4276         }
4277
4278         for (i = 0; i < bp->rx_nr_rings; i++) {
4279                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4280                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4281                 u32 grp_idx = rxr->bnapi->index;
4282                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4283
4284                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4285                         hwrm_ring_free_send_msg(bp, ring,
4286                                                 RING_FREE_REQ_RING_TYPE_RX,
4287                                                 close_path ? cmpl_ring_id :
4288                                                 INVALID_HW_RING_ID);
4289                         ring->fw_ring_id = INVALID_HW_RING_ID;
4290                         bp->grp_info[grp_idx].rx_fw_ring_id =
4291                                 INVALID_HW_RING_ID;
4292                 }
4293         }
4294
4295         for (i = 0; i < bp->rx_nr_rings; i++) {
4296                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4297                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4298                 u32 grp_idx = rxr->bnapi->index;
4299                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4300
4301                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4302                         hwrm_ring_free_send_msg(bp, ring,
4303                                                 RING_FREE_REQ_RING_TYPE_RX,
4304                                                 close_path ? cmpl_ring_id :
4305                                                 INVALID_HW_RING_ID);
4306                         ring->fw_ring_id = INVALID_HW_RING_ID;
4307                         bp->grp_info[grp_idx].agg_fw_ring_id =
4308                                 INVALID_HW_RING_ID;
4309                 }
4310         }
4311
4312         /* The completion rings are about to be freed.  After that the
4313          * IRQ doorbell will not work anymore.  So we need to disable
4314          * IRQ here.
4315          */
4316         bnxt_disable_int_sync(bp);
4317
4318         for (i = 0; i < bp->cp_nr_rings; i++) {
4319                 struct bnxt_napi *bnapi = bp->bnapi[i];
4320                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4321                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4322
4323                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4324                         hwrm_ring_free_send_msg(bp, ring,
4325                                                 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4326                                                 INVALID_HW_RING_ID);
4327                         ring->fw_ring_id = INVALID_HW_RING_ID;
4328                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4329                 }
4330         }
4331 }
4332
4333 /* Caller must hold bp->hwrm_cmd_lock */
4334 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4335 {
4336         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4337         struct hwrm_func_qcfg_input req = {0};
4338         int rc;
4339
4340         if (bp->hwrm_spec_code < 0x10601)
4341                 return 0;
4342
4343         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4344         req.fid = cpu_to_le16(fid);
4345         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4346         if (!rc)
4347                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4348
4349         return rc;
4350 }
4351
4352 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
4353 {
4354         struct hwrm_func_cfg_input req = {0};
4355         int rc;
4356
4357         if (bp->hwrm_spec_code < 0x10601)
4358                 return 0;
4359
4360         if (BNXT_VF(bp))
4361                 return 0;
4362
4363         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4364         req.fid = cpu_to_le16(0xffff);
4365         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4366         req.num_tx_rings = cpu_to_le16(*tx_rings);
4367         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4368         if (rc)
4369                 return rc;
4370
4371         mutex_lock(&bp->hwrm_cmd_lock);
4372         rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4373         mutex_unlock(&bp->hwrm_cmd_lock);
4374         return rc;
4375 }
4376
4377 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
4378         u32 buf_tmrs, u16 flags,
4379         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4380 {
4381         req->flags = cpu_to_le16(flags);
4382         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
4383         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
4384         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
4385         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
4386         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4387         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
4388         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
4389         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
4390 }
4391
4392 int bnxt_hwrm_set_coal(struct bnxt *bp)
4393 {
4394         int i, rc = 0;
4395         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4396                                                            req_tx = {0}, *req;
4397         u16 max_buf, max_buf_irq;
4398         u16 buf_tmr, buf_tmr_irq;
4399         u32 flags;
4400
4401         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4402                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4403         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4404                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4405
4406         /* Each rx completion (2 records) should be DMAed immediately.
4407          * DMA 1/4 of the completion buffers at a time.
4408          */
4409         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
4410         /* max_buf must not be zero */
4411         max_buf = clamp_t(u16, max_buf, 1, 63);
4412         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4413         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4414         /* buf timer set to 1/4 of interrupt timer */
4415         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4416         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4417         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4418
4419         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4420
4421         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
4422          * if coal_ticks is less than 25 us.
4423          */
4424         if (bp->rx_coal_ticks < 25)
4425                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4426
4427         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4428                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4429
4430         /* max_buf must not be zero */
4431         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4432         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4433         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4434         /* buf timer set to 1/4 of interrupt timer */
4435         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4436         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4437         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4438
4439         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4440         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4441                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
4442
4443         mutex_lock(&bp->hwrm_cmd_lock);
4444         for (i = 0; i < bp->cp_nr_rings; i++) {
4445                 struct bnxt_napi *bnapi = bp->bnapi[i];
4446
4447                 req = &req_rx;
4448                 if (!bnapi->rx_ring)
4449                         req = &req_tx;
4450                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4451
4452                 rc = _hwrm_send_message(bp, req, sizeof(*req),
4453                                         HWRM_CMD_TIMEOUT);
4454                 if (rc)
4455                         break;
4456         }
4457         mutex_unlock(&bp->hwrm_cmd_lock);
4458         return rc;
4459 }
4460
4461 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4462 {
4463         int rc = 0, i;
4464         struct hwrm_stat_ctx_free_input req = {0};
4465
4466         if (!bp->bnapi)
4467                 return 0;
4468
4469         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4470                 return 0;
4471
4472         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4473
4474         mutex_lock(&bp->hwrm_cmd_lock);
4475         for (i = 0; i < bp->cp_nr_rings; i++) {
4476                 struct bnxt_napi *bnapi = bp->bnapi[i];
4477                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4478
4479                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4480                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4481
4482                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4483                                                 HWRM_CMD_TIMEOUT);
4484                         if (rc)
4485                                 break;
4486
4487                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4488                 }
4489         }
4490         mutex_unlock(&bp->hwrm_cmd_lock);
4491         return rc;
4492 }
4493
4494 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4495 {
4496         int rc = 0, i;
4497         struct hwrm_stat_ctx_alloc_input req = {0};
4498         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4499
4500         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4501                 return 0;
4502
4503         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4504
4505         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4506
4507         mutex_lock(&bp->hwrm_cmd_lock);
4508         for (i = 0; i < bp->cp_nr_rings; i++) {
4509                 struct bnxt_napi *bnapi = bp->bnapi[i];
4510                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4511
4512                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4513
4514                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4515                                         HWRM_CMD_TIMEOUT);
4516                 if (rc)
4517                         break;
4518
4519                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4520
4521                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4522         }
4523         mutex_unlock(&bp->hwrm_cmd_lock);
4524         return rc;
4525 }
4526
4527 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4528 {
4529         struct hwrm_func_qcfg_input req = {0};
4530         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4531         int rc;
4532
4533         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4534         req.fid = cpu_to_le16(0xffff);
4535         mutex_lock(&bp->hwrm_cmd_lock);
4536         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4537         if (rc)
4538                 goto func_qcfg_exit;
4539
4540 #ifdef CONFIG_BNXT_SRIOV
4541         if (BNXT_VF(bp)) {
4542                 struct bnxt_vf_info *vf = &bp->vf;
4543
4544                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4545         }
4546 #endif
4547         if (BNXT_PF(bp)) {
4548                 u16 flags = le16_to_cpu(resp->flags);
4549
4550                 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
4551                              FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED))
4552                         bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
4553                 if (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)
4554                         bp->flags |= BNXT_FLAG_MULTI_HOST;
4555         }
4556
4557         switch (resp->port_partition_type) {
4558         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4559         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4560         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4561                 bp->port_partition_type = resp->port_partition_type;
4562                 break;
4563         }
4564
4565 func_qcfg_exit:
4566         mutex_unlock(&bp->hwrm_cmd_lock);
4567         return rc;
4568 }
4569
4570 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4571 {
4572         int rc = 0;
4573         struct hwrm_func_qcaps_input req = {0};
4574         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4575
4576         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4577         req.fid = cpu_to_le16(0xffff);
4578
4579         mutex_lock(&bp->hwrm_cmd_lock);
4580         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4581         if (rc)
4582                 goto hwrm_func_qcaps_exit;
4583
4584         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4585                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4586         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4587                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4588
4589         bp->tx_push_thresh = 0;
4590         if (resp->flags &
4591             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4592                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4593
4594         if (BNXT_PF(bp)) {
4595                 struct bnxt_pf_info *pf = &bp->pf;
4596
4597                 pf->fw_fid = le16_to_cpu(resp->fid);
4598                 pf->port_id = le16_to_cpu(resp->port_id);
4599                 bp->dev->dev_port = pf->port_id;
4600                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4601                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4602                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4603                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4604                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4605                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4606                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4607                 if (!pf->max_hw_ring_grps)
4608                         pf->max_hw_ring_grps = pf->max_tx_rings;
4609                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4610                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4611                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4612                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4613                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4614                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4615                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4616                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4617                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4618                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4619                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4620                 if (resp->flags &
4621                     cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED))
4622                         bp->flags |= BNXT_FLAG_WOL_CAP;
4623         } else {
4624 #ifdef CONFIG_BNXT_SRIOV
4625                 struct bnxt_vf_info *vf = &bp->vf;
4626
4627                 vf->fw_fid = le16_to_cpu(resp->fid);
4628
4629                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4630                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4631                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4632                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4633                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4634                 if (!vf->max_hw_ring_grps)
4635                         vf->max_hw_ring_grps = vf->max_tx_rings;
4636                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4637                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4638                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4639
4640                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4641                 mutex_unlock(&bp->hwrm_cmd_lock);
4642
4643                 if (is_valid_ether_addr(vf->mac_addr)) {
4644                         /* overwrite netdev dev_adr with admin VF MAC */
4645                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4646                 } else {
4647                         eth_hw_addr_random(bp->dev);
4648                         rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4649                 }
4650                 return rc;
4651 #endif
4652         }
4653
4654 hwrm_func_qcaps_exit:
4655         mutex_unlock(&bp->hwrm_cmd_lock);
4656         return rc;
4657 }
4658
4659 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4660 {
4661         struct hwrm_func_reset_input req = {0};
4662
4663         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4664         req.enables = 0;
4665
4666         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4667 }
4668
4669 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4670 {
4671         int rc = 0;
4672         struct hwrm_queue_qportcfg_input req = {0};
4673         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4674         u8 i, *qptr;
4675
4676         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4677
4678         mutex_lock(&bp->hwrm_cmd_lock);
4679         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4680         if (rc)
4681                 goto qportcfg_exit;
4682
4683         if (!resp->max_configurable_queues) {
4684                 rc = -EINVAL;
4685                 goto qportcfg_exit;
4686         }
4687         bp->max_tc = resp->max_configurable_queues;
4688         bp->max_lltc = resp->max_configurable_lossless_queues;
4689         if (bp->max_tc > BNXT_MAX_QUEUE)
4690                 bp->max_tc = BNXT_MAX_QUEUE;
4691
4692         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4693                 bp->max_tc = 1;
4694
4695         if (bp->max_lltc > bp->max_tc)
4696                 bp->max_lltc = bp->max_tc;
4697
4698         qptr = &resp->queue_id0;
4699         for (i = 0; i < bp->max_tc; i++) {
4700                 bp->q_info[i].queue_id = *qptr++;
4701                 bp->q_info[i].queue_profile = *qptr++;
4702         }
4703
4704 qportcfg_exit:
4705         mutex_unlock(&bp->hwrm_cmd_lock);
4706         return rc;
4707 }
4708
4709 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4710 {
4711         int rc;
4712         struct hwrm_ver_get_input req = {0};
4713         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4714         u32 dev_caps_cfg;
4715
4716         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4717         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4718         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4719         req.hwrm_intf_min = HWRM_VERSION_MINOR;
4720         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4721         mutex_lock(&bp->hwrm_cmd_lock);
4722         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4723         if (rc)
4724                 goto hwrm_ver_get_exit;
4725
4726         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4727
4728         bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4729                              resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4730         if (resp->hwrm_intf_maj < 1) {
4731                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4732                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
4733                             resp->hwrm_intf_upd);
4734                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4735         }
4736         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4737                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4738                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4739
4740         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4741         if (!bp->hwrm_cmd_timeout)
4742                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4743
4744         if (resp->hwrm_intf_maj >= 1)
4745                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4746
4747         bp->chip_num = le16_to_cpu(resp->chip_num);
4748         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4749             !resp->chip_metal)
4750                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4751
4752         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
4753         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
4754             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
4755                 bp->flags |= BNXT_FLAG_SHORT_CMD;
4756
4757 hwrm_ver_get_exit:
4758         mutex_unlock(&bp->hwrm_cmd_lock);
4759         return rc;
4760 }
4761
4762 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4763 {
4764 #if IS_ENABLED(CONFIG_RTC_LIB)
4765         struct hwrm_fw_set_time_input req = {0};
4766         struct rtc_time tm;
4767         struct timeval tv;
4768
4769         if (bp->hwrm_spec_code < 0x10400)
4770                 return -EOPNOTSUPP;
4771
4772         do_gettimeofday(&tv);
4773         rtc_time_to_tm(tv.tv_sec, &tm);
4774         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4775         req.year = cpu_to_le16(1900 + tm.tm_year);
4776         req.month = 1 + tm.tm_mon;
4777         req.day = tm.tm_mday;
4778         req.hour = tm.tm_hour;
4779         req.minute = tm.tm_min;
4780         req.second = tm.tm_sec;
4781         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4782 #else
4783         return -EOPNOTSUPP;
4784 #endif
4785 }
4786
4787 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4788 {
4789         int rc;
4790         struct bnxt_pf_info *pf = &bp->pf;
4791         struct hwrm_port_qstats_input req = {0};
4792
4793         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4794                 return 0;
4795
4796         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4797         req.port_id = cpu_to_le16(pf->port_id);
4798         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4799         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4800         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4801         return rc;
4802 }
4803
4804 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4805 {
4806         if (bp->vxlan_port_cnt) {
4807                 bnxt_hwrm_tunnel_dst_port_free(
4808                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4809         }
4810         bp->vxlan_port_cnt = 0;
4811         if (bp->nge_port_cnt) {
4812                 bnxt_hwrm_tunnel_dst_port_free(
4813                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4814         }
4815         bp->nge_port_cnt = 0;
4816 }
4817
4818 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4819 {
4820         int rc, i;
4821         u32 tpa_flags = 0;
4822
4823         if (set_tpa)
4824                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4825         for (i = 0; i < bp->nr_vnics; i++) {
4826                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4827                 if (rc) {
4828                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4829                                    i, rc);
4830                         return rc;
4831                 }
4832         }
4833         return 0;
4834 }
4835
4836 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4837 {
4838         int i;
4839
4840         for (i = 0; i < bp->nr_vnics; i++)
4841                 bnxt_hwrm_vnic_set_rss(bp, i, false);
4842 }
4843
4844 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4845                                     bool irq_re_init)
4846 {
4847         if (bp->vnic_info) {
4848                 bnxt_hwrm_clear_vnic_filter(bp);
4849                 /* clear all RSS setting before free vnic ctx */
4850                 bnxt_hwrm_clear_vnic_rss(bp);
4851                 bnxt_hwrm_vnic_ctx_free(bp);
4852                 /* before free the vnic, undo the vnic tpa settings */
4853                 if (bp->flags & BNXT_FLAG_TPA)
4854                         bnxt_set_tpa(bp, false);
4855                 bnxt_hwrm_vnic_free(bp);
4856         }
4857         bnxt_hwrm_ring_free(bp, close_path);
4858         bnxt_hwrm_ring_grp_free(bp);
4859         if (irq_re_init) {
4860                 bnxt_hwrm_stat_ctx_free(bp);
4861                 bnxt_hwrm_free_tunnel_ports(bp);
4862         }
4863 }
4864
4865 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4866 {
4867         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4868         int rc;
4869
4870         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
4871                 goto skip_rss_ctx;
4872
4873         /* allocate context for vnic */
4874         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
4875         if (rc) {
4876                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4877                            vnic_id, rc);
4878                 goto vnic_setup_err;
4879         }
4880         bp->rsscos_nr_ctxs++;
4881
4882         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4883                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4884                 if (rc) {
4885                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4886                                    vnic_id, rc);
4887                         goto vnic_setup_err;
4888                 }
4889                 bp->rsscos_nr_ctxs++;
4890         }
4891
4892 skip_rss_ctx:
4893         /* configure default vnic, ring grp */
4894         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4895         if (rc) {
4896                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4897                            vnic_id, rc);
4898                 goto vnic_setup_err;
4899         }
4900
4901         /* Enable RSS hashing on vnic */
4902         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4903         if (rc) {
4904                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4905                            vnic_id, rc);
4906                 goto vnic_setup_err;
4907         }
4908
4909         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4910                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4911                 if (rc) {
4912                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4913                                    vnic_id, rc);
4914                 }
4915         }
4916
4917 vnic_setup_err:
4918         return rc;
4919 }
4920
4921 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4922 {
4923 #ifdef CONFIG_RFS_ACCEL
4924         int i, rc = 0;
4925
4926         for (i = 0; i < bp->rx_nr_rings; i++) {
4927                 struct bnxt_vnic_info *vnic;
4928                 u16 vnic_id = i + 1;
4929                 u16 ring_id = i;
4930
4931                 if (vnic_id >= bp->nr_vnics)
4932                         break;
4933
4934                 vnic = &bp->vnic_info[vnic_id];
4935                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
4936                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
4937                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
4938                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4939                 if (rc) {
4940                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4941                                    vnic_id, rc);
4942                         break;
4943                 }
4944                 rc = bnxt_setup_vnic(bp, vnic_id);
4945                 if (rc)
4946                         break;
4947         }
4948         return rc;
4949 #else
4950         return 0;
4951 #endif
4952 }
4953
4954 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4955 static bool bnxt_promisc_ok(struct bnxt *bp)
4956 {
4957 #ifdef CONFIG_BNXT_SRIOV
4958         if (BNXT_VF(bp) && !bp->vf.vlan)
4959                 return false;
4960 #endif
4961         return true;
4962 }
4963
4964 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4965 {
4966         unsigned int rc = 0;
4967
4968         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4969         if (rc) {
4970                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4971                            rc);
4972                 return rc;
4973         }
4974
4975         rc = bnxt_hwrm_vnic_cfg(bp, 1);
4976         if (rc) {
4977                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4978                            rc);
4979                 return rc;
4980         }
4981         return rc;
4982 }
4983
4984 static int bnxt_cfg_rx_mode(struct bnxt *);
4985 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4986
4987 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4988 {
4989         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4990         int rc = 0;
4991         unsigned int rx_nr_rings = bp->rx_nr_rings;
4992
4993         if (irq_re_init) {
4994                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4995                 if (rc) {
4996                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4997                                    rc);
4998                         goto err_out;
4999                 }
5000         }
5001
5002         rc = bnxt_hwrm_ring_alloc(bp);
5003         if (rc) {
5004                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5005                 goto err_out;
5006         }
5007
5008         rc = bnxt_hwrm_ring_grp_alloc(bp);
5009         if (rc) {
5010                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5011                 goto err_out;
5012         }
5013
5014         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5015                 rx_nr_rings--;
5016
5017         /* default vnic 0 */
5018         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5019         if (rc) {
5020                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5021                 goto err_out;
5022         }
5023
5024         rc = bnxt_setup_vnic(bp, 0);
5025         if (rc)
5026                 goto err_out;
5027
5028         if (bp->flags & BNXT_FLAG_RFS) {
5029                 rc = bnxt_alloc_rfs_vnics(bp);
5030                 if (rc)
5031                         goto err_out;
5032         }
5033
5034         if (bp->flags & BNXT_FLAG_TPA) {
5035                 rc = bnxt_set_tpa(bp, true);
5036                 if (rc)
5037                         goto err_out;
5038         }
5039
5040         if (BNXT_VF(bp))
5041                 bnxt_update_vf_mac(bp);
5042
5043         /* Filter for default vnic 0 */
5044         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5045         if (rc) {
5046                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5047                 goto err_out;
5048         }
5049         vnic->uc_filter_count = 1;
5050
5051         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5052
5053         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5054                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5055
5056         if (bp->dev->flags & IFF_ALLMULTI) {
5057                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5058                 vnic->mc_list_count = 0;
5059         } else {
5060                 u32 mask = 0;
5061
5062                 bnxt_mc_list_updated(bp, &mask);
5063                 vnic->rx_mask |= mask;
5064         }
5065
5066         rc = bnxt_cfg_rx_mode(bp);
5067         if (rc)
5068                 goto err_out;
5069
5070         rc = bnxt_hwrm_set_coal(bp);
5071         if (rc)
5072                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5073                                 rc);
5074
5075         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5076                 rc = bnxt_setup_nitroa0_vnic(bp);
5077                 if (rc)
5078                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5079                                    rc);
5080         }
5081
5082         if (BNXT_VF(bp)) {
5083                 bnxt_hwrm_func_qcfg(bp);
5084                 netdev_update_features(bp->dev);
5085         }
5086
5087         return 0;
5088
5089 err_out:
5090         bnxt_hwrm_resource_free(bp, 0, true);
5091
5092         return rc;
5093 }
5094
5095 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5096 {
5097         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5098         return 0;
5099 }
5100
5101 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5102 {
5103         bnxt_init_cp_rings(bp);
5104         bnxt_init_rx_rings(bp);
5105         bnxt_init_tx_rings(bp);
5106         bnxt_init_ring_grps(bp, irq_re_init);
5107         bnxt_init_vnics(bp);
5108
5109         return bnxt_init_chip(bp, irq_re_init);
5110 }
5111
5112 static int bnxt_set_real_num_queues(struct bnxt *bp)
5113 {
5114         int rc;
5115         struct net_device *dev = bp->dev;
5116
5117         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5118                                           bp->tx_nr_rings_xdp);
5119         if (rc)
5120                 return rc;
5121
5122         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5123         if (rc)
5124                 return rc;
5125
5126 #ifdef CONFIG_RFS_ACCEL
5127         if (bp->flags & BNXT_FLAG_RFS)
5128                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5129 #endif
5130
5131         return rc;
5132 }
5133
5134 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5135                            bool shared)
5136 {
5137         int _rx = *rx, _tx = *tx;
5138
5139         if (shared) {
5140                 *rx = min_t(int, _rx, max);
5141                 *tx = min_t(int, _tx, max);
5142         } else {
5143                 if (max < 2)
5144                         return -ENOMEM;
5145
5146                 while (_rx + _tx > max) {
5147                         if (_rx > _tx && _rx > 1)
5148                                 _rx--;
5149                         else if (_tx > 1)
5150                                 _tx--;
5151                 }
5152                 *rx = _rx;
5153                 *tx = _tx;
5154         }
5155         return 0;
5156 }
5157
5158 static void bnxt_setup_msix(struct bnxt *bp)
5159 {
5160         const int len = sizeof(bp->irq_tbl[0].name);
5161         struct net_device *dev = bp->dev;
5162         int tcs, i;
5163
5164         tcs = netdev_get_num_tc(dev);
5165         if (tcs > 1) {
5166                 int i, off, count;
5167
5168                 for (i = 0; i < tcs; i++) {
5169                         count = bp->tx_nr_rings_per_tc;
5170                         off = i * count;
5171                         netdev_set_tc_queue(dev, i, count, off);
5172                 }
5173         }
5174
5175         for (i = 0; i < bp->cp_nr_rings; i++) {
5176                 char *attr;
5177
5178                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5179                         attr = "TxRx";
5180                 else if (i < bp->rx_nr_rings)
5181                         attr = "rx";
5182                 else
5183                         attr = "tx";
5184
5185                 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5186                          i);
5187                 bp->irq_tbl[i].handler = bnxt_msix;
5188         }
5189 }
5190
5191 static void bnxt_setup_inta(struct bnxt *bp)
5192 {
5193         const int len = sizeof(bp->irq_tbl[0].name);
5194
5195         if (netdev_get_num_tc(bp->dev))
5196                 netdev_reset_tc(bp->dev);
5197
5198         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5199                  0);
5200         bp->irq_tbl[0].handler = bnxt_inta;
5201 }
5202
5203 static int bnxt_setup_int_mode(struct bnxt *bp)
5204 {
5205         int rc;
5206
5207         if (bp->flags & BNXT_FLAG_USING_MSIX)
5208                 bnxt_setup_msix(bp);
5209         else
5210                 bnxt_setup_inta(bp);
5211
5212         rc = bnxt_set_real_num_queues(bp);
5213         return rc;
5214 }
5215
5216 #ifdef CONFIG_RFS_ACCEL
5217 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5218 {
5219 #if defined(CONFIG_BNXT_SRIOV)
5220         if (BNXT_VF(bp))
5221                 return bp->vf.max_rsscos_ctxs;
5222 #endif
5223         return bp->pf.max_rsscos_ctxs;
5224 }
5225
5226 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5227 {
5228 #if defined(CONFIG_BNXT_SRIOV)
5229         if (BNXT_VF(bp))
5230                 return bp->vf.max_vnics;
5231 #endif
5232         return bp->pf.max_vnics;
5233 }
5234 #endif
5235
5236 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5237 {
5238 #if defined(CONFIG_BNXT_SRIOV)
5239         if (BNXT_VF(bp))
5240                 return bp->vf.max_stat_ctxs;
5241 #endif
5242         return bp->pf.max_stat_ctxs;
5243 }
5244
5245 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5246 {
5247 #if defined(CONFIG_BNXT_SRIOV)
5248         if (BNXT_VF(bp))
5249                 bp->vf.max_stat_ctxs = max;
5250         else
5251 #endif
5252                 bp->pf.max_stat_ctxs = max;
5253 }
5254
5255 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5256 {
5257 #if defined(CONFIG_BNXT_SRIOV)
5258         if (BNXT_VF(bp))
5259                 return bp->vf.max_cp_rings;
5260 #endif
5261         return bp->pf.max_cp_rings;
5262 }
5263
5264 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5265 {
5266 #if defined(CONFIG_BNXT_SRIOV)
5267         if (BNXT_VF(bp))
5268                 bp->vf.max_cp_rings = max;
5269         else
5270 #endif
5271                 bp->pf.max_cp_rings = max;
5272 }
5273
5274 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5275 {
5276 #if defined(CONFIG_BNXT_SRIOV)
5277         if (BNXT_VF(bp))
5278                 return min_t(unsigned int, bp->vf.max_irqs,
5279                              bp->vf.max_cp_rings);
5280 #endif
5281         return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5282 }
5283
5284 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5285 {
5286 #if defined(CONFIG_BNXT_SRIOV)
5287         if (BNXT_VF(bp))
5288                 bp->vf.max_irqs = max_irqs;
5289         else
5290 #endif
5291                 bp->pf.max_irqs = max_irqs;
5292 }
5293
5294 static int bnxt_init_msix(struct bnxt *bp)
5295 {
5296         int i, total_vecs, rc = 0, min = 1;
5297         struct msix_entry *msix_ent;
5298
5299         total_vecs = bnxt_get_max_func_irqs(bp);
5300         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5301         if (!msix_ent)
5302                 return -ENOMEM;
5303
5304         for (i = 0; i < total_vecs; i++) {
5305                 msix_ent[i].entry = i;
5306                 msix_ent[i].vector = 0;
5307         }
5308
5309         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5310                 min = 2;
5311
5312         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5313         if (total_vecs < 0) {
5314                 rc = -ENODEV;
5315                 goto msix_setup_exit;
5316         }
5317
5318         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5319         if (bp->irq_tbl) {
5320                 for (i = 0; i < total_vecs; i++)
5321                         bp->irq_tbl[i].vector = msix_ent[i].vector;
5322
5323                 bp->total_irqs = total_vecs;
5324                 /* Trim rings based upon num of vectors allocated */
5325                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5326                                      total_vecs, min == 1);
5327                 if (rc)
5328                         goto msix_setup_exit;
5329
5330                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5331                 bp->cp_nr_rings = (min == 1) ?
5332                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5333                                   bp->tx_nr_rings + bp->rx_nr_rings;
5334
5335         } else {
5336                 rc = -ENOMEM;
5337                 goto msix_setup_exit;
5338         }
5339         bp->flags |= BNXT_FLAG_USING_MSIX;
5340         kfree(msix_ent);
5341         return 0;
5342
5343 msix_setup_exit:
5344         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5345         kfree(bp->irq_tbl);
5346         bp->irq_tbl = NULL;
5347         pci_disable_msix(bp->pdev);
5348         kfree(msix_ent);
5349         return rc;
5350 }
5351
5352 static int bnxt_init_inta(struct bnxt *bp)
5353 {
5354         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
5355         if (!bp->irq_tbl)
5356                 return -ENOMEM;
5357
5358         bp->total_irqs = 1;
5359         bp->rx_nr_rings = 1;
5360         bp->tx_nr_rings = 1;
5361         bp->cp_nr_rings = 1;
5362         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5363         bp->flags |= BNXT_FLAG_SHARED_RINGS;
5364         bp->irq_tbl[0].vector = bp->pdev->irq;
5365         return 0;
5366 }
5367
5368 static int bnxt_init_int_mode(struct bnxt *bp)
5369 {
5370         int rc = 0;
5371
5372         if (bp->flags & BNXT_FLAG_MSIX_CAP)
5373                 rc = bnxt_init_msix(bp);
5374
5375         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
5376                 /* fallback to INTA */
5377                 rc = bnxt_init_inta(bp);
5378         }
5379         return rc;
5380 }
5381
5382 static void bnxt_clear_int_mode(struct bnxt *bp)
5383 {
5384         if (bp->flags & BNXT_FLAG_USING_MSIX)
5385                 pci_disable_msix(bp->pdev);
5386
5387         kfree(bp->irq_tbl);
5388         bp->irq_tbl = NULL;
5389         bp->flags &= ~BNXT_FLAG_USING_MSIX;
5390 }
5391
5392 static void bnxt_free_irq(struct bnxt *bp)
5393 {
5394         struct bnxt_irq *irq;
5395         int i;
5396
5397 #ifdef CONFIG_RFS_ACCEL
5398         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5399         bp->dev->rx_cpu_rmap = NULL;
5400 #endif
5401         if (!bp->irq_tbl)
5402                 return;
5403
5404         for (i = 0; i < bp->cp_nr_rings; i++) {
5405                 irq = &bp->irq_tbl[i];
5406                 if (irq->requested)
5407                         free_irq(irq->vector, bp->bnapi[i]);
5408                 irq->requested = 0;
5409         }
5410 }
5411
5412 static int bnxt_request_irq(struct bnxt *bp)
5413 {
5414         int i, j, rc = 0;
5415         unsigned long flags = 0;
5416 #ifdef CONFIG_RFS_ACCEL
5417         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5418 #endif
5419
5420         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5421                 flags = IRQF_SHARED;
5422
5423         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
5424                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5425 #ifdef CONFIG_RFS_ACCEL
5426                 if (rmap && bp->bnapi[i]->rx_ring) {
5427                         rc = irq_cpu_rmap_add(rmap, irq->vector);
5428                         if (rc)
5429                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
5430                                             j);
5431                         j++;
5432                 }
5433 #endif
5434                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5435                                  bp->bnapi[i]);
5436                 if (rc)
5437                         break;
5438
5439                 irq->requested = 1;
5440         }
5441         return rc;
5442 }
5443
5444 static void bnxt_del_napi(struct bnxt *bp)
5445 {
5446         int i;
5447
5448         if (!bp->bnapi)
5449                 return;
5450
5451         for (i = 0; i < bp->cp_nr_rings; i++) {
5452                 struct bnxt_napi *bnapi = bp->bnapi[i];
5453
5454                 napi_hash_del(&bnapi->napi);
5455                 netif_napi_del(&bnapi->napi);
5456         }
5457         /* We called napi_hash_del() before netif_napi_del(), we need
5458          * to respect an RCU grace period before freeing napi structures.
5459          */
5460         synchronize_net();
5461 }
5462
5463 static void bnxt_init_napi(struct bnxt *bp)
5464 {
5465         int i;
5466         unsigned int cp_nr_rings = bp->cp_nr_rings;
5467         struct bnxt_napi *bnapi;
5468
5469         if (bp->flags & BNXT_FLAG_USING_MSIX) {
5470                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5471                         cp_nr_rings--;
5472                 for (i = 0; i < cp_nr_rings; i++) {
5473                         bnapi = bp->bnapi[i];
5474                         netif_napi_add(bp->dev, &bnapi->napi,
5475                                        bnxt_poll, 64);
5476                 }
5477                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5478                         bnapi = bp->bnapi[cp_nr_rings];
5479                         netif_napi_add(bp->dev, &bnapi->napi,
5480                                        bnxt_poll_nitroa0, 64);
5481                 }
5482         } else {
5483                 bnapi = bp->bnapi[0];
5484                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
5485         }
5486 }
5487
5488 static void bnxt_disable_napi(struct bnxt *bp)
5489 {
5490         int i;
5491
5492         if (!bp->bnapi)
5493                 return;
5494
5495         for (i = 0; i < bp->cp_nr_rings; i++)
5496                 napi_disable(&bp->bnapi[i]->napi);
5497 }
5498
5499 static void bnxt_enable_napi(struct bnxt *bp)
5500 {
5501         int i;
5502
5503         for (i = 0; i < bp->cp_nr_rings; i++) {
5504                 bp->bnapi[i]->in_reset = false;
5505                 napi_enable(&bp->bnapi[i]->napi);
5506         }
5507 }
5508
5509 void bnxt_tx_disable(struct bnxt *bp)
5510 {
5511         int i;
5512         struct bnxt_tx_ring_info *txr;
5513         struct netdev_queue *txq;
5514
5515         if (bp->tx_ring) {
5516                 for (i = 0; i < bp->tx_nr_rings; i++) {
5517                         txr = &bp->tx_ring[i];
5518                         txq = netdev_get_tx_queue(bp->dev, i);
5519                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
5520                 }
5521         }
5522         /* Stop all TX queues */
5523         netif_tx_disable(bp->dev);
5524         netif_carrier_off(bp->dev);
5525 }
5526
5527 void bnxt_tx_enable(struct bnxt *bp)
5528 {
5529         int i;
5530         struct bnxt_tx_ring_info *txr;
5531         struct netdev_queue *txq;
5532
5533         for (i = 0; i < bp->tx_nr_rings; i++) {
5534                 txr = &bp->tx_ring[i];
5535                 txq = netdev_get_tx_queue(bp->dev, i);
5536                 txr->dev_state = 0;
5537         }
5538         netif_tx_wake_all_queues(bp->dev);
5539         if (bp->link_info.link_up)
5540                 netif_carrier_on(bp->dev);
5541 }
5542
5543 static void bnxt_report_link(struct bnxt *bp)
5544 {
5545         if (bp->link_info.link_up) {
5546                 const char *duplex;
5547                 const char *flow_ctrl;
5548                 u32 speed;
5549                 u16 fec;
5550
5551                 netif_carrier_on(bp->dev);
5552                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5553                         duplex = "full";
5554                 else
5555                         duplex = "half";
5556                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5557                         flow_ctrl = "ON - receive & transmit";
5558                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5559                         flow_ctrl = "ON - transmit";
5560                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5561                         flow_ctrl = "ON - receive";
5562                 else
5563                         flow_ctrl = "none";
5564                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5565                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
5566                             speed, duplex, flow_ctrl);
5567                 if (bp->flags & BNXT_FLAG_EEE_CAP)
5568                         netdev_info(bp->dev, "EEE is %s\n",
5569                                     bp->eee.eee_active ? "active" :
5570                                                          "not active");
5571                 fec = bp->link_info.fec_cfg;
5572                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
5573                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
5574                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
5575                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
5576                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
5577         } else {
5578                 netif_carrier_off(bp->dev);
5579                 netdev_err(bp->dev, "NIC Link is Down\n");
5580         }
5581 }
5582
5583 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5584 {
5585         int rc = 0;
5586         struct hwrm_port_phy_qcaps_input req = {0};
5587         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5588         struct bnxt_link_info *link_info = &bp->link_info;
5589
5590         if (bp->hwrm_spec_code < 0x10201)
5591                 return 0;
5592
5593         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5594
5595         mutex_lock(&bp->hwrm_cmd_lock);
5596         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5597         if (rc)
5598                 goto hwrm_phy_qcaps_exit;
5599
5600         if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5601                 struct ethtool_eee *eee = &bp->eee;
5602                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5603
5604                 bp->flags |= BNXT_FLAG_EEE_CAP;
5605                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5606                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5607                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5608                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5609                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5610         }
5611         if (resp->supported_speeds_auto_mode)
5612                 link_info->support_auto_speeds =
5613                         le16_to_cpu(resp->supported_speeds_auto_mode);
5614
5615 hwrm_phy_qcaps_exit:
5616         mutex_unlock(&bp->hwrm_cmd_lock);
5617         return rc;
5618 }
5619
5620 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5621 {
5622         int rc = 0;
5623         struct bnxt_link_info *link_info = &bp->link_info;
5624         struct hwrm_port_phy_qcfg_input req = {0};
5625         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5626         u8 link_up = link_info->link_up;
5627         u16 diff;
5628
5629         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5630
5631         mutex_lock(&bp->hwrm_cmd_lock);
5632         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5633         if (rc) {
5634                 mutex_unlock(&bp->hwrm_cmd_lock);
5635                 return rc;
5636         }
5637
5638         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5639         link_info->phy_link_status = resp->link;
5640         link_info->duplex =  resp->duplex;
5641         link_info->pause = resp->pause;
5642         link_info->auto_mode = resp->auto_mode;
5643         link_info->auto_pause_setting = resp->auto_pause;
5644         link_info->lp_pause = resp->link_partner_adv_pause;
5645         link_info->force_pause_setting = resp->force_pause;
5646         link_info->duplex_setting = resp->duplex;
5647         if (link_info->phy_link_status == BNXT_LINK_LINK)
5648                 link_info->link_speed = le16_to_cpu(resp->link_speed);
5649         else
5650                 link_info->link_speed = 0;
5651         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5652         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5653         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5654         link_info->lp_auto_link_speeds =
5655                 le16_to_cpu(resp->link_partner_adv_speeds);
5656         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5657         link_info->phy_ver[0] = resp->phy_maj;
5658         link_info->phy_ver[1] = resp->phy_min;
5659         link_info->phy_ver[2] = resp->phy_bld;
5660         link_info->media_type = resp->media_type;
5661         link_info->phy_type = resp->phy_type;
5662         link_info->transceiver = resp->xcvr_pkg_type;
5663         link_info->phy_addr = resp->eee_config_phy_addr &
5664                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5665         link_info->module_status = resp->module_status;
5666
5667         if (bp->flags & BNXT_FLAG_EEE_CAP) {
5668                 struct ethtool_eee *eee = &bp->eee;
5669                 u16 fw_speeds;
5670
5671                 eee->eee_active = 0;
5672                 if (resp->eee_config_phy_addr &
5673                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5674                         eee->eee_active = 1;
5675                         fw_speeds = le16_to_cpu(
5676                                 resp->link_partner_adv_eee_link_speed_mask);
5677                         eee->lp_advertised =
5678                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5679                 }
5680
5681                 /* Pull initial EEE config */
5682                 if (!chng_link_state) {
5683                         if (resp->eee_config_phy_addr &
5684                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5685                                 eee->eee_enabled = 1;
5686
5687                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5688                         eee->advertised =
5689                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5690
5691                         if (resp->eee_config_phy_addr &
5692                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5693                                 __le32 tmr;
5694
5695                                 eee->tx_lpi_enabled = 1;
5696                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5697                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5698                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5699                         }
5700                 }
5701         }
5702
5703         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
5704         if (bp->hwrm_spec_code >= 0x10504)
5705                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
5706
5707         /* TODO: need to add more logic to report VF link */
5708         if (chng_link_state) {
5709                 if (link_info->phy_link_status == BNXT_LINK_LINK)
5710                         link_info->link_up = 1;
5711                 else
5712                         link_info->link_up = 0;
5713                 if (link_up != link_info->link_up)
5714                         bnxt_report_link(bp);
5715         } else {
5716                 /* alwasy link down if not require to update link state */
5717                 link_info->link_up = 0;
5718         }
5719         mutex_unlock(&bp->hwrm_cmd_lock);
5720
5721         diff = link_info->support_auto_speeds ^ link_info->advertising;
5722         if ((link_info->support_auto_speeds | diff) !=
5723             link_info->support_auto_speeds) {
5724                 /* An advertised speed is no longer supported, so we need to
5725                  * update the advertisement settings.  Caller holds RTNL
5726                  * so we can modify link settings.
5727                  */
5728                 link_info->advertising = link_info->support_auto_speeds;
5729                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5730                         bnxt_hwrm_set_link_setting(bp, true, false);
5731         }
5732         return 0;
5733 }
5734
5735 static void bnxt_get_port_module_status(struct bnxt *bp)
5736 {
5737         struct bnxt_link_info *link_info = &bp->link_info;
5738         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5739         u8 module_status;
5740
5741         if (bnxt_update_link(bp, true))
5742                 return;
5743
5744         module_status = link_info->module_status;
5745         switch (module_status) {
5746         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5747         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5748         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5749                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5750                             bp->pf.port_id);
5751                 if (bp->hwrm_spec_code >= 0x10201) {
5752                         netdev_warn(bp->dev, "Module part number %s\n",
5753                                     resp->phy_vendor_partnumber);
5754                 }
5755                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5756                         netdev_warn(bp->dev, "TX is disabled\n");
5757                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5758                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5759         }
5760 }
5761
5762 static void
5763 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5764 {
5765         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
5766                 if (bp->hwrm_spec_code >= 0x10201)
5767                         req->auto_pause =
5768                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
5769                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5770                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5771                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5772                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
5773                 req->enables |=
5774                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5775         } else {
5776                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5777                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5778                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5779                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5780                 req->enables |=
5781                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5782                 if (bp->hwrm_spec_code >= 0x10201) {
5783                         req->auto_pause = req->force_pause;
5784                         req->enables |= cpu_to_le32(
5785                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5786                 }
5787         }
5788 }
5789
5790 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5791                                       struct hwrm_port_phy_cfg_input *req)
5792 {
5793         u8 autoneg = bp->link_info.autoneg;
5794         u16 fw_link_speed = bp->link_info.req_link_speed;
5795         u16 advertising = bp->link_info.advertising;
5796
5797         if (autoneg & BNXT_AUTONEG_SPEED) {
5798                 req->auto_mode |=
5799                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5800
5801                 req->enables |= cpu_to_le32(
5802                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5803                 req->auto_link_speed_mask = cpu_to_le16(advertising);
5804
5805                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5806                 req->flags |=
5807                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5808         } else {
5809                 req->force_link_speed = cpu_to_le16(fw_link_speed);
5810                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5811         }
5812
5813         /* tell chimp that the setting takes effect immediately */
5814         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5815 }
5816
5817 int bnxt_hwrm_set_pause(struct bnxt *bp)
5818 {
5819         struct hwrm_port_phy_cfg_input req = {0};
5820         int rc;
5821
5822         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5823         bnxt_hwrm_set_pause_common(bp, &req);
5824
5825         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5826             bp->link_info.force_link_chng)
5827                 bnxt_hwrm_set_link_common(bp, &req);
5828
5829         mutex_lock(&bp->hwrm_cmd_lock);
5830         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5831         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5832                 /* since changing of pause setting doesn't trigger any link
5833                  * change event, the driver needs to update the current pause
5834                  * result upon successfully return of the phy_cfg command
5835                  */
5836                 bp->link_info.pause =
5837                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5838                 bp->link_info.auto_pause_setting = 0;
5839                 if (!bp->link_info.force_link_chng)
5840                         bnxt_report_link(bp);
5841         }
5842         bp->link_info.force_link_chng = false;
5843         mutex_unlock(&bp->hwrm_cmd_lock);
5844         return rc;
5845 }
5846
5847 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5848                               struct hwrm_port_phy_cfg_input *req)
5849 {
5850         struct ethtool_eee *eee = &bp->eee;
5851
5852         if (eee->eee_enabled) {
5853                 u16 eee_speeds;
5854                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5855
5856                 if (eee->tx_lpi_enabled)
5857                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5858                 else
5859                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5860
5861                 req->flags |= cpu_to_le32(flags);
5862                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5863                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5864                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5865         } else {
5866                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5867         }
5868 }
5869
5870 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5871 {
5872         struct hwrm_port_phy_cfg_input req = {0};
5873
5874         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5875         if (set_pause)
5876                 bnxt_hwrm_set_pause_common(bp, &req);
5877
5878         bnxt_hwrm_set_link_common(bp, &req);
5879
5880         if (set_eee)
5881                 bnxt_hwrm_set_eee(bp, &req);
5882         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5883 }
5884
5885 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5886 {
5887         struct hwrm_port_phy_cfg_input req = {0};
5888
5889         if (!BNXT_SINGLE_PF(bp))
5890                 return 0;
5891
5892         if (pci_num_vf(bp->pdev))
5893                 return 0;
5894
5895         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5896         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
5897         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5898 }
5899
5900 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
5901 {
5902         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5903         struct hwrm_port_led_qcaps_input req = {0};
5904         struct bnxt_pf_info *pf = &bp->pf;
5905         int rc;
5906
5907         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
5908                 return 0;
5909
5910         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
5911         req.port_id = cpu_to_le16(pf->port_id);
5912         mutex_lock(&bp->hwrm_cmd_lock);
5913         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5914         if (rc) {
5915                 mutex_unlock(&bp->hwrm_cmd_lock);
5916                 return rc;
5917         }
5918         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
5919                 int i;
5920
5921                 bp->num_leds = resp->num_leds;
5922                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
5923                                                  bp->num_leds);
5924                 for (i = 0; i < bp->num_leds; i++) {
5925                         struct bnxt_led_info *led = &bp->leds[i];
5926                         __le16 caps = led->led_state_caps;
5927
5928                         if (!led->led_group_id ||
5929                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
5930                                 bp->num_leds = 0;
5931                                 break;
5932                         }
5933                 }
5934         }
5935         mutex_unlock(&bp->hwrm_cmd_lock);
5936         return 0;
5937 }
5938
5939 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
5940 {
5941         struct hwrm_wol_filter_alloc_input req = {0};
5942         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5943         int rc;
5944
5945         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
5946         req.port_id = cpu_to_le16(bp->pf.port_id);
5947         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
5948         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
5949         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
5950         mutex_lock(&bp->hwrm_cmd_lock);
5951         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5952         if (!rc)
5953                 bp->wol_filter_id = resp->wol_filter_id;
5954         mutex_unlock(&bp->hwrm_cmd_lock);
5955         return rc;
5956 }
5957
5958 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
5959 {
5960         struct hwrm_wol_filter_free_input req = {0};
5961         int rc;
5962
5963         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
5964         req.port_id = cpu_to_le16(bp->pf.port_id);
5965         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
5966         req.wol_filter_id = bp->wol_filter_id;
5967         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5968         return rc;
5969 }
5970
5971 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
5972 {
5973         struct hwrm_wol_filter_qcfg_input req = {0};
5974         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5975         u16 next_handle = 0;
5976         int rc;
5977
5978         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
5979         req.port_id = cpu_to_le16(bp->pf.port_id);
5980         req.handle = cpu_to_le16(handle);
5981         mutex_lock(&bp->hwrm_cmd_lock);
5982         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5983         if (!rc) {
5984                 next_handle = le16_to_cpu(resp->next_handle);
5985                 if (next_handle != 0) {
5986                         if (resp->wol_type ==
5987                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
5988                                 bp->wol = 1;
5989                                 bp->wol_filter_id = resp->wol_filter_id;
5990                         }
5991                 }
5992         }
5993         mutex_unlock(&bp->hwrm_cmd_lock);
5994         return next_handle;
5995 }
5996
5997 static void bnxt_get_wol_settings(struct bnxt *bp)
5998 {
5999         u16 handle = 0;
6000
6001         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6002                 return;
6003
6004         do {
6005                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6006         } while (handle && handle != 0xffff);
6007 }
6008
6009 static bool bnxt_eee_config_ok(struct bnxt *bp)
6010 {
6011         struct ethtool_eee *eee = &bp->eee;
6012         struct bnxt_link_info *link_info = &bp->link_info;
6013
6014         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6015                 return true;
6016
6017         if (eee->eee_enabled) {
6018                 u32 advertising =
6019                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6020
6021                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6022                         eee->eee_enabled = 0;
6023                         return false;
6024                 }
6025                 if (eee->advertised & ~advertising) {
6026                         eee->advertised = advertising & eee->supported;
6027                         return false;
6028                 }
6029         }
6030         return true;
6031 }
6032
6033 static int bnxt_update_phy_setting(struct bnxt *bp)
6034 {
6035         int rc;
6036         bool update_link = false;
6037         bool update_pause = false;
6038         bool update_eee = false;
6039         struct bnxt_link_info *link_info = &bp->link_info;
6040
6041         rc = bnxt_update_link(bp, true);
6042         if (rc) {
6043                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6044                            rc);
6045                 return rc;
6046         }
6047         if (!BNXT_SINGLE_PF(bp))
6048                 return 0;
6049
6050         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6051             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6052             link_info->req_flow_ctrl)
6053                 update_pause = true;
6054         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6055             link_info->force_pause_setting != link_info->req_flow_ctrl)
6056                 update_pause = true;
6057         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6058                 if (BNXT_AUTO_MODE(link_info->auto_mode))
6059                         update_link = true;
6060                 if (link_info->req_link_speed != link_info->force_link_speed)
6061                         update_link = true;
6062                 if (link_info->req_duplex != link_info->duplex_setting)
6063                         update_link = true;
6064         } else {
6065                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6066                         update_link = true;
6067                 if (link_info->advertising != link_info->auto_link_speeds)
6068                         update_link = true;
6069         }
6070
6071         /* The last close may have shutdown the link, so need to call
6072          * PHY_CFG to bring it back up.
6073          */
6074         if (!netif_carrier_ok(bp->dev))
6075                 update_link = true;
6076
6077         if (!bnxt_eee_config_ok(bp))
6078                 update_eee = true;
6079
6080         if (update_link)
6081                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6082         else if (update_pause)
6083                 rc = bnxt_hwrm_set_pause(bp);
6084         if (rc) {
6085                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6086                            rc);
6087                 return rc;
6088         }
6089
6090         return rc;
6091 }
6092
6093 /* Common routine to pre-map certain register block to different GRC window.
6094  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6095  * in PF and 3 windows in VF that can be customized to map in different
6096  * register blocks.
6097  */
6098 static void bnxt_preset_reg_win(struct bnxt *bp)
6099 {
6100         if (BNXT_PF(bp)) {
6101                 /* CAG registers map to GRC window #4 */
6102                 writel(BNXT_CAG_REG_BASE,
6103                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6104         }
6105 }
6106
6107 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6108 {
6109         int rc = 0;
6110
6111         bnxt_preset_reg_win(bp);
6112         netif_carrier_off(bp->dev);
6113         if (irq_re_init) {
6114                 rc = bnxt_setup_int_mode(bp);
6115                 if (rc) {
6116                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6117                                    rc);
6118                         return rc;
6119                 }
6120         }
6121         if ((bp->flags & BNXT_FLAG_RFS) &&
6122             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6123                 /* disable RFS if falling back to INTA */
6124                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6125                 bp->flags &= ~BNXT_FLAG_RFS;
6126         }
6127
6128         rc = bnxt_alloc_mem(bp, irq_re_init);
6129         if (rc) {
6130                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6131                 goto open_err_free_mem;
6132         }
6133
6134         if (irq_re_init) {
6135                 bnxt_init_napi(bp);
6136                 rc = bnxt_request_irq(bp);
6137                 if (rc) {
6138                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6139                         goto open_err;
6140                 }
6141         }
6142
6143         bnxt_enable_napi(bp);
6144
6145         rc = bnxt_init_nic(bp, irq_re_init);
6146         if (rc) {
6147                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6148                 goto open_err;
6149         }
6150
6151         if (link_re_init) {
6152                 rc = bnxt_update_phy_setting(bp);
6153                 if (rc)
6154                         netdev_warn(bp->dev, "failed to update phy settings\n");
6155         }
6156
6157         if (irq_re_init)
6158                 udp_tunnel_get_rx_info(bp->dev);
6159
6160         set_bit(BNXT_STATE_OPEN, &bp->state);
6161         bnxt_enable_int(bp);
6162         /* Enable TX queues */
6163         bnxt_tx_enable(bp);
6164         mod_timer(&bp->timer, jiffies + bp->current_interval);
6165         /* Poll link status and check for SFP+ module status */
6166         bnxt_get_port_module_status(bp);
6167
6168         return 0;
6169
6170 open_err:
6171         bnxt_disable_napi(bp);
6172         bnxt_del_napi(bp);
6173
6174 open_err_free_mem:
6175         bnxt_free_skbs(bp);
6176         bnxt_free_irq(bp);
6177         bnxt_free_mem(bp, true);
6178         return rc;
6179 }
6180
6181 /* rtnl_lock held */
6182 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6183 {
6184         int rc = 0;
6185
6186         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6187         if (rc) {
6188                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6189                 dev_close(bp->dev);
6190         }
6191         return rc;
6192 }
6193
6194 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6195  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
6196  * self tests.
6197  */
6198 int bnxt_half_open_nic(struct bnxt *bp)
6199 {
6200         int rc = 0;
6201
6202         rc = bnxt_alloc_mem(bp, false);
6203         if (rc) {
6204                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6205                 goto half_open_err;
6206         }
6207         rc = bnxt_init_nic(bp, false);
6208         if (rc) {
6209                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6210                 goto half_open_err;
6211         }
6212         return 0;
6213
6214 half_open_err:
6215         bnxt_free_skbs(bp);
6216         bnxt_free_mem(bp, false);
6217         dev_close(bp->dev);
6218         return rc;
6219 }
6220
6221 /* rtnl_lock held, this call can only be made after a previous successful
6222  * call to bnxt_half_open_nic().
6223  */
6224 void bnxt_half_close_nic(struct bnxt *bp)
6225 {
6226         bnxt_hwrm_resource_free(bp, false, false);
6227         bnxt_free_skbs(bp);
6228         bnxt_free_mem(bp, false);
6229 }
6230
6231 static int bnxt_open(struct net_device *dev)
6232 {
6233         struct bnxt *bp = netdev_priv(dev);
6234
6235         return __bnxt_open_nic(bp, true, true);
6236 }
6237
6238 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6239 {
6240         int rc = 0;
6241
6242 #ifdef CONFIG_BNXT_SRIOV
6243         if (bp->sriov_cfg) {
6244                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6245                                                       !bp->sriov_cfg,
6246                                                       BNXT_SRIOV_CFG_WAIT_TMO);
6247                 if (rc)
6248                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6249         }
6250 #endif
6251         /* Change device state to avoid TX queue wake up's */
6252         bnxt_tx_disable(bp);
6253
6254         clear_bit(BNXT_STATE_OPEN, &bp->state);
6255         smp_mb__after_atomic();
6256         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
6257                 msleep(20);
6258
6259         /* Flush rings and and disable interrupts */
6260         bnxt_shutdown_nic(bp, irq_re_init);
6261
6262         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6263
6264         bnxt_disable_napi(bp);
6265         del_timer_sync(&bp->timer);
6266         bnxt_free_skbs(bp);
6267
6268         if (irq_re_init) {
6269                 bnxt_free_irq(bp);
6270                 bnxt_del_napi(bp);
6271         }
6272         bnxt_free_mem(bp, irq_re_init);
6273         return rc;
6274 }
6275
6276 static int bnxt_close(struct net_device *dev)
6277 {
6278         struct bnxt *bp = netdev_priv(dev);
6279
6280         bnxt_close_nic(bp, true, true);
6281         bnxt_hwrm_shutdown_link(bp);
6282         return 0;
6283 }
6284
6285 /* rtnl_lock held */
6286 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6287 {
6288         switch (cmd) {
6289         case SIOCGMIIPHY:
6290                 /* fallthru */
6291         case SIOCGMIIREG: {
6292                 if (!netif_running(dev))
6293                         return -EAGAIN;
6294
6295                 return 0;
6296         }
6297
6298         case SIOCSMIIREG:
6299                 if (!netif_running(dev))
6300                         return -EAGAIN;
6301
6302                 return 0;
6303
6304         default:
6305                 /* do nothing */
6306                 break;
6307         }
6308         return -EOPNOTSUPP;
6309 }
6310
6311 static void
6312 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6313 {
6314         u32 i;
6315         struct bnxt *bp = netdev_priv(dev);
6316
6317         if (!bp->bnapi)
6318                 return;
6319
6320         /* TODO check if we need to synchronize with bnxt_close path */
6321         for (i = 0; i < bp->cp_nr_rings; i++) {
6322                 struct bnxt_napi *bnapi = bp->bnapi[i];
6323                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6324                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6325
6326                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6327                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6328                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6329
6330                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6331                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6332                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6333
6334                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6335                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6336                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6337
6338                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6339                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6340                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6341
6342                 stats->rx_missed_errors +=
6343                         le64_to_cpu(hw_stats->rx_discard_pkts);
6344
6345                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6346
6347                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6348         }
6349
6350         if (bp->flags & BNXT_FLAG_PORT_STATS) {
6351                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6352                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6353
6354                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6355                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6356                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6357                                           le64_to_cpu(rx->rx_ovrsz_frames) +
6358                                           le64_to_cpu(rx->rx_runt_frames);
6359                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6360                                    le64_to_cpu(rx->rx_jbr_frames);
6361                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6362                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6363                 stats->tx_errors = le64_to_cpu(tx->tx_err);
6364         }
6365 }
6366
6367 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6368 {
6369         struct net_device *dev = bp->dev;
6370         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6371         struct netdev_hw_addr *ha;
6372         u8 *haddr;
6373         int mc_count = 0;
6374         bool update = false;
6375         int off = 0;
6376
6377         netdev_for_each_mc_addr(ha, dev) {
6378                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6379                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6380                         vnic->mc_list_count = 0;
6381                         return false;
6382                 }
6383                 haddr = ha->addr;
6384                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6385                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6386                         update = true;
6387                 }
6388                 off += ETH_ALEN;
6389                 mc_count++;
6390         }
6391         if (mc_count)
6392                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6393
6394         if (mc_count != vnic->mc_list_count) {
6395                 vnic->mc_list_count = mc_count;
6396                 update = true;
6397         }
6398         return update;
6399 }
6400
6401 static bool bnxt_uc_list_updated(struct bnxt *bp)
6402 {
6403         struct net_device *dev = bp->dev;
6404         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6405         struct netdev_hw_addr *ha;
6406         int off = 0;
6407
6408         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6409                 return true;
6410
6411         netdev_for_each_uc_addr(ha, dev) {
6412                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6413                         return true;
6414
6415                 off += ETH_ALEN;
6416         }
6417         return false;
6418 }
6419
6420 static void bnxt_set_rx_mode(struct net_device *dev)
6421 {
6422         struct bnxt *bp = netdev_priv(dev);
6423         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6424         u32 mask = vnic->rx_mask;
6425         bool mc_update = false;
6426         bool uc_update;
6427
6428         if (!netif_running(dev))
6429                 return;
6430
6431         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6432                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6433                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6434
6435         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
6436                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6437
6438         uc_update = bnxt_uc_list_updated(bp);
6439
6440         if (dev->flags & IFF_ALLMULTI) {
6441                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6442                 vnic->mc_list_count = 0;
6443         } else {
6444                 mc_update = bnxt_mc_list_updated(bp, &mask);
6445         }
6446
6447         if (mask != vnic->rx_mask || uc_update || mc_update) {
6448                 vnic->rx_mask = mask;
6449
6450                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6451                 schedule_work(&bp->sp_task);
6452         }
6453 }
6454
6455 static int bnxt_cfg_rx_mode(struct bnxt *bp)
6456 {
6457         struct net_device *dev = bp->dev;
6458         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6459         struct netdev_hw_addr *ha;
6460         int i, off = 0, rc;
6461         bool uc_update;
6462
6463         netif_addr_lock_bh(dev);
6464         uc_update = bnxt_uc_list_updated(bp);
6465         netif_addr_unlock_bh(dev);
6466
6467         if (!uc_update)
6468                 goto skip_uc;
6469
6470         mutex_lock(&bp->hwrm_cmd_lock);
6471         for (i = 1; i < vnic->uc_filter_count; i++) {
6472                 struct hwrm_cfa_l2_filter_free_input req = {0};
6473
6474                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6475                                        -1);
6476
6477                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6478
6479                 rc = _hwrm_send_message(bp, &req, sizeof(req),
6480                                         HWRM_CMD_TIMEOUT);
6481         }
6482         mutex_unlock(&bp->hwrm_cmd_lock);
6483
6484         vnic->uc_filter_count = 1;
6485
6486         netif_addr_lock_bh(dev);
6487         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6488                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6489         } else {
6490                 netdev_for_each_uc_addr(ha, dev) {
6491                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6492                         off += ETH_ALEN;
6493                         vnic->uc_filter_count++;
6494                 }
6495         }
6496         netif_addr_unlock_bh(dev);
6497
6498         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6499                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6500                 if (rc) {
6501                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6502                                    rc);
6503                         vnic->uc_filter_count = i;
6504                         return rc;
6505                 }
6506         }
6507
6508 skip_uc:
6509         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6510         if (rc)
6511                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6512                            rc);
6513
6514         return rc;
6515 }
6516
6517 /* If the chip and firmware supports RFS */
6518 static bool bnxt_rfs_supported(struct bnxt *bp)
6519 {
6520         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6521                 return true;
6522         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6523                 return true;
6524         return false;
6525 }
6526
6527 /* If runtime conditions support RFS */
6528 static bool bnxt_rfs_capable(struct bnxt *bp)
6529 {
6530 #ifdef CONFIG_RFS_ACCEL
6531         int vnics, max_vnics, max_rss_ctxs;
6532
6533         if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
6534                 return false;
6535
6536         vnics = 1 + bp->rx_nr_rings;
6537         max_vnics = bnxt_get_max_func_vnics(bp);
6538         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
6539
6540         /* RSS contexts not a limiting factor */
6541         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6542                 max_rss_ctxs = max_vnics;
6543         if (vnics > max_vnics || vnics > max_rss_ctxs) {
6544                 netdev_warn(bp->dev,
6545                             "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6546                             min(max_rss_ctxs - 1, max_vnics - 1));
6547                 return false;
6548         }
6549
6550         return true;
6551 #else
6552         return false;
6553 #endif
6554 }
6555
6556 static netdev_features_t bnxt_fix_features(struct net_device *dev,
6557                                            netdev_features_t features)
6558 {
6559         struct bnxt *bp = netdev_priv(dev);
6560
6561         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
6562                 features &= ~NETIF_F_NTUPLE;
6563
6564         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6565          * turned on or off together.
6566          */
6567         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6568             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6569                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6570                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6571                                       NETIF_F_HW_VLAN_STAG_RX);
6572                 else
6573                         features |= NETIF_F_HW_VLAN_CTAG_RX |
6574                                     NETIF_F_HW_VLAN_STAG_RX;
6575         }
6576 #ifdef CONFIG_BNXT_SRIOV
6577         if (BNXT_VF(bp)) {
6578                 if (bp->vf.vlan) {
6579                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6580                                       NETIF_F_HW_VLAN_STAG_RX);
6581                 }
6582         }
6583 #endif
6584         return features;
6585 }
6586
6587 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6588 {
6589         struct bnxt *bp = netdev_priv(dev);
6590         u32 flags = bp->flags;
6591         u32 changes;
6592         int rc = 0;
6593         bool re_init = false;
6594         bool update_tpa = false;
6595
6596         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
6597         if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6598                 flags |= BNXT_FLAG_GRO;
6599         if (features & NETIF_F_LRO)
6600                 flags |= BNXT_FLAG_LRO;
6601
6602         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6603                 flags &= ~BNXT_FLAG_TPA;
6604
6605         if (features & NETIF_F_HW_VLAN_CTAG_RX)
6606                 flags |= BNXT_FLAG_STRIP_VLAN;
6607
6608         if (features & NETIF_F_NTUPLE)
6609                 flags |= BNXT_FLAG_RFS;
6610
6611         changes = flags ^ bp->flags;
6612         if (changes & BNXT_FLAG_TPA) {
6613                 update_tpa = true;
6614                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6615                     (flags & BNXT_FLAG_TPA) == 0)
6616                         re_init = true;
6617         }
6618
6619         if (changes & ~BNXT_FLAG_TPA)
6620                 re_init = true;
6621
6622         if (flags != bp->flags) {
6623                 u32 old_flags = bp->flags;
6624
6625                 bp->flags = flags;
6626
6627                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6628                         if (update_tpa)
6629                                 bnxt_set_ring_params(bp);
6630                         return rc;
6631                 }
6632
6633                 if (re_init) {
6634                         bnxt_close_nic(bp, false, false);
6635                         if (update_tpa)
6636                                 bnxt_set_ring_params(bp);
6637
6638                         return bnxt_open_nic(bp, false, false);
6639                 }
6640                 if (update_tpa) {
6641                         rc = bnxt_set_tpa(bp,
6642                                           (flags & BNXT_FLAG_TPA) ?
6643                                           true : false);
6644                         if (rc)
6645                                 bp->flags = old_flags;
6646                 }
6647         }
6648         return rc;
6649 }
6650
6651 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6652 {
6653         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
6654         int i = bnapi->index;
6655
6656         if (!txr)
6657                 return;
6658
6659         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6660                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6661                     txr->tx_cons);
6662 }
6663
6664 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6665 {
6666         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
6667         int i = bnapi->index;
6668
6669         if (!rxr)
6670                 return;
6671
6672         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6673                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6674                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6675                     rxr->rx_sw_agg_prod);
6676 }
6677
6678 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6679 {
6680         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6681         int i = bnapi->index;
6682
6683         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6684                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6685 }
6686
6687 static void bnxt_dbg_dump_states(struct bnxt *bp)
6688 {
6689         int i;
6690         struct bnxt_napi *bnapi;
6691
6692         for (i = 0; i < bp->cp_nr_rings; i++) {
6693                 bnapi = bp->bnapi[i];
6694                 if (netif_msg_drv(bp)) {
6695                         bnxt_dump_tx_sw_state(bnapi);
6696                         bnxt_dump_rx_sw_state(bnapi);
6697                         bnxt_dump_cp_sw_state(bnapi);
6698                 }
6699         }
6700 }
6701
6702 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6703 {
6704         if (!silent)
6705                 bnxt_dbg_dump_states(bp);
6706         if (netif_running(bp->dev)) {
6707                 int rc;
6708
6709                 if (!silent)
6710                         bnxt_ulp_stop(bp);
6711                 bnxt_close_nic(bp, false, false);
6712                 rc = bnxt_open_nic(bp, false, false);
6713                 if (!silent && !rc)
6714                         bnxt_ulp_start(bp);
6715         }
6716 }
6717
6718 static void bnxt_tx_timeout(struct net_device *dev)
6719 {
6720         struct bnxt *bp = netdev_priv(dev);
6721
6722         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
6723         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6724         schedule_work(&bp->sp_task);
6725 }
6726
6727 #ifdef CONFIG_NET_POLL_CONTROLLER
6728 static void bnxt_poll_controller(struct net_device *dev)
6729 {
6730         struct bnxt *bp = netdev_priv(dev);
6731         int i;
6732
6733         for (i = 0; i < bp->cp_nr_rings; i++) {
6734                 struct bnxt_irq *irq = &bp->irq_tbl[i];
6735
6736                 disable_irq(irq->vector);
6737                 irq->handler(irq->vector, bp->bnapi[i]);
6738                 enable_irq(irq->vector);
6739         }
6740 }
6741 #endif
6742
6743 static void bnxt_timer(unsigned long data)
6744 {
6745         struct bnxt *bp = (struct bnxt *)data;
6746         struct net_device *dev = bp->dev;
6747
6748         if (!netif_running(dev))
6749                 return;
6750
6751         if (atomic_read(&bp->intr_sem) != 0)
6752                 goto bnxt_restart_timer;
6753
6754         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6755                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6756                 schedule_work(&bp->sp_task);
6757         }
6758 bnxt_restart_timer:
6759         mod_timer(&bp->timer, jiffies + bp->current_interval);
6760 }
6761
6762 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6763 {
6764         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6765          * set.  If the device is being closed, bnxt_close() may be holding
6766          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
6767          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6768          */
6769         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6770         rtnl_lock();
6771 }
6772
6773 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
6774 {
6775         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6776         rtnl_unlock();
6777 }
6778
6779 /* Only called from bnxt_sp_task() */
6780 static void bnxt_reset(struct bnxt *bp, bool silent)
6781 {
6782         bnxt_rtnl_lock_sp(bp);
6783         if (test_bit(BNXT_STATE_OPEN, &bp->state))
6784                 bnxt_reset_task(bp, silent);
6785         bnxt_rtnl_unlock_sp(bp);
6786 }
6787
6788 static void bnxt_cfg_ntp_filters(struct bnxt *);
6789
6790 static void bnxt_sp_task(struct work_struct *work)
6791 {
6792         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
6793
6794         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6795         smp_mb__after_atomic();
6796         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6797                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6798                 return;
6799         }
6800
6801         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6802                 bnxt_cfg_rx_mode(bp);
6803
6804         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6805                 bnxt_cfg_ntp_filters(bp);
6806         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6807                 bnxt_hwrm_exec_fwd_req(bp);
6808         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6809                 bnxt_hwrm_tunnel_dst_port_alloc(
6810                         bp, bp->vxlan_port,
6811                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6812         }
6813         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6814                 bnxt_hwrm_tunnel_dst_port_free(
6815                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6816         }
6817         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6818                 bnxt_hwrm_tunnel_dst_port_alloc(
6819                         bp, bp->nge_port,
6820                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6821         }
6822         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6823                 bnxt_hwrm_tunnel_dst_port_free(
6824                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6825         }
6826         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6827                 bnxt_hwrm_port_qstats(bp);
6828
6829         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
6830          * must be the last functions to be called before exiting.
6831          */
6832         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6833                 int rc = 0;
6834
6835                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
6836                                        &bp->sp_event))
6837                         bnxt_hwrm_phy_qcaps(bp);
6838
6839                 bnxt_rtnl_lock_sp(bp);
6840                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6841                         rc = bnxt_update_link(bp, true);
6842                 bnxt_rtnl_unlock_sp(bp);
6843                 if (rc)
6844                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6845                                    rc);
6846         }
6847         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
6848                 bnxt_rtnl_lock_sp(bp);
6849                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6850                         bnxt_get_port_module_status(bp);
6851                 bnxt_rtnl_unlock_sp(bp);
6852         }
6853         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6854                 bnxt_reset(bp, false);
6855
6856         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6857                 bnxt_reset(bp, true);
6858
6859         smp_mb__before_atomic();
6860         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6861 }
6862
6863 /* Under rtnl_lock */
6864 int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp)
6865 {
6866         int max_rx, max_tx, tx_sets = 1;
6867         int tx_rings_needed;
6868         bool sh = true;
6869         int rc;
6870
6871         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6872                 sh = false;
6873
6874         if (tcs)
6875                 tx_sets = tcs;
6876
6877         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
6878         if (rc)
6879                 return rc;
6880
6881         if (max_rx < rx)
6882                 return -ENOMEM;
6883
6884         tx_rings_needed = tx * tx_sets + tx_xdp;
6885         if (max_tx < tx_rings_needed)
6886                 return -ENOMEM;
6887
6888         if (bnxt_hwrm_reserve_tx_rings(bp, &tx_rings_needed) ||
6889             tx_rings_needed < (tx * tx_sets + tx_xdp))
6890                 return -ENOMEM;
6891         return 0;
6892 }
6893
6894 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
6895 {
6896         if (bp->bar2) {
6897                 pci_iounmap(pdev, bp->bar2);
6898                 bp->bar2 = NULL;
6899         }
6900
6901         if (bp->bar1) {
6902                 pci_iounmap(pdev, bp->bar1);
6903                 bp->bar1 = NULL;
6904         }
6905
6906         if (bp->bar0) {
6907                 pci_iounmap(pdev, bp->bar0);
6908                 bp->bar0 = NULL;
6909         }
6910 }
6911
6912 static void bnxt_cleanup_pci(struct bnxt *bp)
6913 {
6914         bnxt_unmap_bars(bp, bp->pdev);
6915         pci_release_regions(bp->pdev);
6916         pci_disable_device(bp->pdev);
6917 }
6918
6919 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6920 {
6921         int rc;
6922         struct bnxt *bp = netdev_priv(dev);
6923
6924         SET_NETDEV_DEV(dev, &pdev->dev);
6925
6926         /* enable device (incl. PCI PM wakeup), and bus-mastering */
6927         rc = pci_enable_device(pdev);
6928         if (rc) {
6929                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6930                 goto init_err;
6931         }
6932
6933         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6934                 dev_err(&pdev->dev,
6935                         "Cannot find PCI device base address, aborting\n");
6936                 rc = -ENODEV;
6937                 goto init_err_disable;
6938         }
6939
6940         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6941         if (rc) {
6942                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6943                 goto init_err_disable;
6944         }
6945
6946         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6947             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6948                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6949                 goto init_err_disable;
6950         }
6951
6952         pci_set_master(pdev);
6953
6954         bp->dev = dev;
6955         bp->pdev = pdev;
6956
6957         bp->bar0 = pci_ioremap_bar(pdev, 0);
6958         if (!bp->bar0) {
6959                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6960                 rc = -ENOMEM;
6961                 goto init_err_release;
6962         }
6963
6964         bp->bar1 = pci_ioremap_bar(pdev, 2);
6965         if (!bp->bar1) {
6966                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6967                 rc = -ENOMEM;
6968                 goto init_err_release;
6969         }
6970
6971         bp->bar2 = pci_ioremap_bar(pdev, 4);
6972         if (!bp->bar2) {
6973                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6974                 rc = -ENOMEM;
6975                 goto init_err_release;
6976         }
6977
6978         pci_enable_pcie_error_reporting(pdev);
6979
6980         INIT_WORK(&bp->sp_task, bnxt_sp_task);
6981
6982         spin_lock_init(&bp->ntp_fltr_lock);
6983
6984         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6985         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6986
6987         /* tick values in micro seconds */
6988         bp->rx_coal_ticks = 12;
6989         bp->rx_coal_bufs = 30;
6990         bp->rx_coal_ticks_irq = 1;
6991         bp->rx_coal_bufs_irq = 2;
6992
6993         bp->tx_coal_ticks = 25;
6994         bp->tx_coal_bufs = 30;
6995         bp->tx_coal_ticks_irq = 2;
6996         bp->tx_coal_bufs_irq = 2;
6997
6998         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6999
7000         init_timer(&bp->timer);
7001         bp->timer.data = (unsigned long)bp;
7002         bp->timer.function = bnxt_timer;
7003         bp->current_interval = BNXT_TIMER_INTERVAL;
7004
7005         clear_bit(BNXT_STATE_OPEN, &bp->state);
7006         return 0;
7007
7008 init_err_release:
7009         bnxt_unmap_bars(bp, pdev);
7010         pci_release_regions(pdev);
7011
7012 init_err_disable:
7013         pci_disable_device(pdev);
7014
7015 init_err:
7016         return rc;
7017 }
7018
7019 /* rtnl_lock held */
7020 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7021 {
7022         struct sockaddr *addr = p;
7023         struct bnxt *bp = netdev_priv(dev);
7024         int rc = 0;
7025
7026         if (!is_valid_ether_addr(addr->sa_data))
7027                 return -EADDRNOTAVAIL;
7028
7029         rc = bnxt_approve_mac(bp, addr->sa_data);
7030         if (rc)
7031                 return rc;
7032
7033         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7034                 return 0;
7035
7036         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7037         if (netif_running(dev)) {
7038                 bnxt_close_nic(bp, false, false);
7039                 rc = bnxt_open_nic(bp, false, false);
7040         }
7041
7042         return rc;
7043 }
7044
7045 /* rtnl_lock held */
7046 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7047 {
7048         struct bnxt *bp = netdev_priv(dev);
7049
7050         if (netif_running(dev))
7051                 bnxt_close_nic(bp, false, false);
7052
7053         dev->mtu = new_mtu;
7054         bnxt_set_ring_params(bp);
7055
7056         if (netif_running(dev))
7057                 return bnxt_open_nic(bp, false, false);
7058
7059         return 0;
7060 }
7061
7062 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
7063 {
7064         struct bnxt *bp = netdev_priv(dev);
7065         bool sh = false;
7066         int rc;
7067
7068         if (tc > bp->max_tc) {
7069                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
7070                            tc, bp->max_tc);
7071                 return -EINVAL;
7072         }
7073
7074         if (netdev_get_num_tc(dev) == tc)
7075                 return 0;
7076
7077         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7078                 sh = true;
7079
7080         rc = bnxt_reserve_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7081                                 tc, bp->tx_nr_rings_xdp);
7082         if (rc)
7083                 return rc;
7084
7085         /* Needs to close the device and do hw resource re-allocations */
7086         if (netif_running(bp->dev))
7087                 bnxt_close_nic(bp, true, false);
7088
7089         if (tc) {
7090                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7091                 netdev_set_num_tc(dev, tc);
7092         } else {
7093                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7094                 netdev_reset_tc(dev);
7095         }
7096         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7097                                bp->tx_nr_rings + bp->rx_nr_rings;
7098         bp->num_stat_ctxs = bp->cp_nr_rings;
7099
7100         if (netif_running(bp->dev))
7101                 return bnxt_open_nic(bp, true, false);
7102
7103         return 0;
7104 }
7105
7106 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
7107                          struct tc_to_netdev *ntc)
7108 {
7109         if (ntc->type != TC_SETUP_MQPRIO)
7110                 return -EINVAL;
7111
7112         ntc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
7113
7114         return bnxt_setup_mq_tc(dev, ntc->mqprio->num_tc);
7115 }
7116
7117 #ifdef CONFIG_RFS_ACCEL
7118 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7119                             struct bnxt_ntuple_filter *f2)
7120 {
7121         struct flow_keys *keys1 = &f1->fkeys;
7122         struct flow_keys *keys2 = &f2->fkeys;
7123
7124         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7125             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7126             keys1->ports.ports == keys2->ports.ports &&
7127             keys1->basic.ip_proto == keys2->basic.ip_proto &&
7128             keys1->basic.n_proto == keys2->basic.n_proto &&
7129             keys1->control.flags == keys2->control.flags &&
7130             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7131             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
7132                 return true;
7133
7134         return false;
7135 }
7136
7137 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7138                               u16 rxq_index, u32 flow_id)
7139 {
7140         struct bnxt *bp = netdev_priv(dev);
7141         struct bnxt_ntuple_filter *fltr, *new_fltr;
7142         struct flow_keys *fkeys;
7143         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
7144         int rc = 0, idx, bit_id, l2_idx = 0;
7145         struct hlist_head *head;
7146
7147         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7148                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7149                 int off = 0, j;
7150
7151                 netif_addr_lock_bh(dev);
7152                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7153                         if (ether_addr_equal(eth->h_dest,
7154                                              vnic->uc_list + off)) {
7155                                 l2_idx = j + 1;
7156                                 break;
7157                         }
7158                 }
7159                 netif_addr_unlock_bh(dev);
7160                 if (!l2_idx)
7161                         return -EINVAL;
7162         }
7163         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7164         if (!new_fltr)
7165                 return -ENOMEM;
7166
7167         fkeys = &new_fltr->fkeys;
7168         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7169                 rc = -EPROTONOSUPPORT;
7170                 goto err_free;
7171         }
7172
7173         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7174              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
7175             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7176              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7177                 rc = -EPROTONOSUPPORT;
7178                 goto err_free;
7179         }
7180         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7181             bp->hwrm_spec_code < 0x10601) {
7182                 rc = -EPROTONOSUPPORT;
7183                 goto err_free;
7184         }
7185         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7186             bp->hwrm_spec_code < 0x10601) {
7187                 rc = -EPROTONOSUPPORT;
7188                 goto err_free;
7189         }
7190
7191         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
7192         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7193
7194         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7195         head = &bp->ntp_fltr_hash_tbl[idx];
7196         rcu_read_lock();
7197         hlist_for_each_entry_rcu(fltr, head, hash) {
7198                 if (bnxt_fltr_match(fltr, new_fltr)) {
7199                         rcu_read_unlock();
7200                         rc = 0;
7201                         goto err_free;
7202                 }
7203         }
7204         rcu_read_unlock();
7205
7206         spin_lock_bh(&bp->ntp_fltr_lock);
7207         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7208                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
7209         if (bit_id < 0) {
7210                 spin_unlock_bh(&bp->ntp_fltr_lock);
7211                 rc = -ENOMEM;
7212                 goto err_free;
7213         }
7214
7215         new_fltr->sw_id = (u16)bit_id;
7216         new_fltr->flow_id = flow_id;
7217         new_fltr->l2_fltr_idx = l2_idx;
7218         new_fltr->rxq = rxq_index;
7219         hlist_add_head_rcu(&new_fltr->hash, head);
7220         bp->ntp_fltr_count++;
7221         spin_unlock_bh(&bp->ntp_fltr_lock);
7222
7223         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
7224         schedule_work(&bp->sp_task);
7225
7226         return new_fltr->sw_id;
7227
7228 err_free:
7229         kfree(new_fltr);
7230         return rc;
7231 }
7232
7233 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7234 {
7235         int i;
7236
7237         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7238                 struct hlist_head *head;
7239                 struct hlist_node *tmp;
7240                 struct bnxt_ntuple_filter *fltr;
7241                 int rc;
7242
7243                 head = &bp->ntp_fltr_hash_tbl[i];
7244                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7245                         bool del = false;
7246
7247                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7248                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7249                                                         fltr->flow_id,
7250                                                         fltr->sw_id)) {
7251                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
7252                                                                          fltr);
7253                                         del = true;
7254                                 }
7255                         } else {
7256                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7257                                                                        fltr);
7258                                 if (rc)
7259                                         del = true;
7260                                 else
7261                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
7262                         }
7263
7264                         if (del) {
7265                                 spin_lock_bh(&bp->ntp_fltr_lock);
7266                                 hlist_del_rcu(&fltr->hash);
7267                                 bp->ntp_fltr_count--;
7268                                 spin_unlock_bh(&bp->ntp_fltr_lock);
7269                                 synchronize_rcu();
7270                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7271                                 kfree(fltr);
7272                         }
7273                 }
7274         }
7275         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7276                 netdev_info(bp->dev, "Receive PF driver unload event!");
7277 }
7278
7279 #else
7280
7281 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7282 {
7283 }
7284
7285 #endif /* CONFIG_RFS_ACCEL */
7286
7287 static void bnxt_udp_tunnel_add(struct net_device *dev,
7288                                 struct udp_tunnel_info *ti)
7289 {
7290         struct bnxt *bp = netdev_priv(dev);
7291
7292         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7293                 return;
7294
7295         if (!netif_running(dev))
7296                 return;
7297
7298         switch (ti->type) {
7299         case UDP_TUNNEL_TYPE_VXLAN:
7300                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7301                         return;
7302
7303                 bp->vxlan_port_cnt++;
7304                 if (bp->vxlan_port_cnt == 1) {
7305                         bp->vxlan_port = ti->port;
7306                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7307                         schedule_work(&bp->sp_task);
7308                 }
7309                 break;
7310         case UDP_TUNNEL_TYPE_GENEVE:
7311                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7312                         return;
7313
7314                 bp->nge_port_cnt++;
7315                 if (bp->nge_port_cnt == 1) {
7316                         bp->nge_port = ti->port;
7317                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7318                 }
7319                 break;
7320         default:
7321                 return;
7322         }
7323
7324         schedule_work(&bp->sp_task);
7325 }
7326
7327 static void bnxt_udp_tunnel_del(struct net_device *dev,
7328                                 struct udp_tunnel_info *ti)
7329 {
7330         struct bnxt *bp = netdev_priv(dev);
7331
7332         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7333                 return;
7334
7335         if (!netif_running(dev))
7336                 return;
7337
7338         switch (ti->type) {
7339         case UDP_TUNNEL_TYPE_VXLAN:
7340                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7341                         return;
7342                 bp->vxlan_port_cnt--;
7343
7344                 if (bp->vxlan_port_cnt != 0)
7345                         return;
7346
7347                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7348                 break;
7349         case UDP_TUNNEL_TYPE_GENEVE:
7350                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7351                         return;
7352                 bp->nge_port_cnt--;
7353
7354                 if (bp->nge_port_cnt != 0)
7355                         return;
7356
7357                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7358                 break;
7359         default:
7360                 return;
7361         }
7362
7363         schedule_work(&bp->sp_task);
7364 }
7365
7366 static const struct net_device_ops bnxt_netdev_ops = {
7367         .ndo_open               = bnxt_open,
7368         .ndo_start_xmit         = bnxt_start_xmit,
7369         .ndo_stop               = bnxt_close,
7370         .ndo_get_stats64        = bnxt_get_stats64,
7371         .ndo_set_rx_mode        = bnxt_set_rx_mode,
7372         .ndo_do_ioctl           = bnxt_ioctl,
7373         .ndo_validate_addr      = eth_validate_addr,
7374         .ndo_set_mac_address    = bnxt_change_mac_addr,
7375         .ndo_change_mtu         = bnxt_change_mtu,
7376         .ndo_fix_features       = bnxt_fix_features,
7377         .ndo_set_features       = bnxt_set_features,
7378         .ndo_tx_timeout         = bnxt_tx_timeout,
7379 #ifdef CONFIG_BNXT_SRIOV
7380         .ndo_get_vf_config      = bnxt_get_vf_config,
7381         .ndo_set_vf_mac         = bnxt_set_vf_mac,
7382         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
7383         .ndo_set_vf_rate        = bnxt_set_vf_bw,
7384         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
7385         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
7386 #endif
7387 #ifdef CONFIG_NET_POLL_CONTROLLER
7388         .ndo_poll_controller    = bnxt_poll_controller,
7389 #endif
7390         .ndo_setup_tc           = bnxt_setup_tc,
7391 #ifdef CONFIG_RFS_ACCEL
7392         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
7393 #endif
7394         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
7395         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
7396         .ndo_xdp                = bnxt_xdp,
7397 };
7398
7399 static void bnxt_remove_one(struct pci_dev *pdev)
7400 {
7401         struct net_device *dev = pci_get_drvdata(pdev);
7402         struct bnxt *bp = netdev_priv(dev);
7403
7404         if (BNXT_PF(bp))
7405                 bnxt_sriov_disable(bp);
7406
7407         pci_disable_pcie_error_reporting(pdev);
7408         unregister_netdev(dev);
7409         cancel_work_sync(&bp->sp_task);
7410         bp->sp_event = 0;
7411
7412         bnxt_clear_int_mode(bp);
7413         bnxt_hwrm_func_drv_unrgtr(bp);
7414         bnxt_free_hwrm_resources(bp);
7415         bnxt_free_hwrm_short_cmd_req(bp);
7416         bnxt_ethtool_free(bp);
7417         bnxt_dcb_free(bp);
7418         kfree(bp->edev);
7419         bp->edev = NULL;
7420         if (bp->xdp_prog)
7421                 bpf_prog_put(bp->xdp_prog);
7422         bnxt_cleanup_pci(bp);
7423         free_netdev(dev);
7424 }
7425
7426 static int bnxt_probe_phy(struct bnxt *bp)
7427 {
7428         int rc = 0;
7429         struct bnxt_link_info *link_info = &bp->link_info;
7430
7431         rc = bnxt_hwrm_phy_qcaps(bp);
7432         if (rc) {
7433                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7434                            rc);
7435                 return rc;
7436         }
7437
7438         rc = bnxt_update_link(bp, false);
7439         if (rc) {
7440                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7441                            rc);
7442                 return rc;
7443         }
7444
7445         /* Older firmware does not have supported_auto_speeds, so assume
7446          * that all supported speeds can be autonegotiated.
7447          */
7448         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7449                 link_info->support_auto_speeds = link_info->support_speeds;
7450
7451         /*initialize the ethool setting copy with NVM settings */
7452         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
7453                 link_info->autoneg = BNXT_AUTONEG_SPEED;
7454                 if (bp->hwrm_spec_code >= 0x10201) {
7455                         if (link_info->auto_pause_setting &
7456                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7457                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7458                 } else {
7459                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7460                 }
7461                 link_info->advertising = link_info->auto_link_speeds;
7462         } else {
7463                 link_info->req_link_speed = link_info->force_link_speed;
7464                 link_info->req_duplex = link_info->duplex_setting;
7465         }
7466         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7467                 link_info->req_flow_ctrl =
7468                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7469         else
7470                 link_info->req_flow_ctrl = link_info->force_pause_setting;
7471         return rc;
7472 }
7473
7474 static int bnxt_get_max_irq(struct pci_dev *pdev)
7475 {
7476         u16 ctrl;
7477
7478         if (!pdev->msix_cap)
7479                 return 1;
7480
7481         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7482         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7483 }
7484
7485 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7486                                 int *max_cp)
7487 {
7488         int max_ring_grps = 0;
7489
7490 #ifdef CONFIG_BNXT_SRIOV
7491         if (!BNXT_PF(bp)) {
7492                 *max_tx = bp->vf.max_tx_rings;
7493                 *max_rx = bp->vf.max_rx_rings;
7494                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7495                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
7496                 max_ring_grps = bp->vf.max_hw_ring_grps;
7497         } else
7498 #endif
7499         {
7500                 *max_tx = bp->pf.max_tx_rings;
7501                 *max_rx = bp->pf.max_rx_rings;
7502                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7503                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7504                 max_ring_grps = bp->pf.max_hw_ring_grps;
7505         }
7506         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7507                 *max_cp -= 1;
7508                 *max_rx -= 2;
7509         }
7510         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7511                 *max_rx >>= 1;
7512         *max_rx = min_t(int, *max_rx, max_ring_grps);
7513 }
7514
7515 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7516 {
7517         int rx, tx, cp;
7518
7519         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7520         if (!rx || !tx || !cp)
7521                 return -ENOMEM;
7522
7523         *max_rx = rx;
7524         *max_tx = tx;
7525         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7526 }
7527
7528 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7529                                bool shared)
7530 {
7531         int rc;
7532
7533         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7534         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7535                 /* Not enough rings, try disabling agg rings. */
7536                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7537                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7538                 if (rc)
7539                         return rc;
7540                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7541                 bp->dev->hw_features &= ~NETIF_F_LRO;
7542                 bp->dev->features &= ~NETIF_F_LRO;
7543                 bnxt_set_ring_params(bp);
7544         }
7545
7546         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7547                 int max_cp, max_stat, max_irq;
7548
7549                 /* Reserve minimum resources for RoCE */
7550                 max_cp = bnxt_get_max_func_cp_rings(bp);
7551                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7552                 max_irq = bnxt_get_max_func_irqs(bp);
7553                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7554                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7555                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7556                         return 0;
7557
7558                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7559                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7560                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7561                 max_cp = min_t(int, max_cp, max_irq);
7562                 max_cp = min_t(int, max_cp, max_stat);
7563                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7564                 if (rc)
7565                         rc = 0;
7566         }
7567         return rc;
7568 }
7569
7570 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
7571 {
7572         int dflt_rings, max_rx_rings, max_tx_rings, rc;
7573
7574         if (sh)
7575                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7576         dflt_rings = netif_get_num_default_rss_queues();
7577         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
7578         if (rc)
7579                 return rc;
7580         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7581         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
7582
7583         rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7584         if (rc)
7585                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7586
7587         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7588         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7589                                bp->tx_nr_rings + bp->rx_nr_rings;
7590         bp->num_stat_ctxs = bp->cp_nr_rings;
7591         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7592                 bp->rx_nr_rings++;
7593                 bp->cp_nr_rings++;
7594         }
7595         return rc;
7596 }
7597
7598 void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7599 {
7600         ASSERT_RTNL();
7601         bnxt_hwrm_func_qcaps(bp);
7602         bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7603 }
7604
7605 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
7606 {
7607         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
7608         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
7609
7610         if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
7611             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
7612                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
7613         else
7614                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
7615                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
7616                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
7617                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
7618                             "Unknown", width);
7619 }
7620
7621 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7622 {
7623         static int version_printed;
7624         struct net_device *dev;
7625         struct bnxt *bp;
7626         int rc, max_irqs;
7627
7628         if (pci_is_bridge(pdev))
7629                 return -ENODEV;
7630
7631         if (version_printed++ == 0)
7632                 pr_info("%s", version);
7633
7634         max_irqs = bnxt_get_max_irq(pdev);
7635         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
7636         if (!dev)
7637                 return -ENOMEM;
7638
7639         bp = netdev_priv(dev);
7640
7641         if (bnxt_vf_pciid(ent->driver_data))
7642                 bp->flags |= BNXT_FLAG_VF;
7643
7644         if (pdev->msix_cap)
7645                 bp->flags |= BNXT_FLAG_MSIX_CAP;
7646
7647         rc = bnxt_init_board(pdev, dev);
7648         if (rc < 0)
7649                 goto init_err_free;
7650
7651         dev->netdev_ops = &bnxt_netdev_ops;
7652         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
7653         dev->ethtool_ops = &bnxt_ethtool_ops;
7654         pci_set_drvdata(pdev, dev);
7655
7656         rc = bnxt_alloc_hwrm_resources(bp);
7657         if (rc)
7658                 goto init_err_pci_clean;
7659
7660         mutex_init(&bp->hwrm_cmd_lock);
7661         rc = bnxt_hwrm_ver_get(bp);
7662         if (rc)
7663                 goto init_err_pci_clean;
7664
7665         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
7666                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
7667                 if (rc)
7668                         goto init_err_pci_clean;
7669         }
7670
7671         rc = bnxt_hwrm_func_reset(bp);
7672         if (rc)
7673                 goto init_err_pci_clean;
7674
7675         bnxt_hwrm_fw_set_time(bp);
7676
7677         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7678                            NETIF_F_TSO | NETIF_F_TSO6 |
7679                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7680                            NETIF_F_GSO_IPXIP4 |
7681                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7682                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
7683                            NETIF_F_RXCSUM | NETIF_F_GRO;
7684
7685         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
7686                 dev->hw_features |= NETIF_F_LRO;
7687
7688         dev->hw_enc_features =
7689                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7690                         NETIF_F_TSO | NETIF_F_TSO6 |
7691                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7692                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7693                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
7694         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
7695                                     NETIF_F_GSO_GRE_CSUM;
7696         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
7697         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7698                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
7699         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
7700         dev->priv_flags |= IFF_UNICAST_FLT;
7701
7702         /* MTU range: 60 - 9500 */
7703         dev->min_mtu = ETH_ZLEN;
7704         dev->max_mtu = BNXT_MAX_MTU;
7705
7706 #ifdef CONFIG_BNXT_SRIOV
7707         init_waitqueue_head(&bp->sriov_cfg_wait);
7708 #endif
7709         bp->gro_func = bnxt_gro_func_5730x;
7710         if (BNXT_CHIP_P4_PLUS(bp))
7711                 bp->gro_func = bnxt_gro_func_5731x;
7712         else
7713                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
7714
7715         rc = bnxt_hwrm_func_drv_rgtr(bp);
7716         if (rc)
7717                 goto init_err_pci_clean;
7718
7719         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
7720         if (rc)
7721                 goto init_err_pci_clean;
7722
7723         bp->ulp_probe = bnxt_ulp_probe;
7724
7725         /* Get the MAX capabilities for this function */
7726         rc = bnxt_hwrm_func_qcaps(bp);
7727         if (rc) {
7728                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
7729                            rc);
7730                 rc = -1;
7731                 goto init_err_pci_clean;
7732         }
7733
7734         rc = bnxt_hwrm_queue_qportcfg(bp);
7735         if (rc) {
7736                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
7737                            rc);
7738                 rc = -1;
7739                 goto init_err_pci_clean;
7740         }
7741
7742         bnxt_hwrm_func_qcfg(bp);
7743         bnxt_hwrm_port_led_qcaps(bp);
7744         bnxt_ethtool_init(bp);
7745         bnxt_dcb_init(bp);
7746
7747         bnxt_set_rx_skb_mode(bp, false);
7748         bnxt_set_tpa_flags(bp);
7749         bnxt_set_ring_params(bp);
7750         bnxt_set_max_func_irqs(bp, max_irqs);
7751         rc = bnxt_set_dflt_rings(bp, true);
7752         if (rc) {
7753                 netdev_err(bp->dev, "Not enough rings available.\n");
7754                 rc = -ENOMEM;
7755                 goto init_err_pci_clean;
7756         }
7757
7758         /* Default RSS hash cfg. */
7759         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
7760                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
7761                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
7762                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
7763         if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
7764                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
7765                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
7766                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
7767         }
7768
7769         bnxt_hwrm_vnic_qcaps(bp);
7770         if (bnxt_rfs_supported(bp)) {
7771                 dev->hw_features |= NETIF_F_NTUPLE;
7772                 if (bnxt_rfs_capable(bp)) {
7773                         bp->flags |= BNXT_FLAG_RFS;
7774                         dev->features |= NETIF_F_NTUPLE;
7775                 }
7776         }
7777
7778         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
7779                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
7780
7781         rc = bnxt_probe_phy(bp);
7782         if (rc)
7783                 goto init_err_pci_clean;
7784
7785         rc = bnxt_init_int_mode(bp);
7786         if (rc)
7787                 goto init_err_pci_clean;
7788
7789         bnxt_get_wol_settings(bp);
7790         if (bp->flags & BNXT_FLAG_WOL_CAP)
7791                 device_set_wakeup_enable(&pdev->dev, bp->wol);
7792         else
7793                 device_set_wakeup_capable(&pdev->dev, false);
7794
7795         rc = register_netdev(dev);
7796         if (rc)
7797                 goto init_err_clr_int;
7798
7799         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
7800                     board_info[ent->driver_data].name,
7801                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
7802
7803         bnxt_parse_log_pcie_link(bp);
7804
7805         return 0;
7806
7807 init_err_clr_int:
7808         bnxt_clear_int_mode(bp);
7809
7810 init_err_pci_clean:
7811         bnxt_cleanup_pci(bp);
7812
7813 init_err_free:
7814         free_netdev(dev);
7815         return rc;
7816 }
7817
7818 static void bnxt_shutdown(struct pci_dev *pdev)
7819 {
7820         struct net_device *dev = pci_get_drvdata(pdev);
7821         struct bnxt *bp;
7822
7823         if (!dev)
7824                 return;
7825
7826         rtnl_lock();
7827         bp = netdev_priv(dev);
7828         if (!bp)
7829                 goto shutdown_exit;
7830
7831         if (netif_running(dev))
7832                 dev_close(dev);
7833
7834         if (system_state == SYSTEM_POWER_OFF) {
7835                 bnxt_ulp_shutdown(bp);
7836                 bnxt_clear_int_mode(bp);
7837                 pci_wake_from_d3(pdev, bp->wol);
7838                 pci_set_power_state(pdev, PCI_D3hot);
7839         }
7840
7841 shutdown_exit:
7842         rtnl_unlock();
7843 }
7844
7845 #ifdef CONFIG_PM_SLEEP
7846 static int bnxt_suspend(struct device *device)
7847 {
7848         struct pci_dev *pdev = to_pci_dev(device);
7849         struct net_device *dev = pci_get_drvdata(pdev);
7850         struct bnxt *bp = netdev_priv(dev);
7851         int rc = 0;
7852
7853         rtnl_lock();
7854         if (netif_running(dev)) {
7855                 netif_device_detach(dev);
7856                 rc = bnxt_close(dev);
7857         }
7858         bnxt_hwrm_func_drv_unrgtr(bp);
7859         rtnl_unlock();
7860         return rc;
7861 }
7862
7863 static int bnxt_resume(struct device *device)
7864 {
7865         struct pci_dev *pdev = to_pci_dev(device);
7866         struct net_device *dev = pci_get_drvdata(pdev);
7867         struct bnxt *bp = netdev_priv(dev);
7868         int rc = 0;
7869
7870         rtnl_lock();
7871         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
7872                 rc = -ENODEV;
7873                 goto resume_exit;
7874         }
7875         rc = bnxt_hwrm_func_reset(bp);
7876         if (rc) {
7877                 rc = -EBUSY;
7878                 goto resume_exit;
7879         }
7880         bnxt_get_wol_settings(bp);
7881         if (netif_running(dev)) {
7882                 rc = bnxt_open(dev);
7883                 if (!rc)
7884                         netif_device_attach(dev);
7885         }
7886
7887 resume_exit:
7888         rtnl_unlock();
7889         return rc;
7890 }
7891
7892 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
7893 #define BNXT_PM_OPS (&bnxt_pm_ops)
7894
7895 #else
7896
7897 #define BNXT_PM_OPS NULL
7898
7899 #endif /* CONFIG_PM_SLEEP */
7900
7901 /**
7902  * bnxt_io_error_detected - called when PCI error is detected
7903  * @pdev: Pointer to PCI device
7904  * @state: The current pci connection state
7905  *
7906  * This function is called after a PCI bus error affecting
7907  * this device has been detected.
7908  */
7909 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
7910                                                pci_channel_state_t state)
7911 {
7912         struct net_device *netdev = pci_get_drvdata(pdev);
7913         struct bnxt *bp = netdev_priv(netdev);
7914
7915         netdev_info(netdev, "PCI I/O error detected\n");
7916
7917         rtnl_lock();
7918         netif_device_detach(netdev);
7919
7920         bnxt_ulp_stop(bp);
7921
7922         if (state == pci_channel_io_perm_failure) {
7923                 rtnl_unlock();
7924                 return PCI_ERS_RESULT_DISCONNECT;
7925         }
7926
7927         if (netif_running(netdev))
7928                 bnxt_close(netdev);
7929
7930         pci_disable_device(pdev);
7931         rtnl_unlock();
7932
7933         /* Request a slot slot reset. */
7934         return PCI_ERS_RESULT_NEED_RESET;
7935 }
7936
7937 /**
7938  * bnxt_io_slot_reset - called after the pci bus has been reset.
7939  * @pdev: Pointer to PCI device
7940  *
7941  * Restart the card from scratch, as if from a cold-boot.
7942  * At this point, the card has exprienced a hard reset,
7943  * followed by fixups by BIOS, and has its config space
7944  * set up identically to what it was at cold boot.
7945  */
7946 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
7947 {
7948         struct net_device *netdev = pci_get_drvdata(pdev);
7949         struct bnxt *bp = netdev_priv(netdev);
7950         int err = 0;
7951         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7952
7953         netdev_info(bp->dev, "PCI Slot Reset\n");
7954
7955         rtnl_lock();
7956
7957         if (pci_enable_device(pdev)) {
7958                 dev_err(&pdev->dev,
7959                         "Cannot re-enable PCI device after reset.\n");
7960         } else {
7961                 pci_set_master(pdev);
7962
7963                 err = bnxt_hwrm_func_reset(bp);
7964                 if (!err && netif_running(netdev))
7965                         err = bnxt_open(netdev);
7966
7967                 if (!err) {
7968                         result = PCI_ERS_RESULT_RECOVERED;
7969                         bnxt_ulp_start(bp);
7970                 }
7971         }
7972
7973         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7974                 dev_close(netdev);
7975
7976         rtnl_unlock();
7977
7978         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7979         if (err) {
7980                 dev_err(&pdev->dev,
7981                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7982                          err); /* non-fatal, continue */
7983         }
7984
7985         return PCI_ERS_RESULT_RECOVERED;
7986 }
7987
7988 /**
7989  * bnxt_io_resume - called when traffic can start flowing again.
7990  * @pdev: Pointer to PCI device
7991  *
7992  * This callback is called when the error recovery driver tells
7993  * us that its OK to resume normal operation.
7994  */
7995 static void bnxt_io_resume(struct pci_dev *pdev)
7996 {
7997         struct net_device *netdev = pci_get_drvdata(pdev);
7998
7999         rtnl_lock();
8000
8001         netif_device_attach(netdev);
8002
8003         rtnl_unlock();
8004 }
8005
8006 static const struct pci_error_handlers bnxt_err_handler = {
8007         .error_detected = bnxt_io_error_detected,
8008         .slot_reset     = bnxt_io_slot_reset,
8009         .resume         = bnxt_io_resume
8010 };
8011
8012 static struct pci_driver bnxt_pci_driver = {
8013         .name           = DRV_MODULE_NAME,
8014         .id_table       = bnxt_pci_tbl,
8015         .probe          = bnxt_init_one,
8016         .remove         = bnxt_remove_one,
8017         .shutdown       = bnxt_shutdown,
8018         .driver.pm      = BNXT_PM_OPS,
8019         .err_handler    = &bnxt_err_handler,
8020 #if defined(CONFIG_BNXT_SRIOV)
8021         .sriov_configure = bnxt_sriov_configure,
8022 #endif
8023 };
8024
8025 module_pci_driver(bnxt_pci_driver);