drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/if.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/if_bridge.h>
  37 #include <linux/rtc.h>
  38 #include <linux/bpf.h>
  39 #include <net/ip.h>
  40 #include <net/tcp.h>
  41 #include <net/udp.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <net/udp_tunnel.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/prefetch.h>
  47 #include <linux/cache.h>
  48 #include <linux/log2.h>
  49 #include <linux/aer.h>
  50 #include <linux/bitmap.h>
  51 #include <linux/cpu_rmap.h>
  52 #include <linux/cpumask.h>
  53 #include <net/pkt_cls.h>
  54
  55 #include "bnxt_hsi.h"
  56 #include "bnxt.h"
  57 #include "bnxt_ulp.h"
  58 #include "bnxt_sriov.h"
  59 #include "bnxt_ethtool.h"
  60 #include "bnxt_dcb.h"
  61 #include "bnxt_xdp.h"
  62 #include "bnxt_vfr.h"
  63 #include "bnxt_tc.h"
  64 #include "bnxt_devlink.h"
  65 #include "bnxt_debugfs.h"
  66
  67 #define BNXT_TX_TIMEOUT         (5 * HZ)
  68
  69 static const char version[] =
  70         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  71
  72 MODULE_LICENSE("GPL");
  73 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  74 MODULE_VERSION(DRV_MODULE_VERSION);
  75
  76 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  77 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  78 #define BNXT_RX_COPY_THRESH 256
  79
  80 #define BNXT_TX_PUSH_THRESH 164
  81
  82 enum board_idx {
  83         BCM57301,
  84         BCM57302,
  85         BCM57304,
  86         BCM57417_NPAR,
  87         BCM58700,
  88         BCM57311,
  89         BCM57312,
  90         BCM57402,
  91         BCM57404,
  92         BCM57406,
  93         BCM57402_NPAR,
  94         BCM57407,
  95         BCM57412,
  96         BCM57414,
  97         BCM57416,
  98         BCM57417,
  99         BCM57412_NPAR,
 100         BCM57314,
 101         BCM57417_SFP,
 102         BCM57416_SFP,
 103         BCM57404_NPAR,
 104         BCM57406_NPAR,
 105         BCM57407_SFP,
 106         BCM57407_NPAR,
 107         BCM57414_NPAR,
 108         BCM57416_NPAR,
 109         BCM57452,
 110         BCM57454,
 111         BCM5745x_NPAR,
 112         BCM58802,
 113         BCM58804,
 114         BCM58808,
 115         NETXTREME_E_VF,
 116         NETXTREME_C_VF,
 117         NETXTREME_S_VF,
 118 };
 119
 120 /* indexed by enum above */
 121 static const struct {
 122         char *name;
 123 } board_info[] = {
 124         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 125         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 126         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 127         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 128         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 129         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 130         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 131         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 132         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 133         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 134         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 135         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 136         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 137         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 138         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 139         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 140         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 141         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 142         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 143         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 144         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 145         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 146         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 147         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 148         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 149         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 150         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 151         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 152         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 153         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 154         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 155         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 156         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 157         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 158         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 159 };
 160
 161 static const struct pci_device_id bnxt_pci_tbl[] = {
 162         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 163         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 164         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 165         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 166         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 167         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 168         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 169         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 170         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 171         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 172         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 173         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 174         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 175         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 176         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 177         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 178         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 179         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 180         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 181         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 182         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 183         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 184         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 185         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 186         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 187         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 188         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 189         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 190         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 191         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 192         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 193         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 194         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 195         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 196         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 197         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 198         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 199 #ifdef CONFIG_BNXT_SRIOV
 200         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 201         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 202         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 203         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 204         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 205         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 206         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 207         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 208         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 209 #endif
 210         { 0 }
 211 };
 212
 213 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 214
 215 static const u16 bnxt_vf_req_snif[] = {
 216         HWRM_FUNC_CFG,
 217         HWRM_FUNC_VF_CFG,
 218         HWRM_PORT_PHY_QCFG,
 219         HWRM_CFA_L2_FILTER_ALLOC,
 220 };
 221
 222 static const u16 bnxt_async_events_arr[] = {
 223         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 224         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 225         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 226         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 227         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 228 };
 229
 230 static struct workqueue_struct *bnxt_pf_wq;
 231
 232 static bool bnxt_vf_pciid(enum board_idx idx)
 233 {
 234         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 235                 idx == NETXTREME_S_VF);
 236 }
 237
 238 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 239 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 240 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 241
 242 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 243                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 244
 245 #define BNXT_CP_DB(db, raw_cons)                                        \
 246                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 247
 248 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 249                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 250
 251 const u16 bnxt_lhint_arr[] = {
 252         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 253         TX_BD_FLAGS_LHINT_512_TO_1023,
 254         TX_BD_FLAGS_LHINT_1024_TO_2047,
 255         TX_BD_FLAGS_LHINT_1024_TO_2047,
 256         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 257         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 258         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 259         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 260         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 261         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 262         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 263         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 264         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 265         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 266         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 267         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 268         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 269         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 270         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 271 };
 272
 273 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 274 {
 275         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 276
 277         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 278                 return 0;
 279
 280         return md_dst->u.port_info.port_id;
 281 }
 282
 283 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 284 {
 285         struct bnxt *bp = netdev_priv(dev);
 286         struct tx_bd *txbd;
 287         struct tx_bd_ext *txbd1;
 288         struct netdev_queue *txq;
 289         int i;
 290         dma_addr_t mapping;
 291         unsigned int length, pad = 0;
 292         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 293         u16 prod, last_frag;
 294         struct pci_dev *pdev = bp->pdev;
 295         struct bnxt_tx_ring_info *txr;
 296         struct bnxt_sw_tx_bd *tx_buf;
 297
 298         i = skb_get_queue_mapping(skb);
 299         if (unlikely(i >= bp->tx_nr_rings)) {
 300                 dev_kfree_skb_any(skb);
 301                 return NETDEV_TX_OK;
 302         }
 303
 304         txq = netdev_get_tx_queue(dev, i);
 305         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 306         prod = txr->tx_prod;
 307
 308         free_size = bnxt_tx_avail(bp, txr);
 309         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 310                 netif_tx_stop_queue(txq);
 311                 return NETDEV_TX_BUSY;
 312         }
 313
 314         length = skb->len;
 315         len = skb_headlen(skb);
 316         last_frag = skb_shinfo(skb)->nr_frags;
 317
 318         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 319
 320         txbd->tx_bd_opaque = prod;
 321
 322         tx_buf = &txr->tx_buf_ring[prod];
 323         tx_buf->skb = skb;
 324         tx_buf->nr_frags = last_frag;
 325
 326         vlan_tag_flags = 0;
 327         cfa_action = bnxt_xmit_get_cfa_action(skb);
 328         if (skb_vlan_tag_present(skb)) {
 329                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 330                                  skb_vlan_tag_get(skb);
 331                 /* Currently supports 8021Q, 8021AD vlan offloads
 332                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 333                  */
 334                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 335                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 336         }
 337
 338         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 339                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 340                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 341                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 342                 void *pdata = tx_push_buf->data;
 343                 u64 *end;
 344                 int j, push_len;
 345
 346                 /* Set COAL_NOW to be ready quickly for the next push */
 347                 tx_push->tx_bd_len_flags_type =
 348                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 349                                         TX_BD_TYPE_LONG_TX_BD |
 350                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 351                                         TX_BD_FLAGS_COAL_NOW |
 352                                         TX_BD_FLAGS_PACKET_END |
 353                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 354
 355                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 356                         tx_push1->tx_bd_hsize_lflags =
 357                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 358                 else
 359                         tx_push1->tx_bd_hsize_lflags = 0;
 360
 361                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 362                 tx_push1->tx_bd_cfa_action =
 363                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 364
 365                 end = pdata + length;
 366                 end = PTR_ALIGN(end, 8) - 1;
 367                 *end = 0;
 368
 369                 skb_copy_from_linear_data(skb, pdata, len);
 370                 pdata += len;
 371                 for (j = 0; j < last_frag; j++) {
 372                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 373                         void *fptr;
 374
 375                         fptr = skb_frag_address_safe(frag);
 376                         if (!fptr)
 377                                 goto normal_tx;
 378
 379                         memcpy(pdata, fptr, skb_frag_size(frag));
 380                         pdata += skb_frag_size(frag);
 381                 }
 382
 383                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 384                 txbd->tx_bd_haddr = txr->data_mapping;
 385                 prod = NEXT_TX(prod);
 386                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 387                 memcpy(txbd, tx_push1, sizeof(*txbd));
 388                 prod = NEXT_TX(prod);
 389                 tx_push->doorbell =
 390                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 391                 txr->tx_prod = prod;
 392
 393                 tx_buf->is_push = 1;
 394                 netdev_tx_sent_queue(txq, skb->len);
 395                 wmb();  /* Sync is_push and byte queue before pushing data */
 396
 397                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 398                 if (push_len > 16) {
 399                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 400                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 401                                          (push_len - 16) << 1);
 402                 } else {
 403                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 404                                          push_len);
 405                 }
 406
 407                 goto tx_done;
 408         }
 409
 410 normal_tx:
 411         if (length < BNXT_MIN_PKT_SIZE) {
 412                 pad = BNXT_MIN_PKT_SIZE - length;
 413                 if (skb_pad(skb, pad)) {
 414                         /* SKB already freed. */
 415                         tx_buf->skb = NULL;
 416                         return NETDEV_TX_OK;
 417                 }
 418                 length = BNXT_MIN_PKT_SIZE;
 419         }
 420
 421         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 422
 423         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 424                 dev_kfree_skb_any(skb);
 425                 tx_buf->skb = NULL;
 426                 return NETDEV_TX_OK;
 427         }
 428
 429         dma_unmap_addr_set(tx_buf, mapping, mapping);
 430         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 431                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 432
 433         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 434
 435         prod = NEXT_TX(prod);
 436         txbd1 = (struct tx_bd_ext *)
 437                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 438
 439         txbd1->tx_bd_hsize_lflags = 0;
 440         if (skb_is_gso(skb)) {
 441                 u32 hdr_len;
 442
 443                 if (skb->encapsulation)
 444                         hdr_len = skb_inner_network_offset(skb) +
 445                                 skb_inner_network_header_len(skb) +
 446                                 inner_tcp_hdrlen(skb);
 447                 else
 448                         hdr_len = skb_transport_offset(skb) +
 449                                 tcp_hdrlen(skb);
 450
 451                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 452                                         TX_BD_FLAGS_T_IPID |
 453                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 454                 length = skb_shinfo(skb)->gso_size;
 455                 txbd1->tx_bd_mss = cpu_to_le32(length);
 456                 length += hdr_len;
 457         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 458                 txbd1->tx_bd_hsize_lflags =
 459                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 460                 txbd1->tx_bd_mss = 0;
 461         }
 462
 463         length >>= 9;
 464         flags |= bnxt_lhint_arr[length];
 465         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 466
 467         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 468         txbd1->tx_bd_cfa_action =
 469                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 470         for (i = 0; i < last_frag; i++) {
 471                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 472
 473                 prod = NEXT_TX(prod);
 474                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 475
 476                 len = skb_frag_size(frag);
 477                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 478                                            DMA_TO_DEVICE);
 479
 480                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 481                         goto tx_dma_error;
 482
 483                 tx_buf = &txr->tx_buf_ring[prod];
 484                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 485
 486                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 487
 488                 flags = len << TX_BD_LEN_SHIFT;
 489                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 490         }
 491
 492         flags &= ~TX_BD_LEN;
 493         txbd->tx_bd_len_flags_type =
 494                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 495                             TX_BD_FLAGS_PACKET_END);
 496
 497         netdev_tx_sent_queue(txq, skb->len);
 498
 499         /* Sync BD data before updating doorbell */
 500         wmb();
 501
 502         prod = NEXT_TX(prod);
 503         txr->tx_prod = prod;
 504
 505         if (!skb->xmit_more || netif_xmit_stopped(txq))
 506                 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 507
 508 tx_done:
 509
 510         mmiowb();
 511
 512         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 513                 if (skb->xmit_more && !tx_buf->is_push)
 514                         bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 515
 516                 netif_tx_stop_queue(txq);
 517
 518                 /* netif_tx_stop_queue() must be done before checking
 519                  * tx index in bnxt_tx_avail() below, because in
 520                  * bnxt_tx_int(), we update tx index before checking for
 521                  * netif_tx_queue_stopped().
 522                  */
 523                 smp_mb();
 524                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 525                         netif_tx_wake_queue(txq);
 526         }
 527         return NETDEV_TX_OK;
 528
 529 tx_dma_error:
 530         last_frag = i;
 531
 532         /* start back at beginning and unmap skb */
 533         prod = txr->tx_prod;
 534         tx_buf = &txr->tx_buf_ring[prod];
 535         tx_buf->skb = NULL;
 536         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 537                          skb_headlen(skb), PCI_DMA_TODEVICE);
 538         prod = NEXT_TX(prod);
 539
 540         /* unmap remaining mapped pages */
 541         for (i = 0; i < last_frag; i++) {
 542                 prod = NEXT_TX(prod);
 543                 tx_buf = &txr->tx_buf_ring[prod];
 544                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 545                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 546                                PCI_DMA_TODEVICE);
 547         }
 548
 549         dev_kfree_skb_any(skb);
 550         return NETDEV_TX_OK;
 551 }
 552
 553 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 554 {
 555         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 556         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 557         u16 cons = txr->tx_cons;
 558         struct pci_dev *pdev = bp->pdev;
 559         int i;
 560         unsigned int tx_bytes = 0;
 561
 562         for (i = 0; i < nr_pkts; i++) {
 563                 struct bnxt_sw_tx_bd *tx_buf;
 564                 struct sk_buff *skb;
 565                 int j, last;
 566
 567                 tx_buf = &txr->tx_buf_ring[cons];
 568                 cons = NEXT_TX(cons);
 569                 skb = tx_buf->skb;
 570                 tx_buf->skb = NULL;
 571
 572                 if (tx_buf->is_push) {
 573                         tx_buf->is_push = 0;
 574                         goto next_tx_int;
 575                 }
 576
 577                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 578                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 579                 last = tx_buf->nr_frags;
 580
 581                 for (j = 0; j < last; j++) {
 582                         cons = NEXT_TX(cons);
 583                         tx_buf = &txr->tx_buf_ring[cons];
 584                         dma_unmap_page(
 585                                 &pdev->dev,
 586                                 dma_unmap_addr(tx_buf, mapping),
 587                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 588                                 PCI_DMA_TODEVICE);
 589                 }
 590
 591 next_tx_int:
 592                 cons = NEXT_TX(cons);
 593
 594                 tx_bytes += skb->len;
 595                 dev_kfree_skb_any(skb);
 596         }
 597
 598         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 599         txr->tx_cons = cons;
 600
 601         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 602          * before checking for netif_tx_queue_stopped().  Without the
 603          * memory barrier, there is a small possibility that bnxt_start_xmit()
 604          * will miss it and cause the queue to be stopped forever.
 605          */
 606         smp_mb();
 607
 608         if (unlikely(netif_tx_queue_stopped(txq)) &&
 609             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 610                 __netif_tx_lock(txq, smp_processor_id());
 611                 if (netif_tx_queue_stopped(txq) &&
 612                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 613                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 614                         netif_tx_wake_queue(txq);
 615                 __netif_tx_unlock(txq);
 616         }
 617 }
 618
 619 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 620                                          gfp_t gfp)
 621 {
 622         struct device *dev = &bp->pdev->dev;
 623         struct page *page;
 624
 625         page = alloc_page(gfp);
 626         if (!page)
 627                 return NULL;
 628
 629         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 630                                       DMA_ATTR_WEAK_ORDERING);
 631         if (dma_mapping_error(dev, *mapping)) {
 632                 __free_page(page);
 633                 return NULL;
 634         }
 635         *mapping += bp->rx_dma_offset;
 636         return page;
 637 }
 638
 639 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 640                                        gfp_t gfp)
 641 {
 642         u8 *data;
 643         struct pci_dev *pdev = bp->pdev;
 644
 645         data = kmalloc(bp->rx_buf_size, gfp);
 646         if (!data)
 647                 return NULL;
 648
 649         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 650                                         bp->rx_buf_use_size, bp->rx_dir,
 651                                         DMA_ATTR_WEAK_ORDERING);
 652
 653         if (dma_mapping_error(&pdev->dev, *mapping)) {
 654                 kfree(data);
 655                 data = NULL;
 656         }
 657         return data;
 658 }
 659
 660 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 661                        u16 prod, gfp_t gfp)
 662 {
 663         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 664         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 665         dma_addr_t mapping;
 666
 667         if (BNXT_RX_PAGE_MODE(bp)) {
 668                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 669
 670                 if (!page)
 671                         return -ENOMEM;
 672
 673                 rx_buf->data = page;
 674                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 675         } else {
 676                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 677
 678                 if (!data)
 679                         return -ENOMEM;
 680
 681                 rx_buf->data = data;
 682                 rx_buf->data_ptr = data + bp->rx_offset;
 683         }
 684         rx_buf->mapping = mapping;
 685
 686         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 687         return 0;
 688 }
 689
 690 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 691 {
 692         u16 prod = rxr->rx_prod;
 693         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 694         struct rx_bd *cons_bd, *prod_bd;
 695
 696         prod_rx_buf = &rxr->rx_buf_ring[prod];
 697         cons_rx_buf = &rxr->rx_buf_ring[cons];
 698
 699         prod_rx_buf->data = data;
 700         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 701
 702         prod_rx_buf->mapping = cons_rx_buf->mapping;
 703
 704         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 705         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 706
 707         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 708 }
 709
 710 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 711 {
 712         u16 next, max = rxr->rx_agg_bmap_size;
 713
 714         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 715         if (next >= max)
 716                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 717         return next;
 718 }
 719
 720 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 721                                      struct bnxt_rx_ring_info *rxr,
 722                                      u16 prod, gfp_t gfp)
 723 {
 724         struct rx_bd *rxbd =
 725                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 726         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 727         struct pci_dev *pdev = bp->pdev;
 728         struct page *page;
 729         dma_addr_t mapping;
 730         u16 sw_prod = rxr->rx_sw_agg_prod;
 731         unsigned int offset = 0;
 732
 733         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 734                 page = rxr->rx_page;
 735                 if (!page) {
 736                         page = alloc_page(gfp);
 737                         if (!page)
 738                                 return -ENOMEM;
 739                         rxr->rx_page = page;
 740                         rxr->rx_page_offset = 0;
 741                 }
 742                 offset = rxr->rx_page_offset;
 743                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 744                 if (rxr->rx_page_offset == PAGE_SIZE)
 745                         rxr->rx_page = NULL;
 746                 else
 747                         get_page(page);
 748         } else {
 749                 page = alloc_page(gfp);
 750                 if (!page)
 751                         return -ENOMEM;
 752         }
 753
 754         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 755                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 756                                      DMA_ATTR_WEAK_ORDERING);
 757         if (dma_mapping_error(&pdev->dev, mapping)) {
 758                 __free_page(page);
 759                 return -EIO;
 760         }
 761
 762         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 763                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 764
 765         __set_bit(sw_prod, rxr->rx_agg_bmap);
 766         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 767         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 768
 769         rx_agg_buf->page = page;
 770         rx_agg_buf->offset = offset;
 771         rx_agg_buf->mapping = mapping;
 772         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 773         rxbd->rx_bd_opaque = sw_prod;
 774         return 0;
 775 }
 776
 777 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 778                                    u32 agg_bufs)
 779 {
 780         struct bnxt *bp = bnapi->bp;
 781         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 782         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 783         u16 prod = rxr->rx_agg_prod;
 784         u16 sw_prod = rxr->rx_sw_agg_prod;
 785         u32 i;
 786
 787         for (i = 0; i < agg_bufs; i++) {
 788                 u16 cons;
 789                 struct rx_agg_cmp *agg;
 790                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 791                 struct rx_bd *prod_bd;
 792                 struct page *page;
 793
 794                 agg = (struct rx_agg_cmp *)
 795                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 796                 cons = agg->rx_agg_cmp_opaque;
 797                 __clear_bit(cons, rxr->rx_agg_bmap);
 798
 799                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 800                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 801
 802                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 803                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 804                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 805
 806                 /* It is possible for sw_prod to be equal to cons, so
 807                  * set cons_rx_buf->page to NULL first.
 808                  */
 809                 page = cons_rx_buf->page;
 810                 cons_rx_buf->page = NULL;
 811                 prod_rx_buf->page = page;
 812                 prod_rx_buf->offset = cons_rx_buf->offset;
 813
 814                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 815
 816                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 817
 818                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 819                 prod_bd->rx_bd_opaque = sw_prod;
 820
 821                 prod = NEXT_RX_AGG(prod);
 822                 sw_prod = NEXT_RX_AGG(sw_prod);
 823                 cp_cons = NEXT_CMP(cp_cons);
 824         }
 825         rxr->rx_agg_prod = prod;
 826         rxr->rx_sw_agg_prod = sw_prod;
 827 }
 828
 829 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 830                                         struct bnxt_rx_ring_info *rxr,
 831                                         u16 cons, void *data, u8 *data_ptr,
 832                                         dma_addr_t dma_addr,
 833                                         unsigned int offset_and_len)
 834 {
 835         unsigned int payload = offset_and_len >> 16;
 836         unsigned int len = offset_and_len & 0xffff;
 837         struct skb_frag_struct *frag;
 838         struct page *page = data;
 839         u16 prod = rxr->rx_prod;
 840         struct sk_buff *skb;
 841         int off, err;
 842
 843         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 844         if (unlikely(err)) {
 845                 bnxt_reuse_rx_data(rxr, cons, data);
 846                 return NULL;
 847         }
 848         dma_addr -= bp->rx_dma_offset;
 849         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 850                              DMA_ATTR_WEAK_ORDERING);
 851
 852         if (unlikely(!payload))
 853                 payload = eth_get_headlen(data_ptr, len);
 854
 855         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 856         if (!skb) {
 857                 __free_page(page);
 858                 return NULL;
 859         }
 860
 861         off = (void *)data_ptr - page_address(page);
 862         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 863         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 864                payload + NET_IP_ALIGN);
 865
 866         frag = &skb_shinfo(skb)->frags[0];
 867         skb_frag_size_sub(frag, payload);
 868         frag->page_offset += payload;
 869         skb->data_len -= payload;
 870         skb->tail += payload;
 871
 872         return skb;
 873 }
 874
 875 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 876                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 877                                    void *data, u8 *data_ptr,
 878                                    dma_addr_t dma_addr,
 879                                    unsigned int offset_and_len)
 880 {
 881         u16 prod = rxr->rx_prod;
 882         struct sk_buff *skb;
 883         int err;
 884
 885         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 886         if (unlikely(err)) {
 887                 bnxt_reuse_rx_data(rxr, cons, data);
 888                 return NULL;
 889         }
 890
 891         skb = build_skb(data, 0);
 892         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 893                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 894         if (!skb) {
 895                 kfree(data);
 896                 return NULL;
 897         }
 898
 899         skb_reserve(skb, bp->rx_offset);
 900         skb_put(skb, offset_and_len & 0xffff);
 901         return skb;
 902 }
 903
 904 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 905                                      struct sk_buff *skb, u16 cp_cons,
 906                                      u32 agg_bufs)
 907 {
 908         struct pci_dev *pdev = bp->pdev;
 909         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 910         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 911         u16 prod = rxr->rx_agg_prod;
 912         u32 i;
 913
 914         for (i = 0; i < agg_bufs; i++) {
 915                 u16 cons, frag_len;
 916                 struct rx_agg_cmp *agg;
 917                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 918                 struct page *page;
 919                 dma_addr_t mapping;
 920
 921                 agg = (struct rx_agg_cmp *)
 922                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 923                 cons = agg->rx_agg_cmp_opaque;
 924                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 925                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 926
 927                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 928                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 929                                    cons_rx_buf->offset, frag_len);
 930                 __clear_bit(cons, rxr->rx_agg_bmap);
 931
 932                 /* It is possible for bnxt_alloc_rx_page() to allocate
 933                  * a sw_prod index that equals the cons index, so we
 934                  * need to clear the cons entry now.
 935                  */
 936                 mapping = cons_rx_buf->mapping;
 937                 page = cons_rx_buf->page;
 938                 cons_rx_buf->page = NULL;
 939
 940                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 941                         struct skb_shared_info *shinfo;
 942                         unsigned int nr_frags;
 943
 944                         shinfo = skb_shinfo(skb);
 945                         nr_frags = --shinfo->nr_frags;
 946                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 947
 948                         dev_kfree_skb(skb);
 949
 950                         cons_rx_buf->page = page;
 951
 952                         /* Update prod since possibly some pages have been
 953                          * allocated already.
 954                          */
 955                         rxr->rx_agg_prod = prod;
 956                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 957                         return NULL;
 958                 }
 959
 960                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 961                                      PCI_DMA_FROMDEVICE,
 962                                      DMA_ATTR_WEAK_ORDERING);
 963
 964                 skb->data_len += frag_len;
 965                 skb->len += frag_len;
 966                 skb->truesize += PAGE_SIZE;
 967
 968                 prod = NEXT_RX_AGG(prod);
 969                 cp_cons = NEXT_CMP(cp_cons);
 970         }
 971         rxr->rx_agg_prod = prod;
 972         return skb;
 973 }
 974
 975 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 976                                u8 agg_bufs, u32 *raw_cons)
 977 {
 978         u16 last;
 979         struct rx_agg_cmp *agg;
 980
 981         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 982         last = RING_CMP(*raw_cons);
 983         agg = (struct rx_agg_cmp *)
 984                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 985         return RX_AGG_CMP_VALID(agg, *raw_cons);
 986 }
 987
 988 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 989                                             unsigned int len,
 990                                             dma_addr_t mapping)
 991 {
 992         struct bnxt *bp = bnapi->bp;
 993         struct pci_dev *pdev = bp->pdev;
 994         struct sk_buff *skb;
 995
 996         skb = napi_alloc_skb(&bnapi->napi, len);
 997         if (!skb)
 998                 return NULL;
 999
1000         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1001                                 bp->rx_dir);
1002
1003         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1004                len + NET_IP_ALIGN);
1005
1006         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1007                                    bp->rx_dir);
1008
1009         skb_put(skb, len);
1010         return skb;
1011 }
1012
1013 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1014                            u32 *raw_cons, void *cmp)
1015 {
1016         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1017         struct rx_cmp *rxcmp = cmp;
1018         u32 tmp_raw_cons = *raw_cons;
1019         u8 cmp_type, agg_bufs = 0;
1020
1021         cmp_type = RX_CMP_TYPE(rxcmp);
1022
1023         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1024                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1025                             RX_CMP_AGG_BUFS) >>
1026                            RX_CMP_AGG_BUFS_SHIFT;
1027         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1028                 struct rx_tpa_end_cmp *tpa_end = cmp;
1029
1030                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1031                             RX_TPA_END_CMP_AGG_BUFS) >>
1032                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1033         }
1034
1035         if (agg_bufs) {
1036                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1037                         return -EBUSY;
1038         }
1039         *raw_cons = tmp_raw_cons;
1040         return 0;
1041 }
1042
1043 static void bnxt_queue_sp_work(struct bnxt *bp)
1044 {
1045         if (BNXT_PF(bp))
1046                 queue_work(bnxt_pf_wq, &bp->sp_task);
1047         else
1048                 schedule_work(&bp->sp_task);
1049 }
1050
1051 static void bnxt_cancel_sp_work(struct bnxt *bp)
1052 {
1053         if (BNXT_PF(bp))
1054                 flush_workqueue(bnxt_pf_wq);
1055         else
1056                 cancel_work_sync(&bp->sp_task);
1057 }
1058
1059 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1060 {
1061         if (!rxr->bnapi->in_reset) {
1062                 rxr->bnapi->in_reset = true;
1063                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1064                 bnxt_queue_sp_work(bp);
1065         }
1066         rxr->rx_next_cons = 0xffff;
1067 }
1068
1069 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1070                            struct rx_tpa_start_cmp *tpa_start,
1071                            struct rx_tpa_start_cmp_ext *tpa_start1)
1072 {
1073         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1074         u16 cons, prod;
1075         struct bnxt_tpa_info *tpa_info;
1076         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1077         struct rx_bd *prod_bd;
1078         dma_addr_t mapping;
1079
1080         cons = tpa_start->rx_tpa_start_cmp_opaque;
1081         prod = rxr->rx_prod;
1082         cons_rx_buf = &rxr->rx_buf_ring[cons];
1083         prod_rx_buf = &rxr->rx_buf_ring[prod];
1084         tpa_info = &rxr->rx_tpa[agg_id];
1085
1086         if (unlikely(cons != rxr->rx_next_cons)) {
1087                 bnxt_sched_reset(bp, rxr);
1088                 return;
1089         }
1090         /* Store cfa_code in tpa_info to use in tpa_end
1091          * completion processing.
1092          */
1093         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1094         prod_rx_buf->data = tpa_info->data;
1095         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1096
1097         mapping = tpa_info->mapping;
1098         prod_rx_buf->mapping = mapping;
1099
1100         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1101
1102         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1103
1104         tpa_info->data = cons_rx_buf->data;
1105         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1106         cons_rx_buf->data = NULL;
1107         tpa_info->mapping = cons_rx_buf->mapping;
1108
1109         tpa_info->len =
1110                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1111                                 RX_TPA_START_CMP_LEN_SHIFT;
1112         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1113                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1114
1115                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1116                 tpa_info->gso_type = SKB_GSO_TCPV4;
1117                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1118                 if (hash_type == 3)
1119                         tpa_info->gso_type = SKB_GSO_TCPV6;
1120                 tpa_info->rss_hash =
1121                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1122         } else {
1123                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1124                 tpa_info->gso_type = 0;
1125                 if (netif_msg_rx_err(bp))
1126                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1127         }
1128         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1129         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1130         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1131
1132         rxr->rx_prod = NEXT_RX(prod);
1133         cons = NEXT_RX(cons);
1134         rxr->rx_next_cons = NEXT_RX(cons);
1135         cons_rx_buf = &rxr->rx_buf_ring[cons];
1136
1137         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1138         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1139         cons_rx_buf->data = NULL;
1140 }
1141
1142 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1143                            u16 cp_cons, u32 agg_bufs)
1144 {
1145         if (agg_bufs)
1146                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1147 }
1148
1149 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1150                                            int payload_off, int tcp_ts,
1151                                            struct sk_buff *skb)
1152 {
1153 #ifdef CONFIG_INET
1154         struct tcphdr *th;
1155         int len, nw_off;
1156         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1157         u32 hdr_info = tpa_info->hdr_info;
1158         bool loopback = false;
1159
1160         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1161         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1162         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1163
1164         /* If the packet is an internal loopback packet, the offsets will
1165          * have an extra 4 bytes.
1166          */
1167         if (inner_mac_off == 4) {
1168                 loopback = true;
1169         } else if (inner_mac_off > 4) {
1170                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1171                                             ETH_HLEN - 2));
1172
1173                 /* We only support inner iPv4/ipv6.  If we don't see the
1174                  * correct protocol ID, it must be a loopback packet where
1175                  * the offsets are off by 4.
1176                  */
1177                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1178                         loopback = true;
1179         }
1180         if (loopback) {
1181                 /* internal loopback packet, subtract all offsets by 4 */
1182                 inner_ip_off -= 4;
1183                 inner_mac_off -= 4;
1184                 outer_ip_off -= 4;
1185         }
1186
1187         nw_off = inner_ip_off - ETH_HLEN;
1188         skb_set_network_header(skb, nw_off);
1189         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1190                 struct ipv6hdr *iph = ipv6_hdr(skb);
1191
1192                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1193                 len = skb->len - skb_transport_offset(skb);
1194                 th = tcp_hdr(skb);
1195                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1196         } else {
1197                 struct iphdr *iph = ip_hdr(skb);
1198
1199                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1200                 len = skb->len - skb_transport_offset(skb);
1201                 th = tcp_hdr(skb);
1202                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1203         }
1204
1205         if (inner_mac_off) { /* tunnel */
1206                 struct udphdr *uh = NULL;
1207                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1208                                             ETH_HLEN - 2));
1209
1210                 if (proto == htons(ETH_P_IP)) {
1211                         struct iphdr *iph = (struct iphdr *)skb->data;
1212
1213                         if (iph->protocol == IPPROTO_UDP)
1214                                 uh = (struct udphdr *)(iph + 1);
1215                 } else {
1216                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1217
1218                         if (iph->nexthdr == IPPROTO_UDP)
1219                                 uh = (struct udphdr *)(iph + 1);
1220                 }
1221                 if (uh) {
1222                         if (uh->check)
1223                                 skb_shinfo(skb)->gso_type |=
1224                                         SKB_GSO_UDP_TUNNEL_CSUM;
1225                         else
1226                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1227                 }
1228         }
1229 #endif
1230         return skb;
1231 }
1232
1233 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1234 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1235
1236 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1237                                            int payload_off, int tcp_ts,
1238                                            struct sk_buff *skb)
1239 {
1240 #ifdef CONFIG_INET
1241         struct tcphdr *th;
1242         int len, nw_off, tcp_opt_len = 0;
1243
1244         if (tcp_ts)
1245                 tcp_opt_len = 12;
1246
1247         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1248                 struct iphdr *iph;
1249
1250                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1251                          ETH_HLEN;
1252                 skb_set_network_header(skb, nw_off);
1253                 iph = ip_hdr(skb);
1254                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1255                 len = skb->len - skb_transport_offset(skb);
1256                 th = tcp_hdr(skb);
1257                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1258         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1259                 struct ipv6hdr *iph;
1260
1261                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1262                          ETH_HLEN;
1263                 skb_set_network_header(skb, nw_off);
1264                 iph = ipv6_hdr(skb);
1265                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1266                 len = skb->len - skb_transport_offset(skb);
1267                 th = tcp_hdr(skb);
1268                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1269         } else {
1270                 dev_kfree_skb_any(skb);
1271                 return NULL;
1272         }
1273
1274         if (nw_off) { /* tunnel */
1275                 struct udphdr *uh = NULL;
1276
1277                 if (skb->protocol == htons(ETH_P_IP)) {
1278                         struct iphdr *iph = (struct iphdr *)skb->data;
1279
1280                         if (iph->protocol == IPPROTO_UDP)
1281                                 uh = (struct udphdr *)(iph + 1);
1282                 } else {
1283                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1284
1285                         if (iph->nexthdr == IPPROTO_UDP)
1286                                 uh = (struct udphdr *)(iph + 1);
1287                 }
1288                 if (uh) {
1289                         if (uh->check)
1290                                 skb_shinfo(skb)->gso_type |=
1291                                         SKB_GSO_UDP_TUNNEL_CSUM;
1292                         else
1293                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1294                 }
1295         }
1296 #endif
1297         return skb;
1298 }
1299
1300 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1301                                            struct bnxt_tpa_info *tpa_info,
1302                                            struct rx_tpa_end_cmp *tpa_end,
1303                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1304                                            struct sk_buff *skb)
1305 {
1306 #ifdef CONFIG_INET
1307         int payload_off;
1308         u16 segs;
1309
1310         segs = TPA_END_TPA_SEGS(tpa_end);
1311         if (segs == 1)
1312                 return skb;
1313
1314         NAPI_GRO_CB(skb)->count = segs;
1315         skb_shinfo(skb)->gso_size =
1316                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1317         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1318         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1319                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1320                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1321         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1322         if (likely(skb))
1323                 tcp_gro_complete(skb);
1324 #endif
1325         return skb;
1326 }
1327
1328 /* Given the cfa_code of a received packet determine which
1329  * netdev (vf-rep or PF) the packet is destined to.
1330  */
1331 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1332 {
1333         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1334
1335         /* if vf-rep dev is NULL, the must belongs to the PF */
1336         return dev ? dev : bp->dev;
1337 }
1338
1339 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1340                                            struct bnxt_napi *bnapi,
1341                                            u32 *raw_cons,
1342                                            struct rx_tpa_end_cmp *tpa_end,
1343                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1344                                            u8 *event)
1345 {
1346         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1347         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1348         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1349         u8 *data_ptr, agg_bufs;
1350         u16 cp_cons = RING_CMP(*raw_cons);
1351         unsigned int len;
1352         struct bnxt_tpa_info *tpa_info;
1353         dma_addr_t mapping;
1354         struct sk_buff *skb;
1355         void *data;
1356
1357         if (unlikely(bnapi->in_reset)) {
1358                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1359
1360                 if (rc < 0)
1361                         return ERR_PTR(-EBUSY);
1362                 return NULL;
1363         }
1364
1365         tpa_info = &rxr->rx_tpa[agg_id];
1366         data = tpa_info->data;
1367         data_ptr = tpa_info->data_ptr;
1368         prefetch(data_ptr);
1369         len = tpa_info->len;
1370         mapping = tpa_info->mapping;
1371
1372         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1373                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1374
1375         if (agg_bufs) {
1376                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1377                         return ERR_PTR(-EBUSY);
1378
1379                 *event |= BNXT_AGG_EVENT;
1380                 cp_cons = NEXT_CMP(cp_cons);
1381         }
1382
1383         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1384                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1385                 if (agg_bufs > MAX_SKB_FRAGS)
1386                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1387                                     agg_bufs, (int)MAX_SKB_FRAGS);
1388                 return NULL;
1389         }
1390
1391         if (len <= bp->rx_copy_thresh) {
1392                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1393                 if (!skb) {
1394                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1395                         return NULL;
1396                 }
1397         } else {
1398                 u8 *new_data;
1399                 dma_addr_t new_mapping;
1400
1401                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1402                 if (!new_data) {
1403                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1404                         return NULL;
1405                 }
1406
1407                 tpa_info->data = new_data;
1408                 tpa_info->data_ptr = new_data + bp->rx_offset;
1409                 tpa_info->mapping = new_mapping;
1410
1411                 skb = build_skb(data, 0);
1412                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1413                                        bp->rx_buf_use_size, bp->rx_dir,
1414                                        DMA_ATTR_WEAK_ORDERING);
1415
1416                 if (!skb) {
1417                         kfree(data);
1418                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1419                         return NULL;
1420                 }
1421                 skb_reserve(skb, bp->rx_offset);
1422                 skb_put(skb, len);
1423         }
1424
1425         if (agg_bufs) {
1426                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1427                 if (!skb) {
1428                         /* Page reuse already handled by bnxt_rx_pages(). */
1429                         return NULL;
1430                 }
1431         }
1432
1433         skb->protocol =
1434                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1435
1436         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1437                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1438
1439         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1440             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1441                 u16 vlan_proto = tpa_info->metadata >>
1442                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1443                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1444
1445                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1446         }
1447
1448         skb_checksum_none_assert(skb);
1449         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1450                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1451                 skb->csum_level =
1452                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1453         }
1454
1455         if (TPA_END_GRO(tpa_end))
1456                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1457
1458         return skb;
1459 }
1460
1461 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1462                              struct sk_buff *skb)
1463 {
1464         if (skb->dev != bp->dev) {
1465                 /* this packet belongs to a vf-rep */
1466                 bnxt_vf_rep_rx(bp, skb);
1467                 return;
1468         }
1469         skb_record_rx_queue(skb, bnapi->index);
1470         napi_gro_receive(&bnapi->napi, skb);
1471 }
1472
1473 /* returns the following:
1474  * 1       - 1 packet successfully received
1475  * 0       - successful TPA_START, packet not completed yet
1476  * -EBUSY  - completion ring does not have all the agg buffers yet
1477  * -ENOMEM - packet aborted due to out of memory
1478  * -EIO    - packet aborted due to hw error indicated in BD
1479  */
1480 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1481                        u8 *event)
1482 {
1483         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1484         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1485         struct net_device *dev = bp->dev;
1486         struct rx_cmp *rxcmp;
1487         struct rx_cmp_ext *rxcmp1;
1488         u32 tmp_raw_cons = *raw_cons;
1489         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1490         struct bnxt_sw_rx_bd *rx_buf;
1491         unsigned int len;
1492         u8 *data_ptr, agg_bufs, cmp_type;
1493         dma_addr_t dma_addr;
1494         struct sk_buff *skb;
1495         void *data;
1496         int rc = 0;
1497         u32 misc;
1498
1499         rxcmp = (struct rx_cmp *)
1500                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1501
1502         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1503         cp_cons = RING_CMP(tmp_raw_cons);
1504         rxcmp1 = (struct rx_cmp_ext *)
1505                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1506
1507         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1508                 return -EBUSY;
1509
1510         cmp_type = RX_CMP_TYPE(rxcmp);
1511
1512         prod = rxr->rx_prod;
1513
1514         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1515                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1516                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1517
1518                 *event |= BNXT_RX_EVENT;
1519                 goto next_rx_no_prod_no_len;
1520
1521         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1522                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1523                                    (struct rx_tpa_end_cmp *)rxcmp,
1524                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1525
1526                 if (IS_ERR(skb))
1527                         return -EBUSY;
1528
1529                 rc = -ENOMEM;
1530                 if (likely(skb)) {
1531                         bnxt_deliver_skb(bp, bnapi, skb);
1532                         rc = 1;
1533                 }
1534                 *event |= BNXT_RX_EVENT;
1535                 goto next_rx_no_prod_no_len;
1536         }
1537
1538         cons = rxcmp->rx_cmp_opaque;
1539         rx_buf = &rxr->rx_buf_ring[cons];
1540         data = rx_buf->data;
1541         data_ptr = rx_buf->data_ptr;
1542         if (unlikely(cons != rxr->rx_next_cons)) {
1543                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1544
1545                 bnxt_sched_reset(bp, rxr);
1546                 return rc1;
1547         }
1548         prefetch(data_ptr);
1549
1550         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1551         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1552
1553         if (agg_bufs) {
1554                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1555                         return -EBUSY;
1556
1557                 cp_cons = NEXT_CMP(cp_cons);
1558                 *event |= BNXT_AGG_EVENT;
1559         }
1560         *event |= BNXT_RX_EVENT;
1561
1562         rx_buf->data = NULL;
1563         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1564                 bnxt_reuse_rx_data(rxr, cons, data);
1565                 if (agg_bufs)
1566                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1567
1568                 rc = -EIO;
1569                 goto next_rx;
1570         }
1571
1572         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1573         dma_addr = rx_buf->mapping;
1574
1575         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1576                 rc = 1;
1577                 goto next_rx;
1578         }
1579
1580         if (len <= bp->rx_copy_thresh) {
1581                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1582                 bnxt_reuse_rx_data(rxr, cons, data);
1583                 if (!skb) {
1584                         rc = -ENOMEM;
1585                         goto next_rx;
1586                 }
1587         } else {
1588                 u32 payload;
1589
1590                 if (rx_buf->data_ptr == data_ptr)
1591                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1592                 else
1593                         payload = 0;
1594                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1595                                       payload | len);
1596                 if (!skb) {
1597                         rc = -ENOMEM;
1598                         goto next_rx;
1599                 }
1600         }
1601
1602         if (agg_bufs) {
1603                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1604                 if (!skb) {
1605                         rc = -ENOMEM;
1606                         goto next_rx;
1607                 }
1608         }
1609
1610         if (RX_CMP_HASH_VALID(rxcmp)) {
1611                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1612                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1613
1614                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1615                 if (hash_type != 1 && hash_type != 3)
1616                         type = PKT_HASH_TYPE_L3;
1617                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1618         }
1619
1620         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1621         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1622
1623         if ((rxcmp1->rx_cmp_flags2 &
1624              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1625             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1626                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1627                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1628                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1629
1630                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1631         }
1632
1633         skb_checksum_none_assert(skb);
1634         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1635                 if (dev->features & NETIF_F_RXCSUM) {
1636                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1637                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1638                 }
1639         } else {
1640                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1641                         if (dev->features & NETIF_F_RXCSUM)
1642                                 cpr->rx_l4_csum_errors++;
1643                 }
1644         }
1645
1646         bnxt_deliver_skb(bp, bnapi, skb);
1647         rc = 1;
1648
1649 next_rx:
1650         rxr->rx_prod = NEXT_RX(prod);
1651         rxr->rx_next_cons = NEXT_RX(cons);
1652
1653         cpr->rx_packets += 1;
1654         cpr->rx_bytes += len;
1655
1656 next_rx_no_prod_no_len:
1657         *raw_cons = tmp_raw_cons;
1658
1659         return rc;
1660 }
1661
1662 /* In netpoll mode, if we are using a combined completion ring, we need to
1663  * discard the rx packets and recycle the buffers.
1664  */
1665 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1666                                  u32 *raw_cons, u8 *event)
1667 {
1668         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1669         u32 tmp_raw_cons = *raw_cons;
1670         struct rx_cmp_ext *rxcmp1;
1671         struct rx_cmp *rxcmp;
1672         u16 cp_cons;
1673         u8 cmp_type;
1674
1675         cp_cons = RING_CMP(tmp_raw_cons);
1676         rxcmp = (struct rx_cmp *)
1677                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1678
1679         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1680         cp_cons = RING_CMP(tmp_raw_cons);
1681         rxcmp1 = (struct rx_cmp_ext *)
1682                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1683
1684         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1685                 return -EBUSY;
1686
1687         cmp_type = RX_CMP_TYPE(rxcmp);
1688         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1689                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1690                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1691         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1692                 struct rx_tpa_end_cmp_ext *tpa_end1;
1693
1694                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1695                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1696                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1697         }
1698         return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1699 }
1700
1701 #define BNXT_GET_EVENT_PORT(data)       \
1702         ((data) &                       \
1703          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1704
1705 static int bnxt_async_event_process(struct bnxt *bp,
1706                                     struct hwrm_async_event_cmpl *cmpl)
1707 {
1708         u16 event_id = le16_to_cpu(cmpl->event_id);
1709
1710         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1711         switch (event_id) {
1712         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1713                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1714                 struct bnxt_link_info *link_info = &bp->link_info;
1715
1716                 if (BNXT_VF(bp))
1717                         goto async_event_process_exit;
1718
1719                 /* print unsupported speed warning in forced speed mode only */
1720                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1721                     (data1 & 0x20000)) {
1722                         u16 fw_speed = link_info->force_link_speed;
1723                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1724
1725                         if (speed != SPEED_UNKNOWN)
1726                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1727                                             speed);
1728                 }
1729                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1730                 /* fall thru */
1731         }
1732         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1733                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1734                 break;
1735         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1736                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1737                 break;
1738         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1739                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1740                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1741
1742                 if (BNXT_VF(bp))
1743                         break;
1744
1745                 if (bp->pf.port_id != port_id)
1746                         break;
1747
1748                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1749                 break;
1750         }
1751         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1752                 if (BNXT_PF(bp))
1753                         goto async_event_process_exit;
1754                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1755                 break;
1756         default:
1757                 goto async_event_process_exit;
1758         }
1759         bnxt_queue_sp_work(bp);
1760 async_event_process_exit:
1761         bnxt_ulp_async_events(bp, cmpl);
1762         return 0;
1763 }
1764
1765 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1766 {
1767         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1768         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1769         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1770                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1771
1772         switch (cmpl_type) {
1773         case CMPL_BASE_TYPE_HWRM_DONE:
1774                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1775                 if (seq_id == bp->hwrm_intr_seq_id)
1776                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1777                 else
1778                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1779                 break;
1780
1781         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1782                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1783
1784                 if ((vf_id < bp->pf.first_vf_id) ||
1785                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1786                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1787                                    vf_id);
1788                         return -EINVAL;
1789                 }
1790
1791                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1792                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1793                 bnxt_queue_sp_work(bp);
1794                 break;
1795
1796         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1797                 bnxt_async_event_process(bp,
1798                                          (struct hwrm_async_event_cmpl *)txcmp);
1799
1800         default:
1801                 break;
1802         }
1803
1804         return 0;
1805 }
1806
1807 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1808 {
1809         struct bnxt_napi *bnapi = dev_instance;
1810         struct bnxt *bp = bnapi->bp;
1811         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1812         u32 cons = RING_CMP(cpr->cp_raw_cons);
1813
1814         cpr->event_ctr++;
1815         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1816         napi_schedule(&bnapi->napi);
1817         return IRQ_HANDLED;
1818 }
1819
1820 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1821 {
1822         u32 raw_cons = cpr->cp_raw_cons;
1823         u16 cons = RING_CMP(raw_cons);
1824         struct tx_cmp *txcmp;
1825
1826         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1827
1828         return TX_CMP_VALID(txcmp, raw_cons);
1829 }
1830
1831 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1832 {
1833         struct bnxt_napi *bnapi = dev_instance;
1834         struct bnxt *bp = bnapi->bp;
1835         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1836         u32 cons = RING_CMP(cpr->cp_raw_cons);
1837         u32 int_status;
1838
1839         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1840
1841         if (!bnxt_has_work(bp, cpr)) {
1842                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1843                 /* return if erroneous interrupt */
1844                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1845                         return IRQ_NONE;
1846         }
1847
1848         /* disable ring IRQ */
1849         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1850
1851         /* Return here if interrupt is shared and is disabled. */
1852         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1853                 return IRQ_HANDLED;
1854
1855         napi_schedule(&bnapi->napi);
1856         return IRQ_HANDLED;
1857 }
1858
1859 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1860 {
1861         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1862         u32 raw_cons = cpr->cp_raw_cons;
1863         u32 cons;
1864         int tx_pkts = 0;
1865         int rx_pkts = 0;
1866         u8 event = 0;
1867         struct tx_cmp *txcmp;
1868
1869         while (1) {
1870                 int rc;
1871
1872                 cons = RING_CMP(raw_cons);
1873                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1874
1875                 if (!TX_CMP_VALID(txcmp, raw_cons))
1876                         break;
1877
1878                 /* The valid test of the entry must be done first before
1879                  * reading any further.
1880                  */
1881                 dma_rmb();
1882                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1883                         tx_pkts++;
1884                         /* return full budget so NAPI will complete. */
1885                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1886                                 rx_pkts = budget;
1887                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1888                         if (likely(budget))
1889                                 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1890                         else
1891                                 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1892                                                            &event);
1893                         if (likely(rc >= 0))
1894                                 rx_pkts += rc;
1895                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1896                          * the NAPI budget.  Otherwise, we may potentially loop
1897                          * here forever if we consistently cannot allocate
1898                          * buffers.
1899                          */
1900                         else if (rc == -ENOMEM && budget)
1901                                 rx_pkts++;
1902                         else if (rc == -EBUSY)  /* partial completion */
1903                                 break;
1904                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1905                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1906                                     (TX_CMP_TYPE(txcmp) ==
1907                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1908                                     (TX_CMP_TYPE(txcmp) ==
1909                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1910                         bnxt_hwrm_handler(bp, txcmp);
1911                 }
1912                 raw_cons = NEXT_RAW_CMP(raw_cons);
1913
1914                 if (rx_pkts == budget)
1915                         break;
1916         }
1917
1918         if (event & BNXT_TX_EVENT) {
1919                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1920                 void __iomem *db = txr->tx_doorbell;
1921                 u16 prod = txr->tx_prod;
1922
1923                 /* Sync BD data before updating doorbell */
1924                 wmb();
1925
1926                 bnxt_db_write_relaxed(bp, db, DB_KEY_TX | prod);
1927         }
1928
1929         cpr->cp_raw_cons = raw_cons;
1930         /* ACK completion ring before freeing tx ring and producing new
1931          * buffers in rx/agg rings to prevent overflowing the completion
1932          * ring.
1933          */
1934         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1935
1936         if (tx_pkts)
1937                 bnapi->tx_int(bp, bnapi, tx_pkts);
1938
1939         if (event & BNXT_RX_EVENT) {
1940                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1941
1942                 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1943                 if (event & BNXT_AGG_EVENT)
1944                         bnxt_db_write(bp, rxr->rx_agg_doorbell,
1945                                       DB_KEY_RX | rxr->rx_agg_prod);
1946         }
1947         return rx_pkts;
1948 }
1949
1950 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1951 {
1952         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1953         struct bnxt *bp = bnapi->bp;
1954         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1955         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1956         struct tx_cmp *txcmp;
1957         struct rx_cmp_ext *rxcmp1;
1958         u32 cp_cons, tmp_raw_cons;
1959         u32 raw_cons = cpr->cp_raw_cons;
1960         u32 rx_pkts = 0;
1961         u8 event = 0;
1962
1963         while (1) {
1964                 int rc;
1965
1966                 cp_cons = RING_CMP(raw_cons);
1967                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1968
1969                 if (!TX_CMP_VALID(txcmp, raw_cons))
1970                         break;
1971
1972                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1973                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1974                         cp_cons = RING_CMP(tmp_raw_cons);
1975                         rxcmp1 = (struct rx_cmp_ext *)
1976                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1977
1978                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1979                                 break;
1980
1981                         /* force an error to recycle the buffer */
1982                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1983                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1984
1985                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1986                         if (likely(rc == -EIO) && budget)
1987                                 rx_pkts++;
1988                         else if (rc == -EBUSY)  /* partial completion */
1989                                 break;
1990                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1991                                     CMPL_BASE_TYPE_HWRM_DONE)) {
1992                         bnxt_hwrm_handler(bp, txcmp);
1993                 } else {
1994                         netdev_err(bp->dev,
1995                                    "Invalid completion received on special ring\n");
1996                 }
1997                 raw_cons = NEXT_RAW_CMP(raw_cons);
1998
1999                 if (rx_pkts == budget)
2000                         break;
2001         }
2002
2003         cpr->cp_raw_cons = raw_cons;
2004         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2005         bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
2006
2007         if (event & BNXT_AGG_EVENT)
2008                 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2009                               DB_KEY_RX | rxr->rx_agg_prod);
2010
2011         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2012                 napi_complete_done(napi, rx_pkts);
2013                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2014         }
2015         return rx_pkts;
2016 }
2017
2018 static int bnxt_poll(struct napi_struct *napi, int budget)
2019 {
2020         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2021         struct bnxt *bp = bnapi->bp;
2022         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2023         int work_done = 0;
2024
2025         while (1) {
2026                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2027
2028                 if (work_done >= budget)
2029                         break;
2030
2031                 if (!bnxt_has_work(bp, cpr)) {
2032                         if (napi_complete_done(napi, work_done))
2033                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2034                                                  cpr->cp_raw_cons);
2035                         break;
2036                 }
2037         }
2038         if (bp->flags & BNXT_FLAG_DIM) {
2039                 struct net_dim_sample dim_sample;
2040
2041                 net_dim_sample(cpr->event_ctr,
2042                                cpr->rx_packets,
2043                                cpr->rx_bytes,
2044                                &dim_sample);
2045                 net_dim(&cpr->dim, dim_sample);
2046         }
2047         mmiowb();
2048         return work_done;
2049 }
2050
2051 static void bnxt_free_tx_skbs(struct bnxt *bp)
2052 {
2053         int i, max_idx;
2054         struct pci_dev *pdev = bp->pdev;
2055
2056         if (!bp->tx_ring)
2057                 return;
2058
2059         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2060         for (i = 0; i < bp->tx_nr_rings; i++) {
2061                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2062                 int j;
2063
2064                 for (j = 0; j < max_idx;) {
2065                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2066                         struct sk_buff *skb = tx_buf->skb;
2067                         int k, last;
2068
2069                         if (!skb) {
2070                                 j++;
2071                                 continue;
2072                         }
2073
2074                         tx_buf->skb = NULL;
2075
2076                         if (tx_buf->is_push) {
2077                                 dev_kfree_skb(skb);
2078                                 j += 2;
2079                                 continue;
2080                         }
2081
2082                         dma_unmap_single(&pdev->dev,
2083                                          dma_unmap_addr(tx_buf, mapping),
2084                                          skb_headlen(skb),
2085                                          PCI_DMA_TODEVICE);
2086
2087                         last = tx_buf->nr_frags;
2088                         j += 2;
2089                         for (k = 0; k < last; k++, j++) {
2090                                 int ring_idx = j & bp->tx_ring_mask;
2091                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2092
2093                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2094                                 dma_unmap_page(
2095                                         &pdev->dev,
2096                                         dma_unmap_addr(tx_buf, mapping),
2097                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2098                         }
2099                         dev_kfree_skb(skb);
2100                 }
2101                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2102         }
2103 }
2104
2105 static void bnxt_free_rx_skbs(struct bnxt *bp)
2106 {
2107         int i, max_idx, max_agg_idx;
2108         struct pci_dev *pdev = bp->pdev;
2109
2110         if (!bp->rx_ring)
2111                 return;
2112
2113         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2114         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2115         for (i = 0; i < bp->rx_nr_rings; i++) {
2116                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2117                 int j;
2118
2119                 if (rxr->rx_tpa) {
2120                         for (j = 0; j < MAX_TPA; j++) {
2121                                 struct bnxt_tpa_info *tpa_info =
2122                                                         &rxr->rx_tpa[j];
2123                                 u8 *data = tpa_info->data;
2124
2125                                 if (!data)
2126                                         continue;
2127
2128                                 dma_unmap_single_attrs(&pdev->dev,
2129                                                        tpa_info->mapping,
2130                                                        bp->rx_buf_use_size,
2131                                                        bp->rx_dir,
2132                                                        DMA_ATTR_WEAK_ORDERING);
2133
2134                                 tpa_info->data = NULL;
2135
2136                                 kfree(data);
2137                         }
2138                 }
2139
2140                 for (j = 0; j < max_idx; j++) {
2141                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2142                         dma_addr_t mapping = rx_buf->mapping;
2143                         void *data = rx_buf->data;
2144
2145                         if (!data)
2146                                 continue;
2147
2148                         rx_buf->data = NULL;
2149
2150                         if (BNXT_RX_PAGE_MODE(bp)) {
2151                                 mapping -= bp->rx_dma_offset;
2152                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2153                                                      PAGE_SIZE, bp->rx_dir,
2154                                                      DMA_ATTR_WEAK_ORDERING);
2155                                 __free_page(data);
2156                         } else {
2157                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2158                                                        bp->rx_buf_use_size,
2159                                                        bp->rx_dir,
2160                                                        DMA_ATTR_WEAK_ORDERING);
2161                                 kfree(data);
2162                         }
2163                 }
2164
2165                 for (j = 0; j < max_agg_idx; j++) {
2166                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2167                                 &rxr->rx_agg_ring[j];
2168                         struct page *page = rx_agg_buf->page;
2169
2170                         if (!page)
2171                                 continue;
2172
2173                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2174                                              BNXT_RX_PAGE_SIZE,
2175                                              PCI_DMA_FROMDEVICE,
2176                                              DMA_ATTR_WEAK_ORDERING);
2177
2178                         rx_agg_buf->page = NULL;
2179                         __clear_bit(j, rxr->rx_agg_bmap);
2180
2181                         __free_page(page);
2182                 }
2183                 if (rxr->rx_page) {
2184                         __free_page(rxr->rx_page);
2185                         rxr->rx_page = NULL;
2186                 }
2187         }
2188 }
2189
2190 static void bnxt_free_skbs(struct bnxt *bp)
2191 {
2192         bnxt_free_tx_skbs(bp);
2193         bnxt_free_rx_skbs(bp);
2194 }
2195
2196 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2197 {
2198         struct pci_dev *pdev = bp->pdev;
2199         int i;
2200
2201         for (i = 0; i < ring->nr_pages; i++) {
2202                 if (!ring->pg_arr[i])
2203                         continue;
2204
2205                 dma_free_coherent(&pdev->dev, ring->page_size,
2206                                   ring->pg_arr[i], ring->dma_arr[i]);
2207
2208                 ring->pg_arr[i] = NULL;
2209         }
2210         if (ring->pg_tbl) {
2211                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2212                                   ring->pg_tbl, ring->pg_tbl_map);
2213                 ring->pg_tbl = NULL;
2214         }
2215         if (ring->vmem_size && *ring->vmem) {
2216                 vfree(*ring->vmem);
2217                 *ring->vmem = NULL;
2218         }
2219 }
2220
2221 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2222 {
2223         int i;
2224         struct pci_dev *pdev = bp->pdev;
2225
2226         if (ring->nr_pages > 1) {
2227                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2228                                                   ring->nr_pages * 8,
2229                                                   &ring->pg_tbl_map,
2230                                                   GFP_KERNEL);
2231                 if (!ring->pg_tbl)
2232                         return -ENOMEM;
2233         }
2234
2235         for (i = 0; i < ring->nr_pages; i++) {
2236                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2237                                                      ring->page_size,
2238                                                      &ring->dma_arr[i],
2239                                                      GFP_KERNEL);
2240                 if (!ring->pg_arr[i])
2241                         return -ENOMEM;
2242
2243                 if (ring->nr_pages > 1)
2244                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2245         }
2246
2247         if (ring->vmem_size) {
2248                 *ring->vmem = vzalloc(ring->vmem_size);
2249                 if (!(*ring->vmem))
2250                         return -ENOMEM;
2251         }
2252         return 0;
2253 }
2254
2255 static void bnxt_free_rx_rings(struct bnxt *bp)
2256 {
2257         int i;
2258
2259         if (!bp->rx_ring)
2260                 return;
2261
2262         for (i = 0; i < bp->rx_nr_rings; i++) {
2263                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2264                 struct bnxt_ring_struct *ring;
2265
2266                 if (rxr->xdp_prog)
2267                         bpf_prog_put(rxr->xdp_prog);
2268
2269                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2270                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2271
2272                 kfree(rxr->rx_tpa);
2273                 rxr->rx_tpa = NULL;
2274
2275                 kfree(rxr->rx_agg_bmap);
2276                 rxr->rx_agg_bmap = NULL;
2277
2278                 ring = &rxr->rx_ring_struct;
2279                 bnxt_free_ring(bp, ring);
2280
2281                 ring = &rxr->rx_agg_ring_struct;
2282                 bnxt_free_ring(bp, ring);
2283         }
2284 }
2285
2286 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2287 {
2288         int i, rc, agg_rings = 0, tpa_rings = 0;
2289
2290         if (!bp->rx_ring)
2291                 return -ENOMEM;
2292
2293         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2294                 agg_rings = 1;
2295
2296         if (bp->flags & BNXT_FLAG_TPA)
2297                 tpa_rings = 1;
2298
2299         for (i = 0; i < bp->rx_nr_rings; i++) {
2300                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2301                 struct bnxt_ring_struct *ring;
2302
2303                 ring = &rxr->rx_ring_struct;
2304
2305                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2306                 if (rc < 0)
2307                         return rc;
2308
2309                 rc = bnxt_alloc_ring(bp, ring);
2310                 if (rc)
2311                         return rc;
2312
2313                 if (agg_rings) {
2314                         u16 mem_size;
2315
2316                         ring = &rxr->rx_agg_ring_struct;
2317                         rc = bnxt_alloc_ring(bp, ring);
2318                         if (rc)
2319                                 return rc;
2320
2321                         ring->grp_idx = i;
2322                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2323                         mem_size = rxr->rx_agg_bmap_size / 8;
2324                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2325                         if (!rxr->rx_agg_bmap)
2326                                 return -ENOMEM;
2327
2328                         if (tpa_rings) {
2329                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2330                                                 sizeof(struct bnxt_tpa_info),
2331                                                 GFP_KERNEL);
2332                                 if (!rxr->rx_tpa)
2333                                         return -ENOMEM;
2334                         }
2335                 }
2336         }
2337         return 0;
2338 }
2339
2340 static void bnxt_free_tx_rings(struct bnxt *bp)
2341 {
2342         int i;
2343         struct pci_dev *pdev = bp->pdev;
2344
2345         if (!bp->tx_ring)
2346                 return;
2347
2348         for (i = 0; i < bp->tx_nr_rings; i++) {
2349                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2350                 struct bnxt_ring_struct *ring;
2351
2352                 if (txr->tx_push) {
2353                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2354                                           txr->tx_push, txr->tx_push_mapping);
2355                         txr->tx_push = NULL;
2356                 }
2357
2358                 ring = &txr->tx_ring_struct;
2359
2360                 bnxt_free_ring(bp, ring);
2361         }
2362 }
2363
2364 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2365 {
2366         int i, j, rc;
2367         struct pci_dev *pdev = bp->pdev;
2368
2369         bp->tx_push_size = 0;
2370         if (bp->tx_push_thresh) {
2371                 int push_size;
2372
2373                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2374                                         bp->tx_push_thresh);
2375
2376                 if (push_size > 256) {
2377                         push_size = 0;
2378                         bp->tx_push_thresh = 0;
2379                 }
2380
2381                 bp->tx_push_size = push_size;
2382         }
2383
2384         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2385                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2386                 struct bnxt_ring_struct *ring;
2387                 u8 qidx;
2388
2389                 ring = &txr->tx_ring_struct;
2390
2391                 rc = bnxt_alloc_ring(bp, ring);
2392                 if (rc)
2393                         return rc;
2394
2395                 ring->grp_idx = txr->bnapi->index;
2396                 if (bp->tx_push_size) {
2397                         dma_addr_t mapping;
2398
2399                         /* One pre-allocated DMA buffer to backup
2400                          * TX push operation
2401                          */
2402                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2403                                                 bp->tx_push_size,
2404                                                 &txr->tx_push_mapping,
2405                                                 GFP_KERNEL);
2406
2407                         if (!txr->tx_push)
2408                                 return -ENOMEM;
2409
2410                         mapping = txr->tx_push_mapping +
2411                                 sizeof(struct tx_push_bd);
2412                         txr->data_mapping = cpu_to_le64(mapping);
2413
2414                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2415                 }
2416                 qidx = bp->tc_to_qidx[j];
2417                 ring->queue_id = bp->q_info[qidx].queue_id;
2418                 if (i < bp->tx_nr_rings_xdp)
2419                         continue;
2420                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2421                         j++;
2422         }
2423         return 0;
2424 }
2425
2426 static void bnxt_free_cp_rings(struct bnxt *bp)
2427 {
2428         int i;
2429
2430         if (!bp->bnapi)
2431                 return;
2432
2433         for (i = 0; i < bp->cp_nr_rings; i++) {
2434                 struct bnxt_napi *bnapi = bp->bnapi[i];
2435                 struct bnxt_cp_ring_info *cpr;
2436                 struct bnxt_ring_struct *ring;
2437
2438                 if (!bnapi)
2439                         continue;
2440
2441                 cpr = &bnapi->cp_ring;
2442                 ring = &cpr->cp_ring_struct;
2443
2444                 bnxt_free_ring(bp, ring);
2445         }
2446 }
2447
2448 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2449 {
2450         int i, rc, ulp_base_vec, ulp_msix;
2451
2452         ulp_msix = bnxt_get_ulp_msix_num(bp);
2453         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2454         for (i = 0; i < bp->cp_nr_rings; i++) {
2455                 struct bnxt_napi *bnapi = bp->bnapi[i];
2456                 struct bnxt_cp_ring_info *cpr;
2457                 struct bnxt_ring_struct *ring;
2458
2459                 if (!bnapi)
2460                         continue;
2461
2462                 cpr = &bnapi->cp_ring;
2463                 ring = &cpr->cp_ring_struct;
2464
2465                 rc = bnxt_alloc_ring(bp, ring);
2466                 if (rc)
2467                         return rc;
2468
2469                 if (ulp_msix && i >= ulp_base_vec)
2470                         ring->map_idx = i + ulp_msix;
2471                 else
2472                         ring->map_idx = i;
2473         }
2474         return 0;
2475 }
2476
2477 static void bnxt_init_ring_struct(struct bnxt *bp)
2478 {
2479         int i;
2480
2481         for (i = 0; i < bp->cp_nr_rings; i++) {
2482                 struct bnxt_napi *bnapi = bp->bnapi[i];
2483                 struct bnxt_cp_ring_info *cpr;
2484                 struct bnxt_rx_ring_info *rxr;
2485                 struct bnxt_tx_ring_info *txr;
2486                 struct bnxt_ring_struct *ring;
2487
2488                 if (!bnapi)
2489                         continue;
2490
2491                 cpr = &bnapi->cp_ring;
2492                 ring = &cpr->cp_ring_struct;
2493                 ring->nr_pages = bp->cp_nr_pages;
2494                 ring->page_size = HW_CMPD_RING_SIZE;
2495                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2496                 ring->dma_arr = cpr->cp_desc_mapping;
2497                 ring->vmem_size = 0;
2498
2499                 rxr = bnapi->rx_ring;
2500                 if (!rxr)
2501                         goto skip_rx;
2502
2503                 ring = &rxr->rx_ring_struct;
2504                 ring->nr_pages = bp->rx_nr_pages;
2505                 ring->page_size = HW_RXBD_RING_SIZE;
2506                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2507                 ring->dma_arr = rxr->rx_desc_mapping;
2508                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2509                 ring->vmem = (void **)&rxr->rx_buf_ring;
2510
2511                 ring = &rxr->rx_agg_ring_struct;
2512                 ring->nr_pages = bp->rx_agg_nr_pages;
2513                 ring->page_size = HW_RXBD_RING_SIZE;
2514                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2515                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2516                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2517                 ring->vmem = (void **)&rxr->rx_agg_ring;
2518
2519 skip_rx:
2520                 txr = bnapi->tx_ring;
2521                 if (!txr)
2522                         continue;
2523
2524                 ring = &txr->tx_ring_struct;
2525                 ring->nr_pages = bp->tx_nr_pages;
2526                 ring->page_size = HW_RXBD_RING_SIZE;
2527                 ring->pg_arr = (void **)txr->tx_desc_ring;
2528                 ring->dma_arr = txr->tx_desc_mapping;
2529                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2530                 ring->vmem = (void **)&txr->tx_buf_ring;
2531         }
2532 }
2533
2534 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2535 {
2536         int i;
2537         u32 prod;
2538         struct rx_bd **rx_buf_ring;
2539
2540         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2541         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2542                 int j;
2543                 struct rx_bd *rxbd;
2544
2545                 rxbd = rx_buf_ring[i];
2546                 if (!rxbd)
2547                         continue;
2548
2549                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2550                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2551                         rxbd->rx_bd_opaque = prod;
2552                 }
2553         }
2554 }
2555
2556 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2557 {
2558         struct net_device *dev = bp->dev;
2559         struct bnxt_rx_ring_info *rxr;
2560         struct bnxt_ring_struct *ring;
2561         u32 prod, type;
2562         int i;
2563
2564         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2565                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2566
2567         if (NET_IP_ALIGN == 2)
2568                 type |= RX_BD_FLAGS_SOP;
2569
2570         rxr = &bp->rx_ring[ring_nr];
2571         ring = &rxr->rx_ring_struct;
2572         bnxt_init_rxbd_pages(ring, type);
2573
2574         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2575                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2576                 if (IS_ERR(rxr->xdp_prog)) {
2577                         int rc = PTR_ERR(rxr->xdp_prog);
2578
2579                         rxr->xdp_prog = NULL;
2580                         return rc;
2581                 }
2582         }
2583         prod = rxr->rx_prod;
2584         for (i = 0; i < bp->rx_ring_size; i++) {
2585                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2586                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2587                                     ring_nr, i, bp->rx_ring_size);
2588                         break;
2589                 }
2590                 prod = NEXT_RX(prod);
2591         }
2592         rxr->rx_prod = prod;
2593         ring->fw_ring_id = INVALID_HW_RING_ID;
2594
2595         ring = &rxr->rx_agg_ring_struct;
2596         ring->fw_ring_id = INVALID_HW_RING_ID;
2597
2598         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2599                 return 0;
2600
2601         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2602                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2603
2604         bnxt_init_rxbd_pages(ring, type);
2605
2606         prod = rxr->rx_agg_prod;
2607         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2608                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2609                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2610                                     ring_nr, i, bp->rx_ring_size);
2611                         break;
2612                 }
2613                 prod = NEXT_RX_AGG(prod);
2614         }
2615         rxr->rx_agg_prod = prod;
2616
2617         if (bp->flags & BNXT_FLAG_TPA) {
2618                 if (rxr->rx_tpa) {
2619                         u8 *data;
2620                         dma_addr_t mapping;
2621
2622                         for (i = 0; i < MAX_TPA; i++) {
2623                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2624                                                             GFP_KERNEL);
2625                                 if (!data)
2626                                         return -ENOMEM;
2627
2628                                 rxr->rx_tpa[i].data = data;
2629                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2630                                 rxr->rx_tpa[i].mapping = mapping;
2631                         }
2632                 } else {
2633                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2634                         return -ENOMEM;
2635                 }
2636         }
2637
2638         return 0;
2639 }
2640
2641 static void bnxt_init_cp_rings(struct bnxt *bp)
2642 {
2643         int i;
2644
2645         for (i = 0; i < bp->cp_nr_rings; i++) {
2646                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2647                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2648
2649                 ring->fw_ring_id = INVALID_HW_RING_ID;
2650                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2651                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2652         }
2653 }
2654
2655 static int bnxt_init_rx_rings(struct bnxt *bp)
2656 {
2657         int i, rc = 0;
2658
2659         if (BNXT_RX_PAGE_MODE(bp)) {
2660                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2661                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2662         } else {
2663                 bp->rx_offset = BNXT_RX_OFFSET;
2664                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2665         }
2666
2667         for (i = 0; i < bp->rx_nr_rings; i++) {
2668                 rc = bnxt_init_one_rx_ring(bp, i);
2669                 if (rc)
2670                         break;
2671         }
2672
2673         return rc;
2674 }
2675
2676 static int bnxt_init_tx_rings(struct bnxt *bp)
2677 {
2678         u16 i;
2679
2680         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2681                                    MAX_SKB_FRAGS + 1);
2682
2683         for (i = 0; i < bp->tx_nr_rings; i++) {
2684                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2685                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2686
2687                 ring->fw_ring_id = INVALID_HW_RING_ID;
2688         }
2689
2690         return 0;
2691 }
2692
2693 static void bnxt_free_ring_grps(struct bnxt *bp)
2694 {
2695         kfree(bp->grp_info);
2696         bp->grp_info = NULL;
2697 }
2698
2699 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2700 {
2701         int i;
2702
2703         if (irq_re_init) {
2704                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2705                                        sizeof(struct bnxt_ring_grp_info),
2706                                        GFP_KERNEL);
2707                 if (!bp->grp_info)
2708                         return -ENOMEM;
2709         }
2710         for (i = 0; i < bp->cp_nr_rings; i++) {
2711                 if (irq_re_init)
2712                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2713                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2714                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2715                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2716                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2717         }
2718         return 0;
2719 }
2720
2721 static void bnxt_free_vnics(struct bnxt *bp)
2722 {
2723         kfree(bp->vnic_info);
2724         bp->vnic_info = NULL;
2725         bp->nr_vnics = 0;
2726 }
2727
2728 static int bnxt_alloc_vnics(struct bnxt *bp)
2729 {
2730         int num_vnics = 1;
2731
2732 #ifdef CONFIG_RFS_ACCEL
2733         if (bp->flags & BNXT_FLAG_RFS)
2734                 num_vnics += bp->rx_nr_rings;
2735 #endif
2736
2737         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2738                 num_vnics++;
2739
2740         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2741                                 GFP_KERNEL);
2742         if (!bp->vnic_info)
2743                 return -ENOMEM;
2744
2745         bp->nr_vnics = num_vnics;
2746         return 0;
2747 }
2748
2749 static void bnxt_init_vnics(struct bnxt *bp)
2750 {
2751         int i;
2752
2753         for (i = 0; i < bp->nr_vnics; i++) {
2754                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2755
2756                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2757                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2758                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2759                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2760
2761                 if (bp->vnic_info[i].rss_hash_key) {
2762                         if (i == 0)
2763                                 prandom_bytes(vnic->rss_hash_key,
2764                                               HW_HASH_KEY_SIZE);
2765                         else
2766                                 memcpy(vnic->rss_hash_key,
2767                                        bp->vnic_info[0].rss_hash_key,
2768                                        HW_HASH_KEY_SIZE);
2769                 }
2770         }
2771 }
2772
2773 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2774 {
2775         int pages;
2776
2777         pages = ring_size / desc_per_pg;
2778
2779         if (!pages)
2780                 return 1;
2781
2782         pages++;
2783
2784         while (pages & (pages - 1))
2785                 pages++;
2786
2787         return pages;
2788 }
2789
2790 void bnxt_set_tpa_flags(struct bnxt *bp)
2791 {
2792         bp->flags &= ~BNXT_FLAG_TPA;
2793         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2794                 return;
2795         if (bp->dev->features & NETIF_F_LRO)
2796                 bp->flags |= BNXT_FLAG_LRO;
2797         else if (bp->dev->features & NETIF_F_GRO_HW)
2798                 bp->flags |= BNXT_FLAG_GRO;
2799 }
2800
2801 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2802  * be set on entry.
2803  */
2804 void bnxt_set_ring_params(struct bnxt *bp)
2805 {
2806         u32 ring_size, rx_size, rx_space;
2807         u32 agg_factor = 0, agg_ring_size = 0;
2808
2809         /* 8 for CRC and VLAN */
2810         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2811
2812         rx_space = rx_size + NET_SKB_PAD +
2813                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2814
2815         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2816         ring_size = bp->rx_ring_size;
2817         bp->rx_agg_ring_size = 0;
2818         bp->rx_agg_nr_pages = 0;
2819
2820         if (bp->flags & BNXT_FLAG_TPA)
2821                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2822
2823         bp->flags &= ~BNXT_FLAG_JUMBO;
2824         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2825                 u32 jumbo_factor;
2826
2827                 bp->flags |= BNXT_FLAG_JUMBO;
2828                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2829                 if (jumbo_factor > agg_factor)
2830                         agg_factor = jumbo_factor;
2831         }
2832         agg_ring_size = ring_size * agg_factor;
2833
2834         if (agg_ring_size) {
2835                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2836                                                         RX_DESC_CNT);
2837                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2838                         u32 tmp = agg_ring_size;
2839
2840                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2841                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2842                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2843                                     tmp, agg_ring_size);
2844                 }
2845                 bp->rx_agg_ring_size = agg_ring_size;
2846                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2847                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2848                 rx_space = rx_size + NET_SKB_PAD +
2849                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2850         }
2851
2852         bp->rx_buf_use_size = rx_size;
2853         bp->rx_buf_size = rx_space;
2854
2855         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2856         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2857
2858         ring_size = bp->tx_ring_size;
2859         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2860         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2861
2862         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2863         bp->cp_ring_size = ring_size;
2864
2865         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2866         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2867                 bp->cp_nr_pages = MAX_CP_PAGES;
2868                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2869                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2870                             ring_size, bp->cp_ring_size);
2871         }
2872         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2873         bp->cp_ring_mask = bp->cp_bit - 1;
2874 }
2875
2876 /* Changing allocation mode of RX rings.
2877  * TODO: Update when extending xdp_rxq_info to support allocation modes.
2878  */
2879 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2880 {
2881         if (page_mode) {
2882                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2883                         return -EOPNOTSUPP;
2884                 bp->dev->max_mtu =
2885                         min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
2886                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2887                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2888                 bp->rx_dir = DMA_BIDIRECTIONAL;
2889                 bp->rx_skb_func = bnxt_rx_page_skb;
2890                 /* Disable LRO or GRO_HW */
2891                 netdev_update_features(bp->dev);
2892         } else {
2893                 bp->dev->max_mtu = bp->max_mtu;
2894                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2895                 bp->rx_dir = DMA_FROM_DEVICE;
2896                 bp->rx_skb_func = bnxt_rx_skb;
2897         }
2898         return 0;
2899 }
2900
2901 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2902 {
2903         int i;
2904         struct bnxt_vnic_info *vnic;
2905         struct pci_dev *pdev = bp->pdev;
2906
2907         if (!bp->vnic_info)
2908                 return;
2909
2910         for (i = 0; i < bp->nr_vnics; i++) {
2911                 vnic = &bp->vnic_info[i];
2912
2913                 kfree(vnic->fw_grp_ids);
2914                 vnic->fw_grp_ids = NULL;
2915
2916                 kfree(vnic->uc_list);
2917                 vnic->uc_list = NULL;
2918
2919                 if (vnic->mc_list) {
2920                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2921                                           vnic->mc_list, vnic->mc_list_mapping);
2922                         vnic->mc_list = NULL;
2923                 }
2924
2925                 if (vnic->rss_table) {
2926                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2927                                           vnic->rss_table,
2928                                           vnic->rss_table_dma_addr);
2929                         vnic->rss_table = NULL;
2930                 }
2931
2932                 vnic->rss_hash_key = NULL;
2933                 vnic->flags = 0;
2934         }
2935 }
2936
2937 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2938 {
2939         int i, rc = 0, size;
2940         struct bnxt_vnic_info *vnic;
2941         struct pci_dev *pdev = bp->pdev;
2942         int max_rings;
2943
2944         for (i = 0; i < bp->nr_vnics; i++) {
2945                 vnic = &bp->vnic_info[i];
2946
2947                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2948                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2949
2950                         if (mem_size > 0) {
2951                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2952                                 if (!vnic->uc_list) {
2953                                         rc = -ENOMEM;
2954                                         goto out;
2955                                 }
2956                         }
2957                 }
2958
2959                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2960                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2961                         vnic->mc_list =
2962                                 dma_alloc_coherent(&pdev->dev,
2963                                                    vnic->mc_list_size,
2964                                                    &vnic->mc_list_mapping,
2965                                                    GFP_KERNEL);
2966                         if (!vnic->mc_list) {
2967                                 rc = -ENOMEM;
2968                                 goto out;
2969                         }
2970                 }
2971
2972                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2973                         max_rings = bp->rx_nr_rings;
2974                 else
2975                         max_rings = 1;
2976
2977                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2978                 if (!vnic->fw_grp_ids) {
2979                         rc = -ENOMEM;
2980                         goto out;
2981                 }
2982
2983                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2984                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2985                         continue;
2986
2987                 /* Allocate rss table and hash key */
2988                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2989                                                      &vnic->rss_table_dma_addr,
2990                                                      GFP_KERNEL);
2991                 if (!vnic->rss_table) {
2992                         rc = -ENOMEM;
2993                         goto out;
2994                 }
2995
2996                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2997
2998                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2999                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3000         }
3001         return 0;
3002
3003 out:
3004         return rc;
3005 }
3006
3007 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3008 {
3009         struct pci_dev *pdev = bp->pdev;
3010
3011         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3012                           bp->hwrm_cmd_resp_dma_addr);
3013
3014         bp->hwrm_cmd_resp_addr = NULL;
3015         if (bp->hwrm_dbg_resp_addr) {
3016                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
3017                                   bp->hwrm_dbg_resp_addr,
3018                                   bp->hwrm_dbg_resp_dma_addr);
3019
3020                 bp->hwrm_dbg_resp_addr = NULL;
3021         }
3022 }
3023
3024 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3025 {
3026         struct pci_dev *pdev = bp->pdev;
3027
3028         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3029                                                    &bp->hwrm_cmd_resp_dma_addr,
3030                                                    GFP_KERNEL);
3031         if (!bp->hwrm_cmd_resp_addr)
3032                 return -ENOMEM;
3033         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
3034                                                     HWRM_DBG_REG_BUF_SIZE,
3035                                                     &bp->hwrm_dbg_resp_dma_addr,
3036                                                     GFP_KERNEL);
3037         if (!bp->hwrm_dbg_resp_addr)
3038                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
3039
3040         return 0;
3041 }
3042
3043 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3044 {
3045         if (bp->hwrm_short_cmd_req_addr) {
3046                 struct pci_dev *pdev = bp->pdev;
3047
3048                 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3049                                   bp->hwrm_short_cmd_req_addr,
3050                                   bp->hwrm_short_cmd_req_dma_addr);
3051                 bp->hwrm_short_cmd_req_addr = NULL;
3052         }
3053 }
3054
3055 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3056 {
3057         struct pci_dev *pdev = bp->pdev;
3058
3059         bp->hwrm_short_cmd_req_addr =
3060                 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3061                                    &bp->hwrm_short_cmd_req_dma_addr,
3062                                    GFP_KERNEL);
3063         if (!bp->hwrm_short_cmd_req_addr)
3064                 return -ENOMEM;
3065
3066         return 0;
3067 }
3068
3069 static void bnxt_free_stats(struct bnxt *bp)
3070 {
3071         u32 size, i;
3072         struct pci_dev *pdev = bp->pdev;
3073
3074         bp->flags &= ~BNXT_FLAG_PORT_STATS;
3075         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3076
3077         if (bp->hw_rx_port_stats) {
3078                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3079                                   bp->hw_rx_port_stats,
3080                                   bp->hw_rx_port_stats_map);
3081                 bp->hw_rx_port_stats = NULL;
3082         }
3083
3084         if (bp->hw_rx_port_stats_ext) {
3085                 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3086                                   bp->hw_rx_port_stats_ext,
3087                                   bp->hw_rx_port_stats_ext_map);
3088                 bp->hw_rx_port_stats_ext = NULL;
3089         }
3090
3091         if (!bp->bnapi)
3092                 return;
3093
3094         size = sizeof(struct ctx_hw_stats);
3095
3096         for (i = 0; i < bp->cp_nr_rings; i++) {
3097                 struct bnxt_napi *bnapi = bp->bnapi[i];
3098                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3099
3100                 if (cpr->hw_stats) {
3101                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3102                                           cpr->hw_stats_map);
3103                         cpr->hw_stats = NULL;
3104                 }
3105         }
3106 }
3107
3108 static int bnxt_alloc_stats(struct bnxt *bp)
3109 {
3110         u32 size, i;
3111         struct pci_dev *pdev = bp->pdev;
3112
3113         size = sizeof(struct ctx_hw_stats);
3114
3115         for (i = 0; i < bp->cp_nr_rings; i++) {
3116                 struct bnxt_napi *bnapi = bp->bnapi[i];
3117                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3118
3119                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3120                                                    &cpr->hw_stats_map,
3121                                                    GFP_KERNEL);
3122                 if (!cpr->hw_stats)
3123                         return -ENOMEM;
3124
3125                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3126         }
3127
3128         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3129                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3130                                          sizeof(struct tx_port_stats) + 1024;
3131
3132                 bp->hw_rx_port_stats =
3133                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3134                                            &bp->hw_rx_port_stats_map,
3135                                            GFP_KERNEL);
3136                 if (!bp->hw_rx_port_stats)
3137                         return -ENOMEM;
3138
3139                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3140                                        512;
3141                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3142                                            sizeof(struct rx_port_stats) + 512;
3143                 bp->flags |= BNXT_FLAG_PORT_STATS;
3144
3145                 /* Display extended statistics only if FW supports it */
3146                 if (bp->hwrm_spec_code < 0x10804 ||
3147                     bp->hwrm_spec_code == 0x10900)
3148                         return 0;
3149
3150                 bp->hw_rx_port_stats_ext =
3151                         dma_zalloc_coherent(&pdev->dev,
3152                                             sizeof(struct rx_port_stats_ext),
3153                                             &bp->hw_rx_port_stats_ext_map,
3154                                             GFP_KERNEL);
3155                 if (!bp->hw_rx_port_stats_ext)
3156                         return 0;
3157
3158                 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3159         }
3160         return 0;
3161 }
3162
3163 static void bnxt_clear_ring_indices(struct bnxt *bp)
3164 {
3165         int i;
3166
3167         if (!bp->bnapi)
3168                 return;
3169
3170         for (i = 0; i < bp->cp_nr_rings; i++) {
3171                 struct bnxt_napi *bnapi = bp->bnapi[i];
3172                 struct bnxt_cp_ring_info *cpr;
3173                 struct bnxt_rx_ring_info *rxr;
3174                 struct bnxt_tx_ring_info *txr;
3175
3176                 if (!bnapi)
3177                         continue;
3178
3179                 cpr = &bnapi->cp_ring;
3180                 cpr->cp_raw_cons = 0;
3181
3182                 txr = bnapi->tx_ring;
3183                 if (txr) {
3184                         txr->tx_prod = 0;
3185                         txr->tx_cons = 0;
3186                 }
3187
3188                 rxr = bnapi->rx_ring;
3189                 if (rxr) {
3190                         rxr->rx_prod = 0;
3191                         rxr->rx_agg_prod = 0;
3192                         rxr->rx_sw_agg_prod = 0;
3193                         rxr->rx_next_cons = 0;
3194                 }
3195         }
3196 }
3197
3198 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3199 {
3200 #ifdef CONFIG_RFS_ACCEL
3201         int i;
3202
3203         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3204          * safe to delete the hash table.
3205          */
3206         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3207                 struct hlist_head *head;
3208                 struct hlist_node *tmp;
3209                 struct bnxt_ntuple_filter *fltr;
3210
3211                 head = &bp->ntp_fltr_hash_tbl[i];
3212                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3213                         hlist_del(&fltr->hash);
3214                         kfree(fltr);
3215                 }
3216         }
3217         if (irq_reinit) {
3218                 kfree(bp->ntp_fltr_bmap);
3219                 bp->ntp_fltr_bmap = NULL;
3220         }
3221         bp->ntp_fltr_count = 0;
3222 #endif
3223 }
3224
3225 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3226 {
3227 #ifdef CONFIG_RFS_ACCEL
3228         int i, rc = 0;
3229
3230         if (!(bp->flags & BNXT_FLAG_RFS))
3231                 return 0;
3232
3233         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3234                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3235
3236         bp->ntp_fltr_count = 0;
3237         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3238                                     sizeof(long),
3239                                     GFP_KERNEL);
3240
3241         if (!bp->ntp_fltr_bmap)
3242                 rc = -ENOMEM;
3243
3244         return rc;
3245 #else
3246         return 0;
3247 #endif
3248 }
3249
3250 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3251 {
3252         bnxt_free_vnic_attributes(bp);
3253         bnxt_free_tx_rings(bp);
3254         bnxt_free_rx_rings(bp);
3255         bnxt_free_cp_rings(bp);
3256         bnxt_free_ntp_fltrs(bp, irq_re_init);
3257         if (irq_re_init) {
3258                 bnxt_free_stats(bp);
3259                 bnxt_free_ring_grps(bp);
3260                 bnxt_free_vnics(bp);
3261                 kfree(bp->tx_ring_map);
3262                 bp->tx_ring_map = NULL;
3263                 kfree(bp->tx_ring);
3264                 bp->tx_ring = NULL;
3265                 kfree(bp->rx_ring);
3266                 bp->rx_ring = NULL;
3267                 kfree(bp->bnapi);
3268                 bp->bnapi = NULL;
3269         } else {
3270                 bnxt_clear_ring_indices(bp);
3271         }
3272 }
3273
3274 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3275 {
3276         int i, j, rc, size, arr_size;
3277         void *bnapi;
3278
3279         if (irq_re_init) {
3280                 /* Allocate bnapi mem pointer array and mem block for
3281                  * all queues
3282                  */
3283                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3284                                 bp->cp_nr_rings);
3285                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3286                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3287                 if (!bnapi)
3288                         return -ENOMEM;
3289
3290                 bp->bnapi = bnapi;
3291                 bnapi += arr_size;
3292                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3293                         bp->bnapi[i] = bnapi;
3294                         bp->bnapi[i]->index = i;
3295                         bp->bnapi[i]->bp = bp;
3296                 }
3297
3298                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3299                                       sizeof(struct bnxt_rx_ring_info),
3300                                       GFP_KERNEL);
3301                 if (!bp->rx_ring)
3302                         return -ENOMEM;
3303
3304                 for (i = 0; i < bp->rx_nr_rings; i++) {
3305                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3306                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3307                 }
3308
3309                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3310                                       sizeof(struct bnxt_tx_ring_info),
3311                                       GFP_KERNEL);
3312                 if (!bp->tx_ring)
3313                         return -ENOMEM;
3314
3315                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3316                                           GFP_KERNEL);
3317
3318                 if (!bp->tx_ring_map)
3319                         return -ENOMEM;
3320
3321                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3322                         j = 0;
3323                 else
3324                         j = bp->rx_nr_rings;
3325
3326                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3327                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3328                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3329                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3330                         if (i >= bp->tx_nr_rings_xdp) {
3331                                 bp->tx_ring[i].txq_index = i -
3332                                         bp->tx_nr_rings_xdp;
3333                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3334                         } else {
3335                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3336                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3337                         }
3338                 }
3339
3340                 rc = bnxt_alloc_stats(bp);
3341                 if (rc)
3342                         goto alloc_mem_err;
3343
3344                 rc = bnxt_alloc_ntp_fltrs(bp);
3345                 if (rc)
3346                         goto alloc_mem_err;
3347
3348                 rc = bnxt_alloc_vnics(bp);
3349                 if (rc)
3350                         goto alloc_mem_err;
3351         }
3352
3353         bnxt_init_ring_struct(bp);
3354
3355         rc = bnxt_alloc_rx_rings(bp);
3356         if (rc)
3357                 goto alloc_mem_err;
3358
3359         rc = bnxt_alloc_tx_rings(bp);
3360         if (rc)
3361                 goto alloc_mem_err;
3362
3363         rc = bnxt_alloc_cp_rings(bp);
3364         if (rc)
3365                 goto alloc_mem_err;
3366
3367         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3368                                   BNXT_VNIC_UCAST_FLAG;
3369         rc = bnxt_alloc_vnic_attributes(bp);
3370         if (rc)
3371                 goto alloc_mem_err;
3372         return 0;
3373
3374 alloc_mem_err:
3375         bnxt_free_mem(bp, true);
3376         return rc;
3377 }
3378
3379 static void bnxt_disable_int(struct bnxt *bp)
3380 {
3381         int i;
3382
3383         if (!bp->bnapi)
3384                 return;
3385
3386         for (i = 0; i < bp->cp_nr_rings; i++) {
3387                 struct bnxt_napi *bnapi = bp->bnapi[i];
3388                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3389                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3390
3391                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3392                         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3393         }
3394 }
3395
3396 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3397 {
3398         struct bnxt_napi *bnapi = bp->bnapi[n];
3399         struct bnxt_cp_ring_info *cpr;
3400
3401         cpr = &bnapi->cp_ring;
3402         return cpr->cp_ring_struct.map_idx;
3403 }
3404
3405 static void bnxt_disable_int_sync(struct bnxt *bp)
3406 {
3407         int i;
3408
3409         atomic_inc(&bp->intr_sem);
3410
3411         bnxt_disable_int(bp);
3412         for (i = 0; i < bp->cp_nr_rings; i++) {
3413                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3414
3415                 synchronize_irq(bp->irq_tbl[map_idx].vector);
3416         }
3417 }
3418
3419 static void bnxt_enable_int(struct bnxt *bp)
3420 {
3421         int i;
3422
3423         atomic_set(&bp->intr_sem, 0);
3424         for (i = 0; i < bp->cp_nr_rings; i++) {
3425                 struct bnxt_napi *bnapi = bp->bnapi[i];
3426                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3427
3428                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3429         }
3430 }
3431
3432 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3433                             u16 cmpl_ring, u16 target_id)
3434 {
3435         struct input *req = request;
3436
3437         req->req_type = cpu_to_le16(req_type);
3438         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3439         req->target_id = cpu_to_le16(target_id);
3440         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3441 }
3442
3443 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3444                                  int timeout, bool silent)
3445 {
3446         int i, intr_process, rc, tmo_count;
3447         struct input *req = msg;
3448         u32 *data = msg;
3449         __le32 *resp_len;
3450         u8 *valid;
3451         u16 cp_ring_id, len = 0;
3452         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3453         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3454         struct hwrm_short_input short_input = {0};
3455
3456         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3457         memset(resp, 0, PAGE_SIZE);
3458         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3459         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3460
3461         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3462                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3463
3464                 memcpy(short_cmd_req, req, msg_len);
3465                 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3466                                                    msg_len);
3467
3468                 short_input.req_type = req->req_type;
3469                 short_input.signature =
3470                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3471                 short_input.size = cpu_to_le16(msg_len);
3472                 short_input.req_addr =
3473                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3474
3475                 data = (u32 *)&short_input;
3476                 msg_len = sizeof(short_input);
3477
3478                 /* Sync memory write before updating doorbell */
3479                 wmb();
3480
3481                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3482         }
3483
3484         /* Write request msg to hwrm channel */
3485         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3486
3487         for (i = msg_len; i < max_req_len; i += 4)
3488                 writel(0, bp->bar0 + i);
3489
3490         /* currently supports only one outstanding message */
3491         if (intr_process)
3492                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3493
3494         /* Ring channel doorbell */
3495         writel(1, bp->bar0 + 0x100);
3496
3497         if (!timeout)
3498                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3499         /* convert timeout to usec */
3500         timeout *= 1000;
3501
3502         i = 0;
3503         /* Short timeout for the first few iterations:
3504          * number of loops = number of loops for short timeout +
3505          * number of loops for standard timeout.
3506          */
3507         tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3508         timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3509         tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3510         resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3511         if (intr_process) {
3512                 /* Wait until hwrm response cmpl interrupt is processed */
3513                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3514                        i++ < tmo_count) {
3515                         /* on first few passes, just barely sleep */
3516                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3517                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3518                                              HWRM_SHORT_MAX_TIMEOUT);
3519                         else
3520                                 usleep_range(HWRM_MIN_TIMEOUT,
3521                                              HWRM_MAX_TIMEOUT);
3522                 }
3523
3524                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3525                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3526                                    le16_to_cpu(req->req_type));
3527                         return -1;
3528                 }
3529                 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3530                       HWRM_RESP_LEN_SFT;
3531                 valid = bp->hwrm_cmd_resp_addr + len - 1;
3532         } else {
3533                 /* Check if response len is updated */
3534                 for (i = 0; i < tmo_count; i++) {
3535                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3536                               HWRM_RESP_LEN_SFT;
3537                         if (len)
3538                                 break;
3539                         /* on first few passes, just barely sleep */
3540                         if (i < DFLT_HWRM_CMD_TIMEOUT)
3541                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3542                                              HWRM_SHORT_MAX_TIMEOUT);
3543                         else
3544                                 usleep_range(HWRM_MIN_TIMEOUT,
3545                                              HWRM_MAX_TIMEOUT);
3546                 }
3547
3548                 if (i >= tmo_count) {
3549                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3550                                    timeout, le16_to_cpu(req->req_type),
3551                                    le16_to_cpu(req->seq_id), len);
3552                         return -1;
3553                 }
3554
3555                 /* Last byte of resp contains valid bit */
3556                 valid = bp->hwrm_cmd_resp_addr + len - 1;
3557                 for (i = 0; i < 5; i++) {
3558                         /* make sure we read from updated DMA memory */
3559                         dma_rmb();
3560                         if (*valid)
3561                                 break;
3562                         udelay(1);
3563                 }
3564
3565                 if (i >= 5) {
3566                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3567                                    timeout, le16_to_cpu(req->req_type),
3568                                    le16_to_cpu(req->seq_id), len, *valid);
3569                         return -1;
3570                 }
3571         }
3572
3573         /* Zero valid bit for compatibility.  Valid bit in an older spec
3574          * may become a new field in a newer spec.  We must make sure that
3575          * a new field not implemented by old spec will read zero.
3576          */
3577         *valid = 0;
3578         rc = le16_to_cpu(resp->error_code);
3579         if (rc && !silent)
3580                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3581                            le16_to_cpu(resp->req_type),
3582                            le16_to_cpu(resp->seq_id), rc);
3583         return rc;
3584 }
3585
3586 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3587 {
3588         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3589 }
3590
3591 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3592                               int timeout)
3593 {
3594         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3595 }
3596
3597 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3598 {
3599         int rc;
3600
3601         mutex_lock(&bp->hwrm_cmd_lock);
3602         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3603         mutex_unlock(&bp->hwrm_cmd_lock);
3604         return rc;
3605 }
3606
3607 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3608                              int timeout)
3609 {
3610         int rc;
3611
3612         mutex_lock(&bp->hwrm_cmd_lock);
3613         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3614         mutex_unlock(&bp->hwrm_cmd_lock);
3615         return rc;
3616 }
3617
3618 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3619                                      int bmap_size)
3620 {
3621         struct hwrm_func_drv_rgtr_input req = {0};
3622         DECLARE_BITMAP(async_events_bmap, 256);
3623         u32 *events = (u32 *)async_events_bmap;
3624         int i;
3625
3626         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3627
3628         req.enables =
3629                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3630
3631         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3632         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3633                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3634
3635         if (bmap && bmap_size) {
3636                 for (i = 0; i < bmap_size; i++) {
3637                         if (test_bit(i, bmap))
3638                                 __set_bit(i, async_events_bmap);
3639                 }
3640         }
3641
3642         for (i = 0; i < 8; i++)
3643                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3644
3645         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3646 }
3647
3648 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3649 {
3650         struct hwrm_func_drv_rgtr_input req = {0};
3651
3652         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3653
3654         req.enables =
3655                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3656                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3657
3658         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3659         req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
3660         req.ver_maj_8b = DRV_VER_MAJ;
3661         req.ver_min_8b = DRV_VER_MIN;
3662         req.ver_upd_8b = DRV_VER_UPD;
3663         req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
3664         req.ver_min = cpu_to_le16(DRV_VER_MIN);
3665         req.ver_upd = cpu_to_le16(DRV_VER_UPD);
3666
3667         if (BNXT_PF(bp)) {
3668                 u32 data[8];
3669                 int i;
3670
3671                 memset(data, 0, sizeof(data));
3672                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3673                         u16 cmd = bnxt_vf_req_snif[i];
3674                         unsigned int bit, idx;
3675
3676                         idx = cmd / 32;
3677                         bit = cmd % 32;
3678                         data[idx] |= 1 << bit;
3679                 }
3680
3681                 for (i = 0; i < 8; i++)
3682                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3683
3684                 req.enables |=
3685                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3686         }
3687
3688         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3689 }
3690
3691 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3692 {
3693         struct hwrm_func_drv_unrgtr_input req = {0};
3694
3695         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3696         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3697 }
3698
3699 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3700 {
3701         u32 rc = 0;
3702         struct hwrm_tunnel_dst_port_free_input req = {0};
3703
3704         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3705         req.tunnel_type = tunnel_type;
3706
3707         switch (tunnel_type) {
3708         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3709                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3710                 break;
3711         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3712                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3713                 break;
3714         default:
3715                 break;
3716         }
3717
3718         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3719         if (rc)
3720                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3721                            rc);
3722         return rc;
3723 }
3724
3725 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3726                                            u8 tunnel_type)
3727 {
3728         u32 rc = 0;
3729         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3730         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3731
3732         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3733
3734         req.tunnel_type = tunnel_type;
3735         req.tunnel_dst_port_val = port;
3736
3737         mutex_lock(&bp->hwrm_cmd_lock);
3738         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3739         if (rc) {
3740                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3741                            rc);
3742                 goto err_out;
3743         }
3744
3745         switch (tunnel_type) {
3746         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3747                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3748                 break;
3749         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3750                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3751                 break;
3752         default:
3753                 break;
3754         }
3755
3756 err_out:
3757         mutex_unlock(&bp->hwrm_cmd_lock);
3758         return rc;
3759 }
3760
3761 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3762 {
3763         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3764         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3765
3766         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3767         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3768
3769         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3770         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3771         req.mask = cpu_to_le32(vnic->rx_mask);
3772         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3773 }
3774
3775 #ifdef CONFIG_RFS_ACCEL
3776 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3777                                             struct bnxt_ntuple_filter *fltr)
3778 {
3779         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3780
3781         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3782         req.ntuple_filter_id = fltr->filter_id;
3783         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3784 }
3785
3786 #define BNXT_NTP_FLTR_FLAGS                                     \
3787         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3788          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3789          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3790          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3791          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3792          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3793          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3794          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3795          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3796          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3797          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3798          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3799          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3800          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3801
3802 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
3803                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3804
3805 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3806                                              struct bnxt_ntuple_filter *fltr)
3807 {
3808         int rc = 0;
3809         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3810         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3811                 bp->hwrm_cmd_resp_addr;
3812         struct flow_keys *keys = &fltr->fkeys;
3813         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3814
3815         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3816         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3817
3818         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3819
3820         req.ethertype = htons(ETH_P_IP);
3821         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3822         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3823         req.ip_protocol = keys->basic.ip_proto;
3824
3825         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3826                 int i;
3827
3828                 req.ethertype = htons(ETH_P_IPV6);
3829                 req.ip_addr_type =
3830                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3831                 *(struct in6_addr *)&req.src_ipaddr[0] =
3832                         keys->addrs.v6addrs.src;
3833                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3834                         keys->addrs.v6addrs.dst;
3835                 for (i = 0; i < 4; i++) {
3836                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3837                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3838                 }
3839         } else {
3840                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3841                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3842                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3843                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3844         }
3845         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3846                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3847                 req.tunnel_type =
3848                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3849         }
3850
3851         req.src_port = keys->ports.src;
3852         req.src_port_mask = cpu_to_be16(0xffff);
3853         req.dst_port = keys->ports.dst;
3854         req.dst_port_mask = cpu_to_be16(0xffff);
3855
3856         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3857         mutex_lock(&bp->hwrm_cmd_lock);
3858         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3859         if (!rc)
3860                 fltr->filter_id = resp->ntuple_filter_id;
3861         mutex_unlock(&bp->hwrm_cmd_lock);
3862         return rc;
3863 }
3864 #endif
3865
3866 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3867                                      u8 *mac_addr)
3868 {
3869         u32 rc = 0;
3870         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3871         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3872
3873         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3874         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3875         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3876                 req.flags |=
3877                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3878         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3879         req.enables =
3880                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3881                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3882                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3883         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3884         req.l2_addr_mask[0] = 0xff;
3885         req.l2_addr_mask[1] = 0xff;
3886         req.l2_addr_mask[2] = 0xff;
3887         req.l2_addr_mask[3] = 0xff;
3888         req.l2_addr_mask[4] = 0xff;
3889         req.l2_addr_mask[5] = 0xff;
3890
3891         mutex_lock(&bp->hwrm_cmd_lock);
3892         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3893         if (!rc)
3894                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3895                                                         resp->l2_filter_id;
3896         mutex_unlock(&bp->hwrm_cmd_lock);
3897         return rc;
3898 }
3899
3900 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3901 {
3902         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3903         int rc = 0;
3904
3905         /* Any associated ntuple filters will also be cleared by firmware. */
3906         mutex_lock(&bp->hwrm_cmd_lock);
3907         for (i = 0; i < num_of_vnics; i++) {
3908                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3909
3910                 for (j = 0; j < vnic->uc_filter_count; j++) {
3911                         struct hwrm_cfa_l2_filter_free_input req = {0};
3912
3913                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3914                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3915
3916                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3917
3918                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3919                                                 HWRM_CMD_TIMEOUT);
3920                 }
3921                 vnic->uc_filter_count = 0;
3922         }
3923         mutex_unlock(&bp->hwrm_cmd_lock);
3924
3925         return rc;
3926 }
3927
3928 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3929 {
3930         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3931         struct hwrm_vnic_tpa_cfg_input req = {0};
3932
3933         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
3934                 return 0;
3935
3936         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3937
3938         if (tpa_flags) {
3939                 u16 mss = bp->dev->mtu - 40;
3940                 u32 nsegs, n, segs = 0, flags;
3941
3942                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3943                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3944                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3945                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3946                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3947                 if (tpa_flags & BNXT_FLAG_GRO)
3948                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3949
3950                 req.flags = cpu_to_le32(flags);
3951
3952                 req.enables =
3953                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3954                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3955                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3956
3957                 /* Number of segs are log2 units, and first packet is not
3958                  * included as part of this units.
3959                  */
3960                 if (mss <= BNXT_RX_PAGE_SIZE) {
3961                         n = BNXT_RX_PAGE_SIZE / mss;
3962                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3963                 } else {
3964                         n = mss / BNXT_RX_PAGE_SIZE;
3965                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3966                                 n++;
3967                         nsegs = (MAX_SKB_FRAGS - n) / n;
3968                 }
3969
3970                 segs = ilog2(nsegs);
3971                 req.max_agg_segs = cpu_to_le16(segs);
3972                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3973
3974                 req.min_agg_len = cpu_to_le32(512);
3975         }
3976         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3977
3978         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3979 }
3980
3981 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3982 {
3983         u32 i, j, max_rings;
3984         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3985         struct hwrm_vnic_rss_cfg_input req = {0};
3986
3987         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3988                 return 0;
3989
3990         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3991         if (set_rss) {
3992                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3993                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3994                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3995                                 max_rings = bp->rx_nr_rings - 1;
3996                         else
3997                                 max_rings = bp->rx_nr_rings;
3998                 } else {
3999                         max_rings = 1;
4000                 }
4001
4002                 /* Fill the RSS indirection table with ring group ids */
4003                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4004                         if (j == max_rings)
4005                                 j = 0;
4006                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4007                 }
4008
4009                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4010                 req.hash_key_tbl_addr =
4011                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
4012         }
4013         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4014         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4015 }
4016
4017 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4018 {
4019         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4020         struct hwrm_vnic_plcmodes_cfg_input req = {0};
4021
4022         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4023         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4024                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4025                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4026         req.enables =
4027                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4028                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4029         /* thresholds not implemented in firmware yet */
4030         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4031         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4032         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4033         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4034 }
4035
4036 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4037                                         u16 ctx_idx)
4038 {
4039         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4040
4041         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4042         req.rss_cos_lb_ctx_id =
4043                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4044
4045         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4046         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4047 }
4048
4049 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4050 {
4051         int i, j;
4052
4053         for (i = 0; i < bp->nr_vnics; i++) {
4054                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4055
4056                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4057                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4058                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4059                 }
4060         }
4061         bp->rsscos_nr_ctxs = 0;
4062 }
4063
4064 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4065 {
4066         int rc;
4067         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4068         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4069                                                 bp->hwrm_cmd_resp_addr;
4070
4071         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4072                                -1);
4073
4074         mutex_lock(&bp->hwrm_cmd_lock);
4075         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4076         if (!rc)
4077                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4078                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
4079         mutex_unlock(&bp->hwrm_cmd_lock);
4080
4081         return rc;
4082 }
4083
4084 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4085 {
4086         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4087                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4088         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4089 }
4090
4091 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4092 {
4093         unsigned int ring = 0, grp_idx;
4094         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4095         struct hwrm_vnic_cfg_input req = {0};
4096         u16 def_vlan = 0;
4097
4098         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4099
4100         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4101         /* Only RSS support for now TBD: COS & LB */
4102         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4103                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4104                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4105                                            VNIC_CFG_REQ_ENABLES_MRU);
4106         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4107                 req.rss_rule =
4108                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4109                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4110                                            VNIC_CFG_REQ_ENABLES_MRU);
4111                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4112         } else {
4113                 req.rss_rule = cpu_to_le16(0xffff);
4114         }
4115
4116         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4117             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4118                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4119                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4120         } else {
4121                 req.cos_rule = cpu_to_le16(0xffff);
4122         }
4123
4124         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4125                 ring = 0;
4126         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4127                 ring = vnic_id - 1;
4128         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4129                 ring = bp->rx_nr_rings - 1;
4130
4131         grp_idx = bp->rx_ring[ring].bnapi->index;
4132         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4133         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4134
4135         req.lb_rule = cpu_to_le16(0xffff);
4136         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4137                               VLAN_HLEN);
4138
4139 #ifdef CONFIG_BNXT_SRIOV
4140         if (BNXT_VF(bp))
4141                 def_vlan = bp->vf.vlan;
4142 #endif
4143         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4144                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4145         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4146                 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4147
4148         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4149 }
4150
4151 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4152 {
4153         u32 rc = 0;
4154
4155         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4156                 struct hwrm_vnic_free_input req = {0};
4157
4158                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4159                 req.vnic_id =
4160                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4161
4162                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4163                 if (rc)
4164                         return rc;
4165                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4166         }
4167         return rc;
4168 }
4169
4170 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4171 {
4172         u16 i;
4173
4174         for (i = 0; i < bp->nr_vnics; i++)
4175                 bnxt_hwrm_vnic_free_one(bp, i);
4176 }
4177
4178 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4179                                 unsigned int start_rx_ring_idx,
4180                                 unsigned int nr_rings)
4181 {
4182         int rc = 0;
4183         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4184         struct hwrm_vnic_alloc_input req = {0};
4185         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4186
4187         /* map ring groups to this vnic */
4188         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4189                 grp_idx = bp->rx_ring[i].bnapi->index;
4190                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4191                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4192                                    j, nr_rings);
4193                         break;
4194                 }
4195                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4196                                         bp->grp_info[grp_idx].fw_grp_id;
4197         }
4198
4199         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4200         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4201         if (vnic_id == 0)
4202                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4203
4204         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4205
4206         mutex_lock(&bp->hwrm_cmd_lock);
4207         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4208         if (!rc)
4209                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4210         mutex_unlock(&bp->hwrm_cmd_lock);
4211         return rc;
4212 }
4213
4214 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4215 {
4216         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4217         struct hwrm_vnic_qcaps_input req = {0};
4218         int rc;
4219
4220         if (bp->hwrm_spec_code < 0x10600)
4221                 return 0;
4222
4223         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4224         mutex_lock(&bp->hwrm_cmd_lock);
4225         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4226         if (!rc) {
4227                 u32 flags = le32_to_cpu(resp->flags);
4228
4229                 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)
4230                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4231                 if (flags &
4232                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4233                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4234         }
4235         mutex_unlock(&bp->hwrm_cmd_lock);
4236         return rc;
4237 }
4238
4239 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4240 {
4241         u16 i;
4242         u32 rc = 0;
4243
4244         mutex_lock(&bp->hwrm_cmd_lock);
4245         for (i = 0; i < bp->rx_nr_rings; i++) {
4246                 struct hwrm_ring_grp_alloc_input req = {0};
4247                 struct hwrm_ring_grp_alloc_output *resp =
4248                                         bp->hwrm_cmd_resp_addr;
4249                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4250
4251                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4252
4253                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4254                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4255                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4256                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4257
4258                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4259                                         HWRM_CMD_TIMEOUT);
4260                 if (rc)
4261                         break;
4262
4263                 bp->grp_info[grp_idx].fw_grp_id =
4264                         le32_to_cpu(resp->ring_group_id);
4265         }
4266         mutex_unlock(&bp->hwrm_cmd_lock);
4267         return rc;
4268 }
4269
4270 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4271 {
4272         u16 i;
4273         u32 rc = 0;
4274         struct hwrm_ring_grp_free_input req = {0};
4275
4276         if (!bp->grp_info)
4277                 return 0;
4278
4279         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4280
4281         mutex_lock(&bp->hwrm_cmd_lock);
4282         for (i = 0; i < bp->cp_nr_rings; i++) {
4283                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4284                         continue;
4285                 req.ring_group_id =
4286                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4287
4288                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4289                                         HWRM_CMD_TIMEOUT);
4290                 if (rc)
4291                         break;
4292                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4293         }
4294         mutex_unlock(&bp->hwrm_cmd_lock);
4295         return rc;
4296 }
4297
4298 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4299                                     struct bnxt_ring_struct *ring,
4300                                     u32 ring_type, u32 map_index)
4301 {
4302         int rc = 0, err = 0;
4303         struct hwrm_ring_alloc_input req = {0};
4304         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4305         struct bnxt_ring_grp_info *grp_info;
4306         u16 ring_id;
4307
4308         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4309
4310         req.enables = 0;
4311         if (ring->nr_pages > 1) {
4312                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4313                 /* Page size is in log2 units */
4314                 req.page_size = BNXT_PAGE_SHIFT;
4315                 req.page_tbl_depth = 1;
4316         } else {
4317                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
4318         }
4319         req.fbo = 0;
4320         /* Association of ring index with doorbell index and MSIX number */
4321         req.logical_id = cpu_to_le16(map_index);
4322
4323         switch (ring_type) {
4324         case HWRM_RING_ALLOC_TX:
4325                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4326                 /* Association of transmit ring with completion ring */
4327                 grp_info = &bp->grp_info[ring->grp_idx];
4328                 req.cmpl_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4329                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4330                 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4331                 req.queue_id = cpu_to_le16(ring->queue_id);
4332                 break;
4333         case HWRM_RING_ALLOC_RX:
4334                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4335                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4336                 break;
4337         case HWRM_RING_ALLOC_AGG:
4338                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4339                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4340                 break;
4341         case HWRM_RING_ALLOC_CMPL:
4342                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4343                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4344                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4345                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4346                 break;
4347         default:
4348                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4349                            ring_type);
4350                 return -1;
4351         }
4352
4353         mutex_lock(&bp->hwrm_cmd_lock);
4354         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4355         err = le16_to_cpu(resp->error_code);
4356         ring_id = le16_to_cpu(resp->ring_id);
4357         mutex_unlock(&bp->hwrm_cmd_lock);
4358
4359         if (rc || err) {
4360                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4361                            ring_type, rc, err);
4362                 return -EIO;
4363         }
4364         ring->fw_ring_id = ring_id;
4365         return rc;
4366 }
4367
4368 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4369 {
4370         int rc;
4371
4372         if (BNXT_PF(bp)) {
4373                 struct hwrm_func_cfg_input req = {0};
4374
4375                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4376                 req.fid = cpu_to_le16(0xffff);
4377                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4378                 req.async_event_cr = cpu_to_le16(idx);
4379                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4380         } else {
4381                 struct hwrm_func_vf_cfg_input req = {0};
4382
4383                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4384                 req.enables =
4385                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4386                 req.async_event_cr = cpu_to_le16(idx);
4387                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4388         }
4389         return rc;
4390 }
4391
4392 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4393 {
4394         int i, rc = 0;
4395
4396         for (i = 0; i < bp->cp_nr_rings; i++) {
4397                 struct bnxt_napi *bnapi = bp->bnapi[i];
4398                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4399                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4400                 u32 map_idx = ring->map_idx;
4401
4402                 cpr->cp_doorbell = bp->bar1 + map_idx * 0x80;
4403                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL,
4404                                               map_idx);
4405                 if (rc)
4406                         goto err_out;
4407                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4408                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4409
4410                 if (!i) {
4411                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4412                         if (rc)
4413                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4414                 }
4415         }
4416
4417         for (i = 0; i < bp->tx_nr_rings; i++) {
4418                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4419                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4420                 u32 map_idx = i;
4421
4422                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4423                                               map_idx);
4424                 if (rc)
4425                         goto err_out;
4426                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4427         }
4428
4429         for (i = 0; i < bp->rx_nr_rings; i++) {
4430                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4431                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4432                 u32 map_idx = rxr->bnapi->index;
4433
4434                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4435                                               map_idx);
4436                 if (rc)
4437                         goto err_out;
4438                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4439                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4440                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4441         }
4442
4443         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4444                 for (i = 0; i < bp->rx_nr_rings; i++) {
4445                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4446                         struct bnxt_ring_struct *ring =
4447                                                 &rxr->rx_agg_ring_struct;
4448                         u32 grp_idx = ring->grp_idx;
4449                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4450
4451                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4452                                                       HWRM_RING_ALLOC_AGG,
4453                                                       map_idx);
4454                         if (rc)
4455                                 goto err_out;
4456
4457                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4458                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4459                                rxr->rx_agg_doorbell);
4460                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4461                 }
4462         }
4463 err_out:
4464         return rc;
4465 }
4466
4467 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4468                                    struct bnxt_ring_struct *ring,
4469                                    u32 ring_type, int cmpl_ring_id)
4470 {
4471         int rc;
4472         struct hwrm_ring_free_input req = {0};
4473         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4474         u16 error_code;
4475
4476         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4477         req.ring_type = ring_type;
4478         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4479
4480         mutex_lock(&bp->hwrm_cmd_lock);
4481         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4482         error_code = le16_to_cpu(resp->error_code);
4483         mutex_unlock(&bp->hwrm_cmd_lock);
4484
4485         if (rc || error_code) {
4486                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
4487                            ring_type, rc, error_code);
4488                 return -EIO;
4489         }
4490         return 0;
4491 }
4492
4493 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4494 {
4495         int i;
4496
4497         if (!bp->bnapi)
4498                 return;
4499
4500         for (i = 0; i < bp->tx_nr_rings; i++) {
4501                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4502                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4503                 u32 grp_idx = txr->bnapi->index;
4504                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4505
4506                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4507                         hwrm_ring_free_send_msg(bp, ring,
4508                                                 RING_FREE_REQ_RING_TYPE_TX,
4509                                                 close_path ? cmpl_ring_id :
4510                                                 INVALID_HW_RING_ID);
4511                         ring->fw_ring_id = INVALID_HW_RING_ID;
4512                 }
4513         }
4514
4515         for (i = 0; i < bp->rx_nr_rings; i++) {
4516                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4517                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4518                 u32 grp_idx = rxr->bnapi->index;
4519                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4520
4521                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4522                         hwrm_ring_free_send_msg(bp, ring,
4523                                                 RING_FREE_REQ_RING_TYPE_RX,
4524                                                 close_path ? cmpl_ring_id :
4525                                                 INVALID_HW_RING_ID);
4526                         ring->fw_ring_id = INVALID_HW_RING_ID;
4527                         bp->grp_info[grp_idx].rx_fw_ring_id =
4528                                 INVALID_HW_RING_ID;
4529                 }
4530         }
4531
4532         for (i = 0; i < bp->rx_nr_rings; i++) {
4533                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4534                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4535                 u32 grp_idx = rxr->bnapi->index;
4536                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4537
4538                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4539                         hwrm_ring_free_send_msg(bp, ring,
4540                                                 RING_FREE_REQ_RING_TYPE_RX,
4541                                                 close_path ? cmpl_ring_id :
4542                                                 INVALID_HW_RING_ID);
4543                         ring->fw_ring_id = INVALID_HW_RING_ID;
4544                         bp->grp_info[grp_idx].agg_fw_ring_id =
4545                                 INVALID_HW_RING_ID;
4546                 }
4547         }
4548
4549         /* The completion rings are about to be freed.  After that the
4550          * IRQ doorbell will not work anymore.  So we need to disable
4551          * IRQ here.
4552          */
4553         bnxt_disable_int_sync(bp);
4554
4555         for (i = 0; i < bp->cp_nr_rings; i++) {
4556                 struct bnxt_napi *bnapi = bp->bnapi[i];
4557                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4558                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4559
4560                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4561                         hwrm_ring_free_send_msg(bp, ring,
4562                                                 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4563                                                 INVALID_HW_RING_ID);
4564                         ring->fw_ring_id = INVALID_HW_RING_ID;
4565                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4566                 }
4567         }
4568 }
4569
4570 static int bnxt_hwrm_get_rings(struct bnxt *bp)
4571 {
4572         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4573         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4574         struct hwrm_func_qcfg_input req = {0};
4575         int rc;
4576
4577         if (bp->hwrm_spec_code < 0x10601)
4578                 return 0;
4579
4580         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4581         req.fid = cpu_to_le16(0xffff);
4582         mutex_lock(&bp->hwrm_cmd_lock);
4583         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4584         if (rc) {
4585                 mutex_unlock(&bp->hwrm_cmd_lock);
4586                 return -EIO;
4587         }
4588
4589         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4590         if (bp->flags & BNXT_FLAG_NEW_RM) {
4591                 u16 cp, stats;
4592
4593                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
4594                 hw_resc->resv_hw_ring_grps =
4595                         le32_to_cpu(resp->alloc_hw_ring_grps);
4596                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
4597                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
4598                 stats = le16_to_cpu(resp->alloc_stat_ctx);
4599                 cp = min_t(u16, cp, stats);
4600                 hw_resc->resv_cp_rings = cp;
4601         }
4602         mutex_unlock(&bp->hwrm_cmd_lock);
4603         return 0;
4604 }
4605
4606 /* Caller must hold bp->hwrm_cmd_lock */
4607 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4608 {
4609         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4610         struct hwrm_func_qcfg_input req = {0};
4611         int rc;
4612
4613         if (bp->hwrm_spec_code < 0x10601)
4614                 return 0;
4615
4616         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4617         req.fid = cpu_to_le16(fid);
4618         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4619         if (!rc)
4620                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4621
4622         return rc;
4623 }
4624
4625 static void
4626 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
4627                              int tx_rings, int rx_rings, int ring_grps,
4628                              int cp_rings, int vnics)
4629 {
4630         u32 enables = 0;
4631
4632         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
4633         req->fid = cpu_to_le16(0xffff);
4634         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4635         req->num_tx_rings = cpu_to_le16(tx_rings);
4636         if (bp->flags & BNXT_FLAG_NEW_RM) {
4637                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4638                 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4639                                       FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4640                 enables |= ring_grps ?
4641                            FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4642                 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4643
4644                 req->num_rx_rings = cpu_to_le16(rx_rings);
4645                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4646                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4647                 req->num_stat_ctxs = req->num_cmpl_rings;
4648                 req->num_vnics = cpu_to_le16(vnics);
4649         }
4650         req->enables = cpu_to_le32(enables);
4651 }
4652
4653 static void
4654 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
4655                              struct hwrm_func_vf_cfg_input *req, int tx_rings,
4656                              int rx_rings, int ring_grps, int cp_rings,
4657                              int vnics)
4658 {
4659         u32 enables = 0;
4660
4661         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
4662         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4663         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4664         enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4665                               FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4666         enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4667         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4668
4669         req->num_tx_rings = cpu_to_le16(tx_rings);
4670         req->num_rx_rings = cpu_to_le16(rx_rings);
4671         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4672         req->num_cmpl_rings = cpu_to_le16(cp_rings);
4673         req->num_stat_ctxs = req->num_cmpl_rings;
4674         req->num_vnics = cpu_to_le16(vnics);
4675
4676         req->enables = cpu_to_le32(enables);
4677 }
4678
4679 static int
4680 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4681                            int ring_grps, int cp_rings, int vnics)
4682 {
4683         struct hwrm_func_cfg_input req = {0};
4684         int rc;
4685
4686         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4687                                      cp_rings, vnics);
4688         if (!req.enables)
4689                 return 0;
4690
4691         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4692         if (rc)
4693                 return -ENOMEM;
4694
4695         if (bp->hwrm_spec_code < 0x10601)
4696                 bp->hw_resc.resv_tx_rings = tx_rings;
4697
4698         rc = bnxt_hwrm_get_rings(bp);
4699         return rc;
4700 }
4701
4702 static int
4703 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4704                            int ring_grps, int cp_rings, int vnics)
4705 {
4706         struct hwrm_func_vf_cfg_input req = {0};
4707         int rc;
4708
4709         if (!(bp->flags & BNXT_FLAG_NEW_RM)) {
4710                 bp->hw_resc.resv_tx_rings = tx_rings;
4711                 return 0;
4712         }
4713
4714         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4715                                      cp_rings, vnics);
4716         req.enables |= cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS |
4717                                    FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS);
4718         req.num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
4719         req.num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
4720         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4721         if (rc)
4722                 return -ENOMEM;
4723
4724         rc = bnxt_hwrm_get_rings(bp);
4725         return rc;
4726 }
4727
4728 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
4729                                    int cp, int vnic)
4730 {
4731         if (BNXT_PF(bp))
4732                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
4733         else
4734                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
4735 }
4736
4737 static int bnxt_cp_rings_in_use(struct bnxt *bp)
4738 {
4739         int cp = bp->cp_nr_rings;
4740         int ulp_msix, ulp_base;
4741
4742         ulp_msix = bnxt_get_ulp_msix_num(bp);
4743         if (ulp_msix) {
4744                 ulp_base = bnxt_get_ulp_msix_base(bp);
4745                 cp += ulp_msix;
4746                 if ((ulp_base + ulp_msix) > cp)
4747                         cp = ulp_base + ulp_msix;
4748         }
4749         return cp;
4750 }
4751
4752 static bool bnxt_need_reserve_rings(struct bnxt *bp)
4753 {
4754         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4755         int cp = bnxt_cp_rings_in_use(bp);
4756         int rx = bp->rx_nr_rings;
4757         int vnic = 1, grp = rx;
4758
4759         if (bp->hwrm_spec_code < 0x10601)
4760                 return false;
4761
4762         if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
4763                 return true;
4764
4765         if (bp->flags & BNXT_FLAG_RFS)
4766                 vnic = rx + 1;
4767         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4768                 rx <<= 1;
4769         if ((bp->flags & BNXT_FLAG_NEW_RM) &&
4770             (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
4771              hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic))
4772                 return true;
4773         return false;
4774 }
4775
4776 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4777                            bool shared);
4778
4779 static int __bnxt_reserve_rings(struct bnxt *bp)
4780 {
4781         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4782         int cp = bnxt_cp_rings_in_use(bp);
4783         int tx = bp->tx_nr_rings;
4784         int rx = bp->rx_nr_rings;
4785         int grp, rx_rings, rc;
4786         bool sh = false;
4787         int vnic = 1;
4788
4789         if (!bnxt_need_reserve_rings(bp))
4790                 return 0;
4791
4792         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4793                 sh = true;
4794         if (bp->flags & BNXT_FLAG_RFS)
4795                 vnic = rx + 1;
4796         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4797                 rx <<= 1;
4798         grp = bp->rx_nr_rings;
4799
4800         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
4801         if (rc)
4802                 return rc;
4803
4804         tx = hw_resc->resv_tx_rings;
4805         if (bp->flags & BNXT_FLAG_NEW_RM) {
4806                 rx = hw_resc->resv_rx_rings;
4807                 cp = hw_resc->resv_cp_rings;
4808                 grp = hw_resc->resv_hw_ring_grps;
4809                 vnic = hw_resc->resv_vnics;
4810         }
4811
4812         rx_rings = rx;
4813         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4814                 if (rx >= 2) {
4815                         rx_rings = rx >> 1;
4816                 } else {
4817                         if (netif_running(bp->dev))
4818                                 return -ENOMEM;
4819
4820                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4821                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4822                         bp->dev->hw_features &= ~NETIF_F_LRO;
4823                         bp->dev->features &= ~NETIF_F_LRO;
4824                         bnxt_set_ring_params(bp);
4825                 }
4826         }
4827         rx_rings = min_t(int, rx_rings, grp);
4828         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
4829         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4830                 rx = rx_rings << 1;
4831         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
4832         bp->tx_nr_rings = tx;
4833         bp->rx_nr_rings = rx_rings;
4834         bp->cp_nr_rings = cp;
4835
4836         if (!tx || !rx || !cp || !grp || !vnic)
4837                 return -ENOMEM;
4838
4839         return rc;
4840 }
4841
4842 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4843                                     int ring_grps, int cp_rings, int vnics)
4844 {
4845         struct hwrm_func_vf_cfg_input req = {0};
4846         u32 flags;
4847         int rc;
4848
4849         if (!(bp->flags & BNXT_FLAG_NEW_RM))
4850                 return 0;
4851
4852         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4853                                      cp_rings, vnics);
4854         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
4855                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4856                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4857                 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4858                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4859                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4860
4861         req.flags = cpu_to_le32(flags);
4862         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4863         if (rc)
4864                 return -ENOMEM;
4865         return 0;
4866 }
4867
4868 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4869                                     int ring_grps, int cp_rings, int vnics)
4870 {
4871         struct hwrm_func_cfg_input req = {0};
4872         u32 flags;
4873         int rc;
4874
4875         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4876                                      cp_rings, vnics);
4877         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4878         if (bp->flags & BNXT_FLAG_NEW_RM)
4879                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4880                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4881                          FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4882                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4883                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4884
4885         req.flags = cpu_to_le32(flags);
4886         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4887         if (rc)
4888                 return -ENOMEM;
4889         return 0;
4890 }
4891
4892 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4893                                  int ring_grps, int cp_rings, int vnics)
4894 {
4895         if (bp->hwrm_spec_code < 0x10801)
4896                 return 0;
4897
4898         if (BNXT_PF(bp))
4899                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
4900                                                 ring_grps, cp_rings, vnics);
4901
4902         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
4903                                         cp_rings, vnics);
4904 }
4905
4906 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4907         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4908 {
4909         u16 val, tmr, max, flags;
4910
4911         max = hw_coal->bufs_per_record * 128;
4912         if (hw_coal->budget)
4913                 max = hw_coal->bufs_per_record * hw_coal->budget;
4914
4915         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4916         req->num_cmpl_aggr_int = cpu_to_le16(val);
4917
4918         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4919         val = min_t(u16, val, 63);
4920         req->num_cmpl_dma_aggr = cpu_to_le16(val);
4921
4922         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4923         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
4924         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4925
4926         tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4927         tmr = max_t(u16, tmr, 1);
4928         req->int_lat_tmr_max = cpu_to_le16(tmr);
4929
4930         /* min timer set to 1/2 of interrupt timer */
4931         val = tmr / 2;
4932         req->int_lat_tmr_min = cpu_to_le16(val);
4933
4934         /* buf timer set to 1/4 of interrupt timer */
4935         val = max_t(u16, tmr / 4, 1);
4936         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4937
4938         tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4939         tmr = max_t(u16, tmr, 1);
4940         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4941
4942         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4943         if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4944                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4945         req->flags = cpu_to_le16(flags);
4946 }
4947
4948 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
4949 {
4950         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
4951         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4952         struct bnxt_coal coal;
4953         unsigned int grp_idx;
4954
4955         /* Tick values in micro seconds.
4956          * 1 coal_buf x bufs_per_record = 1 completion record.
4957          */
4958         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
4959
4960         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
4961         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
4962
4963         if (!bnapi->rx_ring)
4964                 return -ENODEV;
4965
4966         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4967                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4968
4969         bnxt_hwrm_set_coal_params(&coal, &req_rx);
4970
4971         grp_idx = bnapi->index;
4972         req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4973
4974         return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
4975                                  HWRM_CMD_TIMEOUT);
4976 }
4977
4978 int bnxt_hwrm_set_coal(struct bnxt *bp)
4979 {
4980         int i, rc = 0;
4981         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4982                                                            req_tx = {0}, *req;
4983
4984         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4985                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4986         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4987                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4988
4989         bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
4990         bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
4991
4992         mutex_lock(&bp->hwrm_cmd_lock);
4993         for (i = 0; i < bp->cp_nr_rings; i++) {
4994                 struct bnxt_napi *bnapi = bp->bnapi[i];
4995
4996                 req = &req_rx;
4997                 if (!bnapi->rx_ring)
4998                         req = &req_tx;
4999                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
5000
5001                 rc = _hwrm_send_message(bp, req, sizeof(*req),
5002                                         HWRM_CMD_TIMEOUT);
5003                 if (rc)
5004                         break;
5005         }
5006         mutex_unlock(&bp->hwrm_cmd_lock);
5007         return rc;
5008 }
5009
5010 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5011 {
5012         int rc = 0, i;
5013         struct hwrm_stat_ctx_free_input req = {0};
5014
5015         if (!bp->bnapi)
5016                 return 0;
5017
5018         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5019                 return 0;
5020
5021         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5022
5023         mutex_lock(&bp->hwrm_cmd_lock);
5024         for (i = 0; i < bp->cp_nr_rings; i++) {
5025                 struct bnxt_napi *bnapi = bp->bnapi[i];
5026                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5027
5028                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5029                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5030
5031                         rc = _hwrm_send_message(bp, &req, sizeof(req),
5032                                                 HWRM_CMD_TIMEOUT);
5033                         if (rc)
5034                                 break;
5035
5036                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5037                 }
5038         }
5039         mutex_unlock(&bp->hwrm_cmd_lock);
5040         return rc;
5041 }
5042
5043 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5044 {
5045         int rc = 0, i;
5046         struct hwrm_stat_ctx_alloc_input req = {0};
5047         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5048
5049         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5050                 return 0;
5051
5052         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5053
5054         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5055
5056         mutex_lock(&bp->hwrm_cmd_lock);
5057         for (i = 0; i < bp->cp_nr_rings; i++) {
5058                 struct bnxt_napi *bnapi = bp->bnapi[i];
5059                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5060
5061                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5062
5063                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5064                                         HWRM_CMD_TIMEOUT);
5065                 if (rc)
5066                         break;
5067
5068                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5069
5070                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5071         }
5072         mutex_unlock(&bp->hwrm_cmd_lock);
5073         return rc;
5074 }
5075
5076 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5077 {
5078         struct hwrm_func_qcfg_input req = {0};
5079         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5080         u16 flags;
5081         int rc;
5082
5083         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5084         req.fid = cpu_to_le16(0xffff);
5085         mutex_lock(&bp->hwrm_cmd_lock);
5086         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5087         if (rc)
5088                 goto func_qcfg_exit;
5089
5090 #ifdef CONFIG_BNXT_SRIOV
5091         if (BNXT_VF(bp)) {
5092                 struct bnxt_vf_info *vf = &bp->vf;
5093
5094                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5095         }
5096 #endif
5097         flags = le16_to_cpu(resp->flags);
5098         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5099                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5100                 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
5101                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5102                         bp->flags |= BNXT_FLAG_FW_DCBX_AGENT;
5103         }
5104         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5105                 bp->flags |= BNXT_FLAG_MULTI_HOST;
5106
5107         switch (resp->port_partition_type) {
5108         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5109         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5110         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5111                 bp->port_partition_type = resp->port_partition_type;
5112                 break;
5113         }
5114         if (bp->hwrm_spec_code < 0x10707 ||
5115             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5116                 bp->br_mode = BRIDGE_MODE_VEB;
5117         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5118                 bp->br_mode = BRIDGE_MODE_VEPA;
5119         else
5120                 bp->br_mode = BRIDGE_MODE_UNDEF;
5121
5122         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5123         if (!bp->max_mtu)
5124                 bp->max_mtu = BNXT_MAX_MTU;
5125
5126 func_qcfg_exit:
5127         mutex_unlock(&bp->hwrm_cmd_lock);
5128         return rc;
5129 }
5130
5131 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
5132 {
5133         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5134         struct hwrm_func_resource_qcaps_input req = {0};
5135         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5136         int rc;
5137
5138         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
5139         req.fid = cpu_to_le16(0xffff);
5140
5141         mutex_lock(&bp->hwrm_cmd_lock);
5142         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5143         if (rc) {
5144                 rc = -EIO;
5145                 goto hwrm_func_resc_qcaps_exit;
5146         }
5147
5148         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
5149         if (!all)
5150                 goto hwrm_func_resc_qcaps_exit;
5151
5152         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
5153         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5154         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
5155         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5156         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
5157         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5158         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
5159         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5160         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
5161         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
5162         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
5163         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5164         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
5165         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5166         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
5167         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5168
5169         if (BNXT_PF(bp)) {
5170                 struct bnxt_pf_info *pf = &bp->pf;
5171
5172                 pf->vf_resv_strategy =
5173                         le16_to_cpu(resp->vf_reservation_strategy);
5174                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL)
5175                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
5176         }
5177 hwrm_func_resc_qcaps_exit:
5178         mutex_unlock(&bp->hwrm_cmd_lock);
5179         return rc;
5180 }
5181
5182 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
5183 {
5184         int rc = 0;
5185         struct hwrm_func_qcaps_input req = {0};
5186         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5187         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5188         u32 flags;
5189
5190         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
5191         req.fid = cpu_to_le16(0xffff);
5192
5193         mutex_lock(&bp->hwrm_cmd_lock);
5194         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5195         if (rc)
5196                 goto hwrm_func_qcaps_exit;
5197
5198         flags = le32_to_cpu(resp->flags);
5199         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
5200                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
5201         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
5202                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
5203
5204         bp->tx_push_thresh = 0;
5205         if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
5206                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
5207
5208         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5209         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5210         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5211         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5212         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
5213         if (!hw_resc->max_hw_ring_grps)
5214                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
5215         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5216         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5217         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5218
5219         if (BNXT_PF(bp)) {
5220                 struct bnxt_pf_info *pf = &bp->pf;
5221
5222                 pf->fw_fid = le16_to_cpu(resp->fid);
5223                 pf->port_id = le16_to_cpu(resp->port_id);
5224                 bp->dev->dev_port = pf->port_id;
5225                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
5226                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
5227                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
5228                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
5229                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
5230                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
5231                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
5232                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
5233                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
5234                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
5235                         bp->flags |= BNXT_FLAG_WOL_CAP;
5236         } else {
5237 #ifdef CONFIG_BNXT_SRIOV
5238                 struct bnxt_vf_info *vf = &bp->vf;
5239
5240                 vf->fw_fid = le16_to_cpu(resp->fid);
5241                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
5242 #endif
5243         }
5244
5245 hwrm_func_qcaps_exit:
5246         mutex_unlock(&bp->hwrm_cmd_lock);
5247         return rc;
5248 }
5249
5250 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5251 {
5252         int rc;
5253
5254         rc = __bnxt_hwrm_func_qcaps(bp);
5255         if (rc)
5256                 return rc;
5257         if (bp->hwrm_spec_code >= 0x10803) {
5258                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
5259                 if (!rc)
5260                         bp->flags |= BNXT_FLAG_NEW_RM;
5261         }
5262         return 0;
5263 }
5264
5265 static int bnxt_hwrm_func_reset(struct bnxt *bp)
5266 {
5267         struct hwrm_func_reset_input req = {0};
5268
5269         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
5270         req.enables = 0;
5271
5272         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
5273 }
5274
5275 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5276 {
5277         int rc = 0;
5278         struct hwrm_queue_qportcfg_input req = {0};
5279         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
5280         u8 i, *qptr;
5281
5282         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
5283
5284         mutex_lock(&bp->hwrm_cmd_lock);
5285         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5286         if (rc)
5287                 goto qportcfg_exit;
5288
5289         if (!resp->max_configurable_queues) {
5290                 rc = -EINVAL;
5291                 goto qportcfg_exit;
5292         }
5293         bp->max_tc = resp->max_configurable_queues;
5294         bp->max_lltc = resp->max_configurable_lossless_queues;
5295         if (bp->max_tc > BNXT_MAX_QUEUE)
5296                 bp->max_tc = BNXT_MAX_QUEUE;
5297
5298         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
5299                 bp->max_tc = 1;
5300
5301         if (bp->max_lltc > bp->max_tc)
5302                 bp->max_lltc = bp->max_tc;
5303
5304         qptr = &resp->queue_id0;
5305         for (i = 0; i < bp->max_tc; i++) {
5306                 bp->q_info[i].queue_id = *qptr++;
5307                 bp->q_info[i].queue_profile = *qptr++;
5308                 bp->tc_to_qidx[i] = i;
5309         }
5310
5311 qportcfg_exit:
5312         mutex_unlock(&bp->hwrm_cmd_lock);
5313         return rc;
5314 }
5315
5316 static int bnxt_hwrm_ver_get(struct bnxt *bp)
5317 {
5318         int rc;
5319         struct hwrm_ver_get_input req = {0};
5320         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
5321         u32 dev_caps_cfg;
5322
5323         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
5324         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
5325         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
5326         req.hwrm_intf_min = HWRM_VERSION_MINOR;
5327         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
5328         mutex_lock(&bp->hwrm_cmd_lock);
5329         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5330         if (rc)
5331                 goto hwrm_ver_get_exit;
5332
5333         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
5334
5335         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
5336                              resp->hwrm_intf_min_8b << 8 |
5337                              resp->hwrm_intf_upd_8b;
5338         if (resp->hwrm_intf_maj_8b < 1) {
5339                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
5340                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
5341                             resp->hwrm_intf_upd_8b);
5342                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
5343         }
5344         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
5345                  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
5346                  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
5347
5348         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
5349         if (!bp->hwrm_cmd_timeout)
5350                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
5351
5352         if (resp->hwrm_intf_maj_8b >= 1)
5353                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
5354
5355         bp->chip_num = le16_to_cpu(resp->chip_num);
5356         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
5357             !resp->chip_metal)
5358                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
5359
5360         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
5361         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5362             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5363                 bp->flags |= BNXT_FLAG_SHORT_CMD;
5364
5365 hwrm_ver_get_exit:
5366         mutex_unlock(&bp->hwrm_cmd_lock);
5367         return rc;
5368 }
5369
5370 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
5371 {
5372         struct hwrm_fw_set_time_input req = {0};
5373         struct tm tm;
5374         time64_t now = ktime_get_real_seconds();
5375
5376         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
5377             bp->hwrm_spec_code < 0x10400)
5378                 return -EOPNOTSUPP;
5379
5380         time64_to_tm(now, 0, &tm);
5381         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
5382         req.year = cpu_to_le16(1900 + tm.tm_year);
5383         req.month = 1 + tm.tm_mon;
5384         req.day = tm.tm_mday;
5385         req.hour = tm.tm_hour;
5386         req.minute = tm.tm_min;
5387         req.second = tm.tm_sec;
5388         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5389 }
5390
5391 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
5392 {
5393         int rc;
5394         struct bnxt_pf_info *pf = &bp->pf;
5395         struct hwrm_port_qstats_input req = {0};
5396
5397         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5398                 return 0;
5399
5400         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5401         req.port_id = cpu_to_le16(pf->port_id);
5402         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5403         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5404         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5405         return rc;
5406 }
5407
5408 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
5409 {
5410         struct hwrm_port_qstats_ext_input req = {0};
5411         struct bnxt_pf_info *pf = &bp->pf;
5412
5413         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5414                 return 0;
5415
5416         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
5417         req.port_id = cpu_to_le16(pf->port_id);
5418         req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
5419         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
5420         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5421 }
5422
5423 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5424 {
5425         if (bp->vxlan_port_cnt) {
5426                 bnxt_hwrm_tunnel_dst_port_free(
5427                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5428         }
5429         bp->vxlan_port_cnt = 0;
5430         if (bp->nge_port_cnt) {
5431                 bnxt_hwrm_tunnel_dst_port_free(
5432                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5433         }
5434         bp->nge_port_cnt = 0;
5435 }
5436
5437 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5438 {
5439         int rc, i;
5440         u32 tpa_flags = 0;
5441
5442         if (set_tpa)
5443                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5444         for (i = 0; i < bp->nr_vnics; i++) {
5445                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5446                 if (rc) {
5447                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5448                                    i, rc);
5449                         return rc;
5450                 }
5451         }
5452         return 0;
5453 }
5454
5455 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5456 {
5457         int i;
5458
5459         for (i = 0; i < bp->nr_vnics; i++)
5460                 bnxt_hwrm_vnic_set_rss(bp, i, false);
5461 }
5462
5463 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5464                                     bool irq_re_init)
5465 {
5466         if (bp->vnic_info) {
5467                 bnxt_hwrm_clear_vnic_filter(bp);
5468                 /* clear all RSS setting before free vnic ctx */
5469                 bnxt_hwrm_clear_vnic_rss(bp);
5470                 bnxt_hwrm_vnic_ctx_free(bp);
5471                 /* before free the vnic, undo the vnic tpa settings */
5472                 if (bp->flags & BNXT_FLAG_TPA)
5473                         bnxt_set_tpa(bp, false);
5474                 bnxt_hwrm_vnic_free(bp);
5475         }
5476         bnxt_hwrm_ring_free(bp, close_path);
5477         bnxt_hwrm_ring_grp_free(bp);
5478         if (irq_re_init) {
5479                 bnxt_hwrm_stat_ctx_free(bp);
5480                 bnxt_hwrm_free_tunnel_ports(bp);
5481         }
5482 }
5483
5484 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5485 {
5486         struct hwrm_func_cfg_input req = {0};
5487         int rc;
5488
5489         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5490         req.fid = cpu_to_le16(0xffff);
5491         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5492         if (br_mode == BRIDGE_MODE_VEB)
5493                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5494         else if (br_mode == BRIDGE_MODE_VEPA)
5495                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5496         else
5497                 return -EINVAL;
5498         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5499         if (rc)
5500                 rc = -EIO;
5501         return rc;
5502 }
5503
5504 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
5505 {
5506         struct hwrm_func_cfg_input req = {0};
5507         int rc;
5508
5509         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
5510                 return 0;
5511
5512         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5513         req.fid = cpu_to_le16(0xffff);
5514         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
5515         req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
5516         if (size == 128)
5517                 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
5518
5519         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5520         if (rc)
5521                 rc = -EIO;
5522         return rc;
5523 }
5524
5525 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5526 {
5527         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5528         int rc;
5529
5530         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5531                 goto skip_rss_ctx;
5532
5533         /* allocate context for vnic */
5534         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5535         if (rc) {
5536                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5537                            vnic_id, rc);
5538                 goto vnic_setup_err;
5539         }
5540         bp->rsscos_nr_ctxs++;
5541
5542         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5543                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5544                 if (rc) {
5545                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5546                                    vnic_id, rc);
5547                         goto vnic_setup_err;
5548                 }
5549                 bp->rsscos_nr_ctxs++;
5550         }
5551
5552 skip_rss_ctx:
5553         /* configure default vnic, ring grp */
5554         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5555         if (rc) {
5556                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5557                            vnic_id, rc);
5558                 goto vnic_setup_err;
5559         }
5560
5561         /* Enable RSS hashing on vnic */
5562         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5563         if (rc) {
5564                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5565                            vnic_id, rc);
5566                 goto vnic_setup_err;
5567         }
5568
5569         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5570                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5571                 if (rc) {
5572                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5573                                    vnic_id, rc);
5574                 }
5575         }
5576
5577 vnic_setup_err:
5578         return rc;
5579 }
5580
5581 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5582 {
5583 #ifdef CONFIG_RFS_ACCEL
5584         int i, rc = 0;
5585
5586         for (i = 0; i < bp->rx_nr_rings; i++) {
5587                 struct bnxt_vnic_info *vnic;
5588                 u16 vnic_id = i + 1;
5589                 u16 ring_id = i;
5590
5591                 if (vnic_id >= bp->nr_vnics)
5592                         break;
5593
5594                 vnic = &bp->vnic_info[vnic_id];
5595                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5596                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5597                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5598                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5599                 if (rc) {
5600                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5601                                    vnic_id, rc);
5602                         break;
5603                 }
5604                 rc = bnxt_setup_vnic(bp, vnic_id);
5605                 if (rc)
5606                         break;
5607         }
5608         return rc;
5609 #else
5610         return 0;
5611 #endif
5612 }
5613
5614 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5615 static bool bnxt_promisc_ok(struct bnxt *bp)
5616 {
5617 #ifdef CONFIG_BNXT_SRIOV
5618         if (BNXT_VF(bp) && !bp->vf.vlan)
5619                 return false;
5620 #endif
5621         return true;
5622 }
5623
5624 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5625 {
5626         unsigned int rc = 0;
5627
5628         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5629         if (rc) {
5630                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5631                            rc);
5632                 return rc;
5633         }
5634
5635         rc = bnxt_hwrm_vnic_cfg(bp, 1);
5636         if (rc) {
5637                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5638                            rc);
5639                 return rc;
5640         }
5641         return rc;
5642 }
5643
5644 static int bnxt_cfg_rx_mode(struct bnxt *);
5645 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5646
5647 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5648 {
5649         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5650         int rc = 0;
5651         unsigned int rx_nr_rings = bp->rx_nr_rings;
5652
5653         if (irq_re_init) {
5654                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5655                 if (rc) {
5656                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5657                                    rc);
5658                         goto err_out;
5659                 }
5660         }
5661
5662         rc = bnxt_hwrm_ring_alloc(bp);
5663         if (rc) {
5664                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5665                 goto err_out;
5666         }
5667
5668         rc = bnxt_hwrm_ring_grp_alloc(bp);
5669         if (rc) {
5670                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5671                 goto err_out;
5672         }
5673
5674         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5675                 rx_nr_rings--;
5676
5677         /* default vnic 0 */
5678         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5679         if (rc) {
5680                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5681                 goto err_out;
5682         }
5683
5684         rc = bnxt_setup_vnic(bp, 0);
5685         if (rc)
5686                 goto err_out;
5687
5688         if (bp->flags & BNXT_FLAG_RFS) {
5689                 rc = bnxt_alloc_rfs_vnics(bp);
5690                 if (rc)
5691                         goto err_out;
5692         }
5693
5694         if (bp->flags & BNXT_FLAG_TPA) {
5695                 rc = bnxt_set_tpa(bp, true);
5696                 if (rc)
5697                         goto err_out;
5698         }
5699
5700         if (BNXT_VF(bp))
5701                 bnxt_update_vf_mac(bp);
5702
5703         /* Filter for default vnic 0 */
5704         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5705         if (rc) {
5706                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5707                 goto err_out;
5708         }
5709         vnic->uc_filter_count = 1;
5710
5711         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5712
5713         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5714                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5715
5716         if (bp->dev->flags & IFF_ALLMULTI) {
5717                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5718                 vnic->mc_list_count = 0;
5719         } else {
5720                 u32 mask = 0;
5721
5722                 bnxt_mc_list_updated(bp, &mask);
5723                 vnic->rx_mask |= mask;
5724         }
5725
5726         rc = bnxt_cfg_rx_mode(bp);
5727         if (rc)
5728                 goto err_out;
5729
5730         rc = bnxt_hwrm_set_coal(bp);
5731         if (rc)
5732                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5733                                 rc);
5734
5735         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5736                 rc = bnxt_setup_nitroa0_vnic(bp);
5737                 if (rc)
5738                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5739                                    rc);
5740         }
5741
5742         if (BNXT_VF(bp)) {
5743                 bnxt_hwrm_func_qcfg(bp);
5744                 netdev_update_features(bp->dev);
5745         }
5746
5747         return 0;
5748
5749 err_out:
5750         bnxt_hwrm_resource_free(bp, 0, true);
5751
5752         return rc;
5753 }
5754
5755 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5756 {
5757         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5758         return 0;
5759 }
5760
5761 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5762 {
5763         bnxt_init_cp_rings(bp);
5764         bnxt_init_rx_rings(bp);
5765         bnxt_init_tx_rings(bp);
5766         bnxt_init_ring_grps(bp, irq_re_init);
5767         bnxt_init_vnics(bp);
5768
5769         return bnxt_init_chip(bp, irq_re_init);
5770 }
5771
5772 static int bnxt_set_real_num_queues(struct bnxt *bp)
5773 {
5774         int rc;
5775         struct net_device *dev = bp->dev;
5776
5777         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5778                                           bp->tx_nr_rings_xdp);
5779         if (rc)
5780                 return rc;
5781
5782         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5783         if (rc)
5784                 return rc;
5785
5786 #ifdef CONFIG_RFS_ACCEL
5787         if (bp->flags & BNXT_FLAG_RFS)
5788                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5789 #endif
5790
5791         return rc;
5792 }
5793
5794 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5795                            bool shared)
5796 {
5797         int _rx = *rx, _tx = *tx;
5798
5799         if (shared) {
5800                 *rx = min_t(int, _rx, max);
5801                 *tx = min_t(int, _tx, max);
5802         } else {
5803                 if (max < 2)
5804                         return -ENOMEM;
5805
5806                 while (_rx + _tx > max) {
5807                         if (_rx > _tx && _rx > 1)
5808                                 _rx--;
5809                         else if (_tx > 1)
5810                                 _tx--;
5811                 }
5812                 *rx = _rx;
5813                 *tx = _tx;
5814         }
5815         return 0;
5816 }
5817
5818 static void bnxt_setup_msix(struct bnxt *bp)
5819 {
5820         const int len = sizeof(bp->irq_tbl[0].name);
5821         struct net_device *dev = bp->dev;
5822         int tcs, i;
5823
5824         tcs = netdev_get_num_tc(dev);
5825         if (tcs > 1) {
5826                 int i, off, count;
5827
5828                 for (i = 0; i < tcs; i++) {
5829                         count = bp->tx_nr_rings_per_tc;
5830                         off = i * count;
5831                         netdev_set_tc_queue(dev, i, count, off);
5832                 }
5833         }
5834
5835         for (i = 0; i < bp->cp_nr_rings; i++) {
5836                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
5837                 char *attr;
5838
5839                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5840                         attr = "TxRx";
5841                 else if (i < bp->rx_nr_rings)
5842                         attr = "rx";
5843                 else
5844                         attr = "tx";
5845
5846                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
5847                          attr, i);
5848                 bp->irq_tbl[map_idx].handler = bnxt_msix;
5849         }
5850 }
5851
5852 static void bnxt_setup_inta(struct bnxt *bp)
5853 {
5854         const int len = sizeof(bp->irq_tbl[0].name);
5855
5856         if (netdev_get_num_tc(bp->dev))
5857                 netdev_reset_tc(bp->dev);
5858
5859         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5860                  0);
5861         bp->irq_tbl[0].handler = bnxt_inta;
5862 }
5863
5864 static int bnxt_setup_int_mode(struct bnxt *bp)
5865 {
5866         int rc;
5867
5868         if (bp->flags & BNXT_FLAG_USING_MSIX)
5869                 bnxt_setup_msix(bp);
5870         else
5871                 bnxt_setup_inta(bp);
5872
5873         rc = bnxt_set_real_num_queues(bp);
5874         return rc;
5875 }
5876
5877 #ifdef CONFIG_RFS_ACCEL
5878 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5879 {
5880         return bp->hw_resc.max_rsscos_ctxs;
5881 }
5882
5883 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5884 {
5885         return bp->hw_resc.max_vnics;
5886 }
5887 #endif
5888
5889 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5890 {
5891         return bp->hw_resc.max_stat_ctxs;
5892 }
5893
5894 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5895 {
5896         bp->hw_resc.max_stat_ctxs = max;
5897 }
5898
5899 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5900 {
5901         return bp->hw_resc.max_cp_rings;
5902 }
5903
5904 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5905 {
5906         bp->hw_resc.max_cp_rings = max;
5907 }
5908
5909 unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5910 {
5911         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5912
5913         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
5914 }
5915
5916 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5917 {
5918         bp->hw_resc.max_irqs = max_irqs;
5919 }
5920
5921 int bnxt_get_avail_msix(struct bnxt *bp, int num)
5922 {
5923         int max_cp = bnxt_get_max_func_cp_rings(bp);
5924         int max_irq = bnxt_get_max_func_irqs(bp);
5925         int total_req = bp->cp_nr_rings + num;
5926         int max_idx, avail_msix;
5927
5928         max_idx = min_t(int, bp->total_irqs, max_cp);
5929         avail_msix = max_idx - bp->cp_nr_rings;
5930         if (!(bp->flags & BNXT_FLAG_NEW_RM) || avail_msix >= num)
5931                 return avail_msix;
5932
5933         if (max_irq < total_req) {
5934                 num = max_irq - bp->cp_nr_rings;
5935                 if (num <= 0)
5936                         return 0;
5937         }
5938         return num;
5939 }
5940
5941 static int bnxt_get_num_msix(struct bnxt *bp)
5942 {
5943         if (!(bp->flags & BNXT_FLAG_NEW_RM))
5944                 return bnxt_get_max_func_irqs(bp);
5945
5946         return bnxt_cp_rings_in_use(bp);
5947 }
5948
5949 static int bnxt_init_msix(struct bnxt *bp)
5950 {
5951         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
5952         struct msix_entry *msix_ent;
5953
5954         total_vecs = bnxt_get_num_msix(bp);
5955         max = bnxt_get_max_func_irqs(bp);
5956         if (total_vecs > max)
5957                 total_vecs = max;
5958
5959         if (!total_vecs)
5960                 return 0;
5961
5962         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5963         if (!msix_ent)
5964                 return -ENOMEM;
5965
5966         for (i = 0; i < total_vecs; i++) {
5967                 msix_ent[i].entry = i;
5968                 msix_ent[i].vector = 0;
5969         }
5970
5971         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5972                 min = 2;
5973
5974         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5975         ulp_msix = bnxt_get_ulp_msix_num(bp);
5976         if (total_vecs < 0 || total_vecs < ulp_msix) {
5977                 rc = -ENODEV;
5978                 goto msix_setup_exit;
5979         }
5980
5981         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5982         if (bp->irq_tbl) {
5983                 for (i = 0; i < total_vecs; i++)
5984                         bp->irq_tbl[i].vector = msix_ent[i].vector;
5985
5986                 bp->total_irqs = total_vecs;
5987                 /* Trim rings based upon num of vectors allocated */
5988                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5989                                      total_vecs - ulp_msix, min == 1);
5990                 if (rc)
5991                         goto msix_setup_exit;
5992
5993                 bp->cp_nr_rings = (min == 1) ?
5994                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5995                                   bp->tx_nr_rings + bp->rx_nr_rings;
5996
5997         } else {
5998                 rc = -ENOMEM;
5999                 goto msix_setup_exit;
6000         }
6001         bp->flags |= BNXT_FLAG_USING_MSIX;
6002         kfree(msix_ent);
6003         return 0;
6004
6005 msix_setup_exit:
6006         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
6007         kfree(bp->irq_tbl);
6008         bp->irq_tbl = NULL;
6009         pci_disable_msix(bp->pdev);
6010         kfree(msix_ent);
6011         return rc;
6012 }
6013
6014 static int bnxt_init_inta(struct bnxt *bp)
6015 {
6016         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
6017         if (!bp->irq_tbl)
6018                 return -ENOMEM;
6019
6020         bp->total_irqs = 1;
6021         bp->rx_nr_rings = 1;
6022         bp->tx_nr_rings = 1;
6023         bp->cp_nr_rings = 1;
6024         bp->flags |= BNXT_FLAG_SHARED_RINGS;
6025         bp->irq_tbl[0].vector = bp->pdev->irq;
6026         return 0;
6027 }
6028
6029 static int bnxt_init_int_mode(struct bnxt *bp)
6030 {
6031         int rc = 0;
6032
6033         if (bp->flags & BNXT_FLAG_MSIX_CAP)
6034                 rc = bnxt_init_msix(bp);
6035
6036         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
6037                 /* fallback to INTA */
6038                 rc = bnxt_init_inta(bp);
6039         }
6040         return rc;
6041 }
6042
6043 static void bnxt_clear_int_mode(struct bnxt *bp)
6044 {
6045         if (bp->flags & BNXT_FLAG_USING_MSIX)
6046                 pci_disable_msix(bp->pdev);
6047
6048         kfree(bp->irq_tbl);
6049         bp->irq_tbl = NULL;
6050         bp->flags &= ~BNXT_FLAG_USING_MSIX;
6051 }
6052
6053 int bnxt_reserve_rings(struct bnxt *bp)
6054 {
6055         int tcs = netdev_get_num_tc(bp->dev);
6056         int rc;
6057
6058         if (!bnxt_need_reserve_rings(bp))
6059                 return 0;
6060
6061         rc = __bnxt_reserve_rings(bp);
6062         if (rc) {
6063                 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc);
6064                 return rc;
6065         }
6066         if ((bp->flags & BNXT_FLAG_NEW_RM) &&
6067             (bnxt_get_num_msix(bp) != bp->total_irqs)) {
6068                 bnxt_ulp_irq_stop(bp);
6069                 bnxt_clear_int_mode(bp);
6070                 rc = bnxt_init_int_mode(bp);
6071                 bnxt_ulp_irq_restart(bp, rc);
6072                 if (rc)
6073                         return rc;
6074         }
6075         if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
6076                 netdev_err(bp->dev, "tx ring reservation failure\n");
6077                 netdev_reset_tc(bp->dev);
6078                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
6079                 return -ENOMEM;
6080         }
6081         bp->num_stat_ctxs = bp->cp_nr_rings;
6082         return 0;
6083 }
6084
6085 static void bnxt_free_irq(struct bnxt *bp)
6086 {
6087         struct bnxt_irq *irq;
6088         int i;
6089
6090 #ifdef CONFIG_RFS_ACCEL
6091         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
6092         bp->dev->rx_cpu_rmap = NULL;
6093 #endif
6094         if (!bp->irq_tbl || !bp->bnapi)
6095                 return;
6096
6097         for (i = 0; i < bp->cp_nr_rings; i++) {
6098                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6099
6100                 irq = &bp->irq_tbl[map_idx];
6101                 if (irq->requested) {
6102                         if (irq->have_cpumask) {
6103                                 irq_set_affinity_hint(irq->vector, NULL);
6104                                 free_cpumask_var(irq->cpu_mask);
6105                                 irq->have_cpumask = 0;
6106                         }
6107                         free_irq(irq->vector, bp->bnapi[i]);
6108                 }
6109
6110                 irq->requested = 0;
6111         }
6112 }
6113
6114 static int bnxt_request_irq(struct bnxt *bp)
6115 {
6116         int i, j, rc = 0;
6117         unsigned long flags = 0;
6118 #ifdef CONFIG_RFS_ACCEL
6119         struct cpu_rmap *rmap;
6120 #endif
6121
6122         rc = bnxt_setup_int_mode(bp);
6123         if (rc) {
6124                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6125                            rc);
6126                 return rc;
6127         }
6128 #ifdef CONFIG_RFS_ACCEL
6129         rmap = bp->dev->rx_cpu_rmap;
6130 #endif
6131         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
6132                 flags = IRQF_SHARED;
6133
6134         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
6135                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6136                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
6137
6138 #ifdef CONFIG_RFS_ACCEL
6139                 if (rmap && bp->bnapi[i]->rx_ring) {
6140                         rc = irq_cpu_rmap_add(rmap, irq->vector);
6141                         if (rc)
6142                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
6143                                             j);
6144                         j++;
6145                 }
6146 #endif
6147                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6148                                  bp->bnapi[i]);
6149                 if (rc)
6150                         break;
6151
6152                 irq->requested = 1;
6153
6154                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
6155                         int numa_node = dev_to_node(&bp->pdev->dev);
6156
6157                         irq->have_cpumask = 1;
6158                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
6159                                         irq->cpu_mask);
6160                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
6161                         if (rc) {
6162                                 netdev_warn(bp->dev,
6163                                             "Set affinity failed, IRQ = %d\n",
6164                                             irq->vector);
6165                                 break;
6166                         }
6167                 }
6168         }
6169         return rc;
6170 }
6171
6172 static void bnxt_del_napi(struct bnxt *bp)
6173 {
6174         int i;
6175
6176         if (!bp->bnapi)
6177                 return;
6178
6179         for (i = 0; i < bp->cp_nr_rings; i++) {
6180                 struct bnxt_napi *bnapi = bp->bnapi[i];
6181
6182                 napi_hash_del(&bnapi->napi);
6183                 netif_napi_del(&bnapi->napi);
6184         }
6185         /* We called napi_hash_del() before netif_napi_del(), we need
6186          * to respect an RCU grace period before freeing napi structures.
6187          */
6188         synchronize_net();
6189 }
6190
6191 static void bnxt_init_napi(struct bnxt *bp)
6192 {
6193         int i;
6194         unsigned int cp_nr_rings = bp->cp_nr_rings;
6195         struct bnxt_napi *bnapi;
6196
6197         if (bp->flags & BNXT_FLAG_USING_MSIX) {
6198                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6199                         cp_nr_rings--;
6200                 for (i = 0; i < cp_nr_rings; i++) {
6201                         bnapi = bp->bnapi[i];
6202                         netif_napi_add(bp->dev, &bnapi->napi,
6203                                        bnxt_poll, 64);
6204                 }
6205                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6206                         bnapi = bp->bnapi[cp_nr_rings];
6207                         netif_napi_add(bp->dev, &bnapi->napi,
6208                                        bnxt_poll_nitroa0, 64);
6209                 }
6210         } else {
6211                 bnapi = bp->bnapi[0];
6212                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
6213         }
6214 }
6215
6216 static void bnxt_disable_napi(struct bnxt *bp)
6217 {
6218         int i;
6219
6220         if (!bp->bnapi)
6221                 return;
6222
6223         for (i = 0; i < bp->cp_nr_rings; i++) {
6224                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6225
6226                 if (bp->bnapi[i]->rx_ring)
6227                         cancel_work_sync(&cpr->dim.work);
6228
6229                 napi_disable(&bp->bnapi[i]->napi);
6230         }
6231 }
6232
6233 static void bnxt_enable_napi(struct bnxt *bp)
6234 {
6235         int i;
6236
6237         for (i = 0; i < bp->cp_nr_rings; i++) {
6238                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6239                 bp->bnapi[i]->in_reset = false;
6240
6241                 if (bp->bnapi[i]->rx_ring) {
6242                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
6243                         cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
6244                 }
6245                 napi_enable(&bp->bnapi[i]->napi);
6246         }
6247 }
6248
6249 void bnxt_tx_disable(struct bnxt *bp)
6250 {
6251         int i;
6252         struct bnxt_tx_ring_info *txr;
6253
6254         if (bp->tx_ring) {
6255                 for (i = 0; i < bp->tx_nr_rings; i++) {
6256                         txr = &bp->tx_ring[i];
6257                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
6258                 }
6259         }
6260         /* Stop all TX queues */
6261         netif_tx_disable(bp->dev);
6262         netif_carrier_off(bp->dev);
6263 }
6264
6265 void bnxt_tx_enable(struct bnxt *bp)
6266 {
6267         int i;
6268         struct bnxt_tx_ring_info *txr;
6269
6270         for (i = 0; i < bp->tx_nr_rings; i++) {
6271                 txr = &bp->tx_ring[i];
6272                 txr->dev_state = 0;
6273         }
6274         netif_tx_wake_all_queues(bp->dev);
6275         if (bp->link_info.link_up)
6276                 netif_carrier_on(bp->dev);
6277 }
6278
6279 static void bnxt_report_link(struct bnxt *bp)
6280 {
6281         if (bp->link_info.link_up) {
6282                 const char *duplex;
6283                 const char *flow_ctrl;
6284                 u32 speed;
6285                 u16 fec;
6286
6287                 netif_carrier_on(bp->dev);
6288                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
6289                         duplex = "full";
6290                 else
6291                         duplex = "half";
6292                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
6293                         flow_ctrl = "ON - receive & transmit";
6294                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
6295                         flow_ctrl = "ON - transmit";
6296                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
6297                         flow_ctrl = "ON - receive";
6298                 else
6299                         flow_ctrl = "none";
6300                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
6301                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
6302                             speed, duplex, flow_ctrl);
6303                 if (bp->flags & BNXT_FLAG_EEE_CAP)
6304                         netdev_info(bp->dev, "EEE is %s\n",
6305                                     bp->eee.eee_active ? "active" :
6306                                                          "not active");
6307                 fec = bp->link_info.fec_cfg;
6308                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
6309                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
6310                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
6311                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
6312                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
6313         } else {
6314                 netif_carrier_off(bp->dev);
6315                 netdev_err(bp->dev, "NIC Link is Down\n");
6316         }
6317 }
6318
6319 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
6320 {
6321         int rc = 0;
6322         struct hwrm_port_phy_qcaps_input req = {0};
6323         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6324         struct bnxt_link_info *link_info = &bp->link_info;
6325
6326         if (bp->hwrm_spec_code < 0x10201)
6327                 return 0;
6328
6329         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
6330
6331         mutex_lock(&bp->hwrm_cmd_lock);
6332         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6333         if (rc)
6334                 goto hwrm_phy_qcaps_exit;
6335
6336         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
6337                 struct ethtool_eee *eee = &bp->eee;
6338                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
6339
6340                 bp->flags |= BNXT_FLAG_EEE_CAP;
6341                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6342                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
6343                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
6344                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
6345                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
6346         }
6347         if (resp->supported_speeds_auto_mode)
6348                 link_info->support_auto_speeds =
6349                         le16_to_cpu(resp->supported_speeds_auto_mode);
6350
6351         bp->port_count = resp->port_cnt;
6352
6353 hwrm_phy_qcaps_exit:
6354         mutex_unlock(&bp->hwrm_cmd_lock);
6355         return rc;
6356 }
6357
6358 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
6359 {
6360         int rc = 0;
6361         struct bnxt_link_info *link_info = &bp->link_info;
6362         struct hwrm_port_phy_qcfg_input req = {0};
6363         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6364         u8 link_up = link_info->link_up;
6365         u16 diff;
6366
6367         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
6368
6369         mutex_lock(&bp->hwrm_cmd_lock);
6370         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6371         if (rc) {
6372                 mutex_unlock(&bp->hwrm_cmd_lock);
6373                 return rc;
6374         }
6375
6376         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
6377         link_info->phy_link_status = resp->link;
6378         link_info->duplex = resp->duplex_cfg;
6379         if (bp->hwrm_spec_code >= 0x10800)
6380                 link_info->duplex = resp->duplex_state;
6381         link_info->pause = resp->pause;
6382         link_info->auto_mode = resp->auto_mode;
6383         link_info->auto_pause_setting = resp->auto_pause;
6384         link_info->lp_pause = resp->link_partner_adv_pause;
6385         link_info->force_pause_setting = resp->force_pause;
6386         link_info->duplex_setting = resp->duplex_cfg;
6387         if (link_info->phy_link_status == BNXT_LINK_LINK)
6388                 link_info->link_speed = le16_to_cpu(resp->link_speed);
6389         else
6390                 link_info->link_speed = 0;
6391         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
6392         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
6393         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
6394         link_info->lp_auto_link_speeds =
6395                 le16_to_cpu(resp->link_partner_adv_speeds);
6396         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
6397         link_info->phy_ver[0] = resp->phy_maj;
6398         link_info->phy_ver[1] = resp->phy_min;
6399         link_info->phy_ver[2] = resp->phy_bld;
6400         link_info->media_type = resp->media_type;
6401         link_info->phy_type = resp->phy_type;
6402         link_info->transceiver = resp->xcvr_pkg_type;
6403         link_info->phy_addr = resp->eee_config_phy_addr &
6404                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
6405         link_info->module_status = resp->module_status;
6406
6407         if (bp->flags & BNXT_FLAG_EEE_CAP) {
6408                 struct ethtool_eee *eee = &bp->eee;
6409                 u16 fw_speeds;
6410
6411                 eee->eee_active = 0;
6412                 if (resp->eee_config_phy_addr &
6413                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
6414                         eee->eee_active = 1;
6415                         fw_speeds = le16_to_cpu(
6416                                 resp->link_partner_adv_eee_link_speed_mask);
6417                         eee->lp_advertised =
6418                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6419                 }
6420
6421                 /* Pull initial EEE config */
6422                 if (!chng_link_state) {
6423                         if (resp->eee_config_phy_addr &
6424                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
6425                                 eee->eee_enabled = 1;
6426
6427                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
6428                         eee->advertised =
6429                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6430
6431                         if (resp->eee_config_phy_addr &
6432                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
6433                                 __le32 tmr;
6434
6435                                 eee->tx_lpi_enabled = 1;
6436                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
6437                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
6438                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
6439                         }
6440                 }
6441         }
6442
6443         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
6444         if (bp->hwrm_spec_code >= 0x10504)
6445                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
6446
6447         /* TODO: need to add more logic to report VF link */
6448         if (chng_link_state) {
6449                 if (link_info->phy_link_status == BNXT_LINK_LINK)
6450                         link_info->link_up = 1;
6451                 else
6452                         link_info->link_up = 0;
6453                 if (link_up != link_info->link_up)
6454                         bnxt_report_link(bp);
6455         } else {
6456                 /* alwasy link down if not require to update link state */
6457                 link_info->link_up = 0;
6458         }
6459         mutex_unlock(&bp->hwrm_cmd_lock);
6460
6461         diff = link_info->support_auto_speeds ^ link_info->advertising;
6462         if ((link_info->support_auto_speeds | diff) !=
6463             link_info->support_auto_speeds) {
6464                 /* An advertised speed is no longer supported, so we need to
6465                  * update the advertisement settings.  Caller holds RTNL
6466                  * so we can modify link settings.
6467                  */
6468                 link_info->advertising = link_info->support_auto_speeds;
6469                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
6470                         bnxt_hwrm_set_link_setting(bp, true, false);
6471         }
6472         return 0;
6473 }
6474
6475 static void bnxt_get_port_module_status(struct bnxt *bp)
6476 {
6477         struct bnxt_link_info *link_info = &bp->link_info;
6478         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
6479         u8 module_status;
6480
6481         if (bnxt_update_link(bp, true))
6482                 return;
6483
6484         module_status = link_info->module_status;
6485         switch (module_status) {
6486         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
6487         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6488         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6489                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6490                             bp->pf.port_id);
6491                 if (bp->hwrm_spec_code >= 0x10201) {
6492                         netdev_warn(bp->dev, "Module part number %s\n",
6493                                     resp->phy_vendor_partnumber);
6494                 }
6495                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6496                         netdev_warn(bp->dev, "TX is disabled\n");
6497                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6498                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6499         }
6500 }
6501
6502 static void
6503 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6504 {
6505         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
6506                 if (bp->hwrm_spec_code >= 0x10201)
6507                         req->auto_pause =
6508                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
6509                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6510                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6511                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6512                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
6513                 req->enables |=
6514                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6515         } else {
6516                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6517                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6518                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6519                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6520                 req->enables |=
6521                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
6522                 if (bp->hwrm_spec_code >= 0x10201) {
6523                         req->auto_pause = req->force_pause;
6524                         req->enables |= cpu_to_le32(
6525                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6526                 }
6527         }
6528 }
6529
6530 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6531                                       struct hwrm_port_phy_cfg_input *req)
6532 {
6533         u8 autoneg = bp->link_info.autoneg;
6534         u16 fw_link_speed = bp->link_info.req_link_speed;
6535         u16 advertising = bp->link_info.advertising;
6536
6537         if (autoneg & BNXT_AUTONEG_SPEED) {
6538                 req->auto_mode |=
6539                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6540
6541                 req->enables |= cpu_to_le32(
6542                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6543                 req->auto_link_speed_mask = cpu_to_le16(advertising);
6544
6545                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6546                 req->flags |=
6547                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6548         } else {
6549                 req->force_link_speed = cpu_to_le16(fw_link_speed);
6550                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6551         }
6552
6553         /* tell chimp that the setting takes effect immediately */
6554         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6555 }
6556
6557 int bnxt_hwrm_set_pause(struct bnxt *bp)
6558 {
6559         struct hwrm_port_phy_cfg_input req = {0};
6560         int rc;
6561
6562         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6563         bnxt_hwrm_set_pause_common(bp, &req);
6564
6565         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6566             bp->link_info.force_link_chng)
6567                 bnxt_hwrm_set_link_common(bp, &req);
6568
6569         mutex_lock(&bp->hwrm_cmd_lock);
6570         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6571         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6572                 /* since changing of pause setting doesn't trigger any link
6573                  * change event, the driver needs to update the current pause
6574                  * result upon successfully return of the phy_cfg command
6575                  */
6576                 bp->link_info.pause =
6577                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6578                 bp->link_info.auto_pause_setting = 0;
6579                 if (!bp->link_info.force_link_chng)
6580                         bnxt_report_link(bp);
6581         }
6582         bp->link_info.force_link_chng = false;
6583         mutex_unlock(&bp->hwrm_cmd_lock);
6584         return rc;
6585 }
6586
6587 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6588                               struct hwrm_port_phy_cfg_input *req)
6589 {
6590         struct ethtool_eee *eee = &bp->eee;
6591
6592         if (eee->eee_enabled) {
6593                 u16 eee_speeds;
6594                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6595
6596                 if (eee->tx_lpi_enabled)
6597                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6598                 else
6599                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6600
6601                 req->flags |= cpu_to_le32(flags);
6602                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6603                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6604                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6605         } else {
6606                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6607         }
6608 }
6609
6610 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6611 {
6612         struct hwrm_port_phy_cfg_input req = {0};
6613
6614         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6615         if (set_pause)
6616                 bnxt_hwrm_set_pause_common(bp, &req);
6617
6618         bnxt_hwrm_set_link_common(bp, &req);
6619
6620         if (set_eee)
6621                 bnxt_hwrm_set_eee(bp, &req);
6622         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6623 }
6624
6625 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6626 {
6627         struct hwrm_port_phy_cfg_input req = {0};
6628
6629         if (!BNXT_SINGLE_PF(bp))
6630                 return 0;
6631
6632         if (pci_num_vf(bp->pdev))
6633                 return 0;
6634
6635         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6636         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6637         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6638 }
6639
6640 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6641 {
6642         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6643         struct hwrm_port_led_qcaps_input req = {0};
6644         struct bnxt_pf_info *pf = &bp->pf;
6645         int rc;
6646
6647         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6648                 return 0;
6649
6650         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6651         req.port_id = cpu_to_le16(pf->port_id);
6652         mutex_lock(&bp->hwrm_cmd_lock);
6653         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6654         if (rc) {
6655                 mutex_unlock(&bp->hwrm_cmd_lock);
6656                 return rc;
6657         }
6658         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6659                 int i;
6660
6661                 bp->num_leds = resp->num_leds;
6662                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6663                                                  bp->num_leds);
6664                 for (i = 0; i < bp->num_leds; i++) {
6665                         struct bnxt_led_info *led = &bp->leds[i];
6666                         __le16 caps = led->led_state_caps;
6667
6668                         if (!led->led_group_id ||
6669                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
6670                                 bp->num_leds = 0;
6671                                 break;
6672                         }
6673                 }
6674         }
6675         mutex_unlock(&bp->hwrm_cmd_lock);
6676         return 0;
6677 }
6678
6679 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6680 {
6681         struct hwrm_wol_filter_alloc_input req = {0};
6682         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6683         int rc;
6684
6685         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6686         req.port_id = cpu_to_le16(bp->pf.port_id);
6687         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6688         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6689         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6690         mutex_lock(&bp->hwrm_cmd_lock);
6691         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6692         if (!rc)
6693                 bp->wol_filter_id = resp->wol_filter_id;
6694         mutex_unlock(&bp->hwrm_cmd_lock);
6695         return rc;
6696 }
6697
6698 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6699 {
6700         struct hwrm_wol_filter_free_input req = {0};
6701         int rc;
6702
6703         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6704         req.port_id = cpu_to_le16(bp->pf.port_id);
6705         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6706         req.wol_filter_id = bp->wol_filter_id;
6707         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6708         return rc;
6709 }
6710
6711 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6712 {
6713         struct hwrm_wol_filter_qcfg_input req = {0};
6714         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6715         u16 next_handle = 0;
6716         int rc;
6717
6718         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6719         req.port_id = cpu_to_le16(bp->pf.port_id);
6720         req.handle = cpu_to_le16(handle);
6721         mutex_lock(&bp->hwrm_cmd_lock);
6722         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6723         if (!rc) {
6724                 next_handle = le16_to_cpu(resp->next_handle);
6725                 if (next_handle != 0) {
6726                         if (resp->wol_type ==
6727                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6728                                 bp->wol = 1;
6729                                 bp->wol_filter_id = resp->wol_filter_id;
6730                         }
6731                 }
6732         }
6733         mutex_unlock(&bp->hwrm_cmd_lock);
6734         return next_handle;
6735 }
6736
6737 static void bnxt_get_wol_settings(struct bnxt *bp)
6738 {
6739         u16 handle = 0;
6740
6741         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6742                 return;
6743
6744         do {
6745                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6746         } while (handle && handle != 0xffff);
6747 }
6748
6749 static bool bnxt_eee_config_ok(struct bnxt *bp)
6750 {
6751         struct ethtool_eee *eee = &bp->eee;
6752         struct bnxt_link_info *link_info = &bp->link_info;
6753
6754         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6755                 return true;
6756
6757         if (eee->eee_enabled) {
6758                 u32 advertising =
6759                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6760
6761                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6762                         eee->eee_enabled = 0;
6763                         return false;
6764                 }
6765                 if (eee->advertised & ~advertising) {
6766                         eee->advertised = advertising & eee->supported;
6767                         return false;
6768                 }
6769         }
6770         return true;
6771 }
6772
6773 static int bnxt_update_phy_setting(struct bnxt *bp)
6774 {
6775         int rc;
6776         bool update_link = false;
6777         bool update_pause = false;
6778         bool update_eee = false;
6779         struct bnxt_link_info *link_info = &bp->link_info;
6780
6781         rc = bnxt_update_link(bp, true);
6782         if (rc) {
6783                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6784                            rc);
6785                 return rc;
6786         }
6787         if (!BNXT_SINGLE_PF(bp))
6788                 return 0;
6789
6790         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6791             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6792             link_info->req_flow_ctrl)
6793                 update_pause = true;
6794         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6795             link_info->force_pause_setting != link_info->req_flow_ctrl)
6796                 update_pause = true;
6797         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6798                 if (BNXT_AUTO_MODE(link_info->auto_mode))
6799                         update_link = true;
6800                 if (link_info->req_link_speed != link_info->force_link_speed)
6801                         update_link = true;
6802                 if (link_info->req_duplex != link_info->duplex_setting)
6803                         update_link = true;
6804         } else {
6805                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6806                         update_link = true;
6807                 if (link_info->advertising != link_info->auto_link_speeds)
6808                         update_link = true;
6809         }
6810
6811         /* The last close may have shutdown the link, so need to call
6812          * PHY_CFG to bring it back up.
6813          */
6814         if (!netif_carrier_ok(bp->dev))
6815                 update_link = true;
6816
6817         if (!bnxt_eee_config_ok(bp))
6818                 update_eee = true;
6819
6820         if (update_link)
6821                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6822         else if (update_pause)
6823                 rc = bnxt_hwrm_set_pause(bp);
6824         if (rc) {
6825                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6826                            rc);
6827                 return rc;
6828         }
6829
6830         return rc;
6831 }
6832
6833 /* Common routine to pre-map certain register block to different GRC window.
6834  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6835  * in PF and 3 windows in VF that can be customized to map in different
6836  * register blocks.
6837  */
6838 static void bnxt_preset_reg_win(struct bnxt *bp)
6839 {
6840         if (BNXT_PF(bp)) {
6841                 /* CAG registers map to GRC window #4 */
6842                 writel(BNXT_CAG_REG_BASE,
6843                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6844         }
6845 }
6846
6847 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
6848
6849 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6850 {
6851         int rc = 0;
6852
6853         bnxt_preset_reg_win(bp);
6854         netif_carrier_off(bp->dev);
6855         if (irq_re_init) {
6856                 /* Reserve rings now if none were reserved at driver probe. */
6857                 rc = bnxt_init_dflt_ring_mode(bp);
6858                 if (rc) {
6859                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
6860                         return rc;
6861                 }
6862                 rc = bnxt_reserve_rings(bp);
6863                 if (rc)
6864                         return rc;
6865         }
6866         if ((bp->flags & BNXT_FLAG_RFS) &&
6867             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6868                 /* disable RFS if falling back to INTA */
6869                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6870                 bp->flags &= ~BNXT_FLAG_RFS;
6871         }
6872
6873         rc = bnxt_alloc_mem(bp, irq_re_init);
6874         if (rc) {
6875                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6876                 goto open_err_free_mem;
6877         }
6878
6879         if (irq_re_init) {
6880                 bnxt_init_napi(bp);
6881                 rc = bnxt_request_irq(bp);
6882                 if (rc) {
6883                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6884                         goto open_err;
6885                 }
6886         }
6887
6888         bnxt_enable_napi(bp);
6889         bnxt_debug_dev_init(bp);
6890
6891         rc = bnxt_init_nic(bp, irq_re_init);
6892         if (rc) {
6893                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6894                 goto open_err;
6895         }
6896
6897         if (link_re_init) {
6898                 mutex_lock(&bp->link_lock);
6899                 rc = bnxt_update_phy_setting(bp);
6900                 mutex_unlock(&bp->link_lock);
6901                 if (rc)
6902                         netdev_warn(bp->dev, "failed to update phy settings\n");
6903         }
6904
6905         if (irq_re_init)
6906                 udp_tunnel_get_rx_info(bp->dev);
6907
6908         set_bit(BNXT_STATE_OPEN, &bp->state);
6909         bnxt_enable_int(bp);
6910         /* Enable TX queues */
6911         bnxt_tx_enable(bp);
6912         mod_timer(&bp->timer, jiffies + bp->current_interval);
6913         /* Poll link status and check for SFP+ module status */
6914         bnxt_get_port_module_status(bp);
6915
6916         /* VF-reps may need to be re-opened after the PF is re-opened */
6917         if (BNXT_PF(bp))
6918                 bnxt_vf_reps_open(bp);
6919         return 0;
6920
6921 open_err:
6922         bnxt_debug_dev_exit(bp);
6923         bnxt_disable_napi(bp);
6924         bnxt_del_napi(bp);
6925
6926 open_err_free_mem:
6927         bnxt_free_skbs(bp);
6928         bnxt_free_irq(bp);
6929         bnxt_free_mem(bp, true);
6930         return rc;
6931 }
6932
6933 /* rtnl_lock held */
6934 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6935 {
6936         int rc = 0;
6937
6938         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6939         if (rc) {
6940                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6941                 dev_close(bp->dev);
6942         }
6943         return rc;
6944 }
6945
6946 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6947  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
6948  * self tests.
6949  */
6950 int bnxt_half_open_nic(struct bnxt *bp)
6951 {
6952         int rc = 0;
6953
6954         rc = bnxt_alloc_mem(bp, false);
6955         if (rc) {
6956                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6957                 goto half_open_err;
6958         }
6959         rc = bnxt_init_nic(bp, false);
6960         if (rc) {
6961                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6962                 goto half_open_err;
6963         }
6964         return 0;
6965
6966 half_open_err:
6967         bnxt_free_skbs(bp);
6968         bnxt_free_mem(bp, false);
6969         dev_close(bp->dev);
6970         return rc;
6971 }
6972
6973 /* rtnl_lock held, this call can only be made after a previous successful
6974  * call to bnxt_half_open_nic().
6975  */
6976 void bnxt_half_close_nic(struct bnxt *bp)
6977 {
6978         bnxt_hwrm_resource_free(bp, false, false);
6979         bnxt_free_skbs(bp);
6980         bnxt_free_mem(bp, false);
6981 }
6982
6983 static int bnxt_open(struct net_device *dev)
6984 {
6985         struct bnxt *bp = netdev_priv(dev);
6986
6987         return __bnxt_open_nic(bp, true, true);
6988 }
6989
6990 static bool bnxt_drv_busy(struct bnxt *bp)
6991 {
6992         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
6993                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
6994 }
6995
6996 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
6997                              bool link_re_init)
6998 {
6999         /* Close the VF-reps before closing PF */
7000         if (BNXT_PF(bp))
7001                 bnxt_vf_reps_close(bp);
7002
7003         /* Change device state to avoid TX queue wake up's */
7004         bnxt_tx_disable(bp);
7005
7006         clear_bit(BNXT_STATE_OPEN, &bp->state);
7007         smp_mb__after_atomic();
7008         while (bnxt_drv_busy(bp))
7009                 msleep(20);
7010
7011         /* Flush rings and and disable interrupts */
7012         bnxt_shutdown_nic(bp, irq_re_init);
7013
7014         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
7015
7016         bnxt_debug_dev_exit(bp);
7017         bnxt_disable_napi(bp);
7018         del_timer_sync(&bp->timer);
7019         bnxt_free_skbs(bp);
7020
7021         if (irq_re_init) {
7022                 bnxt_free_irq(bp);
7023                 bnxt_del_napi(bp);
7024         }
7025         bnxt_free_mem(bp, irq_re_init);
7026 }
7027
7028 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7029 {
7030         int rc = 0;
7031
7032 #ifdef CONFIG_BNXT_SRIOV
7033         if (bp->sriov_cfg) {
7034                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
7035                                                       !bp->sriov_cfg,
7036                                                       BNXT_SRIOV_CFG_WAIT_TMO);
7037                 if (rc)
7038                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
7039         }
7040 #endif
7041         __bnxt_close_nic(bp, irq_re_init, link_re_init);
7042         return rc;
7043 }
7044
7045 static int bnxt_close(struct net_device *dev)
7046 {
7047         struct bnxt *bp = netdev_priv(dev);
7048
7049         bnxt_close_nic(bp, true, true);
7050         bnxt_hwrm_shutdown_link(bp);
7051         return 0;
7052 }
7053
7054 /* rtnl_lock held */
7055 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7056 {
7057         switch (cmd) {
7058         case SIOCGMIIPHY:
7059                 /* fallthru */
7060         case SIOCGMIIREG: {
7061                 if (!netif_running(dev))
7062                         return -EAGAIN;
7063
7064                 return 0;
7065         }
7066
7067         case SIOCSMIIREG:
7068                 if (!netif_running(dev))
7069                         return -EAGAIN;
7070
7071                 return 0;
7072
7073         default:
7074                 /* do nothing */
7075                 break;
7076         }
7077         return -EOPNOTSUPP;
7078 }
7079
7080 static void
7081 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7082 {
7083         u32 i;
7084         struct bnxt *bp = netdev_priv(dev);
7085
7086         set_bit(BNXT_STATE_READ_STATS, &bp->state);
7087         /* Make sure bnxt_close_nic() sees that we are reading stats before
7088          * we check the BNXT_STATE_OPEN flag.
7089          */
7090         smp_mb__after_atomic();
7091         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7092                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7093                 return;
7094         }
7095
7096         /* TODO check if we need to synchronize with bnxt_close path */
7097         for (i = 0; i < bp->cp_nr_rings; i++) {
7098                 struct bnxt_napi *bnapi = bp->bnapi[i];
7099                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7100                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
7101
7102                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
7103                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
7104                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
7105
7106                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
7107                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
7108                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
7109
7110                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
7111                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
7112                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
7113
7114                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
7115                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
7116                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
7117
7118                 stats->rx_missed_errors +=
7119                         le64_to_cpu(hw_stats->rx_discard_pkts);
7120
7121                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
7122
7123                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
7124         }
7125
7126         if (bp->flags & BNXT_FLAG_PORT_STATS) {
7127                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
7128                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
7129
7130                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
7131                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
7132                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
7133                                           le64_to_cpu(rx->rx_ovrsz_frames) +
7134                                           le64_to_cpu(rx->rx_runt_frames);
7135                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
7136                                    le64_to_cpu(rx->rx_jbr_frames);
7137                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
7138                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
7139                 stats->tx_errors = le64_to_cpu(tx->tx_err);
7140         }
7141         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7142 }
7143
7144 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
7145 {
7146         struct net_device *dev = bp->dev;
7147         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7148         struct netdev_hw_addr *ha;
7149         u8 *haddr;
7150         int mc_count = 0;
7151         bool update = false;
7152         int off = 0;
7153
7154         netdev_for_each_mc_addr(ha, dev) {
7155                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
7156                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7157                         vnic->mc_list_count = 0;
7158                         return false;
7159                 }
7160                 haddr = ha->addr;
7161                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
7162                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
7163                         update = true;
7164                 }
7165                 off += ETH_ALEN;
7166                 mc_count++;
7167         }
7168         if (mc_count)
7169                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
7170
7171         if (mc_count != vnic->mc_list_count) {
7172                 vnic->mc_list_count = mc_count;
7173                 update = true;
7174         }
7175         return update;
7176 }
7177
7178 static bool bnxt_uc_list_updated(struct bnxt *bp)
7179 {
7180         struct net_device *dev = bp->dev;
7181         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7182         struct netdev_hw_addr *ha;
7183         int off = 0;
7184
7185         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
7186                 return true;
7187
7188         netdev_for_each_uc_addr(ha, dev) {
7189                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
7190                         return true;
7191
7192                 off += ETH_ALEN;
7193         }
7194         return false;
7195 }
7196
7197 static void bnxt_set_rx_mode(struct net_device *dev)
7198 {
7199         struct bnxt *bp = netdev_priv(dev);
7200         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7201         u32 mask = vnic->rx_mask;
7202         bool mc_update = false;
7203         bool uc_update;
7204
7205         if (!netif_running(dev))
7206                 return;
7207
7208         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
7209                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
7210                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
7211
7212         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7213                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7214
7215         uc_update = bnxt_uc_list_updated(bp);
7216
7217         if (dev->flags & IFF_ALLMULTI) {
7218                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7219                 vnic->mc_list_count = 0;
7220         } else {
7221                 mc_update = bnxt_mc_list_updated(bp, &mask);
7222         }
7223
7224         if (mask != vnic->rx_mask || uc_update || mc_update) {
7225                 vnic->rx_mask = mask;
7226
7227                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
7228                 bnxt_queue_sp_work(bp);
7229         }
7230 }
7231
7232 static int bnxt_cfg_rx_mode(struct bnxt *bp)
7233 {
7234         struct net_device *dev = bp->dev;
7235         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7236         struct netdev_hw_addr *ha;
7237         int i, off = 0, rc;
7238         bool uc_update;
7239
7240         netif_addr_lock_bh(dev);
7241         uc_update = bnxt_uc_list_updated(bp);
7242         netif_addr_unlock_bh(dev);
7243
7244         if (!uc_update)
7245                 goto skip_uc;
7246
7247         mutex_lock(&bp->hwrm_cmd_lock);
7248         for (i = 1; i < vnic->uc_filter_count; i++) {
7249                 struct hwrm_cfa_l2_filter_free_input req = {0};
7250
7251                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
7252                                        -1);
7253
7254                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
7255
7256                 rc = _hwrm_send_message(bp, &req, sizeof(req),
7257                                         HWRM_CMD_TIMEOUT);
7258         }
7259         mutex_unlock(&bp->hwrm_cmd_lock);
7260
7261         vnic->uc_filter_count = 1;
7262
7263         netif_addr_lock_bh(dev);
7264         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
7265                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7266         } else {
7267                 netdev_for_each_uc_addr(ha, dev) {
7268                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
7269                         off += ETH_ALEN;
7270                         vnic->uc_filter_count++;
7271                 }
7272         }
7273         netif_addr_unlock_bh(dev);
7274
7275         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
7276                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
7277                 if (rc) {
7278                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
7279                                    rc);
7280                         vnic->uc_filter_count = i;
7281                         return rc;
7282                 }
7283         }
7284
7285 skip_uc:
7286         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7287         if (rc)
7288                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
7289                            rc);
7290
7291         return rc;
7292 }
7293
7294 static bool bnxt_can_reserve_rings(struct bnxt *bp)
7295 {
7296 #ifdef CONFIG_BNXT_SRIOV
7297         if ((bp->flags & BNXT_FLAG_NEW_RM) && BNXT_VF(bp)) {
7298                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7299
7300                 /* No minimum rings were provisioned by the PF.  Don't
7301                  * reserve rings by default when device is down.
7302                  */
7303                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
7304                         return true;
7305
7306                 if (!netif_running(bp->dev))
7307                         return false;
7308         }
7309 #endif
7310         return true;
7311 }
7312
7313 /* If the chip and firmware supports RFS */
7314 static bool bnxt_rfs_supported(struct bnxt *bp)
7315 {
7316         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
7317                 return true;
7318         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7319                 return true;
7320         return false;
7321 }
7322
7323 /* If runtime conditions support RFS */
7324 static bool bnxt_rfs_capable(struct bnxt *bp)
7325 {
7326 #ifdef CONFIG_RFS_ACCEL
7327         int vnics, max_vnics, max_rss_ctxs;
7328
7329         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
7330                 return false;
7331
7332         vnics = 1 + bp->rx_nr_rings;
7333         max_vnics = bnxt_get_max_func_vnics(bp);
7334         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
7335
7336         /* RSS contexts not a limiting factor */
7337         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7338                 max_rss_ctxs = max_vnics;
7339         if (vnics > max_vnics || vnics > max_rss_ctxs) {
7340                 if (bp->rx_nr_rings > 1)
7341                         netdev_warn(bp->dev,
7342                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
7343                                     min(max_rss_ctxs - 1, max_vnics - 1));
7344                 return false;
7345         }
7346
7347         if (!(bp->flags & BNXT_FLAG_NEW_RM))
7348                 return true;
7349
7350         if (vnics == bp->hw_resc.resv_vnics)
7351                 return true;
7352
7353         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
7354         if (vnics <= bp->hw_resc.resv_vnics)
7355                 return true;
7356
7357         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
7358         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
7359         return false;
7360 #else
7361         return false;
7362 #endif
7363 }
7364
7365 static netdev_features_t bnxt_fix_features(struct net_device *dev,
7366                                            netdev_features_t features)
7367 {
7368         struct bnxt *bp = netdev_priv(dev);
7369
7370         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
7371                 features &= ~NETIF_F_NTUPLE;
7372
7373         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7374                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7375
7376         if (!(features & NETIF_F_GRO))
7377                 features &= ~NETIF_F_GRO_HW;
7378
7379         if (features & NETIF_F_GRO_HW)
7380                 features &= ~NETIF_F_LRO;
7381
7382         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
7383          * turned on or off together.
7384          */
7385         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
7386             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
7387                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
7388                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7389                                       NETIF_F_HW_VLAN_STAG_RX);
7390                 else
7391                         features |= NETIF_F_HW_VLAN_CTAG_RX |
7392                                     NETIF_F_HW_VLAN_STAG_RX;
7393         }
7394 #ifdef CONFIG_BNXT_SRIOV
7395         if (BNXT_VF(bp)) {
7396                 if (bp->vf.vlan) {
7397                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7398                                       NETIF_F_HW_VLAN_STAG_RX);
7399                 }
7400         }
7401 #endif
7402         return features;
7403 }
7404
7405 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
7406 {
7407         struct bnxt *bp = netdev_priv(dev);
7408         u32 flags = bp->flags;
7409         u32 changes;
7410         int rc = 0;
7411         bool re_init = false;
7412         bool update_tpa = false;
7413
7414         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
7415         if (features & NETIF_F_GRO_HW)
7416                 flags |= BNXT_FLAG_GRO;
7417         else if (features & NETIF_F_LRO)
7418                 flags |= BNXT_FLAG_LRO;
7419
7420         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7421                 flags &= ~BNXT_FLAG_TPA;
7422
7423         if (features & NETIF_F_HW_VLAN_CTAG_RX)
7424                 flags |= BNXT_FLAG_STRIP_VLAN;
7425
7426         if (features & NETIF_F_NTUPLE)
7427                 flags |= BNXT_FLAG_RFS;
7428
7429         changes = flags ^ bp->flags;
7430         if (changes & BNXT_FLAG_TPA) {
7431                 update_tpa = true;
7432                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
7433                     (flags & BNXT_FLAG_TPA) == 0)
7434                         re_init = true;
7435         }
7436
7437         if (changes & ~BNXT_FLAG_TPA)
7438                 re_init = true;
7439
7440         if (flags != bp->flags) {
7441                 u32 old_flags = bp->flags;
7442
7443                 bp->flags = flags;
7444
7445                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7446                         if (update_tpa)
7447                                 bnxt_set_ring_params(bp);
7448                         return rc;
7449                 }
7450
7451                 if (re_init) {
7452                         bnxt_close_nic(bp, false, false);
7453                         if (update_tpa)
7454                                 bnxt_set_ring_params(bp);
7455
7456                         return bnxt_open_nic(bp, false, false);
7457                 }
7458                 if (update_tpa) {
7459                         rc = bnxt_set_tpa(bp,
7460                                           (flags & BNXT_FLAG_TPA) ?
7461                                           true : false);
7462                         if (rc)
7463                                 bp->flags = old_flags;
7464                 }
7465         }
7466         return rc;
7467 }
7468
7469 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
7470 {
7471         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
7472         int i = bnapi->index;
7473
7474         if (!txr)
7475                 return;
7476
7477         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
7478                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
7479                     txr->tx_cons);
7480 }
7481
7482 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
7483 {
7484         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
7485         int i = bnapi->index;
7486
7487         if (!rxr)
7488                 return;
7489
7490         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
7491                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
7492                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
7493                     rxr->rx_sw_agg_prod);
7494 }
7495
7496 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
7497 {
7498         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7499         int i = bnapi->index;
7500
7501         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
7502                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
7503 }
7504
7505 static void bnxt_dbg_dump_states(struct bnxt *bp)
7506 {
7507         int i;
7508         struct bnxt_napi *bnapi;
7509
7510         for (i = 0; i < bp->cp_nr_rings; i++) {
7511                 bnapi = bp->bnapi[i];
7512                 if (netif_msg_drv(bp)) {
7513                         bnxt_dump_tx_sw_state(bnapi);
7514                         bnxt_dump_rx_sw_state(bnapi);
7515                         bnxt_dump_cp_sw_state(bnapi);
7516                 }
7517         }
7518 }
7519
7520 static void bnxt_reset_task(struct bnxt *bp, bool silent)
7521 {
7522         if (!silent)
7523                 bnxt_dbg_dump_states(bp);
7524         if (netif_running(bp->dev)) {
7525                 int rc;
7526
7527                 if (!silent)
7528                         bnxt_ulp_stop(bp);
7529                 bnxt_close_nic(bp, false, false);
7530                 rc = bnxt_open_nic(bp, false, false);
7531                 if (!silent && !rc)
7532                         bnxt_ulp_start(bp);
7533         }
7534 }
7535
7536 static void bnxt_tx_timeout(struct net_device *dev)
7537 {
7538         struct bnxt *bp = netdev_priv(dev);
7539
7540         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
7541         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
7542         bnxt_queue_sp_work(bp);
7543 }
7544
7545 #ifdef CONFIG_NET_POLL_CONTROLLER
7546 static void bnxt_poll_controller(struct net_device *dev)
7547 {
7548         struct bnxt *bp = netdev_priv(dev);
7549         int i;
7550
7551         /* Only process tx rings/combined rings in netpoll mode. */
7552         for (i = 0; i < bp->tx_nr_rings; i++) {
7553                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
7554
7555                 napi_schedule(&txr->bnapi->napi);
7556         }
7557 }
7558 #endif
7559
7560 static void bnxt_timer(struct timer_list *t)
7561 {
7562         struct bnxt *bp = from_timer(bp, t, timer);
7563         struct net_device *dev = bp->dev;
7564
7565         if (!netif_running(dev))
7566                 return;
7567
7568         if (atomic_read(&bp->intr_sem) != 0)
7569                 goto bnxt_restart_timer;
7570
7571         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7572             bp->stats_coal_ticks) {
7573                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
7574                 bnxt_queue_sp_work(bp);
7575         }
7576
7577         if (bnxt_tc_flower_enabled(bp)) {
7578                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
7579                 bnxt_queue_sp_work(bp);
7580         }
7581 bnxt_restart_timer:
7582         mod_timer(&bp->timer, jiffies + bp->current_interval);
7583 }
7584
7585 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
7586 {
7587         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7588          * set.  If the device is being closed, bnxt_close() may be holding
7589          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
7590          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7591          */
7592         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7593         rtnl_lock();
7594 }
7595
7596 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7597 {
7598         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7599         rtnl_unlock();
7600 }
7601
7602 /* Only called from bnxt_sp_task() */
7603 static void bnxt_reset(struct bnxt *bp, bool silent)
7604 {
7605         bnxt_rtnl_lock_sp(bp);
7606         if (test_bit(BNXT_STATE_OPEN, &bp->state))
7607                 bnxt_reset_task(bp, silent);
7608         bnxt_rtnl_unlock_sp(bp);
7609 }
7610
7611 static void bnxt_cfg_ntp_filters(struct bnxt *);
7612
7613 static void bnxt_sp_task(struct work_struct *work)
7614 {
7615         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
7616
7617         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7618         smp_mb__after_atomic();
7619         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7620                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7621                 return;
7622         }
7623
7624         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7625                 bnxt_cfg_rx_mode(bp);
7626
7627         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7628                 bnxt_cfg_ntp_filters(bp);
7629         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7630                 bnxt_hwrm_exec_fwd_req(bp);
7631         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7632                 bnxt_hwrm_tunnel_dst_port_alloc(
7633                         bp, bp->vxlan_port,
7634                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7635         }
7636         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7637                 bnxt_hwrm_tunnel_dst_port_free(
7638                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7639         }
7640         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7641                 bnxt_hwrm_tunnel_dst_port_alloc(
7642                         bp, bp->nge_port,
7643                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7644         }
7645         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7646                 bnxt_hwrm_tunnel_dst_port_free(
7647                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7648         }
7649         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
7650                 bnxt_hwrm_port_qstats(bp);
7651                 bnxt_hwrm_port_qstats_ext(bp);
7652         }
7653
7654         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7655                 int rc;
7656
7657                 mutex_lock(&bp->link_lock);
7658                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7659                                        &bp->sp_event))
7660                         bnxt_hwrm_phy_qcaps(bp);
7661
7662                 rc = bnxt_update_link(bp, true);
7663                 mutex_unlock(&bp->link_lock);
7664                 if (rc)
7665                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7666                                    rc);
7667         }
7668         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7669                 mutex_lock(&bp->link_lock);
7670                 bnxt_get_port_module_status(bp);
7671                 mutex_unlock(&bp->link_lock);
7672         }
7673
7674         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7675                 bnxt_tc_flow_stats_work(bp);
7676
7677         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
7678          * must be the last functions to be called before exiting.
7679          */
7680         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7681                 bnxt_reset(bp, false);
7682
7683         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7684                 bnxt_reset(bp, true);
7685
7686         smp_mb__before_atomic();
7687         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7688 }
7689
7690 /* Under rtnl_lock */
7691 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7692                      int tx_xdp)
7693 {
7694         int max_rx, max_tx, tx_sets = 1;
7695         int tx_rings_needed;
7696         int rx_rings = rx;
7697         int cp, vnics, rc;
7698
7699         if (tcs)
7700                 tx_sets = tcs;
7701
7702         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7703         if (rc)
7704                 return rc;
7705
7706         if (max_rx < rx)
7707                 return -ENOMEM;
7708
7709         tx_rings_needed = tx * tx_sets + tx_xdp;
7710         if (max_tx < tx_rings_needed)
7711                 return -ENOMEM;
7712
7713         vnics = 1;
7714         if (bp->flags & BNXT_FLAG_RFS)
7715                 vnics += rx_rings;
7716
7717         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7718                 rx_rings <<= 1;
7719         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
7720         if (bp->flags & BNXT_FLAG_NEW_RM)
7721                 cp += bnxt_get_ulp_msix_num(bp);
7722         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
7723                                      vnics);
7724 }
7725
7726 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7727 {
7728         if (bp->bar2) {
7729                 pci_iounmap(pdev, bp->bar2);
7730                 bp->bar2 = NULL;
7731         }
7732
7733         if (bp->bar1) {
7734                 pci_iounmap(pdev, bp->bar1);
7735                 bp->bar1 = NULL;
7736         }
7737
7738         if (bp->bar0) {
7739                 pci_iounmap(pdev, bp->bar0);
7740                 bp->bar0 = NULL;
7741         }
7742 }
7743
7744 static void bnxt_cleanup_pci(struct bnxt *bp)
7745 {
7746         bnxt_unmap_bars(bp, bp->pdev);
7747         pci_release_regions(bp->pdev);
7748         pci_disable_device(bp->pdev);
7749 }
7750
7751 static void bnxt_init_dflt_coal(struct bnxt *bp)
7752 {
7753         struct bnxt_coal *coal;
7754
7755         /* Tick values in micro seconds.
7756          * 1 coal_buf x bufs_per_record = 1 completion record.
7757          */
7758         coal = &bp->rx_coal;
7759         coal->coal_ticks = 14;
7760         coal->coal_bufs = 30;
7761         coal->coal_ticks_irq = 1;
7762         coal->coal_bufs_irq = 2;
7763         coal->idle_thresh = 50;
7764         coal->bufs_per_record = 2;
7765         coal->budget = 64;              /* NAPI budget */
7766
7767         coal = &bp->tx_coal;
7768         coal->coal_ticks = 28;
7769         coal->coal_bufs = 30;
7770         coal->coal_ticks_irq = 2;
7771         coal->coal_bufs_irq = 2;
7772         coal->bufs_per_record = 1;
7773
7774         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7775 }
7776
7777 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7778 {
7779         int rc;
7780         struct bnxt *bp = netdev_priv(dev);
7781
7782         SET_NETDEV_DEV(dev, &pdev->dev);
7783
7784         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7785         rc = pci_enable_device(pdev);
7786         if (rc) {
7787                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7788                 goto init_err;
7789         }
7790
7791         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7792                 dev_err(&pdev->dev,
7793                         "Cannot find PCI device base address, aborting\n");
7794                 rc = -ENODEV;
7795                 goto init_err_disable;
7796         }
7797
7798         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7799         if (rc) {
7800                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7801                 goto init_err_disable;
7802         }
7803
7804         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7805             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7806                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7807                 goto init_err_disable;
7808         }
7809
7810         pci_set_master(pdev);
7811
7812         bp->dev = dev;
7813         bp->pdev = pdev;
7814
7815         bp->bar0 = pci_ioremap_bar(pdev, 0);
7816         if (!bp->bar0) {
7817                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7818                 rc = -ENOMEM;
7819                 goto init_err_release;
7820         }
7821
7822         bp->bar1 = pci_ioremap_bar(pdev, 2);
7823         if (!bp->bar1) {
7824                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7825                 rc = -ENOMEM;
7826                 goto init_err_release;
7827         }
7828
7829         bp->bar2 = pci_ioremap_bar(pdev, 4);
7830         if (!bp->bar2) {
7831                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7832                 rc = -ENOMEM;
7833                 goto init_err_release;
7834         }
7835
7836         pci_enable_pcie_error_reporting(pdev);
7837
7838         INIT_WORK(&bp->sp_task, bnxt_sp_task);
7839
7840         spin_lock_init(&bp->ntp_fltr_lock);
7841
7842         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7843         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7844
7845         bnxt_init_dflt_coal(bp);
7846
7847         timer_setup(&bp->timer, bnxt_timer, 0);
7848         bp->current_interval = BNXT_TIMER_INTERVAL;
7849
7850         clear_bit(BNXT_STATE_OPEN, &bp->state);
7851         return 0;
7852
7853 init_err_release:
7854         bnxt_unmap_bars(bp, pdev);
7855         pci_release_regions(pdev);
7856
7857 init_err_disable:
7858         pci_disable_device(pdev);
7859
7860 init_err:
7861         return rc;
7862 }
7863
7864 /* rtnl_lock held */
7865 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7866 {
7867         struct sockaddr *addr = p;
7868         struct bnxt *bp = netdev_priv(dev);
7869         int rc = 0;
7870
7871         if (!is_valid_ether_addr(addr->sa_data))
7872                 return -EADDRNOTAVAIL;
7873
7874         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7875                 return 0;
7876
7877         rc = bnxt_approve_mac(bp, addr->sa_data);
7878         if (rc)
7879                 return rc;
7880
7881         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7882         if (netif_running(dev)) {
7883                 bnxt_close_nic(bp, false, false);
7884                 rc = bnxt_open_nic(bp, false, false);
7885         }
7886
7887         return rc;
7888 }
7889
7890 /* rtnl_lock held */
7891 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7892 {
7893         struct bnxt *bp = netdev_priv(dev);
7894
7895         if (netif_running(dev))
7896                 bnxt_close_nic(bp, false, false);
7897
7898         dev->mtu = new_mtu;
7899         bnxt_set_ring_params(bp);
7900
7901         if (netif_running(dev))
7902                 return bnxt_open_nic(bp, false, false);
7903
7904         return 0;
7905 }
7906
7907 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
7908 {
7909         struct bnxt *bp = netdev_priv(dev);
7910         bool sh = false;
7911         int rc;
7912
7913         if (tc > bp->max_tc) {
7914                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
7915                            tc, bp->max_tc);
7916                 return -EINVAL;
7917         }
7918
7919         if (netdev_get_num_tc(dev) == tc)
7920                 return 0;
7921
7922         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7923                 sh = true;
7924
7925         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7926                               sh, tc, bp->tx_nr_rings_xdp);
7927         if (rc)
7928                 return rc;
7929
7930         /* Needs to close the device and do hw resource re-allocations */
7931         if (netif_running(bp->dev))
7932                 bnxt_close_nic(bp, true, false);
7933
7934         if (tc) {
7935                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7936                 netdev_set_num_tc(dev, tc);
7937         } else {
7938                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7939                 netdev_reset_tc(dev);
7940         }
7941         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
7942         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7943                                bp->tx_nr_rings + bp->rx_nr_rings;
7944         bp->num_stat_ctxs = bp->cp_nr_rings;
7945
7946         if (netif_running(bp->dev))
7947                 return bnxt_open_nic(bp, true, false);
7948
7949         return 0;
7950 }
7951
7952 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
7953                                   void *cb_priv)
7954 {
7955         struct bnxt *bp = cb_priv;
7956
7957         if (!bnxt_tc_flower_enabled(bp) ||
7958             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
7959                 return -EOPNOTSUPP;
7960
7961         switch (type) {
7962         case TC_SETUP_CLSFLOWER:
7963                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
7964         default:
7965                 return -EOPNOTSUPP;
7966         }
7967 }
7968
7969 static int bnxt_setup_tc_block(struct net_device *dev,
7970                                struct tc_block_offload *f)
7971 {
7972         struct bnxt *bp = netdev_priv(dev);
7973
7974         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
7975                 return -EOPNOTSUPP;
7976
7977         switch (f->command) {
7978         case TC_BLOCK_BIND:
7979                 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
7980                                              bp, bp);
7981         case TC_BLOCK_UNBIND:
7982                 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
7983                 return 0;
7984         default:
7985                 return -EOPNOTSUPP;
7986         }
7987 }
7988
7989 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
7990                          void *type_data)
7991 {
7992         switch (type) {
7993         case TC_SETUP_BLOCK:
7994                 return bnxt_setup_tc_block(dev, type_data);
7995         case TC_SETUP_QDISC_MQPRIO: {
7996                 struct tc_mqprio_qopt *mqprio = type_data;
7997
7998                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
7999
8000                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
8001         }
8002         default:
8003                 return -EOPNOTSUPP;
8004         }
8005 }
8006
8007 #ifdef CONFIG_RFS_ACCEL
8008 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
8009                             struct bnxt_ntuple_filter *f2)
8010 {
8011         struct flow_keys *keys1 = &f1->fkeys;
8012         struct flow_keys *keys2 = &f2->fkeys;
8013
8014         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
8015             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
8016             keys1->ports.ports == keys2->ports.ports &&
8017             keys1->basic.ip_proto == keys2->basic.ip_proto &&
8018             keys1->basic.n_proto == keys2->basic.n_proto &&
8019             keys1->control.flags == keys2->control.flags &&
8020             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
8021             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
8022                 return true;
8023
8024         return false;
8025 }
8026
8027 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
8028                               u16 rxq_index, u32 flow_id)
8029 {
8030         struct bnxt *bp = netdev_priv(dev);
8031         struct bnxt_ntuple_filter *fltr, *new_fltr;
8032         struct flow_keys *fkeys;
8033         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
8034         int rc = 0, idx, bit_id, l2_idx = 0;
8035         struct hlist_head *head;
8036
8037         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
8038                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8039                 int off = 0, j;
8040
8041                 netif_addr_lock_bh(dev);
8042                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
8043                         if (ether_addr_equal(eth->h_dest,
8044                                              vnic->uc_list + off)) {
8045                                 l2_idx = j + 1;
8046                                 break;
8047                         }
8048                 }
8049                 netif_addr_unlock_bh(dev);
8050                 if (!l2_idx)
8051                         return -EINVAL;
8052         }
8053         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
8054         if (!new_fltr)
8055                 return -ENOMEM;
8056
8057         fkeys = &new_fltr->fkeys;
8058         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
8059                 rc = -EPROTONOSUPPORT;
8060                 goto err_free;
8061         }
8062
8063         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
8064              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
8065             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
8066              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
8067                 rc = -EPROTONOSUPPORT;
8068                 goto err_free;
8069         }
8070         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
8071             bp->hwrm_spec_code < 0x10601) {
8072                 rc = -EPROTONOSUPPORT;
8073                 goto err_free;
8074         }
8075         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
8076             bp->hwrm_spec_code < 0x10601) {
8077                 rc = -EPROTONOSUPPORT;
8078                 goto err_free;
8079         }
8080
8081         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
8082         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
8083
8084         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
8085         head = &bp->ntp_fltr_hash_tbl[idx];
8086         rcu_read_lock();
8087         hlist_for_each_entry_rcu(fltr, head, hash) {
8088                 if (bnxt_fltr_match(fltr, new_fltr)) {
8089                         rcu_read_unlock();
8090                         rc = 0;
8091                         goto err_free;
8092                 }
8093         }
8094         rcu_read_unlock();
8095
8096         spin_lock_bh(&bp->ntp_fltr_lock);
8097         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
8098                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
8099         if (bit_id < 0) {
8100                 spin_unlock_bh(&bp->ntp_fltr_lock);
8101                 rc = -ENOMEM;
8102                 goto err_free;
8103         }
8104
8105         new_fltr->sw_id = (u16)bit_id;
8106         new_fltr->flow_id = flow_id;
8107         new_fltr->l2_fltr_idx = l2_idx;
8108         new_fltr->rxq = rxq_index;
8109         hlist_add_head_rcu(&new_fltr->hash, head);
8110         bp->ntp_fltr_count++;
8111         spin_unlock_bh(&bp->ntp_fltr_lock);
8112
8113         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
8114         bnxt_queue_sp_work(bp);
8115
8116         return new_fltr->sw_id;
8117
8118 err_free:
8119         kfree(new_fltr);
8120         return rc;
8121 }
8122
8123 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8124 {
8125         int i;
8126
8127         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
8128                 struct hlist_head *head;
8129                 struct hlist_node *tmp;
8130                 struct bnxt_ntuple_filter *fltr;
8131                 int rc;
8132
8133                 head = &bp->ntp_fltr_hash_tbl[i];
8134                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
8135                         bool del = false;
8136
8137                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
8138                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
8139                                                         fltr->flow_id,
8140                                                         fltr->sw_id)) {
8141                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
8142                                                                          fltr);
8143                                         del = true;
8144                                 }
8145                         } else {
8146                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
8147                                                                        fltr);
8148                                 if (rc)
8149                                         del = true;
8150                                 else
8151                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
8152                         }
8153
8154                         if (del) {
8155                                 spin_lock_bh(&bp->ntp_fltr_lock);
8156                                 hlist_del_rcu(&fltr->hash);
8157                                 bp->ntp_fltr_count--;
8158                                 spin_unlock_bh(&bp->ntp_fltr_lock);
8159                                 synchronize_rcu();
8160                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
8161                                 kfree(fltr);
8162                         }
8163                 }
8164         }
8165         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
8166                 netdev_info(bp->dev, "Receive PF driver unload event!");
8167 }
8168
8169 #else
8170
8171 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8172 {
8173 }
8174
8175 #endif /* CONFIG_RFS_ACCEL */
8176
8177 static void bnxt_udp_tunnel_add(struct net_device *dev,
8178                                 struct udp_tunnel_info *ti)
8179 {
8180         struct bnxt *bp = netdev_priv(dev);
8181
8182         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8183                 return;
8184
8185         if (!netif_running(dev))
8186                 return;
8187
8188         switch (ti->type) {
8189         case UDP_TUNNEL_TYPE_VXLAN:
8190                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
8191                         return;
8192
8193                 bp->vxlan_port_cnt++;
8194                 if (bp->vxlan_port_cnt == 1) {
8195                         bp->vxlan_port = ti->port;
8196                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
8197                         bnxt_queue_sp_work(bp);
8198                 }
8199                 break;
8200         case UDP_TUNNEL_TYPE_GENEVE:
8201                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
8202                         return;
8203
8204                 bp->nge_port_cnt++;
8205                 if (bp->nge_port_cnt == 1) {
8206                         bp->nge_port = ti->port;
8207                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
8208                 }
8209                 break;
8210         default:
8211                 return;
8212         }
8213
8214         bnxt_queue_sp_work(bp);
8215 }
8216
8217 static void bnxt_udp_tunnel_del(struct net_device *dev,
8218                                 struct udp_tunnel_info *ti)
8219 {
8220         struct bnxt *bp = netdev_priv(dev);
8221
8222         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8223                 return;
8224
8225         if (!netif_running(dev))
8226                 return;
8227
8228         switch (ti->type) {
8229         case UDP_TUNNEL_TYPE_VXLAN:
8230                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
8231                         return;
8232                 bp->vxlan_port_cnt--;
8233
8234                 if (bp->vxlan_port_cnt != 0)
8235                         return;
8236
8237                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
8238                 break;
8239         case UDP_TUNNEL_TYPE_GENEVE:
8240                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
8241                         return;
8242                 bp->nge_port_cnt--;
8243
8244                 if (bp->nge_port_cnt != 0)
8245                         return;
8246
8247                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
8248                 break;
8249         default:
8250                 return;
8251         }
8252
8253         bnxt_queue_sp_work(bp);
8254 }
8255
8256 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8257                                struct net_device *dev, u32 filter_mask,
8258                                int nlflags)
8259 {
8260         struct bnxt *bp = netdev_priv(dev);
8261
8262         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
8263                                        nlflags, filter_mask, NULL);
8264 }
8265
8266 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
8267                                u16 flags)
8268 {
8269         struct bnxt *bp = netdev_priv(dev);
8270         struct nlattr *attr, *br_spec;
8271         int rem, rc = 0;
8272
8273         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
8274                 return -EOPNOTSUPP;
8275
8276         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8277         if (!br_spec)
8278                 return -EINVAL;
8279
8280         nla_for_each_nested(attr, br_spec, rem) {
8281                 u16 mode;
8282
8283                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8284                         continue;
8285
8286                 if (nla_len(attr) < sizeof(mode))
8287                         return -EINVAL;
8288
8289                 mode = nla_get_u16(attr);
8290                 if (mode == bp->br_mode)
8291                         break;
8292
8293                 rc = bnxt_hwrm_set_br_mode(bp, mode);
8294                 if (!rc)
8295                         bp->br_mode = mode;
8296                 break;
8297         }
8298         return rc;
8299 }
8300
8301 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
8302                                    size_t len)
8303 {
8304         struct bnxt *bp = netdev_priv(dev);
8305         int rc;
8306
8307         /* The PF and it's VF-reps only support the switchdev framework */
8308         if (!BNXT_PF(bp))
8309                 return -EOPNOTSUPP;
8310
8311         rc = snprintf(buf, len, "p%d", bp->pf.port_id);
8312
8313         if (rc >= len)
8314                 return -EOPNOTSUPP;
8315         return 0;
8316 }
8317
8318 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
8319 {
8320         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
8321                 return -EOPNOTSUPP;
8322
8323         /* The PF and it's VF-reps only support the switchdev framework */
8324         if (!BNXT_PF(bp))
8325                 return -EOPNOTSUPP;
8326
8327         switch (attr->id) {
8328         case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
8329                 attr->u.ppid.id_len = sizeof(bp->switch_id);
8330                 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
8331                 break;
8332         default:
8333                 return -EOPNOTSUPP;
8334         }
8335         return 0;
8336 }
8337
8338 static int bnxt_swdev_port_attr_get(struct net_device *dev,
8339                                     struct switchdev_attr *attr)
8340 {
8341         return bnxt_port_attr_get(netdev_priv(dev), attr);
8342 }
8343
8344 static const struct switchdev_ops bnxt_switchdev_ops = {
8345         .switchdev_port_attr_get        = bnxt_swdev_port_attr_get
8346 };
8347
8348 static const struct net_device_ops bnxt_netdev_ops = {
8349         .ndo_open               = bnxt_open,
8350         .ndo_start_xmit         = bnxt_start_xmit,
8351         .ndo_stop               = bnxt_close,
8352         .ndo_get_stats64        = bnxt_get_stats64,
8353         .ndo_set_rx_mode        = bnxt_set_rx_mode,
8354         .ndo_do_ioctl           = bnxt_ioctl,
8355         .ndo_validate_addr      = eth_validate_addr,
8356         .ndo_set_mac_address    = bnxt_change_mac_addr,
8357         .ndo_change_mtu         = bnxt_change_mtu,
8358         .ndo_fix_features       = bnxt_fix_features,
8359         .ndo_set_features       = bnxt_set_features,
8360         .ndo_tx_timeout         = bnxt_tx_timeout,
8361 #ifdef CONFIG_BNXT_SRIOV
8362         .ndo_get_vf_config      = bnxt_get_vf_config,
8363         .ndo_set_vf_mac         = bnxt_set_vf_mac,
8364         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
8365         .ndo_set_vf_rate        = bnxt_set_vf_bw,
8366         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
8367         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
8368         .ndo_set_vf_trust       = bnxt_set_vf_trust,
8369 #endif
8370 #ifdef CONFIG_NET_POLL_CONTROLLER
8371         .ndo_poll_controller    = bnxt_poll_controller,
8372 #endif
8373         .ndo_setup_tc           = bnxt_setup_tc,
8374 #ifdef CONFIG_RFS_ACCEL
8375         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
8376 #endif
8377         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
8378         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
8379         .ndo_bpf                = bnxt_xdp,
8380         .ndo_bridge_getlink     = bnxt_bridge_getlink,
8381         .ndo_bridge_setlink     = bnxt_bridge_setlink,
8382         .ndo_get_phys_port_name = bnxt_get_phys_port_name
8383 };
8384
8385 static void bnxt_remove_one(struct pci_dev *pdev)
8386 {
8387         struct net_device *dev = pci_get_drvdata(pdev);
8388         struct bnxt *bp = netdev_priv(dev);
8389
8390         if (BNXT_PF(bp)) {
8391                 bnxt_sriov_disable(bp);
8392                 bnxt_dl_unregister(bp);
8393         }
8394
8395         pci_disable_pcie_error_reporting(pdev);
8396         unregister_netdev(dev);
8397         bnxt_shutdown_tc(bp);
8398         bnxt_cancel_sp_work(bp);
8399         bp->sp_event = 0;
8400
8401         bnxt_clear_int_mode(bp);
8402         bnxt_hwrm_func_drv_unrgtr(bp);
8403         bnxt_free_hwrm_resources(bp);
8404         bnxt_free_hwrm_short_cmd_req(bp);
8405         bnxt_ethtool_free(bp);
8406         bnxt_dcb_free(bp);
8407         kfree(bp->edev);
8408         bp->edev = NULL;
8409         bnxt_cleanup_pci(bp);
8410         free_netdev(dev);
8411 }
8412
8413 static int bnxt_probe_phy(struct bnxt *bp)
8414 {
8415         int rc = 0;
8416         struct bnxt_link_info *link_info = &bp->link_info;
8417
8418         rc = bnxt_hwrm_phy_qcaps(bp);
8419         if (rc) {
8420                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
8421                            rc);
8422                 return rc;
8423         }
8424         mutex_init(&bp->link_lock);
8425
8426         rc = bnxt_update_link(bp, false);
8427         if (rc) {
8428                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
8429                            rc);
8430                 return rc;
8431         }
8432
8433         /* Older firmware does not have supported_auto_speeds, so assume
8434          * that all supported speeds can be autonegotiated.
8435          */
8436         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
8437                 link_info->support_auto_speeds = link_info->support_speeds;
8438
8439         /*initialize the ethool setting copy with NVM settings */
8440         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
8441                 link_info->autoneg = BNXT_AUTONEG_SPEED;
8442                 if (bp->hwrm_spec_code >= 0x10201) {
8443                         if (link_info->auto_pause_setting &
8444                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
8445                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8446                 } else {
8447                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8448                 }
8449                 link_info->advertising = link_info->auto_link_speeds;
8450         } else {
8451                 link_info->req_link_speed = link_info->force_link_speed;
8452                 link_info->req_duplex = link_info->duplex_setting;
8453         }
8454         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
8455                 link_info->req_flow_ctrl =
8456                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
8457         else
8458                 link_info->req_flow_ctrl = link_info->force_pause_setting;
8459         return rc;
8460 }
8461
8462 static int bnxt_get_max_irq(struct pci_dev *pdev)
8463 {
8464         u16 ctrl;
8465
8466         if (!pdev->msix_cap)
8467                 return 1;
8468
8469         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
8470         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
8471 }
8472
8473 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8474                                 int *max_cp)
8475 {
8476         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8477         int max_ring_grps = 0;
8478
8479         *max_tx = hw_resc->max_tx_rings;
8480         *max_rx = hw_resc->max_rx_rings;
8481         *max_cp = min_t(int, hw_resc->max_irqs, hw_resc->max_cp_rings);
8482         *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs);
8483         max_ring_grps = hw_resc->max_hw_ring_grps;
8484         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
8485                 *max_cp -= 1;
8486                 *max_rx -= 2;
8487         }
8488         if (bp->flags & BNXT_FLAG_AGG_RINGS)
8489                 *max_rx >>= 1;
8490         *max_rx = min_t(int, *max_rx, max_ring_grps);
8491 }
8492
8493 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
8494 {
8495         int rx, tx, cp;
8496
8497         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
8498         if (!rx || !tx || !cp)
8499                 return -ENOMEM;
8500
8501         *max_rx = rx;
8502         *max_tx = tx;
8503         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
8504 }
8505
8506 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8507                                bool shared)
8508 {
8509         int rc;
8510
8511         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8512         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
8513                 /* Not enough rings, try disabling agg rings. */
8514                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
8515                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8516                 if (rc)
8517                         return rc;
8518                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
8519                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8520                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8521                 bnxt_set_ring_params(bp);
8522         }
8523
8524         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
8525                 int max_cp, max_stat, max_irq;
8526
8527                 /* Reserve minimum resources for RoCE */
8528                 max_cp = bnxt_get_max_func_cp_rings(bp);
8529                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
8530                 max_irq = bnxt_get_max_func_irqs(bp);
8531                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
8532                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
8533                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
8534                         return 0;
8535
8536                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
8537                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
8538                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
8539                 max_cp = min_t(int, max_cp, max_irq);
8540                 max_cp = min_t(int, max_cp, max_stat);
8541                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
8542                 if (rc)
8543                         rc = 0;
8544         }
8545         return rc;
8546 }
8547
8548 /* In initial default shared ring setting, each shared ring must have a
8549  * RX/TX ring pair.
8550  */
8551 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
8552 {
8553         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
8554         bp->rx_nr_rings = bp->cp_nr_rings;
8555         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
8556         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8557 }
8558
8559 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
8560 {
8561         int dflt_rings, max_rx_rings, max_tx_rings, rc;
8562
8563         if (!bnxt_can_reserve_rings(bp))
8564                 return 0;
8565
8566         if (sh)
8567                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8568         dflt_rings = netif_get_num_default_rss_queues();
8569         /* Reduce default rings on multi-port cards so that total default
8570          * rings do not exceed CPU count.
8571          */
8572         if (bp->port_count > 1) {
8573                 int max_rings =
8574                         max_t(int, num_online_cpus() / bp->port_count, 1);
8575
8576                 dflt_rings = min_t(int, dflt_rings, max_rings);
8577         }
8578         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
8579         if (rc)
8580                 return rc;
8581         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
8582         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
8583         if (sh)
8584                 bnxt_trim_dflt_sh_rings(bp);
8585         else
8586                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
8587         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8588
8589         rc = __bnxt_reserve_rings(bp);
8590         if (rc)
8591                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
8592         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8593         if (sh)
8594                 bnxt_trim_dflt_sh_rings(bp);
8595
8596         /* Rings may have been trimmed, re-reserve the trimmed rings. */
8597         if (bnxt_need_reserve_rings(bp)) {
8598                 rc = __bnxt_reserve_rings(bp);
8599                 if (rc)
8600                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
8601                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8602         }
8603         bp->num_stat_ctxs = bp->cp_nr_rings;
8604         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8605                 bp->rx_nr_rings++;
8606                 bp->cp_nr_rings++;
8607         }
8608         return rc;
8609 }
8610
8611 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
8612 {
8613         int rc;
8614
8615         if (bp->tx_nr_rings)
8616                 return 0;
8617
8618         rc = bnxt_set_dflt_rings(bp, true);
8619         if (rc) {
8620                 netdev_err(bp->dev, "Not enough rings available.\n");
8621                 return rc;
8622         }
8623         rc = bnxt_init_int_mode(bp);
8624         if (rc)
8625                 return rc;
8626         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8627         if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
8628                 bp->flags |= BNXT_FLAG_RFS;
8629                 bp->dev->features |= NETIF_F_NTUPLE;
8630         }
8631         return 0;
8632 }
8633
8634 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
8635 {
8636         int rc;
8637
8638         ASSERT_RTNL();
8639         bnxt_hwrm_func_qcaps(bp);
8640
8641         if (netif_running(bp->dev))
8642                 __bnxt_close_nic(bp, true, false);
8643
8644         bnxt_ulp_irq_stop(bp);
8645         bnxt_clear_int_mode(bp);
8646         rc = bnxt_init_int_mode(bp);
8647         bnxt_ulp_irq_restart(bp, rc);
8648
8649         if (netif_running(bp->dev)) {
8650                 if (rc)
8651                         dev_close(bp->dev);
8652                 else
8653                         rc = bnxt_open_nic(bp, true, false);
8654         }
8655
8656         return rc;
8657 }
8658
8659 static int bnxt_init_mac_addr(struct bnxt *bp)
8660 {
8661         int rc = 0;
8662
8663         if (BNXT_PF(bp)) {
8664                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8665         } else {
8666 #ifdef CONFIG_BNXT_SRIOV
8667                 struct bnxt_vf_info *vf = &bp->vf;
8668
8669                 if (is_valid_ether_addr(vf->mac_addr)) {
8670                         /* overwrite netdev dev_addr with admin VF MAC */
8671                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8672                 } else {
8673                         eth_hw_addr_random(bp->dev);
8674                         rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
8675                 }
8676 #endif
8677         }
8678         return rc;
8679 }
8680
8681 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
8682 {
8683         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
8684         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
8685
8686         if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) ||
8687             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
8688                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
8689         else
8690                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
8691                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
8692                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
8693                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
8694                             "Unknown", width);
8695 }
8696
8697 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8698 {
8699         static int version_printed;
8700         struct net_device *dev;
8701         struct bnxt *bp;
8702         int rc, max_irqs;
8703
8704         if (pci_is_bridge(pdev))
8705                 return -ENODEV;
8706
8707         if (version_printed++ == 0)
8708                 pr_info("%s", version);
8709
8710         max_irqs = bnxt_get_max_irq(pdev);
8711         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8712         if (!dev)
8713                 return -ENOMEM;
8714
8715         bp = netdev_priv(dev);
8716
8717         if (bnxt_vf_pciid(ent->driver_data))
8718                 bp->flags |= BNXT_FLAG_VF;
8719
8720         if (pdev->msix_cap)
8721                 bp->flags |= BNXT_FLAG_MSIX_CAP;
8722
8723         rc = bnxt_init_board(pdev, dev);
8724         if (rc < 0)
8725                 goto init_err_free;
8726
8727         dev->netdev_ops = &bnxt_netdev_ops;
8728         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8729         dev->ethtool_ops = &bnxt_ethtool_ops;
8730         SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8731         pci_set_drvdata(pdev, dev);
8732
8733         rc = bnxt_alloc_hwrm_resources(bp);
8734         if (rc)
8735                 goto init_err_pci_clean;
8736
8737         mutex_init(&bp->hwrm_cmd_lock);
8738         rc = bnxt_hwrm_ver_get(bp);
8739         if (rc)
8740                 goto init_err_pci_clean;
8741
8742         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
8743                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8744                 if (rc)
8745                         goto init_err_pci_clean;
8746         }
8747
8748         rc = bnxt_hwrm_func_reset(bp);
8749         if (rc)
8750                 goto init_err_pci_clean;
8751
8752         bnxt_hwrm_fw_set_time(bp);
8753
8754         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8755                            NETIF_F_TSO | NETIF_F_TSO6 |
8756                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8757                            NETIF_F_GSO_IPXIP4 |
8758                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8759                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
8760                            NETIF_F_RXCSUM | NETIF_F_GRO;
8761
8762         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8763                 dev->hw_features |= NETIF_F_LRO;
8764
8765         dev->hw_enc_features =
8766                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8767                         NETIF_F_TSO | NETIF_F_TSO6 |
8768                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8769                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8770                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
8771         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8772                                     NETIF_F_GSO_GRE_CSUM;
8773         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8774         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8775                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
8776         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8777                 dev->hw_features |= NETIF_F_GRO_HW;
8778         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
8779         if (dev->features & NETIF_F_GRO_HW)
8780                 dev->features &= ~NETIF_F_LRO;
8781         dev->priv_flags |= IFF_UNICAST_FLT;
8782
8783 #ifdef CONFIG_BNXT_SRIOV
8784         init_waitqueue_head(&bp->sriov_cfg_wait);
8785         mutex_init(&bp->sriov_lock);
8786 #endif
8787         bp->gro_func = bnxt_gro_func_5730x;
8788         if (BNXT_CHIP_P4_PLUS(bp))
8789                 bp->gro_func = bnxt_gro_func_5731x;
8790         else
8791                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
8792
8793         rc = bnxt_hwrm_func_drv_rgtr(bp);
8794         if (rc)
8795                 goto init_err_pci_clean;
8796
8797         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8798         if (rc)
8799                 goto init_err_pci_clean;
8800
8801         bp->ulp_probe = bnxt_ulp_probe;
8802
8803         /* Get the MAX capabilities for this function */
8804         rc = bnxt_hwrm_func_qcaps(bp);
8805         if (rc) {
8806                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8807                            rc);
8808                 rc = -1;
8809                 goto init_err_pci_clean;
8810         }
8811         rc = bnxt_init_mac_addr(bp);
8812         if (rc) {
8813                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
8814                 rc = -EADDRNOTAVAIL;
8815                 goto init_err_pci_clean;
8816         }
8817         rc = bnxt_hwrm_queue_qportcfg(bp);
8818         if (rc) {
8819                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8820                            rc);
8821                 rc = -1;
8822                 goto init_err_pci_clean;
8823         }
8824
8825         bnxt_hwrm_func_qcfg(bp);
8826         bnxt_hwrm_port_led_qcaps(bp);
8827         bnxt_ethtool_init(bp);
8828         bnxt_dcb_init(bp);
8829
8830         /* MTU range: 60 - FW defined max */
8831         dev->min_mtu = ETH_ZLEN;
8832         dev->max_mtu = bp->max_mtu;
8833
8834         rc = bnxt_probe_phy(bp);
8835         if (rc)
8836                 goto init_err_pci_clean;
8837
8838         bnxt_set_rx_skb_mode(bp, false);
8839         bnxt_set_tpa_flags(bp);
8840         bnxt_set_ring_params(bp);
8841         bnxt_set_max_func_irqs(bp, max_irqs);
8842         rc = bnxt_set_dflt_rings(bp, true);
8843         if (rc) {
8844                 netdev_err(bp->dev, "Not enough rings available.\n");
8845                 rc = -ENOMEM;
8846                 goto init_err_pci_clean;
8847         }
8848
8849         /* Default RSS hash cfg. */
8850         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8851                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8852                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8853                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
8854         if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
8855                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8856                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8857                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8858         }
8859
8860         bnxt_hwrm_vnic_qcaps(bp);
8861         if (bnxt_rfs_supported(bp)) {
8862                 dev->hw_features |= NETIF_F_NTUPLE;
8863                 if (bnxt_rfs_capable(bp)) {
8864                         bp->flags |= BNXT_FLAG_RFS;
8865                         dev->features |= NETIF_F_NTUPLE;
8866                 }
8867         }
8868
8869         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
8870                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
8871
8872         rc = bnxt_init_int_mode(bp);
8873         if (rc)
8874                 goto init_err_pci_clean;
8875
8876         /* No TC has been set yet and rings may have been trimmed due to
8877          * limited MSIX, so we re-initialize the TX rings per TC.
8878          */
8879         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8880
8881         bnxt_get_wol_settings(bp);
8882         if (bp->flags & BNXT_FLAG_WOL_CAP)
8883                 device_set_wakeup_enable(&pdev->dev, bp->wol);
8884         else
8885                 device_set_wakeup_capable(&pdev->dev, false);
8886
8887         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
8888
8889         if (BNXT_PF(bp)) {
8890                 if (!bnxt_pf_wq) {
8891                         bnxt_pf_wq =
8892                                 create_singlethread_workqueue("bnxt_pf_wq");
8893                         if (!bnxt_pf_wq) {
8894                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
8895                                 goto init_err_pci_clean;
8896                         }
8897                 }
8898                 bnxt_init_tc(bp);
8899         }
8900
8901         rc = register_netdev(dev);
8902         if (rc)
8903                 goto init_err_cleanup_tc;
8904
8905         if (BNXT_PF(bp))
8906                 bnxt_dl_register(bp);
8907
8908         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
8909                     board_info[ent->driver_data].name,
8910                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
8911
8912         bnxt_parse_log_pcie_link(bp);
8913
8914         return 0;
8915
8916 init_err_cleanup_tc:
8917         bnxt_shutdown_tc(bp);
8918         bnxt_clear_int_mode(bp);
8919
8920 init_err_pci_clean:
8921         bnxt_cleanup_pci(bp);
8922
8923 init_err_free:
8924         free_netdev(dev);
8925         return rc;
8926 }
8927
8928 static void bnxt_shutdown(struct pci_dev *pdev)
8929 {
8930         struct net_device *dev = pci_get_drvdata(pdev);
8931         struct bnxt *bp;
8932
8933         if (!dev)
8934                 return;
8935
8936         rtnl_lock();
8937         bp = netdev_priv(dev);
8938         if (!bp)
8939                 goto shutdown_exit;
8940
8941         if (netif_running(dev))
8942                 dev_close(dev);
8943
8944         bnxt_ulp_shutdown(bp);
8945
8946         if (system_state == SYSTEM_POWER_OFF) {
8947                 bnxt_clear_int_mode(bp);
8948                 pci_wake_from_d3(pdev, bp->wol);
8949                 pci_set_power_state(pdev, PCI_D3hot);
8950         }
8951
8952 shutdown_exit:
8953         rtnl_unlock();
8954 }
8955
8956 #ifdef CONFIG_PM_SLEEP
8957 static int bnxt_suspend(struct device *device)
8958 {
8959         struct pci_dev *pdev = to_pci_dev(device);
8960         struct net_device *dev = pci_get_drvdata(pdev);
8961         struct bnxt *bp = netdev_priv(dev);
8962         int rc = 0;
8963
8964         rtnl_lock();
8965         if (netif_running(dev)) {
8966                 netif_device_detach(dev);
8967                 rc = bnxt_close(dev);
8968         }
8969         bnxt_hwrm_func_drv_unrgtr(bp);
8970         rtnl_unlock();
8971         return rc;
8972 }
8973
8974 static int bnxt_resume(struct device *device)
8975 {
8976         struct pci_dev *pdev = to_pci_dev(device);
8977         struct net_device *dev = pci_get_drvdata(pdev);
8978         struct bnxt *bp = netdev_priv(dev);
8979         int rc = 0;
8980
8981         rtnl_lock();
8982         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
8983                 rc = -ENODEV;
8984                 goto resume_exit;
8985         }
8986         rc = bnxt_hwrm_func_reset(bp);
8987         if (rc) {
8988                 rc = -EBUSY;
8989                 goto resume_exit;
8990         }
8991         bnxt_get_wol_settings(bp);
8992         if (netif_running(dev)) {
8993                 rc = bnxt_open(dev);
8994                 if (!rc)
8995                         netif_device_attach(dev);
8996         }
8997
8998 resume_exit:
8999         rtnl_unlock();
9000         return rc;
9001 }
9002
9003 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
9004 #define BNXT_PM_OPS (&bnxt_pm_ops)
9005
9006 #else
9007
9008 #define BNXT_PM_OPS NULL
9009
9010 #endif /* CONFIG_PM_SLEEP */
9011
9012 /**
9013  * bnxt_io_error_detected - called when PCI error is detected
9014  * @pdev: Pointer to PCI device
9015  * @state: The current pci connection state
9016  *
9017  * This function is called after a PCI bus error affecting
9018  * this device has been detected.
9019  */
9020 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
9021                                                pci_channel_state_t state)
9022 {
9023         struct net_device *netdev = pci_get_drvdata(pdev);
9024         struct bnxt *bp = netdev_priv(netdev);
9025
9026         netdev_info(netdev, "PCI I/O error detected\n");
9027
9028         rtnl_lock();
9029         netif_device_detach(netdev);
9030
9031         bnxt_ulp_stop(bp);
9032
9033         if (state == pci_channel_io_perm_failure) {
9034                 rtnl_unlock();
9035                 return PCI_ERS_RESULT_DISCONNECT;
9036         }
9037
9038         if (netif_running(netdev))
9039                 bnxt_close(netdev);
9040
9041         pci_disable_device(pdev);
9042         rtnl_unlock();
9043
9044         /* Request a slot slot reset. */
9045         return PCI_ERS_RESULT_NEED_RESET;
9046 }
9047
9048 /**
9049  * bnxt_io_slot_reset - called after the pci bus has been reset.
9050  * @pdev: Pointer to PCI device
9051  *
9052  * Restart the card from scratch, as if from a cold-boot.
9053  * At this point, the card has exprienced a hard reset,
9054  * followed by fixups by BIOS, and has its config space
9055  * set up identically to what it was at cold boot.
9056  */
9057 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
9058 {
9059         struct net_device *netdev = pci_get_drvdata(pdev);
9060         struct bnxt *bp = netdev_priv(netdev);
9061         int err = 0;
9062         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
9063
9064         netdev_info(bp->dev, "PCI Slot Reset\n");
9065
9066         rtnl_lock();
9067
9068         if (pci_enable_device(pdev)) {
9069                 dev_err(&pdev->dev,
9070                         "Cannot re-enable PCI device after reset.\n");
9071         } else {
9072                 pci_set_master(pdev);
9073
9074                 err = bnxt_hwrm_func_reset(bp);
9075                 if (!err && netif_running(netdev))
9076                         err = bnxt_open(netdev);
9077
9078                 if (!err) {
9079                         result = PCI_ERS_RESULT_RECOVERED;
9080                         bnxt_ulp_start(bp);
9081                 }
9082         }
9083
9084         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
9085                 dev_close(netdev);
9086
9087         rtnl_unlock();
9088
9089         err = pci_cleanup_aer_uncorrect_error_status(pdev);
9090         if (err) {
9091                 dev_err(&pdev->dev,
9092                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9093                          err); /* non-fatal, continue */
9094         }
9095
9096         return PCI_ERS_RESULT_RECOVERED;
9097 }
9098
9099 /**
9100  * bnxt_io_resume - called when traffic can start flowing again.
9101  * @pdev: Pointer to PCI device
9102  *
9103  * This callback is called when the error recovery driver tells
9104  * us that its OK to resume normal operation.
9105  */
9106 static void bnxt_io_resume(struct pci_dev *pdev)
9107 {
9108         struct net_device *netdev = pci_get_drvdata(pdev);
9109
9110         rtnl_lock();
9111
9112         netif_device_attach(netdev);
9113
9114         rtnl_unlock();
9115 }
9116
9117 static const struct pci_error_handlers bnxt_err_handler = {
9118         .error_detected = bnxt_io_error_detected,
9119         .slot_reset     = bnxt_io_slot_reset,
9120         .resume         = bnxt_io_resume
9121 };
9122
9123 static struct pci_driver bnxt_pci_driver = {
9124         .name           = DRV_MODULE_NAME,
9125         .id_table       = bnxt_pci_tbl,
9126         .probe          = bnxt_init_one,
9127         .remove         = bnxt_remove_one,
9128         .shutdown       = bnxt_shutdown,
9129         .driver.pm      = BNXT_PM_OPS,
9130         .err_handler    = &bnxt_err_handler,
9131 #if defined(CONFIG_BNXT_SRIOV)
9132         .sriov_configure = bnxt_sriov_configure,
9133 #endif
9134 };
9135
9136 static int __init bnxt_init(void)
9137 {
9138         bnxt_debug_init();
9139         return pci_register_driver(&bnxt_pci_driver);
9140 }
9141
9142 static void __exit bnxt_exit(void)
9143 {
9144         pci_unregister_driver(&bnxt_pci_driver);
9145         if (bnxt_pf_wq)
9146                 destroy_workqueue(bnxt_pf_wq);
9147         bnxt_debug_exit();
9148 }
9149
9150 module_init(bnxt_init);
9151 module_exit(bnxt_exit);