drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/if.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/if_bridge.h>
  37 #include <linux/rtc.h>
  38 #include <linux/bpf.h>
  39 #include <net/ip.h>
  40 #include <net/tcp.h>
  41 #include <net/udp.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <net/udp_tunnel.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/prefetch.h>
  47 #include <linux/cache.h>
  48 #include <linux/log2.h>
  49 #include <linux/aer.h>
  50 #include <linux/bitmap.h>
  51 #include <linux/cpu_rmap.h>
  52 #include <linux/cpumask.h>
  53 #include <net/pkt_cls.h>
  54
  55 #include "bnxt_hsi.h"
  56 #include "bnxt.h"
  57 #include "bnxt_ulp.h"
  58 #include "bnxt_sriov.h"
  59 #include "bnxt_ethtool.h"
  60 #include "bnxt_dcb.h"
  61 #include "bnxt_xdp.h"
  62 #include "bnxt_vfr.h"
  63 #include "bnxt_tc.h"
  64 #include "bnxt_devlink.h"
  65
  66 #define BNXT_TX_TIMEOUT         (5 * HZ)
  67
  68 static const char version[] =
  69         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  70
  71 MODULE_LICENSE("GPL");
  72 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  73 MODULE_VERSION(DRV_MODULE_VERSION);
  74
  75 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  76 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  77 #define BNXT_RX_COPY_THRESH 256
  78
  79 #define BNXT_TX_PUSH_THRESH 164
  80
  81 enum board_idx {
  82         BCM57301,
  83         BCM57302,
  84         BCM57304,
  85         BCM57417_NPAR,
  86         BCM58700,
  87         BCM57311,
  88         BCM57312,
  89         BCM57402,
  90         BCM57404,
  91         BCM57406,
  92         BCM57402_NPAR,
  93         BCM57407,
  94         BCM57412,
  95         BCM57414,
  96         BCM57416,
  97         BCM57417,
  98         BCM57412_NPAR,
  99         BCM57314,
 100         BCM57417_SFP,
 101         BCM57416_SFP,
 102         BCM57404_NPAR,
 103         BCM57406_NPAR,
 104         BCM57407_SFP,
 105         BCM57407_NPAR,
 106         BCM57414_NPAR,
 107         BCM57416_NPAR,
 108         BCM57452,
 109         BCM57454,
 110         BCM5745x_NPAR,
 111         BCM58802,
 112         BCM58804,
 113         BCM58808,
 114         NETXTREME_E_VF,
 115         NETXTREME_C_VF,
 116         NETXTREME_S_VF,
 117 };
 118
 119 /* indexed by enum above */
 120 static const struct {
 121         char *name;
 122 } board_info[] = {
 123         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 124         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 125         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 126         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 127         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 128         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 129         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 130         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 131         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 132         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 133         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 134         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 135         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 136         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 137         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 138         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 139         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 140         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 141         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 142         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 143         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 144         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 145         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 146         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 147         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 148         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 149         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 150         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 151         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 152         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 153         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 154         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 155         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 156         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 157         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 158 };
 159
 160 static const struct pci_device_id bnxt_pci_tbl[] = {
 161         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 162         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 163         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 164         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 165         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 166         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 167         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 168         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 169         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 170         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 171         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 172         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 173         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 174         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 175         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 176         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 177         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 178         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 179         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 180         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 181         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 182         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 183         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 184         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 185         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 186         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 187         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 188         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 189         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 190         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 191         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 192         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 193         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 194         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 195         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 196         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 197         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 198 #ifdef CONFIG_BNXT_SRIOV
 199         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 200         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 201         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 202         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 203         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 204         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 205         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 206         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 207         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 208 #endif
 209         { 0 }
 210 };
 211
 212 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 213
 214 static const u16 bnxt_vf_req_snif[] = {
 215         HWRM_FUNC_CFG,
 216         HWRM_FUNC_VF_CFG,
 217         HWRM_PORT_PHY_QCFG,
 218         HWRM_CFA_L2_FILTER_ALLOC,
 219 };
 220
 221 static const u16 bnxt_async_events_arr[] = {
 222         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 223         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 224         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 225         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 226         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 227 };
 228
 229 static struct workqueue_struct *bnxt_pf_wq;
 230
 231 static bool bnxt_vf_pciid(enum board_idx idx)
 232 {
 233         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 234                 idx == NETXTREME_S_VF);
 235 }
 236
 237 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 238 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 239 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 240
 241 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 242                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 243
 244 #define BNXT_CP_DB(db, raw_cons)                                        \
 245                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 246
 247 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 248                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 249
 250 const u16 bnxt_lhint_arr[] = {
 251         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 252         TX_BD_FLAGS_LHINT_512_TO_1023,
 253         TX_BD_FLAGS_LHINT_1024_TO_2047,
 254         TX_BD_FLAGS_LHINT_1024_TO_2047,
 255         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 256         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 257         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 258         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 259         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 260         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 261         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 262         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 263         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 264         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 265         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 266         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 267         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 268         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 269         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 270 };
 271
 272 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 273 {
 274         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 275
 276         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 277                 return 0;
 278
 279         return md_dst->u.port_info.port_id;
 280 }
 281
 282 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 283 {
 284         struct bnxt *bp = netdev_priv(dev);
 285         struct tx_bd *txbd;
 286         struct tx_bd_ext *txbd1;
 287         struct netdev_queue *txq;
 288         int i;
 289         dma_addr_t mapping;
 290         unsigned int length, pad = 0;
 291         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 292         u16 prod, last_frag;
 293         struct pci_dev *pdev = bp->pdev;
 294         struct bnxt_tx_ring_info *txr;
 295         struct bnxt_sw_tx_bd *tx_buf;
 296
 297         i = skb_get_queue_mapping(skb);
 298         if (unlikely(i >= bp->tx_nr_rings)) {
 299                 dev_kfree_skb_any(skb);
 300                 return NETDEV_TX_OK;
 301         }
 302
 303         txq = netdev_get_tx_queue(dev, i);
 304         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 305         prod = txr->tx_prod;
 306
 307         free_size = bnxt_tx_avail(bp, txr);
 308         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 309                 netif_tx_stop_queue(txq);
 310                 return NETDEV_TX_BUSY;
 311         }
 312
 313         length = skb->len;
 314         len = skb_headlen(skb);
 315         last_frag = skb_shinfo(skb)->nr_frags;
 316
 317         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 318
 319         txbd->tx_bd_opaque = prod;
 320
 321         tx_buf = &txr->tx_buf_ring[prod];
 322         tx_buf->skb = skb;
 323         tx_buf->nr_frags = last_frag;
 324
 325         vlan_tag_flags = 0;
 326         cfa_action = bnxt_xmit_get_cfa_action(skb);
 327         if (skb_vlan_tag_present(skb)) {
 328                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 329                                  skb_vlan_tag_get(skb);
 330                 /* Currently supports 8021Q, 8021AD vlan offloads
 331                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 332                  */
 333                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 334                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 335         }
 336
 337         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 338                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 339                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 340                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 341                 void *pdata = tx_push_buf->data;
 342                 u64 *end;
 343                 int j, push_len;
 344
 345                 /* Set COAL_NOW to be ready quickly for the next push */
 346                 tx_push->tx_bd_len_flags_type =
 347                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 348                                         TX_BD_TYPE_LONG_TX_BD |
 349                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 350                                         TX_BD_FLAGS_COAL_NOW |
 351                                         TX_BD_FLAGS_PACKET_END |
 352                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 353
 354                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 355                         tx_push1->tx_bd_hsize_lflags =
 356                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 357                 else
 358                         tx_push1->tx_bd_hsize_lflags = 0;
 359
 360                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 361                 tx_push1->tx_bd_cfa_action =
 362                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 363
 364                 end = pdata + length;
 365                 end = PTR_ALIGN(end, 8) - 1;
 366                 *end = 0;
 367
 368                 skb_copy_from_linear_data(skb, pdata, len);
 369                 pdata += len;
 370                 for (j = 0; j < last_frag; j++) {
 371                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 372                         void *fptr;
 373
 374                         fptr = skb_frag_address_safe(frag);
 375                         if (!fptr)
 376                                 goto normal_tx;
 377
 378                         memcpy(pdata, fptr, skb_frag_size(frag));
 379                         pdata += skb_frag_size(frag);
 380                 }
 381
 382                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 383                 txbd->tx_bd_haddr = txr->data_mapping;
 384                 prod = NEXT_TX(prod);
 385                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 386                 memcpy(txbd, tx_push1, sizeof(*txbd));
 387                 prod = NEXT_TX(prod);
 388                 tx_push->doorbell =
 389                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 390                 txr->tx_prod = prod;
 391
 392                 tx_buf->is_push = 1;
 393                 netdev_tx_sent_queue(txq, skb->len);
 394                 wmb();  /* Sync is_push and byte queue before pushing data */
 395
 396                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 397                 if (push_len > 16) {
 398                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 399                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 400                                          (push_len - 16) << 1);
 401                 } else {
 402                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 403                                          push_len);
 404                 }
 405
 406                 goto tx_done;
 407         }
 408
 409 normal_tx:
 410         if (length < BNXT_MIN_PKT_SIZE) {
 411                 pad = BNXT_MIN_PKT_SIZE - length;
 412                 if (skb_pad(skb, pad)) {
 413                         /* SKB already freed. */
 414                         tx_buf->skb = NULL;
 415                         return NETDEV_TX_OK;
 416                 }
 417                 length = BNXT_MIN_PKT_SIZE;
 418         }
 419
 420         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 421
 422         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 423                 dev_kfree_skb_any(skb);
 424                 tx_buf->skb = NULL;
 425                 return NETDEV_TX_OK;
 426         }
 427
 428         dma_unmap_addr_set(tx_buf, mapping, mapping);
 429         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 430                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 431
 432         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 433
 434         prod = NEXT_TX(prod);
 435         txbd1 = (struct tx_bd_ext *)
 436                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 437
 438         txbd1->tx_bd_hsize_lflags = 0;
 439         if (skb_is_gso(skb)) {
 440                 u32 hdr_len;
 441
 442                 if (skb->encapsulation)
 443                         hdr_len = skb_inner_network_offset(skb) +
 444                                 skb_inner_network_header_len(skb) +
 445                                 inner_tcp_hdrlen(skb);
 446                 else
 447                         hdr_len = skb_transport_offset(skb) +
 448                                 tcp_hdrlen(skb);
 449
 450                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 451                                         TX_BD_FLAGS_T_IPID |
 452                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 453                 length = skb_shinfo(skb)->gso_size;
 454                 txbd1->tx_bd_mss = cpu_to_le32(length);
 455                 length += hdr_len;
 456         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 457                 txbd1->tx_bd_hsize_lflags =
 458                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 459                 txbd1->tx_bd_mss = 0;
 460         }
 461
 462         length >>= 9;
 463         flags |= bnxt_lhint_arr[length];
 464         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 465
 466         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 467         txbd1->tx_bd_cfa_action =
 468                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 469         for (i = 0; i < last_frag; i++) {
 470                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 471
 472                 prod = NEXT_TX(prod);
 473                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 474
 475                 len = skb_frag_size(frag);
 476                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 477                                            DMA_TO_DEVICE);
 478
 479                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 480                         goto tx_dma_error;
 481
 482                 tx_buf = &txr->tx_buf_ring[prod];
 483                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 484
 485                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 486
 487                 flags = len << TX_BD_LEN_SHIFT;
 488                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 489         }
 490
 491         flags &= ~TX_BD_LEN;
 492         txbd->tx_bd_len_flags_type =
 493                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 494                             TX_BD_FLAGS_PACKET_END);
 495
 496         netdev_tx_sent_queue(txq, skb->len);
 497
 498         /* Sync BD data before updating doorbell */
 499         wmb();
 500
 501         prod = NEXT_TX(prod);
 502         txr->tx_prod = prod;
 503
 504         if (!skb->xmit_more || netif_xmit_stopped(txq))
 505                 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 506
 507 tx_done:
 508
 509         mmiowb();
 510
 511         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 512                 if (skb->xmit_more && !tx_buf->is_push)
 513                         bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 514
 515                 netif_tx_stop_queue(txq);
 516
 517                 /* netif_tx_stop_queue() must be done before checking
 518                  * tx index in bnxt_tx_avail() below, because in
 519                  * bnxt_tx_int(), we update tx index before checking for
 520                  * netif_tx_queue_stopped().
 521                  */
 522                 smp_mb();
 523                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 524                         netif_tx_wake_queue(txq);
 525         }
 526         return NETDEV_TX_OK;
 527
 528 tx_dma_error:
 529         last_frag = i;
 530
 531         /* start back at beginning and unmap skb */
 532         prod = txr->tx_prod;
 533         tx_buf = &txr->tx_buf_ring[prod];
 534         tx_buf->skb = NULL;
 535         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 536                          skb_headlen(skb), PCI_DMA_TODEVICE);
 537         prod = NEXT_TX(prod);
 538
 539         /* unmap remaining mapped pages */
 540         for (i = 0; i < last_frag; i++) {
 541                 prod = NEXT_TX(prod);
 542                 tx_buf = &txr->tx_buf_ring[prod];
 543                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 544                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 545                                PCI_DMA_TODEVICE);
 546         }
 547
 548         dev_kfree_skb_any(skb);
 549         return NETDEV_TX_OK;
 550 }
 551
 552 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 553 {
 554         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 555         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 556         u16 cons = txr->tx_cons;
 557         struct pci_dev *pdev = bp->pdev;
 558         int i;
 559         unsigned int tx_bytes = 0;
 560
 561         for (i = 0; i < nr_pkts; i++) {
 562                 struct bnxt_sw_tx_bd *tx_buf;
 563                 struct sk_buff *skb;
 564                 int j, last;
 565
 566                 tx_buf = &txr->tx_buf_ring[cons];
 567                 cons = NEXT_TX(cons);
 568                 skb = tx_buf->skb;
 569                 tx_buf->skb = NULL;
 570
 571                 if (tx_buf->is_push) {
 572                         tx_buf->is_push = 0;
 573                         goto next_tx_int;
 574                 }
 575
 576                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 577                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 578                 last = tx_buf->nr_frags;
 579
 580                 for (j = 0; j < last; j++) {
 581                         cons = NEXT_TX(cons);
 582                         tx_buf = &txr->tx_buf_ring[cons];
 583                         dma_unmap_page(
 584                                 &pdev->dev,
 585                                 dma_unmap_addr(tx_buf, mapping),
 586                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 587                                 PCI_DMA_TODEVICE);
 588                 }
 589
 590 next_tx_int:
 591                 cons = NEXT_TX(cons);
 592
 593                 tx_bytes += skb->len;
 594                 dev_kfree_skb_any(skb);
 595         }
 596
 597         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 598         txr->tx_cons = cons;
 599
 600         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 601          * before checking for netif_tx_queue_stopped().  Without the
 602          * memory barrier, there is a small possibility that bnxt_start_xmit()
 603          * will miss it and cause the queue to be stopped forever.
 604          */
 605         smp_mb();
 606
 607         if (unlikely(netif_tx_queue_stopped(txq)) &&
 608             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 609                 __netif_tx_lock(txq, smp_processor_id());
 610                 if (netif_tx_queue_stopped(txq) &&
 611                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 612                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 613                         netif_tx_wake_queue(txq);
 614                 __netif_tx_unlock(txq);
 615         }
 616 }
 617
 618 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 619                                          gfp_t gfp)
 620 {
 621         struct device *dev = &bp->pdev->dev;
 622         struct page *page;
 623
 624         page = alloc_page(gfp);
 625         if (!page)
 626                 return NULL;
 627
 628         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 629                                       DMA_ATTR_WEAK_ORDERING);
 630         if (dma_mapping_error(dev, *mapping)) {
 631                 __free_page(page);
 632                 return NULL;
 633         }
 634         *mapping += bp->rx_dma_offset;
 635         return page;
 636 }
 637
 638 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 639                                        gfp_t gfp)
 640 {
 641         u8 *data;
 642         struct pci_dev *pdev = bp->pdev;
 643
 644         data = kmalloc(bp->rx_buf_size, gfp);
 645         if (!data)
 646                 return NULL;
 647
 648         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 649                                         bp->rx_buf_use_size, bp->rx_dir,
 650                                         DMA_ATTR_WEAK_ORDERING);
 651
 652         if (dma_mapping_error(&pdev->dev, *mapping)) {
 653                 kfree(data);
 654                 data = NULL;
 655         }
 656         return data;
 657 }
 658
 659 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 660                        u16 prod, gfp_t gfp)
 661 {
 662         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 663         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 664         dma_addr_t mapping;
 665
 666         if (BNXT_RX_PAGE_MODE(bp)) {
 667                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 668
 669                 if (!page)
 670                         return -ENOMEM;
 671
 672                 rx_buf->data = page;
 673                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 674         } else {
 675                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 676
 677                 if (!data)
 678                         return -ENOMEM;
 679
 680                 rx_buf->data = data;
 681                 rx_buf->data_ptr = data + bp->rx_offset;
 682         }
 683         rx_buf->mapping = mapping;
 684
 685         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 686         return 0;
 687 }
 688
 689 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 690 {
 691         u16 prod = rxr->rx_prod;
 692         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 693         struct rx_bd *cons_bd, *prod_bd;
 694
 695         prod_rx_buf = &rxr->rx_buf_ring[prod];
 696         cons_rx_buf = &rxr->rx_buf_ring[cons];
 697
 698         prod_rx_buf->data = data;
 699         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 700
 701         prod_rx_buf->mapping = cons_rx_buf->mapping;
 702
 703         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 704         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 705
 706         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 707 }
 708
 709 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 710 {
 711         u16 next, max = rxr->rx_agg_bmap_size;
 712
 713         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 714         if (next >= max)
 715                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 716         return next;
 717 }
 718
 719 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 720                                      struct bnxt_rx_ring_info *rxr,
 721                                      u16 prod, gfp_t gfp)
 722 {
 723         struct rx_bd *rxbd =
 724                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 725         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 726         struct pci_dev *pdev = bp->pdev;
 727         struct page *page;
 728         dma_addr_t mapping;
 729         u16 sw_prod = rxr->rx_sw_agg_prod;
 730         unsigned int offset = 0;
 731
 732         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 733                 page = rxr->rx_page;
 734                 if (!page) {
 735                         page = alloc_page(gfp);
 736                         if (!page)
 737                                 return -ENOMEM;
 738                         rxr->rx_page = page;
 739                         rxr->rx_page_offset = 0;
 740                 }
 741                 offset = rxr->rx_page_offset;
 742                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 743                 if (rxr->rx_page_offset == PAGE_SIZE)
 744                         rxr->rx_page = NULL;
 745                 else
 746                         get_page(page);
 747         } else {
 748                 page = alloc_page(gfp);
 749                 if (!page)
 750                         return -ENOMEM;
 751         }
 752
 753         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 754                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 755                                      DMA_ATTR_WEAK_ORDERING);
 756         if (dma_mapping_error(&pdev->dev, mapping)) {
 757                 __free_page(page);
 758                 return -EIO;
 759         }
 760
 761         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 762                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 763
 764         __set_bit(sw_prod, rxr->rx_agg_bmap);
 765         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 766         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 767
 768         rx_agg_buf->page = page;
 769         rx_agg_buf->offset = offset;
 770         rx_agg_buf->mapping = mapping;
 771         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 772         rxbd->rx_bd_opaque = sw_prod;
 773         return 0;
 774 }
 775
 776 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 777                                    u32 agg_bufs)
 778 {
 779         struct bnxt *bp = bnapi->bp;
 780         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 781         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 782         u16 prod = rxr->rx_agg_prod;
 783         u16 sw_prod = rxr->rx_sw_agg_prod;
 784         u32 i;
 785
 786         for (i = 0; i < agg_bufs; i++) {
 787                 u16 cons;
 788                 struct rx_agg_cmp *agg;
 789                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 790                 struct rx_bd *prod_bd;
 791                 struct page *page;
 792
 793                 agg = (struct rx_agg_cmp *)
 794                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 795                 cons = agg->rx_agg_cmp_opaque;
 796                 __clear_bit(cons, rxr->rx_agg_bmap);
 797
 798                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 799                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 800
 801                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 802                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 803                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 804
 805                 /* It is possible for sw_prod to be equal to cons, so
 806                  * set cons_rx_buf->page to NULL first.
 807                  */
 808                 page = cons_rx_buf->page;
 809                 cons_rx_buf->page = NULL;
 810                 prod_rx_buf->page = page;
 811                 prod_rx_buf->offset = cons_rx_buf->offset;
 812
 813                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 814
 815                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 816
 817                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 818                 prod_bd->rx_bd_opaque = sw_prod;
 819
 820                 prod = NEXT_RX_AGG(prod);
 821                 sw_prod = NEXT_RX_AGG(sw_prod);
 822                 cp_cons = NEXT_CMP(cp_cons);
 823         }
 824         rxr->rx_agg_prod = prod;
 825         rxr->rx_sw_agg_prod = sw_prod;
 826 }
 827
 828 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 829                                         struct bnxt_rx_ring_info *rxr,
 830                                         u16 cons, void *data, u8 *data_ptr,
 831                                         dma_addr_t dma_addr,
 832                                         unsigned int offset_and_len)
 833 {
 834         unsigned int payload = offset_and_len >> 16;
 835         unsigned int len = offset_and_len & 0xffff;
 836         struct skb_frag_struct *frag;
 837         struct page *page = data;
 838         u16 prod = rxr->rx_prod;
 839         struct sk_buff *skb;
 840         int off, err;
 841
 842         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 843         if (unlikely(err)) {
 844                 bnxt_reuse_rx_data(rxr, cons, data);
 845                 return NULL;
 846         }
 847         dma_addr -= bp->rx_dma_offset;
 848         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 849                              DMA_ATTR_WEAK_ORDERING);
 850
 851         if (unlikely(!payload))
 852                 payload = eth_get_headlen(data_ptr, len);
 853
 854         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 855         if (!skb) {
 856                 __free_page(page);
 857                 return NULL;
 858         }
 859
 860         off = (void *)data_ptr - page_address(page);
 861         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 862         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 863                payload + NET_IP_ALIGN);
 864
 865         frag = &skb_shinfo(skb)->frags[0];
 866         skb_frag_size_sub(frag, payload);
 867         frag->page_offset += payload;
 868         skb->data_len -= payload;
 869         skb->tail += payload;
 870
 871         return skb;
 872 }
 873
 874 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 875                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 876                                    void *data, u8 *data_ptr,
 877                                    dma_addr_t dma_addr,
 878                                    unsigned int offset_and_len)
 879 {
 880         u16 prod = rxr->rx_prod;
 881         struct sk_buff *skb;
 882         int err;
 883
 884         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 885         if (unlikely(err)) {
 886                 bnxt_reuse_rx_data(rxr, cons, data);
 887                 return NULL;
 888         }
 889
 890         skb = build_skb(data, 0);
 891         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 892                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 893         if (!skb) {
 894                 kfree(data);
 895                 return NULL;
 896         }
 897
 898         skb_reserve(skb, bp->rx_offset);
 899         skb_put(skb, offset_and_len & 0xffff);
 900         return skb;
 901 }
 902
 903 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 904                                      struct sk_buff *skb, u16 cp_cons,
 905                                      u32 agg_bufs)
 906 {
 907         struct pci_dev *pdev = bp->pdev;
 908         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 909         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 910         u16 prod = rxr->rx_agg_prod;
 911         u32 i;
 912
 913         for (i = 0; i < agg_bufs; i++) {
 914                 u16 cons, frag_len;
 915                 struct rx_agg_cmp *agg;
 916                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 917                 struct page *page;
 918                 dma_addr_t mapping;
 919
 920                 agg = (struct rx_agg_cmp *)
 921                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 922                 cons = agg->rx_agg_cmp_opaque;
 923                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 924                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 925
 926                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 927                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 928                                    cons_rx_buf->offset, frag_len);
 929                 __clear_bit(cons, rxr->rx_agg_bmap);
 930
 931                 /* It is possible for bnxt_alloc_rx_page() to allocate
 932                  * a sw_prod index that equals the cons index, so we
 933                  * need to clear the cons entry now.
 934                  */
 935                 mapping = cons_rx_buf->mapping;
 936                 page = cons_rx_buf->page;
 937                 cons_rx_buf->page = NULL;
 938
 939                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 940                         struct skb_shared_info *shinfo;
 941                         unsigned int nr_frags;
 942
 943                         shinfo = skb_shinfo(skb);
 944                         nr_frags = --shinfo->nr_frags;
 945                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 946
 947                         dev_kfree_skb(skb);
 948
 949                         cons_rx_buf->page = page;
 950
 951                         /* Update prod since possibly some pages have been
 952                          * allocated already.
 953                          */
 954                         rxr->rx_agg_prod = prod;
 955                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 956                         return NULL;
 957                 }
 958
 959                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 960                                      PCI_DMA_FROMDEVICE,
 961                                      DMA_ATTR_WEAK_ORDERING);
 962
 963                 skb->data_len += frag_len;
 964                 skb->len += frag_len;
 965                 skb->truesize += PAGE_SIZE;
 966
 967                 prod = NEXT_RX_AGG(prod);
 968                 cp_cons = NEXT_CMP(cp_cons);
 969         }
 970         rxr->rx_agg_prod = prod;
 971         return skb;
 972 }
 973
 974 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 975                                u8 agg_bufs, u32 *raw_cons)
 976 {
 977         u16 last;
 978         struct rx_agg_cmp *agg;
 979
 980         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 981         last = RING_CMP(*raw_cons);
 982         agg = (struct rx_agg_cmp *)
 983                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 984         return RX_AGG_CMP_VALID(agg, *raw_cons);
 985 }
 986
 987 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 988                                             unsigned int len,
 989                                             dma_addr_t mapping)
 990 {
 991         struct bnxt *bp = bnapi->bp;
 992         struct pci_dev *pdev = bp->pdev;
 993         struct sk_buff *skb;
 994
 995         skb = napi_alloc_skb(&bnapi->napi, len);
 996         if (!skb)
 997                 return NULL;
 998
 999         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1000                                 bp->rx_dir);
1001
1002         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1003                len + NET_IP_ALIGN);
1004
1005         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1006                                    bp->rx_dir);
1007
1008         skb_put(skb, len);
1009         return skb;
1010 }
1011
1012 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1013                            u32 *raw_cons, void *cmp)
1014 {
1015         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1016         struct rx_cmp *rxcmp = cmp;
1017         u32 tmp_raw_cons = *raw_cons;
1018         u8 cmp_type, agg_bufs = 0;
1019
1020         cmp_type = RX_CMP_TYPE(rxcmp);
1021
1022         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1023                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1024                             RX_CMP_AGG_BUFS) >>
1025                            RX_CMP_AGG_BUFS_SHIFT;
1026         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1027                 struct rx_tpa_end_cmp *tpa_end = cmp;
1028
1029                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1030                             RX_TPA_END_CMP_AGG_BUFS) >>
1031                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1032         }
1033
1034         if (agg_bufs) {
1035                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1036                         return -EBUSY;
1037         }
1038         *raw_cons = tmp_raw_cons;
1039         return 0;
1040 }
1041
1042 static void bnxt_queue_sp_work(struct bnxt *bp)
1043 {
1044         if (BNXT_PF(bp))
1045                 queue_work(bnxt_pf_wq, &bp->sp_task);
1046         else
1047                 schedule_work(&bp->sp_task);
1048 }
1049
1050 static void bnxt_cancel_sp_work(struct bnxt *bp)
1051 {
1052         if (BNXT_PF(bp))
1053                 flush_workqueue(bnxt_pf_wq);
1054         else
1055                 cancel_work_sync(&bp->sp_task);
1056 }
1057
1058 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1059 {
1060         if (!rxr->bnapi->in_reset) {
1061                 rxr->bnapi->in_reset = true;
1062                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1063                 bnxt_queue_sp_work(bp);
1064         }
1065         rxr->rx_next_cons = 0xffff;
1066 }
1067
1068 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1069                            struct rx_tpa_start_cmp *tpa_start,
1070                            struct rx_tpa_start_cmp_ext *tpa_start1)
1071 {
1072         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1073         u16 cons, prod;
1074         struct bnxt_tpa_info *tpa_info;
1075         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1076         struct rx_bd *prod_bd;
1077         dma_addr_t mapping;
1078
1079         cons = tpa_start->rx_tpa_start_cmp_opaque;
1080         prod = rxr->rx_prod;
1081         cons_rx_buf = &rxr->rx_buf_ring[cons];
1082         prod_rx_buf = &rxr->rx_buf_ring[prod];
1083         tpa_info = &rxr->rx_tpa[agg_id];
1084
1085         if (unlikely(cons != rxr->rx_next_cons)) {
1086                 bnxt_sched_reset(bp, rxr);
1087                 return;
1088         }
1089         /* Store cfa_code in tpa_info to use in tpa_end
1090          * completion processing.
1091          */
1092         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1093         prod_rx_buf->data = tpa_info->data;
1094         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1095
1096         mapping = tpa_info->mapping;
1097         prod_rx_buf->mapping = mapping;
1098
1099         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1100
1101         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1102
1103         tpa_info->data = cons_rx_buf->data;
1104         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1105         cons_rx_buf->data = NULL;
1106         tpa_info->mapping = cons_rx_buf->mapping;
1107
1108         tpa_info->len =
1109                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1110                                 RX_TPA_START_CMP_LEN_SHIFT;
1111         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1112                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1113
1114                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1115                 tpa_info->gso_type = SKB_GSO_TCPV4;
1116                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1117                 if (hash_type == 3)
1118                         tpa_info->gso_type = SKB_GSO_TCPV6;
1119                 tpa_info->rss_hash =
1120                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1121         } else {
1122                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1123                 tpa_info->gso_type = 0;
1124                 if (netif_msg_rx_err(bp))
1125                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1126         }
1127         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1128         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1129         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1130
1131         rxr->rx_prod = NEXT_RX(prod);
1132         cons = NEXT_RX(cons);
1133         rxr->rx_next_cons = NEXT_RX(cons);
1134         cons_rx_buf = &rxr->rx_buf_ring[cons];
1135
1136         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1137         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1138         cons_rx_buf->data = NULL;
1139 }
1140
1141 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1142                            u16 cp_cons, u32 agg_bufs)
1143 {
1144         if (agg_bufs)
1145                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1146 }
1147
1148 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1149                                            int payload_off, int tcp_ts,
1150                                            struct sk_buff *skb)
1151 {
1152 #ifdef CONFIG_INET
1153         struct tcphdr *th;
1154         int len, nw_off;
1155         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1156         u32 hdr_info = tpa_info->hdr_info;
1157         bool loopback = false;
1158
1159         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1160         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1161         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1162
1163         /* If the packet is an internal loopback packet, the offsets will
1164          * have an extra 4 bytes.
1165          */
1166         if (inner_mac_off == 4) {
1167                 loopback = true;
1168         } else if (inner_mac_off > 4) {
1169                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1170                                             ETH_HLEN - 2));
1171
1172                 /* We only support inner iPv4/ipv6.  If we don't see the
1173                  * correct protocol ID, it must be a loopback packet where
1174                  * the offsets are off by 4.
1175                  */
1176                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1177                         loopback = true;
1178         }
1179         if (loopback) {
1180                 /* internal loopback packet, subtract all offsets by 4 */
1181                 inner_ip_off -= 4;
1182                 inner_mac_off -= 4;
1183                 outer_ip_off -= 4;
1184         }
1185
1186         nw_off = inner_ip_off - ETH_HLEN;
1187         skb_set_network_header(skb, nw_off);
1188         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1189                 struct ipv6hdr *iph = ipv6_hdr(skb);
1190
1191                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1192                 len = skb->len - skb_transport_offset(skb);
1193                 th = tcp_hdr(skb);
1194                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1195         } else {
1196                 struct iphdr *iph = ip_hdr(skb);
1197
1198                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1199                 len = skb->len - skb_transport_offset(skb);
1200                 th = tcp_hdr(skb);
1201                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1202         }
1203
1204         if (inner_mac_off) { /* tunnel */
1205                 struct udphdr *uh = NULL;
1206                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1207                                             ETH_HLEN - 2));
1208
1209                 if (proto == htons(ETH_P_IP)) {
1210                         struct iphdr *iph = (struct iphdr *)skb->data;
1211
1212                         if (iph->protocol == IPPROTO_UDP)
1213                                 uh = (struct udphdr *)(iph + 1);
1214                 } else {
1215                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1216
1217                         if (iph->nexthdr == IPPROTO_UDP)
1218                                 uh = (struct udphdr *)(iph + 1);
1219                 }
1220                 if (uh) {
1221                         if (uh->check)
1222                                 skb_shinfo(skb)->gso_type |=
1223                                         SKB_GSO_UDP_TUNNEL_CSUM;
1224                         else
1225                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1226                 }
1227         }
1228 #endif
1229         return skb;
1230 }
1231
1232 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1233 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1234
1235 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1236                                            int payload_off, int tcp_ts,
1237                                            struct sk_buff *skb)
1238 {
1239 #ifdef CONFIG_INET
1240         struct tcphdr *th;
1241         int len, nw_off, tcp_opt_len = 0;
1242
1243         if (tcp_ts)
1244                 tcp_opt_len = 12;
1245
1246         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1247                 struct iphdr *iph;
1248
1249                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1250                          ETH_HLEN;
1251                 skb_set_network_header(skb, nw_off);
1252                 iph = ip_hdr(skb);
1253                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1254                 len = skb->len - skb_transport_offset(skb);
1255                 th = tcp_hdr(skb);
1256                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1257         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1258                 struct ipv6hdr *iph;
1259
1260                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1261                          ETH_HLEN;
1262                 skb_set_network_header(skb, nw_off);
1263                 iph = ipv6_hdr(skb);
1264                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1265                 len = skb->len - skb_transport_offset(skb);
1266                 th = tcp_hdr(skb);
1267                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1268         } else {
1269                 dev_kfree_skb_any(skb);
1270                 return NULL;
1271         }
1272
1273         if (nw_off) { /* tunnel */
1274                 struct udphdr *uh = NULL;
1275
1276                 if (skb->protocol == htons(ETH_P_IP)) {
1277                         struct iphdr *iph = (struct iphdr *)skb->data;
1278
1279                         if (iph->protocol == IPPROTO_UDP)
1280                                 uh = (struct udphdr *)(iph + 1);
1281                 } else {
1282                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1283
1284                         if (iph->nexthdr == IPPROTO_UDP)
1285                                 uh = (struct udphdr *)(iph + 1);
1286                 }
1287                 if (uh) {
1288                         if (uh->check)
1289                                 skb_shinfo(skb)->gso_type |=
1290                                         SKB_GSO_UDP_TUNNEL_CSUM;
1291                         else
1292                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1293                 }
1294         }
1295 #endif
1296         return skb;
1297 }
1298
1299 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1300                                            struct bnxt_tpa_info *tpa_info,
1301                                            struct rx_tpa_end_cmp *tpa_end,
1302                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1303                                            struct sk_buff *skb)
1304 {
1305 #ifdef CONFIG_INET
1306         int payload_off;
1307         u16 segs;
1308
1309         segs = TPA_END_TPA_SEGS(tpa_end);
1310         if (segs == 1)
1311                 return skb;
1312
1313         NAPI_GRO_CB(skb)->count = segs;
1314         skb_shinfo(skb)->gso_size =
1315                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1316         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1317         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1318                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1319                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1320         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1321         if (likely(skb))
1322                 tcp_gro_complete(skb);
1323 #endif
1324         return skb;
1325 }
1326
1327 /* Given the cfa_code of a received packet determine which
1328  * netdev (vf-rep or PF) the packet is destined to.
1329  */
1330 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1331 {
1332         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1333
1334         /* if vf-rep dev is NULL, the must belongs to the PF */
1335         return dev ? dev : bp->dev;
1336 }
1337
1338 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1339                                            struct bnxt_napi *bnapi,
1340                                            u32 *raw_cons,
1341                                            struct rx_tpa_end_cmp *tpa_end,
1342                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1343                                            u8 *event)
1344 {
1345         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1346         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1347         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1348         u8 *data_ptr, agg_bufs;
1349         u16 cp_cons = RING_CMP(*raw_cons);
1350         unsigned int len;
1351         struct bnxt_tpa_info *tpa_info;
1352         dma_addr_t mapping;
1353         struct sk_buff *skb;
1354         void *data;
1355
1356         if (unlikely(bnapi->in_reset)) {
1357                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1358
1359                 if (rc < 0)
1360                         return ERR_PTR(-EBUSY);
1361                 return NULL;
1362         }
1363
1364         tpa_info = &rxr->rx_tpa[agg_id];
1365         data = tpa_info->data;
1366         data_ptr = tpa_info->data_ptr;
1367         prefetch(data_ptr);
1368         len = tpa_info->len;
1369         mapping = tpa_info->mapping;
1370
1371         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1372                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1373
1374         if (agg_bufs) {
1375                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1376                         return ERR_PTR(-EBUSY);
1377
1378                 *event |= BNXT_AGG_EVENT;
1379                 cp_cons = NEXT_CMP(cp_cons);
1380         }
1381
1382         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1383                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1384                 if (agg_bufs > MAX_SKB_FRAGS)
1385                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1386                                     agg_bufs, (int)MAX_SKB_FRAGS);
1387                 return NULL;
1388         }
1389
1390         if (len <= bp->rx_copy_thresh) {
1391                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1392                 if (!skb) {
1393                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1394                         return NULL;
1395                 }
1396         } else {
1397                 u8 *new_data;
1398                 dma_addr_t new_mapping;
1399
1400                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1401                 if (!new_data) {
1402                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1403                         return NULL;
1404                 }
1405
1406                 tpa_info->data = new_data;
1407                 tpa_info->data_ptr = new_data + bp->rx_offset;
1408                 tpa_info->mapping = new_mapping;
1409
1410                 skb = build_skb(data, 0);
1411                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1412                                        bp->rx_buf_use_size, bp->rx_dir,
1413                                        DMA_ATTR_WEAK_ORDERING);
1414
1415                 if (!skb) {
1416                         kfree(data);
1417                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1418                         return NULL;
1419                 }
1420                 skb_reserve(skb, bp->rx_offset);
1421                 skb_put(skb, len);
1422         }
1423
1424         if (agg_bufs) {
1425                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1426                 if (!skb) {
1427                         /* Page reuse already handled by bnxt_rx_pages(). */
1428                         return NULL;
1429                 }
1430         }
1431
1432         skb->protocol =
1433                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1434
1435         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1436                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1437
1438         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1439             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1440                 u16 vlan_proto = tpa_info->metadata >>
1441                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1442                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1443
1444                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1445         }
1446
1447         skb_checksum_none_assert(skb);
1448         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1449                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1450                 skb->csum_level =
1451                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1452         }
1453
1454         if (TPA_END_GRO(tpa_end))
1455                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1456
1457         return skb;
1458 }
1459
1460 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1461                              struct sk_buff *skb)
1462 {
1463         if (skb->dev != bp->dev) {
1464                 /* this packet belongs to a vf-rep */
1465                 bnxt_vf_rep_rx(bp, skb);
1466                 return;
1467         }
1468         skb_record_rx_queue(skb, bnapi->index);
1469         napi_gro_receive(&bnapi->napi, skb);
1470 }
1471
1472 /* returns the following:
1473  * 1       - 1 packet successfully received
1474  * 0       - successful TPA_START, packet not completed yet
1475  * -EBUSY  - completion ring does not have all the agg buffers yet
1476  * -ENOMEM - packet aborted due to out of memory
1477  * -EIO    - packet aborted due to hw error indicated in BD
1478  */
1479 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1480                        u8 *event)
1481 {
1482         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1483         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1484         struct net_device *dev = bp->dev;
1485         struct rx_cmp *rxcmp;
1486         struct rx_cmp_ext *rxcmp1;
1487         u32 tmp_raw_cons = *raw_cons;
1488         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1489         struct bnxt_sw_rx_bd *rx_buf;
1490         unsigned int len;
1491         u8 *data_ptr, agg_bufs, cmp_type;
1492         dma_addr_t dma_addr;
1493         struct sk_buff *skb;
1494         void *data;
1495         int rc = 0;
1496         u32 misc;
1497
1498         rxcmp = (struct rx_cmp *)
1499                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1500
1501         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1502         cp_cons = RING_CMP(tmp_raw_cons);
1503         rxcmp1 = (struct rx_cmp_ext *)
1504                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1505
1506         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1507                 return -EBUSY;
1508
1509         cmp_type = RX_CMP_TYPE(rxcmp);
1510
1511         prod = rxr->rx_prod;
1512
1513         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1514                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1515                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1516
1517                 *event |= BNXT_RX_EVENT;
1518                 goto next_rx_no_prod_no_len;
1519
1520         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1521                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1522                                    (struct rx_tpa_end_cmp *)rxcmp,
1523                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1524
1525                 if (IS_ERR(skb))
1526                         return -EBUSY;
1527
1528                 rc = -ENOMEM;
1529                 if (likely(skb)) {
1530                         bnxt_deliver_skb(bp, bnapi, skb);
1531                         rc = 1;
1532                 }
1533                 *event |= BNXT_RX_EVENT;
1534                 goto next_rx_no_prod_no_len;
1535         }
1536
1537         cons = rxcmp->rx_cmp_opaque;
1538         rx_buf = &rxr->rx_buf_ring[cons];
1539         data = rx_buf->data;
1540         data_ptr = rx_buf->data_ptr;
1541         if (unlikely(cons != rxr->rx_next_cons)) {
1542                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1543
1544                 bnxt_sched_reset(bp, rxr);
1545                 return rc1;
1546         }
1547         prefetch(data_ptr);
1548
1549         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1550         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1551
1552         if (agg_bufs) {
1553                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1554                         return -EBUSY;
1555
1556                 cp_cons = NEXT_CMP(cp_cons);
1557                 *event |= BNXT_AGG_EVENT;
1558         }
1559         *event |= BNXT_RX_EVENT;
1560
1561         rx_buf->data = NULL;
1562         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1563                 bnxt_reuse_rx_data(rxr, cons, data);
1564                 if (agg_bufs)
1565                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1566
1567                 rc = -EIO;
1568                 goto next_rx;
1569         }
1570
1571         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1572         dma_addr = rx_buf->mapping;
1573
1574         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1575                 rc = 1;
1576                 goto next_rx;
1577         }
1578
1579         if (len <= bp->rx_copy_thresh) {
1580                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1581                 bnxt_reuse_rx_data(rxr, cons, data);
1582                 if (!skb) {
1583                         rc = -ENOMEM;
1584                         goto next_rx;
1585                 }
1586         } else {
1587                 u32 payload;
1588
1589                 if (rx_buf->data_ptr == data_ptr)
1590                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1591                 else
1592                         payload = 0;
1593                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1594                                       payload | len);
1595                 if (!skb) {
1596                         rc = -ENOMEM;
1597                         goto next_rx;
1598                 }
1599         }
1600
1601         if (agg_bufs) {
1602                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1603                 if (!skb) {
1604                         rc = -ENOMEM;
1605                         goto next_rx;
1606                 }
1607         }
1608
1609         if (RX_CMP_HASH_VALID(rxcmp)) {
1610                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1611                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1612
1613                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1614                 if (hash_type != 1 && hash_type != 3)
1615                         type = PKT_HASH_TYPE_L3;
1616                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1617         }
1618
1619         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1620         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1621
1622         if ((rxcmp1->rx_cmp_flags2 &
1623              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1624             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1625                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1626                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1627                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1628
1629                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1630         }
1631
1632         skb_checksum_none_assert(skb);
1633         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1634                 if (dev->features & NETIF_F_RXCSUM) {
1635                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1636                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1637                 }
1638         } else {
1639                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1640                         if (dev->features & NETIF_F_RXCSUM)
1641                                 cpr->rx_l4_csum_errors++;
1642                 }
1643         }
1644
1645         bnxt_deliver_skb(bp, bnapi, skb);
1646         rc = 1;
1647
1648 next_rx:
1649         rxr->rx_prod = NEXT_RX(prod);
1650         rxr->rx_next_cons = NEXT_RX(cons);
1651
1652         cpr->rx_packets += 1;
1653         cpr->rx_bytes += len;
1654
1655 next_rx_no_prod_no_len:
1656         *raw_cons = tmp_raw_cons;
1657
1658         return rc;
1659 }
1660
1661 /* In netpoll mode, if we are using a combined completion ring, we need to
1662  * discard the rx packets and recycle the buffers.
1663  */
1664 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1665                                  u32 *raw_cons, u8 *event)
1666 {
1667         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1668         u32 tmp_raw_cons = *raw_cons;
1669         struct rx_cmp_ext *rxcmp1;
1670         struct rx_cmp *rxcmp;
1671         u16 cp_cons;
1672         u8 cmp_type;
1673
1674         cp_cons = RING_CMP(tmp_raw_cons);
1675         rxcmp = (struct rx_cmp *)
1676                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1677
1678         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1679         cp_cons = RING_CMP(tmp_raw_cons);
1680         rxcmp1 = (struct rx_cmp_ext *)
1681                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1682
1683         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1684                 return -EBUSY;
1685
1686         cmp_type = RX_CMP_TYPE(rxcmp);
1687         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1688                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1689                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1690         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1691                 struct rx_tpa_end_cmp_ext *tpa_end1;
1692
1693                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1694                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1695                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1696         }
1697         return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1698 }
1699
1700 #define BNXT_GET_EVENT_PORT(data)       \
1701         ((data) &                       \
1702          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1703
1704 static int bnxt_async_event_process(struct bnxt *bp,
1705                                     struct hwrm_async_event_cmpl *cmpl)
1706 {
1707         u16 event_id = le16_to_cpu(cmpl->event_id);
1708
1709         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1710         switch (event_id) {
1711         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1712                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1713                 struct bnxt_link_info *link_info = &bp->link_info;
1714
1715                 if (BNXT_VF(bp))
1716                         goto async_event_process_exit;
1717
1718                 /* print unsupported speed warning in forced speed mode only */
1719                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1720                     (data1 & 0x20000)) {
1721                         u16 fw_speed = link_info->force_link_speed;
1722                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1723
1724                         if (speed != SPEED_UNKNOWN)
1725                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1726                                             speed);
1727                 }
1728                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1729                 /* fall thru */
1730         }
1731         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1732                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1733                 break;
1734         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1735                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1736                 break;
1737         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1738                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1739                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1740
1741                 if (BNXT_VF(bp))
1742                         break;
1743
1744                 if (bp->pf.port_id != port_id)
1745                         break;
1746
1747                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1748                 break;
1749         }
1750         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1751                 if (BNXT_PF(bp))
1752                         goto async_event_process_exit;
1753                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1754                 break;
1755         default:
1756                 goto async_event_process_exit;
1757         }
1758         bnxt_queue_sp_work(bp);
1759 async_event_process_exit:
1760         bnxt_ulp_async_events(bp, cmpl);
1761         return 0;
1762 }
1763
1764 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1765 {
1766         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1767         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1768         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1769                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1770
1771         switch (cmpl_type) {
1772         case CMPL_BASE_TYPE_HWRM_DONE:
1773                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1774                 if (seq_id == bp->hwrm_intr_seq_id)
1775                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1776                 else
1777                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1778                 break;
1779
1780         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1781                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1782
1783                 if ((vf_id < bp->pf.first_vf_id) ||
1784                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1785                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1786                                    vf_id);
1787                         return -EINVAL;
1788                 }
1789
1790                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1791                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1792                 bnxt_queue_sp_work(bp);
1793                 break;
1794
1795         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1796                 bnxt_async_event_process(bp,
1797                                          (struct hwrm_async_event_cmpl *)txcmp);
1798
1799         default:
1800                 break;
1801         }
1802
1803         return 0;
1804 }
1805
1806 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1807 {
1808         struct bnxt_napi *bnapi = dev_instance;
1809         struct bnxt *bp = bnapi->bp;
1810         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1811         u32 cons = RING_CMP(cpr->cp_raw_cons);
1812
1813         cpr->event_ctr++;
1814         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1815         napi_schedule(&bnapi->napi);
1816         return IRQ_HANDLED;
1817 }
1818
1819 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1820 {
1821         u32 raw_cons = cpr->cp_raw_cons;
1822         u16 cons = RING_CMP(raw_cons);
1823         struct tx_cmp *txcmp;
1824
1825         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1826
1827         return TX_CMP_VALID(txcmp, raw_cons);
1828 }
1829
1830 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1831 {
1832         struct bnxt_napi *bnapi = dev_instance;
1833         struct bnxt *bp = bnapi->bp;
1834         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1835         u32 cons = RING_CMP(cpr->cp_raw_cons);
1836         u32 int_status;
1837
1838         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1839
1840         if (!bnxt_has_work(bp, cpr)) {
1841                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1842                 /* return if erroneous interrupt */
1843                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1844                         return IRQ_NONE;
1845         }
1846
1847         /* disable ring IRQ */
1848         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1849
1850         /* Return here if interrupt is shared and is disabled. */
1851         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1852                 return IRQ_HANDLED;
1853
1854         napi_schedule(&bnapi->napi);
1855         return IRQ_HANDLED;
1856 }
1857
1858 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1859 {
1860         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1861         u32 raw_cons = cpr->cp_raw_cons;
1862         u32 cons;
1863         int tx_pkts = 0;
1864         int rx_pkts = 0;
1865         u8 event = 0;
1866         struct tx_cmp *txcmp;
1867
1868         while (1) {
1869                 int rc;
1870
1871                 cons = RING_CMP(raw_cons);
1872                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1873
1874                 if (!TX_CMP_VALID(txcmp, raw_cons))
1875                         break;
1876
1877                 /* The valid test of the entry must be done first before
1878                  * reading any further.
1879                  */
1880                 dma_rmb();
1881                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1882                         tx_pkts++;
1883                         /* return full budget so NAPI will complete. */
1884                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1885                                 rx_pkts = budget;
1886                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1887                         if (likely(budget))
1888                                 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1889                         else
1890                                 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1891                                                            &event);
1892                         if (likely(rc >= 0))
1893                                 rx_pkts += rc;
1894                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1895                          * the NAPI budget.  Otherwise, we may potentially loop
1896                          * here forever if we consistently cannot allocate
1897                          * buffers.
1898                          */
1899                         else if (rc == -ENOMEM && budget)
1900                                 rx_pkts++;
1901                         else if (rc == -EBUSY)  /* partial completion */
1902                                 break;
1903                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1904                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1905                                     (TX_CMP_TYPE(txcmp) ==
1906                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1907                                     (TX_CMP_TYPE(txcmp) ==
1908                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1909                         bnxt_hwrm_handler(bp, txcmp);
1910                 }
1911                 raw_cons = NEXT_RAW_CMP(raw_cons);
1912
1913                 if (rx_pkts == budget)
1914                         break;
1915         }
1916
1917         if (event & BNXT_TX_EVENT) {
1918                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1919                 void __iomem *db = txr->tx_doorbell;
1920                 u16 prod = txr->tx_prod;
1921
1922                 /* Sync BD data before updating doorbell */
1923                 wmb();
1924
1925                 bnxt_db_write_relaxed(bp, db, DB_KEY_TX | prod);
1926         }
1927
1928         cpr->cp_raw_cons = raw_cons;
1929         /* ACK completion ring before freeing tx ring and producing new
1930          * buffers in rx/agg rings to prevent overflowing the completion
1931          * ring.
1932          */
1933         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1934
1935         if (tx_pkts)
1936                 bnapi->tx_int(bp, bnapi, tx_pkts);
1937
1938         if (event & BNXT_RX_EVENT) {
1939                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1940
1941                 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1942                 if (event & BNXT_AGG_EVENT)
1943                         bnxt_db_write(bp, rxr->rx_agg_doorbell,
1944                                       DB_KEY_RX | rxr->rx_agg_prod);
1945         }
1946         return rx_pkts;
1947 }
1948
1949 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1950 {
1951         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1952         struct bnxt *bp = bnapi->bp;
1953         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1954         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1955         struct tx_cmp *txcmp;
1956         struct rx_cmp_ext *rxcmp1;
1957         u32 cp_cons, tmp_raw_cons;
1958         u32 raw_cons = cpr->cp_raw_cons;
1959         u32 rx_pkts = 0;
1960         u8 event = 0;
1961
1962         while (1) {
1963                 int rc;
1964
1965                 cp_cons = RING_CMP(raw_cons);
1966                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1967
1968                 if (!TX_CMP_VALID(txcmp, raw_cons))
1969                         break;
1970
1971                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1972                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1973                         cp_cons = RING_CMP(tmp_raw_cons);
1974                         rxcmp1 = (struct rx_cmp_ext *)
1975                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1976
1977                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1978                                 break;
1979
1980                         /* force an error to recycle the buffer */
1981                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1982                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1983
1984                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1985                         if (likely(rc == -EIO) && budget)
1986                                 rx_pkts++;
1987                         else if (rc == -EBUSY)  /* partial completion */
1988                                 break;
1989                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1990                                     CMPL_BASE_TYPE_HWRM_DONE)) {
1991                         bnxt_hwrm_handler(bp, txcmp);
1992                 } else {
1993                         netdev_err(bp->dev,
1994                                    "Invalid completion received on special ring\n");
1995                 }
1996                 raw_cons = NEXT_RAW_CMP(raw_cons);
1997
1998                 if (rx_pkts == budget)
1999                         break;
2000         }
2001
2002         cpr->cp_raw_cons = raw_cons;
2003         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2004         bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
2005
2006         if (event & BNXT_AGG_EVENT)
2007                 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2008                               DB_KEY_RX | rxr->rx_agg_prod);
2009
2010         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2011                 napi_complete_done(napi, rx_pkts);
2012                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2013         }
2014         return rx_pkts;
2015 }
2016
2017 static int bnxt_poll(struct napi_struct *napi, int budget)
2018 {
2019         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2020         struct bnxt *bp = bnapi->bp;
2021         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2022         int work_done = 0;
2023
2024         while (1) {
2025                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2026
2027                 if (work_done >= budget)
2028                         break;
2029
2030                 if (!bnxt_has_work(bp, cpr)) {
2031                         if (napi_complete_done(napi, work_done))
2032                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2033                                                  cpr->cp_raw_cons);
2034                         break;
2035                 }
2036         }
2037         if (bp->flags & BNXT_FLAG_DIM) {
2038                 struct net_dim_sample dim_sample;
2039
2040                 net_dim_sample(cpr->event_ctr,
2041                                cpr->rx_packets,
2042                                cpr->rx_bytes,
2043                                &dim_sample);
2044                 net_dim(&cpr->dim, dim_sample);
2045         }
2046         mmiowb();
2047         return work_done;
2048 }
2049
2050 static void bnxt_free_tx_skbs(struct bnxt *bp)
2051 {
2052         int i, max_idx;
2053         struct pci_dev *pdev = bp->pdev;
2054
2055         if (!bp->tx_ring)
2056                 return;
2057
2058         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2059         for (i = 0; i < bp->tx_nr_rings; i++) {
2060                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2061                 int j;
2062
2063                 for (j = 0; j < max_idx;) {
2064                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2065                         struct sk_buff *skb = tx_buf->skb;
2066                         int k, last;
2067
2068                         if (!skb) {
2069                                 j++;
2070                                 continue;
2071                         }
2072
2073                         tx_buf->skb = NULL;
2074
2075                         if (tx_buf->is_push) {
2076                                 dev_kfree_skb(skb);
2077                                 j += 2;
2078                                 continue;
2079                         }
2080
2081                         dma_unmap_single(&pdev->dev,
2082                                          dma_unmap_addr(tx_buf, mapping),
2083                                          skb_headlen(skb),
2084                                          PCI_DMA_TODEVICE);
2085
2086                         last = tx_buf->nr_frags;
2087                         j += 2;
2088                         for (k = 0; k < last; k++, j++) {
2089                                 int ring_idx = j & bp->tx_ring_mask;
2090                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2091
2092                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2093                                 dma_unmap_page(
2094                                         &pdev->dev,
2095                                         dma_unmap_addr(tx_buf, mapping),
2096                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2097                         }
2098                         dev_kfree_skb(skb);
2099                 }
2100                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2101         }
2102 }
2103
2104 static void bnxt_free_rx_skbs(struct bnxt *bp)
2105 {
2106         int i, max_idx, max_agg_idx;
2107         struct pci_dev *pdev = bp->pdev;
2108
2109         if (!bp->rx_ring)
2110                 return;
2111
2112         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2113         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2114         for (i = 0; i < bp->rx_nr_rings; i++) {
2115                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2116                 int j;
2117
2118                 if (rxr->rx_tpa) {
2119                         for (j = 0; j < MAX_TPA; j++) {
2120                                 struct bnxt_tpa_info *tpa_info =
2121                                                         &rxr->rx_tpa[j];
2122                                 u8 *data = tpa_info->data;
2123
2124                                 if (!data)
2125                                         continue;
2126
2127                                 dma_unmap_single_attrs(&pdev->dev,
2128                                                        tpa_info->mapping,
2129                                                        bp->rx_buf_use_size,
2130                                                        bp->rx_dir,
2131                                                        DMA_ATTR_WEAK_ORDERING);
2132
2133                                 tpa_info->data = NULL;
2134
2135                                 kfree(data);
2136                         }
2137                 }
2138
2139                 for (j = 0; j < max_idx; j++) {
2140                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2141                         dma_addr_t mapping = rx_buf->mapping;
2142                         void *data = rx_buf->data;
2143
2144                         if (!data)
2145                                 continue;
2146
2147                         rx_buf->data = NULL;
2148
2149                         if (BNXT_RX_PAGE_MODE(bp)) {
2150                                 mapping -= bp->rx_dma_offset;
2151                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2152                                                      PAGE_SIZE, bp->rx_dir,
2153                                                      DMA_ATTR_WEAK_ORDERING);
2154                                 __free_page(data);
2155                         } else {
2156                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2157                                                        bp->rx_buf_use_size,
2158                                                        bp->rx_dir,
2159                                                        DMA_ATTR_WEAK_ORDERING);
2160                                 kfree(data);
2161                         }
2162                 }
2163
2164                 for (j = 0; j < max_agg_idx; j++) {
2165                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2166                                 &rxr->rx_agg_ring[j];
2167                         struct page *page = rx_agg_buf->page;
2168
2169                         if (!page)
2170                                 continue;
2171
2172                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2173                                              BNXT_RX_PAGE_SIZE,
2174                                              PCI_DMA_FROMDEVICE,
2175                                              DMA_ATTR_WEAK_ORDERING);
2176
2177                         rx_agg_buf->page = NULL;
2178                         __clear_bit(j, rxr->rx_agg_bmap);
2179
2180                         __free_page(page);
2181                 }
2182                 if (rxr->rx_page) {
2183                         __free_page(rxr->rx_page);
2184                         rxr->rx_page = NULL;
2185                 }
2186         }
2187 }
2188
2189 static void bnxt_free_skbs(struct bnxt *bp)
2190 {
2191         bnxt_free_tx_skbs(bp);
2192         bnxt_free_rx_skbs(bp);
2193 }
2194
2195 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2196 {
2197         struct pci_dev *pdev = bp->pdev;
2198         int i;
2199
2200         for (i = 0; i < ring->nr_pages; i++) {
2201                 if (!ring->pg_arr[i])
2202                         continue;
2203
2204                 dma_free_coherent(&pdev->dev, ring->page_size,
2205                                   ring->pg_arr[i], ring->dma_arr[i]);
2206
2207                 ring->pg_arr[i] = NULL;
2208         }
2209         if (ring->pg_tbl) {
2210                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2211                                   ring->pg_tbl, ring->pg_tbl_map);
2212                 ring->pg_tbl = NULL;
2213         }
2214         if (ring->vmem_size && *ring->vmem) {
2215                 vfree(*ring->vmem);
2216                 *ring->vmem = NULL;
2217         }
2218 }
2219
2220 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2221 {
2222         int i;
2223         struct pci_dev *pdev = bp->pdev;
2224
2225         if (ring->nr_pages > 1) {
2226                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2227                                                   ring->nr_pages * 8,
2228                                                   &ring->pg_tbl_map,
2229                                                   GFP_KERNEL);
2230                 if (!ring->pg_tbl)
2231                         return -ENOMEM;
2232         }
2233
2234         for (i = 0; i < ring->nr_pages; i++) {
2235                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2236                                                      ring->page_size,
2237                                                      &ring->dma_arr[i],
2238                                                      GFP_KERNEL);
2239                 if (!ring->pg_arr[i])
2240                         return -ENOMEM;
2241
2242                 if (ring->nr_pages > 1)
2243                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2244         }
2245
2246         if (ring->vmem_size) {
2247                 *ring->vmem = vzalloc(ring->vmem_size);
2248                 if (!(*ring->vmem))
2249                         return -ENOMEM;
2250         }
2251         return 0;
2252 }
2253
2254 static void bnxt_free_rx_rings(struct bnxt *bp)
2255 {
2256         int i;
2257
2258         if (!bp->rx_ring)
2259                 return;
2260
2261         for (i = 0; i < bp->rx_nr_rings; i++) {
2262                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2263                 struct bnxt_ring_struct *ring;
2264
2265                 if (rxr->xdp_prog)
2266                         bpf_prog_put(rxr->xdp_prog);
2267
2268                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2269                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2270
2271                 kfree(rxr->rx_tpa);
2272                 rxr->rx_tpa = NULL;
2273
2274                 kfree(rxr->rx_agg_bmap);
2275                 rxr->rx_agg_bmap = NULL;
2276
2277                 ring = &rxr->rx_ring_struct;
2278                 bnxt_free_ring(bp, ring);
2279
2280                 ring = &rxr->rx_agg_ring_struct;
2281                 bnxt_free_ring(bp, ring);
2282         }
2283 }
2284
2285 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2286 {
2287         int i, rc, agg_rings = 0, tpa_rings = 0;
2288
2289         if (!bp->rx_ring)
2290                 return -ENOMEM;
2291
2292         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2293                 agg_rings = 1;
2294
2295         if (bp->flags & BNXT_FLAG_TPA)
2296                 tpa_rings = 1;
2297
2298         for (i = 0; i < bp->rx_nr_rings; i++) {
2299                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2300                 struct bnxt_ring_struct *ring;
2301
2302                 ring = &rxr->rx_ring_struct;
2303
2304                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2305                 if (rc < 0)
2306                         return rc;
2307
2308                 rc = bnxt_alloc_ring(bp, ring);
2309                 if (rc)
2310                         return rc;
2311
2312                 if (agg_rings) {
2313                         u16 mem_size;
2314
2315                         ring = &rxr->rx_agg_ring_struct;
2316                         rc = bnxt_alloc_ring(bp, ring);
2317                         if (rc)
2318                                 return rc;
2319
2320                         ring->grp_idx = i;
2321                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2322                         mem_size = rxr->rx_agg_bmap_size / 8;
2323                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2324                         if (!rxr->rx_agg_bmap)
2325                                 return -ENOMEM;
2326
2327                         if (tpa_rings) {
2328                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2329                                                 sizeof(struct bnxt_tpa_info),
2330                                                 GFP_KERNEL);
2331                                 if (!rxr->rx_tpa)
2332                                         return -ENOMEM;
2333                         }
2334                 }
2335         }
2336         return 0;
2337 }
2338
2339 static void bnxt_free_tx_rings(struct bnxt *bp)
2340 {
2341         int i;
2342         struct pci_dev *pdev = bp->pdev;
2343
2344         if (!bp->tx_ring)
2345                 return;
2346
2347         for (i = 0; i < bp->tx_nr_rings; i++) {
2348                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2349                 struct bnxt_ring_struct *ring;
2350
2351                 if (txr->tx_push) {
2352                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2353                                           txr->tx_push, txr->tx_push_mapping);
2354                         txr->tx_push = NULL;
2355                 }
2356
2357                 ring = &txr->tx_ring_struct;
2358
2359                 bnxt_free_ring(bp, ring);
2360         }
2361 }
2362
2363 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2364 {
2365         int i, j, rc;
2366         struct pci_dev *pdev = bp->pdev;
2367
2368         bp->tx_push_size = 0;
2369         if (bp->tx_push_thresh) {
2370                 int push_size;
2371
2372                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2373                                         bp->tx_push_thresh);
2374
2375                 if (push_size > 256) {
2376                         push_size = 0;
2377                         bp->tx_push_thresh = 0;
2378                 }
2379
2380                 bp->tx_push_size = push_size;
2381         }
2382
2383         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2384                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2385                 struct bnxt_ring_struct *ring;
2386                 u8 qidx;
2387
2388                 ring = &txr->tx_ring_struct;
2389
2390                 rc = bnxt_alloc_ring(bp, ring);
2391                 if (rc)
2392                         return rc;
2393
2394                 ring->grp_idx = txr->bnapi->index;
2395                 if (bp->tx_push_size) {
2396                         dma_addr_t mapping;
2397
2398                         /* One pre-allocated DMA buffer to backup
2399                          * TX push operation
2400                          */
2401                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2402                                                 bp->tx_push_size,
2403                                                 &txr->tx_push_mapping,
2404                                                 GFP_KERNEL);
2405
2406                         if (!txr->tx_push)
2407                                 return -ENOMEM;
2408
2409                         mapping = txr->tx_push_mapping +
2410                                 sizeof(struct tx_push_bd);
2411                         txr->data_mapping = cpu_to_le64(mapping);
2412
2413                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2414                 }
2415                 qidx = bp->tc_to_qidx[j];
2416                 ring->queue_id = bp->q_info[qidx].queue_id;
2417                 if (i < bp->tx_nr_rings_xdp)
2418                         continue;
2419                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2420                         j++;
2421         }
2422         return 0;
2423 }
2424
2425 static void bnxt_free_cp_rings(struct bnxt *bp)
2426 {
2427         int i;
2428
2429         if (!bp->bnapi)
2430                 return;
2431
2432         for (i = 0; i < bp->cp_nr_rings; i++) {
2433                 struct bnxt_napi *bnapi = bp->bnapi[i];
2434                 struct bnxt_cp_ring_info *cpr;
2435                 struct bnxt_ring_struct *ring;
2436
2437                 if (!bnapi)
2438                         continue;
2439
2440                 cpr = &bnapi->cp_ring;
2441                 ring = &cpr->cp_ring_struct;
2442
2443                 bnxt_free_ring(bp, ring);
2444         }
2445 }
2446
2447 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2448 {
2449         int i, rc, ulp_base_vec, ulp_msix;
2450
2451         ulp_msix = bnxt_get_ulp_msix_num(bp);
2452         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2453         for (i = 0; i < bp->cp_nr_rings; i++) {
2454                 struct bnxt_napi *bnapi = bp->bnapi[i];
2455                 struct bnxt_cp_ring_info *cpr;
2456                 struct bnxt_ring_struct *ring;
2457
2458                 if (!bnapi)
2459                         continue;
2460
2461                 cpr = &bnapi->cp_ring;
2462                 ring = &cpr->cp_ring_struct;
2463
2464                 rc = bnxt_alloc_ring(bp, ring);
2465                 if (rc)
2466                         return rc;
2467
2468                 if (ulp_msix && i >= ulp_base_vec)
2469                         ring->map_idx = i + ulp_msix;
2470                 else
2471                         ring->map_idx = i;
2472         }
2473         return 0;
2474 }
2475
2476 static void bnxt_init_ring_struct(struct bnxt *bp)
2477 {
2478         int i;
2479
2480         for (i = 0; i < bp->cp_nr_rings; i++) {
2481                 struct bnxt_napi *bnapi = bp->bnapi[i];
2482                 struct bnxt_cp_ring_info *cpr;
2483                 struct bnxt_rx_ring_info *rxr;
2484                 struct bnxt_tx_ring_info *txr;
2485                 struct bnxt_ring_struct *ring;
2486
2487                 if (!bnapi)
2488                         continue;
2489
2490                 cpr = &bnapi->cp_ring;
2491                 ring = &cpr->cp_ring_struct;
2492                 ring->nr_pages = bp->cp_nr_pages;
2493                 ring->page_size = HW_CMPD_RING_SIZE;
2494                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2495                 ring->dma_arr = cpr->cp_desc_mapping;
2496                 ring->vmem_size = 0;
2497
2498                 rxr = bnapi->rx_ring;
2499                 if (!rxr)
2500                         goto skip_rx;
2501
2502                 ring = &rxr->rx_ring_struct;
2503                 ring->nr_pages = bp->rx_nr_pages;
2504                 ring->page_size = HW_RXBD_RING_SIZE;
2505                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2506                 ring->dma_arr = rxr->rx_desc_mapping;
2507                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2508                 ring->vmem = (void **)&rxr->rx_buf_ring;
2509
2510                 ring = &rxr->rx_agg_ring_struct;
2511                 ring->nr_pages = bp->rx_agg_nr_pages;
2512                 ring->page_size = HW_RXBD_RING_SIZE;
2513                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2514                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2515                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2516                 ring->vmem = (void **)&rxr->rx_agg_ring;
2517
2518 skip_rx:
2519                 txr = bnapi->tx_ring;
2520                 if (!txr)
2521                         continue;
2522
2523                 ring = &txr->tx_ring_struct;
2524                 ring->nr_pages = bp->tx_nr_pages;
2525                 ring->page_size = HW_RXBD_RING_SIZE;
2526                 ring->pg_arr = (void **)txr->tx_desc_ring;
2527                 ring->dma_arr = txr->tx_desc_mapping;
2528                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2529                 ring->vmem = (void **)&txr->tx_buf_ring;
2530         }
2531 }
2532
2533 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2534 {
2535         int i;
2536         u32 prod;
2537         struct rx_bd **rx_buf_ring;
2538
2539         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2540         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2541                 int j;
2542                 struct rx_bd *rxbd;
2543
2544                 rxbd = rx_buf_ring[i];
2545                 if (!rxbd)
2546                         continue;
2547
2548                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2549                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2550                         rxbd->rx_bd_opaque = prod;
2551                 }
2552         }
2553 }
2554
2555 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2556 {
2557         struct net_device *dev = bp->dev;
2558         struct bnxt_rx_ring_info *rxr;
2559         struct bnxt_ring_struct *ring;
2560         u32 prod, type;
2561         int i;
2562
2563         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2564                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2565
2566         if (NET_IP_ALIGN == 2)
2567                 type |= RX_BD_FLAGS_SOP;
2568
2569         rxr = &bp->rx_ring[ring_nr];
2570         ring = &rxr->rx_ring_struct;
2571         bnxt_init_rxbd_pages(ring, type);
2572
2573         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2574                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2575                 if (IS_ERR(rxr->xdp_prog)) {
2576                         int rc = PTR_ERR(rxr->xdp_prog);
2577
2578                         rxr->xdp_prog = NULL;
2579                         return rc;
2580                 }
2581         }
2582         prod = rxr->rx_prod;
2583         for (i = 0; i < bp->rx_ring_size; i++) {
2584                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2585                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2586                                     ring_nr, i, bp->rx_ring_size);
2587                         break;
2588                 }
2589                 prod = NEXT_RX(prod);
2590         }
2591         rxr->rx_prod = prod;
2592         ring->fw_ring_id = INVALID_HW_RING_ID;
2593
2594         ring = &rxr->rx_agg_ring_struct;
2595         ring->fw_ring_id = INVALID_HW_RING_ID;
2596
2597         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2598                 return 0;
2599
2600         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2601                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2602
2603         bnxt_init_rxbd_pages(ring, type);
2604
2605         prod = rxr->rx_agg_prod;
2606         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2607                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2608                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2609                                     ring_nr, i, bp->rx_ring_size);
2610                         break;
2611                 }
2612                 prod = NEXT_RX_AGG(prod);
2613         }
2614         rxr->rx_agg_prod = prod;
2615
2616         if (bp->flags & BNXT_FLAG_TPA) {
2617                 if (rxr->rx_tpa) {
2618                         u8 *data;
2619                         dma_addr_t mapping;
2620
2621                         for (i = 0; i < MAX_TPA; i++) {
2622                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2623                                                             GFP_KERNEL);
2624                                 if (!data)
2625                                         return -ENOMEM;
2626
2627                                 rxr->rx_tpa[i].data = data;
2628                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2629                                 rxr->rx_tpa[i].mapping = mapping;
2630                         }
2631                 } else {
2632                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2633                         return -ENOMEM;
2634                 }
2635         }
2636
2637         return 0;
2638 }
2639
2640 static void bnxt_init_cp_rings(struct bnxt *bp)
2641 {
2642         int i;
2643
2644         for (i = 0; i < bp->cp_nr_rings; i++) {
2645                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2646                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2647
2648                 ring->fw_ring_id = INVALID_HW_RING_ID;
2649                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2650                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2651         }
2652 }
2653
2654 static int bnxt_init_rx_rings(struct bnxt *bp)
2655 {
2656         int i, rc = 0;
2657
2658         if (BNXT_RX_PAGE_MODE(bp)) {
2659                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2660                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2661         } else {
2662                 bp->rx_offset = BNXT_RX_OFFSET;
2663                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2664         }
2665
2666         for (i = 0; i < bp->rx_nr_rings; i++) {
2667                 rc = bnxt_init_one_rx_ring(bp, i);
2668                 if (rc)
2669                         break;
2670         }
2671
2672         return rc;
2673 }
2674
2675 static int bnxt_init_tx_rings(struct bnxt *bp)
2676 {
2677         u16 i;
2678
2679         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2680                                    MAX_SKB_FRAGS + 1);
2681
2682         for (i = 0; i < bp->tx_nr_rings; i++) {
2683                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2684                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2685
2686                 ring->fw_ring_id = INVALID_HW_RING_ID;
2687         }
2688
2689         return 0;
2690 }
2691
2692 static void bnxt_free_ring_grps(struct bnxt *bp)
2693 {
2694         kfree(bp->grp_info);
2695         bp->grp_info = NULL;
2696 }
2697
2698 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2699 {
2700         int i;
2701
2702         if (irq_re_init) {
2703                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2704                                        sizeof(struct bnxt_ring_grp_info),
2705                                        GFP_KERNEL);
2706                 if (!bp->grp_info)
2707                         return -ENOMEM;
2708         }
2709         for (i = 0; i < bp->cp_nr_rings; i++) {
2710                 if (irq_re_init)
2711                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2712                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2713                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2714                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2715                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2716         }
2717         return 0;
2718 }
2719
2720 static void bnxt_free_vnics(struct bnxt *bp)
2721 {
2722         kfree(bp->vnic_info);
2723         bp->vnic_info = NULL;
2724         bp->nr_vnics = 0;
2725 }
2726
2727 static int bnxt_alloc_vnics(struct bnxt *bp)
2728 {
2729         int num_vnics = 1;
2730
2731 #ifdef CONFIG_RFS_ACCEL
2732         if (bp->flags & BNXT_FLAG_RFS)
2733                 num_vnics += bp->rx_nr_rings;
2734 #endif
2735
2736         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2737                 num_vnics++;
2738
2739         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2740                                 GFP_KERNEL);
2741         if (!bp->vnic_info)
2742                 return -ENOMEM;
2743
2744         bp->nr_vnics = num_vnics;
2745         return 0;
2746 }
2747
2748 static void bnxt_init_vnics(struct bnxt *bp)
2749 {
2750         int i;
2751
2752         for (i = 0; i < bp->nr_vnics; i++) {
2753                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2754
2755                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2756                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2757                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2758                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2759
2760                 if (bp->vnic_info[i].rss_hash_key) {
2761                         if (i == 0)
2762                                 prandom_bytes(vnic->rss_hash_key,
2763                                               HW_HASH_KEY_SIZE);
2764                         else
2765                                 memcpy(vnic->rss_hash_key,
2766                                        bp->vnic_info[0].rss_hash_key,
2767                                        HW_HASH_KEY_SIZE);
2768                 }
2769         }
2770 }
2771
2772 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2773 {
2774         int pages;
2775
2776         pages = ring_size / desc_per_pg;
2777
2778         if (!pages)
2779                 return 1;
2780
2781         pages++;
2782
2783         while (pages & (pages - 1))
2784                 pages++;
2785
2786         return pages;
2787 }
2788
2789 void bnxt_set_tpa_flags(struct bnxt *bp)
2790 {
2791         bp->flags &= ~BNXT_FLAG_TPA;
2792         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2793                 return;
2794         if (bp->dev->features & NETIF_F_LRO)
2795                 bp->flags |= BNXT_FLAG_LRO;
2796         else if (bp->dev->features & NETIF_F_GRO_HW)
2797                 bp->flags |= BNXT_FLAG_GRO;
2798 }
2799
2800 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2801  * be set on entry.
2802  */
2803 void bnxt_set_ring_params(struct bnxt *bp)
2804 {
2805         u32 ring_size, rx_size, rx_space;
2806         u32 agg_factor = 0, agg_ring_size = 0;
2807
2808         /* 8 for CRC and VLAN */
2809         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2810
2811         rx_space = rx_size + NET_SKB_PAD +
2812                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2813
2814         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2815         ring_size = bp->rx_ring_size;
2816         bp->rx_agg_ring_size = 0;
2817         bp->rx_agg_nr_pages = 0;
2818
2819         if (bp->flags & BNXT_FLAG_TPA)
2820                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2821
2822         bp->flags &= ~BNXT_FLAG_JUMBO;
2823         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2824                 u32 jumbo_factor;
2825
2826                 bp->flags |= BNXT_FLAG_JUMBO;
2827                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2828                 if (jumbo_factor > agg_factor)
2829                         agg_factor = jumbo_factor;
2830         }
2831         agg_ring_size = ring_size * agg_factor;
2832
2833         if (agg_ring_size) {
2834                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2835                                                         RX_DESC_CNT);
2836                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2837                         u32 tmp = agg_ring_size;
2838
2839                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2840                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2841                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2842                                     tmp, agg_ring_size);
2843                 }
2844                 bp->rx_agg_ring_size = agg_ring_size;
2845                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2846                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2847                 rx_space = rx_size + NET_SKB_PAD +
2848                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2849         }
2850
2851         bp->rx_buf_use_size = rx_size;
2852         bp->rx_buf_size = rx_space;
2853
2854         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2855         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2856
2857         ring_size = bp->tx_ring_size;
2858         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2859         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2860
2861         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2862         bp->cp_ring_size = ring_size;
2863
2864         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2865         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2866                 bp->cp_nr_pages = MAX_CP_PAGES;
2867                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2868                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2869                             ring_size, bp->cp_ring_size);
2870         }
2871         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2872         bp->cp_ring_mask = bp->cp_bit - 1;
2873 }
2874
2875 /* Changing allocation mode of RX rings.
2876  * TODO: Update when extending xdp_rxq_info to support allocation modes.
2877  */
2878 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2879 {
2880         if (page_mode) {
2881                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2882                         return -EOPNOTSUPP;
2883                 bp->dev->max_mtu =
2884                         min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
2885                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2886                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2887                 bp->rx_dir = DMA_BIDIRECTIONAL;
2888                 bp->rx_skb_func = bnxt_rx_page_skb;
2889                 /* Disable LRO or GRO_HW */
2890                 netdev_update_features(bp->dev);
2891         } else {
2892                 bp->dev->max_mtu = bp->max_mtu;
2893                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2894                 bp->rx_dir = DMA_FROM_DEVICE;
2895                 bp->rx_skb_func = bnxt_rx_skb;
2896         }
2897         return 0;
2898 }
2899
2900 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2901 {
2902         int i;
2903         struct bnxt_vnic_info *vnic;
2904         struct pci_dev *pdev = bp->pdev;
2905
2906         if (!bp->vnic_info)
2907                 return;
2908
2909         for (i = 0; i < bp->nr_vnics; i++) {
2910                 vnic = &bp->vnic_info[i];
2911
2912                 kfree(vnic->fw_grp_ids);
2913                 vnic->fw_grp_ids = NULL;
2914
2915                 kfree(vnic->uc_list);
2916                 vnic->uc_list = NULL;
2917
2918                 if (vnic->mc_list) {
2919                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2920                                           vnic->mc_list, vnic->mc_list_mapping);
2921                         vnic->mc_list = NULL;
2922                 }
2923
2924                 if (vnic->rss_table) {
2925                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2926                                           vnic->rss_table,
2927                                           vnic->rss_table_dma_addr);
2928                         vnic->rss_table = NULL;
2929                 }
2930
2931                 vnic->rss_hash_key = NULL;
2932                 vnic->flags = 0;
2933         }
2934 }
2935
2936 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2937 {
2938         int i, rc = 0, size;
2939         struct bnxt_vnic_info *vnic;
2940         struct pci_dev *pdev = bp->pdev;
2941         int max_rings;
2942
2943         for (i = 0; i < bp->nr_vnics; i++) {
2944                 vnic = &bp->vnic_info[i];
2945
2946                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2947                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2948
2949                         if (mem_size > 0) {
2950                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2951                                 if (!vnic->uc_list) {
2952                                         rc = -ENOMEM;
2953                                         goto out;
2954                                 }
2955                         }
2956                 }
2957
2958                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2959                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2960                         vnic->mc_list =
2961                                 dma_alloc_coherent(&pdev->dev,
2962                                                    vnic->mc_list_size,
2963                                                    &vnic->mc_list_mapping,
2964                                                    GFP_KERNEL);
2965                         if (!vnic->mc_list) {
2966                                 rc = -ENOMEM;
2967                                 goto out;
2968                         }
2969                 }
2970
2971                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2972                         max_rings = bp->rx_nr_rings;
2973                 else
2974                         max_rings = 1;
2975
2976                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2977                 if (!vnic->fw_grp_ids) {
2978                         rc = -ENOMEM;
2979                         goto out;
2980                 }
2981
2982                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2983                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2984                         continue;
2985
2986                 /* Allocate rss table and hash key */
2987                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2988                                                      &vnic->rss_table_dma_addr,
2989                                                      GFP_KERNEL);
2990                 if (!vnic->rss_table) {
2991                         rc = -ENOMEM;
2992                         goto out;
2993                 }
2994
2995                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2996
2997                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2998                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2999         }
3000         return 0;
3001
3002 out:
3003         return rc;
3004 }
3005
3006 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3007 {
3008         struct pci_dev *pdev = bp->pdev;
3009
3010         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3011                           bp->hwrm_cmd_resp_dma_addr);
3012
3013         bp->hwrm_cmd_resp_addr = NULL;
3014         if (bp->hwrm_dbg_resp_addr) {
3015                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
3016                                   bp->hwrm_dbg_resp_addr,
3017                                   bp->hwrm_dbg_resp_dma_addr);
3018
3019                 bp->hwrm_dbg_resp_addr = NULL;
3020         }
3021 }
3022
3023 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3024 {
3025         struct pci_dev *pdev = bp->pdev;
3026
3027         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3028                                                    &bp->hwrm_cmd_resp_dma_addr,
3029                                                    GFP_KERNEL);
3030         if (!bp->hwrm_cmd_resp_addr)
3031                 return -ENOMEM;
3032         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
3033                                                     HWRM_DBG_REG_BUF_SIZE,
3034                                                     &bp->hwrm_dbg_resp_dma_addr,
3035                                                     GFP_KERNEL);
3036         if (!bp->hwrm_dbg_resp_addr)
3037                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
3038
3039         return 0;
3040 }
3041
3042 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3043 {
3044         if (bp->hwrm_short_cmd_req_addr) {
3045                 struct pci_dev *pdev = bp->pdev;
3046
3047                 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3048                                   bp->hwrm_short_cmd_req_addr,
3049                                   bp->hwrm_short_cmd_req_dma_addr);
3050                 bp->hwrm_short_cmd_req_addr = NULL;
3051         }
3052 }
3053
3054 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3055 {
3056         struct pci_dev *pdev = bp->pdev;
3057
3058         bp->hwrm_short_cmd_req_addr =
3059                 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3060                                    &bp->hwrm_short_cmd_req_dma_addr,
3061                                    GFP_KERNEL);
3062         if (!bp->hwrm_short_cmd_req_addr)
3063                 return -ENOMEM;
3064
3065         return 0;
3066 }
3067
3068 static void bnxt_free_stats(struct bnxt *bp)
3069 {
3070         u32 size, i;
3071         struct pci_dev *pdev = bp->pdev;
3072
3073         bp->flags &= ~BNXT_FLAG_PORT_STATS;
3074         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3075
3076         if (bp->hw_rx_port_stats) {
3077                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3078                                   bp->hw_rx_port_stats,
3079                                   bp->hw_rx_port_stats_map);
3080                 bp->hw_rx_port_stats = NULL;
3081         }
3082
3083         if (bp->hw_rx_port_stats_ext) {
3084                 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3085                                   bp->hw_rx_port_stats_ext,
3086                                   bp->hw_rx_port_stats_ext_map);
3087                 bp->hw_rx_port_stats_ext = NULL;
3088         }
3089
3090         if (!bp->bnapi)
3091                 return;
3092
3093         size = sizeof(struct ctx_hw_stats);
3094
3095         for (i = 0; i < bp->cp_nr_rings; i++) {
3096                 struct bnxt_napi *bnapi = bp->bnapi[i];
3097                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3098
3099                 if (cpr->hw_stats) {
3100                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3101                                           cpr->hw_stats_map);
3102                         cpr->hw_stats = NULL;
3103                 }
3104         }
3105 }
3106
3107 static int bnxt_alloc_stats(struct bnxt *bp)
3108 {
3109         u32 size, i;
3110         struct pci_dev *pdev = bp->pdev;
3111
3112         size = sizeof(struct ctx_hw_stats);
3113
3114         for (i = 0; i < bp->cp_nr_rings; i++) {
3115                 struct bnxt_napi *bnapi = bp->bnapi[i];
3116                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3117
3118                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3119                                                    &cpr->hw_stats_map,
3120                                                    GFP_KERNEL);
3121                 if (!cpr->hw_stats)
3122                         return -ENOMEM;
3123
3124                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3125         }
3126
3127         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3128                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3129                                          sizeof(struct tx_port_stats) + 1024;
3130
3131                 bp->hw_rx_port_stats =
3132                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3133                                            &bp->hw_rx_port_stats_map,
3134                                            GFP_KERNEL);
3135                 if (!bp->hw_rx_port_stats)
3136                         return -ENOMEM;
3137
3138                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3139                                        512;
3140                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3141                                            sizeof(struct rx_port_stats) + 512;
3142                 bp->flags |= BNXT_FLAG_PORT_STATS;
3143
3144                 /* Display extended statistics only if FW supports it */
3145                 if (bp->hwrm_spec_code < 0x10804 ||
3146                     bp->hwrm_spec_code == 0x10900)
3147                         return 0;
3148
3149                 bp->hw_rx_port_stats_ext =
3150                         dma_zalloc_coherent(&pdev->dev,
3151                                             sizeof(struct rx_port_stats_ext),
3152                                             &bp->hw_rx_port_stats_ext_map,
3153                                             GFP_KERNEL);
3154                 if (!bp->hw_rx_port_stats_ext)
3155                         return 0;
3156
3157                 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3158         }
3159         return 0;
3160 }
3161
3162 static void bnxt_clear_ring_indices(struct bnxt *bp)
3163 {
3164         int i;
3165
3166         if (!bp->bnapi)
3167                 return;
3168
3169         for (i = 0; i < bp->cp_nr_rings; i++) {
3170                 struct bnxt_napi *bnapi = bp->bnapi[i];
3171                 struct bnxt_cp_ring_info *cpr;
3172                 struct bnxt_rx_ring_info *rxr;
3173                 struct bnxt_tx_ring_info *txr;
3174
3175                 if (!bnapi)
3176                         continue;
3177
3178                 cpr = &bnapi->cp_ring;
3179                 cpr->cp_raw_cons = 0;
3180
3181                 txr = bnapi->tx_ring;
3182                 if (txr) {
3183                         txr->tx_prod = 0;
3184                         txr->tx_cons = 0;
3185                 }
3186
3187                 rxr = bnapi->rx_ring;
3188                 if (rxr) {
3189                         rxr->rx_prod = 0;
3190                         rxr->rx_agg_prod = 0;
3191                         rxr->rx_sw_agg_prod = 0;
3192                         rxr->rx_next_cons = 0;
3193                 }
3194         }
3195 }
3196
3197 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3198 {
3199 #ifdef CONFIG_RFS_ACCEL
3200         int i;
3201
3202         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3203          * safe to delete the hash table.
3204          */
3205         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3206                 struct hlist_head *head;
3207                 struct hlist_node *tmp;
3208                 struct bnxt_ntuple_filter *fltr;
3209
3210                 head = &bp->ntp_fltr_hash_tbl[i];
3211                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3212                         hlist_del(&fltr->hash);
3213                         kfree(fltr);
3214                 }
3215         }
3216         if (irq_reinit) {
3217                 kfree(bp->ntp_fltr_bmap);
3218                 bp->ntp_fltr_bmap = NULL;
3219         }
3220         bp->ntp_fltr_count = 0;
3221 #endif
3222 }
3223
3224 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3225 {
3226 #ifdef CONFIG_RFS_ACCEL
3227         int i, rc = 0;
3228
3229         if (!(bp->flags & BNXT_FLAG_RFS))
3230                 return 0;
3231
3232         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3233                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3234
3235         bp->ntp_fltr_count = 0;
3236         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3237                                     sizeof(long),
3238                                     GFP_KERNEL);
3239
3240         if (!bp->ntp_fltr_bmap)
3241                 rc = -ENOMEM;
3242
3243         return rc;
3244 #else
3245         return 0;
3246 #endif
3247 }
3248
3249 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3250 {
3251         bnxt_free_vnic_attributes(bp);
3252         bnxt_free_tx_rings(bp);
3253         bnxt_free_rx_rings(bp);
3254         bnxt_free_cp_rings(bp);
3255         bnxt_free_ntp_fltrs(bp, irq_re_init);
3256         if (irq_re_init) {
3257                 bnxt_free_stats(bp);
3258                 bnxt_free_ring_grps(bp);
3259                 bnxt_free_vnics(bp);
3260                 kfree(bp->tx_ring_map);
3261                 bp->tx_ring_map = NULL;
3262                 kfree(bp->tx_ring);
3263                 bp->tx_ring = NULL;
3264                 kfree(bp->rx_ring);
3265                 bp->rx_ring = NULL;
3266                 kfree(bp->bnapi);
3267                 bp->bnapi = NULL;
3268         } else {
3269                 bnxt_clear_ring_indices(bp);
3270         }
3271 }
3272
3273 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3274 {
3275         int i, j, rc, size, arr_size;
3276         void *bnapi;
3277
3278         if (irq_re_init) {
3279                 /* Allocate bnapi mem pointer array and mem block for
3280                  * all queues
3281                  */
3282                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3283                                 bp->cp_nr_rings);
3284                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3285                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3286                 if (!bnapi)
3287                         return -ENOMEM;
3288
3289                 bp->bnapi = bnapi;
3290                 bnapi += arr_size;
3291                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3292                         bp->bnapi[i] = bnapi;
3293                         bp->bnapi[i]->index = i;
3294                         bp->bnapi[i]->bp = bp;
3295                 }
3296
3297                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3298                                       sizeof(struct bnxt_rx_ring_info),
3299                                       GFP_KERNEL);
3300                 if (!bp->rx_ring)
3301                         return -ENOMEM;
3302
3303                 for (i = 0; i < bp->rx_nr_rings; i++) {
3304                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3305                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3306                 }
3307
3308                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3309                                       sizeof(struct bnxt_tx_ring_info),
3310                                       GFP_KERNEL);
3311                 if (!bp->tx_ring)
3312                         return -ENOMEM;
3313
3314                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3315                                           GFP_KERNEL);
3316
3317                 if (!bp->tx_ring_map)
3318                         return -ENOMEM;
3319
3320                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3321                         j = 0;
3322                 else
3323                         j = bp->rx_nr_rings;
3324
3325                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3326                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3327                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3328                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3329                         if (i >= bp->tx_nr_rings_xdp) {
3330                                 bp->tx_ring[i].txq_index = i -
3331                                         bp->tx_nr_rings_xdp;
3332                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3333                         } else {
3334                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3335                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3336                         }
3337                 }
3338
3339                 rc = bnxt_alloc_stats(bp);
3340                 if (rc)
3341                         goto alloc_mem_err;
3342
3343                 rc = bnxt_alloc_ntp_fltrs(bp);
3344                 if (rc)
3345                         goto alloc_mem_err;
3346
3347                 rc = bnxt_alloc_vnics(bp);
3348                 if (rc)
3349                         goto alloc_mem_err;
3350         }
3351
3352         bnxt_init_ring_struct(bp);
3353
3354         rc = bnxt_alloc_rx_rings(bp);
3355         if (rc)
3356                 goto alloc_mem_err;
3357
3358         rc = bnxt_alloc_tx_rings(bp);
3359         if (rc)
3360                 goto alloc_mem_err;
3361
3362         rc = bnxt_alloc_cp_rings(bp);
3363         if (rc)
3364                 goto alloc_mem_err;
3365
3366         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3367                                   BNXT_VNIC_UCAST_FLAG;
3368         rc = bnxt_alloc_vnic_attributes(bp);
3369         if (rc)
3370                 goto alloc_mem_err;
3371         return 0;
3372
3373 alloc_mem_err:
3374         bnxt_free_mem(bp, true);
3375         return rc;
3376 }
3377
3378 static void bnxt_disable_int(struct bnxt *bp)
3379 {
3380         int i;
3381
3382         if (!bp->bnapi)
3383                 return;
3384
3385         for (i = 0; i < bp->cp_nr_rings; i++) {
3386                 struct bnxt_napi *bnapi = bp->bnapi[i];
3387                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3388                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3389
3390                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3391                         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3392         }
3393 }
3394
3395 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3396 {
3397         struct bnxt_napi *bnapi = bp->bnapi[n];
3398         struct bnxt_cp_ring_info *cpr;
3399
3400         cpr = &bnapi->cp_ring;
3401         return cpr->cp_ring_struct.map_idx;
3402 }
3403
3404 static void bnxt_disable_int_sync(struct bnxt *bp)
3405 {
3406         int i;
3407
3408         atomic_inc(&bp->intr_sem);
3409
3410         bnxt_disable_int(bp);
3411         for (i = 0; i < bp->cp_nr_rings; i++) {
3412                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3413
3414                 synchronize_irq(bp->irq_tbl[map_idx].vector);
3415         }
3416 }
3417
3418 static void bnxt_enable_int(struct bnxt *bp)
3419 {
3420         int i;
3421
3422         atomic_set(&bp->intr_sem, 0);
3423         for (i = 0; i < bp->cp_nr_rings; i++) {
3424                 struct bnxt_napi *bnapi = bp->bnapi[i];
3425                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3426
3427                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3428         }
3429 }
3430
3431 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3432                             u16 cmpl_ring, u16 target_id)
3433 {
3434         struct input *req = request;
3435
3436         req->req_type = cpu_to_le16(req_type);
3437         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3438         req->target_id = cpu_to_le16(target_id);
3439         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3440 }
3441
3442 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3443                                  int timeout, bool silent)
3444 {
3445         int i, intr_process, rc, tmo_count;
3446         struct input *req = msg;
3447         u32 *data = msg;
3448         __le32 *resp_len;
3449         u8 *valid;
3450         u16 cp_ring_id, len = 0;
3451         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3452         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3453         struct hwrm_short_input short_input = {0};
3454
3455         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3456         memset(resp, 0, PAGE_SIZE);
3457         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3458         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3459
3460         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3461                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3462
3463                 memcpy(short_cmd_req, req, msg_len);
3464                 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3465                                                    msg_len);
3466
3467                 short_input.req_type = req->req_type;
3468                 short_input.signature =
3469                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3470                 short_input.size = cpu_to_le16(msg_len);
3471                 short_input.req_addr =
3472                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3473
3474                 data = (u32 *)&short_input;
3475                 msg_len = sizeof(short_input);
3476
3477                 /* Sync memory write before updating doorbell */
3478                 wmb();
3479
3480                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3481         }
3482
3483         /* Write request msg to hwrm channel */
3484         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3485
3486         for (i = msg_len; i < max_req_len; i += 4)
3487                 writel(0, bp->bar0 + i);
3488
3489         /* currently supports only one outstanding message */
3490         if (intr_process)
3491                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3492
3493         /* Ring channel doorbell */
3494         writel(1, bp->bar0 + 0x100);
3495
3496         if (!timeout)
3497                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3498         /* convert timeout to usec */
3499         timeout *= 1000;
3500
3501         i = 0;
3502         /* Short timeout for the first few iterations:
3503          * number of loops = number of loops for short timeout +
3504          * number of loops for standard timeout.
3505          */
3506         tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3507         timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3508         tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3509         resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3510         if (intr_process) {
3511                 /* Wait until hwrm response cmpl interrupt is processed */
3512                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3513                        i++ < tmo_count) {
3514                         /* on first few passes, just barely sleep */
3515                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3516                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3517                                              HWRM_SHORT_MAX_TIMEOUT);
3518                         else
3519                                 usleep_range(HWRM_MIN_TIMEOUT,
3520                                              HWRM_MAX_TIMEOUT);
3521                 }
3522
3523                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3524                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3525                                    le16_to_cpu(req->req_type));
3526                         return -1;
3527                 }
3528                 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3529                       HWRM_RESP_LEN_SFT;
3530                 valid = bp->hwrm_cmd_resp_addr + len - 1;
3531         } else {
3532                 /* Check if response len is updated */
3533                 for (i = 0; i < tmo_count; i++) {
3534                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3535                               HWRM_RESP_LEN_SFT;
3536                         if (len)
3537                                 break;
3538                         /* on first few passes, just barely sleep */
3539                         if (i < DFLT_HWRM_CMD_TIMEOUT)
3540                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3541                                              HWRM_SHORT_MAX_TIMEOUT);
3542                         else
3543                                 usleep_range(HWRM_MIN_TIMEOUT,
3544                                              HWRM_MAX_TIMEOUT);
3545                 }
3546
3547                 if (i >= tmo_count) {
3548                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3549                                    timeout, le16_to_cpu(req->req_type),
3550                                    le16_to_cpu(req->seq_id), len);
3551                         return -1;
3552                 }
3553
3554                 /* Last byte of resp contains valid bit */
3555                 valid = bp->hwrm_cmd_resp_addr + len - 1;
3556                 for (i = 0; i < 5; i++) {
3557                         /* make sure we read from updated DMA memory */
3558                         dma_rmb();
3559                         if (*valid)
3560                                 break;
3561                         udelay(1);
3562                 }
3563
3564                 if (i >= 5) {
3565                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3566                                    timeout, le16_to_cpu(req->req_type),
3567                                    le16_to_cpu(req->seq_id), len, *valid);
3568                         return -1;
3569                 }
3570         }
3571
3572         /* Zero valid bit for compatibility.  Valid bit in an older spec
3573          * may become a new field in a newer spec.  We must make sure that
3574          * a new field not implemented by old spec will read zero.
3575          */
3576         *valid = 0;
3577         rc = le16_to_cpu(resp->error_code);
3578         if (rc && !silent)
3579                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3580                            le16_to_cpu(resp->req_type),
3581                            le16_to_cpu(resp->seq_id), rc);
3582         return rc;
3583 }
3584
3585 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3586 {
3587         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3588 }
3589
3590 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3591                               int timeout)
3592 {
3593         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3594 }
3595
3596 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3597 {
3598         int rc;
3599
3600         mutex_lock(&bp->hwrm_cmd_lock);
3601         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3602         mutex_unlock(&bp->hwrm_cmd_lock);
3603         return rc;
3604 }
3605
3606 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3607                              int timeout)
3608 {
3609         int rc;
3610
3611         mutex_lock(&bp->hwrm_cmd_lock);
3612         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3613         mutex_unlock(&bp->hwrm_cmd_lock);
3614         return rc;
3615 }
3616
3617 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3618                                      int bmap_size)
3619 {
3620         struct hwrm_func_drv_rgtr_input req = {0};
3621         DECLARE_BITMAP(async_events_bmap, 256);
3622         u32 *events = (u32 *)async_events_bmap;
3623         int i;
3624
3625         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3626
3627         req.enables =
3628                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3629
3630         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3631         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3632                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3633
3634         if (bmap && bmap_size) {
3635                 for (i = 0; i < bmap_size; i++) {
3636                         if (test_bit(i, bmap))
3637                                 __set_bit(i, async_events_bmap);
3638                 }
3639         }
3640
3641         for (i = 0; i < 8; i++)
3642                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3643
3644         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3645 }
3646
3647 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3648 {
3649         struct hwrm_func_drv_rgtr_input req = {0};
3650
3651         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3652
3653         req.enables =
3654                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3655                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3656
3657         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3658         req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
3659         req.ver_maj_8b = DRV_VER_MAJ;
3660         req.ver_min_8b = DRV_VER_MIN;
3661         req.ver_upd_8b = DRV_VER_UPD;
3662         req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
3663         req.ver_min = cpu_to_le16(DRV_VER_MIN);
3664         req.ver_upd = cpu_to_le16(DRV_VER_UPD);
3665
3666         if (BNXT_PF(bp)) {
3667                 u32 data[8];
3668                 int i;
3669
3670                 memset(data, 0, sizeof(data));
3671                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3672                         u16 cmd = bnxt_vf_req_snif[i];
3673                         unsigned int bit, idx;
3674
3675                         idx = cmd / 32;
3676                         bit = cmd % 32;
3677                         data[idx] |= 1 << bit;
3678                 }
3679
3680                 for (i = 0; i < 8; i++)
3681                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3682
3683                 req.enables |=
3684                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3685         }
3686
3687         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3688 }
3689
3690 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3691 {
3692         struct hwrm_func_drv_unrgtr_input req = {0};
3693
3694         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3695         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3696 }
3697
3698 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3699 {
3700         u32 rc = 0;
3701         struct hwrm_tunnel_dst_port_free_input req = {0};
3702
3703         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3704         req.tunnel_type = tunnel_type;
3705
3706         switch (tunnel_type) {
3707         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3708                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3709                 break;
3710         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3711                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3712                 break;
3713         default:
3714                 break;
3715         }
3716
3717         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3718         if (rc)
3719                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3720                            rc);
3721         return rc;
3722 }
3723
3724 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3725                                            u8 tunnel_type)
3726 {
3727         u32 rc = 0;
3728         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3729         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3730
3731         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3732
3733         req.tunnel_type = tunnel_type;
3734         req.tunnel_dst_port_val = port;
3735
3736         mutex_lock(&bp->hwrm_cmd_lock);
3737         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3738         if (rc) {
3739                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3740                            rc);
3741                 goto err_out;
3742         }
3743
3744         switch (tunnel_type) {
3745         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3746                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3747                 break;
3748         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3749                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3750                 break;
3751         default:
3752                 break;
3753         }
3754
3755 err_out:
3756         mutex_unlock(&bp->hwrm_cmd_lock);
3757         return rc;
3758 }
3759
3760 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3761 {
3762         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3763         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3764
3765         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3766         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3767
3768         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3769         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3770         req.mask = cpu_to_le32(vnic->rx_mask);
3771         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3772 }
3773
3774 #ifdef CONFIG_RFS_ACCEL
3775 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3776                                             struct bnxt_ntuple_filter *fltr)
3777 {
3778         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3779
3780         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3781         req.ntuple_filter_id = fltr->filter_id;
3782         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3783 }
3784
3785 #define BNXT_NTP_FLTR_FLAGS                                     \
3786         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3787          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3788          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3789          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3790          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3791          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3792          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3793          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3794          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3795          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3796          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3797          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3798          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3799          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3800
3801 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
3802                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3803
3804 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3805                                              struct bnxt_ntuple_filter *fltr)
3806 {
3807         int rc = 0;
3808         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3809         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3810                 bp->hwrm_cmd_resp_addr;
3811         struct flow_keys *keys = &fltr->fkeys;
3812         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3813
3814         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3815         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3816
3817         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3818
3819         req.ethertype = htons(ETH_P_IP);
3820         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3821         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3822         req.ip_protocol = keys->basic.ip_proto;
3823
3824         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3825                 int i;
3826
3827                 req.ethertype = htons(ETH_P_IPV6);
3828                 req.ip_addr_type =
3829                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3830                 *(struct in6_addr *)&req.src_ipaddr[0] =
3831                         keys->addrs.v6addrs.src;
3832                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3833                         keys->addrs.v6addrs.dst;
3834                 for (i = 0; i < 4; i++) {
3835                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3836                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3837                 }
3838         } else {
3839                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3840                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3841                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3842                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3843         }
3844         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3845                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3846                 req.tunnel_type =
3847                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3848         }
3849
3850         req.src_port = keys->ports.src;
3851         req.src_port_mask = cpu_to_be16(0xffff);
3852         req.dst_port = keys->ports.dst;
3853         req.dst_port_mask = cpu_to_be16(0xffff);
3854
3855         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3856         mutex_lock(&bp->hwrm_cmd_lock);
3857         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3858         if (!rc)
3859                 fltr->filter_id = resp->ntuple_filter_id;
3860         mutex_unlock(&bp->hwrm_cmd_lock);
3861         return rc;
3862 }
3863 #endif
3864
3865 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3866                                      u8 *mac_addr)
3867 {
3868         u32 rc = 0;
3869         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3870         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3871
3872         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3873         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3874         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3875                 req.flags |=
3876                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3877         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3878         req.enables =
3879                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3880                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3881                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3882         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3883         req.l2_addr_mask[0] = 0xff;
3884         req.l2_addr_mask[1] = 0xff;
3885         req.l2_addr_mask[2] = 0xff;
3886         req.l2_addr_mask[3] = 0xff;
3887         req.l2_addr_mask[4] = 0xff;
3888         req.l2_addr_mask[5] = 0xff;
3889
3890         mutex_lock(&bp->hwrm_cmd_lock);
3891         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3892         if (!rc)
3893                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3894                                                         resp->l2_filter_id;
3895         mutex_unlock(&bp->hwrm_cmd_lock);
3896         return rc;
3897 }
3898
3899 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3900 {
3901         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3902         int rc = 0;
3903
3904         /* Any associated ntuple filters will also be cleared by firmware. */
3905         mutex_lock(&bp->hwrm_cmd_lock);
3906         for (i = 0; i < num_of_vnics; i++) {
3907                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3908
3909                 for (j = 0; j < vnic->uc_filter_count; j++) {
3910                         struct hwrm_cfa_l2_filter_free_input req = {0};
3911
3912                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3913                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3914
3915                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3916
3917                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3918                                                 HWRM_CMD_TIMEOUT);
3919                 }
3920                 vnic->uc_filter_count = 0;
3921         }
3922         mutex_unlock(&bp->hwrm_cmd_lock);
3923
3924         return rc;
3925 }
3926
3927 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3928 {
3929         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3930         struct hwrm_vnic_tpa_cfg_input req = {0};
3931
3932         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
3933                 return 0;
3934
3935         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3936
3937         if (tpa_flags) {
3938                 u16 mss = bp->dev->mtu - 40;
3939                 u32 nsegs, n, segs = 0, flags;
3940
3941                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3942                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3943                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3944                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3945                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3946                 if (tpa_flags & BNXT_FLAG_GRO)
3947                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3948
3949                 req.flags = cpu_to_le32(flags);
3950
3951                 req.enables =
3952                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3953                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3954                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3955
3956                 /* Number of segs are log2 units, and first packet is not
3957                  * included as part of this units.
3958                  */
3959                 if (mss <= BNXT_RX_PAGE_SIZE) {
3960                         n = BNXT_RX_PAGE_SIZE / mss;
3961                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3962                 } else {
3963                         n = mss / BNXT_RX_PAGE_SIZE;
3964                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3965                                 n++;
3966                         nsegs = (MAX_SKB_FRAGS - n) / n;
3967                 }
3968
3969                 segs = ilog2(nsegs);
3970                 req.max_agg_segs = cpu_to_le16(segs);
3971                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3972
3973                 req.min_agg_len = cpu_to_le32(512);
3974         }
3975         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3976
3977         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3978 }
3979
3980 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3981 {
3982         u32 i, j, max_rings;
3983         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3984         struct hwrm_vnic_rss_cfg_input req = {0};
3985
3986         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3987                 return 0;
3988
3989         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3990         if (set_rss) {
3991                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3992                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3993                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3994                                 max_rings = bp->rx_nr_rings - 1;
3995                         else
3996                                 max_rings = bp->rx_nr_rings;
3997                 } else {
3998                         max_rings = 1;
3999                 }
4000
4001                 /* Fill the RSS indirection table with ring group ids */
4002                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4003                         if (j == max_rings)
4004                                 j = 0;
4005                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4006                 }
4007
4008                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4009                 req.hash_key_tbl_addr =
4010                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
4011         }
4012         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4013         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4014 }
4015
4016 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4017 {
4018         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4019         struct hwrm_vnic_plcmodes_cfg_input req = {0};
4020
4021         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4022         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4023                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4024                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4025         req.enables =
4026                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4027                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4028         /* thresholds not implemented in firmware yet */
4029         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4030         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4031         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4032         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4033 }
4034
4035 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4036                                         u16 ctx_idx)
4037 {
4038         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4039
4040         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4041         req.rss_cos_lb_ctx_id =
4042                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4043
4044         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4045         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4046 }
4047
4048 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4049 {
4050         int i, j;
4051
4052         for (i = 0; i < bp->nr_vnics; i++) {
4053                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4054
4055                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4056                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4057                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4058                 }
4059         }
4060         bp->rsscos_nr_ctxs = 0;
4061 }
4062
4063 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4064 {
4065         int rc;
4066         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4067         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4068                                                 bp->hwrm_cmd_resp_addr;
4069
4070         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4071                                -1);
4072
4073         mutex_lock(&bp->hwrm_cmd_lock);
4074         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4075         if (!rc)
4076                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4077                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
4078         mutex_unlock(&bp->hwrm_cmd_lock);
4079
4080         return rc;
4081 }
4082
4083 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4084 {
4085         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4086                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4087         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4088 }
4089
4090 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4091 {
4092         unsigned int ring = 0, grp_idx;
4093         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4094         struct hwrm_vnic_cfg_input req = {0};
4095         u16 def_vlan = 0;
4096
4097         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4098
4099         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4100         /* Only RSS support for now TBD: COS & LB */
4101         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4102                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4103                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4104                                            VNIC_CFG_REQ_ENABLES_MRU);
4105         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4106                 req.rss_rule =
4107                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4108                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4109                                            VNIC_CFG_REQ_ENABLES_MRU);
4110                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4111         } else {
4112                 req.rss_rule = cpu_to_le16(0xffff);
4113         }
4114
4115         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4116             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4117                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4118                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4119         } else {
4120                 req.cos_rule = cpu_to_le16(0xffff);
4121         }
4122
4123         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4124                 ring = 0;
4125         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4126                 ring = vnic_id - 1;
4127         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4128                 ring = bp->rx_nr_rings - 1;
4129
4130         grp_idx = bp->rx_ring[ring].bnapi->index;
4131         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4132         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4133
4134         req.lb_rule = cpu_to_le16(0xffff);
4135         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4136                               VLAN_HLEN);
4137
4138 #ifdef CONFIG_BNXT_SRIOV
4139         if (BNXT_VF(bp))
4140                 def_vlan = bp->vf.vlan;
4141 #endif
4142         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4143                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4144         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4145                 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4146
4147         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4148 }
4149
4150 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4151 {
4152         u32 rc = 0;
4153
4154         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4155                 struct hwrm_vnic_free_input req = {0};
4156
4157                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4158                 req.vnic_id =
4159                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4160
4161                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4162                 if (rc)
4163                         return rc;
4164                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4165         }
4166         return rc;
4167 }
4168
4169 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4170 {
4171         u16 i;
4172
4173         for (i = 0; i < bp->nr_vnics; i++)
4174                 bnxt_hwrm_vnic_free_one(bp, i);
4175 }
4176
4177 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4178                                 unsigned int start_rx_ring_idx,
4179                                 unsigned int nr_rings)
4180 {
4181         int rc = 0;
4182         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4183         struct hwrm_vnic_alloc_input req = {0};
4184         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4185
4186         /* map ring groups to this vnic */
4187         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4188                 grp_idx = bp->rx_ring[i].bnapi->index;
4189                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4190                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4191                                    j, nr_rings);
4192                         break;
4193                 }
4194                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4195                                         bp->grp_info[grp_idx].fw_grp_id;
4196         }
4197
4198         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4199         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4200         if (vnic_id == 0)
4201                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4202
4203         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4204
4205         mutex_lock(&bp->hwrm_cmd_lock);
4206         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4207         if (!rc)
4208                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4209         mutex_unlock(&bp->hwrm_cmd_lock);
4210         return rc;
4211 }
4212
4213 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4214 {
4215         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4216         struct hwrm_vnic_qcaps_input req = {0};
4217         int rc;
4218
4219         if (bp->hwrm_spec_code < 0x10600)
4220                 return 0;
4221
4222         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4223         mutex_lock(&bp->hwrm_cmd_lock);
4224         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4225         if (!rc) {
4226                 u32 flags = le32_to_cpu(resp->flags);
4227
4228                 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)
4229                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4230                 if (flags &
4231                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4232                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4233         }
4234         mutex_unlock(&bp->hwrm_cmd_lock);
4235         return rc;
4236 }
4237
4238 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4239 {
4240         u16 i;
4241         u32 rc = 0;
4242
4243         mutex_lock(&bp->hwrm_cmd_lock);
4244         for (i = 0; i < bp->rx_nr_rings; i++) {
4245                 struct hwrm_ring_grp_alloc_input req = {0};
4246                 struct hwrm_ring_grp_alloc_output *resp =
4247                                         bp->hwrm_cmd_resp_addr;
4248                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4249
4250                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4251
4252                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4253                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4254                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4255                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4256
4257                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4258                                         HWRM_CMD_TIMEOUT);
4259                 if (rc)
4260                         break;
4261
4262                 bp->grp_info[grp_idx].fw_grp_id =
4263                         le32_to_cpu(resp->ring_group_id);
4264         }
4265         mutex_unlock(&bp->hwrm_cmd_lock);
4266         return rc;
4267 }
4268
4269 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4270 {
4271         u16 i;
4272         u32 rc = 0;
4273         struct hwrm_ring_grp_free_input req = {0};
4274
4275         if (!bp->grp_info)
4276                 return 0;
4277
4278         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4279
4280         mutex_lock(&bp->hwrm_cmd_lock);
4281         for (i = 0; i < bp->cp_nr_rings; i++) {
4282                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4283                         continue;
4284                 req.ring_group_id =
4285                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4286
4287                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4288                                         HWRM_CMD_TIMEOUT);
4289                 if (rc)
4290                         break;
4291                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4292         }
4293         mutex_unlock(&bp->hwrm_cmd_lock);
4294         return rc;
4295 }
4296
4297 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4298                                     struct bnxt_ring_struct *ring,
4299                                     u32 ring_type, u32 map_index)
4300 {
4301         int rc = 0, err = 0;
4302         struct hwrm_ring_alloc_input req = {0};
4303         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4304         struct bnxt_ring_grp_info *grp_info;
4305         u16 ring_id;
4306
4307         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4308
4309         req.enables = 0;
4310         if (ring->nr_pages > 1) {
4311                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4312                 /* Page size is in log2 units */
4313                 req.page_size = BNXT_PAGE_SHIFT;
4314                 req.page_tbl_depth = 1;
4315         } else {
4316                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
4317         }
4318         req.fbo = 0;
4319         /* Association of ring index with doorbell index and MSIX number */
4320         req.logical_id = cpu_to_le16(map_index);
4321
4322         switch (ring_type) {
4323         case HWRM_RING_ALLOC_TX:
4324                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4325                 /* Association of transmit ring with completion ring */
4326                 grp_info = &bp->grp_info[ring->grp_idx];
4327                 req.cmpl_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4328                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4329                 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4330                 req.queue_id = cpu_to_le16(ring->queue_id);
4331                 break;
4332         case HWRM_RING_ALLOC_RX:
4333                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4334                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4335                 break;
4336         case HWRM_RING_ALLOC_AGG:
4337                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4338                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4339                 break;
4340         case HWRM_RING_ALLOC_CMPL:
4341                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4342                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4343                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4344                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4345                 break;
4346         default:
4347                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4348                            ring_type);
4349                 return -1;
4350         }
4351
4352         mutex_lock(&bp->hwrm_cmd_lock);
4353         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4354         err = le16_to_cpu(resp->error_code);
4355         ring_id = le16_to_cpu(resp->ring_id);
4356         mutex_unlock(&bp->hwrm_cmd_lock);
4357
4358         if (rc || err) {
4359                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4360                            ring_type, rc, err);
4361                 return -EIO;
4362         }
4363         ring->fw_ring_id = ring_id;
4364         return rc;
4365 }
4366
4367 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4368 {
4369         int rc;
4370
4371         if (BNXT_PF(bp)) {
4372                 struct hwrm_func_cfg_input req = {0};
4373
4374                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4375                 req.fid = cpu_to_le16(0xffff);
4376                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4377                 req.async_event_cr = cpu_to_le16(idx);
4378                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4379         } else {
4380                 struct hwrm_func_vf_cfg_input req = {0};
4381
4382                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4383                 req.enables =
4384                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4385                 req.async_event_cr = cpu_to_le16(idx);
4386                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4387         }
4388         return rc;
4389 }
4390
4391 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4392 {
4393         int i, rc = 0;
4394
4395         for (i = 0; i < bp->cp_nr_rings; i++) {
4396                 struct bnxt_napi *bnapi = bp->bnapi[i];
4397                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4398                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4399                 u32 map_idx = ring->map_idx;
4400
4401                 cpr->cp_doorbell = bp->bar1 + map_idx * 0x80;
4402                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL,
4403                                               map_idx);
4404                 if (rc)
4405                         goto err_out;
4406                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4407                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4408
4409                 if (!i) {
4410                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4411                         if (rc)
4412                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4413                 }
4414         }
4415
4416         for (i = 0; i < bp->tx_nr_rings; i++) {
4417                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4418                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4419                 u32 map_idx = i;
4420
4421                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4422                                               map_idx);
4423                 if (rc)
4424                         goto err_out;
4425                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4426         }
4427
4428         for (i = 0; i < bp->rx_nr_rings; i++) {
4429                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4430                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4431                 u32 map_idx = rxr->bnapi->index;
4432
4433                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4434                                               map_idx);
4435                 if (rc)
4436                         goto err_out;
4437                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4438                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4439                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4440         }
4441
4442         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4443                 for (i = 0; i < bp->rx_nr_rings; i++) {
4444                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4445                         struct bnxt_ring_struct *ring =
4446                                                 &rxr->rx_agg_ring_struct;
4447                         u32 grp_idx = ring->grp_idx;
4448                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4449
4450                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4451                                                       HWRM_RING_ALLOC_AGG,
4452                                                       map_idx);
4453                         if (rc)
4454                                 goto err_out;
4455
4456                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4457                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4458                                rxr->rx_agg_doorbell);
4459                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4460                 }
4461         }
4462 err_out:
4463         return rc;
4464 }
4465
4466 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4467                                    struct bnxt_ring_struct *ring,
4468                                    u32 ring_type, int cmpl_ring_id)
4469 {
4470         int rc;
4471         struct hwrm_ring_free_input req = {0};
4472         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4473         u16 error_code;
4474
4475         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4476         req.ring_type = ring_type;
4477         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4478
4479         mutex_lock(&bp->hwrm_cmd_lock);
4480         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4481         error_code = le16_to_cpu(resp->error_code);
4482         mutex_unlock(&bp->hwrm_cmd_lock);
4483
4484         if (rc || error_code) {
4485                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
4486                            ring_type, rc, error_code);
4487                 return -EIO;
4488         }
4489         return 0;
4490 }
4491
4492 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4493 {
4494         int i;
4495
4496         if (!bp->bnapi)
4497                 return;
4498
4499         for (i = 0; i < bp->tx_nr_rings; i++) {
4500                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4501                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4502                 u32 grp_idx = txr->bnapi->index;
4503                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4504
4505                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4506                         hwrm_ring_free_send_msg(bp, ring,
4507                                                 RING_FREE_REQ_RING_TYPE_TX,
4508                                                 close_path ? cmpl_ring_id :
4509                                                 INVALID_HW_RING_ID);
4510                         ring->fw_ring_id = INVALID_HW_RING_ID;
4511                 }
4512         }
4513
4514         for (i = 0; i < bp->rx_nr_rings; i++) {
4515                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4516                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4517                 u32 grp_idx = rxr->bnapi->index;
4518                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4519
4520                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4521                         hwrm_ring_free_send_msg(bp, ring,
4522                                                 RING_FREE_REQ_RING_TYPE_RX,
4523                                                 close_path ? cmpl_ring_id :
4524                                                 INVALID_HW_RING_ID);
4525                         ring->fw_ring_id = INVALID_HW_RING_ID;
4526                         bp->grp_info[grp_idx].rx_fw_ring_id =
4527                                 INVALID_HW_RING_ID;
4528                 }
4529         }
4530
4531         for (i = 0; i < bp->rx_nr_rings; i++) {
4532                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4533                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4534                 u32 grp_idx = rxr->bnapi->index;
4535                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4536
4537                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4538                         hwrm_ring_free_send_msg(bp, ring,
4539                                                 RING_FREE_REQ_RING_TYPE_RX,
4540                                                 close_path ? cmpl_ring_id :
4541                                                 INVALID_HW_RING_ID);
4542                         ring->fw_ring_id = INVALID_HW_RING_ID;
4543                         bp->grp_info[grp_idx].agg_fw_ring_id =
4544                                 INVALID_HW_RING_ID;
4545                 }
4546         }
4547
4548         /* The completion rings are about to be freed.  After that the
4549          * IRQ doorbell will not work anymore.  So we need to disable
4550          * IRQ here.
4551          */
4552         bnxt_disable_int_sync(bp);
4553
4554         for (i = 0; i < bp->cp_nr_rings; i++) {
4555                 struct bnxt_napi *bnapi = bp->bnapi[i];
4556                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4557                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4558
4559                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4560                         hwrm_ring_free_send_msg(bp, ring,
4561                                                 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4562                                                 INVALID_HW_RING_ID);
4563                         ring->fw_ring_id = INVALID_HW_RING_ID;
4564                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4565                 }
4566         }
4567 }
4568
4569 static int bnxt_hwrm_get_rings(struct bnxt *bp)
4570 {
4571         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4572         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4573         struct hwrm_func_qcfg_input req = {0};
4574         int rc;
4575
4576         if (bp->hwrm_spec_code < 0x10601)
4577                 return 0;
4578
4579         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4580         req.fid = cpu_to_le16(0xffff);
4581         mutex_lock(&bp->hwrm_cmd_lock);
4582         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4583         if (rc) {
4584                 mutex_unlock(&bp->hwrm_cmd_lock);
4585                 return -EIO;
4586         }
4587
4588         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4589         if (bp->flags & BNXT_FLAG_NEW_RM) {
4590                 u16 cp, stats;
4591
4592                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
4593                 hw_resc->resv_hw_ring_grps =
4594                         le32_to_cpu(resp->alloc_hw_ring_grps);
4595                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
4596                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
4597                 stats = le16_to_cpu(resp->alloc_stat_ctx);
4598                 cp = min_t(u16, cp, stats);
4599                 hw_resc->resv_cp_rings = cp;
4600         }
4601         mutex_unlock(&bp->hwrm_cmd_lock);
4602         return 0;
4603 }
4604
4605 /* Caller must hold bp->hwrm_cmd_lock */
4606 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4607 {
4608         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4609         struct hwrm_func_qcfg_input req = {0};
4610         int rc;
4611
4612         if (bp->hwrm_spec_code < 0x10601)
4613                 return 0;
4614
4615         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4616         req.fid = cpu_to_le16(fid);
4617         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4618         if (!rc)
4619                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4620
4621         return rc;
4622 }
4623
4624 static void
4625 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
4626                              int tx_rings, int rx_rings, int ring_grps,
4627                              int cp_rings, int vnics)
4628 {
4629         u32 enables = 0;
4630
4631         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
4632         req->fid = cpu_to_le16(0xffff);
4633         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4634         req->num_tx_rings = cpu_to_le16(tx_rings);
4635         if (bp->flags & BNXT_FLAG_NEW_RM) {
4636                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4637                 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4638                                       FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4639                 enables |= ring_grps ?
4640                            FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4641                 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4642
4643                 req->num_rx_rings = cpu_to_le16(rx_rings);
4644                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4645                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4646                 req->num_stat_ctxs = req->num_cmpl_rings;
4647                 req->num_vnics = cpu_to_le16(vnics);
4648         }
4649         req->enables = cpu_to_le32(enables);
4650 }
4651
4652 static void
4653 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
4654                              struct hwrm_func_vf_cfg_input *req, int tx_rings,
4655                              int rx_rings, int ring_grps, int cp_rings,
4656                              int vnics)
4657 {
4658         u32 enables = 0;
4659
4660         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
4661         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4662         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4663         enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4664                               FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4665         enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4666         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4667
4668         req->num_tx_rings = cpu_to_le16(tx_rings);
4669         req->num_rx_rings = cpu_to_le16(rx_rings);
4670         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4671         req->num_cmpl_rings = cpu_to_le16(cp_rings);
4672         req->num_stat_ctxs = req->num_cmpl_rings;
4673         req->num_vnics = cpu_to_le16(vnics);
4674
4675         req->enables = cpu_to_le32(enables);
4676 }
4677
4678 static int
4679 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4680                            int ring_grps, int cp_rings, int vnics)
4681 {
4682         struct hwrm_func_cfg_input req = {0};
4683         int rc;
4684
4685         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4686                                      cp_rings, vnics);
4687         if (!req.enables)
4688                 return 0;
4689
4690         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4691         if (rc)
4692                 return -ENOMEM;
4693
4694         if (bp->hwrm_spec_code < 0x10601)
4695                 bp->hw_resc.resv_tx_rings = tx_rings;
4696
4697         rc = bnxt_hwrm_get_rings(bp);
4698         return rc;
4699 }
4700
4701 static int
4702 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4703                            int ring_grps, int cp_rings, int vnics)
4704 {
4705         struct hwrm_func_vf_cfg_input req = {0};
4706         int rc;
4707
4708         if (!(bp->flags & BNXT_FLAG_NEW_RM)) {
4709                 bp->hw_resc.resv_tx_rings = tx_rings;
4710                 return 0;
4711         }
4712
4713         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4714                                      cp_rings, vnics);
4715         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4716         if (rc)
4717                 return -ENOMEM;
4718
4719         rc = bnxt_hwrm_get_rings(bp);
4720         return rc;
4721 }
4722
4723 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
4724                                    int cp, int vnic)
4725 {
4726         if (BNXT_PF(bp))
4727                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
4728         else
4729                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
4730 }
4731
4732 static int bnxt_cp_rings_in_use(struct bnxt *bp)
4733 {
4734         int cp = bp->cp_nr_rings;
4735         int ulp_msix, ulp_base;
4736
4737         ulp_msix = bnxt_get_ulp_msix_num(bp);
4738         if (ulp_msix) {
4739                 ulp_base = bnxt_get_ulp_msix_base(bp);
4740                 cp += ulp_msix;
4741                 if ((ulp_base + ulp_msix) > cp)
4742                         cp = ulp_base + ulp_msix;
4743         }
4744         return cp;
4745 }
4746
4747 static bool bnxt_need_reserve_rings(struct bnxt *bp)
4748 {
4749         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4750         int cp = bnxt_cp_rings_in_use(bp);
4751         int rx = bp->rx_nr_rings;
4752         int vnic = 1, grp = rx;
4753
4754         if (bp->hwrm_spec_code < 0x10601)
4755                 return false;
4756
4757         if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
4758                 return true;
4759
4760         if (bp->flags & BNXT_FLAG_RFS)
4761                 vnic = rx + 1;
4762         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4763                 rx <<= 1;
4764         if ((bp->flags & BNXT_FLAG_NEW_RM) &&
4765             (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
4766              hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic))
4767                 return true;
4768         return false;
4769 }
4770
4771 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4772                            bool shared);
4773
4774 static int __bnxt_reserve_rings(struct bnxt *bp)
4775 {
4776         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4777         int cp = bnxt_cp_rings_in_use(bp);
4778         int tx = bp->tx_nr_rings;
4779         int rx = bp->rx_nr_rings;
4780         int grp, rx_rings, rc;
4781         bool sh = false;
4782         int vnic = 1;
4783
4784         if (!bnxt_need_reserve_rings(bp))
4785                 return 0;
4786
4787         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4788                 sh = true;
4789         if (bp->flags & BNXT_FLAG_RFS)
4790                 vnic = rx + 1;
4791         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4792                 rx <<= 1;
4793         grp = bp->rx_nr_rings;
4794
4795         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
4796         if (rc)
4797                 return rc;
4798
4799         tx = hw_resc->resv_tx_rings;
4800         if (bp->flags & BNXT_FLAG_NEW_RM) {
4801                 rx = hw_resc->resv_rx_rings;
4802                 cp = hw_resc->resv_cp_rings;
4803                 grp = hw_resc->resv_hw_ring_grps;
4804                 vnic = hw_resc->resv_vnics;
4805         }
4806
4807         rx_rings = rx;
4808         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4809                 if (rx >= 2) {
4810                         rx_rings = rx >> 1;
4811                 } else {
4812                         if (netif_running(bp->dev))
4813                                 return -ENOMEM;
4814
4815                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4816                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4817                         bp->dev->hw_features &= ~NETIF_F_LRO;
4818                         bp->dev->features &= ~NETIF_F_LRO;
4819                         bnxt_set_ring_params(bp);
4820                 }
4821         }
4822         rx_rings = min_t(int, rx_rings, grp);
4823         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
4824         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4825                 rx = rx_rings << 1;
4826         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
4827         bp->tx_nr_rings = tx;
4828         bp->rx_nr_rings = rx_rings;
4829         bp->cp_nr_rings = cp;
4830
4831         if (!tx || !rx || !cp || !grp || !vnic)
4832                 return -ENOMEM;
4833
4834         return rc;
4835 }
4836
4837 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4838                                     int ring_grps, int cp_rings, int vnics)
4839 {
4840         struct hwrm_func_vf_cfg_input req = {0};
4841         u32 flags;
4842         int rc;
4843
4844         if (!(bp->flags & BNXT_FLAG_NEW_RM))
4845                 return 0;
4846
4847         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4848                                      cp_rings, vnics);
4849         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
4850                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4851                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4852                 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4853                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4854                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4855
4856         req.flags = cpu_to_le32(flags);
4857         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4858         if (rc)
4859                 return -ENOMEM;
4860         return 0;
4861 }
4862
4863 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4864                                     int ring_grps, int cp_rings, int vnics)
4865 {
4866         struct hwrm_func_cfg_input req = {0};
4867         u32 flags;
4868         int rc;
4869
4870         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4871                                      cp_rings, vnics);
4872         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4873         if (bp->flags & BNXT_FLAG_NEW_RM)
4874                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4875                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4876                          FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4877                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4878                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4879
4880         req.flags = cpu_to_le32(flags);
4881         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4882         if (rc)
4883                 return -ENOMEM;
4884         return 0;
4885 }
4886
4887 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4888                                  int ring_grps, int cp_rings, int vnics)
4889 {
4890         if (bp->hwrm_spec_code < 0x10801)
4891                 return 0;
4892
4893         if (BNXT_PF(bp))
4894                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
4895                                                 ring_grps, cp_rings, vnics);
4896
4897         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
4898                                         cp_rings, vnics);
4899 }
4900
4901 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4902         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4903 {
4904         u16 val, tmr, max, flags;
4905
4906         max = hw_coal->bufs_per_record * 128;
4907         if (hw_coal->budget)
4908                 max = hw_coal->bufs_per_record * hw_coal->budget;
4909
4910         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4911         req->num_cmpl_aggr_int = cpu_to_le16(val);
4912
4913         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4914         val = min_t(u16, val, 63);
4915         req->num_cmpl_dma_aggr = cpu_to_le16(val);
4916
4917         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4918         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
4919         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4920
4921         tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4922         tmr = max_t(u16, tmr, 1);
4923         req->int_lat_tmr_max = cpu_to_le16(tmr);
4924
4925         /* min timer set to 1/2 of interrupt timer */
4926         val = tmr / 2;
4927         req->int_lat_tmr_min = cpu_to_le16(val);
4928
4929         /* buf timer set to 1/4 of interrupt timer */
4930         val = max_t(u16, tmr / 4, 1);
4931         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4932
4933         tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4934         tmr = max_t(u16, tmr, 1);
4935         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4936
4937         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4938         if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4939                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4940         req->flags = cpu_to_le16(flags);
4941 }
4942
4943 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
4944 {
4945         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
4946         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4947         struct bnxt_coal coal;
4948         unsigned int grp_idx;
4949
4950         /* Tick values in micro seconds.
4951          * 1 coal_buf x bufs_per_record = 1 completion record.
4952          */
4953         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
4954
4955         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
4956         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
4957
4958         if (!bnapi->rx_ring)
4959                 return -ENODEV;
4960
4961         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4962                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4963
4964         bnxt_hwrm_set_coal_params(&coal, &req_rx);
4965
4966         grp_idx = bnapi->index;
4967         req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4968
4969         return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
4970                                  HWRM_CMD_TIMEOUT);
4971 }
4972
4973 int bnxt_hwrm_set_coal(struct bnxt *bp)
4974 {
4975         int i, rc = 0;
4976         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4977                                                            req_tx = {0}, *req;
4978
4979         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4980                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4981         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4982                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4983
4984         bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
4985         bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
4986
4987         mutex_lock(&bp->hwrm_cmd_lock);
4988         for (i = 0; i < bp->cp_nr_rings; i++) {
4989                 struct bnxt_napi *bnapi = bp->bnapi[i];
4990
4991                 req = &req_rx;
4992                 if (!bnapi->rx_ring)
4993                         req = &req_tx;
4994                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4995
4996                 rc = _hwrm_send_message(bp, req, sizeof(*req),
4997                                         HWRM_CMD_TIMEOUT);
4998                 if (rc)
4999                         break;
5000         }
5001         mutex_unlock(&bp->hwrm_cmd_lock);
5002         return rc;
5003 }
5004
5005 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5006 {
5007         int rc = 0, i;
5008         struct hwrm_stat_ctx_free_input req = {0};
5009
5010         if (!bp->bnapi)
5011                 return 0;
5012
5013         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5014                 return 0;
5015
5016         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5017
5018         mutex_lock(&bp->hwrm_cmd_lock);
5019         for (i = 0; i < bp->cp_nr_rings; i++) {
5020                 struct bnxt_napi *bnapi = bp->bnapi[i];
5021                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5022
5023                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5024                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5025
5026                         rc = _hwrm_send_message(bp, &req, sizeof(req),
5027                                                 HWRM_CMD_TIMEOUT);
5028                         if (rc)
5029                                 break;
5030
5031                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5032                 }
5033         }
5034         mutex_unlock(&bp->hwrm_cmd_lock);
5035         return rc;
5036 }
5037
5038 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5039 {
5040         int rc = 0, i;
5041         struct hwrm_stat_ctx_alloc_input req = {0};
5042         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5043
5044         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5045                 return 0;
5046
5047         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5048
5049         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5050
5051         mutex_lock(&bp->hwrm_cmd_lock);
5052         for (i = 0; i < bp->cp_nr_rings; i++) {
5053                 struct bnxt_napi *bnapi = bp->bnapi[i];
5054                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5055
5056                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5057
5058                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5059                                         HWRM_CMD_TIMEOUT);
5060                 if (rc)
5061                         break;
5062
5063                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5064
5065                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5066         }
5067         mutex_unlock(&bp->hwrm_cmd_lock);
5068         return rc;
5069 }
5070
5071 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5072 {
5073         struct hwrm_func_qcfg_input req = {0};
5074         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5075         u16 flags;
5076         int rc;
5077
5078         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5079         req.fid = cpu_to_le16(0xffff);
5080         mutex_lock(&bp->hwrm_cmd_lock);
5081         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5082         if (rc)
5083                 goto func_qcfg_exit;
5084
5085 #ifdef CONFIG_BNXT_SRIOV
5086         if (BNXT_VF(bp)) {
5087                 struct bnxt_vf_info *vf = &bp->vf;
5088
5089                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5090         }
5091 #endif
5092         flags = le16_to_cpu(resp->flags);
5093         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5094                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5095                 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
5096                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5097                         bp->flags |= BNXT_FLAG_FW_DCBX_AGENT;
5098         }
5099         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5100                 bp->flags |= BNXT_FLAG_MULTI_HOST;
5101
5102         switch (resp->port_partition_type) {
5103         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5104         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5105         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5106                 bp->port_partition_type = resp->port_partition_type;
5107                 break;
5108         }
5109         if (bp->hwrm_spec_code < 0x10707 ||
5110             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5111                 bp->br_mode = BRIDGE_MODE_VEB;
5112         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5113                 bp->br_mode = BRIDGE_MODE_VEPA;
5114         else
5115                 bp->br_mode = BRIDGE_MODE_UNDEF;
5116
5117         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5118         if (!bp->max_mtu)
5119                 bp->max_mtu = BNXT_MAX_MTU;
5120
5121 func_qcfg_exit:
5122         mutex_unlock(&bp->hwrm_cmd_lock);
5123         return rc;
5124 }
5125
5126 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
5127 {
5128         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5129         struct hwrm_func_resource_qcaps_input req = {0};
5130         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5131         int rc;
5132
5133         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
5134         req.fid = cpu_to_le16(0xffff);
5135
5136         mutex_lock(&bp->hwrm_cmd_lock);
5137         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5138         if (rc) {
5139                 rc = -EIO;
5140                 goto hwrm_func_resc_qcaps_exit;
5141         }
5142
5143         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
5144         if (!all)
5145                 goto hwrm_func_resc_qcaps_exit;
5146
5147         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
5148         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5149         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
5150         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5151         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
5152         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5153         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
5154         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5155         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
5156         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
5157         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
5158         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5159         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
5160         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5161         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
5162         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5163
5164         if (BNXT_PF(bp)) {
5165                 struct bnxt_pf_info *pf = &bp->pf;
5166
5167                 pf->vf_resv_strategy =
5168                         le16_to_cpu(resp->vf_reservation_strategy);
5169                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL)
5170                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
5171         }
5172 hwrm_func_resc_qcaps_exit:
5173         mutex_unlock(&bp->hwrm_cmd_lock);
5174         return rc;
5175 }
5176
5177 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
5178 {
5179         int rc = 0;
5180         struct hwrm_func_qcaps_input req = {0};
5181         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5182         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5183         u32 flags;
5184
5185         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
5186         req.fid = cpu_to_le16(0xffff);
5187
5188         mutex_lock(&bp->hwrm_cmd_lock);
5189         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5190         if (rc)
5191                 goto hwrm_func_qcaps_exit;
5192
5193         flags = le32_to_cpu(resp->flags);
5194         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
5195                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
5196         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
5197                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
5198
5199         bp->tx_push_thresh = 0;
5200         if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
5201                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
5202
5203         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5204         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5205         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5206         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5207         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
5208         if (!hw_resc->max_hw_ring_grps)
5209                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
5210         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5211         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5212         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5213
5214         if (BNXT_PF(bp)) {
5215                 struct bnxt_pf_info *pf = &bp->pf;
5216
5217                 pf->fw_fid = le16_to_cpu(resp->fid);
5218                 pf->port_id = le16_to_cpu(resp->port_id);
5219                 bp->dev->dev_port = pf->port_id;
5220                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
5221                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
5222                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
5223                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
5224                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
5225                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
5226                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
5227                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
5228                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
5229                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
5230                         bp->flags |= BNXT_FLAG_WOL_CAP;
5231         } else {
5232 #ifdef CONFIG_BNXT_SRIOV
5233                 struct bnxt_vf_info *vf = &bp->vf;
5234
5235                 vf->fw_fid = le16_to_cpu(resp->fid);
5236                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
5237 #endif
5238         }
5239
5240 hwrm_func_qcaps_exit:
5241         mutex_unlock(&bp->hwrm_cmd_lock);
5242         return rc;
5243 }
5244
5245 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5246 {
5247         int rc;
5248
5249         rc = __bnxt_hwrm_func_qcaps(bp);
5250         if (rc)
5251                 return rc;
5252         if (bp->hwrm_spec_code >= 0x10803) {
5253                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
5254                 if (!rc)
5255                         bp->flags |= BNXT_FLAG_NEW_RM;
5256         }
5257         return 0;
5258 }
5259
5260 static int bnxt_hwrm_func_reset(struct bnxt *bp)
5261 {
5262         struct hwrm_func_reset_input req = {0};
5263
5264         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
5265         req.enables = 0;
5266
5267         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
5268 }
5269
5270 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5271 {
5272         int rc = 0;
5273         struct hwrm_queue_qportcfg_input req = {0};
5274         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
5275         u8 i, *qptr;
5276
5277         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
5278
5279         mutex_lock(&bp->hwrm_cmd_lock);
5280         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5281         if (rc)
5282                 goto qportcfg_exit;
5283
5284         if (!resp->max_configurable_queues) {
5285                 rc = -EINVAL;
5286                 goto qportcfg_exit;
5287         }
5288         bp->max_tc = resp->max_configurable_queues;
5289         bp->max_lltc = resp->max_configurable_lossless_queues;
5290         if (bp->max_tc > BNXT_MAX_QUEUE)
5291                 bp->max_tc = BNXT_MAX_QUEUE;
5292
5293         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
5294                 bp->max_tc = 1;
5295
5296         if (bp->max_lltc > bp->max_tc)
5297                 bp->max_lltc = bp->max_tc;
5298
5299         qptr = &resp->queue_id0;
5300         for (i = 0; i < bp->max_tc; i++) {
5301                 bp->q_info[i].queue_id = *qptr++;
5302                 bp->q_info[i].queue_profile = *qptr++;
5303                 bp->tc_to_qidx[i] = i;
5304         }
5305
5306 qportcfg_exit:
5307         mutex_unlock(&bp->hwrm_cmd_lock);
5308         return rc;
5309 }
5310
5311 static int bnxt_hwrm_ver_get(struct bnxt *bp)
5312 {
5313         int rc;
5314         struct hwrm_ver_get_input req = {0};
5315         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
5316         u32 dev_caps_cfg;
5317
5318         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
5319         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
5320         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
5321         req.hwrm_intf_min = HWRM_VERSION_MINOR;
5322         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
5323         mutex_lock(&bp->hwrm_cmd_lock);
5324         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5325         if (rc)
5326                 goto hwrm_ver_get_exit;
5327
5328         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
5329
5330         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
5331                              resp->hwrm_intf_min_8b << 8 |
5332                              resp->hwrm_intf_upd_8b;
5333         if (resp->hwrm_intf_maj_8b < 1) {
5334                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
5335                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
5336                             resp->hwrm_intf_upd_8b);
5337                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
5338         }
5339         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
5340                  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
5341                  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
5342
5343         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
5344         if (!bp->hwrm_cmd_timeout)
5345                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
5346
5347         if (resp->hwrm_intf_maj_8b >= 1)
5348                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
5349
5350         bp->chip_num = le16_to_cpu(resp->chip_num);
5351         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
5352             !resp->chip_metal)
5353                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
5354
5355         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
5356         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5357             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5358                 bp->flags |= BNXT_FLAG_SHORT_CMD;
5359
5360 hwrm_ver_get_exit:
5361         mutex_unlock(&bp->hwrm_cmd_lock);
5362         return rc;
5363 }
5364
5365 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
5366 {
5367         struct hwrm_fw_set_time_input req = {0};
5368         struct tm tm;
5369         time64_t now = ktime_get_real_seconds();
5370
5371         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
5372             bp->hwrm_spec_code < 0x10400)
5373                 return -EOPNOTSUPP;
5374
5375         time64_to_tm(now, 0, &tm);
5376         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
5377         req.year = cpu_to_le16(1900 + tm.tm_year);
5378         req.month = 1 + tm.tm_mon;
5379         req.day = tm.tm_mday;
5380         req.hour = tm.tm_hour;
5381         req.minute = tm.tm_min;
5382         req.second = tm.tm_sec;
5383         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5384 }
5385
5386 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
5387 {
5388         int rc;
5389         struct bnxt_pf_info *pf = &bp->pf;
5390         struct hwrm_port_qstats_input req = {0};
5391
5392         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5393                 return 0;
5394
5395         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5396         req.port_id = cpu_to_le16(pf->port_id);
5397         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5398         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5399         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5400         return rc;
5401 }
5402
5403 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
5404 {
5405         struct hwrm_port_qstats_ext_input req = {0};
5406         struct bnxt_pf_info *pf = &bp->pf;
5407
5408         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5409                 return 0;
5410
5411         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
5412         req.port_id = cpu_to_le16(pf->port_id);
5413         req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
5414         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
5415         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5416 }
5417
5418 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5419 {
5420         if (bp->vxlan_port_cnt) {
5421                 bnxt_hwrm_tunnel_dst_port_free(
5422                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5423         }
5424         bp->vxlan_port_cnt = 0;
5425         if (bp->nge_port_cnt) {
5426                 bnxt_hwrm_tunnel_dst_port_free(
5427                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5428         }
5429         bp->nge_port_cnt = 0;
5430 }
5431
5432 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5433 {
5434         int rc, i;
5435         u32 tpa_flags = 0;
5436
5437         if (set_tpa)
5438                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5439         for (i = 0; i < bp->nr_vnics; i++) {
5440                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5441                 if (rc) {
5442                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5443                                    i, rc);
5444                         return rc;
5445                 }
5446         }
5447         return 0;
5448 }
5449
5450 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5451 {
5452         int i;
5453
5454         for (i = 0; i < bp->nr_vnics; i++)
5455                 bnxt_hwrm_vnic_set_rss(bp, i, false);
5456 }
5457
5458 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5459                                     bool irq_re_init)
5460 {
5461         if (bp->vnic_info) {
5462                 bnxt_hwrm_clear_vnic_filter(bp);
5463                 /* clear all RSS setting before free vnic ctx */
5464                 bnxt_hwrm_clear_vnic_rss(bp);
5465                 bnxt_hwrm_vnic_ctx_free(bp);
5466                 /* before free the vnic, undo the vnic tpa settings */
5467                 if (bp->flags & BNXT_FLAG_TPA)
5468                         bnxt_set_tpa(bp, false);
5469                 bnxt_hwrm_vnic_free(bp);
5470         }
5471         bnxt_hwrm_ring_free(bp, close_path);
5472         bnxt_hwrm_ring_grp_free(bp);
5473         if (irq_re_init) {
5474                 bnxt_hwrm_stat_ctx_free(bp);
5475                 bnxt_hwrm_free_tunnel_ports(bp);
5476         }
5477 }
5478
5479 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5480 {
5481         struct hwrm_func_cfg_input req = {0};
5482         int rc;
5483
5484         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5485         req.fid = cpu_to_le16(0xffff);
5486         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5487         if (br_mode == BRIDGE_MODE_VEB)
5488                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5489         else if (br_mode == BRIDGE_MODE_VEPA)
5490                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5491         else
5492                 return -EINVAL;
5493         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5494         if (rc)
5495                 rc = -EIO;
5496         return rc;
5497 }
5498
5499 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
5500 {
5501         struct hwrm_func_cfg_input req = {0};
5502         int rc;
5503
5504         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
5505                 return 0;
5506
5507         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5508         req.fid = cpu_to_le16(0xffff);
5509         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
5510         req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
5511         if (size == 128)
5512                 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
5513
5514         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5515         if (rc)
5516                 rc = -EIO;
5517         return rc;
5518 }
5519
5520 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5521 {
5522         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5523         int rc;
5524
5525         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5526                 goto skip_rss_ctx;
5527
5528         /* allocate context for vnic */
5529         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5530         if (rc) {
5531                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5532                            vnic_id, rc);
5533                 goto vnic_setup_err;
5534         }
5535         bp->rsscos_nr_ctxs++;
5536
5537         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5538                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5539                 if (rc) {
5540                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5541                                    vnic_id, rc);
5542                         goto vnic_setup_err;
5543                 }
5544                 bp->rsscos_nr_ctxs++;
5545         }
5546
5547 skip_rss_ctx:
5548         /* configure default vnic, ring grp */
5549         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5550         if (rc) {
5551                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5552                            vnic_id, rc);
5553                 goto vnic_setup_err;
5554         }
5555
5556         /* Enable RSS hashing on vnic */
5557         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5558         if (rc) {
5559                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5560                            vnic_id, rc);
5561                 goto vnic_setup_err;
5562         }
5563
5564         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5565                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5566                 if (rc) {
5567                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5568                                    vnic_id, rc);
5569                 }
5570         }
5571
5572 vnic_setup_err:
5573         return rc;
5574 }
5575
5576 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5577 {
5578 #ifdef CONFIG_RFS_ACCEL
5579         int i, rc = 0;
5580
5581         for (i = 0; i < bp->rx_nr_rings; i++) {
5582                 struct bnxt_vnic_info *vnic;
5583                 u16 vnic_id = i + 1;
5584                 u16 ring_id = i;
5585
5586                 if (vnic_id >= bp->nr_vnics)
5587                         break;
5588
5589                 vnic = &bp->vnic_info[vnic_id];
5590                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5591                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5592                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5593                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5594                 if (rc) {
5595                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5596                                    vnic_id, rc);
5597                         break;
5598                 }
5599                 rc = bnxt_setup_vnic(bp, vnic_id);
5600                 if (rc)
5601                         break;
5602         }
5603         return rc;
5604 #else
5605         return 0;
5606 #endif
5607 }
5608
5609 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5610 static bool bnxt_promisc_ok(struct bnxt *bp)
5611 {
5612 #ifdef CONFIG_BNXT_SRIOV
5613         if (BNXT_VF(bp) && !bp->vf.vlan)
5614                 return false;
5615 #endif
5616         return true;
5617 }
5618
5619 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5620 {
5621         unsigned int rc = 0;
5622
5623         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5624         if (rc) {
5625                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5626                            rc);
5627                 return rc;
5628         }
5629
5630         rc = bnxt_hwrm_vnic_cfg(bp, 1);
5631         if (rc) {
5632                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5633                            rc);
5634                 return rc;
5635         }
5636         return rc;
5637 }
5638
5639 static int bnxt_cfg_rx_mode(struct bnxt *);
5640 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5641
5642 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5643 {
5644         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5645         int rc = 0;
5646         unsigned int rx_nr_rings = bp->rx_nr_rings;
5647
5648         if (irq_re_init) {
5649                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5650                 if (rc) {
5651                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5652                                    rc);
5653                         goto err_out;
5654                 }
5655         }
5656
5657         rc = bnxt_hwrm_ring_alloc(bp);
5658         if (rc) {
5659                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5660                 goto err_out;
5661         }
5662
5663         rc = bnxt_hwrm_ring_grp_alloc(bp);
5664         if (rc) {
5665                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5666                 goto err_out;
5667         }
5668
5669         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5670                 rx_nr_rings--;
5671
5672         /* default vnic 0 */
5673         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5674         if (rc) {
5675                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5676                 goto err_out;
5677         }
5678
5679         rc = bnxt_setup_vnic(bp, 0);
5680         if (rc)
5681                 goto err_out;
5682
5683         if (bp->flags & BNXT_FLAG_RFS) {
5684                 rc = bnxt_alloc_rfs_vnics(bp);
5685                 if (rc)
5686                         goto err_out;
5687         }
5688
5689         if (bp->flags & BNXT_FLAG_TPA) {
5690                 rc = bnxt_set_tpa(bp, true);
5691                 if (rc)
5692                         goto err_out;
5693         }
5694
5695         if (BNXT_VF(bp))
5696                 bnxt_update_vf_mac(bp);
5697
5698         /* Filter for default vnic 0 */
5699         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5700         if (rc) {
5701                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5702                 goto err_out;
5703         }
5704         vnic->uc_filter_count = 1;
5705
5706         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5707
5708         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5709                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5710
5711         if (bp->dev->flags & IFF_ALLMULTI) {
5712                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5713                 vnic->mc_list_count = 0;
5714         } else {
5715                 u32 mask = 0;
5716
5717                 bnxt_mc_list_updated(bp, &mask);
5718                 vnic->rx_mask |= mask;
5719         }
5720
5721         rc = bnxt_cfg_rx_mode(bp);
5722         if (rc)
5723                 goto err_out;
5724
5725         rc = bnxt_hwrm_set_coal(bp);
5726         if (rc)
5727                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5728                                 rc);
5729
5730         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5731                 rc = bnxt_setup_nitroa0_vnic(bp);
5732                 if (rc)
5733                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5734                                    rc);
5735         }
5736
5737         if (BNXT_VF(bp)) {
5738                 bnxt_hwrm_func_qcfg(bp);
5739                 netdev_update_features(bp->dev);
5740         }
5741
5742         return 0;
5743
5744 err_out:
5745         bnxt_hwrm_resource_free(bp, 0, true);
5746
5747         return rc;
5748 }
5749
5750 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5751 {
5752         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5753         return 0;
5754 }
5755
5756 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5757 {
5758         bnxt_init_cp_rings(bp);
5759         bnxt_init_rx_rings(bp);
5760         bnxt_init_tx_rings(bp);
5761         bnxt_init_ring_grps(bp, irq_re_init);
5762         bnxt_init_vnics(bp);
5763
5764         return bnxt_init_chip(bp, irq_re_init);
5765 }
5766
5767 static int bnxt_set_real_num_queues(struct bnxt *bp)
5768 {
5769         int rc;
5770         struct net_device *dev = bp->dev;
5771
5772         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5773                                           bp->tx_nr_rings_xdp);
5774         if (rc)
5775                 return rc;
5776
5777         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5778         if (rc)
5779                 return rc;
5780
5781 #ifdef CONFIG_RFS_ACCEL
5782         if (bp->flags & BNXT_FLAG_RFS)
5783                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5784 #endif
5785
5786         return rc;
5787 }
5788
5789 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5790                            bool shared)
5791 {
5792         int _rx = *rx, _tx = *tx;
5793
5794         if (shared) {
5795                 *rx = min_t(int, _rx, max);
5796                 *tx = min_t(int, _tx, max);
5797         } else {
5798                 if (max < 2)
5799                         return -ENOMEM;
5800
5801                 while (_rx + _tx > max) {
5802                         if (_rx > _tx && _rx > 1)
5803                                 _rx--;
5804                         else if (_tx > 1)
5805                                 _tx--;
5806                 }
5807                 *rx = _rx;
5808                 *tx = _tx;
5809         }
5810         return 0;
5811 }
5812
5813 static void bnxt_setup_msix(struct bnxt *bp)
5814 {
5815         const int len = sizeof(bp->irq_tbl[0].name);
5816         struct net_device *dev = bp->dev;
5817         int tcs, i;
5818
5819         tcs = netdev_get_num_tc(dev);
5820         if (tcs > 1) {
5821                 int i, off, count;
5822
5823                 for (i = 0; i < tcs; i++) {
5824                         count = bp->tx_nr_rings_per_tc;
5825                         off = i * count;
5826                         netdev_set_tc_queue(dev, i, count, off);
5827                 }
5828         }
5829
5830         for (i = 0; i < bp->cp_nr_rings; i++) {
5831                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
5832                 char *attr;
5833
5834                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5835                         attr = "TxRx";
5836                 else if (i < bp->rx_nr_rings)
5837                         attr = "rx";
5838                 else
5839                         attr = "tx";
5840
5841                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
5842                          attr, i);
5843                 bp->irq_tbl[map_idx].handler = bnxt_msix;
5844         }
5845 }
5846
5847 static void bnxt_setup_inta(struct bnxt *bp)
5848 {
5849         const int len = sizeof(bp->irq_tbl[0].name);
5850
5851         if (netdev_get_num_tc(bp->dev))
5852                 netdev_reset_tc(bp->dev);
5853
5854         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5855                  0);
5856         bp->irq_tbl[0].handler = bnxt_inta;
5857 }
5858
5859 static int bnxt_setup_int_mode(struct bnxt *bp)
5860 {
5861         int rc;
5862
5863         if (bp->flags & BNXT_FLAG_USING_MSIX)
5864                 bnxt_setup_msix(bp);
5865         else
5866                 bnxt_setup_inta(bp);
5867
5868         rc = bnxt_set_real_num_queues(bp);
5869         return rc;
5870 }
5871
5872 #ifdef CONFIG_RFS_ACCEL
5873 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5874 {
5875         return bp->hw_resc.max_rsscos_ctxs;
5876 }
5877
5878 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5879 {
5880         return bp->hw_resc.max_vnics;
5881 }
5882 #endif
5883
5884 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5885 {
5886         return bp->hw_resc.max_stat_ctxs;
5887 }
5888
5889 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5890 {
5891         bp->hw_resc.max_stat_ctxs = max;
5892 }
5893
5894 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5895 {
5896         return bp->hw_resc.max_cp_rings;
5897 }
5898
5899 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5900 {
5901         bp->hw_resc.max_cp_rings = max;
5902 }
5903
5904 unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5905 {
5906         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5907
5908         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
5909 }
5910
5911 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5912 {
5913         bp->hw_resc.max_irqs = max_irqs;
5914 }
5915
5916 int bnxt_get_avail_msix(struct bnxt *bp, int num)
5917 {
5918         int max_cp = bnxt_get_max_func_cp_rings(bp);
5919         int max_irq = bnxt_get_max_func_irqs(bp);
5920         int total_req = bp->cp_nr_rings + num;
5921         int max_idx, avail_msix;
5922
5923         max_idx = min_t(int, bp->total_irqs, max_cp);
5924         avail_msix = max_idx - bp->cp_nr_rings;
5925         if (!(bp->flags & BNXT_FLAG_NEW_RM) || avail_msix >= num)
5926                 return avail_msix;
5927
5928         if (max_irq < total_req) {
5929                 num = max_irq - bp->cp_nr_rings;
5930                 if (num <= 0)
5931                         return 0;
5932         }
5933         return num;
5934 }
5935
5936 static int bnxt_get_num_msix(struct bnxt *bp)
5937 {
5938         if (!(bp->flags & BNXT_FLAG_NEW_RM))
5939                 return bnxt_get_max_func_irqs(bp);
5940
5941         return bnxt_cp_rings_in_use(bp);
5942 }
5943
5944 static int bnxt_init_msix(struct bnxt *bp)
5945 {
5946         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
5947         struct msix_entry *msix_ent;
5948
5949         total_vecs = bnxt_get_num_msix(bp);
5950         max = bnxt_get_max_func_irqs(bp);
5951         if (total_vecs > max)
5952                 total_vecs = max;
5953
5954         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5955         if (!msix_ent)
5956                 return -ENOMEM;
5957
5958         for (i = 0; i < total_vecs; i++) {
5959                 msix_ent[i].entry = i;
5960                 msix_ent[i].vector = 0;
5961         }
5962
5963         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5964                 min = 2;
5965
5966         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5967         ulp_msix = bnxt_get_ulp_msix_num(bp);
5968         if (total_vecs < 0 || total_vecs < ulp_msix) {
5969                 rc = -ENODEV;
5970                 goto msix_setup_exit;
5971         }
5972
5973         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5974         if (bp->irq_tbl) {
5975                 for (i = 0; i < total_vecs; i++)
5976                         bp->irq_tbl[i].vector = msix_ent[i].vector;
5977
5978                 bp->total_irqs = total_vecs;
5979                 /* Trim rings based upon num of vectors allocated */
5980                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5981                                      total_vecs - ulp_msix, min == 1);
5982                 if (rc)
5983                         goto msix_setup_exit;
5984
5985                 bp->cp_nr_rings = (min == 1) ?
5986                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5987                                   bp->tx_nr_rings + bp->rx_nr_rings;
5988
5989         } else {
5990                 rc = -ENOMEM;
5991                 goto msix_setup_exit;
5992         }
5993         bp->flags |= BNXT_FLAG_USING_MSIX;
5994         kfree(msix_ent);
5995         return 0;
5996
5997 msix_setup_exit:
5998         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5999         kfree(bp->irq_tbl);
6000         bp->irq_tbl = NULL;
6001         pci_disable_msix(bp->pdev);
6002         kfree(msix_ent);
6003         return rc;
6004 }
6005
6006 static int bnxt_init_inta(struct bnxt *bp)
6007 {
6008         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
6009         if (!bp->irq_tbl)
6010                 return -ENOMEM;
6011
6012         bp->total_irqs = 1;
6013         bp->rx_nr_rings = 1;
6014         bp->tx_nr_rings = 1;
6015         bp->cp_nr_rings = 1;
6016         bp->flags |= BNXT_FLAG_SHARED_RINGS;
6017         bp->irq_tbl[0].vector = bp->pdev->irq;
6018         return 0;
6019 }
6020
6021 static int bnxt_init_int_mode(struct bnxt *bp)
6022 {
6023         int rc = 0;
6024
6025         if (bp->flags & BNXT_FLAG_MSIX_CAP)
6026                 rc = bnxt_init_msix(bp);
6027
6028         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
6029                 /* fallback to INTA */
6030                 rc = bnxt_init_inta(bp);
6031         }
6032         return rc;
6033 }
6034
6035 static void bnxt_clear_int_mode(struct bnxt *bp)
6036 {
6037         if (bp->flags & BNXT_FLAG_USING_MSIX)
6038                 pci_disable_msix(bp->pdev);
6039
6040         kfree(bp->irq_tbl);
6041         bp->irq_tbl = NULL;
6042         bp->flags &= ~BNXT_FLAG_USING_MSIX;
6043 }
6044
6045 int bnxt_reserve_rings(struct bnxt *bp)
6046 {
6047         int tcs = netdev_get_num_tc(bp->dev);
6048         int rc;
6049
6050         if (!bnxt_need_reserve_rings(bp))
6051                 return 0;
6052
6053         rc = __bnxt_reserve_rings(bp);
6054         if (rc) {
6055                 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc);
6056                 return rc;
6057         }
6058         if ((bp->flags & BNXT_FLAG_NEW_RM) &&
6059             (bnxt_get_num_msix(bp) != bp->total_irqs)) {
6060                 bnxt_ulp_irq_stop(bp);
6061                 bnxt_clear_int_mode(bp);
6062                 rc = bnxt_init_int_mode(bp);
6063                 bnxt_ulp_irq_restart(bp, rc);
6064                 if (rc)
6065                         return rc;
6066         }
6067         if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
6068                 netdev_err(bp->dev, "tx ring reservation failure\n");
6069                 netdev_reset_tc(bp->dev);
6070                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
6071                 return -ENOMEM;
6072         }
6073         bp->num_stat_ctxs = bp->cp_nr_rings;
6074         return 0;
6075 }
6076
6077 static void bnxt_free_irq(struct bnxt *bp)
6078 {
6079         struct bnxt_irq *irq;
6080         int i;
6081
6082 #ifdef CONFIG_RFS_ACCEL
6083         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
6084         bp->dev->rx_cpu_rmap = NULL;
6085 #endif
6086         if (!bp->irq_tbl || !bp->bnapi)
6087                 return;
6088
6089         for (i = 0; i < bp->cp_nr_rings; i++) {
6090                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6091
6092                 irq = &bp->irq_tbl[map_idx];
6093                 if (irq->requested) {
6094                         if (irq->have_cpumask) {
6095                                 irq_set_affinity_hint(irq->vector, NULL);
6096                                 free_cpumask_var(irq->cpu_mask);
6097                                 irq->have_cpumask = 0;
6098                         }
6099                         free_irq(irq->vector, bp->bnapi[i]);
6100                 }
6101
6102                 irq->requested = 0;
6103         }
6104 }
6105
6106 static int bnxt_request_irq(struct bnxt *bp)
6107 {
6108         int i, j, rc = 0;
6109         unsigned long flags = 0;
6110 #ifdef CONFIG_RFS_ACCEL
6111         struct cpu_rmap *rmap;
6112 #endif
6113
6114         rc = bnxt_setup_int_mode(bp);
6115         if (rc) {
6116                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6117                            rc);
6118                 return rc;
6119         }
6120 #ifdef CONFIG_RFS_ACCEL
6121         rmap = bp->dev->rx_cpu_rmap;
6122 #endif
6123         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
6124                 flags = IRQF_SHARED;
6125
6126         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
6127                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6128                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
6129
6130 #ifdef CONFIG_RFS_ACCEL
6131                 if (rmap && bp->bnapi[i]->rx_ring) {
6132                         rc = irq_cpu_rmap_add(rmap, irq->vector);
6133                         if (rc)
6134                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
6135                                             j);
6136                         j++;
6137                 }
6138 #endif
6139                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6140                                  bp->bnapi[i]);
6141                 if (rc)
6142                         break;
6143
6144                 irq->requested = 1;
6145
6146                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
6147                         int numa_node = dev_to_node(&bp->pdev->dev);
6148
6149                         irq->have_cpumask = 1;
6150                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
6151                                         irq->cpu_mask);
6152                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
6153                         if (rc) {
6154                                 netdev_warn(bp->dev,
6155                                             "Set affinity failed, IRQ = %d\n",
6156                                             irq->vector);
6157                                 break;
6158                         }
6159                 }
6160         }
6161         return rc;
6162 }
6163
6164 static void bnxt_del_napi(struct bnxt *bp)
6165 {
6166         int i;
6167
6168         if (!bp->bnapi)
6169                 return;
6170
6171         for (i = 0; i < bp->cp_nr_rings; i++) {
6172                 struct bnxt_napi *bnapi = bp->bnapi[i];
6173
6174                 napi_hash_del(&bnapi->napi);
6175                 netif_napi_del(&bnapi->napi);
6176         }
6177         /* We called napi_hash_del() before netif_napi_del(), we need
6178          * to respect an RCU grace period before freeing napi structures.
6179          */
6180         synchronize_net();
6181 }
6182
6183 static void bnxt_init_napi(struct bnxt *bp)
6184 {
6185         int i;
6186         unsigned int cp_nr_rings = bp->cp_nr_rings;
6187         struct bnxt_napi *bnapi;
6188
6189         if (bp->flags & BNXT_FLAG_USING_MSIX) {
6190                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6191                         cp_nr_rings--;
6192                 for (i = 0; i < cp_nr_rings; i++) {
6193                         bnapi = bp->bnapi[i];
6194                         netif_napi_add(bp->dev, &bnapi->napi,
6195                                        bnxt_poll, 64);
6196                 }
6197                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6198                         bnapi = bp->bnapi[cp_nr_rings];
6199                         netif_napi_add(bp->dev, &bnapi->napi,
6200                                        bnxt_poll_nitroa0, 64);
6201                 }
6202         } else {
6203                 bnapi = bp->bnapi[0];
6204                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
6205         }
6206 }
6207
6208 static void bnxt_disable_napi(struct bnxt *bp)
6209 {
6210         int i;
6211
6212         if (!bp->bnapi)
6213                 return;
6214
6215         for (i = 0; i < bp->cp_nr_rings; i++) {
6216                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6217
6218                 if (bp->bnapi[i]->rx_ring)
6219                         cancel_work_sync(&cpr->dim.work);
6220
6221                 napi_disable(&bp->bnapi[i]->napi);
6222         }
6223 }
6224
6225 static void bnxt_enable_napi(struct bnxt *bp)
6226 {
6227         int i;
6228
6229         for (i = 0; i < bp->cp_nr_rings; i++) {
6230                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6231                 bp->bnapi[i]->in_reset = false;
6232
6233                 if (bp->bnapi[i]->rx_ring) {
6234                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
6235                         cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
6236                 }
6237                 napi_enable(&bp->bnapi[i]->napi);
6238         }
6239 }
6240
6241 void bnxt_tx_disable(struct bnxt *bp)
6242 {
6243         int i;
6244         struct bnxt_tx_ring_info *txr;
6245
6246         if (bp->tx_ring) {
6247                 for (i = 0; i < bp->tx_nr_rings; i++) {
6248                         txr = &bp->tx_ring[i];
6249                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
6250                 }
6251         }
6252         /* Stop all TX queues */
6253         netif_tx_disable(bp->dev);
6254         netif_carrier_off(bp->dev);
6255 }
6256
6257 void bnxt_tx_enable(struct bnxt *bp)
6258 {
6259         int i;
6260         struct bnxt_tx_ring_info *txr;
6261
6262         for (i = 0; i < bp->tx_nr_rings; i++) {
6263                 txr = &bp->tx_ring[i];
6264                 txr->dev_state = 0;
6265         }
6266         netif_tx_wake_all_queues(bp->dev);
6267         if (bp->link_info.link_up)
6268                 netif_carrier_on(bp->dev);
6269 }
6270
6271 static void bnxt_report_link(struct bnxt *bp)
6272 {
6273         if (bp->link_info.link_up) {
6274                 const char *duplex;
6275                 const char *flow_ctrl;
6276                 u32 speed;
6277                 u16 fec;
6278
6279                 netif_carrier_on(bp->dev);
6280                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
6281                         duplex = "full";
6282                 else
6283                         duplex = "half";
6284                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
6285                         flow_ctrl = "ON - receive & transmit";
6286                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
6287                         flow_ctrl = "ON - transmit";
6288                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
6289                         flow_ctrl = "ON - receive";
6290                 else
6291                         flow_ctrl = "none";
6292                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
6293                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
6294                             speed, duplex, flow_ctrl);
6295                 if (bp->flags & BNXT_FLAG_EEE_CAP)
6296                         netdev_info(bp->dev, "EEE is %s\n",
6297                                     bp->eee.eee_active ? "active" :
6298                                                          "not active");
6299                 fec = bp->link_info.fec_cfg;
6300                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
6301                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
6302                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
6303                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
6304                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
6305         } else {
6306                 netif_carrier_off(bp->dev);
6307                 netdev_err(bp->dev, "NIC Link is Down\n");
6308         }
6309 }
6310
6311 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
6312 {
6313         int rc = 0;
6314         struct hwrm_port_phy_qcaps_input req = {0};
6315         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6316         struct bnxt_link_info *link_info = &bp->link_info;
6317
6318         if (bp->hwrm_spec_code < 0x10201)
6319                 return 0;
6320
6321         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
6322
6323         mutex_lock(&bp->hwrm_cmd_lock);
6324         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6325         if (rc)
6326                 goto hwrm_phy_qcaps_exit;
6327
6328         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
6329                 struct ethtool_eee *eee = &bp->eee;
6330                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
6331
6332                 bp->flags |= BNXT_FLAG_EEE_CAP;
6333                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6334                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
6335                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
6336                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
6337                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
6338         }
6339         if (resp->supported_speeds_auto_mode)
6340                 link_info->support_auto_speeds =
6341                         le16_to_cpu(resp->supported_speeds_auto_mode);
6342
6343         bp->port_count = resp->port_cnt;
6344
6345 hwrm_phy_qcaps_exit:
6346         mutex_unlock(&bp->hwrm_cmd_lock);
6347         return rc;
6348 }
6349
6350 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
6351 {
6352         int rc = 0;
6353         struct bnxt_link_info *link_info = &bp->link_info;
6354         struct hwrm_port_phy_qcfg_input req = {0};
6355         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6356         u8 link_up = link_info->link_up;
6357         u16 diff;
6358
6359         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
6360
6361         mutex_lock(&bp->hwrm_cmd_lock);
6362         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6363         if (rc) {
6364                 mutex_unlock(&bp->hwrm_cmd_lock);
6365                 return rc;
6366         }
6367
6368         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
6369         link_info->phy_link_status = resp->link;
6370         link_info->duplex = resp->duplex_cfg;
6371         if (bp->hwrm_spec_code >= 0x10800)
6372                 link_info->duplex = resp->duplex_state;
6373         link_info->pause = resp->pause;
6374         link_info->auto_mode = resp->auto_mode;
6375         link_info->auto_pause_setting = resp->auto_pause;
6376         link_info->lp_pause = resp->link_partner_adv_pause;
6377         link_info->force_pause_setting = resp->force_pause;
6378         link_info->duplex_setting = resp->duplex_cfg;
6379         if (link_info->phy_link_status == BNXT_LINK_LINK)
6380                 link_info->link_speed = le16_to_cpu(resp->link_speed);
6381         else
6382                 link_info->link_speed = 0;
6383         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
6384         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
6385         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
6386         link_info->lp_auto_link_speeds =
6387                 le16_to_cpu(resp->link_partner_adv_speeds);
6388         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
6389         link_info->phy_ver[0] = resp->phy_maj;
6390         link_info->phy_ver[1] = resp->phy_min;
6391         link_info->phy_ver[2] = resp->phy_bld;
6392         link_info->media_type = resp->media_type;
6393         link_info->phy_type = resp->phy_type;
6394         link_info->transceiver = resp->xcvr_pkg_type;
6395         link_info->phy_addr = resp->eee_config_phy_addr &
6396                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
6397         link_info->module_status = resp->module_status;
6398
6399         if (bp->flags & BNXT_FLAG_EEE_CAP) {
6400                 struct ethtool_eee *eee = &bp->eee;
6401                 u16 fw_speeds;
6402
6403                 eee->eee_active = 0;
6404                 if (resp->eee_config_phy_addr &
6405                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
6406                         eee->eee_active = 1;
6407                         fw_speeds = le16_to_cpu(
6408                                 resp->link_partner_adv_eee_link_speed_mask);
6409                         eee->lp_advertised =
6410                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6411                 }
6412
6413                 /* Pull initial EEE config */
6414                 if (!chng_link_state) {
6415                         if (resp->eee_config_phy_addr &
6416                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
6417                                 eee->eee_enabled = 1;
6418
6419                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
6420                         eee->advertised =
6421                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6422
6423                         if (resp->eee_config_phy_addr &
6424                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
6425                                 __le32 tmr;
6426
6427                                 eee->tx_lpi_enabled = 1;
6428                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
6429                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
6430                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
6431                         }
6432                 }
6433         }
6434
6435         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
6436         if (bp->hwrm_spec_code >= 0x10504)
6437                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
6438
6439         /* TODO: need to add more logic to report VF link */
6440         if (chng_link_state) {
6441                 if (link_info->phy_link_status == BNXT_LINK_LINK)
6442                         link_info->link_up = 1;
6443                 else
6444                         link_info->link_up = 0;
6445                 if (link_up != link_info->link_up)
6446                         bnxt_report_link(bp);
6447         } else {
6448                 /* alwasy link down if not require to update link state */
6449                 link_info->link_up = 0;
6450         }
6451         mutex_unlock(&bp->hwrm_cmd_lock);
6452
6453         diff = link_info->support_auto_speeds ^ link_info->advertising;
6454         if ((link_info->support_auto_speeds | diff) !=
6455             link_info->support_auto_speeds) {
6456                 /* An advertised speed is no longer supported, so we need to
6457                  * update the advertisement settings.  Caller holds RTNL
6458                  * so we can modify link settings.
6459                  */
6460                 link_info->advertising = link_info->support_auto_speeds;
6461                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
6462                         bnxt_hwrm_set_link_setting(bp, true, false);
6463         }
6464         return 0;
6465 }
6466
6467 static void bnxt_get_port_module_status(struct bnxt *bp)
6468 {
6469         struct bnxt_link_info *link_info = &bp->link_info;
6470         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
6471         u8 module_status;
6472
6473         if (bnxt_update_link(bp, true))
6474                 return;
6475
6476         module_status = link_info->module_status;
6477         switch (module_status) {
6478         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
6479         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6480         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6481                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6482                             bp->pf.port_id);
6483                 if (bp->hwrm_spec_code >= 0x10201) {
6484                         netdev_warn(bp->dev, "Module part number %s\n",
6485                                     resp->phy_vendor_partnumber);
6486                 }
6487                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6488                         netdev_warn(bp->dev, "TX is disabled\n");
6489                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6490                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6491         }
6492 }
6493
6494 static void
6495 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6496 {
6497         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
6498                 if (bp->hwrm_spec_code >= 0x10201)
6499                         req->auto_pause =
6500                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
6501                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6502                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6503                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6504                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
6505                 req->enables |=
6506                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6507         } else {
6508                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6509                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6510                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6511                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6512                 req->enables |=
6513                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
6514                 if (bp->hwrm_spec_code >= 0x10201) {
6515                         req->auto_pause = req->force_pause;
6516                         req->enables |= cpu_to_le32(
6517                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6518                 }
6519         }
6520 }
6521
6522 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6523                                       struct hwrm_port_phy_cfg_input *req)
6524 {
6525         u8 autoneg = bp->link_info.autoneg;
6526         u16 fw_link_speed = bp->link_info.req_link_speed;
6527         u16 advertising = bp->link_info.advertising;
6528
6529         if (autoneg & BNXT_AUTONEG_SPEED) {
6530                 req->auto_mode |=
6531                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6532
6533                 req->enables |= cpu_to_le32(
6534                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6535                 req->auto_link_speed_mask = cpu_to_le16(advertising);
6536
6537                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6538                 req->flags |=
6539                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6540         } else {
6541                 req->force_link_speed = cpu_to_le16(fw_link_speed);
6542                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6543         }
6544
6545         /* tell chimp that the setting takes effect immediately */
6546         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6547 }
6548
6549 int bnxt_hwrm_set_pause(struct bnxt *bp)
6550 {
6551         struct hwrm_port_phy_cfg_input req = {0};
6552         int rc;
6553
6554         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6555         bnxt_hwrm_set_pause_common(bp, &req);
6556
6557         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6558             bp->link_info.force_link_chng)
6559                 bnxt_hwrm_set_link_common(bp, &req);
6560
6561         mutex_lock(&bp->hwrm_cmd_lock);
6562         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6563         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6564                 /* since changing of pause setting doesn't trigger any link
6565                  * change event, the driver needs to update the current pause
6566                  * result upon successfully return of the phy_cfg command
6567                  */
6568                 bp->link_info.pause =
6569                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6570                 bp->link_info.auto_pause_setting = 0;
6571                 if (!bp->link_info.force_link_chng)
6572                         bnxt_report_link(bp);
6573         }
6574         bp->link_info.force_link_chng = false;
6575         mutex_unlock(&bp->hwrm_cmd_lock);
6576         return rc;
6577 }
6578
6579 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6580                               struct hwrm_port_phy_cfg_input *req)
6581 {
6582         struct ethtool_eee *eee = &bp->eee;
6583
6584         if (eee->eee_enabled) {
6585                 u16 eee_speeds;
6586                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6587
6588                 if (eee->tx_lpi_enabled)
6589                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6590                 else
6591                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6592
6593                 req->flags |= cpu_to_le32(flags);
6594                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6595                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6596                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6597         } else {
6598                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6599         }
6600 }
6601
6602 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6603 {
6604         struct hwrm_port_phy_cfg_input req = {0};
6605
6606         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6607         if (set_pause)
6608                 bnxt_hwrm_set_pause_common(bp, &req);
6609
6610         bnxt_hwrm_set_link_common(bp, &req);
6611
6612         if (set_eee)
6613                 bnxt_hwrm_set_eee(bp, &req);
6614         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6615 }
6616
6617 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6618 {
6619         struct hwrm_port_phy_cfg_input req = {0};
6620
6621         if (!BNXT_SINGLE_PF(bp))
6622                 return 0;
6623
6624         if (pci_num_vf(bp->pdev))
6625                 return 0;
6626
6627         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6628         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6629         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6630 }
6631
6632 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6633 {
6634         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6635         struct hwrm_port_led_qcaps_input req = {0};
6636         struct bnxt_pf_info *pf = &bp->pf;
6637         int rc;
6638
6639         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6640                 return 0;
6641
6642         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6643         req.port_id = cpu_to_le16(pf->port_id);
6644         mutex_lock(&bp->hwrm_cmd_lock);
6645         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6646         if (rc) {
6647                 mutex_unlock(&bp->hwrm_cmd_lock);
6648                 return rc;
6649         }
6650         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6651                 int i;
6652
6653                 bp->num_leds = resp->num_leds;
6654                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6655                                                  bp->num_leds);
6656                 for (i = 0; i < bp->num_leds; i++) {
6657                         struct bnxt_led_info *led = &bp->leds[i];
6658                         __le16 caps = led->led_state_caps;
6659
6660                         if (!led->led_group_id ||
6661                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
6662                                 bp->num_leds = 0;
6663                                 break;
6664                         }
6665                 }
6666         }
6667         mutex_unlock(&bp->hwrm_cmd_lock);
6668         return 0;
6669 }
6670
6671 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6672 {
6673         struct hwrm_wol_filter_alloc_input req = {0};
6674         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6675         int rc;
6676
6677         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6678         req.port_id = cpu_to_le16(bp->pf.port_id);
6679         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6680         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6681         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6682         mutex_lock(&bp->hwrm_cmd_lock);
6683         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6684         if (!rc)
6685                 bp->wol_filter_id = resp->wol_filter_id;
6686         mutex_unlock(&bp->hwrm_cmd_lock);
6687         return rc;
6688 }
6689
6690 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6691 {
6692         struct hwrm_wol_filter_free_input req = {0};
6693         int rc;
6694
6695         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6696         req.port_id = cpu_to_le16(bp->pf.port_id);
6697         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6698         req.wol_filter_id = bp->wol_filter_id;
6699         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6700         return rc;
6701 }
6702
6703 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6704 {
6705         struct hwrm_wol_filter_qcfg_input req = {0};
6706         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6707         u16 next_handle = 0;
6708         int rc;
6709
6710         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6711         req.port_id = cpu_to_le16(bp->pf.port_id);
6712         req.handle = cpu_to_le16(handle);
6713         mutex_lock(&bp->hwrm_cmd_lock);
6714         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6715         if (!rc) {
6716                 next_handle = le16_to_cpu(resp->next_handle);
6717                 if (next_handle != 0) {
6718                         if (resp->wol_type ==
6719                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6720                                 bp->wol = 1;
6721                                 bp->wol_filter_id = resp->wol_filter_id;
6722                         }
6723                 }
6724         }
6725         mutex_unlock(&bp->hwrm_cmd_lock);
6726         return next_handle;
6727 }
6728
6729 static void bnxt_get_wol_settings(struct bnxt *bp)
6730 {
6731         u16 handle = 0;
6732
6733         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6734                 return;
6735
6736         do {
6737                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6738         } while (handle && handle != 0xffff);
6739 }
6740
6741 static bool bnxt_eee_config_ok(struct bnxt *bp)
6742 {
6743         struct ethtool_eee *eee = &bp->eee;
6744         struct bnxt_link_info *link_info = &bp->link_info;
6745
6746         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6747                 return true;
6748
6749         if (eee->eee_enabled) {
6750                 u32 advertising =
6751                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6752
6753                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6754                         eee->eee_enabled = 0;
6755                         return false;
6756                 }
6757                 if (eee->advertised & ~advertising) {
6758                         eee->advertised = advertising & eee->supported;
6759                         return false;
6760                 }
6761         }
6762         return true;
6763 }
6764
6765 static int bnxt_update_phy_setting(struct bnxt *bp)
6766 {
6767         int rc;
6768         bool update_link = false;
6769         bool update_pause = false;
6770         bool update_eee = false;
6771         struct bnxt_link_info *link_info = &bp->link_info;
6772
6773         rc = bnxt_update_link(bp, true);
6774         if (rc) {
6775                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6776                            rc);
6777                 return rc;
6778         }
6779         if (!BNXT_SINGLE_PF(bp))
6780                 return 0;
6781
6782         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6783             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6784             link_info->req_flow_ctrl)
6785                 update_pause = true;
6786         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6787             link_info->force_pause_setting != link_info->req_flow_ctrl)
6788                 update_pause = true;
6789         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6790                 if (BNXT_AUTO_MODE(link_info->auto_mode))
6791                         update_link = true;
6792                 if (link_info->req_link_speed != link_info->force_link_speed)
6793                         update_link = true;
6794                 if (link_info->req_duplex != link_info->duplex_setting)
6795                         update_link = true;
6796         } else {
6797                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6798                         update_link = true;
6799                 if (link_info->advertising != link_info->auto_link_speeds)
6800                         update_link = true;
6801         }
6802
6803         /* The last close may have shutdown the link, so need to call
6804          * PHY_CFG to bring it back up.
6805          */
6806         if (!netif_carrier_ok(bp->dev))
6807                 update_link = true;
6808
6809         if (!bnxt_eee_config_ok(bp))
6810                 update_eee = true;
6811
6812         if (update_link)
6813                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6814         else if (update_pause)
6815                 rc = bnxt_hwrm_set_pause(bp);
6816         if (rc) {
6817                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6818                            rc);
6819                 return rc;
6820         }
6821
6822         return rc;
6823 }
6824
6825 /* Common routine to pre-map certain register block to different GRC window.
6826  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6827  * in PF and 3 windows in VF that can be customized to map in different
6828  * register blocks.
6829  */
6830 static void bnxt_preset_reg_win(struct bnxt *bp)
6831 {
6832         if (BNXT_PF(bp)) {
6833                 /* CAG registers map to GRC window #4 */
6834                 writel(BNXT_CAG_REG_BASE,
6835                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6836         }
6837 }
6838
6839 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6840 {
6841         int rc = 0;
6842
6843         bnxt_preset_reg_win(bp);
6844         netif_carrier_off(bp->dev);
6845         if (irq_re_init) {
6846                 rc = bnxt_reserve_rings(bp);
6847                 if (rc)
6848                         return rc;
6849         }
6850         if ((bp->flags & BNXT_FLAG_RFS) &&
6851             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6852                 /* disable RFS if falling back to INTA */
6853                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6854                 bp->flags &= ~BNXT_FLAG_RFS;
6855         }
6856
6857         rc = bnxt_alloc_mem(bp, irq_re_init);
6858         if (rc) {
6859                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6860                 goto open_err_free_mem;
6861         }
6862
6863         if (irq_re_init) {
6864                 bnxt_init_napi(bp);
6865                 rc = bnxt_request_irq(bp);
6866                 if (rc) {
6867                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6868                         goto open_err;
6869                 }
6870         }
6871
6872         bnxt_enable_napi(bp);
6873
6874         rc = bnxt_init_nic(bp, irq_re_init);
6875         if (rc) {
6876                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6877                 goto open_err;
6878         }
6879
6880         if (link_re_init) {
6881                 mutex_lock(&bp->link_lock);
6882                 rc = bnxt_update_phy_setting(bp);
6883                 mutex_unlock(&bp->link_lock);
6884                 if (rc)
6885                         netdev_warn(bp->dev, "failed to update phy settings\n");
6886         }
6887
6888         if (irq_re_init)
6889                 udp_tunnel_get_rx_info(bp->dev);
6890
6891         set_bit(BNXT_STATE_OPEN, &bp->state);
6892         bnxt_enable_int(bp);
6893         /* Enable TX queues */
6894         bnxt_tx_enable(bp);
6895         mod_timer(&bp->timer, jiffies + bp->current_interval);
6896         /* Poll link status and check for SFP+ module status */
6897         bnxt_get_port_module_status(bp);
6898
6899         /* VF-reps may need to be re-opened after the PF is re-opened */
6900         if (BNXT_PF(bp))
6901                 bnxt_vf_reps_open(bp);
6902         return 0;
6903
6904 open_err:
6905         bnxt_disable_napi(bp);
6906         bnxt_del_napi(bp);
6907
6908 open_err_free_mem:
6909         bnxt_free_skbs(bp);
6910         bnxt_free_irq(bp);
6911         bnxt_free_mem(bp, true);
6912         return rc;
6913 }
6914
6915 /* rtnl_lock held */
6916 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6917 {
6918         int rc = 0;
6919
6920         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6921         if (rc) {
6922                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6923                 dev_close(bp->dev);
6924         }
6925         return rc;
6926 }
6927
6928 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6929  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
6930  * self tests.
6931  */
6932 int bnxt_half_open_nic(struct bnxt *bp)
6933 {
6934         int rc = 0;
6935
6936         rc = bnxt_alloc_mem(bp, false);
6937         if (rc) {
6938                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6939                 goto half_open_err;
6940         }
6941         rc = bnxt_init_nic(bp, false);
6942         if (rc) {
6943                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6944                 goto half_open_err;
6945         }
6946         return 0;
6947
6948 half_open_err:
6949         bnxt_free_skbs(bp);
6950         bnxt_free_mem(bp, false);
6951         dev_close(bp->dev);
6952         return rc;
6953 }
6954
6955 /* rtnl_lock held, this call can only be made after a previous successful
6956  * call to bnxt_half_open_nic().
6957  */
6958 void bnxt_half_close_nic(struct bnxt *bp)
6959 {
6960         bnxt_hwrm_resource_free(bp, false, false);
6961         bnxt_free_skbs(bp);
6962         bnxt_free_mem(bp, false);
6963 }
6964
6965 static int bnxt_open(struct net_device *dev)
6966 {
6967         struct bnxt *bp = netdev_priv(dev);
6968
6969         return __bnxt_open_nic(bp, true, true);
6970 }
6971
6972 static bool bnxt_drv_busy(struct bnxt *bp)
6973 {
6974         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
6975                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
6976 }
6977
6978 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
6979                              bool link_re_init)
6980 {
6981         /* Close the VF-reps before closing PF */
6982         if (BNXT_PF(bp))
6983                 bnxt_vf_reps_close(bp);
6984
6985         /* Change device state to avoid TX queue wake up's */
6986         bnxt_tx_disable(bp);
6987
6988         clear_bit(BNXT_STATE_OPEN, &bp->state);
6989         smp_mb__after_atomic();
6990         while (bnxt_drv_busy(bp))
6991                 msleep(20);
6992
6993         /* Flush rings and and disable interrupts */
6994         bnxt_shutdown_nic(bp, irq_re_init);
6995
6996         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6997
6998         bnxt_disable_napi(bp);
6999         del_timer_sync(&bp->timer);
7000         bnxt_free_skbs(bp);
7001
7002         if (irq_re_init) {
7003                 bnxt_free_irq(bp);
7004                 bnxt_del_napi(bp);
7005         }
7006         bnxt_free_mem(bp, irq_re_init);
7007 }
7008
7009 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7010 {
7011         int rc = 0;
7012
7013 #ifdef CONFIG_BNXT_SRIOV
7014         if (bp->sriov_cfg) {
7015                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
7016                                                       !bp->sriov_cfg,
7017                                                       BNXT_SRIOV_CFG_WAIT_TMO);
7018                 if (rc)
7019                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
7020         }
7021 #endif
7022         __bnxt_close_nic(bp, irq_re_init, link_re_init);
7023         return rc;
7024 }
7025
7026 static int bnxt_close(struct net_device *dev)
7027 {
7028         struct bnxt *bp = netdev_priv(dev);
7029
7030         bnxt_close_nic(bp, true, true);
7031         bnxt_hwrm_shutdown_link(bp);
7032         return 0;
7033 }
7034
7035 /* rtnl_lock held */
7036 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7037 {
7038         switch (cmd) {
7039         case SIOCGMIIPHY:
7040                 /* fallthru */
7041         case SIOCGMIIREG: {
7042                 if (!netif_running(dev))
7043                         return -EAGAIN;
7044
7045                 return 0;
7046         }
7047
7048         case SIOCSMIIREG:
7049                 if (!netif_running(dev))
7050                         return -EAGAIN;
7051
7052                 return 0;
7053
7054         default:
7055                 /* do nothing */
7056                 break;
7057         }
7058         return -EOPNOTSUPP;
7059 }
7060
7061 static void
7062 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7063 {
7064         u32 i;
7065         struct bnxt *bp = netdev_priv(dev);
7066
7067         set_bit(BNXT_STATE_READ_STATS, &bp->state);
7068         /* Make sure bnxt_close_nic() sees that we are reading stats before
7069          * we check the BNXT_STATE_OPEN flag.
7070          */
7071         smp_mb__after_atomic();
7072         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7073                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7074                 return;
7075         }
7076
7077         /* TODO check if we need to synchronize with bnxt_close path */
7078         for (i = 0; i < bp->cp_nr_rings; i++) {
7079                 struct bnxt_napi *bnapi = bp->bnapi[i];
7080                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7081                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
7082
7083                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
7084                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
7085                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
7086
7087                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
7088                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
7089                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
7090
7091                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
7092                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
7093                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
7094
7095                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
7096                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
7097                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
7098
7099                 stats->rx_missed_errors +=
7100                         le64_to_cpu(hw_stats->rx_discard_pkts);
7101
7102                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
7103
7104                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
7105         }
7106
7107         if (bp->flags & BNXT_FLAG_PORT_STATS) {
7108                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
7109                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
7110
7111                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
7112                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
7113                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
7114                                           le64_to_cpu(rx->rx_ovrsz_frames) +
7115                                           le64_to_cpu(rx->rx_runt_frames);
7116                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
7117                                    le64_to_cpu(rx->rx_jbr_frames);
7118                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
7119                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
7120                 stats->tx_errors = le64_to_cpu(tx->tx_err);
7121         }
7122         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7123 }
7124
7125 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
7126 {
7127         struct net_device *dev = bp->dev;
7128         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7129         struct netdev_hw_addr *ha;
7130         u8 *haddr;
7131         int mc_count = 0;
7132         bool update = false;
7133         int off = 0;
7134
7135         netdev_for_each_mc_addr(ha, dev) {
7136                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
7137                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7138                         vnic->mc_list_count = 0;
7139                         return false;
7140                 }
7141                 haddr = ha->addr;
7142                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
7143                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
7144                         update = true;
7145                 }
7146                 off += ETH_ALEN;
7147                 mc_count++;
7148         }
7149         if (mc_count)
7150                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
7151
7152         if (mc_count != vnic->mc_list_count) {
7153                 vnic->mc_list_count = mc_count;
7154                 update = true;
7155         }
7156         return update;
7157 }
7158
7159 static bool bnxt_uc_list_updated(struct bnxt *bp)
7160 {
7161         struct net_device *dev = bp->dev;
7162         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7163         struct netdev_hw_addr *ha;
7164         int off = 0;
7165
7166         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
7167                 return true;
7168
7169         netdev_for_each_uc_addr(ha, dev) {
7170                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
7171                         return true;
7172
7173                 off += ETH_ALEN;
7174         }
7175         return false;
7176 }
7177
7178 static void bnxt_set_rx_mode(struct net_device *dev)
7179 {
7180         struct bnxt *bp = netdev_priv(dev);
7181         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7182         u32 mask = vnic->rx_mask;
7183         bool mc_update = false;
7184         bool uc_update;
7185
7186         if (!netif_running(dev))
7187                 return;
7188
7189         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
7190                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
7191                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
7192
7193         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7194                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7195
7196         uc_update = bnxt_uc_list_updated(bp);
7197
7198         if (dev->flags & IFF_ALLMULTI) {
7199                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7200                 vnic->mc_list_count = 0;
7201         } else {
7202                 mc_update = bnxt_mc_list_updated(bp, &mask);
7203         }
7204
7205         if (mask != vnic->rx_mask || uc_update || mc_update) {
7206                 vnic->rx_mask = mask;
7207
7208                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
7209                 bnxt_queue_sp_work(bp);
7210         }
7211 }
7212
7213 static int bnxt_cfg_rx_mode(struct bnxt *bp)
7214 {
7215         struct net_device *dev = bp->dev;
7216         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7217         struct netdev_hw_addr *ha;
7218         int i, off = 0, rc;
7219         bool uc_update;
7220
7221         netif_addr_lock_bh(dev);
7222         uc_update = bnxt_uc_list_updated(bp);
7223         netif_addr_unlock_bh(dev);
7224
7225         if (!uc_update)
7226                 goto skip_uc;
7227
7228         mutex_lock(&bp->hwrm_cmd_lock);
7229         for (i = 1; i < vnic->uc_filter_count; i++) {
7230                 struct hwrm_cfa_l2_filter_free_input req = {0};
7231
7232                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
7233                                        -1);
7234
7235                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
7236
7237                 rc = _hwrm_send_message(bp, &req, sizeof(req),
7238                                         HWRM_CMD_TIMEOUT);
7239         }
7240         mutex_unlock(&bp->hwrm_cmd_lock);
7241
7242         vnic->uc_filter_count = 1;
7243
7244         netif_addr_lock_bh(dev);
7245         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
7246                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7247         } else {
7248                 netdev_for_each_uc_addr(ha, dev) {
7249                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
7250                         off += ETH_ALEN;
7251                         vnic->uc_filter_count++;
7252                 }
7253         }
7254         netif_addr_unlock_bh(dev);
7255
7256         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
7257                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
7258                 if (rc) {
7259                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
7260                                    rc);
7261                         vnic->uc_filter_count = i;
7262                         return rc;
7263                 }
7264         }
7265
7266 skip_uc:
7267         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7268         if (rc)
7269                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
7270                            rc);
7271
7272         return rc;
7273 }
7274
7275 /* If the chip and firmware supports RFS */
7276 static bool bnxt_rfs_supported(struct bnxt *bp)
7277 {
7278         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
7279                 return true;
7280         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7281                 return true;
7282         return false;
7283 }
7284
7285 /* If runtime conditions support RFS */
7286 static bool bnxt_rfs_capable(struct bnxt *bp)
7287 {
7288 #ifdef CONFIG_RFS_ACCEL
7289         int vnics, max_vnics, max_rss_ctxs;
7290
7291         if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
7292                 return false;
7293
7294         vnics = 1 + bp->rx_nr_rings;
7295         max_vnics = bnxt_get_max_func_vnics(bp);
7296         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
7297
7298         /* RSS contexts not a limiting factor */
7299         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7300                 max_rss_ctxs = max_vnics;
7301         if (vnics > max_vnics || vnics > max_rss_ctxs) {
7302                 if (bp->rx_nr_rings > 1)
7303                         netdev_warn(bp->dev,
7304                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
7305                                     min(max_rss_ctxs - 1, max_vnics - 1));
7306                 return false;
7307         }
7308
7309         if (!(bp->flags & BNXT_FLAG_NEW_RM))
7310                 return true;
7311
7312         if (vnics == bp->hw_resc.resv_vnics)
7313                 return true;
7314
7315         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
7316         if (vnics <= bp->hw_resc.resv_vnics)
7317                 return true;
7318
7319         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
7320         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
7321         return false;
7322 #else
7323         return false;
7324 #endif
7325 }
7326
7327 static netdev_features_t bnxt_fix_features(struct net_device *dev,
7328                                            netdev_features_t features)
7329 {
7330         struct bnxt *bp = netdev_priv(dev);
7331
7332         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
7333                 features &= ~NETIF_F_NTUPLE;
7334
7335         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7336                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7337
7338         if (!(features & NETIF_F_GRO))
7339                 features &= ~NETIF_F_GRO_HW;
7340
7341         if (features & NETIF_F_GRO_HW)
7342                 features &= ~NETIF_F_LRO;
7343
7344         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
7345          * turned on or off together.
7346          */
7347         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
7348             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
7349                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
7350                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7351                                       NETIF_F_HW_VLAN_STAG_RX);
7352                 else
7353                         features |= NETIF_F_HW_VLAN_CTAG_RX |
7354                                     NETIF_F_HW_VLAN_STAG_RX;
7355         }
7356 #ifdef CONFIG_BNXT_SRIOV
7357         if (BNXT_VF(bp)) {
7358                 if (bp->vf.vlan) {
7359                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7360                                       NETIF_F_HW_VLAN_STAG_RX);
7361                 }
7362         }
7363 #endif
7364         return features;
7365 }
7366
7367 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
7368 {
7369         struct bnxt *bp = netdev_priv(dev);
7370         u32 flags = bp->flags;
7371         u32 changes;
7372         int rc = 0;
7373         bool re_init = false;
7374         bool update_tpa = false;
7375
7376         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
7377         if (features & NETIF_F_GRO_HW)
7378                 flags |= BNXT_FLAG_GRO;
7379         else if (features & NETIF_F_LRO)
7380                 flags |= BNXT_FLAG_LRO;
7381
7382         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7383                 flags &= ~BNXT_FLAG_TPA;
7384
7385         if (features & NETIF_F_HW_VLAN_CTAG_RX)
7386                 flags |= BNXT_FLAG_STRIP_VLAN;
7387
7388         if (features & NETIF_F_NTUPLE)
7389                 flags |= BNXT_FLAG_RFS;
7390
7391         changes = flags ^ bp->flags;
7392         if (changes & BNXT_FLAG_TPA) {
7393                 update_tpa = true;
7394                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
7395                     (flags & BNXT_FLAG_TPA) == 0)
7396                         re_init = true;
7397         }
7398
7399         if (changes & ~BNXT_FLAG_TPA)
7400                 re_init = true;
7401
7402         if (flags != bp->flags) {
7403                 u32 old_flags = bp->flags;
7404
7405                 bp->flags = flags;
7406
7407                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7408                         if (update_tpa)
7409                                 bnxt_set_ring_params(bp);
7410                         return rc;
7411                 }
7412
7413                 if (re_init) {
7414                         bnxt_close_nic(bp, false, false);
7415                         if (update_tpa)
7416                                 bnxt_set_ring_params(bp);
7417
7418                         return bnxt_open_nic(bp, false, false);
7419                 }
7420                 if (update_tpa) {
7421                         rc = bnxt_set_tpa(bp,
7422                                           (flags & BNXT_FLAG_TPA) ?
7423                                           true : false);
7424                         if (rc)
7425                                 bp->flags = old_flags;
7426                 }
7427         }
7428         return rc;
7429 }
7430
7431 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
7432 {
7433         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
7434         int i = bnapi->index;
7435
7436         if (!txr)
7437                 return;
7438
7439         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
7440                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
7441                     txr->tx_cons);
7442 }
7443
7444 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
7445 {
7446         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
7447         int i = bnapi->index;
7448
7449         if (!rxr)
7450                 return;
7451
7452         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
7453                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
7454                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
7455                     rxr->rx_sw_agg_prod);
7456 }
7457
7458 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
7459 {
7460         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7461         int i = bnapi->index;
7462
7463         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
7464                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
7465 }
7466
7467 static void bnxt_dbg_dump_states(struct bnxt *bp)
7468 {
7469         int i;
7470         struct bnxt_napi *bnapi;
7471
7472         for (i = 0; i < bp->cp_nr_rings; i++) {
7473                 bnapi = bp->bnapi[i];
7474                 if (netif_msg_drv(bp)) {
7475                         bnxt_dump_tx_sw_state(bnapi);
7476                         bnxt_dump_rx_sw_state(bnapi);
7477                         bnxt_dump_cp_sw_state(bnapi);
7478                 }
7479         }
7480 }
7481
7482 static void bnxt_reset_task(struct bnxt *bp, bool silent)
7483 {
7484         if (!silent)
7485                 bnxt_dbg_dump_states(bp);
7486         if (netif_running(bp->dev)) {
7487                 int rc;
7488
7489                 if (!silent)
7490                         bnxt_ulp_stop(bp);
7491                 bnxt_close_nic(bp, false, false);
7492                 rc = bnxt_open_nic(bp, false, false);
7493                 if (!silent && !rc)
7494                         bnxt_ulp_start(bp);
7495         }
7496 }
7497
7498 static void bnxt_tx_timeout(struct net_device *dev)
7499 {
7500         struct bnxt *bp = netdev_priv(dev);
7501
7502         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
7503         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
7504         bnxt_queue_sp_work(bp);
7505 }
7506
7507 #ifdef CONFIG_NET_POLL_CONTROLLER
7508 static void bnxt_poll_controller(struct net_device *dev)
7509 {
7510         struct bnxt *bp = netdev_priv(dev);
7511         int i;
7512
7513         /* Only process tx rings/combined rings in netpoll mode. */
7514         for (i = 0; i < bp->tx_nr_rings; i++) {
7515                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
7516
7517                 napi_schedule(&txr->bnapi->napi);
7518         }
7519 }
7520 #endif
7521
7522 static void bnxt_timer(struct timer_list *t)
7523 {
7524         struct bnxt *bp = from_timer(bp, t, timer);
7525         struct net_device *dev = bp->dev;
7526
7527         if (!netif_running(dev))
7528                 return;
7529
7530         if (atomic_read(&bp->intr_sem) != 0)
7531                 goto bnxt_restart_timer;
7532
7533         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7534             bp->stats_coal_ticks) {
7535                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
7536                 bnxt_queue_sp_work(bp);
7537         }
7538
7539         if (bnxt_tc_flower_enabled(bp)) {
7540                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
7541                 bnxt_queue_sp_work(bp);
7542         }
7543 bnxt_restart_timer:
7544         mod_timer(&bp->timer, jiffies + bp->current_interval);
7545 }
7546
7547 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
7548 {
7549         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7550          * set.  If the device is being closed, bnxt_close() may be holding
7551          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
7552          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7553          */
7554         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7555         rtnl_lock();
7556 }
7557
7558 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7559 {
7560         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7561         rtnl_unlock();
7562 }
7563
7564 /* Only called from bnxt_sp_task() */
7565 static void bnxt_reset(struct bnxt *bp, bool silent)
7566 {
7567         bnxt_rtnl_lock_sp(bp);
7568         if (test_bit(BNXT_STATE_OPEN, &bp->state))
7569                 bnxt_reset_task(bp, silent);
7570         bnxt_rtnl_unlock_sp(bp);
7571 }
7572
7573 static void bnxt_cfg_ntp_filters(struct bnxt *);
7574
7575 static void bnxt_sp_task(struct work_struct *work)
7576 {
7577         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
7578
7579         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7580         smp_mb__after_atomic();
7581         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7582                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7583                 return;
7584         }
7585
7586         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7587                 bnxt_cfg_rx_mode(bp);
7588
7589         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7590                 bnxt_cfg_ntp_filters(bp);
7591         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7592                 bnxt_hwrm_exec_fwd_req(bp);
7593         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7594                 bnxt_hwrm_tunnel_dst_port_alloc(
7595                         bp, bp->vxlan_port,
7596                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7597         }
7598         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7599                 bnxt_hwrm_tunnel_dst_port_free(
7600                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7601         }
7602         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7603                 bnxt_hwrm_tunnel_dst_port_alloc(
7604                         bp, bp->nge_port,
7605                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7606         }
7607         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7608                 bnxt_hwrm_tunnel_dst_port_free(
7609                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7610         }
7611         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
7612                 bnxt_hwrm_port_qstats(bp);
7613                 bnxt_hwrm_port_qstats_ext(bp);
7614         }
7615
7616         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7617                 int rc;
7618
7619                 mutex_lock(&bp->link_lock);
7620                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7621                                        &bp->sp_event))
7622                         bnxt_hwrm_phy_qcaps(bp);
7623
7624                 rc = bnxt_update_link(bp, true);
7625                 mutex_unlock(&bp->link_lock);
7626                 if (rc)
7627                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7628                                    rc);
7629         }
7630         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7631                 mutex_lock(&bp->link_lock);
7632                 bnxt_get_port_module_status(bp);
7633                 mutex_unlock(&bp->link_lock);
7634         }
7635
7636         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7637                 bnxt_tc_flow_stats_work(bp);
7638
7639         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
7640          * must be the last functions to be called before exiting.
7641          */
7642         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7643                 bnxt_reset(bp, false);
7644
7645         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7646                 bnxt_reset(bp, true);
7647
7648         smp_mb__before_atomic();
7649         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7650 }
7651
7652 /* Under rtnl_lock */
7653 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7654                      int tx_xdp)
7655 {
7656         int max_rx, max_tx, tx_sets = 1;
7657         int tx_rings_needed;
7658         int rx_rings = rx;
7659         int cp, vnics, rc;
7660
7661         if (tcs)
7662                 tx_sets = tcs;
7663
7664         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7665         if (rc)
7666                 return rc;
7667
7668         if (max_rx < rx)
7669                 return -ENOMEM;
7670
7671         tx_rings_needed = tx * tx_sets + tx_xdp;
7672         if (max_tx < tx_rings_needed)
7673                 return -ENOMEM;
7674
7675         vnics = 1;
7676         if (bp->flags & BNXT_FLAG_RFS)
7677                 vnics += rx_rings;
7678
7679         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7680                 rx_rings <<= 1;
7681         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
7682         if (bp->flags & BNXT_FLAG_NEW_RM)
7683                 cp += bnxt_get_ulp_msix_num(bp);
7684         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
7685                                      vnics);
7686 }
7687
7688 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7689 {
7690         if (bp->bar2) {
7691                 pci_iounmap(pdev, bp->bar2);
7692                 bp->bar2 = NULL;
7693         }
7694
7695         if (bp->bar1) {
7696                 pci_iounmap(pdev, bp->bar1);
7697                 bp->bar1 = NULL;
7698         }
7699
7700         if (bp->bar0) {
7701                 pci_iounmap(pdev, bp->bar0);
7702                 bp->bar0 = NULL;
7703         }
7704 }
7705
7706 static void bnxt_cleanup_pci(struct bnxt *bp)
7707 {
7708         bnxt_unmap_bars(bp, bp->pdev);
7709         pci_release_regions(bp->pdev);
7710         pci_disable_device(bp->pdev);
7711 }
7712
7713 static void bnxt_init_dflt_coal(struct bnxt *bp)
7714 {
7715         struct bnxt_coal *coal;
7716
7717         /* Tick values in micro seconds.
7718          * 1 coal_buf x bufs_per_record = 1 completion record.
7719          */
7720         coal = &bp->rx_coal;
7721         coal->coal_ticks = 14;
7722         coal->coal_bufs = 30;
7723         coal->coal_ticks_irq = 1;
7724         coal->coal_bufs_irq = 2;
7725         coal->idle_thresh = 50;
7726         coal->bufs_per_record = 2;
7727         coal->budget = 64;              /* NAPI budget */
7728
7729         coal = &bp->tx_coal;
7730         coal->coal_ticks = 28;
7731         coal->coal_bufs = 30;
7732         coal->coal_ticks_irq = 2;
7733         coal->coal_bufs_irq = 2;
7734         coal->bufs_per_record = 1;
7735
7736         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7737 }
7738
7739 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7740 {
7741         int rc;
7742         struct bnxt *bp = netdev_priv(dev);
7743
7744         SET_NETDEV_DEV(dev, &pdev->dev);
7745
7746         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7747         rc = pci_enable_device(pdev);
7748         if (rc) {
7749                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7750                 goto init_err;
7751         }
7752
7753         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7754                 dev_err(&pdev->dev,
7755                         "Cannot find PCI device base address, aborting\n");
7756                 rc = -ENODEV;
7757                 goto init_err_disable;
7758         }
7759
7760         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7761         if (rc) {
7762                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7763                 goto init_err_disable;
7764         }
7765
7766         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7767             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7768                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7769                 goto init_err_disable;
7770         }
7771
7772         pci_set_master(pdev);
7773
7774         bp->dev = dev;
7775         bp->pdev = pdev;
7776
7777         bp->bar0 = pci_ioremap_bar(pdev, 0);
7778         if (!bp->bar0) {
7779                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7780                 rc = -ENOMEM;
7781                 goto init_err_release;
7782         }
7783
7784         bp->bar1 = pci_ioremap_bar(pdev, 2);
7785         if (!bp->bar1) {
7786                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7787                 rc = -ENOMEM;
7788                 goto init_err_release;
7789         }
7790
7791         bp->bar2 = pci_ioremap_bar(pdev, 4);
7792         if (!bp->bar2) {
7793                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7794                 rc = -ENOMEM;
7795                 goto init_err_release;
7796         }
7797
7798         pci_enable_pcie_error_reporting(pdev);
7799
7800         INIT_WORK(&bp->sp_task, bnxt_sp_task);
7801
7802         spin_lock_init(&bp->ntp_fltr_lock);
7803
7804         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7805         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7806
7807         bnxt_init_dflt_coal(bp);
7808
7809         timer_setup(&bp->timer, bnxt_timer, 0);
7810         bp->current_interval = BNXT_TIMER_INTERVAL;
7811
7812         clear_bit(BNXT_STATE_OPEN, &bp->state);
7813         return 0;
7814
7815 init_err_release:
7816         bnxt_unmap_bars(bp, pdev);
7817         pci_release_regions(pdev);
7818
7819 init_err_disable:
7820         pci_disable_device(pdev);
7821
7822 init_err:
7823         return rc;
7824 }
7825
7826 /* rtnl_lock held */
7827 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7828 {
7829         struct sockaddr *addr = p;
7830         struct bnxt *bp = netdev_priv(dev);
7831         int rc = 0;
7832
7833         if (!is_valid_ether_addr(addr->sa_data))
7834                 return -EADDRNOTAVAIL;
7835
7836         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7837                 return 0;
7838
7839         rc = bnxt_approve_mac(bp, addr->sa_data);
7840         if (rc)
7841                 return rc;
7842
7843         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7844         if (netif_running(dev)) {
7845                 bnxt_close_nic(bp, false, false);
7846                 rc = bnxt_open_nic(bp, false, false);
7847         }
7848
7849         return rc;
7850 }
7851
7852 /* rtnl_lock held */
7853 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7854 {
7855         struct bnxt *bp = netdev_priv(dev);
7856
7857         if (netif_running(dev))
7858                 bnxt_close_nic(bp, false, false);
7859
7860         dev->mtu = new_mtu;
7861         bnxt_set_ring_params(bp);
7862
7863         if (netif_running(dev))
7864                 return bnxt_open_nic(bp, false, false);
7865
7866         return 0;
7867 }
7868
7869 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
7870 {
7871         struct bnxt *bp = netdev_priv(dev);
7872         bool sh = false;
7873         int rc;
7874
7875         if (tc > bp->max_tc) {
7876                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
7877                            tc, bp->max_tc);
7878                 return -EINVAL;
7879         }
7880
7881         if (netdev_get_num_tc(dev) == tc)
7882                 return 0;
7883
7884         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7885                 sh = true;
7886
7887         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7888                               sh, tc, bp->tx_nr_rings_xdp);
7889         if (rc)
7890                 return rc;
7891
7892         /* Needs to close the device and do hw resource re-allocations */
7893         if (netif_running(bp->dev))
7894                 bnxt_close_nic(bp, true, false);
7895
7896         if (tc) {
7897                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7898                 netdev_set_num_tc(dev, tc);
7899         } else {
7900                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7901                 netdev_reset_tc(dev);
7902         }
7903         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
7904         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7905                                bp->tx_nr_rings + bp->rx_nr_rings;
7906         bp->num_stat_ctxs = bp->cp_nr_rings;
7907
7908         if (netif_running(bp->dev))
7909                 return bnxt_open_nic(bp, true, false);
7910
7911         return 0;
7912 }
7913
7914 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
7915                                   void *cb_priv)
7916 {
7917         struct bnxt *bp = cb_priv;
7918
7919         if (!bnxt_tc_flower_enabled(bp) ||
7920             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
7921                 return -EOPNOTSUPP;
7922
7923         switch (type) {
7924         case TC_SETUP_CLSFLOWER:
7925                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
7926         default:
7927                 return -EOPNOTSUPP;
7928         }
7929 }
7930
7931 static int bnxt_setup_tc_block(struct net_device *dev,
7932                                struct tc_block_offload *f)
7933 {
7934         struct bnxt *bp = netdev_priv(dev);
7935
7936         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
7937                 return -EOPNOTSUPP;
7938
7939         switch (f->command) {
7940         case TC_BLOCK_BIND:
7941                 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
7942                                              bp, bp);
7943         case TC_BLOCK_UNBIND:
7944                 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
7945                 return 0;
7946         default:
7947                 return -EOPNOTSUPP;
7948         }
7949 }
7950
7951 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
7952                          void *type_data)
7953 {
7954         switch (type) {
7955         case TC_SETUP_BLOCK:
7956                 return bnxt_setup_tc_block(dev, type_data);
7957         case TC_SETUP_QDISC_MQPRIO: {
7958                 struct tc_mqprio_qopt *mqprio = type_data;
7959
7960                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
7961
7962                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
7963         }
7964         default:
7965                 return -EOPNOTSUPP;
7966         }
7967 }
7968
7969 #ifdef CONFIG_RFS_ACCEL
7970 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7971                             struct bnxt_ntuple_filter *f2)
7972 {
7973         struct flow_keys *keys1 = &f1->fkeys;
7974         struct flow_keys *keys2 = &f2->fkeys;
7975
7976         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7977             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7978             keys1->ports.ports == keys2->ports.ports &&
7979             keys1->basic.ip_proto == keys2->basic.ip_proto &&
7980             keys1->basic.n_proto == keys2->basic.n_proto &&
7981             keys1->control.flags == keys2->control.flags &&
7982             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7983             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
7984                 return true;
7985
7986         return false;
7987 }
7988
7989 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7990                               u16 rxq_index, u32 flow_id)
7991 {
7992         struct bnxt *bp = netdev_priv(dev);
7993         struct bnxt_ntuple_filter *fltr, *new_fltr;
7994         struct flow_keys *fkeys;
7995         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
7996         int rc = 0, idx, bit_id, l2_idx = 0;
7997         struct hlist_head *head;
7998
7999         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
8000                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8001                 int off = 0, j;
8002
8003                 netif_addr_lock_bh(dev);
8004                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
8005                         if (ether_addr_equal(eth->h_dest,
8006                                              vnic->uc_list + off)) {
8007                                 l2_idx = j + 1;
8008                                 break;
8009                         }
8010                 }
8011                 netif_addr_unlock_bh(dev);
8012                 if (!l2_idx)
8013                         return -EINVAL;
8014         }
8015         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
8016         if (!new_fltr)
8017                 return -ENOMEM;
8018
8019         fkeys = &new_fltr->fkeys;
8020         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
8021                 rc = -EPROTONOSUPPORT;
8022                 goto err_free;
8023         }
8024
8025         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
8026              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
8027             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
8028              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
8029                 rc = -EPROTONOSUPPORT;
8030                 goto err_free;
8031         }
8032         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
8033             bp->hwrm_spec_code < 0x10601) {
8034                 rc = -EPROTONOSUPPORT;
8035                 goto err_free;
8036         }
8037         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
8038             bp->hwrm_spec_code < 0x10601) {
8039                 rc = -EPROTONOSUPPORT;
8040                 goto err_free;
8041         }
8042
8043         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
8044         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
8045
8046         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
8047         head = &bp->ntp_fltr_hash_tbl[idx];
8048         rcu_read_lock();
8049         hlist_for_each_entry_rcu(fltr, head, hash) {
8050                 if (bnxt_fltr_match(fltr, new_fltr)) {
8051                         rcu_read_unlock();
8052                         rc = 0;
8053                         goto err_free;
8054                 }
8055         }
8056         rcu_read_unlock();
8057
8058         spin_lock_bh(&bp->ntp_fltr_lock);
8059         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
8060                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
8061         if (bit_id < 0) {
8062                 spin_unlock_bh(&bp->ntp_fltr_lock);
8063                 rc = -ENOMEM;
8064                 goto err_free;
8065         }
8066
8067         new_fltr->sw_id = (u16)bit_id;
8068         new_fltr->flow_id = flow_id;
8069         new_fltr->l2_fltr_idx = l2_idx;
8070         new_fltr->rxq = rxq_index;
8071         hlist_add_head_rcu(&new_fltr->hash, head);
8072         bp->ntp_fltr_count++;
8073         spin_unlock_bh(&bp->ntp_fltr_lock);
8074
8075         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
8076         bnxt_queue_sp_work(bp);
8077
8078         return new_fltr->sw_id;
8079
8080 err_free:
8081         kfree(new_fltr);
8082         return rc;
8083 }
8084
8085 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8086 {
8087         int i;
8088
8089         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
8090                 struct hlist_head *head;
8091                 struct hlist_node *tmp;
8092                 struct bnxt_ntuple_filter *fltr;
8093                 int rc;
8094
8095                 head = &bp->ntp_fltr_hash_tbl[i];
8096                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
8097                         bool del = false;
8098
8099                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
8100                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
8101                                                         fltr->flow_id,
8102                                                         fltr->sw_id)) {
8103                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
8104                                                                          fltr);
8105                                         del = true;
8106                                 }
8107                         } else {
8108                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
8109                                                                        fltr);
8110                                 if (rc)
8111                                         del = true;
8112                                 else
8113                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
8114                         }
8115
8116                         if (del) {
8117                                 spin_lock_bh(&bp->ntp_fltr_lock);
8118                                 hlist_del_rcu(&fltr->hash);
8119                                 bp->ntp_fltr_count--;
8120                                 spin_unlock_bh(&bp->ntp_fltr_lock);
8121                                 synchronize_rcu();
8122                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
8123                                 kfree(fltr);
8124                         }
8125                 }
8126         }
8127         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
8128                 netdev_info(bp->dev, "Receive PF driver unload event!");
8129 }
8130
8131 #else
8132
8133 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8134 {
8135 }
8136
8137 #endif /* CONFIG_RFS_ACCEL */
8138
8139 static void bnxt_udp_tunnel_add(struct net_device *dev,
8140                                 struct udp_tunnel_info *ti)
8141 {
8142         struct bnxt *bp = netdev_priv(dev);
8143
8144         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8145                 return;
8146
8147         if (!netif_running(dev))
8148                 return;
8149
8150         switch (ti->type) {
8151         case UDP_TUNNEL_TYPE_VXLAN:
8152                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
8153                         return;
8154
8155                 bp->vxlan_port_cnt++;
8156                 if (bp->vxlan_port_cnt == 1) {
8157                         bp->vxlan_port = ti->port;
8158                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
8159                         bnxt_queue_sp_work(bp);
8160                 }
8161                 break;
8162         case UDP_TUNNEL_TYPE_GENEVE:
8163                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
8164                         return;
8165
8166                 bp->nge_port_cnt++;
8167                 if (bp->nge_port_cnt == 1) {
8168                         bp->nge_port = ti->port;
8169                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
8170                 }
8171                 break;
8172         default:
8173                 return;
8174         }
8175
8176         bnxt_queue_sp_work(bp);
8177 }
8178
8179 static void bnxt_udp_tunnel_del(struct net_device *dev,
8180                                 struct udp_tunnel_info *ti)
8181 {
8182         struct bnxt *bp = netdev_priv(dev);
8183
8184         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8185                 return;
8186
8187         if (!netif_running(dev))
8188                 return;
8189
8190         switch (ti->type) {
8191         case UDP_TUNNEL_TYPE_VXLAN:
8192                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
8193                         return;
8194                 bp->vxlan_port_cnt--;
8195
8196                 if (bp->vxlan_port_cnt != 0)
8197                         return;
8198
8199                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
8200                 break;
8201         case UDP_TUNNEL_TYPE_GENEVE:
8202                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
8203                         return;
8204                 bp->nge_port_cnt--;
8205
8206                 if (bp->nge_port_cnt != 0)
8207                         return;
8208
8209                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
8210                 break;
8211         default:
8212                 return;
8213         }
8214
8215         bnxt_queue_sp_work(bp);
8216 }
8217
8218 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8219                                struct net_device *dev, u32 filter_mask,
8220                                int nlflags)
8221 {
8222         struct bnxt *bp = netdev_priv(dev);
8223
8224         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
8225                                        nlflags, filter_mask, NULL);
8226 }
8227
8228 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
8229                                u16 flags)
8230 {
8231         struct bnxt *bp = netdev_priv(dev);
8232         struct nlattr *attr, *br_spec;
8233         int rem, rc = 0;
8234
8235         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
8236                 return -EOPNOTSUPP;
8237
8238         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8239         if (!br_spec)
8240                 return -EINVAL;
8241
8242         nla_for_each_nested(attr, br_spec, rem) {
8243                 u16 mode;
8244
8245                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8246                         continue;
8247
8248                 if (nla_len(attr) < sizeof(mode))
8249                         return -EINVAL;
8250
8251                 mode = nla_get_u16(attr);
8252                 if (mode == bp->br_mode)
8253                         break;
8254
8255                 rc = bnxt_hwrm_set_br_mode(bp, mode);
8256                 if (!rc)
8257                         bp->br_mode = mode;
8258                 break;
8259         }
8260         return rc;
8261 }
8262
8263 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
8264                                    size_t len)
8265 {
8266         struct bnxt *bp = netdev_priv(dev);
8267         int rc;
8268
8269         /* The PF and it's VF-reps only support the switchdev framework */
8270         if (!BNXT_PF(bp))
8271                 return -EOPNOTSUPP;
8272
8273         rc = snprintf(buf, len, "p%d", bp->pf.port_id);
8274
8275         if (rc >= len)
8276                 return -EOPNOTSUPP;
8277         return 0;
8278 }
8279
8280 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
8281 {
8282         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
8283                 return -EOPNOTSUPP;
8284
8285         /* The PF and it's VF-reps only support the switchdev framework */
8286         if (!BNXT_PF(bp))
8287                 return -EOPNOTSUPP;
8288
8289         switch (attr->id) {
8290         case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
8291                 attr->u.ppid.id_len = sizeof(bp->switch_id);
8292                 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
8293                 break;
8294         default:
8295                 return -EOPNOTSUPP;
8296         }
8297         return 0;
8298 }
8299
8300 static int bnxt_swdev_port_attr_get(struct net_device *dev,
8301                                     struct switchdev_attr *attr)
8302 {
8303         return bnxt_port_attr_get(netdev_priv(dev), attr);
8304 }
8305
8306 static const struct switchdev_ops bnxt_switchdev_ops = {
8307         .switchdev_port_attr_get        = bnxt_swdev_port_attr_get
8308 };
8309
8310 static const struct net_device_ops bnxt_netdev_ops = {
8311         .ndo_open               = bnxt_open,
8312         .ndo_start_xmit         = bnxt_start_xmit,
8313         .ndo_stop               = bnxt_close,
8314         .ndo_get_stats64        = bnxt_get_stats64,
8315         .ndo_set_rx_mode        = bnxt_set_rx_mode,
8316         .ndo_do_ioctl           = bnxt_ioctl,
8317         .ndo_validate_addr      = eth_validate_addr,
8318         .ndo_set_mac_address    = bnxt_change_mac_addr,
8319         .ndo_change_mtu         = bnxt_change_mtu,
8320         .ndo_fix_features       = bnxt_fix_features,
8321         .ndo_set_features       = bnxt_set_features,
8322         .ndo_tx_timeout         = bnxt_tx_timeout,
8323 #ifdef CONFIG_BNXT_SRIOV
8324         .ndo_get_vf_config      = bnxt_get_vf_config,
8325         .ndo_set_vf_mac         = bnxt_set_vf_mac,
8326         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
8327         .ndo_set_vf_rate        = bnxt_set_vf_bw,
8328         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
8329         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
8330         .ndo_set_vf_trust       = bnxt_set_vf_trust,
8331 #endif
8332 #ifdef CONFIG_NET_POLL_CONTROLLER
8333         .ndo_poll_controller    = bnxt_poll_controller,
8334 #endif
8335         .ndo_setup_tc           = bnxt_setup_tc,
8336 #ifdef CONFIG_RFS_ACCEL
8337         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
8338 #endif
8339         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
8340         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
8341         .ndo_bpf                = bnxt_xdp,
8342         .ndo_bridge_getlink     = bnxt_bridge_getlink,
8343         .ndo_bridge_setlink     = bnxt_bridge_setlink,
8344         .ndo_get_phys_port_name = bnxt_get_phys_port_name
8345 };
8346
8347 static void bnxt_remove_one(struct pci_dev *pdev)
8348 {
8349         struct net_device *dev = pci_get_drvdata(pdev);
8350         struct bnxt *bp = netdev_priv(dev);
8351
8352         if (BNXT_PF(bp)) {
8353                 bnxt_sriov_disable(bp);
8354                 bnxt_dl_unregister(bp);
8355         }
8356
8357         pci_disable_pcie_error_reporting(pdev);
8358         unregister_netdev(dev);
8359         bnxt_shutdown_tc(bp);
8360         bnxt_cancel_sp_work(bp);
8361         bp->sp_event = 0;
8362
8363         bnxt_clear_int_mode(bp);
8364         bnxt_hwrm_func_drv_unrgtr(bp);
8365         bnxt_free_hwrm_resources(bp);
8366         bnxt_free_hwrm_short_cmd_req(bp);
8367         bnxt_ethtool_free(bp);
8368         bnxt_dcb_free(bp);
8369         kfree(bp->edev);
8370         bp->edev = NULL;
8371         bnxt_cleanup_pci(bp);
8372         free_netdev(dev);
8373 }
8374
8375 static int bnxt_probe_phy(struct bnxt *bp)
8376 {
8377         int rc = 0;
8378         struct bnxt_link_info *link_info = &bp->link_info;
8379
8380         rc = bnxt_hwrm_phy_qcaps(bp);
8381         if (rc) {
8382                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
8383                            rc);
8384                 return rc;
8385         }
8386         mutex_init(&bp->link_lock);
8387
8388         rc = bnxt_update_link(bp, false);
8389         if (rc) {
8390                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
8391                            rc);
8392                 return rc;
8393         }
8394
8395         /* Older firmware does not have supported_auto_speeds, so assume
8396          * that all supported speeds can be autonegotiated.
8397          */
8398         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
8399                 link_info->support_auto_speeds = link_info->support_speeds;
8400
8401         /*initialize the ethool setting copy with NVM settings */
8402         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
8403                 link_info->autoneg = BNXT_AUTONEG_SPEED;
8404                 if (bp->hwrm_spec_code >= 0x10201) {
8405                         if (link_info->auto_pause_setting &
8406                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
8407                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8408                 } else {
8409                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8410                 }
8411                 link_info->advertising = link_info->auto_link_speeds;
8412         } else {
8413                 link_info->req_link_speed = link_info->force_link_speed;
8414                 link_info->req_duplex = link_info->duplex_setting;
8415         }
8416         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
8417                 link_info->req_flow_ctrl =
8418                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
8419         else
8420                 link_info->req_flow_ctrl = link_info->force_pause_setting;
8421         return rc;
8422 }
8423
8424 static int bnxt_get_max_irq(struct pci_dev *pdev)
8425 {
8426         u16 ctrl;
8427
8428         if (!pdev->msix_cap)
8429                 return 1;
8430
8431         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
8432         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
8433 }
8434
8435 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8436                                 int *max_cp)
8437 {
8438         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8439         int max_ring_grps = 0;
8440
8441         *max_tx = hw_resc->max_tx_rings;
8442         *max_rx = hw_resc->max_rx_rings;
8443         *max_cp = min_t(int, hw_resc->max_irqs, hw_resc->max_cp_rings);
8444         *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs);
8445         max_ring_grps = hw_resc->max_hw_ring_grps;
8446         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
8447                 *max_cp -= 1;
8448                 *max_rx -= 2;
8449         }
8450         if (bp->flags & BNXT_FLAG_AGG_RINGS)
8451                 *max_rx >>= 1;
8452         *max_rx = min_t(int, *max_rx, max_ring_grps);
8453 }
8454
8455 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
8456 {
8457         int rx, tx, cp;
8458
8459         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
8460         if (!rx || !tx || !cp)
8461                 return -ENOMEM;
8462
8463         *max_rx = rx;
8464         *max_tx = tx;
8465         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
8466 }
8467
8468 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8469                                bool shared)
8470 {
8471         int rc;
8472
8473         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8474         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
8475                 /* Not enough rings, try disabling agg rings. */
8476                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
8477                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8478                 if (rc)
8479                         return rc;
8480                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
8481                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8482                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8483                 bnxt_set_ring_params(bp);
8484         }
8485
8486         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
8487                 int max_cp, max_stat, max_irq;
8488
8489                 /* Reserve minimum resources for RoCE */
8490                 max_cp = bnxt_get_max_func_cp_rings(bp);
8491                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
8492                 max_irq = bnxt_get_max_func_irqs(bp);
8493                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
8494                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
8495                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
8496                         return 0;
8497
8498                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
8499                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
8500                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
8501                 max_cp = min_t(int, max_cp, max_irq);
8502                 max_cp = min_t(int, max_cp, max_stat);
8503                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
8504                 if (rc)
8505                         rc = 0;
8506         }
8507         return rc;
8508 }
8509
8510 /* In initial default shared ring setting, each shared ring must have a
8511  * RX/TX ring pair.
8512  */
8513 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
8514 {
8515         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
8516         bp->rx_nr_rings = bp->cp_nr_rings;
8517         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
8518         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8519 }
8520
8521 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
8522 {
8523         int dflt_rings, max_rx_rings, max_tx_rings, rc;
8524
8525         if (sh)
8526                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8527         dflt_rings = netif_get_num_default_rss_queues();
8528         /* Reduce default rings on multi-port cards so that total default
8529          * rings do not exceed CPU count.
8530          */
8531         if (bp->port_count > 1) {
8532                 int max_rings =
8533                         max_t(int, num_online_cpus() / bp->port_count, 1);
8534
8535                 dflt_rings = min_t(int, dflt_rings, max_rings);
8536         }
8537         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
8538         if (rc)
8539                 return rc;
8540         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
8541         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
8542         if (sh)
8543                 bnxt_trim_dflt_sh_rings(bp);
8544         else
8545                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
8546         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8547
8548         rc = __bnxt_reserve_rings(bp);
8549         if (rc)
8550                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
8551         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8552         if (sh)
8553                 bnxt_trim_dflt_sh_rings(bp);
8554
8555         /* Rings may have been trimmed, re-reserve the trimmed rings. */
8556         if (bnxt_need_reserve_rings(bp)) {
8557                 rc = __bnxt_reserve_rings(bp);
8558                 if (rc)
8559                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
8560                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8561         }
8562         bp->num_stat_ctxs = bp->cp_nr_rings;
8563         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8564                 bp->rx_nr_rings++;
8565                 bp->cp_nr_rings++;
8566         }
8567         return rc;
8568 }
8569
8570 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
8571 {
8572         int rc;
8573
8574         ASSERT_RTNL();
8575         bnxt_hwrm_func_qcaps(bp);
8576
8577         if (netif_running(bp->dev))
8578                 __bnxt_close_nic(bp, true, false);
8579
8580         bnxt_ulp_irq_stop(bp);
8581         bnxt_clear_int_mode(bp);
8582         rc = bnxt_init_int_mode(bp);
8583         bnxt_ulp_irq_restart(bp, rc);
8584
8585         if (netif_running(bp->dev)) {
8586                 if (rc)
8587                         dev_close(bp->dev);
8588                 else
8589                         rc = bnxt_open_nic(bp, true, false);
8590         }
8591
8592         return rc;
8593 }
8594
8595 static int bnxt_init_mac_addr(struct bnxt *bp)
8596 {
8597         int rc = 0;
8598
8599         if (BNXT_PF(bp)) {
8600                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8601         } else {
8602 #ifdef CONFIG_BNXT_SRIOV
8603                 struct bnxt_vf_info *vf = &bp->vf;
8604
8605                 if (is_valid_ether_addr(vf->mac_addr)) {
8606                         /* overwrite netdev dev_addr with admin VF MAC */
8607                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8608                 } else {
8609                         eth_hw_addr_random(bp->dev);
8610                         rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
8611                 }
8612 #endif
8613         }
8614         return rc;
8615 }
8616
8617 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
8618 {
8619         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
8620         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
8621
8622         if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) ||
8623             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
8624                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
8625         else
8626                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
8627                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
8628                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
8629                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
8630                             "Unknown", width);
8631 }
8632
8633 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8634 {
8635         static int version_printed;
8636         struct net_device *dev;
8637         struct bnxt *bp;
8638         int rc, max_irqs;
8639
8640         if (pci_is_bridge(pdev))
8641                 return -ENODEV;
8642
8643         if (version_printed++ == 0)
8644                 pr_info("%s", version);
8645
8646         max_irqs = bnxt_get_max_irq(pdev);
8647         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8648         if (!dev)
8649                 return -ENOMEM;
8650
8651         bp = netdev_priv(dev);
8652
8653         if (bnxt_vf_pciid(ent->driver_data))
8654                 bp->flags |= BNXT_FLAG_VF;
8655
8656         if (pdev->msix_cap)
8657                 bp->flags |= BNXT_FLAG_MSIX_CAP;
8658
8659         rc = bnxt_init_board(pdev, dev);
8660         if (rc < 0)
8661                 goto init_err_free;
8662
8663         dev->netdev_ops = &bnxt_netdev_ops;
8664         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8665         dev->ethtool_ops = &bnxt_ethtool_ops;
8666         SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8667         pci_set_drvdata(pdev, dev);
8668
8669         rc = bnxt_alloc_hwrm_resources(bp);
8670         if (rc)
8671                 goto init_err_pci_clean;
8672
8673         mutex_init(&bp->hwrm_cmd_lock);
8674         rc = bnxt_hwrm_ver_get(bp);
8675         if (rc)
8676                 goto init_err_pci_clean;
8677
8678         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
8679                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8680                 if (rc)
8681                         goto init_err_pci_clean;
8682         }
8683
8684         rc = bnxt_hwrm_func_reset(bp);
8685         if (rc)
8686                 goto init_err_pci_clean;
8687
8688         bnxt_hwrm_fw_set_time(bp);
8689
8690         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8691                            NETIF_F_TSO | NETIF_F_TSO6 |
8692                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8693                            NETIF_F_GSO_IPXIP4 |
8694                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8695                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
8696                            NETIF_F_RXCSUM | NETIF_F_GRO;
8697
8698         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8699                 dev->hw_features |= NETIF_F_LRO;
8700
8701         dev->hw_enc_features =
8702                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8703                         NETIF_F_TSO | NETIF_F_TSO6 |
8704                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8705                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8706                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
8707         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8708                                     NETIF_F_GSO_GRE_CSUM;
8709         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8710         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8711                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
8712         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8713                 dev->hw_features |= NETIF_F_GRO_HW;
8714         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
8715         if (dev->features & NETIF_F_GRO_HW)
8716                 dev->features &= ~NETIF_F_LRO;
8717         dev->priv_flags |= IFF_UNICAST_FLT;
8718
8719 #ifdef CONFIG_BNXT_SRIOV
8720         init_waitqueue_head(&bp->sriov_cfg_wait);
8721         mutex_init(&bp->sriov_lock);
8722 #endif
8723         bp->gro_func = bnxt_gro_func_5730x;
8724         if (BNXT_CHIP_P4_PLUS(bp))
8725                 bp->gro_func = bnxt_gro_func_5731x;
8726         else
8727                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
8728
8729         rc = bnxt_hwrm_func_drv_rgtr(bp);
8730         if (rc)
8731                 goto init_err_pci_clean;
8732
8733         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8734         if (rc)
8735                 goto init_err_pci_clean;
8736
8737         bp->ulp_probe = bnxt_ulp_probe;
8738
8739         /* Get the MAX capabilities for this function */
8740         rc = bnxt_hwrm_func_qcaps(bp);
8741         if (rc) {
8742                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8743                            rc);
8744                 rc = -1;
8745                 goto init_err_pci_clean;
8746         }
8747         rc = bnxt_init_mac_addr(bp);
8748         if (rc) {
8749                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
8750                 rc = -EADDRNOTAVAIL;
8751                 goto init_err_pci_clean;
8752         }
8753         rc = bnxt_hwrm_queue_qportcfg(bp);
8754         if (rc) {
8755                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8756                            rc);
8757                 rc = -1;
8758                 goto init_err_pci_clean;
8759         }
8760
8761         bnxt_hwrm_func_qcfg(bp);
8762         bnxt_hwrm_port_led_qcaps(bp);
8763         bnxt_ethtool_init(bp);
8764         bnxt_dcb_init(bp);
8765
8766         /* MTU range: 60 - FW defined max */
8767         dev->min_mtu = ETH_ZLEN;
8768         dev->max_mtu = bp->max_mtu;
8769
8770         rc = bnxt_probe_phy(bp);
8771         if (rc)
8772                 goto init_err_pci_clean;
8773
8774         bnxt_set_rx_skb_mode(bp, false);
8775         bnxt_set_tpa_flags(bp);
8776         bnxt_set_ring_params(bp);
8777         bnxt_set_max_func_irqs(bp, max_irqs);
8778         rc = bnxt_set_dflt_rings(bp, true);
8779         if (rc) {
8780                 netdev_err(bp->dev, "Not enough rings available.\n");
8781                 rc = -ENOMEM;
8782                 goto init_err_pci_clean;
8783         }
8784
8785         /* Default RSS hash cfg. */
8786         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8787                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8788                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8789                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
8790         if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
8791                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8792                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8793                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8794         }
8795
8796         bnxt_hwrm_vnic_qcaps(bp);
8797         if (bnxt_rfs_supported(bp)) {
8798                 dev->hw_features |= NETIF_F_NTUPLE;
8799                 if (bnxt_rfs_capable(bp)) {
8800                         bp->flags |= BNXT_FLAG_RFS;
8801                         dev->features |= NETIF_F_NTUPLE;
8802                 }
8803         }
8804
8805         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
8806                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
8807
8808         rc = bnxt_init_int_mode(bp);
8809         if (rc)
8810                 goto init_err_pci_clean;
8811
8812         /* No TC has been set yet and rings may have been trimmed due to
8813          * limited MSIX, so we re-initialize the TX rings per TC.
8814          */
8815         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8816
8817         bnxt_get_wol_settings(bp);
8818         if (bp->flags & BNXT_FLAG_WOL_CAP)
8819                 device_set_wakeup_enable(&pdev->dev, bp->wol);
8820         else
8821                 device_set_wakeup_capable(&pdev->dev, false);
8822
8823         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
8824
8825         if (BNXT_PF(bp)) {
8826                 if (!bnxt_pf_wq) {
8827                         bnxt_pf_wq =
8828                                 create_singlethread_workqueue("bnxt_pf_wq");
8829                         if (!bnxt_pf_wq) {
8830                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
8831                                 goto init_err_pci_clean;
8832                         }
8833                 }
8834                 bnxt_init_tc(bp);
8835         }
8836
8837         rc = register_netdev(dev);
8838         if (rc)
8839                 goto init_err_cleanup_tc;
8840
8841         if (BNXT_PF(bp))
8842                 bnxt_dl_register(bp);
8843
8844         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
8845                     board_info[ent->driver_data].name,
8846                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
8847
8848         bnxt_parse_log_pcie_link(bp);
8849
8850         return 0;
8851
8852 init_err_cleanup_tc:
8853         bnxt_shutdown_tc(bp);
8854         bnxt_clear_int_mode(bp);
8855
8856 init_err_pci_clean:
8857         bnxt_cleanup_pci(bp);
8858
8859 init_err_free:
8860         free_netdev(dev);
8861         return rc;
8862 }
8863
8864 static void bnxt_shutdown(struct pci_dev *pdev)
8865 {
8866         struct net_device *dev = pci_get_drvdata(pdev);
8867         struct bnxt *bp;
8868
8869         if (!dev)
8870                 return;
8871
8872         rtnl_lock();
8873         bp = netdev_priv(dev);
8874         if (!bp)
8875                 goto shutdown_exit;
8876
8877         if (netif_running(dev))
8878                 dev_close(dev);
8879
8880         bnxt_ulp_shutdown(bp);
8881
8882         if (system_state == SYSTEM_POWER_OFF) {
8883                 bnxt_clear_int_mode(bp);
8884                 pci_wake_from_d3(pdev, bp->wol);
8885                 pci_set_power_state(pdev, PCI_D3hot);
8886         }
8887
8888 shutdown_exit:
8889         rtnl_unlock();
8890 }
8891
8892 #ifdef CONFIG_PM_SLEEP
8893 static int bnxt_suspend(struct device *device)
8894 {
8895         struct pci_dev *pdev = to_pci_dev(device);
8896         struct net_device *dev = pci_get_drvdata(pdev);
8897         struct bnxt *bp = netdev_priv(dev);
8898         int rc = 0;
8899
8900         rtnl_lock();
8901         if (netif_running(dev)) {
8902                 netif_device_detach(dev);
8903                 rc = bnxt_close(dev);
8904         }
8905         bnxt_hwrm_func_drv_unrgtr(bp);
8906         rtnl_unlock();
8907         return rc;
8908 }
8909
8910 static int bnxt_resume(struct device *device)
8911 {
8912         struct pci_dev *pdev = to_pci_dev(device);
8913         struct net_device *dev = pci_get_drvdata(pdev);
8914         struct bnxt *bp = netdev_priv(dev);
8915         int rc = 0;
8916
8917         rtnl_lock();
8918         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
8919                 rc = -ENODEV;
8920                 goto resume_exit;
8921         }
8922         rc = bnxt_hwrm_func_reset(bp);
8923         if (rc) {
8924                 rc = -EBUSY;
8925                 goto resume_exit;
8926         }
8927         bnxt_get_wol_settings(bp);
8928         if (netif_running(dev)) {
8929                 rc = bnxt_open(dev);
8930                 if (!rc)
8931                         netif_device_attach(dev);
8932         }
8933
8934 resume_exit:
8935         rtnl_unlock();
8936         return rc;
8937 }
8938
8939 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
8940 #define BNXT_PM_OPS (&bnxt_pm_ops)
8941
8942 #else
8943
8944 #define BNXT_PM_OPS NULL
8945
8946 #endif /* CONFIG_PM_SLEEP */
8947
8948 /**
8949  * bnxt_io_error_detected - called when PCI error is detected
8950  * @pdev: Pointer to PCI device
8951  * @state: The current pci connection state
8952  *
8953  * This function is called after a PCI bus error affecting
8954  * this device has been detected.
8955  */
8956 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
8957                                                pci_channel_state_t state)
8958 {
8959         struct net_device *netdev = pci_get_drvdata(pdev);
8960         struct bnxt *bp = netdev_priv(netdev);
8961
8962         netdev_info(netdev, "PCI I/O error detected\n");
8963
8964         rtnl_lock();
8965         netif_device_detach(netdev);
8966
8967         bnxt_ulp_stop(bp);
8968
8969         if (state == pci_channel_io_perm_failure) {
8970                 rtnl_unlock();
8971                 return PCI_ERS_RESULT_DISCONNECT;
8972         }
8973
8974         if (netif_running(netdev))
8975                 bnxt_close(netdev);
8976
8977         pci_disable_device(pdev);
8978         rtnl_unlock();
8979
8980         /* Request a slot slot reset. */
8981         return PCI_ERS_RESULT_NEED_RESET;
8982 }
8983
8984 /**
8985  * bnxt_io_slot_reset - called after the pci bus has been reset.
8986  * @pdev: Pointer to PCI device
8987  *
8988  * Restart the card from scratch, as if from a cold-boot.
8989  * At this point, the card has exprienced a hard reset,
8990  * followed by fixups by BIOS, and has its config space
8991  * set up identically to what it was at cold boot.
8992  */
8993 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
8994 {
8995         struct net_device *netdev = pci_get_drvdata(pdev);
8996         struct bnxt *bp = netdev_priv(netdev);
8997         int err = 0;
8998         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8999
9000         netdev_info(bp->dev, "PCI Slot Reset\n");
9001
9002         rtnl_lock();
9003
9004         if (pci_enable_device(pdev)) {
9005                 dev_err(&pdev->dev,
9006                         "Cannot re-enable PCI device after reset.\n");
9007         } else {
9008                 pci_set_master(pdev);
9009
9010                 err = bnxt_hwrm_func_reset(bp);
9011                 if (!err && netif_running(netdev))
9012                         err = bnxt_open(netdev);
9013
9014                 if (!err) {
9015                         result = PCI_ERS_RESULT_RECOVERED;
9016                         bnxt_ulp_start(bp);
9017                 }
9018         }
9019
9020         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
9021                 dev_close(netdev);
9022
9023         rtnl_unlock();
9024
9025         err = pci_cleanup_aer_uncorrect_error_status(pdev);
9026         if (err) {
9027                 dev_err(&pdev->dev,
9028                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9029                          err); /* non-fatal, continue */
9030         }
9031
9032         return PCI_ERS_RESULT_RECOVERED;
9033 }
9034
9035 /**
9036  * bnxt_io_resume - called when traffic can start flowing again.
9037  * @pdev: Pointer to PCI device
9038  *
9039  * This callback is called when the error recovery driver tells
9040  * us that its OK to resume normal operation.
9041  */
9042 static void bnxt_io_resume(struct pci_dev *pdev)
9043 {
9044         struct net_device *netdev = pci_get_drvdata(pdev);
9045
9046         rtnl_lock();
9047
9048         netif_device_attach(netdev);
9049
9050         rtnl_unlock();
9051 }
9052
9053 static const struct pci_error_handlers bnxt_err_handler = {
9054         .error_detected = bnxt_io_error_detected,
9055         .slot_reset     = bnxt_io_slot_reset,
9056         .resume         = bnxt_io_resume
9057 };
9058
9059 static struct pci_driver bnxt_pci_driver = {
9060         .name           = DRV_MODULE_NAME,
9061         .id_table       = bnxt_pci_tbl,
9062         .probe          = bnxt_init_one,
9063         .remove         = bnxt_remove_one,
9064         .shutdown       = bnxt_shutdown,
9065         .driver.pm      = BNXT_PM_OPS,
9066         .err_handler    = &bnxt_err_handler,
9067 #if defined(CONFIG_BNXT_SRIOV)
9068         .sriov_configure = bnxt_sriov_configure,
9069 #endif
9070 };
9071
9072 static int __init bnxt_init(void)
9073 {
9074         return pci_register_driver(&bnxt_pci_driver);
9075 }
9076
9077 static void __exit bnxt_exit(void)
9078 {
9079         pci_unregister_driver(&bnxt_pci_driver);
9080         if (bnxt_pf_wq)
9081                 destroy_workqueue(bnxt_pf_wq);
9082 }
9083
9084 module_init(bnxt_init);
9085 module_exit(bnxt_exit);