1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
14 #define DRV_MODULE_NAME "bnxt_en"
15 #define DRV_MODULE_VERSION "1.10.0"
18 #define DRV_VER_MIN 10
21 #include <linux/interrupt.h>
22 #include <linux/rhashtable.h>
23 #include <linux/crash_dump.h>
24 #include <net/devlink.h>
25 #include <net/dst_metadata.h>
27 #include <linux/dim.h>
32 __le32 tx_bd_len_flags_type;
33 #define TX_BD_TYPE (0x3f << 0)
34 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
35 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
36 #define TX_BD_FLAGS_PACKET_END (1 << 6)
37 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
38 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
39 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
40 #define TX_BD_FLAGS_LHINT (3 << 13)
41 #define TX_BD_FLAGS_LHINT_SHIFT 13
42 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
43 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
44 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
45 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
46 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
47 #define TX_BD_LEN (0xffff << 16)
48 #define TX_BD_LEN_SHIFT 16
55 __le32 tx_bd_hsize_lflags;
56 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
57 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
58 #define TX_BD_FLAGS_NO_CRC (1 << 2)
59 #define TX_BD_FLAGS_STAMP (1 << 3)
60 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
61 #define TX_BD_FLAGS_LSO (1 << 5)
62 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
63 #define TX_BD_FLAGS_T_IPID (1 << 7)
64 #define TX_BD_HSIZE (0xff << 16)
65 #define TX_BD_HSIZE_SHIFT 16
68 __le32 tx_bd_cfa_action;
69 #define TX_BD_CFA_ACTION (0xffff << 16)
70 #define TX_BD_CFA_ACTION_SHIFT 16
72 __le32 tx_bd_cfa_meta;
73 #define TX_BD_CFA_META_MASK 0xfffffff
74 #define TX_BD_CFA_META_VID_MASK 0xfff
75 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
76 #define TX_BD_CFA_META_PRI_SHIFT 12
77 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
78 #define TX_BD_CFA_META_TPID_SHIFT 16
79 #define TX_BD_CFA_META_KEY (0xf << 28)
80 #define TX_BD_CFA_META_KEY_SHIFT 28
81 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
85 __le32 rx_bd_len_flags_type;
86 #define RX_BD_TYPE (0x3f << 0)
87 #define RX_BD_TYPE_RX_PACKET_BD 0x4
88 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
89 #define RX_BD_TYPE_RX_AGG_BD 0x6
90 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
91 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
92 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
93 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
94 #define RX_BD_FLAGS_SOP (1 << 6)
95 #define RX_BD_FLAGS_EOP (1 << 7)
96 #define RX_BD_FLAGS_BUFFERS (3 << 8)
97 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
98 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
99 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
100 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
101 #define RX_BD_LEN (0xffff << 16)
102 #define RX_BD_LEN_SHIFT 16
109 __le32 tx_cmp_flags_type;
110 #define CMP_TYPE (0x3f << 0)
111 #define CMP_TYPE_TX_L2_CMP 0
112 #define CMP_TYPE_RX_L2_CMP 17
113 #define CMP_TYPE_RX_AGG_CMP 18
114 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
115 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
116 #define CMP_TYPE_RX_TPA_AGG_CMP 22
117 #define CMP_TYPE_STATUS_CMP 32
118 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
119 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
120 #define CMP_TYPE_ERROR_STATUS 48
121 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
122 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
123 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
124 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
125 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
127 #define TX_CMP_FLAGS_ERROR (1 << 6)
128 #define TX_CMP_FLAGS_PUSH (1 << 7)
131 __le32 tx_cmp_errors_v;
132 #define TX_CMP_V (1 << 0)
133 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
134 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
135 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
136 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
137 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
138 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
139 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
140 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
141 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
143 __le32 tx_cmp_unsed_3;
147 __le32 rx_cmp_len_flags_type;
148 #define RX_CMP_CMP_TYPE (0x3f << 0)
149 #define RX_CMP_FLAGS_ERROR (1 << 6)
150 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
151 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
152 #define RX_CMP_FLAGS_UNUSED (1 << 11)
153 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
154 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
155 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
156 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
157 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
158 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
159 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
160 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
161 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
162 #define RX_CMP_LEN (0xffff << 16)
163 #define RX_CMP_LEN_SHIFT 16
166 __le32 rx_cmp_misc_v1;
167 #define RX_CMP_V1 (1 << 0)
168 #define RX_CMP_AGG_BUFS (0x1f << 1)
169 #define RX_CMP_AGG_BUFS_SHIFT 1
170 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
171 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
172 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
173 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
175 __le32 rx_cmp_rss_hash;
178 #define RX_CMP_HASH_VALID(rxcmp) \
179 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
181 #define RSS_PROFILE_ID_MASK 0x1f
183 #define RX_CMP_HASH_TYPE(rxcmp) \
184 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
185 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
188 __le32 rx_cmp_flags2;
189 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
190 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
191 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
192 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
193 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
194 __le32 rx_cmp_meta_data;
195 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
196 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
197 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
198 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
199 __le32 rx_cmp_cfa_code_errors_v2;
200 #define RX_CMP_V (1 << 0)
201 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
202 #define RX_CMPL_ERRORS_SFT 1
203 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
204 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
205 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
206 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
207 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
208 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
209 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
210 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
211 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
212 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
213 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
214 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
217 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
218 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
219 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
220 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
221 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
222 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
223 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
224 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
225 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
226 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
227 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
228 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
229 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
230 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
232 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
233 #define RX_CMPL_CFA_CODE_SFT 16
235 __le32 rx_cmp_unused3;
238 #define RX_CMP_L2_ERRORS \
239 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
241 #define RX_CMP_L4_CS_BITS \
242 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
244 #define RX_CMP_L4_CS_ERR_BITS \
245 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
247 #define RX_CMP_L4_CS_OK(rxcmp1) \
248 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
249 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
251 #define RX_CMP_ENCAP(rxcmp1) \
252 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
253 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
255 #define RX_CMP_CFA_CODE(rxcmpl1) \
256 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
257 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
260 __le32 rx_agg_cmp_len_flags_type;
261 #define RX_AGG_CMP_TYPE (0x3f << 0)
262 #define RX_AGG_CMP_LEN (0xffff << 16)
263 #define RX_AGG_CMP_LEN_SHIFT 16
264 u32 rx_agg_cmp_opaque;
266 #define RX_AGG_CMP_V (1 << 0)
267 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
268 #define RX_AGG_CMP_AGG_ID_SHIFT 16
269 __le32 rx_agg_cmp_unused;
272 #define TPA_AGG_AGG_ID(rx_agg) \
273 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
274 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
276 struct rx_tpa_start_cmp {
277 __le32 rx_tpa_start_cmp_len_flags_type;
278 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
279 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
280 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
281 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
282 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
283 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
284 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
285 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
286 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
287 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
288 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
289 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
290 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
291 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
292 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
293 #define RX_TPA_START_CMP_LEN (0xffff << 16)
294 #define RX_TPA_START_CMP_LEN_SHIFT 16
296 u32 rx_tpa_start_cmp_opaque;
297 __le32 rx_tpa_start_cmp_misc_v1;
298 #define RX_TPA_START_CMP_V1 (0x1 << 0)
299 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
300 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
301 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
302 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
303 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
304 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
306 __le32 rx_tpa_start_cmp_rss_hash;
309 #define TPA_START_HASH_VALID(rx_tpa_start) \
310 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
311 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
313 #define TPA_START_HASH_TYPE(rx_tpa_start) \
314 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
315 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
316 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
318 #define TPA_START_AGG_ID(rx_tpa_start) \
319 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
320 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
322 #define TPA_START_AGG_ID_P5(rx_tpa_start) \
323 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
324 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
326 #define TPA_START_ERROR(rx_tpa_start) \
327 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
328 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
330 struct rx_tpa_start_cmp_ext {
331 __le32 rx_tpa_start_cmp_flags2;
332 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
333 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
334 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
335 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
336 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
337 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
338 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
339 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
340 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
341 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
343 __le32 rx_tpa_start_cmp_metadata;
344 __le32 rx_tpa_start_cmp_cfa_code_v2;
345 #define RX_TPA_START_CMP_V2 (0x1 << 0)
346 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
347 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
348 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
349 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
350 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
351 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
352 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
353 __le32 rx_tpa_start_cmp_hdr_info;
356 #define TPA_START_CFA_CODE(rx_tpa_start) \
357 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
358 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
360 #define TPA_START_IS_IPV6(rx_tpa_start) \
361 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
362 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
364 #define TPA_START_ERROR_CODE(rx_tpa_start) \
365 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
366 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
367 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
369 struct rx_tpa_end_cmp {
370 __le32 rx_tpa_end_cmp_len_flags_type;
371 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
372 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
373 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
374 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
375 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
376 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
377 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
378 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
379 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
380 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
381 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
382 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
383 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
384 #define RX_TPA_END_CMP_LEN (0xffff << 16)
385 #define RX_TPA_END_CMP_LEN_SHIFT 16
387 u32 rx_tpa_end_cmp_opaque;
388 __le32 rx_tpa_end_cmp_misc_v1;
389 #define RX_TPA_END_CMP_V1 (0x1 << 0)
390 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
391 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
392 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
393 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
394 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
395 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
396 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
397 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
398 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
399 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
401 __le32 rx_tpa_end_cmp_tsdelta;
402 #define RX_TPA_END_GRO_TS (0x1 << 31)
405 #define TPA_END_AGG_ID(rx_tpa_end) \
406 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
407 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
409 #define TPA_END_AGG_ID_P5(rx_tpa_end) \
410 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
411 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
413 #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
414 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
415 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
417 #define TPA_END_AGG_BUFS(rx_tpa_end) \
418 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
419 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
421 #define TPA_END_TPA_SEGS(rx_tpa_end) \
422 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
423 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
425 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
426 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
427 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
429 #define TPA_END_GRO(rx_tpa_end) \
430 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
431 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
433 #define TPA_END_GRO_TS(rx_tpa_end) \
434 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
435 cpu_to_le32(RX_TPA_END_GRO_TS)))
437 struct rx_tpa_end_cmp_ext {
438 __le32 rx_tpa_end_cmp_dup_acks;
439 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
440 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
441 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
442 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
443 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
445 __le32 rx_tpa_end_cmp_seg_len;
446 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
448 __le32 rx_tpa_end_cmp_errors_v2;
449 #define RX_TPA_END_CMP_V2 (0x1 << 0)
450 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
451 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
452 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
453 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
454 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
455 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
456 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
457 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
459 u32 rx_tpa_end_cmp_start_opaque;
462 #define TPA_END_ERRORS(rx_tpa_end_ext) \
463 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
464 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
466 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
467 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
468 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
469 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
471 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
472 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
473 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
477 #define NQ_CN_TYPE_MASK 0x3fUL
478 #define NQ_CN_TYPE_SFT 0
479 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
480 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
482 __le32 cq_handle_low;
484 #define NQ_CN_V 0x1UL
485 __le32 cq_handle_high;
488 #define DB_IDX_MASK 0xffffff
489 #define DB_IDX_VALID (0x1 << 26)
490 #define DB_IRQ_DIS (0x1 << 27)
491 #define DB_KEY_TX (0x0 << 28)
492 #define DB_KEY_RX (0x1 << 28)
493 #define DB_KEY_CP (0x2 << 28)
494 #define DB_KEY_ST (0x3 << 28)
495 #define DB_KEY_TX_PUSH (0x4 << 28)
496 #define DB_LONG_TX_PUSH (0x2 << 24)
498 #define BNXT_MIN_ROCE_CP_RINGS 2
499 #define BNXT_MIN_ROCE_STAT_CTXS 1
501 /* 64-bit doorbell */
502 #define DBR_INDEX_MASK 0x0000000000ffffffULL
503 #define DBR_XID_MASK 0x000fffff00000000ULL
504 #define DBR_XID_SFT 32
505 #define DBR_PATH_L2 (0x1ULL << 56)
506 #define DBR_TYPE_SQ (0x0ULL << 60)
507 #define DBR_TYPE_RQ (0x1ULL << 60)
508 #define DBR_TYPE_SRQ (0x2ULL << 60)
509 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
510 #define DBR_TYPE_CQ (0x4ULL << 60)
511 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
512 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
513 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
514 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
515 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
516 #define DBR_TYPE_NQ (0xaULL << 60)
517 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
518 #define DBR_TYPE_NULL (0xfULL << 60)
520 #define INVALID_HW_RING_ID ((u16)-1)
522 /* The hardware supports certain page sizes. Use the supported page sizes
523 * to allocate the rings.
525 #if (PAGE_SHIFT < 12)
526 #define BNXT_PAGE_SHIFT 12
527 #elif (PAGE_SHIFT <= 13)
528 #define BNXT_PAGE_SHIFT PAGE_SHIFT
529 #elif (PAGE_SHIFT < 16)
530 #define BNXT_PAGE_SHIFT 13
532 #define BNXT_PAGE_SHIFT 16
535 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
537 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
538 #if (PAGE_SHIFT > 15)
539 #define BNXT_RX_PAGE_SHIFT 15
541 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
544 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
546 #define BNXT_MAX_MTU 9500
547 #define BNXT_MAX_PAGE_MODE_MTU \
548 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
551 #define BNXT_MIN_PKT_SIZE 52
553 #define BNXT_DEFAULT_RX_RING_SIZE 511
554 #define BNXT_DEFAULT_TX_RING_SIZE 511
557 #define MAX_TPA_P5 256
558 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
559 #define MAX_TPA_SEGS_P5 0x3f
561 #if (BNXT_PAGE_SHIFT == 16)
562 #define MAX_RX_PAGES 1
563 #define MAX_RX_AGG_PAGES 4
564 #define MAX_TX_PAGES 1
565 #define MAX_CP_PAGES 8
567 #define MAX_RX_PAGES 8
568 #define MAX_RX_AGG_PAGES 32
569 #define MAX_TX_PAGES 8
570 #define MAX_CP_PAGES 64
573 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
574 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
575 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
577 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
578 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
580 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
582 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
583 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
585 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
587 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
588 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
589 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
591 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
592 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
594 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
595 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
597 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
598 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
600 #define TX_CMP_VALID(txcmp, raw_cons) \
601 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
602 !((raw_cons) & bp->cp_bit))
604 #define RX_CMP_VALID(rxcmp1, raw_cons) \
605 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
606 !((raw_cons) & bp->cp_bit))
608 #define RX_AGG_CMP_VALID(agg, raw_cons) \
609 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
610 !((raw_cons) & bp->cp_bit))
612 #define NQ_CMP_VALID(nqcmp, raw_cons) \
613 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
615 #define TX_CMP_TYPE(txcmp) \
616 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
618 #define RX_CMP_TYPE(rxcmp) \
619 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
621 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
623 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
625 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
627 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
628 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
629 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
630 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
632 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
633 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
634 #define DFLT_HWRM_CMD_TIMEOUT 500
635 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
636 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
637 #define HWRM_RESP_ERR_CODE_MASK 0xffff
638 #define HWRM_RESP_LEN_OFFSET 4
639 #define HWRM_RESP_LEN_MASK 0xffff0000
640 #define HWRM_RESP_LEN_SFT 16
641 #define HWRM_RESP_VALID_MASK 0xff000000
642 #define BNXT_HWRM_REQ_MAX_SIZE 128
643 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
644 BNXT_HWRM_REQ_MAX_SIZE)
645 #define HWRM_SHORT_MIN_TIMEOUT 3
646 #define HWRM_SHORT_MAX_TIMEOUT 10
647 #define HWRM_SHORT_TIMEOUT_COUNTER 5
649 #define HWRM_MIN_TIMEOUT 25
650 #define HWRM_MAX_TIMEOUT 40
652 #define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \
653 ((n) * HWRM_SHORT_MIN_TIMEOUT) : \
654 (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \
655 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
657 #define HWRM_VALID_BIT_DELAY_USEC 150
659 #define BNXT_HWRM_CHNL_CHIMP 0
660 #define BNXT_HWRM_CHNL_KONG 1
662 #define BNXT_RX_EVENT 1
663 #define BNXT_AGG_EVENT 2
664 #define BNXT_TX_EVENT 4
665 #define BNXT_REDIRECT_EVENT 8
667 struct bnxt_sw_tx_bd {
670 struct xdp_frame *xdpf;
672 DEFINE_DMA_UNMAP_ADDR(mapping);
673 DEFINE_DMA_UNMAP_LEN(len);
678 unsigned short nr_frags;
683 struct bnxt_sw_rx_bd {
689 struct bnxt_sw_rx_agg_bd {
695 struct bnxt_ring_mem_info {
699 #define BNXT_RMEM_VALID_PTE_FLAG 1
700 #define BNXT_RMEM_RING_PTE_FLAG 2
701 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
709 dma_addr_t pg_tbl_map;
715 struct bnxt_ring_struct {
716 struct bnxt_ring_mem_info ring_mem;
718 u16 fw_ring_id; /* Ring id filled by Chimp FW */
721 u16 map_idx; /* Used by cmpl rings */
729 __le32 tx_bd_len_flags_type;
731 struct tx_bd_ext txbd2;
734 struct tx_push_buffer {
735 struct tx_push_bd push_bd;
739 struct bnxt_db_info {
740 void __iomem *doorbell;
747 struct bnxt_tx_ring_info {
748 struct bnxt_napi *bnapi;
752 struct bnxt_db_info tx_db;
754 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
755 struct bnxt_sw_tx_bd *tx_buf_ring;
757 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
759 struct tx_push_buffer *tx_push;
760 dma_addr_t tx_push_mapping;
763 #define BNXT_DEV_STATE_CLOSING 0x1
766 struct bnxt_ring_struct tx_ring_struct;
769 #define BNXT_LEGACY_COAL_CMPL_PARAMS \
770 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
771 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
772 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
773 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
774 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
775 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
776 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
777 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
778 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
780 #define BNXT_COAL_CMPL_ENABLES \
781 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
782 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
783 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
784 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
786 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
787 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
789 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
790 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
792 struct bnxt_coal_cap {
795 u16 num_cmpl_dma_aggr_max;
796 u16 num_cmpl_dma_aggr_during_int_max;
797 u16 cmpl_aggr_dma_tmr_max;
798 u16 cmpl_aggr_dma_tmr_during_int_max;
799 u16 int_lat_tmr_min_max;
800 u16 int_lat_tmr_max_max;
801 u16 num_cmpl_aggr_int_max;
810 /* RING_IDLE enabled when coal ticks < idle_thresh */
816 struct bnxt_tpa_info {
821 unsigned short gso_type;
824 enum pkt_hash_types hash_type;
828 #define BNXT_TPA_L4_SIZE(hdr_info) \
829 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
831 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
832 (((hdr_info) >> 18) & 0x1ff)
834 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
835 (((hdr_info) >> 9) & 0x1ff)
837 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
840 u16 cfa_code; /* cfa_code in TPA start compl */
842 struct rx_agg_cmp *agg_arr;
845 #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
847 struct bnxt_tpa_idx_map {
848 u16 agg_id_tbl[1024];
849 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
852 struct bnxt_rx_ring_info {
853 struct bnxt_napi *bnapi;
858 struct bnxt_db_info rx_db;
859 struct bnxt_db_info rx_agg_db;
861 struct bpf_prog *xdp_prog;
863 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
864 struct bnxt_sw_rx_bd *rx_buf_ring;
866 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
867 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
869 unsigned long *rx_agg_bmap;
870 u16 rx_agg_bmap_size;
872 struct page *rx_page;
873 unsigned int rx_page_offset;
875 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
876 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
878 struct bnxt_tpa_info *rx_tpa;
879 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
881 struct bnxt_ring_struct rx_ring_struct;
882 struct bnxt_ring_struct rx_agg_ring_struct;
883 struct xdp_rxq_info xdp_rxq;
884 struct page_pool *page_pool;
887 struct bnxt_cp_ring_info {
888 struct bnxt_napi *bnapi;
890 struct bnxt_db_info cp_db;
895 u32 last_cp_raw_cons;
897 struct bnxt_coal rx_ring_coal;
905 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
906 struct nqe_cn *nq_desc_ring[MAX_CP_PAGES];
909 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
911 struct ctx_hw_stats *hw_stats;
912 dma_addr_t hw_stats_map;
914 u64 rx_l4_csum_errors;
917 struct bnxt_ring_struct cp_ring_struct;
919 struct bnxt_cp_ring_info *cp_ring_arr[2];
920 #define BNXT_RX_HDL 0
921 #define BNXT_TX_HDL 1
925 struct napi_struct napi;
929 struct bnxt_cp_ring_info cp_ring;
930 struct bnxt_rx_ring_info *rx_ring;
931 struct bnxt_tx_ring_info *tx_ring;
933 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
939 #define BNXT_NAPI_FLAG_XDP 0x1
945 irq_handler_t handler;
949 char name[IFNAMSIZ + 2];
950 cpumask_var_t cpu_mask;
953 #define HWRM_RING_ALLOC_TX 0x1
954 #define HWRM_RING_ALLOC_RX 0x2
955 #define HWRM_RING_ALLOC_AGG 0x4
956 #define HWRM_RING_ALLOC_CMPL 0x8
957 #define HWRM_RING_ALLOC_NQ 0x10
959 #define INVALID_STATS_CTX_ID -1
961 struct bnxt_ring_grp_info {
969 struct bnxt_vnic_info {
970 u16 fw_vnic_id; /* returned by Chimp during alloc */
971 #define BNXT_MAX_CTX_PER_VNIC 8
972 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
974 #define BNXT_MAX_UC_ADDRS 4
975 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
976 /* index 0 always dev_addr */
981 dma_addr_t rss_table_dma_addr;
983 dma_addr_t rss_hash_key_dma_addr;
990 dma_addr_t mc_list_mapping;
991 #define BNXT_MAX_MC_ADDRS 16
994 #define BNXT_VNIC_RSS_FLAG 1
995 #define BNXT_VNIC_RFS_FLAG 2
996 #define BNXT_VNIC_MCAST_FLAG 4
997 #define BNXT_VNIC_UCAST_FLAG 8
998 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1001 struct bnxt_hw_resc {
1002 u16 min_rsscos_ctxs;
1003 u16 max_rsscos_ctxs;
1010 u16 max_tx_sch_inputs;
1014 u16 min_hw_ring_grps;
1015 u16 max_hw_ring_grps;
1016 u16 resv_hw_ring_grps;
1030 #if defined(CONFIG_BNXT_SRIOV)
1031 struct bnxt_vf_info {
1033 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1034 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1038 u16 func_qcfg_flags;
1040 #define BNXT_VF_QOS 0x1
1041 #define BNXT_VF_SPOOFCHK 0x2
1042 #define BNXT_VF_LINK_FORCED 0x4
1043 #define BNXT_VF_LINK_UP 0x8
1044 #define BNXT_VF_TRUST 0x10
1045 u32 func_flags; /* func cfg flags */
1048 void *hwrm_cmd_req_addr;
1049 dma_addr_t hwrm_cmd_req_dma_addr;
1053 struct bnxt_pf_info {
1054 #define BNXT_FIRST_PF_FID 1
1055 #define BNXT_FIRST_VF_FID 128
1058 u8 mac_addr[ETH_ALEN];
1062 u32 max_encap_records;
1063 u32 max_decap_records;
1064 u32 max_tx_em_flows;
1065 u32 max_tx_wm_flows;
1066 u32 max_rx_em_flows;
1067 u32 max_rx_wm_flows;
1068 unsigned long *vf_event_bmap;
1069 u16 hwrm_cmd_req_pages;
1070 u8 vf_resv_strategy;
1071 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1072 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1073 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1074 void *hwrm_cmd_req_addr[4];
1075 dma_addr_t hwrm_cmd_req_dma_addr[4];
1076 struct bnxt_vf_info *vf;
1079 struct bnxt_ntuple_filter {
1080 struct hlist_node hash;
1081 u8 dst_mac_addr[ETH_ALEN];
1082 u8 src_mac_addr[ETH_ALEN];
1083 struct flow_keys fkeys;
1089 unsigned long state;
1090 #define BNXT_FLTR_VALID 0
1091 #define BNXT_FLTR_UPDATE 1
1094 struct bnxt_link_info {
1100 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1101 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1102 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1107 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1108 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1110 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1111 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1112 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1113 PORT_PHY_QCFG_RESP_PAUSE_TX)
1115 u8 auto_pause_setting;
1116 u8 force_pause_setting;
1119 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1120 (mode) <= BNXT_LINK_AUTO_MSK)
1121 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1122 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1123 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1124 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1125 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1126 #define PHY_VER_LEN 3
1127 u8 phy_ver[PHY_VER_LEN];
1129 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1130 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1131 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1132 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1133 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1134 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1135 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1136 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1137 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1138 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1140 u16 auto_link_speeds; /* fw adv setting */
1141 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1142 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1143 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1144 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1145 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1146 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1147 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1148 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1149 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1150 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1151 u16 support_auto_speeds;
1152 u16 lp_auto_link_speeds;
1153 u16 force_link_speed;
1157 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1158 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1159 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
1161 /* copy of requested setting from ethtool cmd */
1163 #define BNXT_AUTONEG_SPEED 1
1164 #define BNXT_AUTONEG_FLOW_CTRL 2
1168 u16 advertising; /* user adv setting */
1169 bool force_link_chng;
1172 unsigned long phy_retry_expires;
1174 /* a copy of phy_qcfg output used to report link
1177 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1180 #define BNXT_MAX_QUEUE 8
1182 struct bnxt_queue_info {
1187 #define BNXT_MAX_LED 4
1189 struct bnxt_led_info {
1194 __le16 led_state_caps;
1195 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1196 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1198 __le16 led_color_caps;
1201 #define BNXT_MAX_TEST 8
1203 struct bnxt_test_info {
1206 #define BNXT_TEST_FL_EXT_LPBK 0x1
1208 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1211 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1212 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1213 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1214 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1215 #define BNXT_CAG_REG_BASE 0x300000
1217 #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1218 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1220 struct bnxt_tc_flow_stats {
1225 struct bnxt_tc_info {
1228 /* hash table to store TC offloaded flows */
1229 struct rhashtable flow_table;
1230 struct rhashtable_params flow_ht_params;
1232 /* hash table to store L2 keys of TC flows */
1233 struct rhashtable l2_table;
1234 struct rhashtable_params l2_ht_params;
1235 /* hash table to store L2 keys for TC tunnel decap */
1236 struct rhashtable decap_l2_table;
1237 struct rhashtable_params decap_l2_ht_params;
1238 /* hash table to store tunnel decap entries */
1239 struct rhashtable decap_table;
1240 struct rhashtable_params decap_ht_params;
1241 /* hash table to store tunnel encap entries */
1242 struct rhashtable encap_table;
1243 struct rhashtable_params encap_ht_params;
1245 /* lock to atomically add/del an l2 node when a flow is
1250 /* Fields used for batching stats query */
1251 struct rhashtable_iter iter;
1252 #define BNXT_FLOW_STATS_BATCH_MAX 10
1253 struct bnxt_tc_stats_batch {
1255 struct bnxt_tc_flow_stats hw_stats;
1256 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1258 /* Stat counter mask (width) */
1263 struct bnxt_vf_rep_stats {
1269 struct bnxt_vf_rep {
1271 struct net_device *dev;
1272 struct metadata_dst *dst;
1277 struct bnxt_vf_rep_stats rx_stats;
1278 struct bnxt_vf_rep_stats tx_stats;
1281 #define PTU_PTE_VALID 0x1UL
1282 #define PTU_PTE_LAST 0x2UL
1283 #define PTU_PTE_NEXT_TO_LAST 0x4UL
1285 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1286 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1288 struct bnxt_ctx_pg_info {
1291 void *ctx_pg_arr[MAX_CTX_PAGES];
1292 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1293 struct bnxt_ring_mem_info ring_mem;
1294 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1297 struct bnxt_ctx_mem_info {
1299 u16 qp_min_qp1_entries;
1300 u16 qp_max_l2_entries;
1302 u16 srq_max_l2_entries;
1303 u32 srq_max_entries;
1305 u16 cq_max_l2_entries;
1308 u16 vnic_max_vnic_entries;
1309 u16 vnic_max_ring_table_entries;
1310 u16 vnic_entry_size;
1311 u32 stat_max_entries;
1312 u16 stat_entry_size;
1314 u32 tqm_min_entries_per_ring;
1315 u32 tqm_max_entries_per_ring;
1316 u32 mrav_max_entries;
1317 u16 mrav_entry_size;
1319 u32 tim_max_entries;
1320 u16 mrav_num_entries_units;
1321 u8 tqm_entries_multiple;
1324 #define BNXT_CTX_FLAG_INITED 0x01
1326 struct bnxt_ctx_pg_info qp_mem;
1327 struct bnxt_ctx_pg_info srq_mem;
1328 struct bnxt_ctx_pg_info cq_mem;
1329 struct bnxt_ctx_pg_info vnic_mem;
1330 struct bnxt_ctx_pg_info stat_mem;
1331 struct bnxt_ctx_pg_info mrav_mem;
1332 struct bnxt_ctx_pg_info tim_mem;
1333 struct bnxt_ctx_pg_info *tqm_mem[9];
1343 #define CHIP_NUM_57301 0x16c8
1344 #define CHIP_NUM_57302 0x16c9
1345 #define CHIP_NUM_57304 0x16ca
1346 #define CHIP_NUM_58700 0x16cd
1347 #define CHIP_NUM_57402 0x16d0
1348 #define CHIP_NUM_57404 0x16d1
1349 #define CHIP_NUM_57406 0x16d2
1350 #define CHIP_NUM_57407 0x16d5
1352 #define CHIP_NUM_57311 0x16ce
1353 #define CHIP_NUM_57312 0x16cf
1354 #define CHIP_NUM_57314 0x16df
1355 #define CHIP_NUM_57317 0x16e0
1356 #define CHIP_NUM_57412 0x16d6
1357 #define CHIP_NUM_57414 0x16d7
1358 #define CHIP_NUM_57416 0x16d8
1359 #define CHIP_NUM_57417 0x16d9
1360 #define CHIP_NUM_57412L 0x16da
1361 #define CHIP_NUM_57414L 0x16db
1363 #define CHIP_NUM_5745X 0xd730
1365 #define CHIP_NUM_57508 0x1750
1366 #define CHIP_NUM_57504 0x1751
1367 #define CHIP_NUM_57502 0x1752
1369 #define CHIP_NUM_58802 0xd802
1370 #define CHIP_NUM_58804 0xd804
1371 #define CHIP_NUM_58808 0xd808
1373 #define BNXT_CHIP_NUM_5730X(chip_num) \
1374 ((chip_num) >= CHIP_NUM_57301 && \
1375 (chip_num) <= CHIP_NUM_57304)
1377 #define BNXT_CHIP_NUM_5740X(chip_num) \
1378 (((chip_num) >= CHIP_NUM_57402 && \
1379 (chip_num) <= CHIP_NUM_57406) || \
1380 (chip_num) == CHIP_NUM_57407)
1382 #define BNXT_CHIP_NUM_5731X(chip_num) \
1383 ((chip_num) == CHIP_NUM_57311 || \
1384 (chip_num) == CHIP_NUM_57312 || \
1385 (chip_num) == CHIP_NUM_57314 || \
1386 (chip_num) == CHIP_NUM_57317)
1388 #define BNXT_CHIP_NUM_5741X(chip_num) \
1389 ((chip_num) >= CHIP_NUM_57412 && \
1390 (chip_num) <= CHIP_NUM_57414L)
1392 #define BNXT_CHIP_NUM_58700(chip_num) \
1393 ((chip_num) == CHIP_NUM_58700)
1395 #define BNXT_CHIP_NUM_5745X(chip_num) \
1396 ((chip_num) == CHIP_NUM_5745X)
1398 #define BNXT_CHIP_NUM_57X0X(chip_num) \
1399 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1401 #define BNXT_CHIP_NUM_57X1X(chip_num) \
1402 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1404 #define BNXT_CHIP_NUM_588XX(chip_num) \
1405 ((chip_num) == CHIP_NUM_58802 || \
1406 (chip_num) == CHIP_NUM_58804 || \
1407 (chip_num) == CHIP_NUM_58808)
1409 struct net_device *dev;
1410 struct pci_dev *pdev;
1415 #define BNXT_FLAG_CHIP_P5 0x1
1416 #define BNXT_FLAG_VF 0x2
1417 #define BNXT_FLAG_LRO 0x4
1419 #define BNXT_FLAG_GRO 0x8
1421 /* Cannot support hardware GRO if CONFIG_INET is not set */
1422 #define BNXT_FLAG_GRO 0x0
1424 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1425 #define BNXT_FLAG_JUMBO 0x10
1426 #define BNXT_FLAG_STRIP_VLAN 0x20
1427 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1429 #define BNXT_FLAG_USING_MSIX 0x40
1430 #define BNXT_FLAG_MSIX_CAP 0x80
1431 #define BNXT_FLAG_RFS 0x100
1432 #define BNXT_FLAG_SHARED_RINGS 0x200
1433 #define BNXT_FLAG_PORT_STATS 0x400
1434 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1435 #define BNXT_FLAG_EEE_CAP 0x1000
1436 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1437 #define BNXT_FLAG_WOL_CAP 0x4000
1438 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1439 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1440 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1441 BNXT_FLAG_ROCEV2_CAP)
1442 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1443 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1444 #define BNXT_FLAG_MULTI_HOST 0x100000
1445 #define BNXT_FLAG_DOUBLE_DB 0x400000
1446 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1447 #define BNXT_FLAG_DIM 0x2000000
1448 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1449 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1450 #define BNXT_FLAG_PCIE_STATS 0x40000000
1452 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1454 BNXT_FLAG_STRIP_VLAN)
1456 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1457 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1458 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
1459 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1460 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1461 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1462 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1463 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
1464 (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1465 (bp)->max_tpa_v2) && !is_kdump_kernel())
1467 /* Chip class phase 5 */
1468 #define BNXT_CHIP_P5(bp) \
1469 ((bp)->chip_num == CHIP_NUM_57508 || \
1470 (bp)->chip_num == CHIP_NUM_57504 || \
1471 (bp)->chip_num == CHIP_NUM_57502)
1473 /* Chip class phase 4.x */
1474 #define BNXT_CHIP_P4(bp) \
1475 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1476 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1477 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1478 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1479 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1481 #define BNXT_CHIP_P4_PLUS(bp) \
1482 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1484 struct bnxt_en_dev *edev;
1485 struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
1487 struct bnxt_napi **bnapi;
1489 struct bnxt_rx_ring_info *rx_ring;
1490 struct bnxt_tx_ring_info *tx_ring;
1493 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1496 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1497 struct bnxt_rx_ring_info *,
1498 u16, void *, u8 *, dma_addr_t,
1504 u32 rx_buf_use_size; /* useable size */
1507 enum dma_data_direction rx_dir;
1509 u32 rx_agg_ring_size;
1512 u32 rx_agg_ring_mask;
1514 int rx_agg_nr_pages;
1522 int tx_nr_rings_per_tc;
1523 int tx_nr_rings_xdp;
1535 /* grp_info indexed by completion ring index */
1536 struct bnxt_ring_grp_info *grp_info;
1537 struct bnxt_vnic_info *vnic_info;
1543 u8 max_lltc; /* lossless TCs */
1544 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1545 u8 tc_to_qidx[BNXT_MAX_QUEUE];
1546 u8 q_ids[BNXT_MAX_QUEUE];
1549 unsigned int current_interval;
1550 #define BNXT_TIMER_INTERVAL HZ
1552 struct timer_list timer;
1554 unsigned long state;
1555 #define BNXT_STATE_OPEN 0
1556 #define BNXT_STATE_IN_SP_TASK 1
1557 #define BNXT_STATE_READ_STATS 2
1559 struct bnxt_irq *irq_tbl;
1561 u8 mac_addr[ETH_ALEN];
1563 #ifdef CONFIG_BNXT_DCB
1564 struct ieee_pfc *ieee_pfc;
1565 struct ieee_ets *ieee_ets;
1569 #endif /* CONFIG_BNXT_DCB */
1574 #define BNXT_FW_CAP_SHORT_CMD 0x00000001
1575 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
1576 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
1577 #define BNXT_FW_CAP_NEW_RM 0x00000008
1578 #define BNXT_FW_CAP_IF_CHANGE 0x00000010
1579 #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080
1580 #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400
1581 #define BNXT_FW_CAP_TRUSTED_VF 0x00000800
1582 #define BNXT_FW_CAP_PKG_VER 0x00004000
1583 #define BNXT_FW_CAP_CFA_ADV_FLOW 0x00008000
1584 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX 0x00010000
1585 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000
1586 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000
1588 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1591 u16 hwrm_cmd_kong_seq;
1592 u16 hwrm_intr_seq_id;
1593 void *hwrm_short_cmd_req_addr;
1594 dma_addr_t hwrm_short_cmd_req_dma_addr;
1595 void *hwrm_cmd_resp_addr;
1596 dma_addr_t hwrm_cmd_resp_dma_addr;
1597 void *hwrm_cmd_kong_resp_addr;
1598 dma_addr_t hwrm_cmd_kong_resp_dma_addr;
1600 struct rtnl_link_stats64 net_stats_prev;
1601 struct rx_port_stats *hw_rx_port_stats;
1602 struct tx_port_stats *hw_tx_port_stats;
1603 struct rx_port_stats_ext *hw_rx_port_stats_ext;
1604 struct tx_port_stats_ext *hw_tx_port_stats_ext;
1605 struct pcie_ctx_hw_stats *hw_pcie_stats;
1606 dma_addr_t hw_rx_port_stats_map;
1607 dma_addr_t hw_tx_port_stats_map;
1608 dma_addr_t hw_rx_port_stats_ext_map;
1609 dma_addr_t hw_tx_port_stats_ext_map;
1610 dma_addr_t hw_pcie_stats_map;
1611 int hw_port_stats_size;
1612 u16 fw_rx_stats_ext_size;
1613 u16 fw_tx_stats_ext_size;
1614 u16 hw_ring_stats_size;
1618 u16 hwrm_max_req_len;
1619 u16 hwrm_max_ext_req_len;
1620 int hwrm_cmd_timeout;
1621 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
1622 struct hwrm_ver_get_output ver_resp;
1623 #define FW_VER_STR_LEN 32
1624 #define BC_HWRM_STR_LEN 21
1625 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1626 char fw_ver_str[FW_VER_STR_LEN];
1629 __le16 vxlan_fw_dst_port_id;
1632 __le16 nge_fw_dst_port_id;
1633 u8 port_partition_type;
1637 struct bnxt_coal_cap coal_cap;
1638 struct bnxt_coal rx_coal;
1639 struct bnxt_coal tx_coal;
1641 u32 stats_coal_ticks;
1642 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1643 #define BNXT_MIN_STATS_COAL_TICKS 250000
1644 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1646 struct work_struct sp_task;
1647 unsigned long sp_event;
1648 #define BNXT_RX_MASK_SP_EVENT 0
1649 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1650 #define BNXT_LINK_CHNG_SP_EVENT 2
1651 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1652 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1653 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1654 #define BNXT_RESET_TASK_SP_EVENT 6
1655 #define BNXT_RST_RING_SP_EVENT 7
1656 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1657 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1658 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1659 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1660 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1661 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1662 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1663 #define BNXT_FLOW_STATS_SP_EVENT 15
1664 #define BNXT_UPDATE_PHY_SP_EVENT 16
1665 #define BNXT_RING_COAL_NOW_SP_EVENT 17
1667 struct bnxt_hw_resc hw_resc;
1668 struct bnxt_pf_info pf;
1669 struct bnxt_ctx_mem_info *ctx;
1670 #ifdef CONFIG_BNXT_SRIOV
1672 struct bnxt_vf_info vf;
1673 wait_queue_head_t sriov_cfg_wait;
1675 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1677 /* lock to protect VF-rep creation/cleanup via
1678 * multiple paths such as ->sriov_configure() and
1679 * devlink ->eswitch_mode_set()
1681 struct mutex sriov_lock;
1684 #if BITS_PER_LONG == 32
1685 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1689 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1690 #define BNXT_NTP_FLTR_HASH_SIZE 512
1691 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1692 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1693 spinlock_t ntp_fltr_lock; /* for hash table add, del */
1695 unsigned long *ntp_fltr_bmap;
1698 /* To protect link related settings during link changes and
1699 * ethtool settings changes.
1701 struct mutex link_lock;
1702 struct bnxt_link_info link_info;
1703 struct ethtool_eee eee;
1708 struct bnxt_test_info *test_info;
1714 struct bnxt_led_info leds[BNXT_MAX_LED];
1716 struct bpf_prog *xdp_prog;
1718 /* devlink interface and vf-rep structs */
1720 struct devlink_port dl_port;
1721 enum devlink_eswitch_mode eswitch_mode;
1722 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
1723 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
1725 struct bnxt_tc_info *tc_info;
1726 struct dentry *debugfs_pdev;
1727 struct dentry *debugfs_dim;
1728 struct device *hwmon_dev;
1731 #define BNXT_RX_STATS_OFFSET(counter) \
1732 (offsetof(struct rx_port_stats, counter) / 8)
1734 #define BNXT_TX_STATS_OFFSET(counter) \
1735 ((offsetof(struct tx_port_stats, counter) + \
1736 sizeof(struct rx_port_stats) + 512) / 8)
1738 #define BNXT_RX_STATS_EXT_OFFSET(counter) \
1739 (offsetof(struct rx_port_stats_ext, counter) / 8)
1741 #define BNXT_TX_STATS_EXT_OFFSET(counter) \
1742 (offsetof(struct tx_port_stats_ext, counter) / 8)
1744 #define BNXT_PCIE_STATS_OFFSET(counter) \
1745 (offsetof(struct pcie_ctx_hw_stats, counter) / 8)
1747 #define I2C_DEV_ADDR_A0 0xa0
1748 #define I2C_DEV_ADDR_A2 0xa2
1749 #define SFF_DIAG_SUPPORT_OFFSET 0x5c
1750 #define SFF_MODULE_ID_SFP 0x3
1751 #define SFF_MODULE_ID_QSFP 0xc
1752 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1753 #define SFF_MODULE_ID_QSFP28 0x11
1754 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1756 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1758 /* Tell compiler to fetch tx indices from memory. */
1761 return bp->tx_ring_size -
1762 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1765 #if BITS_PER_LONG == 32
1766 #define writeq(val64, db) \
1768 spin_lock(&bp->db_lock); \
1769 writel((val64) & 0xffffffff, db); \
1770 writel((val64) >> 32, (db) + 4); \
1771 spin_unlock(&bp->db_lock); \
1774 #define writeq_relaxed writeq
1777 /* For TX and RX ring doorbells with no ordering guarantee*/
1778 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
1779 struct bnxt_db_info *db, u32 idx)
1781 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1782 writeq_relaxed(db->db_key64 | idx, db->doorbell);
1784 u32 db_val = db->db_key32 | idx;
1786 writel_relaxed(db_val, db->doorbell);
1787 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1788 writel_relaxed(db_val, db->doorbell);
1792 /* For TX and RX ring doorbells */
1793 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
1796 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1797 writeq(db->db_key64 | idx, db->doorbell);
1799 u32 db_val = db->db_key32 | idx;
1801 writel(db_val, db->doorbell);
1802 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1803 writel(db_val, db->doorbell);
1807 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
1810 case HWRM_CFA_ENCAP_RECORD_ALLOC:
1811 case HWRM_CFA_ENCAP_RECORD_FREE:
1812 case HWRM_CFA_DECAP_FILTER_ALLOC:
1813 case HWRM_CFA_DECAP_FILTER_FREE:
1814 case HWRM_CFA_NTUPLE_FILTER_ALLOC:
1815 case HWRM_CFA_NTUPLE_FILTER_FREE:
1816 case HWRM_CFA_NTUPLE_FILTER_CFG:
1817 case HWRM_CFA_EM_FLOW_ALLOC:
1818 case HWRM_CFA_EM_FLOW_FREE:
1819 case HWRM_CFA_EM_FLOW_CFG:
1820 case HWRM_CFA_FLOW_ALLOC:
1821 case HWRM_CFA_FLOW_FREE:
1822 case HWRM_CFA_FLOW_INFO:
1823 case HWRM_CFA_FLOW_FLUSH:
1824 case HWRM_CFA_FLOW_STATS:
1825 case HWRM_CFA_METER_PROFILE_ALLOC:
1826 case HWRM_CFA_METER_PROFILE_FREE:
1827 case HWRM_CFA_METER_PROFILE_CFG:
1828 case HWRM_CFA_METER_INSTANCE_ALLOC:
1829 case HWRM_CFA_METER_INSTANCE_FREE:
1836 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
1838 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1839 bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
1842 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
1844 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1845 req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
1848 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
1850 if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
1851 return bp->hwrm_cmd_kong_resp_addr;
1853 return bp->hwrm_cmd_resp_addr;
1856 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
1860 if (dst == BNXT_HWRM_CHNL_CHIMP)
1861 seq_id = bp->hwrm_cmd_seq++;
1863 seq_id = bp->hwrm_cmd_kong_seq++;
1867 extern const u16 bnxt_lhint_arr[];
1869 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1870 u16 prod, gfp_t gfp);
1871 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1872 void bnxt_set_tpa_flags(struct bnxt *bp);
1873 void bnxt_set_ring_params(struct bnxt *);
1874 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1875 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1876 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1877 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
1878 int hwrm_send_message(struct bnxt *, void *, u32, int);
1879 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1880 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1882 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1883 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1884 int bnxt_nq_rings_in_use(struct bnxt *bp);
1885 int bnxt_hwrm_set_coal(struct bnxt *);
1886 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1887 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
1888 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1889 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
1890 int bnxt_get_avail_msix(struct bnxt *bp, int num);
1891 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
1892 void bnxt_tx_disable(struct bnxt *bp);
1893 void bnxt_tx_enable(struct bnxt *bp);
1894 int bnxt_hwrm_set_pause(struct bnxt *);
1895 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1896 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1897 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1898 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
1899 int bnxt_hwrm_fw_set_time(struct bnxt *);
1900 int bnxt_open_nic(struct bnxt *, bool, bool);
1901 int bnxt_half_open_nic(struct bnxt *bp);
1902 void bnxt_half_close_nic(struct bnxt *bp);
1903 int bnxt_close_nic(struct bnxt *, bool, bool);
1904 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1906 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1907 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1908 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
1909 int bnxt_get_port_parent_id(struct net_device *dev,
1910 struct netdev_phys_item_id *ppid);
1911 void bnxt_dim_work(struct work_struct *work);
1912 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);